Freescale Semiconductor Microscope Magnifier MC9S12XDP512 User Manual

2.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

2.8.1 Description of Flash Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Chapter 3

4 Kbyte EEPROM Module (S12XEETX4KV2)

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

3.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

3.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

3.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

3.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

3.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

3.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

3.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

3.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

3.4.1 EEPROM Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

3.4.2 EEPROM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

3.4.3 Illegal EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

3.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

3.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

3.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

3.5.3 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

3.6 EEPROM Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

3.6.1 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 175

3.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

3.7.1 EEPROM Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

3.7.2 Reset While EEPROM Command Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

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3.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

3.8.1 Description of EEPROM Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Chapter 4

Port Integration Module (S12XDP512PIMV2)

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

4.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

4.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

4.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

4.2.1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

4.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

4.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

4.4.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

4.4.2 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

4.4.3 Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

4.4.4 Expanded Bus Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

4.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

4.5 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Chapter 5

Clocks and Reset Generator (S12CRGV6)

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

5.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

5.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

5.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

5.2.1 V

and V

— Operating and Ground Voltage Pins . . . . . . . . . . . . . . . . . . . . 274

DDPLL

SSPLL

5.2.2 XFC — External Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

5.2.3 RESET — Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

5.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

5.4.1 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

5.4.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

5.4.3 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

5.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

5.5.1 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

5.5.2 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

5.5.3 Computer Operating Properly Watchdog (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 307

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5.5.4 Power On Reset, Low V o ltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

5.6.1 Real Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

5.6.2 PLL Lock Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

5.6.3 Self Clock Mode Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

Chapter 6

Pierce Oscillator (S12XOSCLCPV1)

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

6.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

6.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

6.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

6.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

6.2.1 V

and V

— Operating and Ground V o ltage Pins . . . . . . . . . . . . . . . . . . . . 312

DDPLL

SSPLL

6.2.2 EX T A L and X T A L — Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

6.2.3 XCLKS — Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

6.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

6.4.1 Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

6.4.2 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

6.4.3 Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

6.4.4 Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

Chapter 7

Analog-to-Digital Converter (ATD10B16CV4)

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

7.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

7.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

7.2.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input Channel x Pins

319

7.2.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0 — External Trigger Pins . . . . . . . . . . . . . . . . . 319

7.2.3 V , V — High Reference V o ltage Pin, Low Reference V o ltage Pin . . . . . . . . . . . . 319

7.2.4 V

, V

— Analog Circuitry Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . 319

DDA

SSA

7.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

7.4.1 Analog Sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

7.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

7.4.3 Operation in Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

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7.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

Chapter 8

Analog-to-Digital Converter (ATD10B8CV3)

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

8.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

8.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

8.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

8.2.1 ANx (x = 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

8.2.2 ETRIG3, ETRIG2, ETRIG1, and ETRIG0 — External Trigger Pins . . . . . . . . . . . . . . 348

8.2.3 V

8.2.4 V

and V

— High and Low Reference V o ltage Pins . . . . . . . . . . . . . . . . . . . . . . . . 348

RH and RL

— Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

DDA

SSA

8.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

8.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

8.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

8.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

8.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

Chapter 9

XGATE (S12XGATEV2)

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

9.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

9.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

9.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

9.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

9.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

9.4.1 XG A T E RISC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

9.4.2 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

9.4.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

9.4.4 Semaphores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

9.4.5 Software Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

9.5.1 Incoming Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

9.5.2 Outgoing Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

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9.6 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

9.6.1 Debug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

9.6.2 Entering Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

9.6.3 Leaving Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

9.7 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

9.8 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

9.8.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

9.8.2 Instruction Summary and Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

9.8.3 Cycle Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

9.8.4 Thread Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

9.8.5 Instruction Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

9.8.6 Instruction Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

9.9 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

9.9.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

9.9.2 Code Example (Transmit "Hello World!" on SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

Chapter 10

Security (S12X9SECV2)

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

10.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

10.1.3 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

10.1.4 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501

10.1.5 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

10.1.6 Reprogramming the Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

10.1.7 Complete Memory Erase (Special Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

Chapter 11

Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

11.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

11.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

11.2.1 IOC7 — Input Capture and Output Compare Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . 509

11.2.2 IOC6 — Input Capture and Output Compare Channel 6 . . . . . . . . . . . . . . . . . . . . . . . . 509

11.2.3 IOC5 — Input Capture and Output Compare Channel 5 . . . . . . . . . . . . . . . . . . . . . . . . 509

11.2.4 IOC4 — Input Capture and Output Compare Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . 509

11.2.5 IOC3 — Input Capture and Output Compare Channel 3 . . . . . . . . . . . . . . . . . . . . . . . . 509

11.2.6 IOC2 — Input Capture and Output Compare Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . 509

11.2.7 IOC1 — Input Capture and Output Compare Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . 509

11.2.8 IOC0 — Input Capture and Output Compare Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . 509

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11.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548

11.4.1 Enhanced Capture Timer Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

11.4.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558

11.4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

Chapter 12

Pulse-Width Modulator (S12PWM8B8CV1)

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

12.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

12.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562

12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562

12.2.1 PWM7 — PWM Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562

12.2.2 PWM6 — PWM Channel 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562

12.2.3 PWM5 — PWM Channel 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

12.2.4 PWM4 — PWM Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

12.2.5 PWM3 — PWM Channel 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

12.2.6 PWM3 — PWM Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

12.2.7 PWM3 — PWM Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

12.2.8 PWM3 — PWM Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

12.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

12.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

12.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582

12.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

Chapter 13

Inter-Integrated Circuit (MC9S12XDP512) Block Description

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

13.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

13.2.1 IIC_SCL — Serial Clock Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

13.2.2 IIC_SDA — Serial Data Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

13.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

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13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

13.4.1 I-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

13.4.2 Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

13.4.3 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

13.4.4 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

13.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

13.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

13.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612

13.7.1 IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612

Chapter 14

Freescale’s Scalable Controller Area Network (S12MSCANV3)

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617

14.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617

14.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618

14.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618

14.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

14.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

14.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

14.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

14.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620

14.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620

14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622

14.3.3 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644

14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653

14.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653

14.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

14.4.3 Identiﬁer Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

14.4.4 Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663

14.4.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664

14.4.6 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664

14.4.7 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

14.4.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

14.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

14.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

14.5.2 Bus-Off Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

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Chapter 15

Serial Communication Interface (S12MC9S12XDP512V5)

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

15.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674

15.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674

15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675

15.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675

15.2.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675

15.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675

15.3.1 Module Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675

15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688

15.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

15.4.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

15.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690

15.4.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

15.4.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692

15.4.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697

15.4.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

15.4.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

15.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

15.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

15.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

15.5.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707

15.5.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

15.5.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

Chapter 16

Serial Peripheral Interface (S12SPIV4)

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711

16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711

16.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711

16.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712

16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

16.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

16.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

16.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

16.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

16.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714

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16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723

16.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724

16.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725

16.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

16.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730

16.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730

16.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732

16.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732

Chapter 17

Voltage Regulator (S12VREG3V3V5)

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

17.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

17.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736

17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737

17.2.1 VDDR — Regulator Power Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737

17.2.2 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 737

17.2.3 VDD, VSS — Regulator Output1 (Core Logic) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 737

17.2.4 VDDPLL, VSSPLL — Regulator Output2 (PLL) Pins . . . . . . . . . . . . . . . . . . . . . . . . . 738

17.2.5 V

Optional Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738

REGEN —

17.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738

17.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738

17.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739

17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744

17.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744

17.4.2 Regulator Core (REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744

17.4.3 Low-V o ltage Detect (L V D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745

17.4.4 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745

17.4.5 Low-V o ltage Reset (L V R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745

17.4.6 Regulator Control (CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745

17.4.7 Autonomous Periodical Interrupt (API) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745

17.4.8 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746

17.4.9 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746

17.4.10Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746

Chapter 18

Periodic Interrupt Timer (S12PIT24B4CV1)

18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749

18.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749

18.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749

18.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750

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18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750

18.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752

18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761

18.4.1 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761

18.4.2 Interrupt Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762

18.4.3 Hardware Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763

18.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763

18.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763

18.5.2 Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763

18.5.3 Flag Clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763

Chapter 19

Background Debug Module (S12XBDMV2)

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765

19.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765

19.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766

19.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768

19.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768

19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768

19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769

19.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773

19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

19.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

19.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

19.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775

19.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776

19.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778

19.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780

19.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782

19.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784

19.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787

19.4.10Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788

19.4.11Serial Communication Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789

Chapter 20

Debug (S12XDBGV2)

20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791

20.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791

20.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792

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20.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792

20.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793

20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793

20.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795

20.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795

20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812

20.4.1 DBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812

20.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813

20.4.3 Trigger Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816

20.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818

20.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819

20.4.6 Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826

20.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827

Chapter 21

Interrupt (S12MC9S12XDP512V1)

21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843

21.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844

21.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844

21.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844

21.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846

21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847

21.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847

21.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848

21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855

21.4.1 S12X Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855

21.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855

21.4.3 XG A T E Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856

21.4.4 Priority Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856

21.4.5 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857

21.4.6 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857

21.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858

21.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858

21.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858

21.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859

Chapter 22

External Bus Interface (S12XEBIV2)

22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861

22.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861

22.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861

22.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862

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22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862

22.3 Memory Map and Register Deﬁnition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864

22.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864

22.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864

22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868

22.4.1 Operating Modes and External Bus Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868

22.4.2 Internal Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869

22.4.3 Accesses to Port Replacement Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872

22.4.4 Stretched External Bus Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872

22.4.5 Data Select and Data Direction Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873

22.4.6 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875

22.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875

22.5.1 Normal Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876

22.5.2 Emulation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877

Chapter 23

Memory Mapping Control (S12XMMCV2)

23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881

23.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881

23.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881

23.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882

23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882

23.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884

23.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884

23.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885

23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898

23.4.1 MCU Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898

23.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899

23.4.3 Chip Access Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908

23.4.4 Chip Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910

23.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911

23.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911

23.5.1 CALL and RTC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911

23.5.2 Port Replacement Registers (PRRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912

23.5.3 On-Chip ROM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914

Appendix A

Electrical Characteristics

A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919

A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919

A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919

A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920

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A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920

A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921

A.1.6 ESD Protection and Latch-up Immunit y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 22

A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923

A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924

A.1.9 I/O Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926

A.1.10Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928

A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932

A.2.1 ATD Operating Characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 32

A.2.2 Factors Influencing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933

A.2.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935

A.3 NVM, Flash, and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938

A.3.1 NVM Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938

A.3.2 NVM Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941

A.4 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943

A.5 Reset, Oscillator, and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944

A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944

A.5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945

A.5.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947

A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950

A.7 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950

A.7.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951

A.7.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952

A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954

A.8.1 Normal Expanded Mode (External Wait Feature Disabled) . . . . . . . . . . . . . . . . . . . . . . . 954

A.8.2 Normal Expanded Mode (External Wait Feature Enabled) . . . . . . . . . . . . . . . . . . . . . . . 956

A.8.3 Emulation Single-Chip Mode (Without Wait States) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959

A.8.4 Emulation Expanded Mode (With Optional Access Stretching) . . . . . . . . . . . . . . . . . . . 961

A.8.5 External Tag Trigger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964

Appendix B

Package Information

B.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965

B.2 144-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966

B.3 112-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967

B.4 80-Pin QFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968

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Appendix C

Recommended PCB Layout

Appendix D

Derivative Differences

D.1 Memory Sizes and Package Options S12XD - Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974

D.2 Memory Sizes and Package Options S12XA - Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976

D.3 MC9S12XD-Family Flash Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977

D.4 Peripheral Sets S12XD - Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978

D.5 Peripheral Sets S12XA - Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979

D.6 Pinout explanations: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980

Appendix E

Ordering Information

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Chapter 1

Device Overview (MC9S12XDP512V2)

1.1

Introduction

The MC9S12XD family will retain the low cost, power consumption, EMC and code-size efﬁciency

advantages currently enjoyed by users of Freescale's existing 16-Bit MC9S12 MCU Family.

Based around an enhanced S12 core, the MC9S12XD-Family will deliver 2 to 5 times the performance of

a 25-MHz S12 whilst retaining a high degree of pin and code compatibility with the S12.

The MC9S12XD-Family introduces the performance boosting XGATE module. Using enhanced DMA

functionality, this parallel processing module ofﬂoads the CPU by providing high-speed data processing

and transfer between peripheral modules, RAM, and I/O ports. Providing up to 80 MIPS of performance

additional to the CPU, the XGATE can access all peripherals and the RAM block.

The MC9S12XDP512 is composed of standard on-chip peripherals including 512 Kbytes of Flash

EEPROM, 32 Kbytes of RAM, 4 Kbytes of EEPROM, six asynchronous serial communications interfaces

(SCI), three serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, an 8-channel,

10-bit analog-to-digital converter, a 16-channel, 10-bit analog-to-digital converter, an 8-channel

pulse-width modulator (PWM), ﬁve CAN 2.0 A, B software compatible modules (MSCAN12), two

inter-IC bus blocks, and a periodic interrupt timer. The MC9S12XDP512 has full 16-bit data paths

throughout. The non-multiplexed expanded bus interface available on the 144-pin versions allows an easy

interface to external memories.

The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit

operational requirements. System power consumption can be further improved with the new “fast exit from

stop mode” feature.

In addition to the I/O ports available in each module, up to 25 further I/O ports are available with interrupt

capability allowing wake-up from stop or wait mode.

The MC9S12XDP512 will be available in 144-pin LQFP with external bus interface and in 112-pin LQFP

or 80-pin QFP package without external bus interface.

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Chapter 1 Device Overview (MC9S12XDP512V2)

1.1.1

Features

•

HCS12X Core

— 16-bit HCS12X CPU

– Upward compatible with MC9S12 instruction set

– Interrupt stacking and programmer’s model identical to MC9S12

– Instruction queue

– Enhanced indexed addressing

– Enhanced instruction set

— EBI (external bus interface)

— MMC (module mapping control)

— INT (interrupt controller)

— DBG (debug module to monitor HCS12X CPU and XGATE bus activity)

— BDM (background debug mode)

XGATE (peripheral coprocessor)

•

— Parallel processing module off loads the CPU by providing high-speed data processing and

transfer

— Data transfer between Flash EEPROM, RAM, peripheral modules, and I/O ports

PIT (periodic interrupt timer)

•

— Four timers with independent time-out periods

— Time-out periods selectable between 1 and 2 bus clock cycles

CRG (clock and reset generator)

— Low noise/low power Pierce oscillator

— PLL

— COP watchdog

— Real time interrupt

— Clock monitor

— Fast wake-up from stop mode

8-bit ports with interrupt functionality

— Digital ﬁltering

— Programmable rising or falling edge trigger

Memory

•

— 512-Kbyte Flash EEPROM

— 4-Kbyte EEPROM

— 32-Kbyte RAM

•

One 8-channel and one 16-channel ADC (analog-to-digital converter)

— 10-bit resolution

— External conversion trigger capability

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Chapter 1 Device Overview (MC9S12XDP512V2)

•

Five 1 M bit per second, CAN 2.0 A, B software compatible modules

— Five receive and three transmit buffers

— Flexible identiﬁer ﬁlter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit

— Four separate interrupt channels for Rx, Tx, error, and wake-up

— Low-pass ﬁlter wake-up function

— Loop-back for self-test operation

•

ECT (enhanced capture timer)

— 16-bit main counter with 7-bit prescaler

— 8 programmable input capture or output compare channels

— Four 8-bit or two 16-bit pulse accumulators

8 PWM (pulse-width modulator) channels

— Programmable period and duty cycle

— 8-bit 8-channel or 16-bit 4-channel

— Separate control for each pulse width and duty cycle

— Center-aligned or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

— Fast emergency shutdown input

— Usable as interrupt inputs

•

Serial interfaces

— Six asynchronous serial communication interfaces (SCI) with additional LIN support and

selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse width

— Three Synchronous Serial Peripheral Interfaces (SPI)

Two IIC (Inter-IC bus) Modules

— Compatible with IIC bus standard

— Multi-master operation

— Software programmable for one of 256 different serial clock frequencies

On-Chip Voltage Regulator

— Two parallel, linear voltage regulators with bandgap reference

— Low-voltage detect (LVD) with low-voltage interrupt (LVI)

— Power-on reset (POR) circuit

— 3.3-V–5.5-V operation

— Low-voltage reset (LVR)

— Ultra low-power wake-up timer

•

144 -pin LQFP, 112-pin LQFP, and 80-pin QFP packages

— I/O lines with 5-V input and drive capability

— Input threshold on external bus interface inputs switchable for 3.3-V or 5-V operation

— 5-V A/D converter inputs

— Operation at 80 MHz equivalent to 40-MHz bus speed

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Chapter 1 Device Overview (MC9S12XDP512V2)

•

Development support

— Single-wire background debug™ mode (BDM)

— Four on-chip hardware breakpoints

1.1.2

Modes of Operation

User modes:

•

Normal and emulation operating modes

— Normal single-chip mode

— Normal expanded mode

— Emulation of single-chip mode

— Emulation of expanded mode

•

Special Operating Modes

— Special single-chip mode with active background debug mode

— Special test mode (Freescale use only)

Low-power modes:

•

System stop modes

— Pseudo stop mode

— Full stop mode

System wait mode

•

1.1.3

Block Diagram

Figure 1-1 shows a block diagram of the MC9S12XDP512 device.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

DDA

512/384/256/128/64-Kbyte Flash

32/20/16/14/10/8/4-Kbyte RAM

4/2/1-Kbyte EEPROM

ATD0

ATD1

AN8

AN9

AN10

AN11

AN12

AN13

AN14

AN15

AN16

AN17

AN18

AN19

AN20

AN21

AN22

AN23

DDA

SSA

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

PAD00

PAD01

PAD02

PAD03

PAD04

PAD05

PAD06

PAD08

PAD09

PAD10

PAD11

PAD12

PAD13

PAD14

PAD15

PAD16

PAD17

PAD18

PAD19

PAD20

PAD21

PAD22

PAD23

PT0

DDR

SSR

Voltage Regulator

REGEN

DD1,2

SS1,2

Single-Wire

Background

Debug Module

PAD07

BKGD

CPU12X

XFC

Enhanced Multilevel

Interrupt Module

DDPLL

Clock

PLL

Periodic Interrupt

COP Watchdog

Clock Monitor

Breakpoints

and Reset

Generation

Module

SSPLL

EXTAL

XGATE

Peripheral Co-Processor

XTAL

RESET

TEST

IOC0

PE0

PE1

PE2

PE3

PE4

PE5

PE6

PE7

PK0

XIRQ

IRQ

R/W/WE

LSTRB/LDS/EROMCTL

ECLK

MODA/RE/TAGLO

MODB/TAGHI

ECLKX2/XCLKS

IQSTAT0

IOC1

IOC2

IOC3

IOC4

IOC5

IOC6

IOC7

RXD

TXD

PT1

PT2

PT3

PT4

PT5

Enhanced Capture

Timer

PT6

PT7

PS0

PS1

PS2

PS3

PS4

PS5

PS6

PS7

PM0

PM1

PM2

PM3

PM4

PM5

PM6

PM7

SCI0

SCI1

ADDR16

PK1

PK2

PK3

PK4

PK5

IQSTAT1

IQSTAT2

ADDR17

ADDR18

ADDR19

ADDR20

ADDR21

RXD

TXD

IQSTAT3

8-Bit PPAGE

MISO

MOSI

SCK

ACC0

ACC1

ACC2

Allows 4-MByte

Program space

SPI0

ADDR22 PK6

EWAIT PK7

ADDR15 PA7

ADDR14 PA6

ADDR13 PA5

ADDR12 PA4

ADDR11 PA3

ADDR10 PA2

ADDR9 PA1

ADDR8 PA0

ADDR7 PB7

ADDR6 PB6

ADDR5 PB5

ADDR4 PB4

ADDR3 PB3

ADDR2 PB2

ADDR1 PB1

ADDR0 PB0

DATA15 PC7

DATA14 PC6

DATA13 PC5

DATA12 PC4

DATA11 PC3

DATA10 PC2

DATA9 PC1

DATA8 PC0

DATA7 PD7

DATA6 PD6

DATA5 PD5

DATA4 PD4

DATA3 PD3

DATA2 PD2

DATA1 PD1

DATA0 PD0

ROMCTL/EWAIT

RXCAN

TXCAN

RXCAN

TXCAN

RXCAN

TXCAN

RXCAN

TXCAN

CAN0

Timer

4-Channel

16-Bit with Prescaler

for Internal Timebases

CAN1

CAN2

RXD

SCI3

CAN3

TXD

RXCAN

TXCAN

Digital Supply 2.5 V

CAN4

DD1,2

RXD

TXD

KWJ0

KWJ1

KWJ2

KWJ4

KWJ5

KWJ6

KWJ7

KWP0

KWP1

KWP2

KWP3

KWP4

KWP5

KWP6

KWP7

KWH0

KWH1

KWH2

KWH3

KWH4

KWH5

KWH6

KWH7

PJ0 CS3

PJ1

PJ2 CS1

PJ4 CS0

PJ5 CS2

PJ6

PJ7

PP0

PP1

PP2

PP3

PP4

PP5

PP6

PP7

PH0

PH1

PH2

PH3

PH4

PH5

PH6

PH7

SCI2

SS1,2

SDA

SCL

SDA

SCL

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

PWM7

MISO

MOSI

SCK

MISO

MOSI

SCK

IIC1

PLL Supply 2.5 V

DDPLL

UDS

IIC0

SSPLL

Analog Supply 3-5 V

VDDA

VSSA

PWM

I/O Supply 3-5 V

DDX1,2

SSX1,2

Voltage Regulator 3-5 V

DDR1,2

SPI1

SSR1,2

RXD

TXD

RXD

TXD

SCI4

SCI5

SPI2

Figure 1-1. MC9S12XD-Family Block Diagram

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

1.1.4

Device Memory Map

Table 1-1shows the device register memory map of the MC9S12XDP512.

Table 1-1. Device Register Memory Map

Size

(Bytes)

Address

Module

0x0000–0x0009

0x000A–0x000B

0x000C–0x000D

0x000E–0x000F

0x0010–0x0017

0x0018–0x0019

0x001A–0x001B

0x001C–0x001F

0x0020–0x002F

0x0030–0x0031

0x0032–0x0033

0x0034–0x003F

0x0040–0x007F

0x0080–0x00AF

0x00B0–0x00B7

0x00B8–0x00BF

0x00C0–0x00C7

0x00C8–0x00CF

0x00D0–0x00D7

0x00D8–0x00DF

0x00E0–0x00E7

0x00E8–0x00EF

0x00F0–0x00F7

0x00F8–0x00FF

0x0100–0x010F

0x0110–0x011B

0x011C–0x011F

0x0120–0x012F

0x0130–0x0137

0x0138–0x013F

0x0140–0x017F

PIM (port integration module)

MMC (memory map control)

PIM (port integration module)

EBI (external bus interface)

MMC (memory map control)

Reserved

Device ID register

PIM (port integration module)

DBG (debug module)

MMC (memory map control)

PIM (port integration module)

CRG (clock and reset generator)

ECT (enhanced capture timer 16-bit 8-channel)s

ATD1 (analog-to-digital converter 10-bit 16-channel)

IIC1 (inter IC bus)

SCI2 (serial communications interface)

SCI3 (serial communications interface)

SCI0 (serial communications interface)

SCI1 (serial communications interface)

SPI0 (serial peripheral interface)

IIC0 (inter IC bus)

Reserved

SPI1 (serial peripheral interface)

SPI2 (serial peripheral interface)

Flash control register

EEPROM control register

MMC (memory map control)

INT (interrupt module)

SCI4 (serial communications interface)

SCI5 (serial communications interface)

CAN0 (scalable CAN)

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

Table 1-1. Device Register Memory Map (continued)

Size

(Bytes)

Address

Module

0x0180–0x01BF

0x01C0–0x01FF

0x0200–0x023F

0x0240–0x027F

0x0280–0x02BF

0x02C0–0x02DF

0x02E0–0x02EF

0x02F0–0x02F7

0x02F8–0x02FF

0x0300–0x0327

0x0328–0x033F

0x0340–0x0367

0x0368–0x037F

0x0380–0x03BF

0x03C0–0x03FF

0x0400–0x07FF

CAN1 (scalable CAN)

CAN2 (scalable CAN)

CAN3 (scalable CAN)

PIM (port integration module)

CAN4 (scalable CAN)

ATD0 (analog-to-digital converter 10 bit 8-channel)

Reserved

Voltage regulator

Reserved

PWM (pulse-width modulator 8 channels)

1024

Reserved

Periodic interrupt timer

Reserved

XGATE

Reserved

NOTE

Reserved register space shown in Table 1-1 is not allocated to any module.

This register space is reserved for future use. Writing to these locations have

no effect. Read access to these locations returns zero.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

1.1.5

Address Mapping

1.1.5.1

Local-to-Global Address Mapping

$00_0000

$00_0800

2K Registers

$0000

2K Registers

$0F_8000

RAM

6*4K paged

$0800

$0F_DFFF

$0F_E000

EEPROM

1K paged

8K RAM

$0C00

$1000

$0F_FFFF

$10_0000

EPAGE

RPAGE

1K EEPROM

RAM

4K paged

$13_F000

EEPROM

3*1K paged

$2000

$4000

$8000

$13_FC00

$14_0000

1K EEPROM

8K RAM

Unpaged Flash

PPAGE

Flash

16K paged

PPAGE = $E0

$78_0000

PPAGES

29 * 16K

$C000

$FFFF

Unpaged Flash

Vectors

PPAGE = $FD

$7F_4000

$7F_8000

Unpaged 16K

or PPAGE $FD

PPAGE = $FE

PPAGE = $FF

Unpaged 16K

or PPAGE $FE

$7F_C000

$7F_FFFF

Unpaged 16K

or PPAGE $FF

Figure 1-2. Local-to-Global Address Mapping S12X_CPU/S12X_BDM

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

Device Global Memory Map

XGATE

Local Memory Map

$00_0000

2K Registers

$00_0800

$00_1000

$0000

2K Registers

$0F_8000

$0800

RAM

$0F_FFFF

$10_0000

FLASH

$7FFF

$8000

RAM

$78_0800

30KB FLASH

$FFFF

$78_7FFF

$78_8000

Not Used by XGATE

$7F_FFFF

Figure 1-3. Local-to-Global Address Mapping XGATE

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

1.1.5.2

Logical Address Map

$0000 2-K Register Space

$07FF

$0000

$0800

$0C00

$0800 4-Kbytes EEPROM

four * 1K pages accessible through $0800–$0BFF

$0FFF

$1000

$2000

32-Kbytes RAM

eight * 4K pages accessible

through $1000–$1FFF

$3FFF

$4000

$8000

$C000

16-K Fixed Flash EEPROM

$7FFF

$8000

16-K Page Window

thirtytwo * 16-K Flash EEPROM Pages

EXT

$BFFF

$BF00

BDM visible on PPAGE = $FF

(If Active)

$BFFF

$C000

16-K Fixed Flash EEPROM

2-K, 4-K, 8-K, or 16-K Protected Boot Sector

$FFFF

$FF00

BDM

(If Active, except for speciﬁc BDM hardware

command, for details refer to BDM BlockGuide)

$FF00

$FFFF

Vectors

$FFFF

Normal

Expanded

Special

Single Chip

Figure 1-4. Memory Map

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

1.1.6

Detailed Register Map

The following tables show the detailed register map of the MC9S12XDP512.

0x0000–0x0009 Port Integration Module (PIM) Map 1 of 5

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0000

PORTA

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA 0

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

0x0008

0x0009

PORTB

DDRA

PB7

DDRA7

DDRB7

PC7

PB6

DDRA6

DDRB6

PC6

PB5

DDRA5

DDRB5

PC5

PB4

DDRA4

DDRB4

PC4

PB3

DDRA3

DDRB3

PC3

PB2

DDRA2

DDRB2

PC2

PB1

DDRA1

DDRB1

PC1

PB0

DDRA0

DDRB0

PC0

DDRB

PORTC

PORTD

DDRC

DDRD

PORTE

DDRE

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

DDRC7

DDRD7

PE7

DDRC6

DDRD6

PE6

DDRC5

DDRD5

PE5

DDRC4

DDRD4

PE4

DDRC3

DDRD3

PE3

DDRC2

DDRD2

PE2

DDRC1

DDRC0

DDRD1

PE1

DDRD0

PE0

DDRE7

DDRE6

DDRE5

DDRE4

DDRE3

DDRE2

0x000A–0x000B Module Mapping Control (S12XMMC) Map 1 of 4

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x000A

MMCCTL0

CS2E

CS1E

CS0E

0x000B

MODE

MODC

MODB

MODA

0x000C–0x000D Port Integration Module (PIM) Map 2 of 5

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x000C

PUCR

PUPKE

BKPUE

PUPEE

PUPDE

PUPCE

PUPBE

PUPAE

0x000D

RDRIV

RDPK

RDPE

RDPD

RDPC

RDPB

RDPA

0x000E–0x000F External Bus Interface (S12XEBI) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x000E

EBICTL0

ITHRS

HDBE

ASIZ4

ASIZ3

ASIZ2

ASIZ1

ASIZ0

0x000F

EBICTL1

EWAITE

EXSTR2

EXSTR1

EXSTR0

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x0010–0x0017 Module Mapping Control (S12XMMC) Map 2 of 4

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0010

GPAGE

GP6

GP5

GP4

GP3

GP2

GP1

GP0

0x0011

0x0012

0x0013

0x0014

0x0015

0x0016

0x0017

DIRECT

Reserved

MMCCTL1

Reserved

RPAGE

DP15

DP14

DP13

DP12

DP11

DP10

DP9

DP8

EROMON ROMHM

ROMON

RP7

EP7

RP6

EP6

RP5

EP5

RP4

EP4

RP3

EP3

RP2

EP2

RP1

EP1

RP0

EP0

EPAGE

0x0018–0x001B Miscellaneous Peripheral

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0018

Reserved

0x0019

0x001A

0x001B

Reserved

PARTIDH

PARTIDL

0x001C–0x001F Port Integration Module (PIM) Map 3 of 5

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x001C

ECLKCTL

NECLK

NCLKX2

EDIV1

EDIV0

0x001D

0x001E

0x001F

Reserved

IRQCR

IRQE

IRQEN

Reserved

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x0020–0x0027 Debug Module (S12XDBG) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0020

DBGC1

ARM

TBF

XGSBPE

BDM

DBGBRK

COMRV

TRIG

EXTF

SSF2

SSF1

SSF0

0x0021

0x0022

0x0023

0x0024

0x0025

0x0026

0x0027

DBGSR

DBGTCR

DBGC2

TSOURCE

TRANGE

TRCMOD

CDCM

TALIGN

ABCM

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

DBGTBH

DBGTBL

DBGCNT

DBGSCRX

CNT

SC3

SC2

RWE

SC1

SRC

SC0

DBGXCTL

(COMPA/C)

0x0028

NDB

Bit 22

TAG

BRK

COMPE

Bit 16

Bit 8

DBGXCTL

(COMPB/D)

0x0028

SZE

0x0029

0x002A

0x002B

0x002C

0x002D

0x002E

0x002F

DBGXAH

DBGXAM

DBGXAL

Bit 15

Bit 7

Bit 0

DBGXDH

DBGXDL

DBGXDHM

DBGXDLM

Bit 15

Bit 7

Bit 8

Bit 0

Bit 15

Bit 7

Bit 8

Bit 0

This represents the contents if the Comparator A or C control register is blended into this address

This represents the contents if the Comparator B or D control register is blended into this address

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x0030–0x0031 Module Mapping Control (S12XMMC) Map 3 of 4

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0030

PPAGE

PIX7

PIX6

PIX5

PIX4

PIX3

PIX2

PIX1

PIX0

0x0031

Reserved

0x0032–0x0033 Port Integration Module (PIM) Map 4 of 5

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0032

PORTK

PK7

PK6

PK5

PK4

PK3

PK2

PK1

PK0

0x0033

DDRK

DDRK7

DDRK6

DDRK5

DDRK4

DDRK3

DDRK2

DDRK1

DDRK0

0x0034–0x003F Clock and Reset Generator (CRG) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0034

SYNR

SYN5

SYN4

SYN3

SYN2

SYN1

SYN0

0x0035

0x0036

0x0037

0x0038

0x0039

0x003A

0x003B

0x003C

0x003D

0x003E

0x003F

REFDV

CTFLG

REFDV5

REFDV4

REFDV3

REFDV2

REFDV1

REFDV0

Reserved For Factory Test

LOCK

TRACK

SCM

CRGFLG

CRGINT

CLKSEL

PLLCTL

RTICTL

COPCTL

FORBYP

CTCTL

RTIF

RTIE

PORF

ILAF

LVRF

LOCKIF

SCMIF

SCMIE

RTIWAI

PCE

LOCKIE

PLLSEL

CME

PSTP

PLLON

RTR6

PLLWAI

COPWAI

SCME

RTR0

AUTO

ACQ

FSTWKP

PRE

RTDEC

RTR5

RTR4

RTR3

RTR2

RTR1

WCOP

RSBCK

CR2

CR1

CR0

Reserved For Factory Test

ARMCOP

Bit 7

Bit 0

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 1 of 3)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0040

TIOS

IOS7

IOS6

IOS5

IOS4

IOS3

IOS2

IOS1

IOS0

0x0041

0x0042

0x0043

0x0044

0x0045

0x0046

0x0047

0x0048

0x0049

0x004A

0x004B

0x004C

0x004D

0x004E

0x004F

0x0050

0x0051

0x0052

0x0053

0x0054

0x0055

CFORC

OC7M

FOC7

FOC6

FOC5

FOC4

FOC3

FOC2

FOC1

FOC0

OC7M7

OC7M6

OC7M5

OC7M4

OC7M3

OC7M2

OC7M1

OC7M0

OC7D

OC7D7

Bit 15

OC7D6

OC7D5

OC7D4

OC7D3

OC7D2

OC7D1

OC7D0

Bit 8

TCNT (hi)

TCNT (lo)

TSCR1

TTOV

Bit 7

Bit 0

TEN

TOV7

OM7

OM3

EDG7B

EDG3B

C7I

TSWAI

TOV6

OL7

TSFRZ

TOV5

TFFCA

TOV4

OL6

PRNT

TOV3

OM5

TOV2

OL5

TOV1

OM4

TOV0

OL4

TCTL1

TCTL2

TCTL3

TCTL4

TIE

OM6

OL3

OM2

OL2

OM1

OL1

OM0

OL0

EDG7A

EDG3A

EDG6B

EDG2B

EDG6A

EDG2A

EDG5B

EDG1B

C3I

EDG5A

EDG1A

C2I

EDG4B

EDG0B

C1I

EDG4A

EDG0A

C0I

C6I

C5I

C4I

TSCR2

TFLG1

TFLG2

TC0 (hi)

TC0 (lo)

TC1 (hi)

TC1 (lo)

TC2 (hi)

TC2 (lo)

TOI

TCRE

PR2

PR1

PR0

C7F

C6F

C5F

C4F

C3F

C2F

C1F

C0F

TOF

Bit 15

Bit 7

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 15

Bit 7

Bit 15

Bit 7

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 2 of 3)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0056

TC3 (hi)

Bit 15

Bit 8

0x0057

0x0058

0x0059

0x005A

0x005B

0x005C

0x005D

0x005E

0x005F

0x0060

0x0061

0x0062

0x0063

0x0064

0x0065

0x0066

0x0067

0x0068

0x0069

0x006A

0x006B

0x006C

TC3 (lo)

TC4 (hi)

TC4 (lo)

TC5 (hi)

TC5 (lo)

TC6 (hi)

TC6 (lo)

TC7 (hi)

TC7 (lo)

PACTL

Bit 7

Bit 15

Bit 7

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

PAI

Bit 15

Bit 7

Bit 15

Bit 7

Bit 15

Bit 7

PAEN

PAMOD

PEDGE

CLK1

CLK0

PAOVI

PAFLG

PAOVF

PAIF

Bit 0

PACN3 (hi)

PACN2 (lo)

PACN1 (hi)

PACN0 (lo)

MCCTL

MCFLG

ICPAR

Bit 7

MCZI

ICLAT

MODMC

RDMCL

MCEN

POLF2

MCPR1

POLF1

MCPR0

POLF0

FLMC

POLF3

MCZF

PA3EN

DLY3

PA2EN

DLY2

PA1EN

DLY1

PA0EN

DLY0

DLYCT

DLY7

DLY6

DLY5

DLY4

ICOVW

NOVW7

NOVW6

NOVW5

NOVW4

NOVW3

NOVW2

NOVW1

NOVW0

ICSYS

SH37

SH26

SH15

SH04

TFMOD

PACMX

BUFEN

LATQ

Reserved

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 3 of 3)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x006D

TIMTST

Reserved For Factory Test

0x006E

0x006F

0x0070

0x0071

0x0072

0x0073

0x0074

0x0075

0x0076

0x0077

0x0078

0x0079

0x007A

0x007B

0x007C

0x007D

0x007E

0x007F

PTPSR

PTMCPSR

PBCTL

PTPS7

PTPS6

PTPS5

PTPS4 PTPS3

PTPS2

PTPS1

PTPS0

PTMPS7 PTMPS6 PTMPS5 PTMPS4 PTMPS3 PTMPS2 PTMPS1 PTMPS0

PBEN

PBOVI

PBFLG

PBOVF

PA3H1

PA3H7

PA2H7

PA1H7

PA0H7

PA3H6

PA2H6

PA1H6

PA0H6

PA3H5

PA2H5

PA1H5

PA0H5

PA3H4

PA2H4

PA1H4

PA0H4

PA3H3

PA2H3

PA1H3

PA0H3

PA3H2

PA2H2

PA1H2

PA0H2

PA3H0

PA2H0

PA1H 0

PA0H0

PA3H

PA2H1

PA1H1

PA0H1

PA2H

PA1H

PA0H

MCCNT (hi)

MCCNT (lo)

TC0H (hi)

TC0H (lo)

TC1H (hi)

TC1H (lo)

TC2H (hi)

TC2H (lo)

TC3H (hi)

TC3H (lo)

Bit 15

Bit 8

Bit 7

Bit 0

Bit 8

Bit 15

Bit 7

Bit 15

Bit 7

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 15

Bit 7

Bit 15

Bit 7

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

Download from Www.Somanuals.com. All Manuals Search And Download.

Chapter 1 Device Overview (MC9S12XDP512V2)

0x0080–0x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD1) Map (Sheet 1 of

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0080

ATD1CTL0

WRAP3

WRAP2

WRAP1

WRAP0

ETRIG

SEL

ETRIG

CH3

ETRIG

CH2

ETRIG

CH1

ETRIG

CH0

0x0081

0x0082

0x0083

0x0084

0x0085

0x0086

0x0087

ATD1CTL1

ATD1CTL2

ATD1CTL3

ATD1CTL4

ATD1CTL5

ATD1STAT0

Reserved

ASCIF

ADPU

AFFC

S8C

AWAI

S4C

ETRIGLE ETRIGP

ETRIGE

FIFO

ASCIE

FRZ1

PRS1

S2C

PRS4

MULT

S1C

FRZ0

PRS0

SRES8

DJM

SMP1

SMP0

SCAN

PRS3

PRS2

DSGN

CC3

CC2

CC1

CC0

SCF

ETORF

FIFOR

0x0088 ATD1TEST0

0x0089 ATD1TEST1

0x008A ATD1STAT2

0x008B ATD1STAT1

0x008C ATD1DIEN0

Reserved For Factory Test

CCF15

CCF7

CCF14

CCF6

CCF13

CCF5

CCF12

CCF11

CCF10

CCF2

CCF9

CCF1

CCF8

CCF0

CCF4

CCF3

IEN15

IEN14

IEN13

IEN12

IEN11

IEN10

IEN9

IEN8

0x008D

ATD1DIEN

IEN7

IEN6

IEN5

IEN4

IEN3

IEN2

IEN1

IEN0

PTAD15

PTAD14

PTAD13

PTAD12

PTAD11

PTAD10

PTAD9

PTAD8

0x008E ATD1PTAD0

0x008F ATD1PTAD1

PTAD7

Bit15

Bit7

PTAD6

PTAD5

PTAD4

PTAD3

PTAD2

PTAD1

PTAD0

Bit8

0x0090

0x0091

0x0092

0x0093

0x0094

0x0095

ATD1DR0H

ATD1DR0L

ATD1DR1H

ATD1DR1L

ATD1DR2H

ATD1DR2L

Bit6

Bit15

Bit7

Bit8

Bit6

Bit15

Bit7

Bit8

Bit6

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x0080–0x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD1) Map (Sheet 2 of

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit15

Bit8

0x0096

ATD1DR3H

Bit7

Bit15

Bit7

Bit6

Bit8

0x0097

0x0098

0x0099

0x009A

0x009B

0x009C

0x009D

0x009E

0x009F

0x00A0

0x00A1

0x00A2

0x00A3

ATD1DR3L

ATD1DR4H

ATD1DR4L

ATD1DR5H

ATD1DR5L

ATD1DR6H

ATD1DR6L

ATD1DR7H

ATD1DR7L

ATD1DR8H

ATD1DR8L

ATD1DR9H

ATD1DR9L

Bit6

Bit15

Bit7

Bit8

Bit6

Bit15

Bit7

Bit8

Bit6

Bit15

Bit7

Bit8

Bit6

Bit15

Bit7

Bit8

Bit6

Bit15

Bit7

Bit8

Bit6

Bit15

Bit7

Bit8

0x00A4 ATD1DR10H

0x00A5 ATD1DR10L

0x00A6 ATD1DR11H

0x00A7 ATD1DR11L

0x00A8 ATD1DR12H

0x00A9 ATD1DR12L

0x00AA ATD1DR13H

0x00AB ATD1DR13L

Bit6

Bit15

Bit7

Bit8

Bit6

Bit15

Bit7

Bit8

Bit6

Bit15

Bit7

Bit8

Bit6

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

Download from Www.Somanuals.com. All Manuals Search And Download.

Chapter 1 Device Overview (MC9S12XDP512V2)

0x0080–0x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD1) Map (Sheet 3 of

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit15

Bit8

0x00AC ATD1DR14H

0x00AD ATD1DR14L

0x00AE ATD1DR15H

0x00AF ATD1DR15L

Bit7

Bit15

Bit7

Bit6

Bit8

Bit6

0x00B0–0x00B7 Inter IC Bus (IIC1) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00B0

IBAD

ADR7

ADR6

ADR5

ADR4

ADR3

ADR2

ADR1

0x00B1

0x00B2

0x00B3

0x00B4

0x00B5

0x00B6

0x00B7

IBFD

IBCR

IBC7

IBC6

IBC5

IBC4

TX/RX

IBAL

IBC3

IBC2

IBC1

IBC0

IBEN

TCF

IBIE

MS/SL

IBB

TXAK

IBSWAI

RXAK

RSTA

SRW

IAAS

IBSR

IBIF

IBDR

D 0

Reserved

0x00B8–0x00BF Asynchronous Serial Interface (SCI2) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00B8

SCI2BDH

IREN

TNP1

TNP0

SBR12

SBR11

SBR10

SBR9

SBR8

0x00B9

0x00BA

SCI2BDL

SBR7

LOOPS

SBR6

SBR5

SBR4

SBR3

SBR2

ILT

SBR1

SBR0

SCI2CR1

SCISWAI

RSRC

WAKE

0x00B8 SCI2ASR1

0x00B9 SCI2ACR1

0x00BA SCI2ACR2

RXEDGIF

BERRV

BERRIF

BERRIE

BKDIF

BKDIE

BKDFE

RXEDGIE

BERRM1 BERRM0

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x00B8–0x00BF Asynchronous Serial Interface (SCI2) Map (continued)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00BB

SCI2CR2

TIE

TCIE

RIE

ILIE

RWU

SBK

TDRE

RDRF

IDLE

0x00BC

0x00BD

0x00BE

0x00BF

SCI2SR1

SCI2SR2

SCI2DRH

SCI2DRL

RAF

AMAP

TXPOL

RXPOL

BRK13

TXDIR

Those registers are accessible if the AMAP bit in the SCI2SR2 register is set to zero

Those registers are accessible if the AMAP bit in the SCI2SR2 register is set to one

0x00C0–0x00C7 Asynchronous Serial Interface (SCI3) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00C0

SCI3BDH

IREN

TNP1

TNP0

SBR12

SBR11

SBR10

SBR9

SBR8

0x00C1

0x00C2

SCI3BDL

SBR7

LOOPS

SBR6

SBR5

SBR4

SBR3

SBR2

ILT

SBR1

SBR0

SCI3CR1

SCISWAI

RSRC

WAKE

0x00C0 SCI3ASR1

0x00C1 SCI3ACR1

0x00C2 SCI3ACR2

RXEDGIF

BERRV

BERRIF

BERRIE

BKDIF

BKDIE

BKDFE

RXEDGIE

BERRM1 BERRM0

0x00C3

0x00C4

0x00C5

0x00C6

0x00C7

SCI3CR2

SCI3SR1

SCI3SR2

SCI3DRH

SCI3DRL

TIE

TCIE

RIE

ILIE

RWU

SBK

TDRE

RDRF

IDLE

RAF

AMAP

TXPOL

RXPOL

BRK13

TXDIR

Those registers are accessible if the AMAP bit in the SCI3SR2 register is set to zero

Those registers are accessible if the AMAP bit in the SCI3SR2 register is set to one

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x00C8–0x00CF Asynchronous Serial Interface (SCI0) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00C8

SCI0BDH

IREN

TNP1

TNP0

SBR12

SBR11

SBR10

SBR9

SBR8

0x00C9

0x00CA

SCI0BDL

SBR7

LOOPS

SBR6

SBR5

SBR4

SBR3

SBR2

ILT

SBR1

SBR0

SCI0CR1

SCISWAI

RSRC

WAKE

0x00C8 SCI0ASR1

0x00C9 SCI0ACR1

0x00CA SCI0ACR2

RXEDGIF

BERRV

BERRIF

BERRIE

BKDIF

BKDIE

BKDFE

RXEDGIE

BERRM1 BERRM0

0x00CB

0x00CC

0x00CD

0x00CE

0x00CF

SCI0CR2

SCI0SR1

SCI0SR2

SCI0DRH

SCI0DRL

TIE

TCIE

RIE

ILIE

RWU

SBK

TDRE

RDRF

IDLE

RAF

AMAP

TXPOL

RXPOL

BRK13

TXDIR

Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to zero

Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to one

0x00D0–0x00D7 Asynchronous Serial Interface (SCI1) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00D0

SCI1BDH

IREN

TNP1

TNP0

SBR12

SBR11

SBR10

SBR9

SBR8

0x00D1

0x00D2

SCI1BDL

SBR7

LOOPS

SBR6

SBR5

SBR4

SBR3

SBR2

ILT

SBR1

SBR0

SCI1CR1

SCISWAI

RSRC

WAKE

0x00D0 SCI1ASR1

0x00D1 SCI1ACR1

0x00D2 SCI1ACR2

RXEDGIF

BERRV

BERRIF

BERRIE

BKDIF

BKDIE

BKDFE

RXEDGIE

BERRM1 BERRM0

0x00D3

0x00D4

SCI1CR2

SCI1SR1

TIE

TCIE

RIE

ILIE

RWU

SBK

TDRE

RDRF

IDLE

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x00D0–0x00D7 Asynchronous Serial Interface (SCI1) Map (continued)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RAF

0x00D5

SCI1SR2

AMAP

TXPOL

RXPOL

BRK13

TXDIR

0x00D6

0x00D7

SCI1DRH

SCI1DRL

Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to zero

Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to one

0x00D8–0x00DF Serial Peripheral Interface (SPI0) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00D8

SPI0CR1

SPIE

SPE

SPTIE

MSTR

CPOL

CPHA

SSOE

LSBFE

0x00D9

0x00DA

0x00DB

0x00DC

0x00DD

0x00DE

0x00DF

SPI0CR2

SPI0BR

MODFEN BIDIROE

SPISWAI

SPC0

SPIF

SPPR2

SPPR1

SPTEF

SPPR0

SPR2

SPR1

SPR0

MODF

SPI0SR

Reserved

SPI0DR

Reserved

Bit7

Bit0

0x00E0–0x00E7 Inter IC Bus (IIC0) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00E0

IBAD

ADR7

ADR6

ADR5

ADR4

ADR3

ADR2

ADR1

0x00E1

0x00E2

0x00E3

0x00E4

IBFD

IBCR

IBSR

IBDR

IBC7

IBC6

IBC5

IBC4

TX/RX

IBAL

IBC3

IBC2

IBC1

IBC0

IBEN

TCF

IBIE

MS/SL

IBB

TXAK

IBSWAI

RXAK

RSTA

SRW

IAAS

IBIF

D 0

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x00E0–0x00E7 Inter IC Bus (IIC0) Map (continued)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00E5

Reserved

0x00E6

0x00E7

Reserved

0x00E8–0x00EF Reserved

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00E8

Reserved

0x00E9

0x00EA

0x00EB

0x00EC

0x00ED

0x00EE

0x00EF

Reserved

0x00F0–0x00F7 Serial Peripheral Interface (SPI1) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00F0

SPI1CR1

SPIE

SPE

SPTIE

MSTR

CPOL

CPHA

SSOE

LSBFE

0x00F1

0x00F2

0x00F3

0x00F4

0x00F5

0x00F6

0x00F7

SPI1CR2

SPI1BR

MODFEN BIDIROE

SPISWAI

SPC0

SPIF

SPPR2

SPPR1

SPTEF

SPPR0

SPR2

SPR1

SPR0

MODF

SPI1SR

Reserved

SPI1DR

Reserved

Bit7

Bit0

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x00F8–0x00FF Serial Peripheral Interface (SPI2) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00F8

SPI2CR1

SPIE

SPE

SPTIE

MSTR

CPOL

CPHA

SSOE

LSBFE

0x00F9

0x00FA

0x00FB

0x00FC

0x00FD

0x00FE

0x00FF

SPI2CR2

SPI2BR

MODFEN BIDIROE

SPISWAI

SPC0

SPIF

SPPR2

SPPR1

SPTEF

SPPR0

SPR2

SPR1

SPR0

MODF

SPI2SR

Reserved

SPI2DR

Reserved

Bit7

Bit0

0x0100–0x010F Flash Control Register (FTX512K4) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FDIVLD

0x0100

FCLKDIV

PRDIV8

FDIV5

RNV5

FDIV4

RNV4

FDIV3

RNV3

FDIV2

RNV2

FDIV1

SEC1

FDIV0

SEC0

KEYEN1 KEYEN0

0x0101

0x0102

0x0103

0x0104

0x0105

0x0106

0x0107

0x0108

0x0109

0x010A

0x010B

FSEC

FTSTMOD

FCNFG

FPROT

MRDS

WRALL

CBEIE

CCIE

KEYACC

FPHDIS

PVIOL

RNV6

FPOPEN

FPHS1

FPHS0

FPLDIS

BLANK

FPLS1

FPLS0

CCIF

NV6

FSTAT

CBEIF

ACCERR

FCMD

CMDB[6:0]

NV3

NV7

NV5

NV4

NV2

NV1

NV0

FCTL

FADDRHI

FADDRLO

FDATAHI

FDATALO

FADDRLO

FDATAHI

FDATALO

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x0100–0x010F Flash Control Register (FTX512K4) Map (continued)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x010C

Reserved

0x010D

0x010E

0x010F

Reserved

0x0110–0x011B EEPROM Control Register (EETX4K) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EDIVLD

0x0110

ECLKDIV

PRDIV8

EDIV5

EDIV4

EDIV3

EDIV2

EDIV1

EDIV0

0x0111

0x0112

0x0113

0x0114

0x0115

0x0116

0x0117

0x0118

0x0119

0x011A

0x011B

Reserved

ECNFG

CBEIE

CCIE

RNV6

RNV5

RNV4

EPROT

EPOPEN

EPDIS

EPS2

EPS1

EPS0

CCIF

BLANK

ESTAT

CBEIF

PVIOL

ACCERR

ECMD

CMDB[6:0]

Reserved

EADDRHI

EADDRLO

EDATAHI

EDATALO

EABHI

EABLO

EDHI

EDLO

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x011C–0x011F Memory Map Control (S12XMMC) Map 4 of 4

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x011C

RAMWPC

RPWE

AVIE

AVIF

0x011D

0x011E

0x011F

RAMXGU

RAMSHL

RAMSHU

XGU6

SHL6

SHU6

XGU5

SHL5

SHU5

XGU4

SHL4

SHU4

XGU3

SHL3

SHU3

XGU2

SHL2

SHU2

XGU1

SHL1

SHU1

XGU0

SHL0

SHU0

0x0120–0x012F Interrupt Module (S12XINT) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0120

Reserved

0x0121

0x0122

0x0123

0x0124

0x0125

IVBR

IVB_ADDR[7:0]

Reserved

0x0126 INT_XGPRIO

0x0127 INT_CFADDR

0x0128 INT_CFDATA0

0x0129 INT_CFDATA1

0x012A INT_CFDATA2

0x012B INT_CFDATA3

0x012C INT_CFDATA4

0x012D INT_CFDATA5

0x012E INT_CFDATA6

0x012F INT_CFDATA7

XILVL[2:0]

INT_CFADDR[7:4]

RQST

PRIOLVL[2:0]

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x00130–0x0137 Asynchronous Serial Interface (SCI4) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0130

SCI4BDH

IREN

TNP1

TNP0

SBR12

SBR11

SBR10

SBR9

SBR8

0x0131

0x0132

0x0130

0x0131

0x0132

0x0133

0x0134

0x0135

0x0136

0x0137

SCI4BDL

SBR7

LOOPS

SBR6

SBR5

SBR4

SBR3

SBR2

ILT

SBR1

SBR0

SCI4CR1

SCI4ASR1

SCI4ACR1

SCI4ACR2

SCI4CR2

SCI4SR1

SCI4SR2

SCI4DRH

SCI4DRL

SCISWAI

RSRC

WAKE

RXEDGIF

BERRV

BERRIF

BERRIE

BKDIF

BKDIE

BKDFE

RXEDGIE

BERRM1 BERRM0

TIE

TCIE

RIE

ILIE

RWU

SBK

TDRE

RDRF

IDLE

RAF

AMAP

TXPOL

RXPOL

BRK13

TXDIR

Those registers are accessible if the AMAP bit in the SCI4SR2 register is set to zero

Those registers are accessible if the AMAP bit in the SCI4SR2 register is set to one

0x0138–0x013F Asynchronous Serial Interface (SCI5) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0138

SCI5BDH

IREN

TNP1

TNP0

SBR12

SBR11

SBR10

SBR9

SBR8

0x0139

0x013A

0x0138

0x0139

SCI5BDL

SBR7

LOOPS

SBR6

SBR5

SBR4

SBR3

SBR2

ILT

SBR1

SBR0

SCI5CR1

SCI5ASR1

SCI5ACR1

SCISWAI

RSRC

WAKE

RXEDGIF

BERRV

BERRIF

BERRIE

BKDIF

BKDIE

BKDFE

RXEDGIE

0x013A SCI5ACR2

BERRM1 BERRM0

0x013B

0x013C

SCI5CR2

SCI5SR1

TIE

TCIE

RIE

ILIE

RWU

SBK

TDRE

RDRF

IDLE

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x0138–0x013F Asynchronous Serial Interface (SCI5) Map (continued)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RAF

0x013D

SCI5SR2

AMAP

TXPOL

RXPOL

BRK13

TXDIR

0x013E

0x013F

SCI5DRH

SCI5DRL

Those registers are accessible if the AMAP bit in the SCI5SR2 register is set to zero

Those registers are accessible if the AMAP bit in the SCI5SR2 register is set to one

0x0140–0x017F Freescale Scalable CAN — MSCAN (CAN0) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RXACT

SYNCH

0x0140

CAN0CTL0

RXFRM

CSWAI

TIME

WUPE

SLPRQ

SLPAK

INITRQ

INITAK

0x0141

0x0142

0x0143

0x0144

0x0145

0x0146

0x0147

0x0148

0x0149

CAN0CTL1

CAN0BTR0

CAN0BTR1

CAN0RFLG

CAN0RIER

CAN0TFLG

CAN0TIER

CAN0TARQ

CAN0TAAK

CANE

SJW1

SAMP

WUPIF

CLKSRC

SJW0

LOOPB

BRP5

LISTEN

BRP4

BORM

BRP3

WUPM

BRP2

BRP1

TSEG11

OVRIF

OVRIE

TXE1

BRP0

TSEG10

RXF

TSEG22

CSCIF

TSEG21

RSTAT1

TSEG20

RSTAT0

TSEG13

TSTAT1

TSEG12

TSTAT0

WUPIE

CSCIE

RSTATE1 RSTATE0 TSTATE1 TSTATE0

RXFIE

TXE0

TXE2

TXEIE2

TXEIE1

TXEIE0

ABTRQ2 ABTRQ1 ABTRQ0

ABTAK2

ABTAK1

ABTAK0

0x014A CAN0TBSEL

TX2

TX1

TX0

IDHIT2

IDHIT1

IDHIT0

0x014B

0x014C

0x014D

CAN0IDAC

Reserved

IDAM1

IDAM0

CAN0MISC

BOHOLD

RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0

TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0

0x014E CAN0RXERR

0x014F CAN0TXERR

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x0140–0x017F Freescale Scalable CAN — MSCAN (CAN0) Map (continued)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0150– CAN0IDAR0–

0x0153 CAN0IDAR3

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

0x0154– CAN0IDMR0–

0x0157 CAN0IDMR3

AM7

AC7

AM6

AC6

AM5

AC5

AM4

AC4

AM3

AC3

AM2

AC2

AM1

AC1

AM0

AC0

0x0158– CAN0IDAR4–

0x015B CAN0IDAR7

0x015C

CAN0IDMR4–

–

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

CAN0IDMR7

0x015F

FOREGROUND RECEIVE BUFFER

(See Detailed MSCAN Foreground Receive and Transmit Buffer Layout)

0x0160–

CAN0RXFG

0x016F

0x0170–

CAN0TXFG

0x017F

FOREGROUND TRANSMIT BUFFER

(See Detailed MSCAN Foreground Receive and Transmit Buffer Layout)

Detailed MSCAN Foreground Receive and Transmit Buffer Layout

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Extended ID

ID28

ID10

ID27

ID9

ID26

ID8

ID25

ID7

ID24

ID6

ID23

ID5

ID22

ID4

ID21

ID3

0xXXX0 Standard ID

CANxRIDR0

Extended ID

ID20

ID2

ID19

ID1

ID18

ID0

SRR=1

RTR

IDE=1

IDE=0

ID17

ID9

ID16

ID8

ID15

ID7

0xXXX1 Standard ID

CANxRIDR1

Extended ID

ID14

ID6

ID13

ID5

ID12

ID4

ID11

ID3

ID10

ID2

0xXXX2 Standard ID

CANxRIDR2

Extended ID

ID1

ID0

RTR

0xXXX3 Standard ID

CANxRIDR3

0xXXX4

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

CANxRDSR0–

–

CANxRDSR7

0xXXXB

DLC3

DLC2

DLC1

DLC0

0xXXXC CANRxDLR

0xXXXD

Reserved

TSR15

TSR7

TSR14

TSR6

TSR13

TSR5

TSR12

TSR4

TSR11

TSR3

TSR10

TSR2

TSR9

TSR1

TSR8

TSR0

0xXXXE CANxRTSRH

0xXXXF CANxRTSRL

Extended ID

ID28

ID10

ID27

ID9

ID26

ID8

ID25

ID7

ID24

ID6

ID23

ID5

ID22

ID4

ID21

ID3

CANxTIDR0

0xXX10

Standard ID

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Extended ID

CANxTIDR1

Standard ID

ID20

ID19

ID18

SRR=1

IDE=1

ID17

ID16

ID15

0xXX0x

XX10

ID2

ID1

ID0

RTR

ID11

IDE=0

ID10

Extended ID

CANxTIDR2

Standard ID

ID14

ID13

ID12

ID9

ID1

ID8

ID0

ID7

0xXX12

0xXX13

Extended ID

CANxTIDR3

Standard ID

ID6

ID5

ID4

ID3

ID2

RTR

0xXX14

–

0xXX1B

CANxTDSR0–

CANxTDSR7

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0xXX1C CANxTDLR

0xXX1D CANxTTBPR

0xXX1E CANxTTSRH

0xXX1F CANxTTSRL

DLC3

DLC2

DLC1

DLC0

PRIO7

TSR15

PRIO6

TSR14

PRIO5

TSR13

PRIO4

TSR12

PRIO3

TSR11

PRIO2

TSR10

PRIO1

TSR9

PRIO0

TSR8

TSR7

TSR6

TSR5

TSR4

TSR3

TSR2

TSR1

TSR0

0x0180–0x01BF Freescale Scalable CAN — MSCAN (CAN1) Map (Sheet 1 of 3)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RXACT

SYNCH

0x0180

CAN1CTL0

RXFRM

CSWAI

TIME

WUPE

SLPRQ

SLPAK

INITRQ

INITAK

0x0181

0x0182

0x0183

0x0184

0x0185

0x0186

0x0187

0x0188

CAN1CTL1

CAN1BTR0

CAN1BTR1

CAN1RFLG

CAN1RIER

CAN1TFLG

CAN1TIER

CAN1TARQ

CANE

SJW1

SAMP

WUPIF

CLKSRC

SJW0

LOOPB

BRP5

LISTEN

BRP4

BORM

BRP3

WUPM

BRP2

BRP1

TSEG11

OVRIF

OVRIE

TXE1

BRP0

TSEG10

RXF

TSEG22

CSCIF

TSEG21

RSTAT1

TSEG20

RSTAT0

TSEG13

TSTAT1

TSEG12

TSTAT0

WUPIE

CSCIE

RSTATE1 RSTATE0 TSTATE1 TSTATE0

RXFIE

TXE0

TXE2

TXEIE2

TXEIE1

TXEIE0

ABTRQ2 ABTRQ1 ABTRQ0

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x0180–0x01BF Freescale Scalable CAN — MSCAN (CAN1) Map (Sheet 2 of 3)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ABTAK2

ABTAK1

ABTAK0

0x0189

CAN1TAAK

0x018A CAN1TBSEL

TX2

TX1

TX0

IDHIT2

IDHIT1

IDHIT0

0x018B

0x018C

0x018D

CAN1IDAC

Reserved

IDAM1

IDAM0

CAN1MISC

BOHOLD

RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0

TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0

0x018E CAN1RXERR

0x018F CAN1TXERR

0x0190 CAN1IDAR0

0x0191 CAN1IDAR1

0x0192 CAN1IDAR2

0x0193 CAN1IDAR3

0x0194 CAN1IDMR0

0x0195 CAN1IDMR1

0x0196 CAN1IDMR2

0x0197 CAN1IDMR3

0x0198 CAN1IDAR4

0x0199 CAN1IDAR5

0x019A CAN1IDAR6

0x019B CAN1IDAR7

0x019C CAN1IDMR4

0x019D CAN1IDMR5

0x019E CAN1IDMR6

AC7

AM7

AC7

AM7

AC6

AM6

AC6

AM6

AC5

AM5

AC5

AM5

AC4

AM4

AC4

AM4

AC3

AM3

AC3

AM3

AC2

AM2

AC2

AM2

AC1

AM1

AC1

AM1

AC0

AM0

AC0

AM0

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x0180–0x01BF Freescale Scalable CAN — MSCAN (CAN1) Map (Sheet 3 of 3)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x019F CAN1IDMR7

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

FOREGROUND RECEIVE BUFFER

0x01A0–

CAN1RXFG

0x01AF

(See Detailed MSCAN Foreground Receive and Transmit Buffer Layout)

0x01B0–

CAN1TXFG

0x01BF

FOREGROUND TRANSMIT BUFFER

(See Detailed MSCAN Foreground Receive and Transmit Buffer Layout)

0x01C0–0x01FF Freescale Scalable CAN — MSCAN (CAN2) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RXACT

SYNCH

0x01C0

CAN2CTL0

RXFRM

CSWAI

TIME

WUPE

SLPRQ

SLPAK

INITRQ

INITAK

0x01C1

CAN2CTL1

CANE

SJW1

SAMP

WUPIF

CLKSRC

SJW0

LOOPB

BRP5

LISTEN

BRP4

BORM

BRP3

WUPM

BRP2

0x01C2 CAN2BTR0

0x01C3 CAN2BTR1

0x01C4 CAN2RFLG

BRP1

TSEG11

OVRIF

OVRIE

TXE1

BRP0

TSEG10

RXF

TSEG22

CSCIF

TSEG21

RSTAT1

TSEG20

RSTAT0

TSEG13

TSTAT1

TSEG12

TSTAT0

0x01C5

0x01C6 CAN2TFLG

0x01C7 CAN2TIER

0x01C8 CAN2TARQ

0x01C9 CAN2TAAK

0x01CA CAN2TBSEL

CAN2RIER

WUPIE

CSCIE

RSTATE1 RSTATE0 TSTATE1 TSTATE0

RXFIE

TXE0

TXE2

TXEIE2

TXEIE1

TXEIE0

ABTRQ2 ABTRQ1 ABTRQ0

ABTAK2

ABTAK1

ABTAK0

TX2

TX1

TX0

IDHIT2

IDHIT1

IDHIT0

0x01CB

0x01CC

CAN2IDAC

Reserved

IDAM1

IDAM0

0x01CD CAN2MISC

0x01CE CAN2RXERR

0x01CF CAN2TXERR

0x01D0 CAN2IDAR0

BOHOLD

RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0

TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x01C0–0x01FF Freescale Scalable CAN — MSCAN (CAN2) Map (continued)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x01D1 CAN2IDAR1

0x01D2 CAN2IDAR2

0x01D3 CAN2IDAR3

0x01D4 CAN2IDMR0

0x01D5 CAN2IDMR1

0x01D6 CAN2IDMR2

0x01D7 CAN2IDMR3

0x01D8 CAN2IDAR4

0x01D9 CAN2IDAR5

0x01DA CAN2IDAR6

0x01DB CAN2IDAR7

0x01DC CAN2IDMR4

0x01DD CAN2IDMR5

0x01DE CAN2IDMR6

0x01DF CAN2IDMR7

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

AC7

AM7

AC7

AM7

AC6

AM6

AC6

AM6

AC5

AM5

AC5

AM5

AC4

AM4

AC4

AM4

AC3

AM3

AC3

AM3

AC2

AM2

AC2

AM2

AC1

AM1

AC1

AM1

AC0

AM0

AC0

AM0

FOREGROUND RECEIVE BUFFER

0x01E0–

CAN2RXFG

0x01EF

(See Detailed MSCAN Foreground Receive and Transmit Buffer Layout)

0x01F0–

CAN2TXFG

0x01FF

FOREGROUND TRANSMIT BUFFER

(See Detailed MSCAN Foreground Receive and Transmit Buffer Layout)

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x0200–0x023F Freescale Scalable CAN — MSCAN (CAN3)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RXACT

SYNCH

0x0200

CAN3CTL0

RXFRM

CSWAI

TIME

WUPE

SLPRQ

SLPAK

INITRQ

INITAK

0x0201

0x0202

0x0203

0x0204

0x0205

0x0206

0x0207

0x0208

0x0209

CAN3CTL1

CAN3BTR0

CAN3BTR1

CAN3RFLG

CAN3RIER

CAN3TFLG

CAN3TIER

CAN3TARQ

CAN3TAAK

CANE

SJW1

SAMP

WUPIF

CLKSRC

SJW0

LOOPB

BRP5

LISTEN

BRP4

BORM

BRP3

WUPM

BRP2

BRP1

TSEG11

OVRIF

OVRIE

TXE1

BRP0

TSEG10

RXF

TSEG22

CSCIF

TSEG21

RSTAT1

TSEG20

RSTAT0

TSEG13

TSTAT1

TSEG12

TSTAT0

WUPIE

CSCIE

RSTATE1 RSTATE0 TSTATE1 TSTATE0

RXFIE

TXE0

TXE2

TXEIE2

TXEIE1

TXEIE0

ABTRQ2 ABTRQ1 ABTRQ0

ABTAK2

ABTAK1

ABTAK0

0x020A CAN3TBSEL

TX2

TX1

TX0

IDHIT2

IDHIT1

IDHIT0

0x020B

0x020C

0x020D

CAN3IDAC

Reserved

IDAM1

IDAM0

BOHOLD

RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0

TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0

0x020E CAN3RXERR

0x020F CAN3TXERR

0x0210 CAN3IDAR0

0x0211 CAN3IDAR1

0x0212 CAN3IDAR2

0x0213 CAN3IDAR3

0x0214 CAN3IDMR0

0x0215 CAN3IDMR1

AC7

AM7

AC6

AM6

AC5

AM5

AC4

AM4

AC3

AM3

AC2

AM2

AC1

AM1

AC0

AM0

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x0200–0x023F Freescale Scalable CAN — MSCAN (CAN3) (continued)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0216 CAN3IDMR2

0x0217 CAN3IDMR3

0x0218 CAN3IDAR4

0x0219 CAN3IDAR5

0x021A CAN3IDAR6

0x021B CAN3IDAR7

0x021C CAN3IDMR4

0x021D CAN3IDMR5

0x021E CAN3IDMR6

0x021F CAN3IDMR7

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

AM7

AC7

AM7

AM6

AC6

AM6

AM5

AC5

AM5

AM4

AC4

AM4

AM3

AC3

AM3

AM2

AC2

AM2

AM1

AC1

AM1

AM0

AC0

AM0

FOREGROUND RECEIVE BUFFER

0x0220–

CAN3RXFG

0x022F

(See Detailed MSCAN Foreground Receive and Transmit Buffer Layout)

0x0230–

CAN3TXFG

0x023F

FOREGROUND TRANSMIT BUFFER

(See Detailed MSCAN Foreground Receive and Transmit Buffer Layout)

0x0240–0x027F Port Integration Module PIM_9DX (PIM) Map (Sheet 1 of 4)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0240

PTT

PTT7

PTT6

PTT5

PTT4

PTT3

PTT2

PTT1

PTT0

PTIT7

PTIT6

PTIT5

PTIT4

PTIT3

PTIT2

PTIT1

PTIT0

0x0241

0x0242

0x0243

0x0244

0x0245

0x0246

0x0247

PTIT

DDRT

DDRT7

RDRT7

PERT7

DDRT7

RDRT6

PERT6

DDRT5

RDRT5

PERT5

DDRT4

RDRT4

PERT4

DDRT3

RDRT3

PERT3

DDRT2

RDRT2

PERT2

DDRT1

RDRT1

PERT1

DDRT0

RDRT0

PERT0

RDRT

PERT

PPST

PPST7

PPST6

PPST5

PPST4

PPST3

PPST2

PPST1

PPST0

Reserved

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x0240–0x027F Port Integration Module PIM_9DX (PIM) Map (Sheet 2 of 4)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0248

PTS

PTS7

PTS6

PTS5

PTS4

PTS3

PTS2

PTS1

PTS0

PTIS7

PTIS6

PTIS5

PTIS4

PTIS3

PTIS2

PTIS1

PTIS0

0x0249

0x024A

0x024B

0x024C

0x024D

0x024E

0x024F

0x0250

0x0251

0x0252

0x0253

0x0254

0x0255

0x0256

0x0257

0x0258

0x0259

0x025A

0x025B

0x025C

0x025D

0x025E

0x025F

PTIS

DDRS

RDRS

PERS

PPSS

WOMS

Reserved

PTM

DDRS7

RDRS7

PERS7

PPSS7

DDRS7

RDRS6

PERS6

PPSS6

DDRS5

RDRS5

PERS5

PPSS5

DDRS4

RDRS4

PERS4

PPSS4

DDRS3

RDRS3

PERS3

PPSS3

DDRS2

RDRS2

PERS2

PPSS2

DDRS1

RDRS1

PERS1

PPSS1

DDRS0

RDRS0

PERS0

PPSS0

WOMS7

WOMS6

WOMS5

WOMS4

WOMS3

WOMS2

WOMS1

WOMS0

PTM7

PTM6

PTM5

PTM4

PTM3

PTM2

PTM1

PTM0

PTIM7

PTIM6

PTIM5

PTIM4

PTIM3

PTIM2

PTIM1

PTIM0

PTIM

DDRM

RDRM

PERM

PPSM

WOMM

MODRR

PTP

DDRM7

RDRM7

PERM7

PPSM7

DDRM7

RDRM6

PERM6

PPSM6

DDRM5

RDRM5

PERM5

PPSM5

DDRM4

RDRM4

PERM4

PPSM4

DDRM3

RDRM3

PERM3

PPSM3

DDRM2

RDRM2

PERM2

PPSM2

DDRM1

RDRM1

PERM1

PPSM1

DDRM0

RDRM0

PERM0

PPSM0

WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0

MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0

PTP7

PTP6

PTP5

PTP4

PTP3

PTP2

PTP1

PTP0

PTIP7

PTIP6

PTIP5

PTIP4

PTIP3

PTIP2

PTIP1

PTIP0

PTIP

DDRP

RDRP

PERP

PPSP

PIEP

DDRP7

RDRP7

PERP7

PPSP7

PIEP7

DDRP7

RDRP6

PERP6

PPSP6

PIEP6

DDRP5

RDRP5

PERP5

PPSP5

PIEP5

DDRP4

RDRP4

PERP4

PPSP4

PIEP4

DDRP3

RDRP3

PERP3

PPSP3

PIEP3

DDRP2

RDRP2

PERP2

PPSP2

PIEP2

DDRP1

RDRP1

PERP1

PPSP1

PIEP1

DDRP0

RDRP0

PERP0

PPSS0

PIEP0

PIFP

PIFP7

PIFP6

PIFP5

PIFP4

PIFP3

PIFP2

PIFP1

PIFP0

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

Download from Www.Somanuals.com. All Manuals Search And Download.

Chapter 1 Device Overview (MC9S12XDP512V2)

0x0240–0x027F Port Integration Module PIM_9DX (PIM) Map (Sheet 3 of 4)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0260

PTH

PTH7

PTH6

PTH5

PTH4

PTH3

PTH2

PTH1

PTH0

PTIH7

PTIH6

PTIH5

PTIH4

PTIH3

PTIH2

PTIH1

PTIH0

0x0261

0x0262

0x0263

0x0264

0x0265

0x0266

0x0267

0x0268

0x0269

0x026A

0x026B

0x026C

0x026D

0x026E

0x026F

0x0270

0x0271

0x0272

0x0273

0x0274

0x0275

0x0276

0x0277

PTIH

DDRH

RDRH

PERH

DDRH7

RDRH7

PERH7

PPSH7

PIEH7

DDRH7

RDRH6

PERH6

PPSH6

PIEH6

DDRH5

RDRH5

PERH5

PPSH5

PIEH5

DDRH4

RDRH4

PERH4

PPSH4

PIEH4

DDRH3

RDRH3

PERH3

PPSH3

PIEH3

DDRH2

RDRH2

PERH2

PPSH2

PIEH2

DDRH1

RDRH1

PERH1

PPSH1

PIEH1

DDRH0

RDRH0

PERH0

PPSH0

PIEH0

PPSH

PIEH

PIFH

PIFH7

PIFH6

PIFH5

PIFH4

PIFH3

PIFH2

PIFH1

PIFH0

PTJ

PTJ7

PTJ6

PTJ5

PTJ4

PTJ2

PTJ1

PTJ0

PTIJ7

PTIJ6

PTIJ5

PTIJ4

PTIJ2

PTIJ1

PTIJ0

PTIJ

DDRJ

DDRJ7

RDRJ7

PERJ7

PPSJ7

PIEJ7

DDRJ7

RDRJ6

PERJ6

PPSJ6

PIEJ6

DDRJ5

RDRJ5

PERJ5

PPSJ5

PIEJ5

DDRJ4

RDRJ4

PERJ4

PPSJ4

PIEJ4

DDRJ2

RDRJ2

PERJ2

PPSJ2

PIEJ2

DDRJ1

RDRJ1

PERJ1

PPSJ1

PIEJ1

DDRJ0

RDRJ0

PERJ0

PPSJ0

PIEJ0

RDRJ

PERJ

PPSJ

PIEJ

PIFJ

PIFJ7

PIFJ6

PIFJ5

PIFJ4

PIFJ2

PIFJ1

PIFJ0

Reserved

PT1AD0

Reserved

DDR1AD0

Reserved

RDR1AD0

Reserved

PER1AD0

PT1AD07 PT1AD06 PT1AD05 PT1AD04 PT1AD03 PT1AD02 PT1AD01 PT1AD00

DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0

RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0

PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

Download from Www.Somanuals.com. All Manuals Search And Download.

Chapter 1 Device Overview (MC9S12XDP512V2)

0x0240–0x027F Port Integration Module PIM_9DX (PIM) Map (Sheet 4 of 4)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PT0AD1

0x0278

PT0AD1

PT1AD1

0x0279

0x027A

0x027B

0x027C

0x027D

0x027E

0x027F

PT1AD1

DDR0AD1

DDR1AD1

RDR0AD1

RDR1AD1

PER0AD1

PER1AD1

DDR0AD1 DDR0AD1 DDR0AD1 DDR0AD1 DDR0AD1 DDR0AD1 DDR0AD1 DDR0AD1

23 22 21 20 19 18 17 16

DDR1AD1 DDR1AD1 DDR1AD1 DDR1AD1 DDR1AD1 DDR1AD1 DDR1AD1 DDR1AD1

15 14 13 12 11 10

RDR0AD1 RDR0AD1 RDR0AD1 RDR0AD1 RDR0AD1 RDR0AD1 RDR0AD1 RDR0AD1

23 22 21 20 19 18 17 16

RDR1AD1 RDR1AD1 RDR1AD1 RDR1AD1 RDR1AD1 RDR1AD1 RDR1AD1 RDR1AD1

15 14 13 12 11 10

PER0AD1 PER0AD1 PER0AD1 PER0AD1 PER0AD1 PER0AD1 PER0AD1 PER0AD1

23 22 21 20 19 18 17 16

PER1AD1 PER1AD1 PER1AD1 PER1AD1 PER1AD1 PER1A1D PER1AD1 PER1AD1

0x0280–0x02BF Freescale Scalable CAN — MSCAN (CAN4) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RXACT

SYNCH

0x0280

CAN4CTL0

RXFRM

CSWAI

TIME

WUPE

SLPRQ

SLPAK

INITRQ

INITAK

0x0281

0x0282

0x0283

0x0284

0x0285

0x0286

0x0287

0x0288

0x0289

CAN4CTL1

CAN4BTR0

CAN4BTR1

CAN4RFLG

CAN4RIER

CAN4TFLG

CAN4TIER

CAN4TARQ

CAN4TAAK

CANE

SJW1

SAMP

WUPIF

CLKSRC

SJW0

LOOPB

BRP5

LISTEN

BRP4

BORM

BRP3

WUPM

BRP2

BRP1

TSEG11

OVRIF

OVRIE

TXE1

BRP0

TSEG10

RXF

TSEG22

CSCIF

TSEG21

RSTAT1

TSEG20

RSTAT0

TSEG13

TSTAT1

TSEG12

TSTAT0

WUPIE

CSCIE

RSTATE1 RSTATE0 TSTATE1 TSTATE0

RXFIE

TXE0

TXE2

TXEIE2

TXEIE1

TXEIE0

ABTRQ2 ABTRQ1 ABTRQ0

ABTAK2

ABTAK1

ABTAK0

0x028A CAN4TBSEL

TX2

TX1

TX0

IDHIT2

IDHIT1

IDHIT0

0x028B

0x028C

CAN4IDAC

Reserved

IDAM1

IDAM0

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

Download from Www.Somanuals.com. All Manuals Search And Download.

Chapter 1 Device Overview (MC9S12XDP512V2)

0x0280–0x02BF Freescale Scalable CAN — MSCAN (CAN4) Map (continued)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x028D

CAN4MISC

BOHOLD

RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0

TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0

0x028E CAN4RXERR

0x028F CAN4TXERR

0x0290 CAN4IDAR0

0x0291 CAN4IDAR1

0x0292 CAN4IDAR2

0x0293 CAN4IDAR3

0x0294 CAN4IDMR0

0x0295 CAN4IDMR1

0x0296 CAN4IDMR2

0x0297 CAN4IDMR3

0x0298 CAN4IDAR4

0x0299 CAN4IDAR5

0x029A CAN4IDAR6

0x029B CAN4IDAR7

0x029C CAN4IDMR4

0x029D CAN4IDMR5

0x029E CAN4IDMR6

0x029F CAN4IDMR7

AC7

AM7

AC7

AM7

AC6

AM6

AC6

AM6

AC5

AM5

AC5

AM5

AC4

AM4

AC4

AM4

AC3

AM3

AC3

AM3

AC2

AM2

AC2

AM2

AC1

AM1

AC1

AM1

AC0

AM0

AC0

AM0

FOREGROUND RECEIVE BUFFER

0x02A0–

CAN4RXFG

0x02AF

(See Detailed MSCAN Foreground Receive and Transmit Buffer Layout)

0x02B0–

CAN4TXFG

0x02BF

FOREGROUND TRANSMIT BUFFER

(See Detailed MSCAN Foreground Receive and Transmit Buffer Layout)

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

Download from Www.Somanuals.com. All Manuals Search And Download.

Chapter 1 Device Overview (MC9S12XDP512V2)

0x02C0–0x02DF Analog-to-Digital Converter 10-Bit 8-Channel (ATD0) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x02C0

ATD0CTL0

WRAP2

WRAP1

WRAP0

ETRIG

SEL

ETRIG

CH2

ETRIG

CH1

ETRIG

CH0

0x02C1

0x02C2

0x02C3

0x02C4

0x02C5

ATD0CTL1

ATD0CTL2

ATD0CTL3

ATD0CTL4

ATD0CTL5

ASCIF

ADPU

AFFC

S8C

AWAI

S4C

ETRIGLE ETRIGP

ETRIGE

FIFO

ASCIE

FRZ1

PRS1

S2C

PRS4

MULT

S1C

FRZ0

PRS0

SRES8

DJM

SMP1

SMP0

SCAN

PRS3

PRS2

DSGN

CC2

CC1

CC0

0x02C6 ATD0STAT0

0x02C7 Reserved

SCF

ETORF

FIFOR

0x02C8 ATD0TEST0

0x02C9 ATD0TEST1

0x02CA

Reserved

CCF7

CCF6

CCF5

CCF4

CCF3

CCF2

CCF1

CCF0

0x02CB ATD0STAT1

0x02CC

0x02CD

0x02CE

Reserved

ATD0DIEN

Reserved

IEN7

IEN6

IEN5

IEN4

IEN3

IEN2

IEN1

IEN0

Bit7

Bit15

Bit7

BIT 0

Bit8

0x02CF ATD0PTAD0

0x02D0

0x02D1

0x02D2

0x02D3

0x02D4

0x02D5

ATD0DR0H

ATD0DR0L

ATD0DR1H

ATD0DR1L

ATD0DR2H

ATD0DR2L

Bit6

Bit15

Bit7

Bit8

Bit6

Bit15

Bit7

Bit8

Bit6

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

Download from Www.Somanuals.com. All Manuals Search And Download.

Chapter 1 Device Overview (MC9S12XDP512V2)

0x02C0–0x02DF Analog-to-Digital Converter 10-Bit 8-Channel (ATD0) Map (continued)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit15

Bit8

0x02D6

ATD0DR3H

Bit7

Bit15

Bit7

Bit6

Bit8

0x02D7

0x02D8

0x02D9

ATD0DR3L

ATD0DR4H

ATD0DR4L

Bit6

Bit15

Bit7

Bit8

0x02DA ATD0DR5H

0x02DB ATD0DR5L

0x02DC ATD0DR6H

0x02DD ATD0DR6L

0x02DE ATD0DR7H

0x02DF ATD0DR7L

Bit6

Bit15

Bit7

Bit8

Bit6

Bit15

Bit7

Bit8

Bit6

0x02E0–0x02EF Reserved

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x02E0–

0x02EF

Reserved

0x02F0–0x02F7 Voltage Regulator (VREG_3V3) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x02F0 VREGHTCL

0x02F1 VREGCTRL

0x02F2 VREGAPICL

0x02F3 VREGAPITR

0x02F4 VREGAPIRH

0x02F5 VREGAPIRL

Reserved for Factory Test

LVDS

LVIE

LVIF

APICLK

APIFE

APITR0

APIR10

APIE

APIF

APITR5

APITR4

APITR3

APITR2

APITR1

APIR11

APIR9

APIR8

APIR7

APIR6

APIR5

APIR4

APIR3

APIR2

APIR1

APIR0

0x02F6

0x02F7

Reserved

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

Download from Www.Somanuals.com. All Manuals Search And Download.

Chapter 1 Device Overview (MC9S12XDP512V2)

0x02F8–0x02FF Reserved

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x02F8–

0x02FF

Reserved

0x0300–0x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0300

PWME

PWME7

PWME6

PWME5

PWME4

PWME3

PWME2

PWME1

PWME0

0x0301

0x0302

PWMPOL

PWMCLK

PPOL7

PPOL6

PCLK6

PCKB2

CAE6

PPOL5

PCLK5

PCKB1

CAE5

PPOL4

PCLK4

PCKB0

CAE4

PPOL3

PPOL2

PCLK2

PCKA2

CAE2

PPOL1

PCLK1

PCKA1

PPOL0

PCLK0

PCKA0

PCLK7

PCLK3

0x0303 PWMPRCLK

0x0304

0x0305

0x0306

0x0307

0x0308

0x0309

PWMCAE

PWMCTL

CAE7

CAE3

CAE1

CAE0

CON67

CON45

CON23

CON01

PSWAI

PFRZ

PWMTST

Test Only

PWMPRSC

PWMSCLA

PWMSCLB

Bit 7

Bit 0

Bit 7

Bit 0

0x030A PWMSCNTA

0x030B PWMSCNTB

Bit 7

Bit 0

0x030C

0x030D

0x030E

0x030F

0x0310

0x0311

0x0312

0x0313

PWMCNT0

PWMCNT1

PWMCNT2

PWMCNT3

PWMCNT4

PWMCNT5

PWMCNT6

PWMCNT7

Bit 7

Bit 0

Bit 7

Bit 0

Bit 7

Bit 0

Bit 7

Bit 0

Bit 7

Bit 0

Bit 7

Bit 0

Bit 7

Bit 0

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

Download from Www.Somanuals.com. All Manuals Search And Download.

Chapter 1 Device Overview (MC9S12XDP512V2)

0x0300–0x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0314

PWMPER0

Bit 7

Bit 0

0x0315

0x0316

0x0317

0x0318

0x0319

0x031A

0x031B

0x031C

0x031D

0x031E

0x031F

0x0320

0x0321

0x0322

0x0323

PWMPER1

PWMPER2

PWMPER3

PWMPER4

PWMPER5

PWMPER6

PWMPER7

PWMDTY0

PWMDTY1

PWMDTY2

PWMDTY3

PWMDTY4

PWMDTY5

PWMDTY6

PWMDTY7

Bit 7

Bit 0

PWM7IN

PWM7

ENA

0x0324

PWMSDN

PWMIF

PWMIE

PWMLVL

PWM7INL

PWM

RSTRT

0x0325

0x0326

0x0327

Reserved

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

Download from Www.Somanuals.com. All Manuals Search And Download.

Chapter 1 Device Overview (MC9S12XDP512V2)

0x0328–0x033F Reserved

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0328–

0x033F

Reserved

0x0340–0x0367 Periodic Interrupt Timer (PIT) Map

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PFLMT1

PFLMT0

0x0340

PITCFLMT

PITE

PITSWAI

PITFRZ

0x0341

0x0342

0x0343

0x0344

0x0345

0x0346

0x0347

0x0348

0x0349

PITFLT

PITCE

PFLT3

PFLT2

PFLT1

PFLT0

PCE3

PMUX3

PINTE3

PTF3

PCE2

PMUX2

PINTE2

PTF2

PCE1

PMUX1

PINTE1

PTF1

PCE0

PMUX0

PINTE0

PTF0

PITMUX

PITINTE

PITTF

PITMTLD0

PITMTLD1

PITLD0 (hi)

PITLD0 (lo)

PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0

PLD15

PLD7

PLD14

PLD6

PLD13

PLD5

PLD12

PLD4

PLD11

PLD3

PLD10

PLD2

PLD9

PLD1

PLD8

PLD0

0x034A PITCNT0 (hi)

0x034B PITCNT0 (lo)

PCNT15

PCNT7

PLD15

PLD7

PCNT14

PCNT6

PLD14

PLD6

PCNT13

PCNT5

PLD13

PLD5

PCNT12

PCNT4

PLD12

PLD4

PCNT11

PCNT3

PLD11

PLD3

PCNT10

PCNT2

PLD10

PLD2

PCNT9

PCNT1

PLD9

PCNT8

PCNT0

PLD8

0x034C

0x034D

PITLD1 (hi)

PITLD1 (lo)

PLD1

PLD0

0x034E PITCNT1 (hi)

0x034F PITCNT1 (lo)

PCNT15

PCNT7

PLD15

PLD7

PCNT14

PCNT6

PLD14

PLD6

PCNT13

PCNT5

PLD13

PLD5

PCNT12

PCNT4

PLD12

PLD4

PCNT11

PCNT3

PLD11

PLD3

PCNT10

PCNT2

PLD10

PLD2

PCNT9

PCNT1

PLD9

PCNT8

PCNT0

PLD8

0x0350

0x0351

PITLD2 (hi)

PITLD2 (lo)

PLD1

PLD0

0x0352 PITCNT2 (hi)

0x0353 PITCNT2 (lo)

PCNT15

PCNT7

PCNT14

PCNT6

PCNT13

PCNT5

PCNT12

PCNT4

PCNT11

PCNT3

PCNT10

PCNT2

PCNT9

PCNT1

PCNT8

PCNT0

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

Download from Www.Somanuals.com. All Manuals Search And Download.

Chapter 1 Device Overview (MC9S12XDP512V2)

0x0340–0x0367 Periodic Interrupt Timer (PIT) Map (continued)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0354

PITLD3 (hi)

PLD15

PLD14

PLD13

PLD12

PLD11

PLD10

PLD9

PLD8

0x0355

PITLD3 (lo)

PLD7

PLD6

PLD5

PLD4

PLD3

PLD2

PLD1

PLD0

0x0356 PITCNT3 (hi)

0x0357 PITCNT3 (lo)

PCNT15

PCNT14

PCNT13

PCNT12

PCNT11

PCNT10

PCNT9

PCNT8

PCNT7

PCNT6

PCNT5

PCNT4

PCNT3

PCNT2

PCNT1

PCNT0

0x0358–

Reserved

0x0367

0x0368–0x037F Reserved

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0368–

0x037F

Reserved

0x0380–0x03BF XGATE Map (Sheet 1 of 3)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0380

XGMCTL

XGIEM

XGS

WEIFM

XGEM

XGFRZM XGDBGM XGSSM XGFACTM

0x0381

0x0382

0x0383

0x0384

0x0385

0x0386

0x0387

0x0388

0x0389

0x038A

0x023B

0x023C

XGMCTL

XGCHID

Reserved

XGVBR

XGIF

XGE

XGFRZ

XGDBG

XGSS

XGFACT

XGSWEIF

XGIE

XGCHID[6:0]

XGVBR[15:8]

XGVBR[7:1]

XGIF_78

XGIF

XGIF_77 XGIF_76 XGIF_75 XGIF_74 XGIF_73 XGIF_72 XGIF_71 XGIF_70

XGIF_6F XGIF_6E XGIF_6D XGIF_6C XGIF_6B XGIF_6A XGIF_69 XGIF_68

XGIF_67 XGIF_66 XGIF_65 XGIF_64 XGIF_63 XGIF_62 XGIF_61 XGIF_60

XGIF_5F XGIF_5E XGIF_5D XGIF_5C XGIF_5B XGIF_5A XGIF_59 XGIF_58

XGIF

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x0380–0x03BF XGATE Map (Sheet 2 of 3)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x038D

XGIF

XGIF_57 XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50

XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48

XGIF_47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40

XGIF_3F XGIF_3E XGIF_3D XGIF_3C XGIF_3B XGIF_3A XGIF_39 XGIF_38

XGIF_37 XGIF_36 XGIF_35 XGIF_34 XGIF_33 XGIF_32 XGIF_31 XGIF_30

XGIF_2F XGIF_2E XGIF_2D XGIF_2C XGIF_2B XGIF_2A XGIF_29 XGIF_28

XGIF_27 XGIF_26 XGIF_25 XGIF_24 XGIF_23 XGIF_22 XGIF_21 XGIF_20

XGIF_1F XGIF_1E XGIF_1D XGIF_1C XGIF_1B XGIF_1A XGIF_19 XGIF_18

XGIF_17 XGIF_16 XGIF_15 XGIF_14 XGIF_13 XGIF_12 XGIF_11 XGIF_10

0x038E

0x038F

0x0390

0x0391

0x0392

0x0393

0x0394

0x0395

0x0396

0x0397

XGIF

XGIF_0F XGIF_0E XGIF_0D XGIF_0C XGIF_0B XGIF_0A XGIF_09

0x0398 XGSWT (hi)

0x0399 XGSWT (lo)

0x039A XGSEM (hi)

0x039B XGSEM (lo)

XGSWTM[7:0]

XGSWT[7:0]

XGSEMM[7:0]

XGSEM[7:0]

0x039C

0x039D

0x039E

0x039F

0x03A0

0x03A1

0x03A2

0x03A3

Reserved

XGCCR

XGN

XGZ

XGV

XGC

XGPC (hi)

XGPC (lo)

Reserved

XGR1 (hi)

XGR1 (lo)

XGPC[15:8]

XGPC[7:0]

XGR1[15:8]

XGR1[7:0]

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

0x0380–0x03BF XGATE Map (Sheet 3 of 3)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x03A4

XGR2 (hi)

XGR2[15:8]

0x03A5

0x03A6

0x03A7

0x03A8

0x03A9

0x03AA

0x03AB

0x03AC

0x03AD

0x03AE

0x03AF

XGR2 (lo)

XGR3 (hi)

XGR3 (lo)

XGR4 (hi)

XGR4 (lo)

XGR5 (hi)

XGR5(lo)

XGR6 (hi)

XGR6 (lo)

XGR7 (hi)

XGR7 (lo)

Reserved

XGR2[7:0]

XGR3[15:8]

XGR3[7:0]

XGR4[15:8]

XGR4[7:0]

XGR5[15:8]

XGR5[7:0]

XGR6[15:8]

XGR6[7:0]

XGR7[15:8]

XGR7[7:0]

0x03B0–

0x03BF

0x03C0–0x07FF Reserved

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x03C0

–0x07FF

Reserved

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

1.1.7

Part ID Assignments

The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B).

The read-only value is a unique part ID for each revision of the chip. Table 1-2 shows the assigned part ID

number and Mask Set number.

Table 1-2. Assigned Part ID Numbers

Device

Mask Set Number

Part ID

MC9S12XDP512

MC9S12XDT384

L15Y

0xC410

The coding is as follows:

Bit 15-12: Major family identiﬁer

Bit 11-8: Minor family identiﬁer

Bit 7-4: Major mask set revision number including FAB transfers

Bit 3-0: Minor — non full — mask set revision

1.2

Signal Description

This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal

properties, and detailed discussion of signals. It is built from the signal description sections of the Block

User Guides of the individual IP blocks on the device.

1.2.1

Device Pinout

The XD-Family of devices offers pin-compatible packaged devices to assist with system development and

accommodate expansion of the application.

The MC9S12XD-Family and MC9S12XA-Family devices are offered in the following package options:

•

144-pin LQFP package with an external bus interface (address/data bus)

112-pin LQFP without external bus interface

80-pin QFP without external bus interface

Most pins perform two or more functions, as described in more detail in Section 1.2.2, “Signal Properties

Summary”. Figure 1-5, Figure 1-6, and Figure 1-7 show the pin assignments for the various packages.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

108

107

106

105

104

103

102

101

100

SS1/PWM3/KWP3/PP3

SCK1/PWM2/KWP2/PP2

MOSI1/PWM1/KWP1/PP1

MISO1/PWM0/KWP0/PP0

CS1/KWJ2/PJ2

ACC2/ADDR22/PK6

IQSTAT3/ADDR19/PK3

IQSTAT2/ADDR18/PK2

IQSTAT1/ADDR17/PK1

IQSTAT0/ADDR16/PK0

IOC0/PT0

VRH

VDDA

PAD17/AN17

PAD16/AN16

PAD15/AN15

PAD07/AN07

PAD14/AN14

PAD06/AN06

PAD13/AN13

PAD05/AN05

PAD12/AN12

PAD04/AN04

PAD11/AN11

PAD03/AN03

PAD10/AN10

PAD02/AN02

PAD09/AN09

PAD01/AN01

PAD08/AN08

PAD00/AN00

VSS2

IOC1/PT1

IOC2/PT2

IOC3/PT3

VDD1

VSS1

IOC4/PT4

MC9S12XD-Family

144-Pin LQFP

IOC5/PT5

IOC6/PT6

IOC7/PT7

ACC1/ADDR21/PK5

ACC0/ADDR20/PK4

TXD2/KWJ1/PJ1

CS3/RXD2/KWJ0/PJ0

MODC/BKGD

VDD2

PD7/DATA7

PD6/DATA6

PD5/DATA5

PD4/DATA4

VDDR2

VDDX2

VSSX2

Pins shown in BOLD-ITALICS are not available on the

DATA8/PC0

VSSR2

112-Pin LQFP or the 80-Pin QFP package option

DATA9/PC1

PA7/ADDR15

PA6/ADDR14

PA5/ADDR13

PA4/ADDR12

PA3/ADDR11

PA2/ADDR10

PA1/ADDR9

PA0/ADDR8

DATA10/PC2

DATA11/PC3

Pins shown in BOLD are not available on the

UDS/ADDR0/PB0

ADDR1/PB1

80-Pin QFP package option

ADDR2/PB2

ADDR3/PB3

ADDR4/PB4

Figure 1-5. MC9S12XD-Family Pin Assignment 144-Pin LQFP Package

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

SS1/PWM3/KWP3/PP3

SCK1/PWM2/KWP2/PP2

DDA

MOSI1/PWM1/KWP1/PP1

MISO1/PWM0/KWP0/PP0

PAD15/AN15

PAD07/AN07

PAD14/AN14

PAD06/AN06

PAD13/AN13

PAD05/AN05

PAD12/AN12

PAD04/AN04

PAD11/AN11

PAD03/AN03

PAD10/AN10

PAD02/AN02

PAD09/AN09

PAD01/AN01

PAD08/AN08

PAD00/AN00

PK3

PK2

PK1

PK0

IOC0/PT0

IOC1/PT1

IOC2/PT2

IOC3/PT3

VDD1

MC9S12XD-Family

112-Pin LQFP

VSS1

IOC4/PT4

IOC5/PT5

IOC6/PT6

IOC7/PT7

PK5

Pins shown in BOLD are not available on the

80-Pin QFP package option

SS2

PK4

DD2

TXD2/KWJ1/PJ1

CS3/RXD2/KWJ0/PJ0

MODC/BKGD

PB0

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

PB1

PB2

PB3

PB4

Figure 1-6. MC9S12XD-Family Pin Assignments 112-Pin LQFP Package

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

SS1/PWM3/KWP3/PP3

SCK1/PWM2/KWP2/PP2

MOSI1/PWM1/KWP1/PP1

MISO1/PWM0/KWP0/PP0

IOC0/PT0

DDA

PAD07/AN07

PAD06/AN06

PAD05/AN05

PAD04/AN04

PAD03/AN03

PAD02/AN02

PAD01/AN01

PAD00/AN00

IOC1/PT1

IOC2/PT2

IOC3/PT3

DD1

SS1

MC9S12XD-Family

80-Pin QFP

IOC4/PT4

IOC5/PT5

IOC6/PT6

IOC7/PT7

MODC/BKGD

PB0

SS2

DD2

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

PB1

PB2

PB3

PB4

Figure 1-7. MC9S12XD-Family Pin Assignments 80-Pin QFP Package

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

1.2.2

Signal Properties Summary

Table 1-3 summarizes the pin functionality.

Table 1-3. Signal Properties Summary (Sheet 1 of 4)

Internal Pull

Resistor

Name

Power

Supply

Description

Reset

Function 1 Function 2 Function 3 Function 4 Function 5

CTRL

State

EXTAL

XTAL

—

Oscillator pins

DDPLL

RESET

TEST

PULLUP

External reset

DDR

N.A.

RESET pin DOWN Test input

PUCR

Voltage regulator enable

Input

REGEN

DDX

XFC

—

PLL loop ﬁlter

DDPLL

BKGD

MODC

Always on

Background debug

DDR

PAD[23:08] AN[23:8]

PER0

AD1/

PER1

AD1

Disabled Port AD inputs of ATD1,

analog inputs of ATD1

DDA

PAD[07:00]

AN[7:0]

—

PER1

AD0

Disabled Port AD inputs of ATD0,

analog inputs of ATD0

DDA

DDR

PA[7:0] ADDR[15:8] IVD[15:8]

PUCR

Disabled Port A I/O, address bus,

internal visibility data

PB[7:1]

PB0

ADDR[7:1]

ADDR0

IVD[7:0]

UDS

Disabled Port B I/O, address bus,

internal visibility data

Disabled Port B I/O, address bus,

upper data strobe

PC[7:0]

PD[7:0]

PE7

DATA[15:8]

DATA[7:0]

ECLKX2

—

PUCR

Disabled Port C I/O, data bus

Disabled Port D I/O, data bus

DDR

XCLKS

Port E I/O, system clock

output, clock select

PE6

PE5

TAGHI

MODB

MODA

—

While RESET

pin is low: down

Port E I/O, tag high, mode

input

DDR

TAGLO

While RESET

pin is low: down

Port E I/O, read enable,

mode input, tag low input

PE4

PE3

ECLK

—

PUCR

Port E I/O, bus clock output

DDR

LSTRB

LDS

EROMCTL

Port E I/O, low byte data

strobe, EROMON control

DDR

PE2

PE1

R/W

IRQ

—

PUCR

Port E I/O, read/write

DDR

Port E Input, maskable

interrupt

PE0

XIRQ

—

PUCR

Port E input, non-maskable

interrupt

DDR

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

Table 1-3. Signal Properties Summary (Sheet 2 of 4)

Internal Pull

Resistor

Name

Power

Supply

Description

Reset

State

Function 1 Function 2 Function 3 Function 4 Function 5

CTRL

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

PJ7

KWH7

KWH6

KWH5

KWH4

KWH3

KWH2

KWH1

KWH0

KWJ7

SS2

SCK2

TXD5

RXD5

TXD4

RXD4

—

PERH/PPSH Disabled Port H I/O, interrupt, SS of

SPI2, TXD of SCI5

DDR

DDX

—

PERH/

PPSH

Disabled Port H I/O, interrupt, SCK of

SPI2, RXD of SCI5

MOSI2

MISO2

SS1

—

PERH/

PPSH

Disabled Port H I/O, interrupt, MOSI

of SPI2, TXD of SCI4

—

PERH/PPSH Disabled Port H I/O, interrupt, MISO

of SPI2, RXD of SCI4

PERH/PPSH Disabled Port H I/O, interrupt, SS of

SPI1

SCK1

—

PERH/PPSH Disabled Port H I/O, interrupt, SCK of

SPI1

MOSI1

MISO1

TXCAN4

—

PERH/PPSH Disabled Port H I/O, interrupt, MOSI

of SPI1

—

PERH/PPSH Disabled Port H I/O, interrupt, MISO

of SPI1

SCL0

TXCAN0

PERJ/

PPSJ

Port J I/O, interrupt, TX of

CAN4, SCL of IIC0, TX of

CAN0

PJ6

KWJ6

RXCAN4

SDA0

RXCAN0

PERJ/

PPSJ

Port J I/O, interrupt, RX of

CAN4, SDA of IIC0, RX of

CAN0

DDX

PJ5

PJ4

KWJ5

KWJ4

KWJ2

KWJ1

KWJ0

EWAIT

SCL1

SDA1

CS2

CS0

—

PERJ/

PPSJ

Port J I/O, interrupt, SCL of

IIC1, chip select 2

DDX

PERJ/

PPSJ

Port J I/O, interrupt, SDA of

IIC1, chip select 0

PJ2

CS1

PERJ/

PPSJ

Port J I/O, interrupt, chip

select 1

PJ1

TXD2

—

PERJ/

PPSJ

Port J I/O, interrupt, TXD of

SCI2

PJ0

RXD2

CS3

—

PERJ/

PPSJ

Port J I/O, interrupt, RXD of

SCI2

PK7

ROMCTL

ACC[2:0]

PUCR

Port K I/O, EWAIT input,

ROM on control

PK[6:4]

ADDR

[22:20]

—

PUCR

Port K I/O, extended

addresses, access source

for external access

PK3

PK2

PK1

ADDR19

ADDR18

ADDR17

IQSTAT3

IQSTAT2

IQSTAT1

—

PUCR

Extended address, PIPE

status

DDX

Extended address, PIPE

status

Extended address, PIPE

status

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

Table 1-3. Signal Properties Summary (Sheet 3 of 4)

Internal Pull

Resistor

Name

Power

Supply

Description

Reset

Function 1 Function 2 Function 3 Function 4 Function 5

CTRL

State

PK0

PM7

PM6

PM5

PM4

PM3

PM2

ADDR16

TXCAN3

RXCAN3

TXCAN2

RXCAN2

TXCAN1

RXCAN1

IQSTAT0

TXD3

—

PUCR

Extended address, PIPE

status

DDX

TXCAN4

RXCAN4

TXCAN4

RXCAN4

—

PERM/

PPSM

Disabled Port M I/O, TX of CAN3 and

CAN4, TXD of SCI3

RXD3

—

PERM/PPSM Disabled Port M I/O RX of CAN3 and

CAN4, RXD of SCI3

TXCAN0

RXCAN0

TXCAN0

RXCAN0

SCK0

MOSI0

SS0

PERM/PPSM Disabled Port M I/OCAN0, CAN2,

CAN4, SCK of SPI0

PERM/PPSM Disabled Port M I/O, CAN0, CAN2,

CAN4, MOSI of SPI0

PERM/PPSM Disabled Port M I/O TX of CAN1,

CAN0, SS of SPI0

—

MISO0

PERM/PPSM Disabled Port M I/O, RX of CAN1,

CAN0, MISO of SPI0

PM1

PM0

PP7

TXCAN0

RXCAN0

KWP7

—

PERM/PPSM Disabled Port M I/O, TX of CAN0

PERM/PPSM Disabled Port M I/O, RX of CAN0

DDX

PWM7

SCK2

PERP/

PPSP

Disabled Port P I/O, interrupt, channel

of PWM, SCK of SPI2

PP6

PP5

PP4

PP3

PP2

PP1

PP0

PS7

PS6

PS5

PS4

KWP6

KWP5

KWP4

KWP3

KWP2

KWP1

KWP0

SS0

PWM6

PWM5

PWM4

PWM3

PWM2

PWM1

PWM0

—

SS2

MOSI2

MISO2

SS1

—

PERP/

PPSP

Disabled Port P I/O, interrupt, channel

6 of PWM, SS of SPI2

DDX

PERP/

PPSP

Disabled Port P I/O, interrupt, channel

5 of PWM, MOSI of SPI2

PERP/

PPSP

Disabled Port P I/O, interrupt, channel

4 of PWM, MISO2 of SPI2

PERP/

PPSP

Disabled Port P I/O, interrupt, channel

3 of PWM, SS of SPI1

SCK1

MOSI1

MISO1

—

PERP/

PPSP

Disabled Port P I/O, interrupt, channel

2 of PWM, SCK of SPI1

PERP/

PPSP

Disabled Port P I/O, interrupt, channel

1 of PWM, MOSI of SPI1

PERP/

PPSP

Disabled Port P I/O, interrupt, channel

0 of PWM, MISO2 of SPI1

PERS/

PPSS

Port S I/O, SS of SPI0

Port S I/O, SCK of SPI0

Port S I/O, MOSI of SPI0

Port S I/O, MISO of SPI0

SCK0

MOSI0

MISO0

—

PERS/

PPSS

—

PERS/

PPSS

—

PERS/

PPSS

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

Table 1-3. Signal Properties Summary (Sheet 4 of 4)

Internal Pull

Resistor

Name

Power

Supply

Description

Reset

Function 1 Function 2 Function 3 Function 4 Function 5

CTRL

State

PS3

PS2

TXD1

RXD1

—

PERS/

PPSS

Port S I/O, TXD of SCI1

Port S I/O, RXD of SCI1

Port S I/O, TXD of SCI0

Port S I/O, RXD of SCI0

DDX

PERS/

PPSS

PS1

TXD0

PERS/

PPSS

PS0

RXD0

PERS/

PPSS

PT[7:0]

IOC[7:0]

PERT/

PPST

Disabled Port T I/O, timer channels

NOTE

For devices assembled in 80-pin and 112-pin packages all non-bonded out

pins should be conﬁgured as outputs after reset in order to avoid current

drawn from ﬂoating inputs. Refer to Table 1-3 for affected pins.

1.2.3

Detailed Signal Descriptions

EXTAL, XTAL — Oscillator Pins

1.2.3.1

EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived

from the EXTAL input frequency. XTAL is the crystal output.

1.2.3.2

RESET — External Reset Pin

The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a

known start-up state, and an output when an internal MCU function causes a reset.The RESET pin has an

internal pullup device.

1.2.3.3

TEST — Test Pin

This input only pin is reserved for test. This pin has a pulldown device.

NOTE

The TEST pin must be tied to V in all applications.

1.2.3.4

— Voltage Regulator Enable Pin

REGEN

This input only pin enables or disables the on-chip voltage regulator. The input has a pullup device.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

1.2.3.5

XFC — PLL Loop Filter Pin

Please ask your Freescale representative for the interactive application note to compute PLL loop ﬁlter

elements. Any current leakage on this pin must be avoided.

DDPLL

MCU

XFC

Figure 1-8. PLL Loop Filter Connections

1.2.3.6

BKGD / MODC — Background Debug and Mode Pin

The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It

is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit

at the rising edge of RESET. The BKGD pin has a pullup device.

1.2.3.7

PAD[23:8] / AN[23:8] — Port AD Input Pins of ATD1

PAD[23:8] are general-purpose input or output pins and analog inputs AN[23:8] of the analog-to-digital

converter ATD1.

1.2.3.8

PAD[7:0] / AN[7:0] — Port AD Input Pins of ATD0

PAD[7:0] are general-purpose input or output pins and analog inputs AN[7:0] of the analog-to-digital

converter ATD0.

1.2.3.9

PA[7:0] / ADDR[15:8] / IVD[15:8] — Port A I/O Pins

PA[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are

used for the external address bus. In MCU emulation modes of operation, these pins are used for external

address bus and internal visibility read data.

1.2.3.10 PB[7:1] / ADDR[7:1] / IVD[7:1] — Port B I/O Pins

PB[7:1] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are

used for the external address bus. In MCU emulation modes of operation, these pins are used for external

address bus and internal visibility read data.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 1 Device Overview (MC9S12XDP512V2)

1.2.3.11 PB0 / ADDR0 / UDS / IVD[0] — Port B I/O Pin 0

PB0 is a general-purpose input or output pin. In MCU expanded modes of operation, this pin is used for

the external address bus ADDR0 or as upper data strobe signal. In MCU emulation modes of operation,

this pin is used for external address bus ADDR0 and internal visibility read data IVD0.

1.2.3.12 PC[7:0] / DATA [15:8] — Port C I/O Pins

PC[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are

used for the external data bus.

The input voltage thresholds for PC[7:0] can be conﬁgured to reduced levels, to allow data from an external

3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage thresholds for PC[7:0] are

conﬁgured to reduced levels out of reset in expanded and emulation modes. The input voltage thresholds

for PC[7:0] are conﬁgured to 5-V levels out of reset in normal modes.

1.2.3.13 PD[7:0] / DATA [7:0] — Port D I/O Pins

PD[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are

used for the external data bus.

The input voltage thresholds for PD[7:0] can be conﬁgured to reduced levels, to allow data from an

external 3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage thresholds for

PD[7:0] are conﬁgured to reduced levels out of reset in expanded and emulation modes. The input voltage

thresholds for PC[7:0] are conﬁgured to 5-V levels out of reset in normal modes.

1.2.3.14 PE7 / ECLKX2 / XCLKS — Port E I/O Pin 7

PE7 is a general-purpose input or output pin. The XCLKS is an input signal which controls whether a

crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether

full swing Pierce oscillator/external clock circuitry is used.

The XCLKS signal selects the oscillator conﬁguration during reset low phase while a clock quality check

is ongoing. This is the case for:

•

Power on reset or low-voltage reset

Clock monitor reset

Any reset while in self-clock mode or full stop mode

The selected oscillator conﬁguration is frozen with the rising edge of reset.

The pin can be conﬁgured to drive the internal system clock ECLKX2.

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EXTAL

MCU

Crystal or

Ceramic Resonator

XTAL

SSPLL

Figure 1-9. Loop Controlled Pierce Oscillator Connections (PE7 = 1)

EXTAL

MCU

Crystal or

Ceramic Resonator

XTAL

SSPLL

Figure 1-10. Full Swing Pierce Oscillator Connections (PE7 = 0)

CMOS-Compatible

External Oscillator

EXTAL

MCU

XTAL

Not Connected

Figure 1-11. External Clock Connections (PE7 = 0)

1.2.3.15 PE6 / MODB / TAGHI — Port E I/O Pin 6

PE6 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset.

The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is an input with a

pull-down device which is only active when RESET is low. TAGHI is used to tag the high half of the

instruction word being read into the instruction queue.

The input voltage threshold for PE6 can be conﬁgured to reduced levels, to allow data from an external

3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage threshold for PE6 is

conﬁgured to reduced levels out of reset in expanded and emulation modes.

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1.2.3.16 PE5 / MODA / TAGLO / RE — Port E I/O Pin 5

PE5 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset.

The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the

read enable RE output. This pin is an input with a pull-down device which is only active when RESET is

low. TAGLO is used to tag the low half of the instruction word being read into the instruction queue.

The input voltage threshold for PE5 can be conﬁgured to reduced levels, to allow data from an external

3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage threshold for PE5 is

conﬁgured to reduced levels out of reset in expanded and emulation modes.

1.2.3.17 PE4 / ECLK — Port E I/O Pin 4

PE4 is a general-purpose input or output pin. It can be conﬁgured to drive the internal bus clock ECLK.

ECLK can be used as a timing reference.

1.2.3.18 PE3 / LSTRB / LDS / EROMCTL— Port E I/O Pin 3

PE3 is a general-purpose input or output pin. In MCU expanded modes of operation, LSTRB or LDS can

be used for the low byte strobe function to indicate the type of bus access. At the rising edge of RESET

the state of this pin is latched to the EROMON bit.

1.2.3.19 PE2 / R/W / WE— Port E I/O Pin 2

PE2 is a general-purpose input or output pin. In MCU expanded modes of operations, this pin drives the

read/write output signal or write enable output signal for the external bus. It indicates the direction of data

on the external bus.

1.2.3.20 PE1 / IRQ — Port E Input Pin 1

PE1 is a general-purpose input pin and the maskable interrupt request input that provides a means of

applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode.

1.2.3.21 PE0 / XIRQ — Port E Input Pin 0

PE0 is a general-purpose input pin and the non-maskable interrupt request input that provides a means of

applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode.

1.2.3.22 PH7 / KWH7 / SS2 / TXD5 — Port H I/O Pin 7

PH7 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the

MCU to exit stop or wait mode. It can be conﬁgured as slave select pin SS of the serial peripheral

interface 2 (SPI2). It can be conﬁgured as the transmit pin TXD of serial communication interface 5

(SCI5).

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1.2.3.23 PH6 / KWH6 / SCK2 / RXD5 — Port H I/O Pin 6

PH6 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the

MCU to exit stop or wait mode. It can be conﬁgured as serial clock pin SCK of the serial peripheral

interface 2 (SPI2). It can be conﬁgured as the receive pin (RXD) of serial communication interface 5

(SCI5).

1.2.3.24 PH5 / KWH5 / MOSI2 / TXD4 — Port H I/O Pin 5

PH5 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the

MCU to exit stop or wait mode. It can be conﬁgured as master output (during master mode) or slave input

pin (during slave mode) MOSI of the serial peripheral interface 2 (SPI2). It can be conﬁgured as the

transmit pin TXD of serial communication interface 4 (SCI4).

1.2.3.25 PH4 / KWH4 / MISO2 / RXD4 — Port H I/O Pin 4

PH4 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the

MCU to exit stop or wait mode. It can be conﬁgured as master input (during master mode) or slave output

(during slave mode) pin MISO of the serial peripheral interface 2 (SPI2). It can be conﬁgured as the receive

pin RXD of serial communication interface 4 (SCI4).

1.2.3.26 PH3 / KWH3 / SS1 — Port H I/O Pin 3

PH3 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the

MCU to exit stop or wait mode. It can be conﬁgured as slave select pin SS of the serial peripheral

interface 1 (SPI1).

1.2.3.27 PH2 / KWH2 / SCK1 — Port H I/O Pin 2

PH2 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the

MCU to exit stop or wait mode. It can be conﬁgured as serial clock pin SCK of the serial peripheral

interface 1 (SPI1).

1.2.3.28 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1

PH1 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the

MCU to exit stop or wait mode. It can be conﬁgured as master output (during master mode) or slave input

pin (during slave mode) MOSI of the serial peripheral interface 1 (SPI1).

1.2.3.29 PH0 / KWH0 / MISO1 — Port H I/O Pin 0

PH0 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the

MCU to exit stop or wait mode. It can be conﬁgured as master input (during master mode) or slave output

(during slave mode) pin MISO of the serial peripheral interface 1 (SPI1).

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1.2.3.30 PJ7 / KWJ7 / TXCAN4 / SCL0 / TXCAN0— PORT J I/O Pin 7

PJ7 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the MCU

to exit stop or wait mode. It can be conﬁgured as the transmit pin TXCAN for the scalable controller area

network controller 0 or 4 (CAN0 or CAN4) or as the serial clock pin SCL of the IIC0 module.

1.2.3.31 PJ6 / KWJ6 / RXCAN4 / SDA0 / RXCAN0 — PORT J I/O Pin 6

PJ6 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the MCU

to exit stop or wait mode. It can be conﬁgured as the receive pin RXCAN for the scalable controller area

network controller 0 or 4 (CAN0 or CAN4) or as the serial data pin SDA of the IIC0 module.

1.2.3.32 PJ5 / KWJ5 / SCL1 / CS2 — PORT J I/O Pin 5

PJ5 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the MCU

to exit stop or wait mode. It can be conﬁgured as the serial clock pin SCL of the IIC1 module. It can be

conﬁgured to provide a chip-select output.

1.2.3.33 PJ4 / KWJ4 / SDA1 / CS0 — PORT J I/O Pin 4

PJ4 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the MCU

to exit stop or wait mode. It can be conﬁgured as the serial data pin SDA of the IIC1 module. It can be

conﬁgured to provide a chip-select output.

1.2.3.34 PJ2 / KWJ2 / CS1 — PORT J I/O Pin 2

PJ2 is a general-purpose input or output pins. It can be conﬁgured to generate an interrupt causing the

MCU to exit stop or wait mode. It can be conﬁgured to provide a chip-select output.

1.2.3.35 PJ1 / KWJ1 / TXD2 — PORT J I/O Pin 1

PJ1 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the MCU

to exit stop or wait mode. It can be conﬁgured as the transmit pin TXD of the serial communication

interface 2 (SCI2).

1.2.3.36 PJ0 / KWJ0 / RXD2 / CS3 — PORT J I/O Pin 0

PJ0 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the MCU

to exit stop or wait mode. It can be conﬁgured as the receive pin RXD of the serial communication interface

2 (SCI2).It can be conﬁgured to provide a chip-select output.

1.2.3.37 PK7 / EWAIT / ROMCTL — Port K I/O Pin 7

PK7 is a general-purpose input or output pin. During MCU emulation modes and normal expanded modes

of operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMCTL). At

the rising edge of RESET, the state of this pin is latched to the ROMON bit. The EWAIT input signal

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maintains the external bus access until the external device is ready to capture data (write) or provide data

(read).

The input voltage threshold for PK7 can be conﬁgured to reduced levels, to allow data from an external

3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage threshold for PK7 is

conﬁgured to reduced levels out of reset in expanded and emulation modes.

1.2.3.38 PK[6:4] / ADDR[22:20] / ACC[2:0] — Port K I/O Pin [6:4]

PK[6:4] are general-purpose input or output pins. During MCU expanded modes of operation, the

ACC[2:0] signals are used to indicate the access source of the bus cycle. This pins also provide the

expanded addresses ADDR[22:20] for the external bus. In Emulation modes ACC[2:0] is available and is

time multiplexed with the high addresses

1.2.3.39 PK[3:0] / ADDR[19:16] / IQSTAT[3:0] — Port K I/O Pins [3:0]

PK3-PK0 are general-purpose input or output pins. In MCU expanded modes of operation, these pins

provide the expanded address ADDR[19:16] for the external bus and carry instruction pipe information.

1.2.3.40 PM7 / TXCAN3 / TXCAN4 / TXD3 — Port M I/O Pin 7

PM7 is a general-purpose input or output pin. It can be conﬁgured as the transmit pin TXCAN of the

scalable controller area network controller 3 or 4 (CAN3 or CAN4). PM7 can be conﬁgured as the transmit

pin TXD3 of the serial communication interface 3 (SCI3).

1.2.3.41 PM6 / RXCAN3 / RXCAN4 / RXD3 — Port M I/O Pin 6

PM6 is a general-purpose input or output pin. It can be conﬁgured as the receive pin RXCAN of the

scalable controller area network controller 3 or 4 (CAN3 or CAN4). PM6 can be conﬁgured as the receive

pin RXD3 of the serial communication interface 3 (SCI3).

1.2.3.42 PM5 / TXCAN0 / TXCAN2 / TXCAN4 / SCK0 — Port M I/O Pin 5

PM5 is a general-purpose input or output pin. It can be conﬁgured as the transmit pin TXCAN of the

scalable controller area network controllers 0, 2 or 4 (CAN0, CAN2, or CAN4). It can be conﬁgured as

the serial clock pin SCK of the serial peripheral interface 0 (SPI0).

1.2.3.43 PM4 / RXCAN0 / RXCAN2 / RXCAN4 / MOSI0 — Port M I/O Pin 4

PM4 is a general-purpose input or output pin. It can be conﬁgured as the receive pin RXCAN of the

scalable controller area network controllers 0, 2, or 4 (CAN0, CAN2, or CAN4). It can be conﬁgured as

the master output (during master mode) or slave input pin (during slave mode) MOSI for the serial

peripheral interface 0 (SPI0).

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1.2.3.44 PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3

PM3 is a general-purpose input or output pin. It can be conﬁgured as the transmit pin TXCAN of the

scalable controller area network controllers 1 or 0 (CAN1 or CAN0). It can be conﬁgured as the slave

select pin SS of the serial peripheral interface 0 (SPI0).

1.2.3.45 PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2

PM2 is a general-purpose input or output pin. It can be conﬁgured as the receive pin RXCAN of the

scalable controller area network controllers 1 or 0 (CAN1 or CAN0). It can be conﬁgured as the master

input (during master mode) or slave output pin (during slave mode) MISO for the serial peripheral

interface 0 (SPI0).

1.2.3.46 PM1 / TXCAN0 — Port M I/O Pin 1

PM1 is a general-purpose input or output pin. It can be conﬁgured as the transmit pin TXCAN of the

scalable controller area network controller 0 (CAN0).

1.2.3.47 PM0 / RXCAN0 — Port M I/O Pin 0

PM0 is a general-purpose input or output pin. It can be conﬁgured as the receive pin RXCAN of the

scalable controller area network controller 0 (CAN0).

1.2.3.48 PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7

PP7 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the MCU

to exit stop or wait mode. It can be conﬁgured as pulse width modulator (PWM) channel 7 output. It can

be conﬁgured as serial clock pin SCK of the serial peripheral interface 2 (SPI2).

1.2.3.49 PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6

PP6 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the MCU

to exit stop or wait mode. It can be conﬁgured as pulse width modulator (PWM) channel 6 output. It can

be conﬁgured as slave select pin SS of the serial peripheral interface 2 (SPI2).

1.2.3.50 PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5

PP5 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the MCU

to exit stop or wait mode. It can be conﬁgured as pulse width modulator (PWM) channel 5 output. It can

be conﬁgured as master output (during master mode) or slave input pin (during slave mode) MOSI of the

serial peripheral interface 2 (SPI2).

1.2.3.51 PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4

PP4 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the MCU

to exit stop or wait mode. It can be conﬁgured as pulse width modulator (PWM) channel 4 output. It can

MC9S12XDP512 Data Sheet, Rev. 2.11

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be conﬁgured as master input (during master mode) or slave output (during slave mode) pin MISO of the

serial peripheral interface 2 (SPI2).

1.2.3.52 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3

PP3 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the MCU

to exit stop or wait mode. It can be conﬁgured as pulse width modulator (PWM) channel 3 output. It can

be conﬁgured as slave select pin SS of the serial peripheral interface 1 (SPI1).

1.2.3.53 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2

PP2 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the MCU

to exit stop or wait mode. It can be conﬁgured as pulse width modulator (PWM) channel 2 output. It can

be conﬁgured as serial clock pin SCK of the serial peripheral interface 1 (SPI1).

1.2.3.54 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1

PP1 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the MCU

to exit stop or wait mode. It can be conﬁgured as pulse width modulator (PWM) channel 1 output. It can

be conﬁgured as master output (during master mode) or slave input pin (during slave mode) MOSI of the

serial peripheral interface 1 (SPI1).

1.2.3.55 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0

PP0 is a general-purpose input or output pin. It can be conﬁgured to generate an interrupt causing the MCU

to exit stop or wait mode. It can be conﬁgured as pulse width modulator (PWM) channel 0 output. It can

be conﬁgured as master input (during master mode) or slave output (during slave mode) pin MISO of the

serial peripheral interface 1 (SPI1).

1.2.3.56 PS7 / SS0 — Port S I/O Pin 7

PS7 is a general-purpose input or output pin. It can be conﬁgured as the slave select pin SS of the serial

peripheral interface 0 (SPI0).

1.2.3.57 PS6 / SCK0 — Port S I/O Pin 6

PS6 is a general-purpose input or output pin. It can be conﬁgured as the serial clock pin SCK of the serial

peripheral interface 0 (SPI0).

1.2.3.58 PS5 / MOSI0 — Port S I/O Pin 5

PS5 is a general-purpose input or output pin. It can be conﬁgured as master output (during master mode)

or slave input pin (during slave mode) MOSI of the serial peripheral interface 0 (SPI0).

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1.2.3.59 PS4 / MISO0 — Port S I/O Pin 4

PS4 is a general-purpose input or output pin. It can be conﬁgured as master input (during master mode) or

slave output pin (during slave mode) MOSI of the serial peripheral interface 0 (SPI0).

1.2.3.60 PS3 / TXD1 — Port S I/O Pin 3

PS3 is a general-purpose input or output pin. It can be conﬁgured as the transmit pin TXD of serial

communication interface 1 (SCI1).

1.2.3.61 PS2 / RXD1 — Port S I/O Pin 2

PS2 is a general-purpose input or output pin. It can be conﬁgured as the receive pin RXD of serial

communication interface 1 (SCI1).

1.2.3.62 PS1 / TXD0 — Port S I/O Pin 1

PS1 is a general-purpose input or output pin. It can be conﬁgured as the transmit pin TXD of serial

communication interface 0 (SCI0).

1.2.3.63 PS0 / RXD0 — Port S I/O Pin 0

PS0 is a general-purpose input or output pin. It can be conﬁgured as the receive pin RXD of serial

communication interface 0 (SCI0).

1.2.3.64 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0]

PT[7:0] are general-purpose input or output pins. They can be conﬁgured as input capture or output

compare pins IOC[7:0] of the enhanced capture timer (ECT).

1.2.4

Power Supply Pins

MC9S12XDP512 power and ground pins are described below.

NOTE

All V pins must be connected together in the application.

1.2.4.1

, V

— Power and Ground Pins for I/O Drivers

DDX1

DDX2

SSX1 SSX2

External power and ground for I/O drivers. Because fast signal transitions place high, short-duration

current demands on the power supply, use bypass capacitors with high-frequency characteristics and place

them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are

loaded.

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1.2.4.2

, V

, V — Power and Ground Pins for I/O Drivers

SSR2

DDR1

DDR2

SSR1

and for Internal Voltage Regulator

External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal

transitions place high, short-duration current demands on the power supply, use bypass capacitors with

high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements

depend on how heavily the MCU pins are loaded.

1.2.4.3

, V

— Core Power Pins

SS2

DD1

DD2

SS1

Power is supplied to the MCU through V and V . Because fast signal transitions place high,

short-duration current demands on the power supply, use bypass capacitors with high-frequency

characteristics and place them as close to the MCU as possible. This 2.5-V supply is derived from the

internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is

turned off, if V

is tied to ground.

REGEN

NOTE

No load allowed except for bypass capacitors.

1.2.4.4

, V

— Power Supply Pins for ATD and V

SSA REG

DDA

, V

are the power supply and ground input pins for the voltage regulator and the analog-to-digital

DDA SSA

converters.

1.2.4.5

V , V — ATD Reference Voltage Input Pins

RH RL

and V are the reference voltage input pins for the analog-to-digital converter.

1.2.4.6

, V

— Power Supply Pins for PLL

SSPLL

DDPLL

Provides operating voltage and ground for the oscillator and the phased-locked loop. This allows the

supply voltage to the oscillator and PLL to be bypassed independently. This 2.5-V voltage is generated by

the internal voltage regulator.

NOTE

No load allowed except for bypass capacitors.

1.2.4.7

— On--Chip Voltage Regulator Enable

REGEN

Enables the internal 5 V to 2.5 V voltage regulator. If this pin is tied low, V

supplied externally.

and V

must be

DD1,2

DDPLL

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Table 1-4. MC9S12XDP512 Power and Ground Connection Summary

Pin Number

Nominal

Voltage

Mnemonic

Description

144-Pin

LQFP

112-Pin

LQFP

80-Pin

QFP

15, 87

16, 88

13, 65

14, 66

9, 49

10, 50

2.5 V

Internal power and ground generated by

internal regulator

DD1, 2

SS1, 2

5.0 V

0 V

External power and ground, supply to pin

drivers and internal voltage regulator

DDR1

SSR1

DDX1

139

138

107

106

N.A.

5.0 V

0 V

External power and ground, supply to pin

drivers

SSX1

N.A.

5.0 V

0 V

External power and ground, supply to pin

drivers

DDX2

SSX2

DDR2

5.0 V

0 V

External power and ground, supply to pin

drivers

SSR2

107

110

5.0 V

0 V

Operating voltage and ground for the

analog-to-digital converters and the

reference for the internal voltage regulator,

allows the supply voltage to the A/D to be

bypassed independently.

DDA

SSA

109

108

0 V

5.0 V

2.5 V

0 V

Reference voltages for the analog-to-digital

converter.

Provides operating voltage and ground for

the phased-locked loop. This allows the

supply voltage to the PLL to be bypassed

independently. Internal power and ground

generated by internal regulator.

DDPLL

SSPLL

127

N.A.

Internal voltage regulator enable/disable

REGEN

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1.3

System Clock Description

The clock and reset generator module (CRG) provides the internal clock signals for the core and all

peripheral modules. Figure 1-12 shows the clock connections from the CRG to all modules.

Consult the CRG Block User Guide for details on clock generation.

SCI0 . . SCI 5

CAN0 . . CAN4

SPI0 . . SPI2

IIC0 & IIC1

ATD0 & ATD1

Bus Clock

PIT

EXTAL

Oscillator Clock

ECT

CRG

PIM

XTAL

Core Clock

RAM

S12X

XGATE

FLASH

EEPROM

Figure 1-12. Clock Connections

The MCU’s system clock can be supplied in several ways enabling a range of system operating frequencies

to be supported:

•

The on-chip phase locked loop (PLL)

the PLL self clocking

the oscillator

The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and

bus clock. As shown in Figure 1-12, this system clocks are used throughout the MCU to drive the core, the

memories, and the peripherals.

MC9S12XDP512 Data Sheet, Rev. 2.11

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The program Flash memory and the EEPROM are supplied by the bus clock and the oscillator clock.The

oscillator clock is used as a time base to derive the program and erase times for the NVM’s. Consult the

FTX512k4 Block Guide and the EETX4K Block Guide for more details on the operation of the NVM’s.

The CAN modules may be conﬁgured to have their clock sources derived either from the bus clock or

directly from the oscillator clock. This allows the user to select its clock based on the required jitter

performance. Consult MSCAN block description for more details on the operation and conﬁguration of

the CAN blocks.

In order to ensure the presence of the clock the MCU includes an on-chip clock monitor connected to the

output of the oscillator. The clock monitor can be conﬁgured to invoke the PLL self-clocking mode or to

generate a system reset if it is allowed to time out as a result of no oscillator clock being present.

In addition to the clock monitor, the MCU also provides a clock quality checker which performs a more

accurate check of the clock. The clock quality checker counts a predetermined number of clock edges

within a deﬁned time window to insure that the clock is running. The checker can be invoked following

speciﬁc events such as on wake-up or clock monitor failure.

1.4

Chip Conﬁguration Summary

The MCU can operate in six different modes. The different modes, the state of ROMCTL and EROMCTL

signal on rising edge of RESET, and the security state of the MCU affects the following device

characteristics:

•

External bus interface conﬁguration

Flash in memory map, or not

Debug features enabled or disabled

The operating mode out of reset is determined by the states of the MODC, MODB, and MODA signals

during reset (see Table 1-5). The MODC, MODB, and MODA bits in the MODE register show the current

operating mode and provide limited mode switching during operation. The states of the MODC, MODB,

and MODA signals are latched into these bits on the rising edge of RESET.

In normal expanded mode and in emulation modes the ROMON bit and the EROMON bit in the

MMCCTL1 register deﬁnes if the on chip ﬂash memory is the memory map, or not. (See Table 1-5.) For

a detailed description of the ROMON and EROMON bits refer to the S12X_MMC Block Guide.

The state of the ROMCTL signal is latched into the ROMON bit in the MMCCTL1 register on the rising

edge of RESET. The state of the EROMCTL signal is latched into the EROMON bit in the MISC register

on the rising edge of RESET.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 1 Device Overview (MC9S12XDP512V2)

Table 1-5. Chip Modes and Data Sources

BKGD =

MODC

PE6 =

MODB

PE5 =

MODA

PK7 =

ROMCTL

PE3 =

EROMCTL

Chip Modes

Data Source

Normal single chip

Special single chip

Emulation single chip

Internal

Emulation memory

Internal Flash

Normal expanded

External application

Internal Flash

Emulation expanded

External application

Emulation memory

Internal Flash

Special test

External application

Internal Flash

Internal means resources inside the MCU are read/written.

Internal Flash means Flash resources inside the MCU are read/written.

Emulation memory means resources inside the emulator are read/written (PRU registers, Flash replacement, RAM, EEPROM,

and register space are always considered internal).

External application means resources residing outside the MCU are read/written.

The conﬁguration of the oscillator can be selected using the XCLKS signal (see Table 1-6). For a detailed

description please refer to the CRG Block Guide.

Table 1-6. Clock Selection Based on PE7

PE7 = XCLKS

Description

Full swing Pierce oscillator or external clock source selected

Loop controlled Pierce oscillator selected

The logic level on the voltage regulator enable pin V

regulator is enabled or disabled (see Table 1-7).

determines whether the on-chip voltage

REGEN

Table 1-7. Voltage Regulator VREGEN

Description

REGEN

Internal voltage regulator enabled

Internal voltage regulator disabled, V

supplied externally

and V

must be

DDPLL

DD1,2

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 1 Device Overview (MC9S12XDP512V2)

1.5

Modes of Operation

1.5.1

User Modes

1.5.1.1

Normal Expanded Mode

Ports K, A, and B are conﬁgured as a 23-bit address bus, ports C and D are conﬁgured as a 16-bit data bus,

and port E provides bus control and status signals. This mode allows 16-bit external memory and

peripheral devices to be interfaced to the system. The fastest external bus rate is divide by 2 from the

internal bus rate.

1.5.1.2

Normal Single-Chip Mode

There is no external bus in this mode. The processor program is executed from internal memory. Ports A,

B,C,D, K, and most pins of port E are available as general-purpose I/O.

1.5.1.3

Special Single-Chip Mode

This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The

background debug module BDM is active in this mode. The CPU executes a monitor program located in

an on-chip ROM. BDM ﬁrmware is waiting for additional serial commands through the BKGD pin. There

is no external bus after reset in this mode.

1.5.1.4

Emulation of Expanded Mode

Developers use this mode for emulation systems in which the users target application is normal expanded

mode. Code is executed from external memory or from internal memory depending on the state of

ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface.

1.5.1.5

Emulation of Single-Chip Mode

Developers use this mode for emulation systems in which the user’s target application is normal

single-chip mode. Code is executed from external memory or from internal memory depending on the state

of ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface.

1.5.1.6

Special Test Mode

Freescale internal use only.

1.5.2

Low-Power Modes

The microcontroller features two main low-power modes. Consult the respective Block Guide for

information on the module behavior in system stop, system pseudo stop, and system wait mode. An

important source of information about the clock system is the Clock and Reset Generator Block Guide

(CRG).

MC9S12XDP512 Data Sheet, Rev. 2.11

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1.5.2.1

System Stop Modes

The system stop modes are entered if the CPU executes the STOP instruction and the XGATE doesn’t

execute a thread and the XGFACT bit in the XGMCTL register is cleared. Depending on the state of the

PSTP bit in the CLKSEL register the MCU goes into pseudo stop mode or full stop mode. Please refer to

CRG Block Guide. Asserting RESET, XIRQ, IRQ or any other interrupt ends the system stop modes.

1.5.2.2

Pseudo Stop Mode

In this mode the clocks are stopped but the oscillator is still running and the real time interrupt (RTI) or

watchdog (COP) submodule can stay active. Other peripherals are turned off. This mode consumes more

current than the system stop mode, but the wake up time from this mode is signiﬁcantly shorter.

1.5.2.3

Full Stop Mode

The oscillator is stopped in this mode. All clocks are switched off. All counters and dividers remain frozen.

1.5.2.4

System Wait Mode

This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will not execute

instructions. The internal CPU clock is switched off. All peripherals and the XGATE can be active in

system wait mode. For further power consumption the peripherals can individually turn off their local

clocks. Asserting RESET, XIRQ, IRQ or any other interrupt that has not been masked ends system wait

mode.

1.5.3

Freeze Mode

The enhanced capture timer, pulse width modulator, analog-to-digital converters, the periodic interrupt

timer and the XGATE module provide a software programmable option to freeze the module status during

the background debug module is active. This is useful when debugging application software. For detailed

description of the behavior of the ATD0, ATD1, ECT, PWM, XGATE and PIT when the background debug

module is active consult the corresponding Block Guides.

1.6

Resets and Interrupts

Consult the S12XCPU Block Guide for information on exception processing.

1.6.1

Vectors

Table 1-8 lists all interrupt sources and vectors in the default order of priority. The interrupt module

(S12XINT) provides an interrupt vector base register (IVBR) to relocate the vectors. Associated with each

I-bit maskable service request is a conﬁguration register. It selects if the service request is enabled, the

service request priority level and whether the service request is handled either by the S12X CPU or by the

XGATE module.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Table 1-8. Interrupt Vector Locations (Sheet 1 of 3)

XGATE

Channel ID

CCR

Mask

Vector Address

Interrupt Source

Local Enable

$FFFE

$FFFC

$FFFA

—

System reset or illegal access reset

Clock monitor reset

None

X Bit

I bit

None

PLLCTL (CME, SCME)

COP rate select

None

—

COP watchdog reset

Vector base + $F8

Vector base+ $F6

Vector base+ $F4

Vector base+ $F2

Vector base+ $F0

Vector base+ $EE

Vector base + $EC

Vector base+ $EA

Vector base+ $E8

Vector base+ $E6

Vector base+ $E4

Vector base + $E2

Vector base+ $E0

Vector base+ $DE

Vector base+ $DC

Vector base + $DA

Vector base + $D8

Vector base+ $D6

—

Unimplemented instruction trap

SWI

—

None

—

XIRQ

None

—

IRQ

IRQCR (IRQEN)

CRGINT (RTIE)

TIE (C0I)

$78

$77

$76

$75

$74

$73

$72

$71

$70

$6F

$6E

$6D

$6C

$6B

Real time interrupt

I bit

Enhanced capture timer channel 0

Enhanced capture timer channel 1

Enhanced capture timer channel 2

Enhanced capture timer channel 3

Enhanced capture timer channel 4

Enhanced capture timer channel 5

Enhanced capture timer channel 6

Enhanced capture timer channel 7

Enhanced capture timer overﬂow

Pulse accumulator A overﬂow

Pulse accumulator input edge

SPI0

I bit

TIE (C1I)

I bit

TIE (C2I)

I bit

TIE (C3I)

I bit

TIE (C4I)

I bit

TIE (C5I)

I bit

TIE (C6I)

I bit

TIE (C7I)

I bit

TSRC2 (TOF)

PACTL (PAOVI)

PACTL (PAI)

SPI0CR1 (SPIE, SPTIE)

I bit

SCI0

I bit

SCI0CR2

(TIE, TCIE, RIE, ILIE)

Vector base + $D4

$6A

SCI1

I bit

SCI1CR2

(TIE, TCIE, RIE, ILIE)

Vector base + $D2

Vector base + $D0

Vector base + $CE

Vector base + $CC

Vector base + $CA

Vector base + $C8

Vector base + $C6

Vector base + $C4

Vector base + $C2

Vector base + $C0

Vector base + $BE

$69

$68

$67

$66

$65

$64

$63

$62

$61

$60

$5F

ATD0

ATD1

I bit

ATD0CTL2 (ASCIE)

ATD1CTL2 (ASCIE)

PIEJ (PIEJ7-PIEJ0)

PIEH (PIEH7-PIEH0)

MCCTL(MCZI)

Port J

Port H

Modulus down counter underﬂow

Pulse accumulator B overﬂow

CRG PLL lock

PBCTL(PBOVI)

CRGINT(LOCKIE)

CRGINT (SCMIE)

CRG self-clock mode

Reserved

IIC0 bus

SPI1

I bit

IBCR0 (IBIE)

SPI1CR1 (SPIE, SPTIE)

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 1 Device Overview (MC9S12XDP512V2)

Table 1-8. Interrupt Vector Locations (Sheet 2 of 3)

XGATE

Channel ID

CCR

Mask

Vector Address

Interrupt Source

Local Enable

Vector base + $BC

Vector base + $BA

Vector base + $B8

Vector base + $B6

Vector base + $B4

Vector base + $B2

Vector base + $B0

Vector base + $AE

Vector base + $AC

Vector base + $AA

Vector base + $A8

Vector base + $A6

Vector base + $A4

Vector base + $A2

Vector base + $A0

Vector base + $9E

Vector base+ $9C

Vector base+ $9A

Vector base + $98

Vector base + $96

Vector base + $94

Vector base + $92

Vector base + $90

Vector base + $8E

Vector base+ $8C

Vector base + $8A

$5E

$5D

$5C

$5B

$5A

$59

$58

$57

$56

$55

$54

$53

$52

$51

$50

$4F

$4E

$4D

$4C

$4B

$4A

$49

$48

$47

$46

$45

SPI2

EEPROM

I bit

SPI2CR1 (SPIE, SPTIE)

ECNFG (CCIE, CBEIE)

FCNFG (CCIE, CBEIE)

CAN0RIER (WUPIE)

FLASH

CAN0 wake-up

CAN0 errors

CAN0RIER (CSCIE, OVRIE)

CAN0RIER (RXFIE)

CAN0 receive

CAN0 transmit

CAN1 wake-up

CAN1 errors

CAN0TIER (TXEIE[2:0])

CAN1RIER (WUPIE)

CAN1RIER (CSCIE, OVRIE)

CAN1RIER (RXFIE)

CAN1 receive

CAN1 transmit

CAN2 wake-up

CAN2 errors

CAN1TIER (TXEIE[2:0])

CAN2RIER (WUPIE)

CAN2RIER (CSCIE, OVRIE)

CAN2RIER (RXFIE)

CAN2 receive

CAN2 transmit

CAN3 wake-up

CAN3 errors

CAN2TIER (TXEIE[2:0])

CAN3RIER (WUPIE)

CAN3RIER (CSCIE, OVRIE)

CAN3RIER (RXFIE)

CAN3 receive

CAN3 transmit

CAN4 wake-up

CAN4 errors

CAN3TIER (TXEIE[2:0])

CAN4RIER (WUPIE)

CAN4RIER (CSCIE, OVRIE)

CAN4RIER (RXFIE)

CAN4 receive

CAN4 transmit

Port P Interrupt

PWM emergency shutdown

SCI2

CAN4TIER (TXEIE[2:0])

PIEP (PIEP7-PIEP0)

PWMSDN (PWMIE)

SCI2CR2

(TIE, TCIE, RIE, ILIE)

Vector base + $88

Vector base + $86

Vector base + $84

$44

$43

$42

SCI3

SCI4

SCI5

I bit

SCI3CR2

(TIE, TCIE, RIE, ILIE)

SCI4CR2

(TIE, TCIE, RIE, ILIE)

SCI5CR2

(TIE, TCIE, RIE, ILIE)

Vector base + $82

Vector base + $80

$41

$40

IIC1 Bus

I bit

IBCR (IBIE)

Low-voltage interrupt (LVI)

VREGCTRL (LVIE)

MC9S12XDP512 Data Sheet, Rev. 2.11

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Table 1-8. Interrupt Vector Locations (Sheet 3 of 3)

XGATE

Channel ID

CCR

Mask

Vector Address

Interrupt Source

Local Enable

Vector base + $7E

Vector base + $7C

Vector base + $7A

Vector base + $78

Vector base + $76

Vector base + $74

Vector base + $72

Vector base + $70

Vector base + $6E

Vector base + $6C

Vector base + $6A

Vector base + $68

Vector base + $66

Vector base + $64

Vector base + $62

Vector base + $60

$3F

$3E

$3D

$3C

$3B

$3A

$39

$38

$37

$36

$35

$34

$33

$32

—

Autonomous periodical interrupt (API)

I bit

VREGAPICTRL (APIE)

Reserved

Periodic interrupt timer channel 0

Periodic interrupt timer channel 1

Periodic interrupt timer channel 2

Periodic interrupt timer channel 3

XGATE software trigger 0

XGATE software trigger 1

XGATE software trigger 2

XGATE software trigger 3

XGATE software trigger 4

XGATE software trigger 5

XGATE software trigger 6

XGATE software trigger 7

XGATE software error interrupt

S12XCPU RAM access violation

Reserved

I bit

PITINTE (PINTE0)

PITINTE (PINTE1)

PITINTE (PINTE2)

PITINTE (PINTE3)

XGMCTL (XGIE)

RAMWPC (AVIE)

—

Vector base+ $12

Vector base + $5E

Vector base + $10

—

Spurious interrupt

—

None

16 bits vector address based

For detailed description of XGATE channel ID refer to XGATE Block Guide

1.6.2

Effects of Reset

When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the

respective module Block Guides for register reset states.

1.6.2.1

I/O Pins

Refer to the PIM Block Guide for reset conﬁgurations of all peripheral module ports.

1.6.2.2

Memory

The RAM array is not initialized out of reset.

MC9S12XDP512 Data Sheet, Rev. 2.11

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1.7

COP Conﬁguration

The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge

of RESET from the Flash control register FCTL ($0107) located in the Flash EEPROM block. See

Table 1-9 and Table 1-10 for coding. The FCTL register is loaded from the Flash conﬁguration ﬁeld byte

at global address $7FFF0E during the reset sequence

NOTE

If the MCU is secured the COP timeout rate is always set to the longest

period (CR[2:0] = 111) after COP reset.

Table 1-9. Initial COP Rate Conﬁguration

NV[2:0] in

CR[2:0] in

FCTL Register

COPCTL Register

000

001

010

011

100

101

110

111

110

101

100

011

010

001

000

Table 1-10. Initial WCOP Conﬁguration

NV[3] in

WCOP in

FCTL Register

COPCTL Register

1.8

ATD0 External Trigger Input Connection

The ATD_10B8C module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG, and ETRIG3.

The external trigger allows the user to synchronize ATD conversion to external trigger events. Table 1-11

shows the connection of the external trigger inputs on MC9S12XDP512.

Table 1-11. ATD0 External Trigger Sources

External Trigger

Connectivity

Input

ETRIG0

ETRIG1

ETRIG2

ETRIG3

Pulse width modulator channel 1

Pulse width modulator channel 3

Periodic interrupt timer hardware trigger 0

Periodic interrupt timer hardware trigger 1

MC9S12XDP512 Data Sheet, Rev. 2.11

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Consult the ATD_10B8C Block Guide for information about the analog-to-digital converter module.

When the ATD_10B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.

1.9

ATD1 External Trigger Input Connection

The A T D_10B16C module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG, and ETRIG3.

The external trigger feature allows the user to synchronize ATD conversion to external trigger events.

Table 1-12 shows the connection of the external trigger inputs on MC9S12XDP512.

Table 1-12. ATD1 External Trigger Sources

External Trigger

Connectivity

Input

ETRIG0

ETRIG1

ETRIG2

ETRIG3

Pulse width modulator channel 1

Pulse width modulator channel 3

Periodic interrupt timer hardware trigger 0

Periodic interrupt timer hardware trigger 1

Consult the ATD_10B16C Block Guide for information about the analog-to-digital converter module.

When the ATD_10B16C Block Guide refers to freeze mode this is equivalent to active BDM mode.

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Chapter 2

512 Kbyte Flash Module (S12XFTX512K4V2)

2.1

Introduction

This document describes the FTX512K4 module that includes a 512K Kbyte Flash (nonvolatile) memory.

The Flash memory may be read as either bytes, aligned words or misaligned words. Read access time is

one bus cycle for bytes and aligned words, and two bus cycles for misaligned words.

The Flash memory is ideal for program and data storage for single-supply applications allowing for ﬁeld

reprogramming without requiring external voltage sources for program or erase. Program and erase

functions are controlled by a command driven interface. The Flash module supports both block erase and

sector erase. An erased bit reads 1 and a programmed bit reads 0. The high voltage required to program

and erase the Flash memory is generated internally. It is not possible to read from a Flash block while it is

being erased or programmed.

CAUTION

A Flash word must be in the erased state before being programmed.

Cumulative programming of bits within a Flash word is not allowed.

2.1.1

Glossary

Command Write Sequence — A three-step MCU instruction sequence to execute built-in algorithms

(including program and erase) on the Flash memory.

Multiple-Input Signature Register (MISR) — A Multiple-Input Signature Register is an output

response analyzer implemented using a linear feedback shift-register (LFSR). A 16-bit MISR is used to

compress data and generate a signature that is particular to the data read from a Flash block.

2.1.2

Features

•

512 Kbytes of Flash memory comprised of four 128 Kbyte blocks with each block divided into

128 sectors of 1024 bytes

•

Automated program and erase algorithm

Interrupts on Flash command completion, command buffer empty

Fast sector erase and word program operation

2-stage command pipeline for faster multi-word program times

Sector erase abort feature for critical interrupt response

Flexible protection scheme to prevent accidental program or erase

Single power supply for all Flash operations including program and erase

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512 Kbyte Flash Module (S12XFTX512K4V2)

•

Security feature to prevent unauthorized access to the Flash memory

Code integrity check using built-in data compression

2.1.3

Modes of Operation

Program, erase, erase verify, and data compress operations (please refer to Section 2.4.1, “Flash Command

Operations” for details).

2.1.4

Block Diagram

A block diagram of the Flash module is shown in Figure 2-1.

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512 Kbyte Flash Module (S12XFTX512K4V2)

FTX512K4

Flash Block 0

64K * 16 Bits

sector 0

sector 1

Flash

Interface

Command Pipeline

sector 127

Command

Interrupt

Request

Flash Block 1

64K * 16 Bits

cmd1

cmd2

addr1

addr2

data1_0

data1_1

data1_2

data1_3

data2_0

data2_1

data2_2

data2_3

sector 0

sector 1

Registers

sector 127

Flash Block 2

64K * 16 Bits

Protection

Security

sector 0

sector 1

sector 127

Oscillator

Clock

Divider

Flash Block 3

64K * 16 Bits

FCLK

sector 0

sector 1

sector 127

Figure 2-1. FTX512K4 Block Diagram

2.2

External Signal Description

The Flash module contains no signals that connect off-chip.

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512 Kbyte Flash Module (S12XFTX512K4V2)

2.3

Memory Map and Register Deﬁnition

This section describes the memory map and registers for the Flash module.

2.3.1

Module Memory Map

The Flash memory map is shown in Figure 2-2 . The HCS12X architecture places the Flash memory

addresses between global addresses 0x78_0000 and 0x7F_FFFF. The FPROT register, described in

Section 2.3.2.5, “Flash Protection Register (FPROT)”, can be set to protect regions in the Flash memory

from accidental program or erase. Three separate memory regions, one growing upward from global

address 0x7F_8000 in the Flash memory (called the lower region), one growing downward from global

address 0x7F_FFFF in the Flash memory (called the higher region), and the remaining addresses in the

Flash memory, can be activated for protection. The Flash memory addresses covered by these protectable

regions are shown in the Flash memory map. The higher address region is mainly targeted to hold the boot

loader code since it covers the vector space. The lower address region can be used for EEPROM emulation

in an MCU without an EEPROM module since it can be left unprotected while the remaining addresses

are protected from program or erase. Default protection settings as well as security information that allows

the MCU to restrict access to the Flash module are stored in the Flash conﬁguration ﬁeld as described in

Table 2-1.

Table 2-1. Flash Conﬁguration Field

Size

(Bytes)

Global Address

Description

0x7F_FF00 – 0x7F_FF07

Backdoor Comparison Key

Refer to Section 2.6.1, “Unsecuring the MCU using Backdoor Key Access”

0x7F_FF08 – 0x7F_FF0C

0x7F_FF0D

Reserved

Flash Protection byte

Refer to Section 2.3.2.5, “Flash Protection Register (FPROT)”

0x7F_FF0E

0x7F_FF0F

Flash Nonvolatile byte

Refer to Section 2.3.2.8, “Flash Control Register (FCTL)”

Flash Security byte

Refer to Section 2.3.2.2, “Flash Security Register (FSEC)”

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512 Kbyte Flash Module (S12XFTX512K4V2)

MODULE BASE + 0x0000

Flash Registers

16 bytes

MODULE BASE + 0x000F

FLASH START = 0x78_0000

Flash Protected/Unprotected Region

480 Kbytes

0x7F_8000

0x7F_8400

0x7F_8800

Flash Protected/Unprotected Lower Region

1, 2, 4, 8 Kbytes

0x7F_9000

0x7F_A000

Flash Protected/Unprotected Region

8 Kbytes (up to 29 Kbytes)

0x7F_C000

Flash Protected/Unprotected Higher Region

2, 4, 8, 16 Kbytes

0x7F_E000

0x7F_F000

0x7F_F800

Flash Conﬁguration Field

16 bytes (0x7F_FF00 - 0x7F_FF0F)

FLASH END = 0x7F_FFFF

Figure 2-2. Flash Memory Map

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512 Kbyte Flash Module (S12XFTX512K4V2)

The Flash module also contains a set of 16 control and status registers located between module base +

0x0000 and 0x000F. A summary of the Flash module registers is given in Table 2-2 while their

accessibility is detailed in Section 2.3.2, “Register Descriptions”.

Table 2-2. Flash Register Map

Module

Base +

Normal Mode

Access

0x0000

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

0x0008

0x0009

0x000A

0x000B

0x000C

0x000D

0x000E

0x000F

Flash Clock Divider Register (FCLKDIV)

Flash Security Register (FSEC)

R/W

Flash Test Mode Register (FTSTMOD)

Flash Conﬁguration Register (FCNFG)

Flash Protection Register (FPROT)

Flash Status Register (FSTAT)

R/W

Flash Command Register (FCMD)

Flash Control Register (FCTL)

Flash High Address Register (FADDRHI)

Flash Low Address Register (FADDRLO)

Flash High Data Register (FDATAHI)

Flash Low Data Register (FDATALO)

RESERVED1

RESERVED2

RESERVED3

RESERVED4

1 Intended for factory test purposes only.

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512 Kbyte Flash Module (S12XFTX512K4V2)

2.3.2

Name

Bit 7

Bit 0

0x0000

FCLKDIV

FDIVLD

PRDIV8

FDIV5

RNV5

FDIV4

RNV4

FDIV3

RNV3

FDIV2

RNV2

FDIV1

FDIV0

0x0001

FSEC

KEYEN

SEC

0x0002

FTSTMOD

MRDS

0x0003

FCNFG

CBEIE

CCIE

KEYACC

FPHDIS

PVIOL

0x0004

FPROT

RNV6

FPOPEN

FPHS

FPLDIS

BLANK

FPLS

0x0005

FSTAT

CCIF

NV6

CBEIF

ACCERR

0x0006

FCMD

CMDB

NV3

0x0007

FCTL

NV7

NV5

NV4

NV2

NV1

NV0

0x0008

FADDRHI

0x0009

FADDRLO

FDATAHI

FDATALO

0x000A

FDATAHI

0x000B

FDATALO

0x000C

RESERVED1

Figure 2-3. FTX512K4 Register Summary

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512 Kbyte Flash Module (S12XFTX512K4V2)

Bit 7

Bit 0

Name

0x000D

RESERVED2

0x000E

RESERVED3

0x000F

RESERVED4

Figure 2-3. FTX512K4 Register Summary (continued)

2.3.2.1

Flash Clock Divider Register (FCLKDIV)

The FCLKDIV register is used to control timed events in program and erase algorithms.

Module Base + 0x0000

FDIVLD

PRDIV8

FDIV5

FDIV4

FDIV3

FDIV2

FDIV1

FDIV0

Reset

= Unimplemented or Reserved

Figure 2-4. Flash Clock Divider Register (FCLKDIV)

All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable.

Table 2-3. FCLKDIV Field Descriptions

Field

Description

Clock Divider Loaded.

FDIVLD

0 Register has not been written.

1 Register has been written to since the last reset.

Enable Prescalar by 8.

PRDIV8

0 The oscillator clock is directly fed into the clock divider.

1 The oscillator clock is divided by 8 before feeding into the clock divider.

5-0

Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a

FDIV[5:0] frequency of 150 kHz–200 kHz. The maximum divide ratio is 512. Please refer to Section 2.4.1.1, “Writing the

FCLKDIV Register” for more information.

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512 Kbyte Flash Module (S12XFTX512K4V2)

2.3.2.2

Flash Security Register (FSEC)

The FSEC register holds all bits associated with the security of the MCU and Flash module.

Module Base + 0x0001

KEYEN

RNV5

RNV4

RNV3

RNV2

SEC

Reset

= Unimplemented or Reserved

Figure 2-5. Flash Security Register (FSEC)

All bits in the FSEC register are readable but are not writable.

The FSEC register is loaded from the Flash Conﬁguration Field at address 0x7F_FF0F during the reset

sequence, indicated by F in Figure 2-5.

Table 2-4. FSEC Field Descriptions

Field

Description

7-6

Backdoor Key Security Enable Bits — The KEYEN[1:0] bits deﬁne the enabling of backdoor key access to the

KEYEN[1:0] Flash module as shown in Table 2-5.

5-2

Reserved Nonvolatile Bits — The RNV[5:2] bits should remain in the erased state for future enhancements.

RNV[5:2]

1-0

Flash Security Bits — The SEC[1:0] bits deﬁne the security state of the MCU as shown in Table 2-6. If the Flash

SEC[1:0]

module is unsecured using backdoor key access, the SEC[1:0] bits are forced to 1:0.

Table 2-5. Flash KEYEN States

KEYEN[1:0]

Status of Backdoor Key Access

DISABLED

ENABLED

DISABLED

1 Preferred KEYEN state to disable Backdoor Key Access.

Table 2-6. Flash Security States

SEC[1:0]

Status of Security

SECURED

UNSECURED

SECURED

1 Preferred SEC state to set MCU to secured state.

The security function in the Flash module is described in Section 2.6, “Flash Module Security”.

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512 Kbyte Flash Module (S12XFTX512K4V2)

2.3.2.3

Flash Test Mode Register (FTSTMOD)

The FTSTMOD register is used to control Flash test features.

Module Base + 0x0002

MRDS

Reset

= Unimplemented or Reserved

Figure 2-6. Flash Test Mode Register (FTSTMOD —Normal Mode)

Module Base + 0x0002

MRDS

WRALL

Reset

= Unimplemented or Reserved

Figure 2-7. Flash Test Mode Register (FTSTMOD — Special Mode)

MRDS bits are readable and writable while all remaining bits read 0 and are not writable in normal mode.

The WRALL bit is writable only in special mode to simplify mass erase and erase verify operations. When

writing to the FTSTMOD register in special mode, all unimplemented/reserved bits must be written to 0.

Table 2-7. FTSTMOD Field Descriptions

Field

Description

6–5

Margin Read Setting — The MRDS[1:0] bits are used to set the sense-amp margin level for reads of the Flash

MRDS[1:0] array as shown in Table 2-8.

Write to all Register Banks — If the WRALL bit is set, all banked FDATA registers sharing the same register

WRALL

address will be written simultaneously during a register write.

0 Write only to the FDATA register bank selected using BKSEL.

1 Write to all FDATA register banks.

Table 2-8. FTSTMOD Margin Read Settings

MRDS[1:0]

Margin Read Setting

Normal

Program Margin

Erase Margin

Normal

1 Flash array reads will be sensitive to program margin.

2 Flash array reads will be sensitive to erase margin.

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512 Kbyte Flash Module (S12XFTX512K4V2)

2.3.2.4

Flash Conﬁguration Register (FCNFG)

The FCNFG register enables the Flash interrupts and gates the security backdoor writes.

Module Base + 0x0003

CBEIE

CCIE

KEYACC

Reset

= Unimplemented or Reserved

Figure 2-8. Flash Conﬁguration Register (FCNFG — Normal Mode)

Module Base + 0x0003

CBEIE

CCIE

KEYACC

BKSEL

Reset

= Unimplemented or Reserved

Figure 2-9. Flash Conﬁguration Register (FCNFG — Special Mode)

CBEIE, CCIE and KE YACC bits are readable and writable while all remaining bits read 0 and are not

writable in normal mode. KEYACC is only writable if KEYEN (see Section 2.3.2.2, “Flash Security

mass erase and erase verify operations. When writing to the FCNFG register in special mode, all

unimplemented/ reserved bits must be written to 0.

Table 2-9. FCNFG Field Descriptions

Field

Description

Command Buffer Empty Interrupt Enable — The CBEIE bit enables an interrupt in case of an empty command

CBEIE

buffer in the Flash module.

0 Command buffer empty interrupt disabled.

1 An interrupt will be requested whenever the CBEIF ﬂag (see Section 2.3.2.6, “Flash Status Register (FSTAT)”)

is set.

Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been

CCIE

completed in the Flash module.

0 Command complete interrupt disabled.

1 An interrupt will be requested whenever the CCIF ﬂag (see Section 2.3.2.6, “Flash Status Register (FSTAT)”)

is set.

Enable Security Key Writing

KEYACC

0 Flash writes are interpreted as the start of a command write sequence.

1 Writes to Flash array are interpreted as keys to open the backdoor. Reads of the Flash array return invalid

data.

1–0

Block Select — The BKSEL[1:0] bits indicates which register bank is active according to Table 2-10.

BKSEL[1:0]

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512 Kbyte Flash Module (S12XFTX512K4V2)

Table 2-10. Flash Register Bank Selects

BKSEL[1:0]

Selected Block

Flash Block 0

Flash Block 1

Flash Block 2

Flash Block 3

2.3.2.5

Flash Protection Register (FPROT)

The FPROT register defines which Flash sectors are protected against program or erase operations.

Module Base + 0x0004

RNV6

FPOPEN

FPHDIS

FPHS

FPLDIS

FPLS

Reset

= Unimplemented or Reserved

Figure 2-10. Flash Protection Register (FPROT)

All bits in the FPROT register are readable and writable with restrictions (see Section 2.3.2.5.1, “Flash

Protection Restrictions”) except for RNV[6] which is only readable.

During the reset sequence, the FPROT register is loaded from the Flash Conﬁguration Field at global

address 0x7F_FF0D. To change the Flash protection that will be loaded during the reset sequence, the

upper sector of the Flash memory must be unprotected, then the Flash Protect/Security byte located as

described in Table 2-1 must be reprogrammed.

Trying to alter data in any protected area in the Flash memory will result in a protection violation error and

the PVIOL ﬂag will be set in the FSTAT register. The mass erase of a Flash block is not possible if any of

the Flash sectors contained in the Flash block are protected.

Table 2-11. FPROT Field Descriptions

Field

Description

Flash Protection Open — The FPOPEN bit determines the protection function for program or erase as shown

FPOPEN in Table 2-12.

0 The FPHDIS and FPLDIS bits deﬁne unprotected address ranges as speciﬁed by the corresponding

FPHS[1:0] and FPLS[1:0] bits. For an MCU without an EEPROM module, the FPOPEN clear state allows the

main part of the Flash block to be protected while a small address range can remain unprotected for EEPROM

emulation.

1 The FPHDIS and FPLDIS bits enable protection for the address range speciﬁed by the corresponding

FPHS[1:0] and FPLS[1:0] bits.

Reserved Nonvolatile Bit — The RNV[6] bit should remain in the erased state for future enhancements.

RNV6

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512 Kbyte Flash Module (S12XFTX512K4V2)

Table 2-11. FPROT Field Descriptions (continued)

Field

Description

Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a

protected/unprotected area in a speciﬁc region of the Flash memory ending with global address 0x7F_FFFF.

0 Protection/Unprotection enabled.

FPHDIS

1 Protection/Unprotection disabled.

4–3

Flash Protection Higher Address Size — The FPHS[1:0] bits determine the size of the protected/unprotected

FPHS[1:0] area as shown inTable 2-13. The FPHS[1:0] bits can only be written to while the FPHDIS bit is set.

Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a

protected/unprotected area in a speciﬁc region of the Flash memory beginning with global address 0x7F_8000.

0 Protection/Unprotection enabled.

FPLDIS

1 Protection/Unprotection disabled.

1–0

Flash Protection Lower Address Size — The FPLS[1:0] bits determine the size of the protected/unprotected

FPLS[1:0] area as shown in Table 2-14. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set.

Table 2-12. Flash Protection Function

FPOPEN

FPHDIS

FPLDIS

Function

No Protection

Protected Low Range

Protected High Range

Protected High and Low Ranges

Full Flash memory Protected

Unprotected Low Range

Unprotected High Range

Unprotected High and Low Ranges

1 For range sizes, refer to Table 2-13 and Table 2-14.

Table 2-13. Flash Protection Higher Address Range

Global

FPHS[1:0]

Protected Size

Address Range

0x7F_F800–0x7F_FFFF

0x7F_F000–0x7F_FFFF

0x7F_E000–0x7F_FFFF

0x7F_C000–0x7F_FFFF

2 Kbytes

4 Kbytes

8 Kbytes

16 Kbytes

Table 2-14. Flash Protection Lower Address Range

Global

FPLS[1:0]

Protected Size

Address Range

0x7F_8000–0x7F_83FF

0x7F_8000–0x7F_87FF

0x7F_8000–0x7F_8FFF

0x7F_8000–0x7F_9FFF

1 Kbytes

2 Kbytes

4 Kbytes

8 Kbytes

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512 Kbyte Flash Module (S12XFTX512K4V2)

All possible Flash protection scenarios are shown in Figure 2-11. Although the protection scheme is

loaded from the Flash array at global address 0x7F_FF0D during the reset sequence, it can be changed by

the user. This protection scheme can be used by applications requiring re-programming in single chip

mode while providing as much protection as possible if re-programming is not required.

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512 Kbyte Flash Module (S12XFTX512K4V2)

FPHDIS=1

FPLDIS=1

FPHDIS=1

FPLDIS=0

FPHDIS=0

FPLDIS=1

FPHDIS=0

FPLDIS=0

Scenario

0x78_0000

0x7F_8000

FPLS[1:0]

FPOPEN=1

FPHS[1:0]

0x7F_FFFF

0x78_0000

Scenario

0x7F_8000

FPLS[1:0]

FPOPEN=0

FPHS[1:0]

0x7F_FFFF

Protected region with size

Unprotected region

Protected region

defined by FPLS

Protected region with size

defined by FPHS

not defined by FPLS, FPHS

Figure 2-11. Flash Protection Scenarios

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512 Kbyte Flash Module (S12XFTX512K4V2)

2.3.2.5.1

Flash Protection Restrictions

The general guideline is that Flash protection can only be added and not removed. Table 2-15 speciﬁes all

valid transitions between Flash protection scenarios. Any attempt to write an invalid scenario to the

FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the

FPROT register reﬂect the active protection scenario. See the FPHS and FPLS descriptions for additional

restrictions.

Table 2-15. Flash Protection Scenario Transitions

To Protection Scenario

From

Protection Scenario

1 Allowed transitions marked with X.

2.3.2.6

Flash Status Register (FSTAT)

The FSTAT register defines the operational status of the module.

Module Base + 0x0005

CCIF

BLANK

CBEIF

PVIOL

ACCERR

Reset

= Unimplemented or Reserved

Figure 2-12. Flash Status Register (FSTAT — Normal Mode)

Module Base + 0x0005

CCIF

BLANK

CBEIF

PVIOL

ACCERR

FAIL

Reset

= Unimplemented or Reserved

Figure 2-13. Flash Status Register (FSTAT — Special Mode)

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512 Kbyte Flash Module (S12XFTX512K4V2)

CBEIF, PVIOL, and ACCERR are readable and writable, CCIF and BLANK are readable and not writable,

remaining bits read 0 and are not writable in normal mode. FAIL is readable and writable in special mode.

FAIL must be clear in special mode when starting a command write sequence.

Table 2-16. FSTAT Field Descriptions

Field

Description

Command Buffer Empty Interrupt Flag — The CBEIF ﬂag indicates that the address, data and command

buffers are empty so that a new command write sequence can be started. Writing a 0 to the CBEIF ﬂag has no

effect on CBEIF. Writing a 0 to CBEIF after writing an aligned word to the Flash address space, but before CBEIF

is cleared, will abort a command write sequence and cause the ACCERR ﬂag to be set. Writing a 0 to CBEIF

outside of a command write sequence will not set the ACCERR ﬂag. The CBEIF ﬂag is cleared by writing a 1 to

CBEIF. The CBEIF ﬂag is used together with the CBEIE bit in the FCNFG register to generate an interrupt

request (see Figure 2-32).

CBEIF

0 Command buffers are full.

1 Command buffers are ready to accept a new command.

Command Complete Interrupt Flag — The CCIF ﬂag indicates that there are no more commands pending. The

CCIF ﬂag is cleared when CBEIF is cleared and sets automatically upon completion of all active and pending

commands. The CCIF ﬂag does not set when an active commands completes and a pending command is

fetched from the command buffer. Writing to the CCIF ﬂag has no effect on CCIF. The CCIF ﬂag is used together

with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 2-32).

0 Command in progress.

CCIF

1 All commands are completed.

Protection Violation Flag —The PVIOL ﬂag indicates an attempt was made to program or erase an address in

a protected area of the Flash memory during a command write sequence. Writing a 0 to the PVIOL ﬂag has no

effect on PVIOL. The PVIOL ﬂag is cleared by writing a 1 to PVIOL. While PVIOL is set, it is not possible to launch

a command or start a command write sequence.

PVIOL

0 No protection violation detected.

1 Protection violation has occurred.

Access Error Flag — The ACCERR ﬂag indicates an illegal access has occurred to the Flash memory caused

ACCERR by either a violation of the command write sequence (see Section 2.4.1.2, “Command Write Sequence”), issuing

an illegal Flash command (see Table 2-18), launching the sector erase abort command terminating a sector

erase operation early (see Section 2.4.2.6, “Sector Erase Abort Command”) or the execution of a CPU STOP

instruction while a command is executing (CCIF = 0). Writing a 0 to the ACCERR ﬂag has no effect on ACCERR.

The ACCERR ﬂag is cleared by writing a 1 to ACCERR.While ACCERR is set, it is not possible to launch a

command or start a command write sequence. If ACCERR is set by an erase verify operation or a data compress

operation, any buffered command will not launch.

0 No access error detected.

1 Access error has occurred.

Flag Indicating the Erase Verify Operation Status — When the CCIF ﬂag is set after completion of an erase

verify command, the BLANK ﬂag indicates the result of the erase verify operation. The BLANK ﬂag is cleared by

the Flash module when CBEIF is cleared as part of a new valid command write sequence. Writing to the BLANK

ﬂag has no effect on BLANK.

BLANK

0 Flash block veriﬁed as not erased.

1 Flash block veriﬁed as erased.

Flag Indicating a Failed Flash Operation — The FAIL ﬂag will set if the erase verify operation fails (selected

FAIL

Flash block veriﬁed as not erased). Writing a 0 to the FAIL ﬂag has no effect on FAIL. The FAIL ﬂag is cleared by

writing a 1 to FAIL.

0 Flash operation completed without error.

1 Flash operation failed.

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512 Kbyte Flash Module (S12XFTX512K4V2)

2.3.2.7

Flash Command Register (FCMD)

The FCMD register is the Flash command register.

Module Base + 0x0006

CMDB

Reset

= Unimplemented or Reserved

Figure 2-14. Flash Command Register (FCMD)

All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not

writable.

Table 2-17. FCMD Field Descriptions

Field

Description

6-0

Flash Command — Valid Flash commands are shown in Table 2-18. Writing any command other than those

CMDB[6:0] listed in Table 2-18 sets the ACCERR ﬂag in the FSTAT register.

Table 2-18. Valid Flash Command List

CMDB[6:0]

NVM Command

0x05

0x06

0x20

0x40

0x41

0x47

Erase Verify

Data Compress

Word Program

Sector Erase

Mass Erase

Sector Erase Abort

2.3.2.8

Flash Control Register (FCTL)

The FCTL register is the Flash control register.

Module Base + 0x0007

NV7

NV6

NV5

NV4

NV3

NV2

NV1

NV0

Reset

= Unimplemented or Reserved

Figure 2-15. Flash Control Register (FCTL)

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512 Kbyte Flash Module (S12XFTX512K4V2)

All bits in the FCTL register are readable but are not writable.

The FCTL register is loaded from the Flash Conﬁguration Field byte at global address 0x7F_FF0E during

the reset sequence, indicated by F in Figure 2-15.

Table 2-19. FCTL Field Descriptions

Field

Description

7-0

Non volatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the Device User Guide for proper

NV[7:0]

use of the NV bits.

2.3.2.9

Flash Address Registers (FADDR)

The FADDRHI and FADDRLO registers are the Flash address registers.

Module Base + 0x0008

FADDRHI

Reset

= Unimplemented or Reserved

Figure 2-16. Flash Address High Register (FADDRHI)

Module Base + 0x0009

FADDRLO

Reset

= Unimplemented or Reserved

Figure 2-17. Flash Address Low Register (FADDRLO)

All FADDRHI and FADDRLO bits are readable but are not writable. After an array write as part of a

command write sequence, the FADDR registers will contain the mapped MCU address written.

2.3.2.10 Flash Data Registers (FDATA)

The FDATAHI and FDATALO registers are the Flash data registers.

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512 Kbyte Flash Module (S12XFTX512K4V2)

Module Base + 0x000A

FDATAHI

Reset

= Unimplemented or Reserved

Figure 2-18. Flash Data High Register (FDATAHI)

Module Base + 0x000B

FDATALO

Reset

= Unimplemented or Reserved

Figure 2-19. Flash Data Low Register (FDATALO)

All FDATAHI and FDATALO bits are readable but are not writable. At the completion of a data compress

operation, the resulting 16-bit signature is stored in the FDATA registers. The data compression signature

is readable in the FDATA registers until a new command write sequence is started.

2.3.2.11 RESERVED1

This register is reserved for factory testing and is not accessible.

Module Base + 0x000C

Reset

= Unimplemented or Reserved

Figure 2-20. RESERVED1

All bits read 0 and are not writable.

2.3.2.12 RESERVED2

This register is reserved for factory testing and is not accessible.

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512 Kbyte Flash Module (S12XFTX512K4V2)

Module Base + 0x000D

Reset

= Unimplemented or Reserved

Figure 2-21. RESERVED2

All bits read 0 and are not writable.

2.3.2.13 RESERVED3

This register is reserved for factory testing and is not accessible.

Module Base + 0x000E

Reset

= Unimplemented or Reserved

Figure 2-22. RESERVED3

All bits read 0 and are not writable.

2.3.2.14 RESERVED4

This register is reserved for factory testing and is not accessible.

Module Base + 0x000F

Reset

= Unimplemented or Reserved

Figure 2-23. RESERVED4

All bits read 0 and are not writable.

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512 Kbyte Flash Module (S12XFTX512K4V2)

2.4

Functional Description

2.4.1

Flash Command Operations

Write operations are used to execute program, erase, erase verify, erase abort, and data compress

algorithms described in this section. The program and erase algorithms are controlled by a state machine

whose timebase, FCLK, is derived from the oscillator clock via a programmable divider. The command

FIFO) so that a second command along with the necessary data and address can be stored to the buffer

while the ﬁrst command is still in progress. This pipelined operation allows a time optimization when

programming more than one word on a speciﬁc row in the Flash block as the high voltage generation can

be kept active in between two programming commands. The pipelined operation also allows a

simpliﬁcation of command launching. Buffer empty as well as command completion are signalled by ﬂags

in the Flash status register with corresponding interrupts generated, if enabled.

The next sections describe:

1. How to write the FCLKDIV register

2. Command write sequences to program, erase, erase verify, erase abort, and data compress

operations on the Flash memory

3. Valid Flash commands

4. Effects resulting from illegal Flash command write sequences or aborting Flash operations

2.4.1.1

Writing the FCLKDIV Register

Prior to issuing any Flash command after a reset, the user is required to write the FCLKDIV register to

divide the oscillator clock down to within the 150 kHz to 200 kHz range. Since the program and erase

timings are also a function of the bus clock, the FCLKDIV determination must take this information into

account.

If we deﬁne:

•

FCLK as the clock of the Flash timing control block

Tbus as the period of the bus clock

INT(x) as taking the integer part of x (e.g. INT(4.323) = 4)

then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 2-24.

For example, if the oscillator clock frequency is 950kHz and the bus clock frequency is 10MHz,

FCLKDIV bits FDIV[5:0] should be set to 0x04 (000100) and bit PRDIV8 set to 0. The resulting FCLK

frequency is then 190kHz. As a result, the Flash program and erase algorithm timings are increased over

the optimum target by:

(200 – 190) ⁄ 200 × 100 = 5%

If the oscillator clock frequency is 16MHz and the bus clock frequency is 40MHz, FCLKDIV bits

FDIV[5:0] should be set to 0x0A (001010) and bit PRDIV8 set to 1. The resulting FCLK frequency is then

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512 Kbyte Flash Module (S12XFTX512K4V2)

182kHz. In this case, the Flash program and erase algorithm timings are increased over the optimum target

by:

(200 – 182) ⁄ 200 × 100 = 9%

CAUTION

Program and erase command execution time will increase proportionally

with the period of FCLK. Because of the impact of clock synchronization

on the accuracy of the functional timings, programming or erasing the Flash

memory cannot be performed if the bus clock runs at less than 1 MHz.

Programming or erasing the Flash memory with FCLK < 150 kHz should

be avoided. Setting FCLKDIV to a value such that FCLK < 150 kHz can

destroy the Flash memory due to overstress. Setting FCLKDIV to a value

such that (1/FCLK+Tbus) < 5µs can result in incomplete programming or

erasure of the Flash memory cells.

If the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the

FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written

to, the Flash command loaded during a command write sequence will not execute and the ACCERR ﬂag

in the FSTAT register will set.

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512 Kbyte Flash Module (S12XFTX512K4V2)

START

Tbus < 1µs?

ALL COMMANDS IMPOSSIBLE

yes

PRDIV8=0 (reset)

oscillator_clock

12.8MHz?

yes

PRDIV8=1

PRDCLK=oscillator_clock/8

PRDCLK=oscillator_clock

PRDCLK[MHz]*(5+Tbus[µs])

an integer?

FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs]))

yes

FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1

TRY TO DECREASE Tbus

FCLK=(PRDCLK)/(1+FDIV[5:0])

yes

1/FCLK[MHz] + Tbus[µs] > 5

END

AND

FCLK > 0.15MHz

yes

FDIV[5:0] > 4?

ALL COMMANDS IMPOSSIBLE

Figure 2-24. Determination Procedure for PRDIV8 and FDIV Bits

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512 Kbyte Flash Module (S12XFTX512K4V2)

2.4.1.2

Command Write Sequence

The Flash command controller is used to supervise the command write sequence to execute program,

erase, erase verify, erase abort, and data compress algorithms.

Before starting a command write sequence, the ACCERR and PVIOL ﬂags in the FSTAT register must be

clear (see Section 2.3.2.6, “Flash Status Register (FSTAT)”) and the CBEIF ﬂag should be tested to

determine the state of the address, data and command buffers. If the CBEIF ﬂag is set, indicating the

buffers are empty, a new command write sequence can be started. If the CBEIF ﬂag is clear, indicating the

buffers are not available, a new command write sequence will overwrite the contents of the address, data

and command buffers.

A command write sequence consists of three steps which must be strictly adhered to with writes to the

Flash module not permitted between the steps. However, Flash register and array reads are allowed during

a command write sequence. The basic command write sequence is as follows:

1. Write to a valid address in the Flash memory. Addresses in multiple Flash blocks can be written to

as long as the location is at the same relative address in each available Flash block. Multiple

addresses must be written in Flash block order starting with the lower Flash block.

2. Write a valid command to the FCMD register.

3. Clear the CBEIF ﬂag in the FSTAT register by writing a 1 to CBEIF to launch the command.

The address written in step 1 will be stored in the FADDR registers and the data will be stored in the

FDATA registers. If the CBEIF ﬂag in the FSTAT register is clear when the ﬁrst Flash array write occurs,

the contents of the address and data buffers will be overwritten and the CBEIF ﬂag will be set. When the

CBEIF ﬂag is cleared, the CCIF ﬂag is cleared on the same bus cycle by the Flash command controller

indicating that the command was successfully launched. For all command write sequences except data

compress and sector erase abort, the CBEIF ﬂag will set four bus cycles after the CCIF ﬂag is cleared

indicating that the address, data, and command buffers are ready for a new command write sequence to

begin. For data compress and sector erase abort operations, the CBEIF ﬂag will remain clear until the

operation completes. Except for the sector erase abort command, a buffered command will wait for the

active operation to be completed before being launched. The sector erase abort command is launched when

the CBEIF ﬂag is cleared as part of a sector erase abort command write sequence. Once a command is

launched, the completion of the command operation is indicated by the setting of the CCIF ﬂag in the

FSTAT register. The CCIF ﬂag will set upon completion of all active and buffered commands.

2.4.2

Flash Commands

Table 2-20 summarizes the valid Flash commands along with the effects of the commands on the Flash

block.

Table 2-20. Flash Command Description

NVM

Command

FCMDB

Function on Flash Memory

0x05

Erase

Verify

Verify all memory bytes in the Flash block are erased.

If the Flash block is erased, the BLANK ﬂag in the FSTAT register will set upon command

completion.

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512 Kbyte Flash Module (S12XFTX512K4V2)

Table 2-20. Flash Command Description

NVM

Command

FCMDB

Function on Flash Memory

0x06

Data

Compress

Compress data from a selected portion of the Flash block.

The resulting signature is stored in the FDATA register.

0x20

0x40

Program

Program a word (two bytes) in the Flash block.

Sector

Erase

Erase all memory bytes in a sector of the Flash block.

0x41

0x47

Mass

Erase

Erase all memory bytes in the Flash block.

A mass erase of the full Flash block is only possible when FPLDIS, FPHDIS and

FPOPEN bits in the FPROT register are set prior to launching the command.

Sector

Erase

Abort

Abort the sector erase operation.

The sector erase operation will terminate according to a set procedure. The Flash sector

should not be considered erased if the ACCERR ﬂag is set upon command completion.

CAUTION

A Flash word must be in the erased state before being programmed.

Cumulative programming of bits within a Flash word is not allowed.

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512 Kbyte Flash Module (S12XFTX512K4V2)

2.4.2.1

Erase Verify Command

The erase verify operation will verify that a Flash block is erased.

An example ﬂow to execute the erase verify operation is shown in Figure 2-25. The erase verify command

write sequence is as follows:

1. Write to a Flash block address to start the command write sequence for the erase verify command.

The address and data written will be ignored. Multiple Flash blocks can be simultaneously erase

veriﬁed by writing to the same relative address in each Flash block.

2. Write the erase verify command, 0x05, to the FCMD register.

3. Clear the CBEIF ﬂag in the FSTAT register by writing a 1 to CBEIF to launch the erase verify

command.

After launching the erase verify command, the CCIF ﬂag in the FSTAT register will set after the operation

has completed unless a new command write sequence has been buffered. The number of bus cycles

required to execute the erase verify operation is equal to the number of addresses in a Flash block plus 14

bus cycles as measured from the time the CBEIF ﬂag is cleared until the CCIF ﬂag is set. Upon completion

of the erase verify operation, the BLANK ﬂag in the FSTAT register will be set if all addresses in the

selected Flash blocks are veriﬁed to be erased. If any address in a selected Flash block is not erased, the

erase verify operation will terminate and the BLANK ﬂag in the FSTAT register will remain clear. The

MRDS bits in the FTSTMOD register will determine the sense-amp margin setting during the erase verify

operation.

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512 Kbyte Flash Module (S12XFTX512K4V2)

START

Read: FCLKDIV register

Clock Register

Written

NOTE: FCLKDIV needs to

be set once after each reset.

FDIVLD

Set?

Check

yes

Write: FCLKDIV register

Read: FSTAT register

Address, Data,

Command

Buffer Empty Check

CBEIF

Set?

yes

ACCERR/

PVIOL

Set?

yes

Access Error and

Protection Violation

Check

Write: FSTAT register

Clear ACCERR/PVIOL 0x30

Write: Flash Block Address

and Dummy Data

Simultaneous

Multiple Flash Block

Decision

Flash

Block?

yes

Decrement Global Address

by 128K

Write: FCMD register

Erase Verify Command 0x05

Write: FSTAT register

Clear CBEIF 0x80

Read: FSTAT register

Bit Polling for

Command Completion

Check

CCIF

Set?

yes

Erase Verify

Status

BLANK

Set?

yes

Flash Block

Erased

Flash Block

EXIT

Not Erased

Figure 2-25. Example Erase Verify Command Flow

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512 Kbyte Flash Module (S12XFTX512K4V2)

2.4.2.2

Data Compress Command

The data compress operation will check Flash code integrity by compressing data from a selected portion

of the Flash memory into a signature analyzer.

An example ﬂow to execute the data compress operation is shown in Figure 2-26. The data compress

command write sequence is as follows:

1. Write to a Flash block address to start the command write sequence for the data compress

command. The address written determines the starting address for the data compress operation and

the data written determines the number of consecutive words to compress. If the data value written

is 0x0000, 64K addresses or 128 Kbytes will be compressed. Multiple Flash blocks can be

simultaneously compressed by writing to the same relative address in each Flash block. If more

than one Flash block is written to in this step, the ﬁrst data written will determine the number of

consecutive words to compress in each selected Flash block.

2. Write the data compress command, 0x06, to the FCMD register.

3. Clear the CBEIF ﬂag in the FSTAT register by writing a 1 to CBEIF to launch the data compress

command.

After launching the data compress command, the CCIF ﬂag in the FSTAT register will set after the data

compress operation has completed. The number of bus cycles required to execute the data compress

operation is equal to two times the number of consecutive words to compress plus the number of Flash

blocks simultaneously compressed plus 18 bus cycles as measured from the time the CBEIF ﬂag is cleared

until the CCIF ﬂag is set. Once the CCIF ﬂag is set, the signature generated by the data compress operation

is available in the FDATA registers. The signature in the FDATA registers can be compared to the expected

signature to determine the integrity of the selected data stored in the selected Flash memory. If the last

address of a Flash block is reached during the data compress operation, data compression will continue

with the starting address of the same Flash block. The MRDS bits in the FTSTMOD register will determine

the sense-amp margin setting during the data compress operation.

NOTE

Since the FDATA registers (or data buffer) are written to as part of the data

compress operation, a command write sequence is not allowed to be

buffered behind a data compress command write sequence. The CBEIF ﬂag

will not set after launching the data compress command to indicate that a

command should not be buffered behind it. If an attempt is made to start a

new command write sequence with a data compress operation active, the

ACCERR ﬂag in the FSTAT register will be set. A new command write

sequence should only be started after reading the signature stored in the

FDATA registers.

In order to take corrective action, it is recommended that the data compress command be executed on a

Flash sector or subset of a Flash sector. If the data compress operation on a Flash sector returns an invalid

signature, the Flash sector should be erased using the sector erase command and then reprogrammed using

the program command.

The data compress command can be used to verify that a sector or sequential set of sectors are erased.

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512 Kbyte Flash Module (S12XFTX512K4V2)

START

Read: FCLKDIV register

Clock Register

Written

NOTE: FCLKDIV needs to

be set once after each reset.

FDIVLD

Set?

Check

yes

Write: FCLKDIV register

Read: FSTAT register

Address, Data,

Command

Buffer Empty Check

CBEIF

Set?

yes

ACCERR/

PVIOL

Set?

yes

Access Error and

Protection Violation

Check

Write: FSTAT register

Clear ACCERR/PVIOL 0x30

Write: Flash Address to start

compression and number of word

addresses to compress

NOTE: address used to select

Flash block; data ignored.

Simultaneous

Multiple Flash Block

Decision

Flash

Block?

yes

Decrement Global Address

by 128K

Write: FCMD register

Data Compress Command 0x06

Write: FSTAT register

Clear CBEIF 0x80

Read: FSTAT register

Bit Polling for

Command Completion

Check

CCIF

Set?

yes

Read: FDATA registers

Data Compress Signature

Signature

Valid?

Erase and Reprogram

Flash Sector(s) Compressed

yes

EXIT

Figure 2-26. Example Data Compress Command Flow

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512 Kbyte Flash Module (S12XFTX512K4V2)

2.4.2.2.1

Data Compress Operation

The Flash module contains a 16-bit multiple-input signature register (MISR) for each Flash block to

generate a 16-bit signature based on selected Flash array data. If multiple Flash blocks are selected for

simultaneous compression, then the signature from each Flash block is further compressed to generate a

single 16-bit signature. The ﬁnal 16-bit signature, found in the FDATA registers after the data compress

operation has completed, is based on the following logic equation which is executed on every data

compression cycle during the operation:

MISR[15:0] = {MISR[14:0], ^MISR[15,4,2,1]} ^ DATA[15:0]

Eqn. 2-1

where MISR is the content of the internal signature register associated with each Flash block and DATA

is the data to be compressed as shown in Figure 2-27.

DATA[0]

DATA[1]

DATA[2]

DATA[3]

DATA[4]

DATA[5]

DATA[15]

...

D Q

M15

= Exclusive-OR

MISR[15:0] = Q[15:0]

Figure 2-27. 16-Bit MISR Diagram

During the data compress operation, the following steps are executed:

1. MISR for each Flash block is reset to 0xFFFF.

2. Initialized DATA equal to 0xFFFF is compressed into the MISR for each selected Flash block

which results in the MISR containing 0x0001.

3. DATA equal to the selected Flash array data range is read and compressed into the MISR for each

selected Flash block with addresses incrementing.

4. DATA equal to the selected Flash array data range is read and compressed into the MISR for each

selected Flash block with addresses decrementing.

5. If Flash block 0 is selected for compression, DATA equal to the contents of the MISR for Flash

block 0 is compressed into the MISR for Flash block 0. If data in Flash block 0 was not selected

for compression, the MISR for Flash block 0 contains 0xFFFF.

6. If Flash block 1 is selected for compression, DATA equal to the contents of the MISR for Flash

block 1 is compressed into the MISR for Flash block 0.

7. If Flash block 2 is selected for compression, DATA equal to the contents of the MISR for Flash

block 2 is compressed into the MISR for Flash block 0.

8. If Flash block 3 is selected for compression, DATA equal to the contents of the MISR for Flash

block 3 is compressed into the MISR for Flash block 0.

9. The contents of the MISR for Flash block 0 are written to the FDATA registers.

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512 Kbyte Flash Module (S12XFTX512K4V2)

2.4.2.3

Program Command

The program operation will program a previously erased word in the Flash memory using an embedded

algorithm.

An example ﬂow to execute the program operation is shown in Figure 2-28. The program command write

sequence is as follows:

1. Write to a Flash block address to start the command write sequence for the program command. The

data written will be programmed to the address written. Multiple Flash blocks can be

simultaneously programmed by writing to the same relative address in each Flash block.

2. Write the program command, 0x20, to the FCMD register.

3. Clear the CBEIF ﬂag in the FSTAT register by writing a 1 to CBEIF to launch the program

command.

If a word to be programmed is in a protected area of the Flash block, the PVIOL ﬂag in the FSTAT register

will set and the program command will not launch. Once the program command has successfully launched,

the CCIF ﬂag in the FSTAT register will set after the program operation has completed unless a new

command write sequence has been buffered. By executing a new program command write sequence on

sequential words after the CBEIF ﬂag in the FSTAT register has been set, up to 55% faster programming

time per word can be effectively achieved than by waiting for the CCIF ﬂag to set after each program

operation.

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512 Kbyte Flash Module (S12XFTX512K4V2)

START

Read: FCLKDIV register

Clock Register

NOTE: FCLKDIV needs to

FDIVLD

Set?

Written

Check

be set once after each reset.

yes

Write: FCLKDIV register

Read: FSTAT register

Address, Data,

Command

Buffer Empty Check

CBEIF

Set?

yes

ACCERR/

PVIOL

Set?

yes

Access Error and

Protection Violation

Check

Write: FSTAT register

Clear ACCERR/PVIOL 0x30

Write: Flash Address

and program Data

Simultaneous

Multiple Flash Block

Decision

Flash

Block?

yes

Decrement Global Address

by 128K

Write: FCMD register

Program Command 0x20

Write: FSTAT register

Clear CBEIF 0x80

Read: FSTAT register

Bit Polling for

Buffer Empty

Check

CBEIF

Set?

yes

Sequential

Programming

Decision

yes

Word?

Read: FSTAT register

Bit Polling for

Command Completion

Check

CCIF

Set?

yes

EXIT

Figure 2-28. Example Program Command Flow

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512 Kbyte Flash Module (S12XFTX512K4V2)

2.4.2.4

Sector Erase Command

The sector erase operation will erase all addresses in a 1 Kbyte sector of Flash memory using an embedded

algorithm.

An example ﬂow to execute the sector erase operation is shown in Figure 2-29. The sector erase command

write sequence is as follows:

1. Write to a Flash block address to start the command write sequence for the sector erase command.

The Flash address written determines the sector to be erased while global address bits [9:0] and the

data written are ignored. Multiple Flash sectors can be simultaneously erased by writing to the

same relative address in each Flash block.

2. Write the sector erase command, 0x40, to the FCMD register.

3. Clear the CBEIF ﬂag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase

command.

If a Flash sector to be erased is in a protected area of the Flash block, the PVIOL ﬂag in the FSTAT register

will set and the sector erase command will not launch. Once the sector erase command has successfully

launched, the CCIF ﬂag in the FSTAT register will set after the sector erase operation has completed unless

a new command write sequence has been buffered.

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512 Kbyte Flash Module (S12XFTX512K4V2)

START

Read: FCLKDIV register

Clock Register

NOTE: FCLKDIV needs to

FDIVLD

Set?

Written

Check

be set once after each reset.

yes

Write: FCLKDIV register

Read: FSTAT register

Address, Data,

Command

Buffer Empty Check

CBEIF

Set?

yes

ACCERR/

PVIOL

Set?

yes

Access Error and

Protection Violation

Check

Write: FSTAT register

Clear ACCERR/PVIOL 0x30

Write: Flash Sector Address

and Dummy Data

Simultaneous

Multiple Flash Block

Decision

Flash

yes

Decrement Global Address

by 128K

Block?

Write: FCMD register

Sector Erase Command 0x40

Write: FSTAT register

Clear CBEIF 0x80

Read: FSTAT register

Bit Polling for

Command Completion

Check

CCIF

Set?

yes

EXIT

Figure 2-29. Example Sector Erase Command Flow

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512 Kbyte Flash Module (S12XFTX512K4V2)

2.4.2.5

Mass Erase Command

The mass erase operation will erase all addresses in a Flash block using an embedded algorithm.

An example ﬂow to execute the mass erase operation is shown in Figure 2-30. The mass erase command

write sequence is as follows:

1. Write to a Flash block address to start the command write sequence for the mass erase command.

The address and data written will be ignored. Multiple Flash blocks can be simultaneously mass

erased by writing to the same relative address in each Flash block.

2. Write the mass erase command, 0x41, to the FCMD register.

3. Clear the CBEIF ﬂag in the FSTAT register by writing a 1 to CBEIF to launch the mass erase

command.

If a Flash block to be erased contains any protected area, the PVIOL ﬂag in the FSTAT register will set and

the mass erase command will not launch. Once the mass erase command has successfully launched, the

CCIF ﬂag in the FSTAT register will set after the mass erase operation has completed unless a new

command write sequence has been buffered.

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512 Kbyte Flash Module (S12XFTX512K4V2)

START

Read: FCLKDIV register

Clock Register

NOTE: FCLKDIV needs to

FDIVLD

Set?

Written

Check

be set once after each reset.

yes

Write: FCLKDIV register

Read: FSTAT register

Address, Data,

Command

Buffer Empty Check

CBEIF

Set?

yes

ACCERR/

PVIOL

Set?

yes

Access Error and

Protection Violation

Check

Write: FSTAT register

Clear ACCERR/PVIOL 0x30

Write: Flash Block Address

and Dummy Data

Simultaneous

Multiple Flash Block

Decision

Flash

Block?

yes

Decrement Global Address

by 128K

Write: FCMD register

Mass Erase Command 0x41

Write: FSTAT register

Clear CBEIF 0x80

Read: FSTAT register

Bit Polling for

Command Completion

Check

CCIF

Set?

yes

EXIT

Figure 2-30. Example Mass Erase Command Flow

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512 Kbyte Flash Module (S12XFTX512K4V2)

2.4.2.6

Sector Erase Abort Command

The sector erase abort operation will terminate the active sector erase operation so that other sectors in a

Flash block are available for read and program operations without waiting for the sector erase operation to

complete.

An example ﬂow to execute the sector erase abort operation is shown in Figure 2-31. The sector erase abort

command write sequence is as follows:

1. Write to any Flash block address to start the command write sequence for the sector erase abort

command. The address and data written are ignored.

2. Write the sector erase abort command, 0x47, to the FCMD register.

3. Clear the CBEIF ﬂag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase abort

command.

If the sector erase abort command is launched resulting in the early termination of an active sector erase

operation, the ACCERR ﬂag will set once the operation completes as indicated by the CCIF ﬂag being set.

The ACCERR ﬂag sets to inform the user that the Flash sector may not be fully erased and a new sector

erase command must be launched before programming any location in that speciﬁc sector. If the sector

erase abort command is launched but the active sector erase operation completes normally, the ACCERR

ﬂag will not set upon completion of the operation as indicated by the CCIF ﬂag being set. Therefore, if the

ACCERR ﬂag is not set after the sector erase abort command has completed, a Flash sector being erased

when the abort command was launched will be fully erased. The maximum number of cycles required to

abort a sector erase operation is equal to four FCLK periods (see Section 2.4.1.1, “Writing the FCLKDIV

set. If sectors in multiple Flash blocks are being simultaneously erased, the sector erase abort operation

will be applied to all active Flash blocks without writing to each Flash block in the sector erase abort

command write sequence.

NOTE

Since the ACCERR bit in the FSTAT register may be set at the completion

of the sector erase abort operation, a command write sequence is not

allowed to be buffered behind a sector erase abort command write sequence.

The CBEIF ﬂag will not set after launching the sector erase abort command

to indicate that a command should not be buffered behind it. If an attempt is

made to start a new command write sequence with a sector erase abort

operation active, the ACCERR ﬂag in the FSTAT register will be set. A new

command write sequence may be started after clearing the ACCERR ﬂag, if

set.

NOTE

The sector erase abort command should be used sparingly since a sector

erase operation that is aborted counts as a complete program/erase cycle.

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512 Kbyte Flash Module (S12XFTX512K4V2)

Execute Sector Erase Command Flow

Read: FSTAT register

Erase

Abort

Needed?

Bit Polling for

Command

Completion Check

CCIF

Set?

yes

Sector Erase

Completed

EXIT

Write: Dummy Flash Address

and Dummy Data

Write: FCMD register

Sector Erase Abort Cmd 0x47

Write: FSTAT register

Clear CBEIF 0x80

Read: FSTAT register

Bit Polling for

Command

Completion Check

CCIF

Set?

yes

ACCERR

Set?

Access

Error Check

Write: FSTAT register

Clear ACCERR 0x10

Sector Erase

Completed

Sector Erase

Aborted

EXIT

Figure 2-31. Example Sector Erase Abort Command Flow

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512 Kbyte Flash Module (S12XFTX512K4V2)

2.4.3

Illegal Flash Operations

The ACCERR ﬂag will be set during the command write sequence if any of the following illegal steps are

performed, causing the command write sequence to immediately abort:

1. Writing to a Flash address before initializing the FCLKDIV register.

2. Writing a byte or misaligned word to a valid Flash address.

3. Starting a command write sequence while a data compress operation is active.

4. Starting a command write sequence while a sector erase abort operation is active.

5. Writing a Flash address in step 1 of a command write sequence that is not the same relative address

as the ﬁrst one written in the same command write sequence.

6. Writing to any Flash register other than FCMD after writing to a Flash address.

7. Writing a second command to the FCMD register in the same command write sequence.

8. Writing an invalid command to the FCMD register.

9. When security is enabled, writing a command other than mass erase to the FCMD register when

the write originates from a non-secure memory location or from the Background Debug Mode.

10. Writing to a Flash address after writing to the FCMD register.

11. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the FCMD

12. Writing a 0 to the CBEIF ﬂag in the FSTAT register to abort a command write sequence.

The ACCERR ﬂag will not be set if any Flash register is read during a valid command write sequence.

The ACCERR ﬂag will also be set if any of the following events occur:

1. Launching the sector erase abort command while a sector erase operation is active which results in

the early termination of the sector erase operation (see Section 2.4.2.6, “Sector Erase Abort

Command”).

2. The MCU enters stop mode and a program or erase operation is in progress. The operation is

aborted immediately and any pending command is purged (see Section 2.5.2, “Stop Mode”).

If the Flash memory is read during execution of an algorithm (CCIF = 0), the read operation will return

invalid data and the ACCERR ﬂag will not be set.

If the ACCERR ﬂag is set in the FSTAT register, the user must clear the ACCERR ﬂag before starting

another command write sequence (see Section 2.3.2.6, “Flash Status Register (FSTAT)”).

The PVIOL ﬂag will be set after the command is written to the FCMD register during a command write

sequence if any of the following illegal operations are attempted, causing the command write sequence to

immediately abort:

1. Writing the program command if an address written in the command write sequence was in a

protected area of the Flash memory

2. Writing the sector erase command if an address written in the command write sequence was in a

protected area of the Flash memory

3. Writing the mass erase command to a Flash block while any Flash protection is enabled in the

block

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If the PVIOL ﬂag is set in the FSTAT register, the user must clear the PVIOL ﬂag before starting another

command write sequence (see Section 2.3.2.6, “Flash Status Register (FSTAT)”).

2.5

Operating Modes

Wait Mode

2.5.1

If a command is active (CCIF = 0) when the MCU enters wait mode, the active command and any buffered

command will be completed.

The Flash module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled

(see Section 2.8, “Interrupts”).

2.5.2

Stop Mode

If a command is active (CCIF = 0) when the MCU enters stop mode, the operation will be aborted and, if

the operation is program or erase, the Flash array data being programmed or erased may be corrupted and

the CCIF and ACCERR ﬂags will be set. If active, the high voltage circuitry to the Flash memory will

immediately be switched off when entering stop mode. Upon exit from stop mode, the CBEIF ﬂag is set

and any buffered command will not be launched. The ACCERR ﬂag must be cleared before starting a

command write sequence (see Section 2.4.1.2, “Command Write Sequence”).

NOTE

As active commands are immediately aborted when the MCU enters stop

mode, it is strongly recommended that the user does not use the STOP

instruction during program or erase operations.

2.5.3

Background Debug Mode

In background debug mode (BDM), the FPROT register is writable. If the MCU is unsecured, then all

Flash commands listed in Table 2-20 can be executed. If the MCU is secured and is in special single chip

mode, only mass erase can be executed.

2.6

Flash Module Security

The Flash module provides the necessary security information to the MCU. After each reset, the Flash

module determines the security state of the MCU as deﬁned in Section 2.3.2.2, “Flash Security Register

(FSEC)”.

The contents of the Flash security byte at 0x7F_FF0F in the Flash Conﬁguration Field must be changed

directly by programming 0x7F_FF0F when the MCU is unsecured and the higher address sector is

unprotected. If the Flash security byte is left in a secured state, any reset will cause the MCU to initialize

to a secure operating mode.

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512 Kbyte Flash Module (S12XFTX512K4V2)

2.6.1

Unsecuring the MCU using Backdoor Key Access

The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the

contents of the backdoor keys (four 16-bit words programmed at addresses 0x7F_FF00–0x7F_FF07). If

the KEYEN[1:0] bits are in the enabled state (see Section 2.3.2.2, “Flash Security Register (FSEC)”) and

the KEYACC bit is set, a write to a backdoor key address in the Flash memory triggers a comparison

between the written data and the backdoor key data stored in the Flash memory. If all four words of data

are written to the correct addresses in the correct order and the data matches the backdoor keys stored in

the Flash memory, the MCU will be unsecured. The data must be written to the backdoor keys sequentially

starting with 0x7F_FF00–1 and ending with 0x7F_FF06–7. 0x0000 and 0xFFFF are not permitted as

backdoor keys. While the KEYACC bit is set, reads of the Flash memory will return invalid data.

The user code stored in the Flash memory must have a method of receiving the backdoor keys from an

external stimulus. This external stimulus would typically be through one of the on-chip serial ports.

If the KEYEN[1:0] bits are in the enabled state (see Section 2.3.2.2, “Flash Security Register (FSEC)”),

the MCU can be unsecured by the backdoor key access sequence described below:

1. Set the KEYACC bit in the Flash Conﬁguration Register (FCNFG).

2. Write the correct four 16-bit words to Flash addresses 0xFF00–0xFF07 sequentially starting with

0x7F_FF00.

3. Clear the KEYACC bit. Depending on the user code used to write the backdoor keys, a wait cycle

(NOP) may be required before clearing the KEYACC bit.

4. If all four 16-bit words match the backdoor keys stored in Flash addresses

0x7F_FF00–0x7F_FF07, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are

forced to the unsecure state of 1:0.

The backdoor key access sequence is monitored by an internal security state machine. An illegal operation

during the backdoor key access sequence will cause the security state machine to lock, leaving the MCU

in the secured state. A reset of the MCU will cause the security state machine to exit the lock state and

allow a new backdoor key access sequence to be attempted. The following operations during the backdoor

key access sequence will lock the security state machine:

1. If any of the four 16-bit words does not match the backdoor keys programmed in the Flash array.

2. If the four 16-bit words are written in the wrong sequence.

3. If more than four 16-bit words are written.

4. If any of the four 16-bit words written are 0x0000 or 0xFFFF.

5. If the KEYACC bit does not remain set while the four 16-bit words are written.

6. If any two of the four 16-bit words are written on successive MCU clock cycles.

After the backdoor keys have been correctly matched, the MCU will be unsecured. Once the MCU is

unsecured, the Flash security byte can be programmed to the unsecure state, if desired.

In the unsecure state, the user has full control of the contents of the backdoor keys by programming

addresses 0x7F_FF00–0x7F_FF07 in the Flash Conﬁguration Field.

The security as deﬁned in the Flash security byte (0x7F_FF0F) is not changed by using the backdoor key

access sequence to unsecure. The backdoor keys stored in addresses 0x7F_FF00–0x7F_FF07 are

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unaffected by the backdoor key access sequence. After the next reset of the MCU, the security state of the

Flash module is determined by the Flash security byte (0x7F_FF0F). The backdoor key access sequence

has no effect on the program and erase protections deﬁned in the Flash protection register.

It is not possible to unsecure the MCU in special single chip mode by using the backdoor key access

sequence in background debug mode (BDM).

2.6.2

Unsecuring the MCU in Special Single Chip Mode using BDM

The MCU can be unsecured in special single chip mode by erasing the Flash module by the following

method:

•

Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM

secure ROM, send BDM commands to disable protection in the Flash module, and execute a mass

erase command write sequence to erase the Flash memory.

After the CCIF ﬂag sets to indicate that the mass operation has completed, reset the MCU into special

single chip mode. The BDM secure ROM will verify that the Flash memory is erased and will assert the

UNSEC bit in the BDM status register. This BDM action will cause the MCU to override the Flash security

state and the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte

may be programmed to the unsecure state by the following method:

•

Send BDM commands to execute a word program sequence to program the Flash security byte to

the unsecured state and reset the MCU.

2.7

Resets

2.7.1

Flash Reset Sequence

On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following

registers from the Flash memory according to Table 2-1 :

•

FPROT — Flash Protection Register (see Section 2.3.2.5).

FCTL - Flash Control Register (see Section 2.3.2.8 ).

FSEC — Flash Security Register (see Section 2.3.2.2).

2.7.2

Reset While Flash Command Active

If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The

state of the word being programmed or the sector/block being erased is not guaranteed.

2.8

Interrupts

The Flash module can generate an interrupt when all Flash command operations have completed, when the

Flash address, data and command buffers are empty.

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512 Kbyte Flash Module (S12XFTX512K4V2)

Table 2-21. Flash Interrupt Sources

Interrupt Source

Interrupt Flag

Local Enable

Global (CCR) Mask

Flash Address, Data and Command Buffers empty

CBEIF

CBEIE

I Bit

(FSTAT register)

(FCNFG register)

All Flash commands completed

CCIF

CCIE

I Bit

(FSTAT register)

(FCNFG register)

NOTE

Vector addresses and their relative interrupt priority are determined at the

MCU level.

2.8.1

Description of Flash Interrupt Operation

The logic used for generating interrupts is shown in Figure 2-32.

The Flash module uses the CBEIF and CCIF ﬂags in combination with the CBIE and CCIE enable bits to

generate the Flash command interrupt request.

CBEIF

CBEIE

Flash Command Interrupt Request

CCIF

CCIE

Figure 2-32. Flash Interrupt Implementation

For a detailed description of the register bits, refer to Section 2.3.2.4, “Flash Conﬁguration Register

(FCNFG)” and Section 2.3.2.6, “Flash Status Register (FSTAT)” .

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Chapter 3

4 Kbyte EEPROM Module (S12XEETX4KV2)

3.1

Introduction

This document describes the module which includes a Kbyte EEPROM (nonvolatile) memory. The

EEPROM memory may be read as either bytes, aligned words, or misaligned words. Read access time is

one bus cycle for bytes and aligned words, and two bus cycles for misaligned words.

The EEPROM memory is ideal for data storage for single-supply applications allowing for ﬁeld

reprogramming without requiring external voltage sources for program or erase. Program and erase

functions are controlled by a command driven interface. The EEPROM module supports both block erase

(all memory bytes) and sector erase (4 memory bytes). An erased bit reads 1 and a programmed bit reads

0. The high voltage required to program and erase the EEPROM memory is generated internally. It is not

possible to read from the EEPROM block while it is being erased or programmed.

CAUTION

An EEPROM word (2 bytes) must be in the erased state before being

programmed. Cumulative programming of bits within a word is not allowed.

3.1.1

Glossary

Command Write Sequence — A three-step MCU instruction sequence to execute built-in algorithms

(including program and erase) on the EEPROM memory.

3.1.2

Features

•

Automated program and erase algorithm

Interrupts on EEPROM command completion and command buffer empty

Fast sector erase and word program operation

2-stage command pipeline

Sector erase abort feature for critical interrupt response

Flexible protection scheme to prevent accidental program or erase

Single power supply for all EEPROM operations including program and erase

3.1.3

Modes of Operation

Program, erase and erase verify operations (please refer to Section 3.4.1, “EEPROM Command

Operations” for details).

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

3.1.4

Block Diagram

A block diagram of the EEPROM module is shown in .

3.2

External Signal Description

The EEPROM module contains no signals that connect off-chip.

3.3

Memory Map and Register Deﬁnition

This section describes the memory map and registers for the EEPROM module.

3.3.1

Module Memory Map

The EEPROM memory map is shown in . The HCS12X architecture places the EEPROM memory

addresses between global addresses . The EPROT register, described in Section 3.3.2.5, “EEPROM

Protection Register (EPROT)”, can be set to protect the upper region in the EEPROM memory from

accidental program or erase. The EEPROM addresses covered by this protectable region are shown in the

EEPROM memory map. The default protection setting is stored in the EEPROM conﬁguration ﬁeld as

described in Table 3-1.

Table 3-1. EEPROM Conﬁguration Field

Size

(bytes)

Global Address

Description

0x13_FFFC

0x13_FFFD

Reserved

EEPROM Protection byte

Refer to Section 3.3.2.5, “EEPROM Protection Register (EPROT)”

0x13_FFFE – 0x13_FFFF

Reserved

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

The EEPROM module also contains a set of 12 control and status registers located between EEPROM

module base + 0x0000 and 0x000B. A summary of the EEPROM module registers is given in Table 3-2

while their accessibility is detailed in Section 3.3.2, “Register Descriptions”.

Table 3-2. EEPROM Register Map

Module

Base +

Normal Mode

Access

0x0000

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

0x0008

0x0009

0x000A

0x000B

EEPROM Clock Divider Register (ECLKDIV)

R/W

RESERVED1

RESERVED2

EEPROM Conﬁguration Register (ECNFG)

EEPROM Protection Register (EPROT)

EEPROM Status Register (ESTAT)

R/W

EEPROM Command Register (ECMD)

RESERVED3

EEPROM High Address Register (EADDRHI)

EEPROM Low Address Register (EADDRLO)

EEPROM High Data Register (EDATAHI)

EEPROM Low Data Register (EDATALO)

Intended for factory test purposes only.

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3.3.2

Name

Bit 7

PRDIV8

EDIV5

EDIV4

EDIV3

EDIV2

EDIV1

Bit 0

EDIV0

0x0000

ECLKDIV

EDIVLD

0x0001

RESERVED1

0x0002

RESERVED2

0x0003

ECNFG

CBEIE

CCIE

0x0004

EPROT

RNV6

RNV5

RNV4

EPOPEN

EPDIS

EPS2

EPS1

EPS0

0x0005

ESTAT

CCIF

BLANK

CBEIF

PVIOL

ACCERR

0x0006

ECMD

CMDB

0x0007

RESERVED3

0x0009

EABLO

EADDRLO

0x000A

EDHI

EDATAHI

0x000B

EDLO

EDATALO

= Unimplemented or Reserved

Figure 3-1. MC9S12XDP512 Register Summary

3.3.2.1

EEPROM Clock Divider Register (ECLKDIV)

The ECLKDIV register is used to control timed events in program and erase algorithms.

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Module Base + 0x0000

EDIVLD

PRDIV8

EDIV5

EDIV4

EDIV3

EDIV2

EDIV1

EDIV0

Reset

= Unimplemented or Reserved

Figure 3-2. EEPROM Clock Divider Register (ECLKDIV)

All bits in the ECLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.

Table 3-3. ECLKDIV Field Descriptions

Field

Description

Clock Divider Loaded

EDIVLD

0 Register has not been written.

1 Register has been written to since the last reset.

Enable Prescalar by 8

PRDIV8

0 The oscillator clock is directly fed into the ECLKDIV divider.

1 Enables a Prescalar by 8, to divide the oscillator clock before feeding into the clock divider.

5–0

Clock Divider Bits — The combination of PRDIV8 and EDIV[5:0] effectively divides the EEPROM module input

EDIV[5:0] oscillator clock down to a frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Please refer to

Section 3.4.1.1, “Writing the ECLKDIV Register” for more information.

3.3.2.2

RESERVED1

This register is reserved for factory testing and is not accessible.

Module Base + 0x0001

Reset

= Unimplemented or Reserved

Figure 3-3. RESERVED1

All bits read 0 and are not writable.

3.3.2.3

RESERVED2

This register is reserved for factory testing and is not accessible.

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Module Base + 0x0002

Reset

= Unimplemented or Reserved

Figure 3-4. RESERVED2

All bits read 0 and are not writable.

3.3.2.4

EEPROM Conﬁguration Register (ECNFG)

The ECNFG register enables the EEPROM interrupts.

Module Base + 0x0003

CBEIE

CCIE

Reset

= Unimplemented or Reserved

Figure 3-5. EEPROM Conﬁguration Register (ECNFG)

CBEIE and CCIE bits are readable and writable while all remaining bits read 0 and are not writable.

Table 3-4. ECNFG Field Descriptions

Field

Description

Command Buffer Empty Interrupt Enable — The CBEIE bit enables an interrupt in case of an empty command

buffer in the EEPROM module.

CBEIE

0 Command Buffer Empty interrupt disabled.

1 An interrupt will be requested whenever the CBEIF ﬂag (see Section 3.3.2.6, “EEPROM Status Register

(ESTAT)”) is set.

Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been

completed in the EEPROM module.

CCIE

0 Command Complete interrupt disabled.

1 An interrupt will be requested whenever the CCIF ﬂag (see Section 3.3.2.6, “EEPROM Status Register

(ESTAT)”) is set.

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3.3.2.5

EEPROM Protection Register (EPROT)

The EPROT register deﬁnes which EEPROM sectors are protected against program or erase operations.

Module Base + 0x0004

RNV6

RNV5

RNV4

EPOPEN

EPDIS

EPS2

EPS1

EPS0

Reset

= Unimplemented or Reserved

Figure 3-6. EEPROM Protection Register (EPROT)

During the reset sequence, the EPROT register is loaded from the EEPROM Protection byte at address

offset 0x0FFD (see Table 3-1).All bits in the EPROT register are readable and writable except for

RNV[6:4] which are only readable. The EPOPEN and EPDIS bits can only be written to the protected

state. The EPS bits can be written anytime until bit EPDIS is cleared. If the EPOPEN bit is cleared, the

state of the EPDIS and EPS bits is irrelevant.

To change the EEPROM protection that will be loaded during the reset sequence, the EEPROM memory

must be unprotected, then the EEPROM Protection byte must be reprogrammed. Trying to alter data in any

protected area in the EEPROM memory will result in a protection violation error and the PVIOL ﬂag will

be set in the ESTAT register. The mass erase of an EEPROM block is possible only when protection is

fully disabled by setting the EPOPEN and EPDIS bits.

Table 3-5. EPROT Field Descriptions

Field

Description

Opens the EEPROM for Program or Erase

EPOPEN 0 The entire EEPROM memory is protected from program and erase.

1 The EEPROM sectors not protected are enabled for program or erase.

6–4

Reserved Nonvolatile Bits — The RNV[6:4] bits should remain in the erased state “1” for future enhancements.

RNV[6:4]

EEPROM Protection Address Range Disable — The EPDIS bit determines whether there is a protected area

in a speciﬁc region of the EEPROM memory ending with address offset 0x0FFF.

0 Protection enabled.

EPDIS

1 Protection disabled.

2–0

EEPROM Protection Address Size — The EPS[2:0] bits determine the size of the protected area as shown

EPS[2:0]

inTable 3-6. The EPS bits can only be written to while the EPDIS bit is set.

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Table 3-6. EEPROM Protection Address Range

EPS[2:0]

Address Offset Range

Protected Size

000

001

010

011

100

101

110

111

0x0FC0 – 0x0FFF

0x0F80 – 0x0FFF

0x0F40 – 0x0FFF

0x0F00 – 0x0FFF

0x0EC0 – 0x0FFF

0x0E80 – 0x0FFF

0x0E40 – 0x0FFF

0x0E00 – 0x0FFF

64 bytes

128 bytes

192 bytes

256 bytes

320 bytes

384 bytes

448 bytes

512 bytes

3.3.2.6

EEPROM Status Register (ESTAT)

The ESTAT register deﬁnes the operational status of the module.

Module Base + 0x0005

CCIF

BLANK

CBEIF

PVIOL

ACCERR

Reset

= Unimplemented or Reserved

Figure 3-7. EEPROM Status Register (ESTAT — Normal Mode)

Module Base + 0x0005

CCIF

BLANK

CBEIF

PVIOL

ACCERR

FAIL

Reset

= Unimplemented or Reserved

Figure 3-8. EEPROM Status Register (ESTAT — Special Mode)

CBEIF, PVIOL, and ACCERR are readable and writable, CCIF and BLANK are readable and not writable,

remaining bits read 0 and are not writable in normal mode. FAIL is readable and writable in special mode.

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Table 3-7. ESTAT Field Descriptions

Field

Description

Command Buffer Empty Interrupt Flag — The CBEIF ﬂag indicates that the address, data, and command

buffers are empty so that a new command write sequence can be started. The CBEIF ﬂag is cleared by writing

a 1 to CBEIF. Writing a 0 to the CBEIF ﬂag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned

word to the EEPROM address space but before CBEIF is cleared will abort a command write sequence and

cause the ACCERR ﬂag to be set. Writing a 0 to CBEIF outside of a command write sequence will not set the

ACCERR ﬂag. The CBEIF ﬂag is used together with the CBEIE bit in the ECNFG register to generate an interrupt

request (see Figure 3-21).

CBEIF

0 Buffers are full.

1 Buffers are ready to accept a new command.

Command Complete Interrupt Flag — The CCIF ﬂag indicates that there are no more commands pending. The

CCIF ﬂag is cleared when CBEIF is clear and sets automatically upon completion of all active and pending

commands. The CCIF ﬂag does not set when an active commands completes and a pending command is

fetched from the command buffer. Writing to the CCIF ﬂag has no effect on CCIF. The CCIF ﬂag is used together

with the CCIE bit in the ECNFG register to generate an interrupt request (see Figure 3-21).

0 Command in progress.

CCIF

1 All commands are completed.

Protection Violation Flag — The PVIOL ﬂag indicates an attempt was made to program or erase an address

in a protected area of the EEPROM memory during a command write sequence. The PVIOL ﬂag is cleared by

writing a 1 to PVIOL. Writing a 0 to the PVIOL ﬂag has no effect on PVIOL. While PVIOL is set, it is not possible

to launch a command or start a command write sequence.

PVIOL

0 No failure.

1 A protection violation has occurred.

Access Error Flag — The ACCERR ﬂag indicates an illegal access has occurred to the EEPROM memory

ACCERR caused by either a violation of the command write sequence (see Section 3.4.1.2, “Command Write Sequence”),

issuing an illegal EEPROM command (see Table 3-9), launching the sector erase abort command terminating a

sector erase operation early (see Section 3.4.2.5, “Sector Erase Abort Command”) or the execution of a CPU

STOP instruction while a command is executing (CCIF = 0). The ACCERR ﬂag is cleared by writing a 1 to

ACCERR. Writing a 0 to the ACCERR ﬂag has no effect on ACCERR. While ACCERR is set, it is not possible to

launch a command or start a command write sequence. If ACCERR is set by an erase verify operation, any

buffered command will not launch.

0 No access error detected.

1 Access error has occurred.

Flag Indicating the Erase Verify Operation Status — When the CCIF ﬂag is set after completion of an erase

verify command, the BLANK ﬂag indicates the result of the erase verify operation. The BLANK ﬂag is cleared by

the EEPROM module when CBEIF is cleared as part of a new valid command write sequence. Writing to the

BLANK ﬂag has no effect on BLANK.

BLANK

0 EEPROM block veriﬁed as not erased.

1 EEPROM block veriﬁed as erased.

FAIL

Flag Indicating a Failed EEPROM Operation — The FAIL ﬂag will set if the erase verify operation fails

(EEPROM block veriﬁed as not erased). The FAIL ﬂag is cleared by writing a 1 to FAIL. Writing a 0 to the FAIL

ﬂag has no effect on FAIL.

0 EEPROM operation completed without error.

1 EEPROM operation failed.

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3.3.2.7

EEPROM Command Register (ECMD)

The ECMD register is the EEPROM command register.

Module Base + 0x0006

CMDB

Reset

= Unimplemented or Reserved

Figure 3-9. EEPROM Command Register (ECMD)

All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not

writable.

Table 3-8. ECMD Field Descriptions

Field

Description

6–0

EEPROM Command Bits — Valid EEPROM commands are shown in Table 3-9. Writing any command other

CMDB[6:0] than those listed in Table 3-9 sets the ACCERR ﬂag in the ESTAT register.

Table 3-9. Valid EEPROM Command List

CMDB[6:0]

Command

0x05

0x20

0x40

0x41

0x47

0x60

Erase Verify

Word Program

Sector Erase

Mass Erase

Sector Erase Abort

Sector Modify

3.3.2.8

RESERVED3

This register is reserved for factory testing and is not accessible.

Module Base + 0x0007

Reset

= Unimplemented or Reserved

Figure 3-10. RESERVED3

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

All bits read 0 and are not writable.

EEPROM Address Registers (EADDR)

The EADDRHI and EADDRLO registers are the EEPROM address registers.

Module Base + 0x0009

EABLO

Reset

= Unimplemented or Reserved

Figure 3-11. EEPROM Address Low Register (EADDRLO)

All EABHI and EABLO bits read 0 and are not writable in normal modes.

All EABHI and EABLO bits are readable and writable in special modes.

The MCU address bit AB0 is not stored in the EADDR registers since the EEPROM block is not byte

addressable.

3.3.2.9

EEPROM Data Registers (EDATA)

The EDATAHI and EDATALO registers are the EEPROM data registers.

Module Base + 0x000A

EDHI

Reset

= Unimplemented or Reserved

Figure 3-12. EEPROM Data High Register (EDATAHI)

Module Base + 0x000B

EDLO

Reset

= Unimplemented or Reserved

Figure 3-13. EEPROM Data Low Register (EDATALO)

All EDHI and EDLO bits read 0 and are not writable in normal modes.

All EDHI and EDLO bits are readable and writable in special modes.

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

3.4

Functional Description

3.4.1

EEPROM Command Operations

Write operations are used to execute program, erase, erase verify, sector erase abort, and sector modify

algorithms described in this section. The program, erase, and sector modify algorithms are controlled by

a state machine whose timebase, EECLK, is derived from the oscillator clock via a programmable divider.

The command register as well as the associated address and data registers operate as a buffer and a register

(2-stage FIFO) so that a second command along with the necessary data and address can be stored to the

buffer while the ﬁrst command is still in progress. Buffer empty as well as command completion are

signalled by ﬂags in the EEPROM status register with interrupts generated, if enabled.

The next sections describe:

1. How to write the ECLKDIV register

2. Command write sequences to program, erase, erase verify, sector erase abort, and sector modify

operations on the EEPROM memory

3. Valid EEPROM commands

4. Effects resulting from illegal EEPROM command write sequences or aborting EEPROM

operations

3.4.1.1

Writing the ECLKDIV Register

Prior to issuing any EEPROM command after a reset, the user is required to write the ECLKDIV register

to divide the oscillator clock down to within the 150 kHz to 200 kHz range. Since the program and erase

timings are also a function of the bus clock, the ECLKDIV determination must take this information into

account.

If we deﬁne:

•

ECLK as the clock of the EEPROM timing control block

Tbus as the period of the bus clock

INT(x) as taking the integer part of x (e.g., INT(4.323)=4)

then ECLKDIV register bits PRDIV8 and EDIV[5:0] are to be set as described in Figure 3-14.

For example, if the oscillator clock frequency is 4 MHz and the bus clock frequency is 40 MHz, ECLKDIV

bits EDIV[5:0] should be set to 0x14 (010100) and bit PRDIV8 set to 0. The resulting EECLK frequency

is then 190 kHz. As a result, the EEPROM program and erase algorithm timings are increased over the

optimum target by:

(200 – 190) ⁄ 200 × 100 = 5%

If the oscillator clock frequency is 16 MHz and the bus clock frequency is 40 MHz, ECLKDIV bits

EDIV[5:0] should be set to 0x0A (001010) and bit PRDIV8 set to 1. The resulting EECLK frequency is

then 182 kHz. In this case, the EEPROM program and erase algorithm timings are increased over the

optimum target by:

(200 – 182) ⁄ 200 × 100 = 9%

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

CAUTION

Program and erase command execution time will increase proportionally

with the period of EECLK. Because of the impact of clock synchronization

on the accuracy of the functional timings, programming or erasing the

EEPROM memory cannot be performed if the bus clock runs at less than 1

MHz. Programming or erasing the EEPROM memory with EECLK < 150

kHz should be avoided. Setting ECLKDIV to a value such that EECLK <

150 kHz can destroy the EEPROM memory due to overstress. Setting

ECLKDIV to a value such that (1/EECLK+Tbus) < 5 µs can result in

incomplete programming or erasure of the EEPROM memory cells.

If the ECLKDIV register is written, the EDIVLD bit is set automatically. If the EDIVLD bit is 0, the

ECLKDIV register has not been written since the last reset. If the ECLKDIV register has not been written

to, the EEPROM command loaded during a command write sequence will not execute and the ACCERR

ﬂag in the ESTAT register will set.

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

START

Tbus < 1µs?

ALL COMMANDS IMPOSSIBLE

yes

PRDIV8 = 0 (reset)

oscillator_clock

>12.8 MHz?

yes

PRDIV8 = 1

PRDCLK = oscillator_clock/8

PRDCLK = oscillator_clock

PRDCLK[MHz]*(5+Tbus[µs])

an integer?

EDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs]))

yes

EDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])–1

TRY TO DECREASE Tbus EECLK = (PRDCLK)/(1+EDIV[5:0])

yes

1/EECLK[MHz] + Tbus[ms] > 5

END

AND

EECLK > 0.15 MHz

yes

EDIV[5:0] > 4?

ALL COMMANDS IMPOSSIBLE

Figure 3-14. Determination Procedure for PRDIV8 and EDIV Bits

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

3.4.1.2

Command Write Sequence

The EEPROM command controller is used to supervise the command write sequence to execute program,

erase, erase verify, sector erase abort, and sector modify algorithms.

Before starting a command write sequence, the ACCERR and PVIOL ﬂags in the ESTAT register must be

clear (see Section 3.3.2.6, “EEPROM Status Register (ESTAT)”) and the CBEIF ﬂag should be tested to

determine the state of the address, data and command buffers. If the CBEIF ﬂag is set, indicating the

buffers are empty, a new command write sequence can be started. If the CBEIF ﬂag is clear, indicating the

buffers are not available, a new command write sequence will overwrite the contents of the address, data

and command buffers.

A command write sequence consists of three steps which must be strictly adhered to with writes to the

EEPROM module not permitted between the steps. However, EEPROM register and array reads are

allowed during a command write sequence. The basic command write sequence is as follows:

1. Write to one address in the EEPROM memory.

2. Write a valid command to the ECMD register.

3. Clear the CBEIF ﬂag in the ESTAT register by writing a 1 to CBEIF to launch the command.

The address written in step 1 will be stored in the EADDR registers and the data will be stored in the

EDATA registers. If the CBEIF ﬂag in the ESTAT register is clear when the ﬁrst EEPROM array write

occurs, the contents of the address and data buffers will be overwritten and the CBEIF ﬂag will be set.

When the CBEIF ﬂag is cleared, the CCIF ﬂag is cleared on the same bus cycle by the EEPROM command

controller indicating that the command was successfully launched. For all command write sequences

except sector erase abort, the CBEIF ﬂag will set four bus cycles after the CCIF ﬂag is cleared indicating

that the address, data, and command buffers are ready for a new command write sequence to begin. For

sector erase abort operations, the CBEIF ﬂag will remain clear until the operation completes. Except for

the sector erase abort command, a buffered command will wait for the active operation to be completed

before being launched. The sector erase abort command is launched when the CBEIF ﬂag is cleared as part

of a sector erase abort command write sequence. Once a command is launched, the completion of the

command operation is indicated by the setting of the CCIF ﬂag in the ESTAT register. The CCIF ﬂag will

set upon completion of all active and buffered commands.

3.4.2

EEPROM Commands

Table 3-10 summarizes the valid EEPROM commands along with the effects of the commands on the

EEPROM block.

Table 3-10. EEPROM Command Description

ECMDB

Command

Function on EEPROM Memory

0x05

Erase

Verify

Verify all memory bytes in the EEPROM block are erased. If the EEPROM block is erased, the

BLANK ﬂag in the ESTAT register will set upon command completion.

0x20

0x40

Program

Program a word (two bytes) in the EEPROM block.

Sector

Erase

Erase all four memory bytes in a sector of the EEPROM block.

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

Table 3-10. EEPROM Command Description

ECMDB

Command

Function on EEPROM Memory

0x41

Mass

Erase

Erase all memory bytes in the EEPROM block. A mass erase of the full EEPROM block is only

possible when EPOPEN and EPDIS bits in the EPROT register are set prior to launching the

command.

0x47

0x60

Sector Erase

Abort

Abort the sector erase operation. The sector erase operation will terminate according to a set

procedure. The EEPROM sector should not be considered erased if the ACCERR ﬂag is set

upon command completion.

Sector

Modify

Erase all four memory bytes in a sector of the EEPROM block and reprogram the addressed

word.

CAUTION

An EEPROM word (2 bytes) must be in the erased state before being

programmed. Cumulative programming of bits within a word is not allowed.

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

3.4.2.1

Erase Verify Command

The erase verify operation will verify that the EEPROM memory is erased.

An example ﬂow to execute the erase verify operation is shown in Figure 3-15. The erase verify command

write sequence is as follows:

1. Write to an EEPROM address to start the command write sequence for the erase verify command.

The address and data written will be ignored.

2. Write the erase verify command, 0x05, to the ECMD register.

3. Clear the CBEIF ﬂag in the ESTAT register by writing a 1 to CBEIF to launch the erase verify

command.

After launching the erase verify command, the CCIF ﬂag in the ESTAT register will set after the operation

has completed unless a new command write sequence has been buffered. The number of bus cycles

required to execute the erase verify operation is equal to the number of words in the EEPROM memory

plus 14 bus cycles as measured from the time the CBEIF ﬂag is cleared until the CCIF ﬂag is set. Upon

completion of the erase verify operation, the BLANK ﬂag in the ESTAT register will be set if all addresses

in the EEPROM memory are veriﬁed to be erased. If any address in the EEPROM memory is not erased,

the erase verify operation will terminate and the BLANK ﬂag in the ESTAT register will remain clear.

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

START

Read: ECLKDIV register

Clock Register

EDIVLD

Written

NOTE: ECLKDIV needs to

be set once after each reset.

Set?

Check

yes

Write: ECLKDIV register

Read: ESTAT register

Address, Data,

Command

Buffer Empty Check

CBEIF

Set?

yes

ACCERR/

PVIOL

Set?

yes

Access Error and

Protection Violation

Check

Write: ESTAT register

Clear ACCERR/PVIOL 0x30

Write: EEPROM Address

and Dummy Data

NOTE: command write sequence

aborted by writing 0x00 to

ESTAT register.

Write: ECMD register

Erase Verify Command 0x05

NOTE: command write sequence

aborted by writing 0x00 to

ESTAT register.

Write: ESTAT register

Clear CBEIF 0x80

Read: ESTAT register

Bit Polling for

Command Completion

Check

CCIF

Set?

yes

Erase Verify

Status

BLANK

Set?

yes

EEPROM Memory

Erased

EEPROM Memory

Not Erased

EXIT

Figure 3-15. Example Erase Verify Command Flow

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

3.4.2.2

Program Command

The program operation will program a previously erased word in the EEPROM memory using an

embedded algorithm.

An example ﬂow to execute the program operation is shown in Figure 3-16. The program command write

sequence is as follows:

1. Write to an EEPROM block address to start the command write sequence for the program

command. The data written will be programmed to the address written.

2. Write the program command, 0x20, to the ECMD register.

3. Clear the CBEIF ﬂag in the ESTAT register by writing a 1 to CBEIF to launch the program

command.

If a word to be programmed is in a protected area of the EEPROM memory, the PVIOL ﬂag in the ESTAT

launched, the CCIF ﬂag in the ESTAT register will set after the program operation has completed unless a

new command write sequence has been buffered.

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

START

Read: ECLKDIV register

Clock Register

EDIVLD

Written

NOTE: ECLKDIV needs to

be set once after each reset.

Set?

Check

yes

Write: ECLKDIV register

Read: ESTAT register

Address, Data,

Command

Buffer Empty Check

CBEIF

Set?

yes

ACCERR/

PVIOL

Set?

yes

Access Error and

Protection Violation

Check

Write: ESTAT register

Clear ACCERR/PVIOL 0x30

Write: EEPROM Address

and program Data

NOTE: command write sequence

aborted by writing 0x00 to

ESTAT register.

Write: ECMD register

Program Command 0x20

NOTE: command write sequence

aborted by writing 0x00 to

ESTAT register.

Write: ESTAT register

Clear CBEIF 0x80

Read: ESTAT register

Bit Polling for

Buffer Empty

Check

CBEIF

Set?

yes

Sequential

Programming

Decision

yes

Word?

Read: ESTAT register

Bit Polling for

Command Completion

Check

CCIF

Set?

yes

EXIT

Figure 3-16. Example Program Command Flow

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

3.4.2.3

Sector Erase Command

The sector erase operation will erase both words in a sector of EEPROM memory using an embedded

algorithm.

An example ﬂow to execute the sector erase operation is shown in Figure 3-17. The sector erase command

write sequence is as follows:

1. Write to an EEPROM memory address to start the command write sequence for the sector erase

command. The EEPROM address written determines the sector to be erased while global address

bits [1:0] and the data written are ignored.

2. Write the sector erase command, 0x40, to the ECMD register.

3. Clear the CBEIF ﬂag in the ESTAT register by writing a 1 to CBEIF to launch the sector erase

command.

If an EEPROM sector to be erased is in a protected area of the EEPROM memory, the PVIOL ﬂag in the

ESTAT register will set and the sector erase command will not launch. Once the sector erase command has

successfully launched, the CCIF ﬂag in the ESTAT register will set after the sector erase operation has

completed unless a new command write sequence has been buffered.

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

START

Read: ECLKDIV register

Clock Register

EDIVLD

Written

NOTE: ECLKDIV needs to

be set once after each reset.

Set?

Check

yes

Write: ECLKDIV register

Read: ESTAT register

Address, Data,

Command

Buffer Empty Check

CBEIF

Set?

yes

ACCERR/

PVIOL

Set?

yes

Access Error and

Protection Violation

Check

Write: ESTAT register

Clear ACCERR/PVIOL 0x30

Write: EEPROM Sector Address

and Dummy Data

NOTE: command write sequence

aborted by writing 0x00 to

ESTAT register.

Write: ECMD register

Sector Erase Command 0x40

NOTE: command write sequence

aborted by writing 0x00 to

ESTAT register.

Write: ESTAT register

Clear CBEIF 0x80

Read: ESTAT register

Bit Polling for

Command Completion

Check

CCIF

Set?

yes

EXIT

Figure 3-17. Example Sector Erase Command Flow

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

3.4.2.4

Mass Erase Command

The mass erase operation will erase all addresses in an EEPROM block using an embedded algorithm.

An example ﬂow to execute the mass erase operation is shown in Figure 3-18. The mass erase command

write sequence is as follows:

1. Write to an EEPROM memory address to start the command write sequence for the mass erase

command. The address and data written will be ignored.

2. Write the mass erase command, 0x41, to the ECMD register.

3. Clear the CBEIF ﬂag in the ESTAT register by writing a 1 to CBEIF to launch the mass erase

command.

If the EEPROM memory to be erased contains any protected area, the PVIOL ﬂag in the ESTAT register

will set and the mass erase command will not launch. Once the mass erase command has successfully

launched, the CCIF ﬂag in the ESTAT register will set after the mass erase operation has completed unless

a new command write sequence has been buffered.

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

START

Read: ECLKDIV register

Clock Register

EDIVLD

Written

NOTE: ECLKDIV needs to

be set once after each reset.

Set?

Check

yes

Write: ECLKDIV register

Read: ESTAT register

Address, Data,

Command

Buffer Empty Check

CBEIF

Set?

yes

ACCERR/

PVIOL

Set?

yes

Access Error and

Protection Violation

Check

Write: ESTAT register

Clear ACCERR/PVIOL 0x30

Write: EEPROM Address

and Dummy Data

NOTE: command write sequence

aborted by writing 0x00 to

ESTAT register.

Write: ECMD register

Mass Erase Command 0x41

NOTE: command write sequence

aborted by writing 0x00 to

ESTAT register.

Write: ESTAT register

Clear CBEIF 0x80

Read: ESTAT register

Bit Polling for

Command Completion

Check

CCIF

Set?

yes

EXIT

Figure 3-18. Example Mass Erase Command Flow

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

3.4.2.5

Sector Erase Abort Command

The sector erase abort operation will terminate the active sector erase or sector modify operation so that

other sectors in an EEPROM block are available for read and program operations without waiting for the

sector erase or sector modify operation to complete.

An example ﬂow to execute the sector erase abort operation is shown in Figure 3-19. The sector erase abort

command write sequence is as follows:

1. Write to any EEPROM memory address to start the command write sequence for the sector erase

abort command. The address and data written are ignored.

2. Write the sector erase abort command, 0x47, to the ECMD register.

3. Clear the CBEIF ﬂag in the ESTAT register by writing a 1 to CBEIF to launch the sector erase abort

command.

If the sector erase abort command is launched resulting in the early termination of an active sector erase

or sector modify operation, the ACCERR ﬂag will set once the operation completes as indicated by the

CCIF ﬂag being set. The ACCERR ﬂag sets to inform the user that the EEPROM sector may not be fully

erased and a new sector erase or sector modify command must be launched before programming any

location in that speciﬁc sector. If the sector erase abort command is launched but the active sector erase or

sector modify operation completes normally, the ACCERR ﬂag will not set upon completion of the

operation as indicated by the CCIF ﬂag being set. If the sector erase abort command is launched after the

sector modify operation has completed the sector erase step, the program step will be allowed to complete.

The maximum number of cycles required to abort a sector erase or sector modify operation is equal to four

EECLK periods (see Section 3.4.1.1, “Writing the ECLKDIV Register”) plus ﬁve bus cycles as measured

from the time the CBEIF ﬂag is cleared until the CCIF ﬂag is set.

NOTE

Since the ACCERR bit in the ESTAT register may be set at the completion

of the sector erase abort operation, a command write sequence is not

allowed to be buffered behind a sector erase abort command write sequence.

The CBEIF ﬂag will not set after launching the sector erase abort command

to indicate that a command should not be buffered behind it. If an attempt is

made to start a new command write sequence with a sector erase abort

operation active, the ACCERR ﬂag in the ESTAT register will be set. A new

command write sequence may be started after clearing the ACCERR ﬂag, if

set.

NOTE

The sector erase abort command should be used sparingly since a sector

erase operation that is aborted counts as a complete program/erase cycle.

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

Execute Sector Erase/Modify Command Flow

Read: ESTAT register

Erase

Abort

Needed?

Bit Polling for

Command

Completion Check

CCIF

Set?

yes

Sector Erase

Completed

EXIT

Write: Dummy EEPROM Address

and Dummy Data

NOTE: command write sequence

aborted by writing 0x00 to

ESTAT register.

Write: ECMD register

Sector Erase Abort Cmd 0x47

NOTE: command write sequence

aborted by writing 0x00 to

ESTAT register.

Write: ESTAT register

Clear CBEIF 0x80

Read: ESTAT register

Bit Polling for

Command

Completion Check

CCIF

Set?

yes

ACCERR

Set?

Access

Error Check

Write: ESTAT register

Clear ACCERR 0x10

Sector Erase

or Modify

Aborted

EXIT

or Modify

Completed

Figure 3-19. Example Sector Erase Abort Command Flow

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

3.4.2.6

Sector Modify Command

The sector modify operation will erase both words in a sector of EEPROM memory followed by a

reprogram of the addressed word using an embedded algorithm.

An example ﬂow to execute the sector modify operation is shown in Figure 3-20. The sector modify

command write sequence is as follows:

1. Write to an EEPROM memory address to start the command write sequence for the sector modify

command. The EEPROM address written determines the sector to be erased and word to be

reprogrammed while byte address bit 0 is ignored.

2. Write the sector modify command, 0x60, to the ECMD register.

3. Clear the CBEIF ﬂag in the ESTAT register by writing a 1 to CBEIF to launch the sector erase

command.

If an EEPROM sector to be modiﬁed is in a protected area of the EEPROM memory, the PVIOL ﬂag in

the ESTAT register will set and the sector modify command will not launch. Once the sector modify

command has successfully launched, the CCIF ﬂag in the ESTAT register will set after the sector modify

operation has completed unless a new command write sequence has been buffered.

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

START

Read: ECLKDIV register

Clock Register

EDIVLD

Written

NOTE: ECLKDIV needs to

be set once after each reset.

Set?

Check

yes

Write: ECLKDIV register

Read: ESTAT register

Address, Data,

Command

Buffer Empty Check

CBEIF

Set?

yes

ACCERR/

PVIOL

Set?

yes

Access Error and

Protection Violation

Check

Write: ESTAT register

Clear ACCERR/PVIOL 0x30

Write: EEPROM Word Address

and program Data

NOTE: command write sequence

aborted by writing 0x00 to

ESTAT register.

Write: ECMD register

Sector Modify Command 0x60

NOTE: command write sequence

aborted by writing 0x00 to

ESTAT register.

Write: ESTAT register

Clear CBEIF 0x80

Read: ESTAT register

Bit Polling for

Command Completion

Check

CCIF

Set?

yes

EXIT

Figure 3-20. Example Sector Modify Command Flow

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

3.4.3

Illegal EEPROM Operations

The ACCERR ﬂag will be set during the command write sequence if any of the following illegal steps are

performed, causing the command write sequence to immediately abort:

1. Writing to an EEPROM address before initializing the ECLKDIV register.

2. Writing a byte or misaligned word to a valid EEPROM address.

3. Starting a command write sequence while a sector erase abort operation is active.

4. Writing to any EEPROM register other than ECMD after writing to an EEPROM address.

5. Writing a second command to the ECMD register in the same command write sequence.

6. Writing an invalid command to the ECMD register.

7. Writing to an EEPROM address after writing to the ECMD register.

8. Writing to any EEPROM register other than ESTAT (to clear CBEIF) after writing to the ECMD

9. Writing a 0 to the CBEIF ﬂag in the ESTAT register to abort a command write sequence.

The ACCERR ﬂag will not be set if any EEPROM register is read during a valid command write sequence.

The ACCERR ﬂag will also be set if any of the following events occur:

1. Launching the sector erase abort command while a sector erase or sector modify operation is active

which results in the early termination of the sector erase or sector modify operation (see

Section 3.4.2.5, “Sector Erase Abort Command”).

2. The MCU enters stop mode and a command operation is in progress. The operation is aborted

immediately and any pending command is purged (see Section 3.5.2, “Stop Mode”).

If the EEPROM memory is read during execution of an algorithm (CCIF = 0), the read operation will

return invalid data and the ACCERR ﬂag will not be set.

If the ACCERR ﬂag is set in the ESTAT register, the user must clear the ACCERR ﬂag before starting

another command write sequence (see Section 3.3.2.6, “EEPROM Status Register (ESTAT)”).

The PVIOL ﬂag will be set after the command is written to the ECMD register during a command write

sequence if any of the following illegal operations are attempted, causing the command write sequence to

immediately abort:

1. Writing the program command if the address written in the command write sequence was in a

protected area of the EEPROM memory.

2. Writing the sector erase command if the address written in the command write sequence was in a

protected area of the EEPROM memory.

3. Writing the mass erase command to the EEPROM memory while any EEPROM protection is

enabled.

4. Writing the sector modify command if the address written in the command write sequence was in

a protected area of the EEPROM memory.

If the PVIOL ﬂag is set in the ESTAT register, the user must clear the PVIOL ﬂag before starting another

command write sequence (see Section 3.3.2.6, “EEPROM Status Register (ESTAT)”).

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

173

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

3.5

Operating Modes

Wait Mode

3.5.1

If a command is active (CCIF = 0) when the MCU enters the wait mode, the active command and any

buffered command will be completed.

The EEPROM module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled

(see Section 3.8, “Interrupts”).

3.5.2

Stop Mode

If a command is active (CCIF = 0) when the MCU enters the stop mode, the operation will be aborted and,

if the operation is program, sector erase, mass erase, or sector modify, the EEPROM array data being

programmed or erased may be corrupted and the CCIF and ACCERR ﬂags will be set. If active, the high

voltage circuitry to the EEPROM memory will immediately be switched off when entering stop mode.

Upon exit from stop mode, the CBEIF ﬂag is set and any buffered command will not be launched. The

ACCERR ﬂag must be cleared before starting a command write sequence (see Section 3.4.1.2, “Command

Write Sequence”).

NOTE

As active commands are immediately aborted when the MCU enters stop

mode, it is strongly recommended that the user does not use the STOP

instruction during program, sector erase, mass erase, or sector modify

operations.

3.5.3

Background Debug Mode

In background debug mode (BDM), the EPROT register is writable. If the MCU is unsecured, then all

EEPROM commands listed in Table 3-10 can be executed. If the MCU is secured and is in special single

chip mode, the only command available to execute is mass erase.

3.6

EEPROM Module Security

The EEPROM module does not provide any security information to the MCU. After each reset, the

security state of the MCU is a function of information provided by the Flash module (see the speciﬁc FTX

Block Guide).

MC9S12XDP512 Data Sheet, Rev. 2.11

174

Freescale Semiconductor

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

3.6.1

Unsecuring the MCU in Special Single Chip Mode using BDM

Before the MCU can be unsecured in special single chip mode, the EEPROM memory must be erased

using the following method :

•

Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM

secure ROM, send BDM commands to disable protection in the EEPROM module, and execute a

mass erase command write sequence to erase the EEPROM memory.

After the CCIF ﬂag sets to indicate that the EEPROM mass operation has completed and assuming that the

Flash memory has also been erased, reset the MCU into special single chip mode. The BDM secure ROM

will verify that the Flash and EEPROM memory are erased and will assert the UNSEC bit in the BDM

status register. This BDM action will cause the MCU to override the Flash security state and the MCU will

be unsecured. Once the MCU is unsecured, BDM commands will be enabled and the Flash security byte

may be programmed to the unsecure state.

3.7

Resets

3.7.1

EEPROM Reset Sequence

On each reset, the EEPROM module executes a reset sequence to hold CPU activity while loading the

EPROT register from the EEPROM memory according to Table 3-1.

3.7.2

Reset While EEPROM Command Active

If a reset occurs while any EEPROM command is in progress, that command will be immediately aborted.

The state of a word being programmed or the sector / block being erased is not guaranteed.

3.8

Interrupts

The EEPROM module can generate an interrupt when all EEPROM command operations have completed,

when the EEPROM address, data, and command buffers are empty.

Table 3-11. EEPROM Interrupt Sources

Interrupt Source

Interrupt Flag

Local Enable

Global (CCR) Mask

EEPROM address, data, and command buffers empty

CBEIF

CBEIE

I Bit

(ESTAT register)

(ECNFG register)

All EEPROM commands completed

CCIF

CCIE

I Bit

(ESTAT register)

(ECNFG register)

NOTE

Vector addresses and their relative interrupt priority are determined at the

MCU level.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

175

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Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)

3.8.1

Description of EEPROM Interrupt Operation

The logic used for generating interrupts is shown in Figure 3-21.

The EEPROM module uses the CBEIF and CCIF ﬂags in combination with the CBIE and CCIE enable

bits to generate the EEPROM command interrupt request.

CBEIF

CBEIE

EEPROM Command Interrupt Request

CCIF

CCIE

Figure 3-21. EEPROM Interrupt Implementation

For a detailed description of the register bits, refer to Section 3.3.2.4, “EEPROM Conﬁguration Register

(ECNFG)” and Section 3.3.2.6, “EEPROM Status Register (ESTAT)” .

MC9S12XDP512 Data Sheet, Rev. 2.11

176

Freescale Semiconductor

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Chapter 4

Port Integration Module (S12XDP512PIMV2)

4.1

Introduction

The S12XD family port integration module (below referred to as PIM) establishes the interface between

the peripheral modules including the non-multiplexed external bus interface module (S12X_EBI) and the

I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and

multiplexing on shared pins.

This document covers the description of:

•

Port A, B used as address output of the S12X_EBI

Port C, D used as data I/O of the S12X_EBI

Port E associated with the S12X_EBI control signals and the IRQ, XIRQ interrupt inputs

Port K associated with address output and control signals of the S12X_EBI

Port T connected to the Enhanced Capture Timer (ECT) module

Port S associated with 2 SCI and 1 SPI modules

Port M associated with 4 MSCAN modules and 1 SCI module

Port P connected to the PWM and 2 SPI modules — inputs can be used as an external interrupt

source

•

Port H associated with 2 SCI modules — inputs can be used as an external interrupt source

Port J associated with 1 MSCAN, 1 SCI, and 2 IIC modules — inputs can be used as an external

interrupt source

•

Port AD0 and AD1 associated with one 8-channel and one 16-channel ATD module

Most I/O pins can be configured by register bits to select data direction and drive strength, to enable and

select pull-up or pull-down devices. Interrupts can be enabled on specific pins resulting in status flags.

The I/O’s of 2 MSCAN and all 3 SPI modules can be routed from their default location to alternative port

pins.

NOTE

The implementation of the PIM is device dependent. Therefore some

functions are not available on certain derivatives or 112-pin and 80-pin

package options.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

177

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.1.1

Features

A full-featured PIM module includes these distinctive registers:

•

Data and data direction registers for Ports A, B, C, D, E, K, T, S, M, P, H, J, AD0, and AD1 when

used as general-purpose I/O

•

Control registers to enable/disable pull-device and select pull-ups/pull-downs on Ports T, S, M, P,

H, and J on per-pin basis

•

Control registers to enable/disable pull-up devices on Ports AD0, and AD1 on per-pin basis

Single control register to enable/disable pull-ups on Ports A, B, C, D, E, and K on per-port basis

and on BKGD pin

•

Control registers to enable/disable reduced output drive on Ports T, S, M, P, H, J, AD0, and AD1

on per-pin basis

Single control register to enable/disable reduced output drive on Ports A, B, C, D, E, and K on

per-port basis

•

Control registers to enable/disable open-drain (wired-OR) mode on Ports S and M

Control registers to enable/disable pin interrupts on Ports P, H, and J

Interrupt flag register for pin interrupts on Ports P, H, and J

Control register to configure IRQ pin operation

Free-running clock outputs

A standard port pin has the following minimum features:

•

Input/output selection

5V output drive with two selectable drive strengths

5V digital and analog input

Input with selectable pull-up or pull-down device

Optional features:

•

Open drain for wired-OR connections

Interrupt inputs with glitch filtering

Reduced input threshold to support low voltage applications

4.1.2

Block Diagram

Figure 4-1 is a block diagram of the MC9S12XDP512.

•

Signals shown in Bold are not available in 80-pin packages.

Signals shown in Bold-Italics are neither available in 112-pin nor in 80-pin packages.

Shaded labels denote alternative module routing ports.

MC9S12XDP512 Data Sheet, Rev. 2.11

178

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Port Integration Module

PAD23

PAD21

PAD19

PAD17

PAD15

PAD13

PAD11

PAD09

AN15,14

PAD22

PAD20

PAD18

PAD16

PAD14

PAD12

PAD10

PAD08

TXD

RXD

TXD

RXD

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

AN13,12

AN11,10

AN9,8

AN7,6

AN5,4

AN3,2

AN1,0

SCI5

SCI4

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

PAD07

PAD06

PAD05

PAD04

PAD03

PAD02

PAD01

PAD00

TXCAN

RXCAN

SCL

SDA

SCL

PJ7

PJ6

CAN4

IIC0

PJ5

PJ4

PJ2

PJ1

PJ0

IIC1

SDA

TXD

RXD

SCI2

IOC7

IOC6

IOC5

IOC4

IOC3

IOC2

IOC1

IOC0

PT7

PT6

PT5

PT4

PT3

PT2

PT1

PT0

PM7

PM6

PM5

PM4

PM3

PM2

PM1

PM0

TXCAN

RXCAN

TXCAN

RXCAN

TXCAN

RXCAN

TXCAN

RXCAN

TXD

RXD

CAN3

CAN2

CAN1

CAN0

SCI3

PWM7

SCK

PP7

PP6

PP5

PP4

PP3

PP2

PP1

PP0

SPI2

PWM6

PWM5

PWM4

PWM3

PWM2

PWM1

PWM0

MOSI

MISO

SCK

MOSI

MISO

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

ADDR15

ADDR14

ADDR13

ADDR12

ADDR11

ADDR10

ADDR9

SPI1

PS7

PS6

PS5

PS4

PS3

PS2

PS1

PS0

SPI0

ADDR8

SCK

MOSI

MISO

TXD

RXD

TXD

RXD

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

ADDR7

ADDR6

ADDR5

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0/UDS

SCI1

SCI0

BKGD/MODC

ECLKX2/XCLKS

TAGHI/MODB

TAGLO/RE/MODA

ECLK

BKGD

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

DATA15

DATA14

DATA13

DATA12

DATA11

DATA10

DATA9

S12X_EBI

S12X_BDM

S12X_DBG

S12X_INT

LDS/LSTRB

WE/R/W

IRQ

XIRQ

DATA8

PK7

PK6

PK5

PK4

PK3

PK2

PK1

PK0

EWAIT/ROMCTL

NOACC/ADDR22

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

ADDR21

ADRR20

ADDR19

ADDR18

ADDR17

ADDR16

Figure 4-1. MC9S12XDP512 Block Diagram

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

179

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.2

External Signal Description

This section lists and describes the signals that do connect off-chip.

4.2.1

Signal Properties

Table 4-1 shows all the pins and their functions that are controlled by the MC9S12XDP512. Refer to

Section 4.4, “Functional Description” for the availability of the individual pins in the different package

options.

NOTE

If there is more than one function associated with a pin, the priority is

indicated by the position in the table from top (highest priority) to bottom

(lowest priority).

Table 4-1. Pin Functions and Priorities (Sheet 1 of 7)

Pin Function

and Priority

Pin Function

after Reset

Port

Pin Name

I/O

Description

MODC input during RESET

—

BKGD

MODC

BKGD

I/O S12X_BDM communication pin

PA[7:0]

PB[7:1]

PB[0]

ADDR[15:8]

mux

IVD[15:8]

High-order external bus address output

(multiplexed with IVIS data)

Mode

dependent

GPIO

I/O General-purpose I/O

ADDR[7:1]

mux

Low-order external bus address output

(multiplexed with IVIS data)

Mode

dependent

IVD[7:1]

GPIO

I/O General-purpose I/O

ADDR[0]

mux

Low-order external bus address output

(multiplexed with IVIS data)

IVD0

UDS

GPIO

Upper data strobe

I/O General-purpose I/O

PC[7:0]

PD[7:0]

DATA[15:8]

I/O High-order bidirectional data input/output

Conﬁgurable for reduced input threshold

Mode

dependent

GPIO

I/O General-purpose I/O

DATA[7:0]

I/O Low-order bidirectional data input/output

Conﬁgurable for reduced input threshold

Mode

dependent

GPIO

I/O General-purpose I/O

MC9S12XDP512 Data Sheet, Rev. 2.11

180

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-1. Pin Functions and Priorities (Sheet 2 of 7)

Pin Function

and Priority

Pin Function

after Reset

Port

Pin Name

I/O

Description

External clock selection input during RESET

XCLKS

PE[7]

ECLKX2

GPIO

Free-running clock output at Core Clock rate (ECLK x 2)

I/O General-purpose I/O

MODB input during RESET

MODB

Instruction tagging low pin

Conﬁgurable for reduced input threshold

PE[6]

PE[5]

TAGHI

GPIO

I/O General-purpose I/O

MODA input during RESET

Read enable signal

MODA

Instruction tagging low pin

Conﬁgurable for reduced input threshold

TAGLO

GPIO

ECLK

GPIO

I/O General-purpose I/O

Free-running clock output at the Bus Clock rate or

programmable divided in normal modes

Mode

PE[4]

PE[3]

dependent

I/O General-purpose I/O

EROMON bit control input during RESET

Low strobe bar output

EROMCTL

LSTRB

LDS

Lower data strobe

GPIO

R/W

I/O General-purpose I/O

Read/write output for external bus

Write enable signal

PE[2]

GPIO

IRQ

I/O General-purpose I/O

Maskable level- or falling edge-sensitive interrupt input

I/O General-purpose I/O

Non-maskable level-sensitive interrupt input

PE[1]

PE[0]

GPIO

XIRQ

GPIO

I/O General-purpose I/O

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

181

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-1. Pin Functions and Priorities (Sheet 3 of 7)

Pin Function

and Priority

Pin Function

after Reset

Port

Pin Name

I/O

Description

ROMON bit control input during RESET

ROMCTL

External Wait signal

Conﬁgurable for reduced input threshold

PK[7]

EWAIT

GPIO

I/O General-purpose I/O

ADDR[22:20]

mux

Extended external bus address output

(multiplexed with access master output)

Mode

PK[6:4]

PK[3:0]

ACC[2:0]

dependent

GPIO

I/O General-purpose I/O

ADDR[19:16]

mux

Extended external bus address output

(multiplexed with instruction pipe status bits)

IQSTAT[3:0]

GPIO

IOC[7:0]

GPIO

I/O General-purpose I/O

I/O Enhanced Capture Timer Channels 7–0 input/output

I/O General-purpose I/O

PT[7:0]

PS7

GPIO

Serial Peripheral Interface 0 slave select output in master

mode, input in slave mode or master mode.

SS0

I/O

GPIO

SCK0

GPIO

MOSI0

GPIO

MISO0

GPIO

TXD1

GPIO

RXD1

GPIO

TXD0

GPIO

RXD0

GPIO

I/O General-purpose I/O

I/O Serial Peripheral Interface 0 serial clock pin

I/O General-purpose I/O

PS6

PS5

PS4

PS3

PS2

PS1

PS0

I/O Serial Peripheral Interface 0 master out/slave in pin

I/O General-purpose I/O

I/O Serial Peripheral Interface 0 master in/slave out pin

I/O General-purpose I/O

GPIO

Serial Communication Interface 1 transmit pin

I/O General-purpose I/O

Serial Communication Interface 1 receive pin

I/O General-purpose I/O

Serial Communication Interface 0 transmit pin

I/O General-purpose I/O

Serial Communication Interface 0 receive pin

I/O General-purpose I/O

MC9S12XDP512 Data Sheet, Rev. 2.11

182

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-1. Pin Functions and Priorities (Sheet 4 of 7)

Pin Function

and Priority

Pin Function

after Reset

Port

Pin Name

I/O

Description

TXCAN3

TXCAN4

TXD3

MSCAN3 transmit pin

MSCAN4 transmit pin

PM7

Serial Communication Interface 3 transmit pin

GPIO

I/O General-purpose I/O

RXCAN3

RXCAN4

RXD3

MSCAN3 receive pin

MSCAN4 receive pin

PM6

PM5

Serial Communication Interface 3 receive pin

GPIO

I/O General-purpose I/O

TXCAN2

TXCAN0

TXCAN4

MSCAN2 transmit pin

MSCAN0 transmit pin

MSCAN4 transmit pin

Serial Peripheral Interface 0 serial clock pin

SCK0

I/O If CAN0 is routed to PM[3:2] the SPI0 can still be used in

bidirectional master mode.

GPIO

I/O General-purpose I/O

RXCAN2

RXCAN0

RXCAN4

MSCAN2 receive pin

MSCAN0 receive pin

GPIO

MSCAN4 receive pin

PM4

Serial Peripheral Interface 0 master out/slave in pin

MOSI0

I/O If CAN0 is routed to PM[3:2] the SPI0 can still be used in

bidirectional master mode.

GPIO

I/O General-purpose I/O

TXCAN1

TXCAN0

MSCAN1 transmit pin

MSCAN0 transmit pin

PM3

PM2

Serial Peripheral Interface 0 slave select output in master

mode, input for slave mode or master mode.

SS0

I/O

GPIO

RXCAN1

RXCAN0

MISO0

GPIO

I/O General-purpose I/O

MSCAN1 receive pin

MSCAN0 receive pin

I/O Serial Peripheral Interface 0 master in/slave out pin

I/O General-purpose I/O

TXCAN0

GPIO

MSCAN0 transmit pin

I/O General-purpose I/O

MSCAN0 receive pin

PM1

PM0

RXCAN0

GPIO

I/O General-purpose I/O

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

183

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-1. Pin Functions and Priorities (Sheet 5 of 7)

Pin Function

and Priority

Pin Function

after Reset

Port

Pin Name

I/O

Description

PWM7

SCK2

I/O Pulse Width Modulator input/output channel 7

I/O Serial Peripheral Interface 2 serial clock pin

I/O General-purpose I/O with interrupt

PP7

GPIO/KWP7

PWM6

Pulse Width Modulator output channel 6

Serial Peripheral Interface 2 slave select output in master

mode, input for slave mode or master mode.

PP6

SS2

I/O

GPIO/KWP6

PWM5

I/O General-purpose I/O with interrupt

Pulse Width Modulator output channel 5

PP5

PP4

MOSI2

I/O Serial Peripheral Interface 2 master out/slave in pin

I/O General-purpose I/O with interrupt

GPIO/KWP5

PWM4

Pulse Width Modulator output channel 4

MISO2

I/O Serial Peripheral Interface 2 master in/slave out pin

I/O General-purpose I/O with interrupt

GPIO/KWP4

PWM3

GPIO

Pulse Width Modulator output channel 3

Serial Peripheral Interface 1 slave select output in master

mode, input for slave mode or master mode.

PP3

SS1

I/O

GPIO/KWP3

PWM2

I/O General-purpose I/O with interrupt

Pulse Width Modulator output channel 2

PP2

PP1

PP0

SCK1

I/O Serial Peripheral Interface 1 serial clock pin

I/O General-purpose I/O with interrupt

GPIO/KWP2

PWM1

Pulse Width Modulator output channel 1

MOSI1

I/O Serial Peripheral Interface 1 master out/slave in pin

I/O General-purpose I/O with interrupt

GPIO/KWP1

PWM0

Pulse Width Modulator output channel 0

MISO1

I/O Serial Peripheral Interface 1 master in/slave out pin

I/O General-purpose I/O with interrupt

GPIO/KWP0

MC9S12XDP512 Data Sheet, Rev. 2.11

184

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-1. Pin Functions and Priorities (Sheet 6 of 7)

Pin Function

and Priority

Pin Function

after Reset

Port

Pin Name

I/O

Description

Serial Peripheral Interface 2 slave select output in master

mode, input for slave mode or master mode

SS2

I/O

PH7

TXD5

GPIO/KWH7

SCK2

Serial Communication Interface 5 transmit pin

I/O General-purpose I/O with interrupt

I/O Serial Peripheral Interface 2 serial clock pin

PH6

PH5

RXD5

Serial Communication Interface 5 receive pin

GPIO/KWH6

MOSI2

I/O General-purpose I/O with interrupt

I/O Serial Peripheral Interface 2 master out/slave in pin

TXD4

Serial Communication Interface 4 transmit pin

GPIO/KWH5

MISO2

I/O General-purpose I/O with interrupt

I/O Serial Peripheral Interface 2 master in/slave out pin

GPIO

PH4

PH3

RXD4

Serial Communication Interface 4 receive pin

GPIO/KWH4

I/O General-purpose I/O with interrupt

Serial Peripheral Interface 1 slave select output in master

mode, input for slave mode or master mode.

SS1

I/O

GPIO/KWH3

SCK1

I/O General-purpose I/O with interrupt

I/O Serial Peripheral Interface 1 serial clock pin

I/O General-purpose I/O with interrupt

PH2

PH1

PH0

GPIO/KWH2

MOSI1

I/O Serial Peripheral Interface 1 master out/slave in pin

I/O General-purpose I/O with interrupt

GPIO/KWH1

MISO1

I/O Serial Peripheral Interface 1 master in/slave out pin

I/O General-purpose I/O with interrupt

GPIO/KWH0

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

185

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-1. Pin Functions and Priorities (Sheet 7 of 7)

Pin Function

and Priority

Pin Function

after Reset

Port

Pin Name

I/O

Description

TXCAN4

SCL0

MSCAN4 transmit pin

Inter Integrated Circuit 0 serial clock line

MSCAN0 transmit pin

PJ7

TXCAN0

GPIO/KWJ7

RXCAN4

SDA0

I/O General-purpose I/O with interrupt

MSCAN4 receive pin

I/O Inter Integrated Circuit 0 serial data line

MSCAN0 receive pin

I/O General-purpose I/O with interrupt

PJ6

RXCAN0

GPIO/KWJ6

SCL1

Inter Integrated Circuit 1 serial clock line

Chip select 2

PJ5

PJ4

CS2

GPIO/KWJ7

SDA1

I/O General-purpose I/O with interrupt

GPIO

I/O Inter Integrated Circuit 1 serial data line

CS0

Chip select 0

I/O General-purpose I/O with interrupt

Chip select 1

I/O General-purpose I/O with interrupt

Serial Communication Interface 2 transmit pin

I/O General-purpose I/O with interrupt

GPIO/KWJ6

CS1

PJ2

PJ1

GPIO/KWJ2

TXD2

GPIO/KWJ1

RXD2

Serial Communication Interface 2 receive pin

Chip select 3

PJ0

CS3

GPIO/KWJ0

GPIO

I/O General-purpose I/O with interrupt

I/O General-purpose I/O

AD0

AD1

PAD[07:00]

PAD[23:08]

GPIO

AN[7:0]

GPIO

ATD0 analog inputs

I/O General-purpose I/O

ATD1 analog inputs

AN[15:0]

Function active when RESET asserted.

Only available in emulation modes or in Special Test Mode with IVIS on.

Refer also to Table 4-70 and S12X_EBI section.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3

Memory Map and Register Deﬁnition

This section provides a detailed description of all MC9S12XDP512 registers.

4.3.1

Module Memory Map

Table 4-2 shows the register map of the port integration module.

Table 4-2. PIM Memory Map (Sheet 1 of 3)

Address

Use

Port A Data Register (PORTA)

Access

0x0000

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

0x0008

0x0009

Read / Write

Port B Data Register (PORTB)

Port A Data Direction Register (DDRA)

Port B Data Direction Register (DDRB)

Port C Data Register (PORTC)

Port D Data Register (PORTD)

Port C Data Direction Register (DDRC)

Port D Data Direction Register (DDRD)

Port E Data Register (PORTE)

Read / Write

—

Port E Data Direction Register (DDRE)

Non-PIM Address Range

0x000A

0x000B

0x000C

0x000D

Pull-up Up Control Register (PUCR)

Reduced Drive Register (RDRIV)

Non-PIM Address Range

Read / Write

—

0x000E

0x001B

0x001C

0x001D

0x001E

0x001F

ECLK Control Register (ECLKCTL)

PIM Reserved

Read / Write

—

IRQ Control Register (IRQCR)

PIM Reserved

Read / Write

—

0x0020

Non-PIM Address Range

0x0031

0x0032

0x0033

Port K Data Register (PORTK)

Port K Data Direction Register (DDRK)

Non-PIM Address Range

Read / Write

—

0x0034

0x023F

0x0240

Port T Data Register (PTT)

Read / Write

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-2. PIM Memory Map (Sheet 2 of 3)

Address

Use

Access

0x0241

0x0242

0x0243

0x0244

0x0245

0x0246

0x0247

0x0248

0x0249

0x024A

0x024B

0x024C

0x024D

0x024E

0x024F

0x0250

0x0251

0x0252

0x0253

0x0254

0x0255

0x0256

0x0257

0x0258

0x0259

0x025A

0x025B

0x025C

0x025D

0x025E

0x025F

0x0260

0x0261

0x0262

0x0263

Port T Input Register (PTIT)

Read

Port T Data Direction Register (DDRT)

Port T Reduced Drive Register (RDRT)

Port T Pull Device Enable Register (PERT)

Port T Polarity Select Register (PPST)

Reserved

Read / Write

—

Reserved

—

Port S Data Register (PTS)

Read / Write

Read

Port S Input Register (PTIS)

Port S Data Direction Register (DDRS)

Port S Reduced Drive Register (RDRS)

Port S Pull Device Enable Register (PERS)

Port S Polarity Select Register (PPSS)

Port S Wired-OR Mode Register (WOMS)

Reserved

Read / Write

—

Port M Data Register (PTM)

Read / Write

Read

Port M Input Register (PTIM)

Port M Data Direction Register (DDRM)

Port M Reduced Drive Register (RDRM)

Port M Pull Device Enable Register (PERM)

Port M Polarity Select Register (PPSM)

Port M Wired-OR Mode Register (WOMM)

Module Routing Register (MODRR)

Port P Data Register (PTP)

Read / Write

Read

Port P Input Register (PTIP)

Port P Data Direction Register (DDRP)

Port P Reduced Drive Register (RDRP)

Port P Pull Device Enable Register (PERP)

Port P Polarity Select Register (PPSP)

Port P Interrupt Enable Register (PIEP)

Port P Interrupt Flag Register (PIFP)

Port H Data Register (PTH)

Read / Write

Read

Port H Input Register (PTIH)

Port H Data Direction Register (DDRH)

Port H Reduced Drive Register (RDRH)

Read / Write

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-2. PIM Memory Map (Sheet 3 of 3)

Address

Use

Access

0x0264

0x0265

0x0266

0x0267

0x0268

0x0269

0x026A

0x026B

0x026C

0x026D

0x026E

0x026F

0x0270

0x0271

0x0272

0x0273

0x0274

0x0275

0x0276

0x0277

0x0278

0x0279

0x027A

0x027B

0x027C

0x027D

0x027E

0x027F

Port H Pull Device Enable Register (PERH)

Port H Polarity Select Register (PPSH)

Port H Interrupt Enable Register (PIEH)

Port H Interrupt Flag Register (PIFH)

Port J Data Register (PTJ)

Read / Write

Read

Port J Input Register (PTIJ)

Port J Data Direction Register (DDRJ)

Port J Reduced Drive Register (RDRJ)

Port J Pull Device Enable Register (PERJ)

Port J Polarity Select Register (PPSJ)

Port J Interrupt Enable Register (PIEJ)

Port J Interrupt Flag Register (PIFJ)

Reserved

Read / Write

—

Port AD0 Data Register 1 (PT1AD0)

Reserved

Read / Write

—

Port AD0 Data Direction Register 1 (DDR1AD0)

Reserved

Read / Write

—

Port AD0 Reduced Drive Register 1 (RDR1AD0)

Reserved

Read / Write

—

Port AD0 Pull Up Enable Register 1 (PER1AD0)

Port AD1 Data Register 0 (PT0AD1)

Port AD1 Data Register 1 (PT1AD1)

Port AD1 Data Direction Register 0 (DDR0AD1)

Port AD1 Data Direction Register 1 (DDR1AD1)

Port AD1 Reduced Drive Register 0 (RDR0AD1)

Port AD1 Reduced Drive Register 1 (RDR1AD1)

Port AD1 Pull Up Enable Register 0 (PER0AD1)

Port AD1 Pull Up Enable Register 1 (PER1AD1)

Read / Write

Write access not applicable for one or more register bits. Refer to Section 4.3.2, “Register

Descriptions”.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

189

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2

Table 4-3 summarizes the effect on the various configuration bits, data direction (DDR), output level (IO),

reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the ports.

The configuration bit PS is used for two purposes:

1. Conﬁgure the sensitive interrupt edge (rising or falling), if interrupt is enabled.

2. Select either a pull-up or pull-down device if PE is active.

Table 4-3. Pin Conﬁguration Summary

DDR

RDR

Function

Pull Device

Interrupt

Input

Disabled

Pull Up

Disabled

Pull Down

Disabled

Pull Up

Disabled

Falling edge

Rising edge

Falling edge

Rising edge

Disabled

Pull Down

Disabled

Output, full drive to 0

Output, full drive to 1

Disabled

Output, reduced drive to 0

Output, reduced drive to 1

Output, full drive to 0

Disabled

Falling edge

Rising edge

Falling edge

Rising edge

Output, full drive to 1

Output, reduced drive to 0

Output, reduced drive to 1

Always “0” on Port A, B, C, D, E, K, AD0, and AD1.

Applicable only on Port P, H, and J.

NOTE

All register bits in this module are completely synchronous to internal

clocks during a register read.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Name

Bit 7

Bit 0

0x0000

PORTA

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

0x0001

PORTB

PB7

DDRA7

DDRB7

PC7

PB6

DDRA6

DDRB6

PC6

PB5

DDRA5

DDRB5

PC5

PB4

DDRA4

DDRB4

PC4

PB3

DDRA3

DDRB3

PC3

PB2

DDRA2

DDRB2

PC2

PB1

DDRA1

DDRB1

PC1

PB0

DDRA0

DDRB0

PC0

0x0002

DDRA

0x0003

DDRB

0x0004

PORTC

0x0005

PORTD

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

0x0006

DDRC

DDRC7

DDRD7

PE7

DDRC6

DDRD6

PE6

DDRC5

DDRD5

PE5

DDRC4

DDRD4

PE4

DDRC3

DDRD3

PE3

DDRC2

DDRD2

PE2

DDRC1

DDRC0

0x0007

DDRD

DDRD1

PE1

DDRD0

PE0

0x0008

PORTE

0x0009

DDRE

DDRE7

DDRE6

DDRE5

DDRE4

DDRE3

DDRE2

0x000A

0x000B

Non-PIM

Address

Range

Non-PIM Address Range

0x000C

PUCR

PUPKE

RDPK

BKPUE

PUPEE

RDPE

PUPDE

RDPD

PUPCE

RDPC

PUPBE

RDPB

PUPAE

RDPA

0x000D

RDRIV

= Unimplemented or Reserved

Figure 4-2. PIM Register Summary (Sheet 1 of 6)

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

191

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Bit 7

Bit 0

Name

0x000E–

0x001B

Non-PIM

Address

Range

Non-PIM Address Range

0x001C

ECLKCTL

NECLK

NCLKX2

EDIV1

EDIV0

0x001D

Reserved

0x001E

IRQCR

IRQE

IRQEN

0x001F

Reserved

0x0020–

0x0031

Non-PIM

Address

Range

Non-PIM Address Range

0x0032

PORTK

PK7

PK6

PK5

PK4

PK3

PK2

PK1

PK0

0x0033

DDRK

DDRK7

DDRK6

DDRK5

DDRK4

DDRK3

DDRK2

DDRK1

DDRK0

0x0034–

9x023F

Non-PIM

Address

Range

Non-PIM Address Range

0x0240

PTT

PTT7

PTT6

PTT5

PTT4

PTT3

PTT2

PTT1

PTT0

0x0241

PTIT

PTIT7

PTIT6

PTIT5

PTIT4

PTIT3

PTIT2

PTIT1

PTIT0

0x0242

DDRT

DDRT7

RDRT7

DDRT6

RDRT6

DDRT5

RDRT5

DDRT4

RDRT4

DDRT3

RDRT3

DDRT2

RDRT2

DDRT1

RDRT1

DDRT0

RDRT0

0x0243

RDRT

= Unimplemented or Reserved

Figure 4-2. PIM Register Summary (Sheet 2 of 6)

MC9S12XDP512 Data Sheet, Rev. 2.11

192

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Name

Bit 7

Bit 0

0x0244

PERT

PERT7

PERT6

PERT5

PERT4

PERT3

PERT2

PERT1

PERT0

0x0245

PPST

PPST7

PPST6

PPST5

PPST4

PPST3

PPST2

PPST1

PPST0

0x0246

Reserved

0x0247

Reserved

0x0248

PTS

PTS7

PTS6

PTS5

PTS4

PTS3

PTS2

PTS1

PTS0

0x0249

PTIS

PTIS7

PTIS6

PTIS5

PTIS4

PTIS3

PTIS2

PTIS1

PTIS0

0x024A

DDRS

DDRS7

RDRS7

PERS7

PPSS7

DDRS6

RDRS6

PERS6

PPSS6

DDRS5

RDRS5

PERS5

PPSS5

DDRS4

RDRS4

PERS4

PPSS4

DDRS3

RDRS3

PERS3

PPSS3

DDRS2

RDRS2

PERS2

PPSS2

DDRS1

RDRS1

PERS1

PPSS1

DDRS0

RDRS0

PERS0

PPSS0

0x024B

RDRS

0x024C

PERS

0x024D

PPSS

0x024E

WOMS

WOMS7

WOMS6

WOMS5

WOMS4

WOMS3

WOMS2

WOMS1

WOMS0

0x024F

Reserved

0x0250

PTM

PTM7

PTM6

PTM5

PTM4

PTM3

PTM2

PTM1

PTM0

0x0251

PTIM

PTIM7

PTIM6

PTIM5

PTIM4

PTIM3

PTIM2

PTIM1

PTIM0

0x0252

DDRM

DDRM7

DDRM6

DDRM5

DDRM4

DDRM3

DDRM2

DDRM1

DDRM0

= Unimplemented or Reserved

Figure 4-2. PIM Register Summary (Sheet 3 of 6)

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

193

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Bit 7

Bit 0

Name

0x0253

RDRM

RDRM7

PERM7

PPSM7

RDRM6

PERM6

PPSM6

WOMM6

MODRR6

RDRM5

PERM5

PPSM5

WOMM5

MODRR5

RDRM4

PERM4

PPSM4

WOMM4

MODRR4

RDRM3

PERM3

PPSM3

WOMM3

MODRR3

RDRM2

PERM2

PPSM2

WOMM2

MODRR2

RDRM1

PERM1

PPSM1

WOMM1

MODRR1

RDRM0

PERM0

PPSM0

WOMM0

MODRR0

0x0254

PERM

0x0255

PPSM

0x0256

WOMM

WOMM7

0x0257

MODRR

0x0258

PTP

PTP7

PTP6

PTP5

PTP4

PTP3

PTP2

PTP1

PTP0

0x0259

PTIP

PTIP7

PTIP6

PTIP5

PTIP4

PTIP3

PTIP2

PTIP1

PTIP0

0x025A

DDRP

DDRP7

RDRP7

PERP7

PPSP7

PIEP7

DDRP6

RDRP6

PERP6

PPSP6

PIEP6

DDRP5

RDRP5

PERP5

PPSP5

PIEP5

DDRP4

RDRP4

PERP4

PPSP4

PIEP4

DDRP3

RDRP3

PERP3

PPSP3

PIEP3

DDRP2

RDRP2

PERP2

PPSP2

PIEP2

DDRP1

RDRP1

PERP1

PPSP1

PIEP1

DDRP0

RDRP0

PERP0

PPSP0

PIEP0

0x025B

RDRP

0x025C

PERP

0x025D

PPSP

0x025E

PIEP

0x025F

PIFP

PIFP7

PIFP6

PIFP5

PIFP4

PIFP3

PIFP2

PIFP1

PIFP0

0x0260

PTH

PTH7

PTH6

PTH5

PTH4

PTH3

PTH2

PTH1

PTH0

0x0261

PTIH

PTIH7

PTIH6

PTIH5

PTIH4

PTIH3

PTIH2

PTIH1

PTIH0

= Unimplemented or Reserved

Figure 4-2. PIM Register Summary (Sheet 4 of 6)

MC9S12XDP512 Data Sheet, Rev. 2.11

194

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Name

Bit 7

Bit 0

0x0262

DDRH

DDRH7

DDRH6

DDRH5

DDRH4

DDRH3

DDRH2

DDRH1

DDRH0

0x0263

RDRH

RDRH7

PERH7

PPSH7

PIEH7

PIFH7

RDRH6

PERH6

PPSH6

PIEH6

PIFH6

RDRH5

PERH5

PPSH5

PIEH5

PIFH5

RDRH4

PERH4

PPSH4

PIEH4

PIFH4

RDRH3

PERH3

PPSH3

PIEH3

RDRH2

PERH2

PPSH2

PIEH2

PIFH2

RDRH1

PERH1

PPSH1

PIEH1

PIFH1

RDRH0

PERH0

PPSH0

PIEH0

PIFH0

0x0264

PERH

0x0265

PPSH

0x0266

PIEH

0x0267

PIFH

PIFH3

0x0268

PTJ

PTJ7

PTJ6

PTJ5

PTJ4

PTJ2

PTJ1

PTJ0

0x0269

PTIJ

PTIJ7

PTIJ6

PTIJ5

PTIJ4

PTIJ2

PTIJ1

PTIJ0

0x026A

DDRJ

DDRJ7

RDRJ7

PERJ7

PPSJ7

PIEJ7

DDRJ6

RDRJ6

PERJ6

PPSJ6

PIEJ6

DDRJ5

RDRJ5

PERJ5

PPSJ5

PIEJ5

DDRJ4

RDRJ4

PERJ4

PPSJ4

PIEJ4

DDRJ2

RDRJ2

PERJ2

PPSJ2

PIEJ2

DDRJ1

RDRJ1

PERJ1

PPSJ1

PIEJ1

DDRJ0

RDRJ0

PERJ0

PPSJ0

PIEJ0

0x026B

RDRJ

0x026C

PERJ

0x026D

PPSJ

0x026E

PIEJ

0x026F

PIFJ

PPSJ7

PPSJ6

PPSJ5

PPSJ4

PPSJ2

PPSJ1

PPSJ0

0x0270

Reserved

= Unimplemented or Reserved

Figure 4-2. PIM Register Summary (Sheet 5 of 6)

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

195

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Bit 7

PT1AD07

PT1AD06

PT1AD05

PT1AD04

PT1AD03

PT1AD02

PT1AD01

Bit 0

PT1AD00

Name

0x0271

PT1AD0

0x0272

Reserved

0x0273

Name

DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00

0x0274

Reserved

0x0275

RDR1AD0

RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00

0x0276

Reserved

0x0277

PER1AD0

PER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00

PT0AD123 PT0AD122 PT0AD121 PT0AD120 PT0AD119 PT0AD118 PT0AD117 PT0AD116

0x0278

PT0AD1

0x0279

PT1AD1

PT1AD115 PT1AD114 PT1AD113 PT1AD112 PT1AD111 PT1AD110

PT1AD19

PT1AD18

0x027A

DDR0AD1

DDR0AD123 DDR0AD122 DDR0AD121 DDR0AD120 DDR0AD119 DDR0AD118 DDR0AD117 DDR0AD116

DDR1AD115 DDR1AD114 DDR1AD113 DDR1AD112 DDR1AD111 DDR1AD110 DDR1AD19 DDR1AD18

RDR0AD123 RDR0AD122 RDR0AD121 RDR0AD120 RDR0AD119 RDR0AD118 RDR0AD117 RDR0AD116

RDR1AD115 RDR1AD114 RDR1AD113 RDR1AD112 RDR1AD111 RDR1AD110 RDR1AD19 RDR1AD18

PER0AD123 PER0AD122 PER0AD121 PER0AD120 PER0AD119 PER0AD118 PER0AD117 PER0AD116

PER1AD115 PER1AD114 PER1AD113 PER1AD112 PER1AD111 PER1AD110 PER1AD19 PER1AD18

0x027B

DDR1AD1

0x027C

RDR0AD1

0x027D

RDR1AD1

0x027E

PER0AD1

0x027F

PER1AD1

= Unimplemented or Reserved

Figure 4-2. PIM Register Summary (Sheet 6 of 6)

MC9S12XDP512 Data Sheet, Rev. 2.11

196

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.1

Port A Data Register (PORTA)

0x0000 (PRR)

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Alt. ADDR15

ADDR14

mux

ADDR13

mux

ADDR12

mux

ADDR11

mux

ADDR10

mux

ADDR9

mux

ADDR8

mux

Function

mux

IVD15

IVD14

IVD13

IVD12

IVD11

IVD10

IVD9

IVD8

Reset

Figure 4-3. Port A Data Register (PORTA)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data source is depending on the data direction value.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

Table 4-4. PORTA Field Descriptions

Field

Description

7–0

PA[7:0]

Port A — Port A pins 7–0 are associated with address outputs ADDR15 through ADDR8 respectively in

expanded modes. When this port is not used for external addresses, these pins can be used as general purpose

I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the

port register, otherwise the buffered pin input state is read.

4.3.2.2

Port B Data Register (PORTB)

0x0001 (PRR)

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

Alt.

Function

ADDR0

mux

IVD0

ADDR7

mux

IVD7

ADDR6

mux

IVD6

ADDR5

mux

IVD5

ADDR4

mux

IVD4

ADDR3

mux

IVD3

ADDR2

mux

IVD2

ADDR1

mux

IVD1

UDS

Reset

Figure 4-4. Port B Data Register (PORTB)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data source is depending on the data direction value.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

197

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

Table 4-5. PORTB Field Descriptions

Field

Description

7–0

PB[7:0]

Port B — Port B pins 7–0 are associated with address outputs ADDR7 through ADDR1 respectively in expanded

modes. Pin 0 is associated with output ADDR0 in emulation modes and special test mode and with Upper Data

Select (UDS) in normal expanded mode. When this port is not used for external addresses, these pins can be

used as general purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read

returns the value of the port register, otherwise the buffered pin input state is read.

MC9S12XDP512 Data Sheet, Rev. 2.11

198

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.3

Port A Data Direction Register (DDRA)

0x0002 (PRR)

DDRA7

DDRA6

DDRA5

DDRA4

DDRA3

DDRA2

DDRA1

DDRA0

Reset

Figure 4-5. Port A Data Direction Register (DDRA)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data are read from this register.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

Table 4-6. DDRA Field Descriptions

Field

Description

7–0

Data Direction Port A — This register controls the data direction for port A. When Port A is operating as a general

DDRA[7:0] purpose I/O port, DDRA determines whether each pin is an input or output. A logic level “1” causes the

associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.

0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PORTA after changing the DDRA register.

4.3.2.4

Port B Data Direction Register (DDRB)

0x0003 (PRR)

DDRB7

DDRB6

DDRB5

DDRB4

DDRB3

DDRB2

DDRB1

DDRB0

Reset

Figure 4-6. Port B Data Direction Register (DDRB)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data are read from this register.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-7. DDRB Field Descriptions

Field

Description

7–0

Data Direction Port B — This register controls the data direction for port B. When Port B is operating as a general

DDRB[7:0] purpose I/O port, DDRB determines whether each pin is an input or output. A logic level “1” causes the

associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.

0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PORTB after changing the DDRB register.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.5

Port C Data Register (PORTC)

0x0004 (PRR)

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

Exp.:

DATA15

DATA14

DATA13

DATA12

DATA11

DATA10

DATA9

DATA8

Reset

Figure 4-7. Port C Data Register (PORTC)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data source is depending on the data direction value.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

Table 4-8. PORTC Field Descriptions

Field

Description

7–0

PC[7:0]

Port C — Port C pins 7–0 are associated with data I/O lines DATA15 through DATA8 respectively in expanded

modes. When this port is not used for external data, these pins can be used as general purpose I/O. If the data

direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register,

otherwise the buffered pin input state is read.

4.3.2.6

Port D Data Register (PORTD)

0x0005 (PRR)

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

Exp.:

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

Reset

Figure 4-8. Port D Data Register (PORTD)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data source is depending on the data direction value.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

Table 4-9. PORTD Field Descriptions

Field

Description

7–0

PD[7:0]

Port D — Port D pins 7–0 are associated with data I/O lines DATA7 through DATA0 respectively in expanded

modes. When this port is not used for external data, these pins can be used as general purpose I/O. — If the

data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register,

otherwise the buffered pin input state is read.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.7

Port C Data Direction Register (DDRC)

0x0006 (PRR)

DDRC7

DDRC6

DDRC5

DDRC4

DDRC3

DDRC2

DDRC1

DDRC0

Reset

Figure 4-9. Port C Data Direction Register (DDRC)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data are read from this register.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

Table 4-10. DDRC Field Descriptions

Field

Description

7–0

Data Direction Port C — This register controls the data direction for port C. When Port C is operating as a general

DDRC[7:0] purpose I/O port, DDRC determines whether each pin is an input or output. A logic level “1” causes the

associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.

0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PORTC after changing the DDRC register.

4.3.2.8

Port D Data Direction Register (DDRD)

0x0007 (PRR)

DDRD7

DDRD6

DDRD5

DDRD4

DDRD3

DDRD2

DDRD1

DDRD0

Reset

Figure 4-10. Port D Data Direction Register (DDRD)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data are read from this register.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-11. DDRD Field Descriptions

Field

Description

7–0

Data Direction Port D — This register controls the data direction for port D. When Port D is operating as a general

DDRD[7:0] purpose I/O port, DDRD determines whether each pin is an input or output. A logic level “1” causes the

associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.

0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PORTD after changing the DDRD register.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.9

Port E Data Register (PORTE)

0x0008 (PRR)

PE1

PE0

PE7

PE6

PE5

PE4

PE3

PE2

MODA

TAGLO

EROMCTL

LSTRB

XCLKS

ECLKX2

MODB

TAGHI

R/W

Alt.

Func.

ECLK

IRQ

XIRQ

LDS

Reset

—

= Unimplemented or Reserved

Figure 4-11. Port E Data Register (PORTE)

These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated

pin values.

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data source is depending on the data direction value.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

Table 4-12. PORTE Field Descriptions

Field

Description

7–0

PE[7:0]

Port E — Port E bits 7–0 are associated with external bus control signals and interrupt inputs. These include

mode select (MODB, MODA), E clock, double frequency E clock, Instruction Tagging High and Low (TAGHI,

TAGLO), Read/Write (R/W), Read Enable and Write Enable (RE, WE), Lower Data Select (LDS), IRQ, and XIRQ.

When not used for any of these speciﬁc functions, Port E pins 7–2 can be used as general purpose I/O and

pins 1–0 can be used as general purpose inputs.

If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port

Pins 6 and 5 are inputs with enabled pull-down devices while RESET pin is low.

Pins 7 and 3 are inputs with enabled pull-up devices while RESET pin is low.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.10 Port E Data Direction Register (DDRE)

0x0009 (PRR)

DDRE7

DDRE6

DDRE5

DDRE4

DDRE3

DDRE2

Reset

= Unimplemented or Reserved

Figure 4-12. Port E Data Direction Register (DDRE)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data are read from this register.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

Table 4-13. DDRE Field Descriptions

Field

Description

7–0

Data Direction Port E — his register controls the data direction for port E. When Port E is operating as a general

DDRE[7:2] purpose I/O port, DDRE determines whether each pin is an input or output. A logic level “1” causes the

associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.

Port E bit 1 (associated with IRQ) and bit 0 (associated with XIRQ) cannot be conﬁgured as outputs. Port E, bits

1 and 0, can be read regardless of whether the alternate interrupt function is enabled.

0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PORTE after changing the DDRE register.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.11 S12X_EBI Ports, BKGD, VREGEN Pin Pull-up Control Register (PUCR)

0x000C (PRR)

PUPKE

BKPUE

PUPEE

PUPDE

PUPCE

PUPBE

PUPAE

Reset

= Unimplemented or Reserved

Figure 4-13. S12X_EBI Ports, BKGD, VREGEN Pin Pull-up Control Register (PUCR)

Read: Anytime in single-chip modes.

Write: Anytime, except BKPUE which is writable in special test mode only.

This register is used to enable pull-up devices for the associated ports A, B, C, D, E, and K. Pull-up devices

are assigned on a per-port basis and apply to any pin in the corresponding port that is currently configured

as an input.

Table 4-14. PUCR Field Descriptions

Field

Description

Pull-up Port K Enable

PUPKE

0 Port K pull-up devices are disabled.

1 Enable pull-up devices for Port K input pins.

BKGD and VREGEN Pin Pull-up Enable

BKPUE

0 BKGD and V

pull-up devices are disabled.

REGEN

1 Enable pull-up devices on BKGD and V

pins.

REGEN

Pull-up Port E Enable

PUPEE

0 Port E pull-up devices on bit 7, 4–0 are disabled.

1 Enable pull-up devices for Port E input pins bits 7, 4–0.

Note: Bits 5 and 6 of Port E have pull-down devices which are only enabled during reset. This bit has no effect

on these pins.

Pull-up Port D Enable

PUPDE

0 Port D pull-up devices are disabled.

1 Enable pull-up devices for all Port D input pins.

Pull-up Port C Enable

PUPCE

0 Port C pull-up devices are disabled.

1 Enable pull-up devices for all Port C input pins.

Pull-up Port B Enable

PUPBE

0 Port B pull-up devices are disabled.

1 Enable pull-up devices for all Port B input pins.

Pull-up Port A Enable

PUPAE

0 Port A pull-up devices are disabled.

1 Enable pull-up devices for all Port A input pins.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.12 S12X_EBI Ports Reduced Drive Register (RDRIV)

0x000D (PRR)

RDPK

RDPE

RDPD

RDPC

RDPB

RDPA

Reset

= Unimplemented or Reserved

Figure 4-14. S12X_EBI Ports Reduced Drive Register (RDRIV)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data are read from this register.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

This register is used to select reduced drive for the pins associated with the S12X_EBI ports A, B, C, D,

E, and K. If enabled, the pins drive at about 1/6 of the full drive strength. The reduced drive function is

independent of which function is being used on a particular pin.

The reduced drive functionality does not take effect on the pins in emulation modes.

Table 4-15. RDRIV Field Descriptions

Field

Description

Reduced Drive of Port K

RDPK

0 All port K output pins have full drive enabled.

1 All port K output pins have reduced drive enabled.

Reduced Drive of Port E

RDPE

0 All port E output pins have full drive enabled.

1 All port E output pins have reduced drive enabled.

Reduced Drive of Port D

RDPD

0 All port D output pins have full drive enabled.

1 All port D output pins have reduced drive enabled.

Reduced Drive of Port C

RDPC

0 All port C output pins have full drive enabled.

1 All port C output pins have reduced drive enabled.

Reduced Drive of Port B

RDPB

0 All port B output pins have full drive enabled.

1 All port B output pins have reduced drive enabled.

Reduced Drive of Ports A

RDPA

0 All Port A output pins have full drive enabled.

1 All port A output pins have reduced drive enabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.13 ECLK Control Register (ECLKCTL)

0x001C (PRR)

NECLK

NCLKX2

EDIV1

EDIV0

Reset

Mode

Dependent

Special

Single-Chip

Emulation

Single-Chip

Special

Test

Emulation

Expanded

Normal

Single-Chip

Normal

Expanded

= Unimplemented or Reserved

Figure 4-15. ECLK Control Register (ECLKCTL)

Reset values in emulation modes are identical to those of the target mode.

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data are read from this register.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

The ECLKCTL register is used to control the availability of the free-running clocks and the free-running

clock divider.

Table 4-16. ECLKCTL Field Descriptions

Field

Description

No ECLK — This bit controls the availability of a free-running clock on the ECLK pin. Clock output is always

NECLK

active in emulation modes and if enabled in all other operating modes.

0 ECLK enabled

1 ECLK disabled

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-16. ECLKCTL Field Descriptions (continued)

Field

Description

No ECLKX2 — This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a ﬁxed

NCLKX2

rate of twice the internal bus clock. Clock output is always active in emulation modes and if enabled in all other

operating modes.

0 ECLKX2 is enabled

1 ECLKX2 is disabled

1–0

Free-Running ECLK Divider — These bits determine the rate of the free-running clock on the ECLK pin. The

EDIV[1:0] usage of the bits is shown in Table 4-17. Divider is always disabled in emulation modes and active as

programmed in all other operating modes.

Table 4-17. Free-Running ECLK Clock Rate

EDIV[1:0]

Rate of Free-Running ECLK

ECLK = Bus clock rate

ECLK = Bus clock rate divided by 2

ECLK = Bus clock rate divided by 3

ECLK = Bus clock rate divided by 4

4.3.2.14 IRQ Control Register (IRQCR)

0x001E

IRQE

IRQEN

Reset

= Unimplemented or Reserved

Figure 4-16. IRQ Control Register (IRQCR)

Read: See individual bit descriptions below.

Write: See individual bit descriptions below.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-18. IRQCR Field Descriptions

Field

Description

IRQ Select Edge Sensitive Only

IRQE

Special modes: Read or write anytime.

Normal and emulation modes: Read anytime, write once.

0 IRQ conﬁgured for low level recognition.

1 IRQ conﬁgured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime

IRQE = 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.

External IRQ Enable

IRQEN

Read or write anytime.

0 External IRQ pin is disconnected from interrupt logic.

1 External IRQ pin is connected to interrupt logic.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.15 Port K Data Register (PORTK)

0x0032 (PRR)

PK7

PK6

PK5

PK4

PK3

PK2

PK1

PK0

ROMCTL

EWAIT

ADDR22

mux

NOACC

ADDR19

mux

IQSTAT3

ADDR18

mux

IQSTAT2

ADDR17

mux

IQSTAT1

ADDR16

mux

IQSTAT0

Alt.

Func.

ADDR21

ADDR20

Reset

Figure 4-17. Port K Data Register (PORTK)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data source is depending on the data direction value.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

Table 4-19. PORTK Field Descriptions

Field

Description

7–0

PK[7:0]

Port K — Port K pins 7–0 are associated with external bus control signals and internal memory expansion

emulation pins. These include ADDR22-ADDR16, No-Access (NOACC), External Wait (EWAIT) and instruction

pipe signals IQSTAT3-IQSTAT0. Bits 6-0 carry the external addresses in all expanded modes. In emulation or

special test mode with internal visibility enabled the address is multiplexed with the alternate functions NOACC

and IQSTAT on the respective pins. In single-chip modes the port pins can be used as general-purpose I/O. If

the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port

4.3.2.16 Port K Data Direction Register (DDRK)

0x0033 (PRR)

DDRK7

DDRK6

DDRK5

DDRK4

DDRK3

DDRK2

DDRK1

DDRK0

Reset

Figure 4-18. Port K Data Direction Register (DDRK)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data are read from this register.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

This register controls the data direction for port K. When Port K is operating as a general purpose I/O port,

DDRK determines whether each pin is an input or output. A logic level “1” causes the associated port pin

to be an output and a logic level “0” causes the associated pin to be a high-impedance input.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-20. DDRK Field Descriptions

Field

Description

7–0

Data Direction Port K

DDRK[7:0] 0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PORTK after changing the DDRK register.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.17 Port T Data Register (PTT)

0x0240

PTT7

PTT6

PTT5

PTT4

PTT3

PTT2

PTT1

PTT0

ECT

Reset

IOC7

IOC6

IOC5

IOC4

IOC3

IOC2

IOC1

IOC0

Figure 4-19. Port T Data Register (PTT)

Read: Anytime.

Write: Anytime.

Table 4-21. PTT Field Descriptions

Description

Field

7–0

Port T — Port T bits 7–0 are associated with ECT channels IOC7–IOC0 (refer to ECT section). When not used

PTT[7:0]

with the ECT, these pins can be used as general purpose I/O.

If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port

4.3.2.18 Port T Input Register (PTIT)

0x0241

PTIT7

PTIT6

PTIT5

PTIT4

PTIT3

PTIT2

PTIT1

PTIT0

Reset

—

= Unimplemented or Reserved

Figure 4-20. Port T Input Register (PTIT)

These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated

pin values.

Read: Anytime.

Write: Never, writes to this register have no effect.

Table 4-22. PTIT Field Descriptions

Field

Description

7–0

Port T Input — This register always reads back the buffered state of the associated pins. This can also be used

PTIT[7:0] to detect overload or short circuit conditions on output pins.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.19 Port T Data Direction Register (DDRT)

0x0242

DDRT7

DDRT6

DDRT5

DDRT4

DDRT3

DDRT2

DDRT1

DDRT0

Reset

Figure 4-21. Port T Data Direction Register (DDRT)

Read: Anytime.

Write: Anytime.

This register conﬁgures each port T pin as either input or output.

The ECT forces the I/O state to be an output for each timer port associated with an enabled output compare.

In this case the data direction bits will not change.

The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output compare

is disabled.

The timer input capture always monitors the state of the pin.

Table 4-23. DDRT Field Descriptions

Field

Description

7–0

Data Direction Port T

DDRT[7:0] 0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PTT or PTIT registers, when changing the DDRT register.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.20 Port T Reduced Drive Register (RDRT)

0x0243

RDRT7

RDRT6

RDRT5

RDRT4

RDRT3

RDRT2

RDRT1

RDRT0

Reset

Figure 4-22. Port T Reduced Drive Register (RDRT)

Read: Anytime.

Write: Anytime.

This register configures the drive strength of each port T output pin as either full or reduced. If the port is

used as input this bit is ignored.

Table 4-24. RDRT Field Descriptions

Field

Description

7–0

Reduced Drive Port T

RDRT[7:0] 0 Full drive strength at output.

1 Associated pin drives at about 1/6 of the full drive strength.

4.3.2.21 Port T Pull Device Enable Register (PERT)

0x0244

PERT7

PERT6

PERT5

PERT4

PERT3

PERT2

PERT1

PERT0

Reset

Figure 4-23. Port T Pull Device Enable Register (PERT)

Read: Anytime.

Write: Anytime.

This register configures whether a pull-up or a pull-down device is activated, if the port is used as input.

This bit has no effect if the port is used as output. Out of reset no pull device is enabled.

Table 4-25. PERT Field Descriptions

Field

Description

7–0

Pull Device Enable Port T

PERT[7:0] 0 Pull-up or pull-down device is disabled.

1 Either a pull-up or pull-down device is enabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.22 Port T Polarity Select Register (PPST)

0x0245

PPST7

PPST6

PPST5

PPST4

PPST3

PPST2

PPST1

PPST0

Reset

Figure 4-24. Port T Polarity Select Register (PPST)

Read: Anytime.

Write: Anytime.

This register selects whether a pull-down or a pull-up device is connected to the pin.

Table 4-26. PPST Field Descriptions

Field

Description

7–0

Pull Select Port T

PPST[7:0] 0 A pull-up device is connected to the associated port T pin, if enabled by the associated bit in register PERT

and if the port is used as input.

1 A pull-down device is connected to the associated port T pin, if enabled by the associated bit in register PERT

and if the port is used as input.

4.3.2.23 Port S Data Register (PTS)

0x0248

PTS7

PTS6

PTS5

PTS4

PTS3

PTS2

PTS1

PTS0

SCI/SPI

Reset

SS0

SCK0

MOSI0

MISO0

TXD1

RXD1

TXD0

RXD0

Figure 4-25. Port S Data Register (PTS)

Read: Anytime.

Write: Anytime.

Port S pins 7–4 are associated with the SPI0. The SPI0 pin configuration is determined by several status

bits in the SPI0 module. Refer to SPI section for details. When not used with the SPI0, these pins can be

used as general purpose I/O.

Port S bits 3–0 are associated with the SCI1 and SCI0. The SCI ports associated with transmit pins 3 and

1 are configured as outputs if the transmitter is enabled. The SCI ports associated with receive pins 2 and

0 are configured as inputs if the receiver is enabled. Refer to SCI section for details. When not used with

the SCI, these pins can be used as general purpose I/O.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the

port register, otherwise the buffered pin input state is read.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.24 Port S Input Register (PTIS)

0x0249

PTIS7

PTIS6

PTIS5

PTIS4

PTIS3

PTIS2

PTIS1

PTIS0

Reset

—

= Unimplemented or Reserved

Figure 4-26. Port S Input Register (PTIS)

These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated

pin values.

Read: Anytime.

Write: Never, writes to this register have no effect.

This register always reads back the buffered state of the associated pins. This also can be used to detect

overload or short circuit conditions on output pins.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.25 Port S Data Direction Register (DDRS)

0x024A

DDRS7

DDRS6

DDRS5

DDRS4

DDRS3

DDRS2

DDRS1

DDRS0

Reset

Figure 4-27. Port S Data Direction Register (DDRS)

Read: Anytime.

Write: Anytime.

This register configures each port S pin as either input or output.

If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.

If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin

is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive

channel is enabled.

The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is disabled.

Table 4-27. DDRS Field Descriptions

Field

Description

7–0

Data Direction Port S

DDRS[7:0] 0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PTS or PTIS registers, when changing the DDRS register.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

219

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.26 Port S Reduced Drive Register (RDRS)

0x024B

RDRS7

RDRS6

RDRS5

RDRS4

RDRS3

RDRS2

RDRS1

RDRS0

Reset

Figure 4-28. Port S Reduced Drive Register (RDRS)

Read: Anytime.

Write: Anytime.

This register configures the drive strength of each port S output pin as either full or reduced. If the port is

used as input this bit is ignored.

Table 4-28. RDRS Field Descriptions

Field

Description

7–0

Reduced Drive Port S

RDRS[7:0] 0 Full drive strength at output.

1 Associated pin drives at about 1/6 of the full drive strength.

4.3.2.27 Port S Pull Device Enable Register (PERS)

0x024C

PERS7

PERS6

PERS5

PERS4

PERS3

PERS2

PERS1

PERS0

Reset

Figure 4-29. Port S Pull Device Enable Register (PERS)

Read: Anytime.

Write: Anytime.

This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or

as output in wired-OR (open drain) mode. This bit has no effect if the port is used as push-pull output. Out

of reset a pull-up device is enabled.

Table 4-29. PERS Field Descriptions

Field

Description

7–0

Pull Device Enable Port S

PERS[7:0] 0 Pull-up or pull-down device is disabled.

1 Either a pull-up or pull-down device is enabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.28 Port S Polarity Select Register (PPSS)

0x024D

PPSS7

PPSS6

PPSS5

PPSS4

PPSS3

PPSS2

PPSS1

PPSS0

Reset

Figure 4-30. Port S Polarity Select Register (PPSS)

Read: Anytime.

Write: Anytime.

This register selects whether a pull-down or a pull-up device is connected to the pin.

Table 4-30. PPSS Field Descriptions

Field

Description

7–0

Pull Select Port S

PPSS[7:0] 0 A pull-up device is connected to the associated port S pin, if enabled by the associated bit in register PERS

and if the port is used as input or as wired-OR output.

1 A pull-down device is connected to the associated port S pin, if enabled by the associated bit in register PERS

and if the port is used as input.

4.3.2.29 Port S Wired-OR Mode Register (WOMS)

0x024E

WOMS7

WOMS6

WOMS5

WOMS4

WOMS3

WOMS2

WOMS1

WOMS0

Reset

Figure 4-31. Port S Wired-OR Mode Register (WOMS)

Read: Anytime.

Write: Anytime.

This register configures the output pins as wired-OR. If enabled the output is driven active low only

(open-drain). A logic level of “1” is not driven. It applies also to the SPI and SCI outputs and allows a

multipoint connection of several serial modules. These bits have no influence on pins used as inputs.

Table 4-31. WOMS Field Descriptions

Field

Description

7–0

Wired-OR Mode Port S

WOMS[7:0] 0 Output buffers operate as push-pull outputs.

1 Output buffers operate as open-drain outputs.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.30 Port M Data Register (PTM)

0x0250

PTM7

PTM6

PTM5

PTM4

PTM3

PTM2

PTM1

PTM0

CAN TXCAN3

RXCAN3

RXCAN4

TXCAN2

TXCAN0

RXCAN2

RXCAN0

TXCAN1

TXCAN0

RXCAN1

RXCAN0

TXCAN0

RXCAN0

Routed

CAN0

Routed

CAN4

TXCAN4

RXCAN4

Routed

SPIO

SCK0

MOSI0

SS0

MISO0

Reset

Figure 4-32. Port M Data Register (PTM)

Read: Anytime.

Write: Anytime.

Port M pins 75–0 are associated with the CAN0, CAN1, CAN2, CAN3, SCI3, as well as the routed CAN0,

CAN4, and SPI0 modules. When not used with any of the peripherals, these pins can be used as general

purpose I/O.

If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the

port register, otherwise the buffered pin input state is read.

Table 4-32. PTM Field Descriptions

Field

Description

7–6

PTM[7:6]

The CAN3 function (TXCAN3 and RXCAN3) takes precedence over the CAN4, SCI3 and the general purpose

I/O function if the CAN3 module is enabled. Refer to MSCAN section for details.

The CAN4 function (TXCAN4 and RXCAN4) takes precedence over the SCI3 and the general purpose I/O

function if the CAN4 module is enabled. Refer to MSCAN section for details.

The SCI3 function (TXD3 and RXD3) takes precedence over the general purpose I/O function if the SCI3 module

is enabled. Refer to SCI section for details.

5–4

PTM[5:4]

The CAN2 function (TXCAN2 and RXCAN2) takes precedence over the routed CAN0, routed CAN4, the routed

SPI0 and the general purpose I/O function if the CAN2 module is enabled{pim_9xd_prio.m}.

The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the routed CAN4, the routed SPI0

and the general purpose I/O function if the routed CAN0 module is enabled.

The routed CAN4 function (TXCAN4 and RXCAN4) takes precedence over the routed SPI0 and general purpose

I/O function if the routed CAN4 module is enabled. Refer to MSCAN section for details.

The routed SPI0 function (SCK0 and MOSI0) takes precedence of the general purpose I/O function if the routed

SPI0 is enabled. Refer to SPI section for details.

MC9S12XDP512 Data Sheet, Rev. 2.11

222

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-32. PTM Field Descriptions (continued)

Field

Description

3–2

PTM[3:2]

The CAN1 function (TXCAN1 and RXCAN1) takes precedence over the routed CAN0, the routed SPI0 and the

general purpose I/O function if the CAN1 module is enabled.

The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the routed SPI0 and the general

purpose I/O function if the routed CAN0 module is enabled. Refer to MSCAN section for details.

The routed SPI0 function (SS0 and MISO0) takes precedence of the general purpose I/O function if the routed

SPI0 is enabled and not in bidirectional mode. Refer to SPI section for details.

1–0

The CAN0 function (TXCAN0 and RXCAN0) takes precedence over the general purpose I/O function if the CAN0

PTM[1:0]

module is enabled. Refer to MSCAN section for details.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

223

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.31 Port M Input Register (PTIM)

0x0251

PTIM7

PTIM6

PTIM5

PTIM4

PTIM3

PTIM2

PTIM1

PTIM0

Reset

—

= Unimplemented or Reserved

Figure 4-33. Port M Input Register (PTIM)

These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated

pin values.

Read: Anytime.

Write: Never, writes to this register have no effect.

This register always reads back the buffered state of the associated pins. This can also be used to detect

overload or short circuit conditions on output pins.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.32 Port M Data Direction Register (DDRM)

0x0252

DDRM7

DDRM6

DDRM5

DDRM4

DDRM3

DDRM2

DDRM1

DDRM0

Reset

Figure 4-34. Port M Data Direction Register (DDRM)

Read: Anytime.

Write: Anytime.

This register configures each port M pin as either input or output.

The CAN/SCI3 forces the I/O state to be an output for each port line associated with an enabled output

(TXCAN[3:0], TXD3). TheyAlso forces the I/O state to be an input for each port line associated with an

enabled input (RXCAN[3:0], RXD3). In those cases the data direction bits will not change.

The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is

disabled.

Table 4-33. DDRM Field Descriptions

Field

Description

7–0

Data Direction Port M

DDRM[7:0] 0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PTM or PTIM registers, when changing the DDRM register.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.33 Port M Reduced Drive Register (RDRM)

0x0253

RDRM7

RDRM6

RDRM5

RDRM4

RDRM3

RDRM2

RDRM1

RDRM0

Reset

Figure 4-35. Port M Reduced Drive Register (RDRM)

Read: Anytime.

Write: Anytime.

This register configures the drive strength of each Port M output pin as either full or reduced. If the port

is used as input this bit is ignored.

Table 4-34. RDRM Field Descriptions

Field

Description

7–0

Reduced Drive Port M

RDRM[7:0] 0 Full drive strength at output.

1 Associated pin drives at about 1/6 of the full drive strength.

4.3.2.34 Port M Pull Device Enable Register (PERM)

0x0254

PERM7

PERM6

PERM5

PERM4

PERM3

PERM2

PERM1

PERM0

Reset

Figure 4-36. Port M Pull Device Enable Register (PERM)

Read: Anytime.

Write: Anytime.

This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or

wired-OR output. This bit has no effect if the port is used as push-pull output. Out of reset no pull device

is enabled.

Table 4-35. PERM Field Descriptions

Field

Description

7–0

Pull Device Enable Port M

PERM[7:0] 0 Pull-up or pull-down device is disabled.

1 Either a pull-up or pull-down device is enabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.35 Port M Polarity Select Register (PPSM)

0x0255

PPSM7

PPSM6

PPSM5

PPSM4

PPSM3

PPSM2

PPSM1

PPSM0

Reset

Figure 4-37. Port M Polarity Select Register (PPSM)

Read: Anytime.

Write: Anytime.

This register selects whether a pull-down or a pull-up device is connected to the pin. If CAN is active a

pull-up device can be activated on the RXCAN[3:0] inputs, but not a pull-down.

Table 4-36. PPSM Field Descriptions

Field

Description

7–0

Pull Select Port M

PPSM[7:0] 0 A pull-up device is connected to the associated port M pin, if enabled by the associated bit in register PERM

and if the port is used as general purpose or RXCAN input.

1 A pull-down device is connected to the associated port M pin, if enabled by the associated bit in register PERM

and if the port is used as a general purpose but not as RXCAN.

4.3.2.36 Port M Wired-OR Mode Register (WOMM)

0x0256

WOMM7

WOMM6

WOMM5

WOMM4

WOMM3

WOMM2

WOMM1

WOMM0

Reset

Figure 4-38. Port M Wired-OR Mode Register (WOMM)

Read: Anytime.

Write: Anytime.

This register configures the output pins as wired-OR. If enabled the output is driven active low only

(open-drain). A logic level of “1” is not driven. It applies also to the CAN outputs and allows a multipoint

connection of several serial modules. This bit has no influence on pins used as inputs.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-37. WOMM Field Descriptions

Field

Description

7–0

Wired-OR Mode Port M

WOMM[7:0] 0 Output buffers operate as push-pull outputs.

1 Output buffers operate as open-drain outputs.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.37 Module Routing Register (MODRR)

0x0257

MODRR6

MODRR5

MODRR4

MODRR3

MODRR2

MODRR1

MODRR0

Reset

= Unimplemented or Reserved

Figure 4-39. Module Routing Register (MODRR)

Read: Anytime.

Write: Anytime.

This register configures the re-routing of CAN0, CAN4, SPI0, SPI1, and SPI2 on alternative ports.

Table 4-38. Module Routing Summary

MODRR

Related Pins

Module

CAN0

RXCAN

TXCAN

PM0

PM2

PM4

PJ6

PM1

PM3

PM5

PJ7

PJ6

PJ7

PM4

PM6

PM5

PM7

CAN4

Reserved

MISO

MOSI

SCK

PS4

PM2

PP0

PH0

PP4

PH4

PS5

PM4

PP1

PH1

PP5

PH5

PS6

PM5

PP2

PH2

PP7

PH6

PS7

PM3

PP3

PH3

PP6

PH7

SPI0

SPI1

SPI2

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.38 Port P Data Register (PTP)

0x0258

PTP7

PTP6

PTP5

PTP4

PTP3

PTP2

PTP1

PTP0

PWM

SPI

PWM7

SCK2

PWM6

SS2

PWM5

MOSI2

PWM4

MISO2

PWM3

SS1

PWM2

SCK1

PWM1

MOSI1

PWM0

MISO1

Reset

Figure 4-40. Port P Data Register (PTP)

Read: Anytime.

Write: Anytime.

Port P pins 7, and 5–0 are associated with the PWM as well as the SPI1 and SPI2 modules. These pins can

be used as general purpose I/O when not used with any of the peripherals.

If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the

port register, otherwise the buffered pin input state is read.

The PWM function takes precedence over the general purpose I/O and the SPI2 or SPI1 function if the

associated PWM channel is enabled. While channels 6 and 5-0 are output only if the respective channel is

enabled, channel 7 can be PWM output or input if the shutdown feature is enabled. Refer to PWM section

for details.

The SPI2 function takes precedence over the general purpose I/O function if enabled. Refer to SPI section

for details.

The SPI1 function takes precedence over the general purpose I/O function if enabled. Refer to SPI section

for details.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.39 Port P Input Register (PTIP)

0x0259

PTIP7

PTIP6

PTIP5

PTIP4

PTIP3

PTIP2

PTIP1

PTIP0

Reset

—

= Unimplemented or Reserved

Figure 4-41. Port P Input Register (PTIP)

These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated

pin values.

Read: Anytime.

Write: Never, writes to this register have no effect.

This register always reads back the buffered state of the associated pins. This can also be used to detect

overload or short circuit conditions on output pins.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.40 Port P Data Direction Register (DDRP)

0x025A

DDRP7

DDRP6

DDRP5

DDRP4

DDRP3

DDRP2

DDRP1

DDRP0

Reset

Figure 4-42. Port P Data Direction Register (DDRP)

Read: Anytime.

Write: Anytime.

This register configures each port P pin as either input or output.

If the associated PWM channel or SPI module is enabled this register has no effect on the pins.

The PWM forces the I/O state to be an output for each port line associated with an enabled PWM7–0

channel. Channel 7 can force the pin to input if the shutdown feature is enabled. Refer to PWM section for

details.

If a SPI module is enabled, the SPI determines the pin direction. Refer to SPI section for details.

The DDRP bits revert to controlling the I/O direction of a pin when the associated peripherals are disabled.

Table 4-39. DDRP Field Descriptions

Field

Description

7–0

Data Direction Port P

DDRP[7:0] 0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PTP or PTIP registers, when changing the DDRP register.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.41 Port P Reduced Drive Register (RDRP)

0x025B

RDRP7

RDRP6

RDRP5

RDRP4

RDRP3

RDRP2

RDRP1

RDRP0

Reset

Figure 4-43. Port P Reduced Drive Register (RDRP)

Read: Anytime.

Write: Anytime.

This register configures the drive strength of each port P output pin as either full or reduced. If the port is

used as input this bit is ignored.

Table 4-40. RDRP Field Descriptions

Field

Description

7–0

Reduced Drive Port P

RDRP[7:0] 0 Full drive strength at output.

1 Associated pin drives at about 1/6 of the full drive strength.

4.3.2.42 Port P Pull Device Enable Register (PERP)

0x025C

PERP7

PERP6

PERP5

PERP4

PERP3

PERP2

PERP1

PERP0

Reset

Figure 4-44. Port P Pull Device Enable Register (PERP)

Read: Anytime.

Write: Anytime.

This register configures whether a pull-up or a pull-down device is activated, if the port is used as input.

This bit has no effect if the port is used as output. Out of reset no pull device is enabled.

Table 4-41. PERP Field Descriptions

Field

Description

7–0

Pull Device Enable Port P

PERP[7:0] 0 Pull-up or pull-down device is disabled.

1 Either a pull-up or pull-down device is enabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.43 Port P Polarity Select Register (PPSP)

0x025D

PPSP7

PPSP6

PPSP5

PPSP4

PPSP3

PPSP2

PPSP1

PPSP0

Reset

Figure 4-45. Port P Polarity Select Register (PPSP)

Read: Anytime.

Write: Anytime.

This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting

a pull-up or pull-down device if enabled.

Table 4-42. PPSP Field Descriptions

Field

Description

7–0

Polarity Select Port P

PPSP[7:0] 0 Falling edge on the associated port P pin sets the associated ﬂag bit in the PIFP register.A pull-up device is

connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used

as input.

1 Rising edge on the associated port P pin sets the associated ﬂag bit in the PIFP register.A pull-down device

is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is

used as input.

4.3.2.44 Port P Interrupt Enable Register (PIEP)

0x025E

PIEP7

PIEP6

PIEP5

PIEP4

PIEP3

PIEP2

PIEP1

PIEP0

Reset

Figure 4-46. Port P Interrupt Enable Register (PIEP)

Read: Anytime.

Write: Anytime.

This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with

Port P.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-43. PIEP Field Descriptions

Field

Description

7–0

Interrupt Enable Port P

PIEP[7:0] 0 Interrupt is disabled (interrupt ﬂag masked).

1 Interrupt is enabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.45 Port P Interrupt Flag Register (PIFP)

0x025F

PIFP7

PIFP6

PIFP5

PIFP4

PIFP3

PIFP2

PIFP1

PIFP0

Reset

Figure 4-47. Port P Interrupt Flag Register (PIFP)

Read: Anytime.

Write: Anytime.

Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based

on the state of the PPSP register. To clear this flag, write logic level “1” to the corresponding bit in the

PIFP register. Writing a “0” has no effect.

Table 4-44. PIFP Field Descriptions

Field

Description

7–0

Interrupt Flags Port P

PIFP[7:0] 0 No active edge pending. Writing a “0” has no effect.

1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).

Writing a logic level “1” clears the associated ﬂag.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.46 Port H Data Register (PTH)

0x0260

PTH7

PTH6

PTH5

PTH4

PTH3

PTH2

PTH1

PTH0

Routed

SPI

SS2

SCK2

MOSI2

MISO2

SS1

SCK1

MOSI1

MISO1

Reset

Figure 4-48. Port H Data Register (PTH)

Read: Anytime.

Write: Anytime.

Port H pins 7–0 are associated with the SCI4 and SCI5 as well as the routed SPI1 and SPI2 modules.

These pins can be used as general purpose I/O when not used with any of the peripherals.

If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the

port register, otherwise the buffered pin input state is read.

The routed SPI2 function takes precedence over the SCI4 and SCI5 and the general purpose I/O function

if the routed SPI2 module is enabled. Refer to SPI section for details.

The routed SPI1 function takes precedence over the general purpose I/O function if the routed SPI1 is

enabled. Refer to SPI section for details.

The SCI4 and SCI5 function takes precedence over the general purpose I/O function if the SCI4 or SCI5

is enabled. Refer to SCI section for details.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

237

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.47 Port H Input Register (PTIH)

0x0261

PTIH7

PTIH6

PTIH5

PTIH4

PTIH3

PTIH2

PTIH1

PTIH0

Reset

—

= Unimplemented or Reserved

Figure 4-49. Port H Input Register (PTIH)

These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated

pin values.

Read: Anytime.

Write: Never, writes to this register have no effect.

This register always reads back the buffered state of the associated pins. This can also be used to detect

overload or short circuit conditions on output pins.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.48 Port H Data Direction Register (DDRH)

0x0262

DDRH7

DDRH6

DDRH5

DDRH4

DDRH3

DDRH2

DDRH1

DDRH0

Reset

Figure 4-50. Port H Data Direction Register (DDRH)

Read: Anytime.

Write: Anytime.

This register configures each port H pin as either input or output.

If the associated SCI channel or routed SPI module is enabled this register has no effect on the pins.

The SCI forces the I/O state to be an output for each port line associated with an enabled output (TXD5,

TXD4). It also forces the I/O state to be an input for each port line associated with an enabled input (RXD5,

RXD4). In those cases the data direction bits will not change.

If a SPI module is enabled, the SPI determines the pin direction. Refer to SPI section for details.

The DDRH bits revert to controlling the I/O direction of a pin when the associated peripheral modules are

disabled.

Table 4-45. DDRH Field Descriptions

Field

Description

7–0

Data Direction Port H

DDRH[7:0] 0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PTH or PTIH registers, when changing the DDRH register.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.49 Port H Reduced Drive Register (RDRH)

0x0263

RDRH7

RDRH6

RDRH5

RDRH4

RDRH3

RDRH2

RDRH1

RDRH0

Reset

Figure 4-51. Port H Reduced Drive Register (RDRH)

Read: Anytime.

Write: Anytime.

This register configures the drive strength of each Port H output pin as either full or reduced. If the port is

used as input this bit is ignored.

Table 4-46. RDRH Field Descriptions

Field

Description

7–0

Reduced Drive Port H

RDRH[7:0] 0 Full drive strength at output.

1 Associated pin drives at about 1/6 of the full drive strength.

4.3.2.50 Port H Pull Device Enable Register (PERH)

0x0264

PERH7

PERH6

PERH5

PERH4

PERH3

PERH2

PERH1

PERH0

Reset

Figure 4-52. Port H Pull Device Enable Register (PERH)

Read: Anytime.

Write: Anytime.

This register configures whether a pull-up or a pull-down device is activated, if the port is used as input.

This bit has no effect if the port is used as output. Out of reset no pull device is enabled.

Table 4-47. PERH Field Descriptions

Field

Description

7–0

Pull Device Enable Port H

PERH[7:0] 0 Pull-up or pull-down device is disabled.

1 Either a pull-up or pull-down device is enabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.51 Port H Polarity Select Register (PPSH)

0x0265

PPSH7

PPSH6

PPSH5

PPSH4

PPSH3

PPSH2

PPSH1

PPSH0

Reset

Figure 4-53. Port H Polarity Select Register (PPSH)

Read: Anytime.

Write: Anytime.

This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting

a pull-up or pull-down device if enabled.

Table 4-48. PPSH Field Descriptions

Field

Description

7–0

Polarity Select Port H

PPSH[7:0] 0 Falling edge on the associated port H pin sets the associated ﬂag bit in the PIFH register.

A pull-up device is connected to the associated port H pin, if enabled by the associated bit in register PERH

and if the port is used as input.

1 Rising edge on the associated port H pin sets the associated ﬂag bit in the PIFH register.

A pull-down device is connected to the associated port H pin, if enabled by the associated bit in register PERH

and if the port is used as input.

4.3.2.52 Port H Interrupt Enable Register (PIEH)

0x0266

PIEH7

PIEH6

PIEH5

PIEH4

PIEH3

PIEH2

PIEH1

PIEH0

Reset

Figure 4-54. Port H Interrupt Enable Register (PIEH)

Read: Anytime.

Write: Anytime.

This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with

Port H.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-49. PIEH Field Descriptions

Field

Description

7–0

Interrupt Enable Port H

PIEH[7:0] 0 Interrupt is disabled (interrupt ﬂag masked).

1 Interrupt is enabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.53 Port H Interrupt Flag Register (PIFH)

0x0267

PIFH7

PIFH6

PIFH5

PIFH4

PIFH3

PIFH2

PIFH1

PIFH0

Reset

Figure 4-55. Port H Interrupt Flag Register (PIFH)

Read: Anytime.

Write: Anytime.

Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based

on the state of the PPSH register. To clear this flag, write logic level “1” to the corresponding bit in the

PIFH register. Writing a “0” has no effect.

Table 4-50. PIFH Field Descriptions

Field

Description

7–0

Interrupt Flags Port H

PIFH[7:0] 0 No active edge pending. Writing a “0” has no effect.

1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).

Writing a logic level “1” clears the associated ﬂag.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.54 Port J Data Register (PTJ)

0x0268

PTJ7

PTJ6

PTJ5

PTJ4

PTJ2

PTJ1

PTJ0

CAN4/

SCI2

TXCAN4

SCL0

RXCAN4

SDA0

TXD2

RXD2

IICO

IIC1

SCL1

SDA1

Routed

CAN0

TXCAN0

RXCAN0

Alt.

Function

CS2

CS0

CS1

CS3

Reset

= Unimplemented or Reserved

Figure 4-56. Port J Data Register (PTJ)

Read: Anytime.

Write: Anytime.

Port J pins 7–4 and 2–0 are associated with the CAN4, SCI2, IIC0 and IIC1, the routed CAN0 modules

and chip select signals (CS0, CS1, CS2, CS3). These pins can be used as general purpose I/O when not

used with any of the peripherals.

If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the

port register, otherwise the buffered pin input state is read.

Table 4-51. PTJ Field Descriptions

Field

Description

7–6

PJ[7:0]

The CAN4 function (TXCAN4 and RXCAN4) takes precedence over the IIC0, the routed CAN0 and the general

purpose I/O function if the CAN4 module is enabled.

The IIC0 function (SCL0 and SDA0) takes precedence over the routed CAN0 and the general purpose I/O

function if the IIC0 is enabled. If the IIC0 module takes precedence the SDA0 and SCL0 outputs are conﬁgured

as open drain outputs. Refer to IIC section for details.

The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the general purpose I/O function if

the routed CAN0 module is enabled. Refer to MSCAN section for details.

5-4

PJ[5:4]

The IIC1 function (SCL1 and SDA1) takes precedence over the chip select (CS0, CS2) and general purpose I/O

function if the IIC1 is enabled. The chip selects (CS0, CS2) take precedence over the general purpose I/O. If the

IIC1 module takes precedence the SDA1 and SCL1 outputs are conﬁgured as open drain outputs. Refer to IIC

section for details.

The chip select function (CS1) takes precedence over the general purpose I/O.

PJ2

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-51. PTJ Field Descriptions (continued)

Field

Description

The SCI2 function takes precedence over the general purpose I/O function if the SCI2 module is enabled. Refer

PJ1

to SCI section for details.

PJ0

The SCI2 function takes precedence over the chip select (CS3) and the general purpose I/O function if the SCI2

module is enabled. The chip select (CS3) takes precedence over the general purpose I/O function. Refer to SCI

section for details.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.55 Port J Input Register (PTIJ)

0x0269

PTIJ7

PTIJ6

PTIJ5

PTIJ4

PTIJ2

PTIJ1

PTIJ0

Reset

= Unimplemented or Reserved

Figure 4-57. Port J Input Register (PTIJ)

These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated

pin values.

Read: Anytime.

Write: Never, writes to this register have no effect.

This register always reads back the buffered state of the associated pins. This can be used to detect

overload or short circuit conditions on output pins.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.56 Port J Data Direction Register (DDRJ)

0x026A

DDRJ7

DDRJ6

DDRJ5

DDRJ4

DDRJ2

DDRJ1

DDRJ0

Reset

= Unimplemented or Reserved

Figure 4-58. Port J Data Direction Register (DDRJ)

Read: Anytime.

Write: Anytime.

This register configures each port J pin as either input or output.

The CAN forces the I/O state to be an output on PJ7 (TXCAN4) and an input on pin PJ6 (RXCAN4). The

IIC takes control of the I/O if enabled. In these cases the data direction bits will not change.

The SCI2 forces the I/O state to be an output for each port line associated with an enabled output (TXD2).

It also forces the I/O state to be an input for each port line associated with an enabled input (RXD2). In

these cases the data direction bits will not change.

The DDRJ bits revert to controlling the I/O direction of a pin when the associated peripheral module is

disabled.

Table 4-52. DDRJ Field Descriptions

Field

Description

7–0

Data Direction Port J

DDRJ[7:4] 0 Associated pin is conﬁgured as input.

DDRJ[2:0] 1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PTJ or PTIJ registers, when changing the DDRJ register.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

247

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.57 Port J Reduced Drive Register (RDRJ)

0x026B

RDRJ7

RDRJ6

RDRJ5

RDRJ4

RDRJ2

RDRJ1

RDRJ0

Reset

= Unimplemented or Reserved

Figure 4-59. Port J Reduced Drive Register (RDRJ)

Read: Anytime.

Write: Anytime.

This register configures the drive strength of each port J output pin as either full or reduced. If the port is

used as input this bit is ignored.

Table 4-53. RDRJ Field Descriptions

Field

Description

7–0

Reduced Drive Port J

RDRJ[7:4] 0 Full drive strength at output.

RDRJ[2:0] 1 Associated pin drives at about 1/6 of the full drive strength.

4.3.2.58 Port J Pull Device Enable Register (PERJ)

0x026C

PERJ7

PERJ6

PERJ5

PERJ4

PERJ2

PERJ1

PERJ0

Reset

= Unimplemented or Reserved

Figure 4-60. Port J Pull Device Enable Register (PERJ)

Read: Anytime.

Write: Anytime.

This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or

as wired-OR output. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up

device is enabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-54. PERJ Field Descriptions

Field

Description

7–0

Pull Device Enable Port J

PERJ[7:4] 0 Pull-up or pull-down device is disabled.

PERJ[2:0] 1 Either a pull-up or pull-down device is enabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.59 Port J Polarity Select Register (PPSJ)

0x026D

PPSJ7

PPSJ6

PPSJ5

PPSJ4

PPSJ2

PPSJ1

PPSJ0

Reset

= Unimplemented or Reserved

Figure 4-61. Port J Polarity Select Register (PPSJ)

Read: Anytime.

Write: Anytime.

This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting

a pull-up or pull-down device if enabled.

Table 4-55. PPSJ Field Descriptions

Field

Description

7–0

Polarity Select Port J

PPSJ[7:4]

PPSJ[2:0]

Falling edge on the associated port J pin sets the associated ﬂag bit in the PIFJ register.

A pull-up device is connected to the associated port J pin, if enabled by the associated bit in register PERJ

and if the port is used as general purpose input or as IIC port.

Rising edge on the associated port J pin sets the associated ﬂag bit in the PIFJ register.

A pull-down device is connected to the associated port J pin, if enabled by the associated bit in register PERJ

and if the port is used as input.

4.3.2.60 Port J Interrupt Enable Register (PIEJ)

0x026E

PIEJ7

PIEJ6

PIEJ5

PIEJ4

PIEJ2

PIEJ1

PIEJ0

Reset

= Unimplemented or Reserved

Figure 4-62. Port J Interrupt Enable Register (PIEJ)

This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with

Port J.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-56. PIEJ Field Descriptions

Field

Description

7–0

Interrupt Enable Port J

PIEJ[7:4]

PIEJ[2:0]

0 Interrupt is disabled (interrupt ﬂag masked).

1 Interrupt is enabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.61 Port J Interrupt Flag Register (PIFJ)

0x026F

PIFJ7

PIFJ6

PIFJ5

PIFJ4

PIFJ2

PIFJ1

PIFJ0

Reset

= Unimplemented or Reserved

Figure 4-63. Port J Interrupt Flag Register (PIFJ)

Read: Anytime.

Write: Anytime.

Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based

on the state of the PPSJ register. To clear this flag, write logic level “1” to the corresponding bit in the PIFJ

Table 4-57. PIEJ Field Descriptions

Field

Description

7–0

Interrupt Flags Port J

PIFJ[7:4]

PIFJ[2:0]

0 No active edge pending. Writing a “0” has no effect.

1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).

Writing a logic level “1” clears the associated ﬂag.

4.3.2.62 Port AD0 Data Register 1 (PT1AD0)

0x0271

PT1AD07

PT1AD06

PT1AD05

PT1AD04

PT1AD03

PT1AD02

PT1AD01

PT1AD00

Reset

Figure 4-64. Port AD0 Data Register 1 (PT1AD0)

Read: Anytime.

Write: Anytime.

This register is associated with AD0 pins PAD[23:10]. These pins can also be used as general purpose I/O.

If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,

otherwise the value at the pins is read.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.63 Port AD0 Data Direction Register 1 (DDR1AD0)

0x0273

DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00

Reset

Figure 4-65. Port AD0 Data Direction Register 1 (DDR1AD0)

Read: Anytime.

Write: Anytime.

This register configures pins PAD[07:00] as either input or output.

Table 4-58. DDR1AD0 Field Descriptions

Field

Description

7–0

Data Direction Port AD0 Register 1

DDR1AD0[7:0] 0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is

read on PTAD01 register, when changing the DDR1AD0 register.

Note: To use the digital input function on port AD0 the ATD0 digital input enable register (ATD0DIEN) has to

be set to logic level “1”.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.64 Port AD0 Reduced Drive Register 1 (RDR1AD0)

0x0275

RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00

Reset

Figure 4-66. Port AD0 Reduced Drive Register 1 (RDR1AD0)

Read: Anytime.

Write: Anytime.

This register configures the drive strength of each output pin PAD[07:00] as either full or reduced. If the

port is used as input this bit is ignored.

Table 4-59. RDR1AD0 Field Descriptions

Field

Description

7–0

Reduced Drive Port AD0 Register 1

RDR1AD0[7:0] 0 Full drive strength at output.

1 Associated pin drives at about 1/6 of the full drive strength.

4.3.2.65 Port AD0 Pull Up Enable Register 1 (PER1AD0)

0x0277

PER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00

Reset

Figure 4-67. Port AD0 Pull Up Enable Register 1 (PER1AD0)

Read: Anytime.

Write: Anytime.

This register activates a pull-up device on the respective pin PAD[07:00] if the port is used as input. This

bit has no effect if the port is used as output. Out of reset no pull device is enabled.

Table 4-60. PER1AD0 Field Descriptions

Field

Description

7–0

Pull Device Enable Port AD0 Register 1

PER1AD0[7:0] 0 Pull-up device is disabled.

1 Pull-up device is enabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.66 Port AD1 Data Register 0 (PT0AD1)

0x0278

PT0AD123

PT0AD122

PT0AD121

PT0AD120

PT0AD119

PT0AD118

PT0AD117

PT0AD116

Reset

Figure 4-68. Port AD1 Data Register 0 (PT0AD1)

Read: Anytime.

Write: Anytime.

This register is associated with AD1 pins PAD[23:16]. These pins can also be used as general purpose I/O.

If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,

otherwise the value at the pins is read.

4.3.2.67 Port AD1 Data Register 1 (PT1AD1)

0x0279

PT1AD115

PT1AD114

PT1AD113

PT1AD112

PT1AD111

PT1AD110

PT1AD19

PT1AD18

Reset

Figure 4-69. Port AD1 Data Register 1 (PT1AD1)

Read: Anytime.

Write: Anytime.

This register is associated with AD1 pins PAD[15:08]. These pins can also be used as general purpose I/O.

If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,

otherwise the value at the pins is read.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.68 Port AD1 Data Direction Register 0 (DDR0AD1)

0x027A

DDR0AD123 DDR0AD122 DDR0AD121 DDR0AD120 DDR0AD119 DDR0AD118 DDR0AD117 DDR0AD116

Reset

Figure 4-70. Port AD1 Data Direction Register 0 (DDR0AD1)

Read: Anytime.

Write: Anytime.

This register configures pin PAD[23:16] as either input or output.

Table 4-61. DDR0AD1 Field Descriptions

Field

Description

7–0

Data Direction Port AD1 Register 0

DDR0AD1[23:16] 0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is

read on PTAD10 register, when changing the DDR0AD1 register.

Note: To use the digital input function on Port AD1 the ATD1 digital input enable register (ATD1DIEN0) has

to be set to logic level “1”.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.69 Port AD1 Data Direction Register 1 (DDR1AD1)

0x027B

DDR1AD115 DDR1AD114 DDR1AD113 DDR1AD112 DDR1AD111 DDR1AD110 DDR1AD19 DDR1AD18

Reset

Figure 4-71. Port AD1 Data Direction Register 1 (DDR1AD1)

Read: Anytime.

Write: Anytime.

This register configures pins PAD[15:08] as either input or output.

Table 4-62. DDR1AD1 Field Descriptions

Field

Description

7–0

Data Direction Port AD1 Register 1

DDR1AD1[15:8] 0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is

read on PTAD11 register, when changing the DDR1AD1 register.

Note: To use the digital input function on port AD1 the ATD1 digital input enable register (ATD1DIEN1) has

to be set to logic level “1”.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.70 Port AD1 Reduced Drive Register 0 (RDR0AD1)

0x027C

RDR0AD123 RDR0AD122 RDR0AD121 RDR0AD120 RDR0AD119 RDR0AD118 RDR0AD117 RDR0AD116

Reset

Figure 4-72. Port AD1 Reduced Drive Register 0 (RDR0AD1)

Read: Anytime.

Write: Anytime.

This register configures the drive strength of each PAD[23:16] output pin as either full or reduced. If the

port is used as input this bit is ignored.

Table 4-63. RDR0AD1 Field Descriptions

Field

Description

7–0

Reduced Drive Port AD1 Register 0

RDR0AD1[23:16] 0 Full drive strength at output.

1 Associated pin drives at about 1/6 of the full drive strength.

4.3.2.71 Port AD1 Reduced Drive Register 1 (RDR1AD1)

0x027D

RDR1AD115 RDR1AD114 RDR1AD113 RDR1AD112 RDR1AD111 RDR1AD110 RDR1AD19 RDR1AD18

Reset

Figure 4-73. Port AD1 Reduced Drive Register 1 (RDR1AD1)

Read: Anytime.

Write: Anytime.

This register configures the drive strength of each PAD[15:08] output pin as either full or reduced. If the

port is used as input this bit is ignored.

Table 4-64. RDR1AD1 Field Descriptions

Field

Description

7–0

Reduced Drive Port AD1 Register 1

RDR1AD1[15:8] 0 Full drive strength at output.

1 Associated pin drives at about 1/6 of the full drive strength.

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.3.2.72 Port AD1 Pull Up Enable Register 0 (PER0AD1)

0x027E

PER0AD123 PER0AD122 PER0AD121 PER0AD120 PER0AD119 PER0AD118 PER0AD117 PER0AD116

Reset

Figure 4-74. Port AD1 Pull Up Enable Register 0 (PER0AD1)

Read: Anytime.

Write: Anytime.

This register activates a pull-up device on the respective PAD[23:16] pin if the port is used as input. This

bit has no effect if the port is used as output. Out of reset no pull-up device is enabled.

Table 4-65. PER0AD1 Field Descriptions

Field

Description

7–0

Pull Device Enable Port AD1 Register 0

PER0AD1[23:16] 0 Pull-up device is disabled.

1 Pull-up device is enabled.

4.3.2.73 Port AD1 Pull Up Enable Register 1 (PER1AD1)

0x027F

PER1AD115 PER1AD114 PER1AD113 PER1AD112 PER1AD111 PER1AD110 PER1AD19 PER1AD18

Reset

Figure 4-75. Port AD1 Pull Up Enable Register 1 (PER1AD1)

Read: Anytime.

Write: Anytime.

This register activates a pull-up device on the respective PAD[15:08] pin if the port is used as input. This

bit has no effect if the port is used as output. Out of reset no pull-up device is enabled.

Table 4-66. PER1AD1 Field Descriptions

Field

Description

7–0

Pull Device Enable Port AD1 Register 1

PER1AD1[15:8] 0 Pull-up device is disabled.

1 Pull-up device is enabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.4

Functional Description

Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an

output from the external bus interface module or a peripheral module or an input to the external bus

interface module or a peripheral module.

A set of configuration registers is common to all ports with exceptions in the expanded bus interface and

ATD ports (Table 4-67). All registers can be written at any time; however a specific configuration might

not become active.

Example: Selecting a pull-up device

This device does not become active while the port is used as a push-pull output.

Table 4-67. Register Availability per Port

Data

Direction

Reduced

Drive

Pull

Enable

Polarity

Select

Wired-OR Interrupt

Interrupt

Flag

Port

Data

Input

Mode

Enable

yes

—

yes

—

yes

—

yes

—

yes

—

yes

—

yes

—

yes

—

AD0

AD1

—

Each cell represents one register with individual conﬁguration bits

4.4.1

Registers

4.4.1.1

Data Register

This register holds the value driven out to the pin if the pin is used as a general purpose I/O.

Writing to this register has only an effect on the pin if the pin is used as general purpose output. When

reading this address, the buffered state of the pin is returned if the associated data direction register bit is

set to “0”.

If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This

is independent of any other configuration (Figure 4-76).

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.4.1.2

Input Register

This is a read-only register and always returns the buffered state of the pin (Figure 4-76).

4.4.1.3

Data Direction Register

This register defines whether the pin is used as an input or an output.

If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 4-76).

PTI

DDR

data out

Module

output enable

module enable

Figure 4-76. Illustration of I/O Pin Functionality

4.4.1.4

Reduced Drive Register

If the pin is used as an output this register allows the configuration of the drive strength.

4.4.1.5

Pull Device Enable Register

This register turns on a pull-up or pull-down device. It becomes active only if the pin is used as an input

or as a wired-OR output.

4.4.1.6

Polarity Select Register

This register selects either a pull-up or pull-down device if enabled. It becomes active only if the pin is

used as an input. A pull-up device can be activated if the pin is used as a wired-OR output. If the pin is

used as an interrupt input this register selects the active interrupt edge.

4.4.1.7

Wired-OR Mode Register

If the pin is used as an output this register turns off the active high drive. This allows wired-OR type

connections of outputs.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.4.1.8

Interrupt Enable Register

If the pin is used as an interrupt input this register serves as a mask to the interrupt flag to enable/disable

the interrupt.

4.4.1.9

Interrupt Flag Register

If the pin is used as an interrupt input this register holds the interrupt flag after a valid pin event.

4.4.1.10 Module Routing Register

This register supports the re-routing of the CAN0, CAN4, SPI0, SPI1, and SPI2 pins to alternative ports.

This allows a software re-configuration of the pinouts of the different package options with respect to

above peripherals.

NOTE

The purpose of the module routing register is to provide maximum

ﬂexibility for derivatives with a lower number of MSCAN and SPI modules.

Table 4-68. Module Implementations on Derivatives

MSCAN Modules

SPI Modules

SPI1

Number

of Modules

CAN0

CAN1

CAN2

CAN3

CAN4

SPI0

SPI2

yes

—

yes

—

yes

—

yes

—

yes

—

yes

—

4.4.2

Ports

4.4.2.1

BKGD Pin

The BKGD pin is associated with the S12X_BDM and S12X_EBI modules. During reset, the BKGD pin

is used as MODC input.

4.4.2.2

Port A and B

Port A pins PA[7:0] and Port B pins PB[7:0] can be used for either general-purpose I/O, or, in 144-pin

packages, also with the external bus interface. In this case port A and port B are associated with the

external address bus outputs ADDR15–ADDR8 and ADDR7–ADDR0, respectively. PB0 is the ADDR0

or UDS output.

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.4.2.3

Port C and D

Port C pins PC[7:0] and port D pins PD[7:0] can be used for either general-purpose I/O, or, in 144-pin

packages, also with the external bus interface. In this case port C and port D are associated with the

external data bus inputs/outputs DATA15–DATA8 and DATA7–DATA0, respectively.

These pins are configured for reduced input threshold in certain operating modes (refer to S12X_EBI

section).

NOTE

Port C and D are neither available in 112-pin nor in 80-pin packages.

4.4.2.4

Port E

Port E is associated with the external bus control outputs R/W, LSTRB, LDS and RE, the free-running

clock outputs ECLK and ECLK2X, as well as with the TAGHI, TAGLO, MODA and MODB and

interrupt inputs IRQ and XIRQ.

Port E pins PE[7:2] can be used for either general-purpose I/O or with the alternative functions.

Port E pin PE[7] an be used for either general-purpose I/O or as the free-running clock ECLKX2 output

running at the core clock rate. The clock output is always enabled in emulation modes.

Port E pin PE[4] an be used for either general-purpose I/O or as the free-running clock ECLK output

running at the bus clock rate or at the programmed divided clock rate. The clock output is always enabled

in emulation modes.

Port E pin PE[1] can be used for either general-purpose input or as the level- or falling edge-sensitive IRQ

interrupt input. IRQ will be enabled by setting the IRQEN configuration bit (Section 4.3.2.14, “IRQ

Control Register (IRQCR)”) and clearing the I-bit in the CPU’s condition code register. It is inhibited at

reset so this pin is initially configured as a simple input with a pull-up.

Port E pin PE[0] can be used for either general-purpose input or as the level-sensitive XIRQ interrupt

input. XIRQ can be enabled by clearing the X-bit in the CPU’s condition code register. It is inhibited at

reset so this pin is initially configured as a high-impedance input with a pull-up.

Port E pins PE[5] and PE[6] are configured for reduced input threshold in certain modes (refer to

S12X_EBI section).

4.4.2.5

Port K

Port K pins PK[7:0] can be used for either general-purpose I/O, or, in 144-pin packages, also with the

external bus interface. In this case port K pins PK[6:0] are associated with the external address bus outputs

ADDR22–ADDR16 and PK7 is associated to the EWAIT input.

Port K pin PE[7] is configured for reduced input threshold in certain modes (refer to S12X_EBI section).

NOTE

Port K is not available in 80-pin packages. PK[6] is not available in 112-pin

packages.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.4.2.6

Port T

This port is associated with the ECT module. Port T pins PT[7:0] can be used for either general-purpose

I/O, or with the channels of the enhanced capture timer.

4.4.2.7

Port S

This port is associated with SCI0, SCI1 and SPI0. Port S pins PS[7:0] can be used either for general-

purpose I/O, or with the SCI and SPI subsystems.

The SPI0 pins can be re-routed. Refer to Section 4.3.2.37, “Module Routing Register (MODRR)”.

NOTE

PS[7:4] are not available in 80-pin packages.

4.4.2.8

Port M

This port is associated with the SCI3, CAN4–0 and SPI0. Port M pins PM[7:0] can be used for either

general purpose I/O, or with the CAN, SCI and SPI subsystems.

The CAN0, CAN4 and SPI0 pins can be re-routed. Refer to Section 4.3.2.37, “Module Routing Register

(MODRR)”.

NOTE

PM[7:6] are not available in 80-pin packages.

4.4.2.9

Port P

This port is associated with the PWM, SPI1 and SPI2. Port P pins PP[7:0] can be used for either general

purpose I/O, or with the PWM and SPI subsystems.

The pins are shared between the PWM channels and the SPI1 and SPI2 modules. If the PWM is enabled

the pins become PWM output channels with the exception of pin 7 which can be PWM input or output. If

SPI1 or SPI2 are enabled and PWM is disabled, the respective pin configuration is determined by status

bits in the SPI modules.

The SPI1 and SPI2 pins can be re-routed. Refer to Section 4.3.2.37, “Module Routing Register

(MODRR)”.

Port P offers 8 I/O pins with edge triggered interrupt capability in wired-OR fashion (Section 4.4.3, “Pin

Interrupts”).

NOTE

PP[6] is not available in 80-pin packages.

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.4.2.10 Port H

This port is associated with the SPI1, SPI2, SCI4, and SCI5. Port H pins PH[7:0] can be used for either

general purpose I/O, or with the SPI and SCI subsystems. Port H pins can be used with the routed SPI1

and SPI2 modules. Refer to Section 4.3.2.37, “Module Routing Register (MODRR)”.

Port H offers 8 I/O pins with edge triggered interrupt capability (Section 4.4.3, “Pin Interrupts”).

NOTE

Port H is not available in 80-pin packages.

4.4.2.11 Port J

This port is associated with the chip selects CS0, CS1, CS2 and CS3 as well as with CAN4, CAN0, IIC1,

IIC0, and SCI2. Port J pins PJ[7:4] and PJ[2:0] can be used for either general purpose I/O, or with the

CAN, IIC, or SCI subsystems. If IIC takes precedence the associated pins become IIC open-drain output

pins. The CAN4 pins can be re-routed. Refer to Section 4.3.2.37, “Module Routing Register (MODRR)”.

Port J pins can be used with the routed CAN0 modules. Refer to Section 4.3.2.37, “Module Routing

Port J offers 7 I/O pins with edge triggered interrupt capability (Section 4.4.3, “Pin Interrupts”).

NOTE

PJ[5,4,2] are not available in 112-pin packages. PJ[5,4,2,1,0] are not

available in 80-pin packages.

4.4.2.12 Port AD0

This port is associated with the ATD0. Port AD0 pins PAD07–PAD00 can be used for either general

purpose I/O, or with the ATD0 subsystem.

4.4.2.13 Port AD1

This port is associated with the ATD1. Port AD1 pins PAD23–PAD08 can be used for either general

purpose I/O, or with the ATD1 subsystem.

NOTE

PAD[23:16] are not available in 112-pin packages. PAD[23:08] are not

available in 80-pin packages.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

4.4.3

Pin Interrupts

Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or

falling edges can be individually configured on per-pin basis. All bits/pins in a port share the same

interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.

An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt

enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or

WAIT mode.

A digital filter on each pin prevents pulses (Figure 4-78) shorter than a specified time from generating an

interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 4-77 and

Table 4-69).

Glitch, ﬁltered out, no interrupt ﬂag set

Valid pulse, interrupt ﬂag set

uncertain

pign

pval

Figure 4-77. Interrupt Glitch Filter on Port P, H, and J (PPS = 0)

Table 4-69. Pulse Detection Criteria

Mode

Pulse

STOP

≤ 3

Unit

STOP

Ignored

Uncertain

Valid

Bus clocks

≤ t

pulse

pign

3 < t

< 4

< t

pval

pulse

pign

pulse

≥ 4

≥ t

pulse

pval

These values include the spread of the oscillator frequency over temperature,

voltage and process.

pulse

Figure 4-78. Pulse Illustration

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by

4 consecutive samples of an active level directly or indirectly.

The filters are continuously clocked by the bus clock in run and wait mode. In stop mode, the clock is

generated by an RC-oscillator in the port integration module. To maximize current saving the RC

oscillator runs only if the following condition is true on any pin individually:

Sample count <= 4 and interrupt enabled (PIE = 1) and interrupt flag not set (PIF = 0).

4.4.4

Expanded Bus Pin Functions

All peripheral ports T, S, M, P, H, J, AD0, and AD1 start up as general purpose inputs after reset.

Depending on the external mode pin condition, the external bus interface related ports A, B, C, D, E, and

K start up as general purpose inputs on reset or are configured for their alternate functions.

Table 4-70 lists the pin functions in relationship with the different operating modes. If two entries per pin

are displayed, a ‘mux’ indicates time-multiplexing between the two functions and an ‘or’ means that a

configuration bit exists which can be altered after reset to select the respective function (displayed in

italics). Refer to S12X_EBI section for details.

Table 4-70. Expanded Bus Pin Functions versus Operating Modes

Single-Chip Modes

Expanded Modes

Normal

Single-Chip

Special

Single-Chip

Normal

Expanded

Emulation

Single-Chip

Emulation

Expanded

Special

Test

PK7

GPIO

EWAIT

GPIO

EWAIT

GPIO

PK[6:4]

PK[3:0]

PA[7:0]

PB[7:1]

PB0

GPIO

ADDR[22:20]

mux

ACC[2:0]

ADDR[22:20]

mux

ACC[2:0]

ADDR[22:20]

ADDR[19:16]

ADDR[15:8]

ADDR[7:1]

ADDR0

GPIO

ADDR[19:16]

mux

IQSTAT[3:0]

ADDR[19:16]

mux

IQSTAT[3:0]

GPIO

ADDR[15:8]

mux

IVD[15:8]

ADDR[15:8]

mux

IVD[15:8]

GPIO

ADDR[7:1]

mux

IVD[7:1]

ADDR[7:1]

mux

IVD[7:1]

GPIO

UDS

GPIO

ADDR0

mux

IVD0

ADDR0

mux

IVD0

PC[7:0]

DATA[15:8]

GPIO

PD[7:0]

PE7

DATA[7:0]

ECLKX2

DATA[7:0]

ECLKX2

DATA[7:0]

GPIO

ECLKX2

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

Table 4-70. Expanded Bus Pin Functions versus Operating Modes (continued)

Single-Chip Modes

Expanded Modes

Normal

Single-Chip

Special

Single-Chip

Normal

Expanded

Emulation

Single-Chip

Emulation

Expanded

Special

Test

PE6

PE5

PE4

GPIO

TAGHI

TAGLO

ECLK

TAGHI

TAGLO

ECLK

GPIO

ECLK

GPIO

PE3

GPIO

LDS

GPIO

LSTRB

R/W

LSTRB

PE2

PJ5

GPIO

R/W

GPIO

CS2

PJ4

PJ2

PJ0

GPIO

CS0

(1)

GPIO

CS1

GPIO

CS1

GPIO

CS1

GPIO

CS3

Depending on ROMON bit. Refer to Device Guide, S12X_EBI section and S12X_MMC section for details.

4.4.5

Low-Power Options

Run Mode

4.4.5.1

No low-power options exist for this module in run mode.

4.4.5.2

Wait Mode

No low-power options exist for this module in wait mode.

4.4.5.3

Stop Mode

All clocks are stopped. There are asynchronous paths to generate interrupts from stop on port P, H, and J.

4.5

Initialization and Application Information

•

It is not recommended to write PORTx and DDRx in a word access. When changing the register

pins from inputs to outputs, the data may have extra transitions during the write access. Initialize

the port data register before enabling the outputs.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

•

Power consumption will increase the more the voltages on general purpose input pins deviate from

the supply voltages towards mid-range because the digital input buffers operate in the linear region.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 4 Port Integration Module (S12XDP512PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.11

270

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Chapter 5

Clocks and Reset Generator (S12CRGV6)

5.1

Introduction

This speciﬁcation describes the function of the clocks and reset generator (MC9S12XDP512).

5.1.1

Features

The main features of this block are:

•

Phase locked loop (PLL) frequency multiplier

— Reference divider

— Automatic bandwidth control mode for low-jitter operation

— Automatic frequency lock detector

— Interrupt request on entry or exit from locked condition

— Self clock mode in absence of reference clock

System clock generator

— Clock quality check

— User selectable fast wake-up from Stop in self-clock mode for power saving and immediate

program execution

— Clock switch for either oscillator or PLL based system clocks

Computer operating properly (COP) watchdog timer with time-out clear window

System reset generation from the following possible sources:

— Power on reset

•

— Low voltage reset

— Illegal address reset

— COP reset

— Loss of clock reset

— External pin reset

•

Real-time interrupt (RTI)

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.1.2

Modes of Operation

This subsection lists and brieﬂy describes all operating modes supported by the CRG.

•

Run mode

All functional parts of the CRG are running during normal run mode. If RTI or COP functionality

is required, the individual bits of the associated rate select registers (COPCTL, RTICTL) have to

be set to a nonzero value.

•

Wait mode

In this mode, the PLL can be disabled automatically depending on the PLLSEL bit in the CLKSEL

Stop mode

Depending on the setting of the PSTP bit, stop mode can be differentiated between full stop mode

(PSTP = 0) and pseudo stop mode (PSTP = 1).

— Full stop mode

The oscillator is disabled and thus all system and core clocks are stopped. The COP and the

RTI remain frozen.

— Pseudo stop mode

The oscillator continues to run and most of the system and core clocks are stopped. If the

respective enable bits are set, the COP and RTI will continue to run, or else they remain frozen.

•

Self clock mode

Self clock mode will be entered if the clock monitor enable bit (CME) and the self clock mode

enable bit (SCME) are both asserted and the clock monitor in the oscillator block detects a loss of

clock. As soon as self clock mode is entered, the MC9S12XDP512 starts to perform a clock quality

check. Self clock mode remains active until the clock quality check indicates that the required

quality of the incoming clock signal is met (frequency and amplitude). Self clock mode should be

used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock

is causing severe system conditions.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.1.3

Block Diagram

Figure 5-1 shows a block diagram of the MC9S12XDP512.

Illegal Address Reset

S12X_MMC

Power on Reset

Voltage

Regulator

Low Voltage Reset

CRG

CM fail

RESET

Reset

Generator

System Reset

Clock

Monitor

XCLKS

Clock Quality

Checker

OSCCLK

Oscillator

EXTAL

XTAL

Bus Clock

Core Clock

COP

RTI

Oscillator Clock

Registers

XFC

PLLCLK

Real Time Interrupt

PLL Lock Interrupt

DDPLL

Clock and Reset

Control

PLL

SSPLL

Self Clock Mode

Interrupt

Figure 5-1. CRG Block Diagram

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.2

External Signal Description

This section lists and describes the signals that connect off chip.

5.2.1

and V

— Operating and Ground Voltage Pins

SSPLL

DDPLL

These pins provide operating voltage (V

) and ground (V

) for the PLL circuitry. This allows

DDPLL

SSPLL

the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required, V

DDPLL

and V

must be connected to properly.

SSPLL

5.2.2

XFC — External Loop Filter Pin

A passive external loop ﬁlter must be placed on the XFC pin. The ﬁlter is a second-order, low-pass ﬁlter

that eliminates the VCO input ripple. The value of the external ﬁlter network and the reference frequency

determines the speed of the corrections and the stability of the PLL. Refer to the device speciﬁcation for

calculation of PLL Loop Filter (XFC) components. If PLL usage is not required, the XFC pin must be tied

to V

DDPLL

MCU

XFC

Figure 5-2. PLL Loop Filter Connections

5.2.3

RESET — Reset Pin

RESET is an active low bidirectional reset pin. As an input. it initializes the MCU asynchronously to a

known start-up state. As an open-drain output, it indicates that a system reset (internal to the MCU) has

been triggered.

5.3

Memory Map and Register Deﬁnition

This section provides a detailed description of all registers accessible in the MC9S12XDP512.

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.3.1

Module Memory Map

Table 5-1 gives an overview on all MC9S12XDP512 registers.

Table 5-1. MC9S12XDP512 Memory Map

Address

Offset

Use

Access

0x_00

0x_01

0x_02

0x_03

0x_04

0x_05

0x_06

0x_07

0x_08

0x_09

0x_0A

0x_0B

CRG Synthesizer Register (SYNR)

R/W

CRG Reference Divider Register (REFDV)

CRG Test Flags Register (CTFLG)

CRG Flags Register (CRGFLG)

CRG Interrupt Enable Register (CRGINT)

CRG Clock Select Register (CLKSEL)

CRG PLL Control Register (PLLCTL)

CRG RTI Control Register (RTICTL)

CRG COP Control Register (COPCTL)

CRG Force and Bypass Test Register (FORBYP)

CRG Test Control Register (CTCTL)

CRG COP Arm/Timer Reset (ARMCOP)

CTFLG is intended for factory test purposes only.

FORBYP is intended for factory test purposes only.

CTCTL is intended for factory test purposes only.

NOTE

is deﬁned at the MCU level and the Address Offset is deﬁned at the module

level.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.3.2

This section describes in address order all the MC9S12XDP512 registers and their individual bits.

Name

Bit 7

Bit 0

0x_00

SYNR

SYN5

SYN4

SYN3

SYN2

SYN1

SYN0

0x_01

REFDV

REFDV5

REFDV4

REFDV3

REFDV2

REFDV1

REFDV0

0x_02

CTFLG

0x_03

CRGFLG

LOCK

TRACK

SCM

RTIF

RTIE

PORF

ILAF

LVRF

LOCKIF

SCMIF

SCMIE

RTIWAI

PCE

0x_04

CRGINT

LOCKIE

0x_05

CLKSEL

PLLSEL

CME

PSTP

PLLON

RTR6

PLLWAI

COPWAI

SCME

RTR0

0x_06

PLLCTL

AUTO

RTR5

ACQ

FSTWKP

PRE

0x_07

RTICTL

RTDEC

RTR4

RTR3

RTR2

RTR1

0x_08

COPCTL

WCOP

RSBCK

CR2

CR1

CR0

WRTMASK

0x_09

FORBYP

0x_0A

CTCTL

0x_0B

ARMCOP

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

= Unimplemented or Reserved

Figure 5-3. S12CRGV6 Register Summary

MC9S12XDP512 Data Sheet, Rev. 2.11

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Freescale Semiconductor

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.3.2.1

CRG Synthesizer Register (SYNR)

The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop

divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency

by 2 x (SYNR + 1). PLLCLK will not be below the minimum VCO frequency (f

SCM

(SYNR + 1)

PLLCLK = 2xOSCCLKx-----------------------------------

(REFDV + 1)

NOTE

If PLL is selected (PLLSEL=1), Bus Clock = PLLCLK / 2

Bus Clock must not exceed the maximum operating system frequency.

Module Base +0x_00

SYN5

SYN4

SYN3

SYN2

SYN1

SYN0

Reset

= Unimplemented or Reserved

Figure 5-4. CRG Synthesizer Register (SYNR)

Read: Anytime

Write: Anytime except if PLLSEL = 1

NOTE

Write to this register initializes the lock detector bit and the track detector

bit.

5.3.2.2

CRG Reference Divider Register (REFDV)

The REFDV register provides a ﬁner granularity for the PLL multiplier steps. The count in the reference

divider divides OSCCLK frequency by REFDV + 1.

Module Base +0x_01

REFDV5

REFDV4

REFDV3

REFDV2

REFDV1

REFDV0

Reset

= Unimplemented or Reserved

Figure 5-5. CRG Reference Divider Register (REFDV)

Read: Anytime

Write: Anytime except when PLLSEL = 1

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

NOTE

Write to this register initializes the lock detector bit and the track detector

bit.

5.3.2.3

Reserved Register (CTFLG)

This register is reserved for factory testing of the MC9S12XDP512 module and is not available in normal

modes.

Module Base +0x_02

Reset

= Unimplemented or Reserved

Figure 5-6. Reserved Register (CTFLG)

Read: Always reads 0x_00 in normal modes

Write: Unimplemented in normal modes

NOTE

Writing to this register when in special mode can alter the MC9S12XDP512

fucntionality.

5.3.2.4

CRG Flags Register (CRGFLG)

This register provides CRG status bits and ﬂags.

Module Base +0x_03

LOCK

TRACK

SCM

RTIF

PORF

LVRF

LOCKIF

SCMIF

Reset

1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset.

2. LVRF is set to 1 when a low-voltage reset occurs. Unaffected by system reset.

= Unimplemented or Reserved

Figure 5-7. CRG Flags Register (CRGFLG)

Read: Anytime

Write: Refer to each bit for individual write conditions

MC9S12XDP512 Data Sheet, Rev. 2.11

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Freescale Semiconductor

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

Table 5-2. CRGFLG Field Descriptions

Field

Description

RTIF

Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This ﬂag can only be cleared by writing

a 1. Writing a 0 has no effect. If enabled (RTIE = 1), RTIF causes an interrupt request.

0 RTI time-out has not yet occurred.

1 RTI time-out has occurred.

Power on Reset Flag — PORF is set to 1 when a power on reset occurs. This ﬂag can only be cleared by writing

a 1. Writing a 0 has no effect.

PORF

0 Power on reset has not occurred.

1 Power on reset has occurred.

Low Voltage Reset Flag — If low voltage reset feature is not available (see device speciﬁcation) LVRF always

reads 0. LVRF is set to 1 when a low voltage reset occurs. This ﬂag can only be cleared by writing a 1. Writing

a 0 has no effect.

LVRF

0 Low voltage reset has not occurred.

1 Low voltage reset has occurred.

PLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This ﬂag can only be cleared

by writing a 1. Writing a 0 has no effect.If enabled (LOCKIE = 1), LOCKIF causes an interrupt request.

0 No change in LOCK bit.

LOCKIF

1 LOCK bit has changed.

Lock Status Bit — LOCK reﬂects the current state of PLL lock condition. This bit is cleared in self clock mode.

Writes have no effect.

LOCK

0 PLL VCO is not within the desired tolerance of the target frequency.

1 PLL VCO is within the desired tolerance of the target frequency.

Track Status Bit — TRACK reﬂects the current state of PLL track condition. This bit is cleared in self clock

TRACK

mode. Writes have no effect.

0 Acquisition mode status.

1Tracking mode status.

Self Clock Mode Interrupt Flag — SCMIF is set to 1 when SCM status bit changes. This ﬂag can only be

cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE = 1), SCMIF causes an interrupt request.

0 No change in SCM bit.

SCMIF

1 SCM bit has changed.

SCM

Self Clock Mode Status Bit — SCM reﬂects the current clocking mode. Writes have no effect.

0 MCU is operating normally with OSCCLK available.

1 MCU is operating in self clock mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK

running at its minimum frequency f

SCM

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.3.2.5

CRG Interrupt Enable Register (CRGINT)

This register enables CRG interrupt requests.

Module Base +0x_04

RTIE

ILAF

LOCKIE

SCMIE

Reset

1. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low

voltage reset.

= Unimplemented or Reserved

Figure 5-8. CRG Interrupt Enable Register (CRGINT)

Read: Anytime

Write: Anytime

Table 5-3. CRGINT Field Descriptions

Description

Field

Real Time Interrupt Enable Bit

0 Interrupt requests from RTI are disabled.

RTIE

1 Interrupt will be requested whenever RTIF is set.

ILAF

Illegal Address Reset Flag — ILAF is set to 1 when an illegal address reset occurs. Refer to S12XMMC Block

Guide for details. This ﬂag can only be cleared by writing a 1. Writing a 0 has no effect.

0 Illegal address reset has not occurred.

1 Illegal address reset has occurred.

Lock Interrupt Enable Bit

LOCKIE

0 LOCK interrupt requests are disabled.

1 Interrupt will be requested whenever LOCKIF is set.

Self ClockMmode Interrupt Enable Bit

0 SCM interrupt requests are disabled.

SCMIE

1 Interrupt will be requested whenever SCMIF is set.

MC9S12XDP512 Data Sheet, Rev. 2.11

280

Freescale Semiconductor

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.3.2.6

CRG Clock Select Register (CLKSEL)

This register controls CRG clock selection. Refer to Figure 5-17 for more details on the effect of each bit.

Module Base +0x_05

PLLSEL

PSTP

PLLWAI

RTIWAI

COPWAI

Reset

= Unimplemented or Reserved

Figure 5-9. CRG Clock Select Register (CLKSEL)

Read: Anytime

Write: Refer to each bit for individual write conditions

Table 5-4. CLKSEL Field Descriptions

Field

Description

PLL Select Bit — Write anytime. Writing a1 when LOCK = 0 and AUTO = 1, or TRACK = 0 and AUTO = 0 has

no effect This prevents the selection of an unstable PLLCLK as SYSCLK. PLLSEL bit is cleared when the MCU

enters self clock mode, Stop mode or wait mode with PLLWAI bit set.

PLLSEL

0 System clocks are derived from OSCCLK (Bus Clock = OSCCLK / 2).

1 System clocks are derived from PLLCLK (Bus Clock = PLLCLK / 2).

Pseudo Stop Bit

PSTP

Write: Anytime

This bit controls the functionality of the oscillator during stop mode.

0 Oscillator is disabled in stop mode.

1 Oscillator continues to run in stop mode (pseudo stop).

Note: Pseudo stop mode allows for faster STOP recovery and reduces the mechanical stress and aging of the

resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption.

PLL Stops in Wait Mode Bit

PLLWAI

Write: Anytime

If PLLWAI is set, the MC9S12XDP512 will clear the PLLSEL bit before entering wait mode. The PLLON bit

remains set during wait mode, but the PLL is powered down. Upon exiting wait mode, the PLLSEL bit has to be

set manually if PLL clock is required.

While the PLLWAI bit is set, the AUTO bit is set to 1 in order to allow the PLL to automatically lock on the selected

target frequency after exiting wait mode.

0 PLL keeps running in wait mode.

1 PLL stops in wait mode.

RTI Stops in Wait Mode Bit

RTIWAI

Write: Anytime

0 RTI keeps running in wait mode.

1 RTI stops and initializes the RTI dividers whenever the part goes into wait mode.

COP Stops in Wait Mode Bit

COPWAI

Normal modes: Write once

Special modes: Write anytime

0 COP keeps running in wait mode.

1 COP stops and initializes the COP counter whenever the part goes into wait mode.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

281

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.3.2.7

CRG PLL Control Register (PLLCTL)

This register controls the PLL functionality.

Module Base +0x_06

CME

PLLON

AUTO

ACQ

FSTWKP

PRE

PCE

SCME

Reset

Figure 5-10. CRG PLL Control Register (PLLCTL)

Read: Anytime

Write: Refer to each bit for individual write conditions

Table 5-5. PLLCTL Field Descriptions

Field

Description

Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1.

CME

0 Clock monitor is disabled.

1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or self clock

mode.

Note: Operating with CME = 0 will not detect any loss of clock. In case of poor clock quality, this could cause

unpredictable operation of the MCU!

Note: In stop mode (PSTP = 0) the clock monitor is disabled independently of the CME bit setting and any loss

of external clock will not be detected. Also after wake-up from stop mode (PSTP = 0) with fast wake-up

enabled (FSTWKP = 1) the clock monitor is disabled independently of the CME bit setting and any loss

of external clock will not be detected.

Phase Lock Loop On Bit — PLLON turns on the PLL circuitry. In self clock mode, the PLL is turned on, but the

PLLON bit reads the last latched value. Write anytime except when PLLSEL = 1.

0 PLL is turned off.

PLLON

1 PLL is turned on. If AUTO bit is set, the PLL will lock automatically.

Automatic Bandwidth Control Bit — AUTO selects either the high bandwidth (acquisition) mode or the low

bandwidth (tracking) mode depending on how close to the desired frequency the VCO is running. Write anytime

except when PLLWAI = 1, because PLLWAI sets the AUTO bit to 1.

AUTO

0 Automatic mode control is disabled and the PLL is under software control, using ACQ bit.

1 Automatic mode control is enabled and ACQ bit has no effect.

Acquisition Bit

ACQ

Write anytime. If AUTO=1 this bit has no effect.

0 Low bandwidth ﬁlter is selected.

1 High bandwidth ﬁlter is selected.

Fast Wake-up from Full Stop Bit — FSTWKP enables fast wake-up from full stop mode. Write anytime. If

self-clock mode is disabled (SCME = 0) this bit has no effect.

FSTWKP

0 Fast wake-up from full stop mode is disabled.

1 Fast wake-up from full stop mode is enabled.

When waking up from full stop mode the system will immediately resume operation in self-clock mode (see

Section 5.4.1.4, “Clock Quality Checker”). The SCMIF ﬂag will not be set. The system will remain in self-clock

mode with oscillator and clock monitor disabled until FSTWKP bit is cleared. The clearing of FSTWKP will

start the oscillator, the clock monitor and the clock quality check. If the clock quality check is successful, the

CRG will switch all system clocks to OSCCLK. The SCMIF ﬂag will be set. See application examples in

Figure 5-23 and Figure 5-24.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

Table 5-5. PLLCTL Field Descriptions (continued)

Field

Description

PRE

RTI Enable during Pseudo Stop Bit — PRE enables the RTI during pseudo stop mode. Write anytime.

0 RTI stops running during pseudo stop mode.

1 RTI continues running during pseudo stop mode.

Note: If the PRE bit is cleared the RTI dividers will go static while pseudo stop mode is active. The RTI dividers

will not initialize like in wait mode with RTIWAI bit set.

PCE

COP Enable during Pseudo Stop Bit — PCE enables the COP during pseudo stop mode. Write anytime.

0 COP stops running during pseudo stop mode

1 COP continues running during pseudo stop mode

Note: If the PCE bit is cleared, the COP dividers will go static while pseudo stop mode is active. The COP

dividers will not initialize like in wait mode with COPWAI bit set.

Self Clock Mode Enable Bit

SCME

Normal modes: Write once

Special modes: Write anytime

SCME can not be cleared while operating in self clock mode (SCM = 1).

0 Detection of crystal clock failure causes clock monitor reset (see Section 5.5.2, “Clock Monitor Reset”).

1 Detection of crystal clock failure forces the MCU in self clock mode (see Section 5.4.2.2, “Self Clock Mode”).

5.3.2.8

CRG RTI Control Register (RTICTL)

This register selects the timeout period for the real time interrupt.

Module Base +0x_07

RTDEC

RTR6

RTR5

RTR4

RTR3

RTR2

RTR1

RTR0

Reset

Figure 5-11. CRG RTI Control Register (RTICTL)

Read: Anytime

Write: Anytime

NOTE

A write to this register initializes the RTI counter.

Table 5-6. RTICTL Field Descriptions

Description

Field

Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.

0 Binary based divider value. See Table 5-7

RTDEC

1 Decimal based divider value. See Table 5-8

6–4

Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See Table 5-7

RTR[6:4]

and Table 5-8.

3–0

RTR[3:0]

Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to

provide additional granularity.Table 5-7 and Table 5-8 show all possible divide values selectable by the RTICTL

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

283

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

Table 5-7. RTI Frequency Divide Rates for RTDEC = 0

RTR[6:4] =

RTR[3:0]

000

(OFF)

001

010

011

100

101

110

111

)

0000 (÷1)

0001 (÷2)

0010 (÷3)

0011 (÷4)

0100 (÷5)

0101 (÷6)

0110 (÷7)

0111 (÷8)

1000 (÷9)

1001 (÷10)

1010 (÷11)

1011 (÷12)

1100 (÷13)

1101 (÷14)

1110 (÷15)

1111 (÷16)

OFF*

OFF

2x2

3x2

4x2

5x2

6x2

7x2

8x2

9x2

2x2

3x2

4x2

5x2

6x2

7x2

8x2

9x2

2x2

3x2

4x2

5x2

6x2

7x2

8x2

9x2

2x2

3x2

4x2

5x2

6x2

7x2

8x2

9x2

2x2

3x2

4x2

5x2

6x2

7x2

8x2

9x2

2x2

3x2

4x2

5x2

6x2

7x2

8x2

9x2

2x2

3x2

4x2

5x2

6x2

7x2

8x2

9x2

10x2

11x2

12x2

13x2

14x2

15x2

16x2

10x2

11x2

12x2

13x2

14x2

15x2

16x2

10x2

11x2

12x2

13x2

14x2

15x2

16x2

10x2

11x2

12x2

13x2

14x2

15x2

16x2

10x2

11x2

12x2

13x2

14x2

15x2

16x2

10x2

11x2

12x2

13x2

14x2

15x2

16x2

10x2

11x2

12x2

13x2

14x2

15x2

16x2

* Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Freescale Semiconductor

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

Table 5-8. RTI Frequency Divide Rates for RTDEC = 1

RTR[6:4] =

100

RTR[3:0]

000

(1x10 )

001

(2x10 )

010

(5x10 )

011

(10x10 )

101

(50x10 )

110

(100x10 )

111

(200x10 )

(20x10 )

0000 (÷1)

0001 (÷2)

0010 (÷3)

0011 (÷4)

0100 (÷5)

0101 (÷6)

0110 (÷7)

0111 (÷8)

1000 (÷9)

1001 (÷10)

1010 (÷11)

1011 (÷12)

1100 (÷13)

1101 (÷14)

1110 (÷15)

1111 (÷16)

1x10

2x10

5x10

10x10

20x10

50x10

100x10

200x10

2x10

4x10

10x10

20x10

40x10

100x10

200x10

400x10

3x10

6x10

15x10

30x10

60x10

150x10

300x10

600x10

4x10

8x10

20x10

40x10

80x10

200x10

400x10

800x10

5x10

10x10

25x10

50x10

100x10

250x10

500x10

1x10

6x10

12x10

30x10

60x10

120x10

300x10

600x10

1.2x10

7x10

14x10

35x10

70x10

140x10

350x10

700x10

1.4x10

8x10

16x10

40x10

80x10

160x10

400x10

800x10

1.6x10

9x10

18x10

45x10

90x10

180x10

450x10

900x10

1.8x10

10 x10

20x10

50x10

100x10

200x10

500x10

1x10

2x10

11 x10

22x10

55x10

110x10

220x10

550x10

1.1x10

2.2x10

12x10

24x10

60x10

120x10

240x10

600x10

1.2x10

2.4x10

13x10

26x10

65x10

130x10

260x10

650x10

1.3x10

2.6x10

14x10

28x10

70x10

140x10

280x10

700x10

1.4x10

2.8x10

15x10

30x10

75x10

150x10

300x10

750x10

1.5x10

3x10

16x10

32x10

80x10

160x10

320x10

800x10

1.6x10

3.2x10

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

285

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.3.2.9

CRG COP Control Register (COPCTL)

This register controls the COP (computer operating properly) watchdog.

Module Base +0x_08

WCOP

RSBCK

CR2

CR1

CR0

WRTMASK

Reset

1. Refer to Device User Guide (Section: CRG) for reset values of WCOP, CR2, CR1, and CR0.

= Unimplemented or Reserved

Figure 5-12. CRG COP Control Register (COPCTL)

Read: Anytime

Write:

1. RSBCK: Anytime in special modes; write to “1” but not to “0” in all other modes

2. WCOP, CR2, CR1, CR0:

— Anytime in special modes

— Write once in all other modes

Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition.

Writing WCOP to “0” has no effect, but counts for the “write once” condition.

The COP time-out period is restarted if one these two conditions is true:

1. Writing a nonzero value to CR[2:0] (anytime in special modes, once in all other modes) with

WRTMASK = 0.

2. Changing RSBCK bit from “0” to “1”.

Table 5-9. COPCTL Field Descriptions

Field

Description

Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected

period. A write during the ﬁrst 75% of the selected period will reset the part. As long as all writes occur during

this window, 0x_55 can be written as often as desired. Once 0x_AA is written after the 0x_55, the time-out logic

restarts and the user must wait until the next window before writing to ARMCOP. Table 5-10 shows the duration

of this window for the seven available COP rates.

WCOP

0 Normal COP operation

1 Window COP operation

COP and RTI Stop in Active BDM Mode Bit

RSBCK

0 Allows the COP and RTI to keep running in active BDM mode.

1 Stops the COP and RTI counters whenever the part is in active BDM mode.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Freescale Semiconductor

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

Table 5-9. COPCTL Field Descriptions (continued)

Field

Description

Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits

WRTMASK while writing the COPCTL register. It is intended for BDM writing the RSBCK without touching the contents of

WCOP and CR[2:0].

0 Write of WCOP and CR[2:0] has an effect with this write of COPCTL

1 Write of WCOP and CR[2:0] has no effect with this write of COPCTL. (Does not count for “write once”.)

2–0

CR[1:0]

COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see Table 5-10). The COP

time-out period is OSCCLK period divided by CR[2:0] value. Writing a nonzero value to CR[2:0] enables the

COP counter and starts the time-out period. A COP counter time-out causes a system reset. This can be

avoided by periodically (before time-out) reinitializing the COP counter via the ARMCOP register.

While all of the following three conditions are true the CR[2:0], WCOP bits are ignored and the COP operates

at highest time-out period (2

cycles) in normal COP mode (Window COP mode disabled):

1) COP is enabled (CR[2:0] is not 000)

2) BDM mode active

3) RSBCK = 0

4) Operation in emulation or special modes

Table 5-10. COP Watchdog Rates

OSCCLK

Cycles to Time-out

CR2

CR1

CR0

COP disabled

OSCCLK cycles are referenced from the previous COP time-out reset

(writing 0x_55/0x_AA to the ARMCOP register)

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

287

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.3.2.10 Reserved Register (FORBYP)

NOTE

This reserved register is designed for factory test purposes only, and is not

intended for general user access. Writing to this register when in special

modes can alter the CRG’s functionality.

Module Base +0x_09

Reset

= Unimplemented or Reserved

Figure 5-13. Reserved Register (FORBYP)

Read: Always read 0x_00 except in special modes

Write: Only in special modes

5.3.2.11 Reserved Register (CTCTL)

NOTE

This reserved register is designed for factory test purposes only, and is not

intended for general user access. Writing to this register when in special test

modes can alter the CRG’s functionality.

Module Base +0x_0A

Reset

= Unimplemented or Reserved

Figure 5-14. Reserved Register (CTCTL)

Read: always read 0x_80 except in special modes

Write: only in special modes

MC9S12XDP512 Data Sheet, Rev. 2.11

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Freescale Semiconductor

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.3.2.12 CRG COP Timer Arm/Reset Register (ARMCOP)

This register is used to restart the COP time-out period.

Module Base +0x_0B

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Figure 5-15. ARMCOP Register Diagram

Read: Always reads 0x_00

Write: Anytime

When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.

When the COP is enabled by setting CR[2:0] nonzero, the following applies:

Writing any value other than 0x_55 or 0x_AA causes a COP reset. To restart the COP time-out

period you must write 0x_55 followed by a write of 0x_AA. Other instructions may be executed

between these writes but the sequence (0x_55, 0x_AA) must be completed prior to COP end of

time-out period to avoid a COP reset. Sequences of 0x_55 writes or sequences of 0x_AA writes

are allowed. When the WCOP bit is set, 0x_55 and 0x_AA writes must be done in the last 25% of

the selected time-out period; writing any value in the ﬁrst 75% of the selected period will cause a

COP reset.

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.4

Functional Description

5.4.1

Functional Blocks

5.4.1.1

Phase Locked Loop (PLL)

The PLL is used to run the MCU from a different time base than the incoming OSCCLK. For increased

ﬂexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency. This offers

a ﬁner multiplication granularity. The PLL can multiply this reference clock by a multiple of 2, 4, 6,...

126,128 based on the SYNR register.

[SYNR + 1]

PLLCLK = 2 × OSCCLK ×

-----------------------------------

[REFDV + 1]

CAUTION

Although it is possible to set the two dividers to command a very high clock

frequency, do not exceed the speciﬁed bus frequency limit for the MCU.

If (PLLSEL = 1), Bus Clock = PLLCLK / 2

The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on

the difference between the output frequency and the target frequency. The PLL can change between

acquisition and tracking modes either automatically or manually.

The VCO has a minimum operating frequency, which corresponds to the self clock mode frequency f

SCM

REFERENCE

LOCK

DETECTOR

REFDV <5:0>

FEEDBACK

EXTAL

XTAL

REDUCED

CONSUMPTION

OSCILLATOR

OSCCLK

REFERENCE

PROGRAMMABLE

DIVIDER

DDPLL SSPLL

PDET

PHASE

DETECTOR

CPUMP

VCO

DOWN

CRYSTAL

MONITOR

DDPLL

LOOP

PROGRAMMABLE

DIVIDER

LOOP

FILTER

XFC

supplied by:

SYN <5:0>

DDPLL SSPLL

PLLCLK

DD SS

Figure 5-16. PLL Functional Diagram

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.4.1.1.1

PLL Operation

The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is

divided in a range of 1 to 64 (REFDV + 1) to output the REFERENCE clock. The VCO output clock,

(PLLCLK) is fed back through the programmable loop divider and is divided in a range of 2 to 128 in

increments of [2 x (SYNR + 1)] to output the FEEDBACK clock. Figure 5-16.

The phase detector then compares the FEEDBACK clock, with the REFERENCE clock. Correction pulses

are generated based on the phase difference between the two signals. The loop ﬁlter then slightly alters the

DC voltage on the external ﬁlter capacitor connected to XFC pin, based on the width and direction of the

correction pulse. The ﬁlter can make fast or slow corrections depending on its mode, as described in the

next subsection. The values of the external ﬁlter network and the reference frequency determine the speed

of the corrections and the stability of the PLL.

The minimum VCO frequency is reached with the XFC pin forced to V

frequency.

. This is the self clock mode

DDPLL

5.4.1.1.2

Acquisition and Tracking Modes

The lock detector compares the frequencies of the FEEDBACK clock, and the REFERENCE clock.

Therefore, the speed of the lock detector is directly proportional to the ﬁnal reference frequency. The

circuit determines the mode of the PLL and the lock condition based on this comparison.

The PLL ﬁlter can be manually or automatically conﬁgured into one of two possible operating modes:

•

Acquisition mode

In acquisition mode, the ﬁlter can make large frequency corrections to the VCO. This mode is used

at PLL start-up or when the PLL has suffered a severe noise hit and the VCO frequency is far off

the desired frequency. When in acquisition mode, the TRACK status bit is cleared in the CRGFLG

•

Tracking mode

In tracking mode, the ﬁlter makes only small corrections to the frequency of the VCO. PLL jitter

is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking

mode when the VCO frequency is nearly correct and the TRACK bit is set in the CRGFLG register.

The PLL can change the bandwidth or operational mode of the loop ﬁlter manually or automatically.

In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between

acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the

PLL clock (PLLCLK) is safe to use as the source for the system and core clocks. If PLL LOCK interrupt

requests are enabled, the software can wait for an interrupt request and then check the LOCK bit. If

interrupt requests are disabled, software can poll the LOCK bit continuously (during PLL start-up, usually)

or at periodic intervals. In either case, only when the LOCK bit is set, is the PLLCLK clock safe to use as

the source for the system and core clocks. If the PLL is selected as the source for the system and core

clocks and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take

appropriate action, depending on the application.

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

The following conditions apply when the PLL is in automatic bandwidth control mode (AUTO = 1):

•

The TRACK bit is a read-only indicator of the mode of the ﬁlter.

The TRACK bit is set when the VCO frequency is within a certain tolerance, ∆ , and is clear when

trk

the VCO frequency is out of a certain tolerance, ∆ .

unt

•

The LOCK bit is a read-only indicator of the locked state of the PLL.

The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆

, and is cleared

Lock

when the VCO frequency is out of a certain tolerance, ∆ .

unl

•

Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling

the LOCK bit.

The PLL can also operate in manual mode (AUTO = 0). Manual mode is used by systems that do not

require an indicator of the lock condition for proper operation. Such systems typically operate well below

the maximum system frequency (f ) and require fast start-up. The following conditions apply when in

sys

manual mode:

•

ACQ is a writable control bit that controls the mode of the ﬁlter. Before turning on the PLL in

manual mode, the ACQ bit should be asserted to conﬁgure the ﬁlter in acquisition mode.

After turning on the PLL by setting the PLLON bit software must wait a given time (t ) before

acq

entering tracking mode (ACQ = 0).

After entering tracking mode software must wait a given time (t ) before selecting the PLLCLK

as the source for system and core clocks (PLLSEL = 1).

5.4.1.2

System Clocks Generator

PLLSEL or SCM

STOP

PHASE

LOCK

LOOP

PLLCLK

SYSCLK

CORE CLOCK

BUS CLOCK

÷2

CLOCK PHASE

GENERATOR

SCM

WAIT(RTIWAI),

STOP(PSTP,PRE),

RTI ENABLE

EXTAL

XTAL

RTI

OSCCLK

OSCILLATOR

WAIT(COPWAI),

STOP(PSTP,PCE),

COP ENABLE

COP

CLOCK

MONITOR

STOP

GATING

CONDITION

OSCILLATOR

CLOCK

= CLOCK GATE

Figure 5-17. System Clocks Generator

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

The clock generator creates the clocks used in the MCU (see Figure 5-17). The gating condition placed on

top of the individual clock gates indicates the dependencies of different modes (STOP, WAIT) and the

setting of the respective conﬁguration bits.

The peripheral modules use the bus clock. Some peripheral modules also use the oscillator clock. The

memory blocks use the bus clock. If the MCU enters self clock mode (see Section 5.4.2.2, “Self Clock

Mode”) oscillator clock source is switched to PLLCLK running at its minimum frequency f

. The bus

SCM

clock is used to generate the clock visible at the ECLK pin. The core clock signal is the clock for the CPU.

The core clock is twice the bus clock as shown in Figure 5-18. But note that a CPU cycle corresponds to

one bus clock.

PLL clock mode is selected with PLLSEL bit in the CLKSEL registerr. When selected, the PLL output

clock drives SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned

off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum

of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and

CPU activity ceases.

CORE CLOCK

BUS CLOCK / ECLK

Figure 5-18. Core Clock and Bus Clock Relationship

5.4.1.3

Clock Monitor (CM)

If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block

generates a clock monitor fail event. The MC9S12XDP512 then asserts self clock mode or generates a

system reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks

is detected no failure is indicated by the oscillator block.The clock monitor function is enabled/disabled

by the CME control bit.

5.4.1.4

Clock Quality Checker

The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker

provides a more accurate check in addition to the clock monitor.

A clock quality check is triggered by any of the following events:

•

Power on reset (POR)

Low voltage reset (LVR)

Wake-up from full stop mode (exit full stop)

Clock monitor fail indication (CM fail)

A time window of 50,000 VCO clock cycles is called check window.

1. VCO clock cycles are generated by the PLL when running at minimum frequency f

SCM

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that

osc ok immediately terminates the current check window. See Figure 5-19 as an example.

check window

49999

50000

VCO

Clock

4096

OSCCLK

4095

osc ok

Figure 5-19. Check Window Example

The sequence for clock quality check is shown in Figure 5-20.

CM fail

Clock OK

exit full stop

POR

yes

SCME = 1 &

FSTWKP = 1

FSTWKP = 0

num = 0

Enter SCM

LVR

yes

Clock Monitor Reset

Enter SCM

num = 0

num = 50

yes

SCM

active?

check window

num=num–1

yes

osc ok

SCME=1

num > 0

yes

SCM

active?

Switch to OSCCLK

Exit SCM

Figure 5-20. Sequence for Clock Quality Check

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

NOTE

Remember that in parallel to additional actions caused by self clock mode

or clock monitor reset handling the clock quality checker continues to

check the OSCCLK signal.

The clock quality checker enables the PLL and the voltage regulator

(VREG) anytime a clock check has to be performed. An ongoing clock

quality check could also cause a running PLL (f

during pseudo stop mode or wait mode.

) and an active VREG

SCM

5.4.1.5

Computer Operating Properly Watchdog (COP)

The COP (free running watchdog timer) enables the user to check that a program is running and

sequencing properly. When the COP is being used, software is responsible for keeping the COP from

timing out. If the COP times out it is an indication that the software is no longer being executed in the

intended sequence; thus a system reset is initiated (see Section 5.4.1.5, “Computer Operating Properly

Watchdog (COP)”). The COP runs with a gated OSCCLK. Three control bits in the COPCTL register

allow selection of seven COP time-out periods.

When COP is enabled, the program must write 0x_55 and 0x_AA (in this order) to the ARMCOP register

during the selected time-out period. Once this is done, the COP time-out period is restarted. If the program

fails to do this and the COP times out, the part will reset. Also, if any value other than 0x_55 or 0x_AA is

written, the part is immediately reset.

Windowed COP operation is enabled by setting WCOP in the COPCTL register. In this mode, writes to

the ARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period.

A premature write will immediately reset the part.

If PCE bit is set, the COP will continue to run in pseudo stop mode.

5.4.1.6

Real Time Interrupt (RTI)

The RTI can be used to generate a hardware interrupt at a ﬁxed periodic rate. If enabled (by setting

RTIE = 1), this interrupt will occur at the rate selected by the RTICTL register. The RTI runs with a gated

OSCCLK. At the end of the RTI time-out period the RTIF ﬂag is set to 1 and a new RTI time-out period

starts immediately.

A write to the RTICTL register restarts the RTI time-out period.

If the PRE bit is set, the RTI will continue to run in pseudo stop mode.

5.4.2

Operating Modes

Normal Mode

5.4.2.1

The MC9S12XDP512 block behaves as described within this speciﬁcation in all normal modes.

1. A Clock Monitor Reset will always set the SCME bit to logical 1.

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.4.2.2

Self Clock Mode

The VCO has a minimum operating frequency, f

. If the external clock frequency is not available due

SCM

to a failure or due to long crystal start-up time, the bus clock and the core clock are derived from the VCO

running at minimum operating frequency; this mode of operation is called self clock mode. This requires

CME = 1 and SCME = 1. If the MCU was clocked by the PLL clock prior to entering self clock mode, the

PLLSEL bit will be cleared. If the external clock signal has stabilized again, the CRG will automatically

select OSCCLK to be the system clock and return to normal mode. Section 5.4.1.4, “Clock Quality

Checker” for more information on entering and leaving self clock mode.

NOTE

In order to detect a potential clock loss the CME bit should be always

enabled (CME = 1)!

If CME bit is disabled and the MCU is conﬁgured to run on PLL clock

(PLLCLK), a loss of external clock (OSCCLK) will not be detected and will

cause the system clock to drift towards the VCO’s minimum frequency

. As soon as the external clock is available again the system clock

SCM

ramps up to its PLL target frequency. If the MCU is running on external

clock any loss of clock will cause the system to go static.

5.4.3

Low Power Options

This section summarizes the low power options available in the MC9S12XDP512.

5.4.3.1

Run Mode

The RTI can be stopped by setting the associated rate select bits to 0.

The COP can be stopped by setting the associated rate select bits to 0.

5.4.3.2

Wait Mode

The WAI instruction puts the MCU in a low power consumption stand-by mode depending on setting of

the individual bits in the CLKSEL register. All individual wait mode conﬁguration bits can be superposed.

This provides enhanced granularity in reducing the level of power consumption during wait mode.

Table 5-11 lists the individual conﬁguration bits and the parts of the MCU that are affected in wait mode

Table 5-11. MCU Conﬁguration During Wait Mode

PLLWAI

RTIWAI

COPWAI

PLL

RTI

Stopped

—

Stopped

—

COP

Stopped

After executing the WAI instruction the core requests the CRG to switch MCU into wait mode. The CRG

then checks whether the PLLWAI bit is asserted (Figure 5-21). Depending on the conﬁguration, the CRG

switches the system and core clocks to OSCCLK by clearing the PLLSEL bit and disables the PLL. As

soon as all clocks are switched off wait mode is active.

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

CPU Req’s

Wait Mode.

PLLWAI=1

Yes

Clear PLLSEL,

Disable PLL

Enter

Wait Mode

CME=1

INT

Wait Mode left

due to external reset

Yes

Exit Wait w.

ext.RESET

CM Fail

Yes

Exit Wait w.

CMRESET

SCME=1

Yes

Exit

Wait Mode

SCMIE=1

Yes

Generate

SCM Interrupt

SCM=1

(Wakeup from Wait)

Exit

Wait Mode

Yes

Enter

SCM

Enter

SCM

Continue w.

Normal OP

Figure 5-21. Wait Mode Entry/Exit Sequence

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

There are four different scenarios for the CRG to restart the MCU from wait mode:

•

External reset

Clock monitor reset

COP reset

Any interrupt

If the MCU gets an external reset or COP reset during wait mode active, the CRG asynchronously restores

all conﬁguration bits in the register space to its default settings and starts the reset generator. After

completing the reset sequence processing begins by fetching the normal or COP reset vector. Wait mode

is left and the MCU is in run mode again.

If the clock monitor is enabled (CME = 1) the MCU is able to leave wait mode when loss of

oscillator/external clock is detected by a clock monitor fail. If the SCME bit is not asserted the CRG

generates a clock monitor fail reset (CMRESET). The CRG’s behavior for CMRESET is the same

compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the

SCME bit is asserted the CRG generates a SCM interrupt if enabled (SCMIE = 1). After generating the

interrupt the CRG enters self-clock mode and starts the clock quality checker (Section 5.4.1.4, “Clock

Quality Checker”). Then the MCU continues with normal operation.If the SCM interrupt is blocked by

SCMIE = 0, the SCMIF ﬂag will be asserted and clock quality checks will be performed but the MCU will

not wake-up from wait-mode.

If any other interrupt source (e.g., RTI) triggers exit from wait mode, the MCU immediately continues with

normal operation. If the PLL has been powered-down during wait mode, the PLLSEL bit is cleared and

the MCU runs on OSCCLK after leaving wait mode. The software must manually set the PLLSEL bit

again, in order to switch system and core clocks to the PLLCLK.

If wait mode is entered from self-clock mode the CRG will continue to check the clock quality until clock

check is successful. The PLL and voltage regulator (VREG) will remain enabled.

Table 5-12 summarizes the outcome of a clock loss while in wait mode.

5.4.3.3

System Stop Mode

All clocks are stopped in STOP mode, dependent of the setting of the PCE, PRE, and PSTP bit. The

oscillator is disabled in STOP mode unless the PSTP bit is set. All counters and dividers remain frozen but

do not initialize. If the PRE or PCE bits are set, the RTI or COP continues to run in pseudo stop mode. In

addition to disabling system and core clocks the CRG requests other functional units of the MCU (e.g.,

voltage-regulator) to enter their individual power saving modes (if available). This is the main difference

between pseudo stop mode and wait mode.

If the PLLSEL bit is still set when entering stop mode, the CRG will switch the system and core clocks to

OSCCLK by clearing the PLLSEL bit. Then the CRG disables the PLL, disables the core clock and ﬁnally

disables the remaining system clocks. As soon as all clocks are switched off, stop mode is active.

If pseudo stop mode (PSTP = 1) is entered from self-clock mode, the CRG will continue to check the clock

quality until clock check is successful. The PLL and the voltage regulator (VREG) will remain enabled. If

full stop mode (PSTP = 0) is entered from self-clock mode, an ongoing clock quality check will be

stopped. A complete timeout window check will be started when stop mode is left again.

Wake-up from stop mode also depends on the setting of the PSTP bit.

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

Table 5-12. Outcome of Clock Loss in Wait Mode

CME

SCME

SCMIE

CRG Actions

Clock failure -->

No action, clock loss not detected.

Clock failure -->

CRG performs Clock Monitor Reset immediately

Clock failure -->

Scenario 1: OSCCLK recovers prior to exiting wait mode.

– MCU remains in wait mode,

– VREG enabled,

– PLL enabled,

– SCM activated,

– Start clock quality check,

– Set SCMIF interrupt ﬂag.

Some time later OSCCLK recovers.

– CM no longer indicates a failure,

– 4096 OSCCLK cycles later clock quality check indicates clock o.k.,

– SCM deactivated,

– PLL disabled depending on PLLWAI,

– VREG remains enabled (never gets disabled in wait mode).

– MCU remains in wait mode.

Some time later either a wakeup interrupt occurs (no SCM interrupt)

– Exit wait mode using OSCCLK as system clock (SYSCLK),

– Continue normal operation.

or an External Reset is applied.

– Exit wait mode using OSCCLK as system clock,

– Start reset sequence.

Scenario 2: OSCCLK does not recover prior to exiting wait mode.

– MCU remains in wait mode,

– VREG enabled,

– PLL enabled,

– SCM activated,

– Start clock quality check,

– Set SCMIF interrupt ﬂag,

– Keep performing clock quality checks (could continue inﬁnitely) while in wait mode.

Some time later either a wakeup interrupt occurs (no SCM interrupt)

– Exit wait mode in SCM using PLL clock (f

) as system clock,

SCM

– Continue to perform additional clock quality checks until OSCCLK is o.k. again.

or an External RESET is applied.

– Exit wait mode in SCM using PLL clock (f

– Start reset sequence,

) as system clock,

SCM

– Continue to perform additional clock quality checks until OSCCLKis o.k.again.

Clock failure -->

– VREG enabled,

– PLL enabled,

– SCM activated,

– Start clock quality check,

– SCMIF set.

SCMIF generates self clock mode wakeup interrupt.

– Exit wait mode in SCM using PLL clock (f

) as system clock,

SCM

– Continue to perform a additional clock quality checks until OSCCLK is o.k. again.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

Core req’s

Stop Mode.

Clear PLLSEL,

Disable PLL

Stop Mode left

due to external reset

Enter

Stop Mode

Exit Stop w.

ext.RESET

Yes

CME=1

INT

Yes

PSTP=1

Yes

SCME=1 &

FSTWKP=1

CM fail

Yes

Clock

Exit Stop w.

CMRESET

SCME=1

Yes

Exit Stop w.

CMRESET

SCME=1

Yes

Exit

Stop Mode

Yes

Exit

Stop Mode

SCMIE=1

Yes

Generate

SCM Interrupt

(Wakeup from Stop)

Exit

Stop Mode

Exit

Stop Mode

Exit

Stop Mode

SCM=1

Yes

Enter SCM

SCMIF not

set!

Enter

SCM

Enter

SCM

Enter

SCM

Continue w.

normal OP

Figure 5-22. Stop Mode Entry/Exit Sequence

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.4.3.3.1

Wake-up from Pseudo Stop Mode (PSTP=1)

Wake-up from pseudo stop mode is the same as wake-up from wait mode. There are also four different

scenarios for the CRG to restart the MCU from pseudo stop mode:

•

External reset

Clock monitor fail

COP reset

Wake-up interrupt

If the MCU gets an external reset or COP reset during pseudo stop mode active, the CRG asynchronously

restores all conﬁguration bits in the register space to its default settings and starts the reset generator. After

completing the reset sequence processing begins by fetching the normal or COP reset vector. pseudo stop

mode is left and the MCU is in run mode again.

If the clock monitor is enabled (CME = 1), the MCU is able to leave pseudo stop mode when loss of

oscillator/external clock is detected by a clock monitor fail. If the SCME bit is not asserted the CRG

generates a clock monitor fail reset (CMRESET). The CRG’s behavior for CMRESET is the same

compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the

SCME bit is asserted the CRG generates a SCM interrupt if enabled (SCMIE = 1). After generating the

interrupt the CRG enters self-clock mode and starts the clock quality checker (Section 5.4.1.4, “Clock

Quality Checker”). Then the MCU continues with normal operation. If the SCM interrupt is blocked by

SCMIE=0, the SCMIF ﬂag will be asserted but the CRG will not wake-up from pseudo stop mode.

If any other interrupt source (e.g., RTI) triggers exit from pseudo stop mode, the MCU immediately

continues with normal operation. Because the PLL has been powered-down during stop mode, the

PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving stop mode. The software must set the

PLLSEL bit again, in order to switch system and core clocks to the PLLCLK.

Table 5-13 summarizes the outcome of a clock loss while in pseudo stop mode.

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

Table 5-13. Outcome of Clock Loss in Pseudo Stop Mode

CME

SCME

SCMIE

CRG Actions

Clock failure -->

No action, clock loss not detected.

Clock failure -->

CRG performs Clock Monitor Reset immediately

Clock Monitor failure -->

Scenario 1: OSCCLK recovers prior to exiting pseudo stop mode.

– MCU remains in pseudo stop mode,

– VREG enabled,

– PLL enabled,

– SCM activated,

– Start clock quality check,

– Set SCMIF interrupt ﬂag.

Some time later OSCCLK recovers.

– CM no longer indicates a failure,

– 4096 OSCCLK cycles later clock quality check indicates clock o.k.,

– SCM deactivated,

– PLL disabled,

– VREG disabled.

– MCU remains in pseudo stop mode.

Some time later either a wakeup interrupt occurs (no SCM interrupt)

– Exit pseudo stop mode using OSCCLK as system clock (SYSCLK),

– Continue normal operation.

or an External Reset is applied.

– Exit pseudo stop mode using OSCCLK as system clock,

– Start reset sequence.

Scenario 2: OSCCLK does not recover prior to exiting pseudo stop mode.

– MCU remains in pseudo stop mode,

– VREG enabled,

– PLL enabled,

– SCM activated,

– Start clock quality check,

– Set SCMIF interrupt ﬂag,

– Keep performing clock quality checks (could continue inﬁnitely) while

in pseudo stop mode.

Some time later either a wakeup interrupt occurs (no SCM interrupt)

– Exit pseudo stop mode in SCM using PLL clock (f

) as system clock

SCM

– Continue to perform additional clock quality checks until OSCCLK is o.k. again.

or an External RESET is applied.

– Exit pseudo stop mode in SCM using PLL clock (f

– Start reset sequence,

) as system clock

SCM

– Continue to perform additional clock quality checks until OSCCLK is o.k.again.

Clock failure -->

– VREG enabled,

– PLL enabled,

– SCM activated,

– Start clock quality check,

– SCMIF set.

SCMIF generates self clock mode wakeup interrupt.

– Exit pseudo stop mode in SCM using PLL clock (f

) as system clock,

SCM

– Continue to perform a additional clock quality checks until OSCCLK is o.k. again.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.4.3.3.2

Wake-up from Full Stop (PSTP = 0)

The MCU requires an external interrupt or an external reset in order to wake-up from stop-mode.

If the MCU gets an external reset during full stop mode active, the CRG asynchronously restores all

conﬁguration bits in the register space to its default settings and will perform a maximum of 50 clock

check_windows (see Section 5.4.1.4, “Clock Quality Checker”). After completing the clock quality check

the CRG starts the reset generator. After completing the reset sequence processing begins by fetching the

normal reset vector. Full stop-mode is left and the MCU is in run mode again.

If the MCU is woken-up by an interrupt and the fast wake-up feature is disabled (FSTWKP = 0 or

SCME = 0), the CRG will also perform a maximum of 50 clock check_windows (see Section 5.4.1.4,

“Clock Quality Checker”). If the clock quality check is successful, the CRG will release all system and

core clocks and will continue with normal operation. If all clock checks within the Timeout-Window are

failing, the CRG will switch to self-clock mode or generate a clock monitor reset (CMRESET) depending

on the setting of the SCME bit.

If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP = 1 and

SCME = 1), the system will immediately resume operation in self-clock mode (see Section 5.4.1.4, “Clock

Quality Checker”). The SCMIF ﬂag will not be set. The system will remain in self-clock mode with

oscillator disabled until FSTWKP bit is cleared. The clearing of FSTWKP will start the oscillator and the

clock quality check. If the clock quality check is successful, the CRG will switch all system clocks to

oscillator clock. The SCMIF ﬂag will be set. See application examples in Figure 5-23 and Figure 5-24.

Because the PLL has been powered-down during stop-mode the PLLSEL bit is cleared and the MCU runs

on OSCCLK after leaving stop-mode. The software must manually set the PLLSEL bit again, in order to

switch system and core clocks to the PLLCLK.

NOTE

In full stop mode or self-clock mode caused by the fast wake-up feature, the

clock monitor and the oscillator are disabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

CPU resumes program execution immediately

Instruction

IRQ Service

Interrupt

IRQ Service

STOP

FSTWKP=1

STOP

SCME=1

Interrupt

Power Saving

Oscillator Clock

Oscillator Disabled

PLL Clock

Core Clock

Self-Clock Mode

Figure 5-23. Fast Wake-up from Full Stop Mode: Example 1

CPU resumes program execution immediately

Instruction

Freq. Critical

Instr. Possible

Freq. Uncritical

Instructions

FSTWKP=1

SCME=1

IRQ Service

FSTWKP=0

STOP

SCMIE=1

IRQ Interrupt

SCM Interrupt

Clock Quality Check

Oscillator Clock

Oscillator Disabled

OSC Startup

PLL Clock

Core Clock

Self-Clock Mode

Figure 5-24. Fast Wake-up from Full Stop Mode: Example 2

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.5

Resets

This section describes how to reset the MC9S12XDP512, and how the MC9S12XDP512 itself controls the

reset of the MCU. It explains all special reset requirements. Since the reset generator for the MCU is part

of the CRG, this section also describes all automatic actions that occur during or as a result of individual

reset conditions. The reset values of registers and signals are provided in Section 5.3, “Memory Map and

vector addresses and priorities.

Table 5-14. Reset Summary

Reset Source

Local Enable

Power on Reset

Low Voltage Reset

External Reset

None

Illegal Address Reset

Clock Monitor Reset

COP Watchdog Reset

None

PLLCTL (CME = 1, SCME = 0)

COPCTL (CR[2:0] nonzero)

5.5.1

Description of Reset Operation

The reset sequence is initiated by any of the following events:

•

Low level is detected at the RESET pin (external reset)

Power on is detected

Low voltage is detected

Illegal Address Reset is detected (see S12XMMC Block Guide for details)

COP watchdog times out

Clock monitor failure is detected and self-clock mode was disabled (SCME=0)

Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles

(see Figure 5-25). Since entry into reset is asynchronous, it does not require a running SYSCLK. However,

the internal reset circuit of the MC9S12XDP512 cannot sequence out of current reset condition without a

running SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional

SYSCLK cycles depending on the internal synchronization latency. After 128 + n SYSCLK cycles the

RESET pin is released. The reset generator of the MC9S12XDP512 waits for additional 64 SYSCLK

cycles and then samples the RESET pin to determine the originating source. Table 5-15 shows which

vector will be fetched.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

Table 5-15. Reset Vector Selection

Sampled RESET Pin

(64 cycles

Clock Monitor

Reset Pending

COP

Reset Pending

Vector Fetch

after release)

POR / LVR / Illegal Address Reset / External Reset

Clock Monitor Reset

COP Reset

POR / LVR / Illegal Address Reset / External Reset

with rise of RESET pin

NOTE

External circuitry connected to the RESET pin should not include a large

capacitance that would interfere with the ability of this signal to rise to a

valid logic 1 within 64 SYSCLK cycles after the low drive is released.

The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long

reset sequence. The reset generator circuitry always makes sure the internal reset is deasserted

synchronously after completion of the 192 SYSCLK cycles. In case the RESET pin is externally driven

low for more than these 192 SYSCLK cycles (external reset), the internal reset remains asserted too.

RESET

) (

CRG drives RESET pin low

RESET pin

released

)

(

)

(

SYSCLK

(

128 + n cycles

64 cycles

With n being

Possibly

RESET

min 3 / max 6

cycles depending

on internal

synchronization

delay

SYSCLK

not

running

driven low

externally

Figure 5-25. RESET Timing

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.5.2

Clock Monitor Reset

The MC9S12XDP512 generates a clock monitor reset in case all of the following conditions are true:

•

Clock monitor is enabled (CME = 1)

Loss of clock is detected

Self-clock mode is disabled (SCME = 0).

The reset event asynchronously forces the conﬁguration registers to their default settings (see Section 5.3,

“Memory Map and Register Deﬁnition”). In detail the CME and the SCME are reset to logical ‘1’ (which

doesn’t change the state of the CME bit, because it has already been set). As a consequence the CRG

immediately enters self clock mode and starts its internal reset sequence. In parallel the clock quality check

starts. As soon as clock quality check indicates a valid oscillator clock the CRG switches to OSCCLK and

leaves self clock mode. Since the clock quality checker is running in parallel to the reset generator, the

CRG may leave self clock mode while still completing the internal reset sequence. When the reset

sequence is ﬁnished, the CRG checks the internally latched state of the clock monitor fail circuit. If a clock

monitor fail is indicated, processing begins by fetching the clock monitor reset vector.

5.5.3

Computer Operating Properly Watchdog (COP) Reset

When COP is enabled, the CRG expects sequential write of 0x_55 and 0x_AA (in this order) to the

ARMCOP register during the selected time-out period. Once this is done, the COP time-out period restarts.

If the program fails to do this the CRG will generate a reset. Also, if any value other than 0x_55 or 0x_AA

is written, the CRG immediately generates a reset. In case windowed COP operation is enabled writes

(0x_55 or 0x_AA) to the ARMCOP register must occur in the last 25% of the selected time-out period. A

premature write the CRG will immediately generate a reset.

As soon as the reset sequence is completed the reset generator checks the reset condition. If no clock

monitor failure is indicated and the latched state of the COP timeout is true, processing begins by fetching

the COP vector.

5.5.4

Power On Reset, Low Voltage Reset

The on-chip voltage regulator detects when V to the MCU has reached a certain level and asserts power

on reset or low voltage reset or both. As soon as a power on reset or low voltage reset is triggered the CRG

performs a quality check on the incoming clock signal. As soon as clock quality check indicates a valid

oscillator clock signal, the reset sequence starts using the oscillator clock. If after 50 check windows the

clock quality check indicated a non-valid oscillator clock, the reset sequence starts using self-clock mode.

Figure 5-26 and Figure 5-27 show the power-up sequence for cases when the RESET pin is tied to V

and when the RESET pin is held low.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

Clock Quality Check

(no Self-Clock Mode)

RESET

) (

Internal POR

) (

128 SYSCLK

Internal RESET

64 SYSCLK

) (

Figure 5-26. RESET Pin Tied to V (by a pull-up resistor)

Clock Quality Check

(no Self Clock Mode)

RESET

) (

Internal POR

) (

128 SYSCLK

64 SYSCLK

Internal RESET

) (

Figure 5-27. RESET Pin Held Low Externally

5.6

Interrupts

The interrupts/reset vectors requested by the CRG are listed in Table 5-16. Refer to MCU speciﬁcation for

related vector addresses and priorities.

Table 5-16. CRG Interrupt Vectors

CCR

Mask

Interrupt Source

Local Enable

Real time interrupt

LOCK interrupt

SCM interrupt

I bit

CRGINT (RTIE)

CRGINT (LOCKIE)

CRGINT (SCMIE)

5.6.1

Real Time Interrupt

The MC9S12XDP512 generates a real time interrupt when the selected interrupt time period elapses. RTI

interrupts are locally disabled by setting the RTIE bit to 0. The real time interrupt ﬂag (RTIF) is set to1

when a timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit.

The RTI continues to run during pseudo stop mode if the PRE bit is set to 1. This feature can be used for

periodic wakeup from pseudo stop if the RTI interrupt is enabled.

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

5.6.2

PLL Lock Interrupt

The MC9S12XDP512 generates a PLL Lock interrupt when the LOCK condition of the PLL has changed,

either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting

the LOCKIE bit to 0. The PLL Lock interrupt ﬂag (LOCKIF) is set to1 when the LOCK condition has

changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.

5.6.3

Self Clock Mode Interrupt

The MC9S12XDP512 generates a self clock mode interrupt when the SCM condition of the system has

changed, either entered or exited self clock mode. SCM conditions can only change if the self clock mode

enable bit (SCME) is set to 1. SCM conditions are caused by a failing clock quality check after power on

reset (POR) or low voltage reset (LVR) or recovery from full stop mode (PSTP = 0) or clock monitor

failure. For details on the clock quality check refer to Section 5.4.1.4, “Clock Quality Checker”. If the

clock monitor is enabled (CME = 1) a loss of external clock will also cause a SCM condition (SCME = 1).

SCM interrupts are locally disabled by setting the SCMIE bit to 0. The SCM interrupt ﬂag (SCMIF) is set

to1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 5 Clocks and Reset Generator (S12CRGV6)

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 6

Pierce Oscillator (S12XOSCLCPV1)

6.1

Introduction

The Pierce oscillator (XOSC) module provides a robust, low-noise and low-power clock source. The

module will be operated from the V supply rail (2.5 V nominal) and require the minimum number

DDPLL

of external components. It is designed for optimal start-up margin with typical crystal oscillators.

6.1.1

Features

The XOSC will contain circuitry to dynamically control current gain in the output amplitude. This ensures

a signal with low harmonic distortion, low power and good noise immunity.

•

High noise immunity due to input hysteresis

Low RF emissions with peak-to-peak swing limited dynamically

Transconductance (gm) sized for optimum start-up margin for typical oscillators

Dynamic gain control eliminates the need for external current limiting resistor

Integrated resistor eliminates the need for external bias resistor

Low power consumption:

— Operates from 2.5 V (nominal) supply

— Amplitude control limits power

•

Clock monitor

6.1.2

Modes of Operation

Two modes of operation exist:

1. Loop controlled Pierce oscillator

2. External square wave mode featuring also full swing Pierce without internal feedback resistor

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 6 Pierce Oscillator (S12XOSCLCPV1)

6.1.3

Block Diagram

Figure 6-1 shows a block diagram of the XOSC.

Monitor_Failure

OSCCLK

Clock

Monitor

Peak

Detector

Gain Control

= 2.5 V

DDPLL

XTAL

EXTAL

Figure 6-1. XOSC Block Diagram

6.2

External Signal Description

This section lists and describes the signals that connect off chip

6.2.1

and V

— Operating and Ground Voltage Pins

SSPLL

DDPLL

Theses pins provides operating voltage (V

) and ground (V

) for the XOSC circuitry. This

DDPLL

SSPLL

allows the supply voltage to the XOSC to be independently bypassed.

6.2.2

EXTAL and XTAL — Input and Output Pins

These pins provide the interface for either a crystal or a CMOS compatible clock to control the internal

clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator ampliﬁer.

XTAL is the output of the crystal oscillator ampliﬁer. The MCU internal system clock is derived from the

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 6 Pierce Oscillator (S12XOSCLCPV1)

EXTAL input frequency. In full stop mode (PSTP = 0), the EXTAL pin is pulled down by an internal

resistor of typical 200 kΩ.

NOTE

Freescale recommends an evaluation of the application board and chosen

resonator or crystal by the resonator or crystal supplier.

Loop controlled circuit is not suited for overtone resonators and crystals.

EXTAL

MCU

Crystal or

Ceramic Resonator

XTAL

SSPLL

Figure 6-2. Loop Controlled Pierce Oscillator Connections (XCLKS = 0)

NOTE

Full swing Pierce circuit is not suited for overtone resonators and crystals

without a careful component selection.

EXTAL

MCU

Crystal or

Ceramic Resonator

RS*

XTAL

SSPLL

* R can be zero (shorted) when use with higher frequency crystals.

Refer to manufacturer’s data.

Figure 6-3. Full Swing Pierce Oscillator Connections (XCLKS = 1)

CMOS Compatible

External Oscillator

EXTAL

MCU

Level)

DDPLL

XTAL

Not Connected

Figure 6-4. External Clock Connections (XCLKS = 1)

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 6 Pierce Oscillator (S12XOSCLCPV1)

6.2.3

XCLKS — Input Signal

The XCLKS is an input signal which controls whether a crystal in combination with the internal loop

controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock

circuitry is used. Refer to the Device Overview chapter for polarity and sampling conditions of the XCLKS

pin. Table 6-1 lists the state coding of the sampled XCLKS signal.

Table 6-1. Clock Selection Based on XCLKS

XCLKS

Description

Loop controlled Pierce oscillator selected

Full swing Pierce oscillator/external clock selected

6.3

Memory Map and Register Deﬁnition

The CRG contains the registers and associated bits for controlling and monitoring the oscillator module.

6.4

Functional Description

The XOSC module has control circuitry to maintain the crystal oscillator circuit voltage level to an optimal

level which is determined by the amount of hysteresis being used and the maximum oscillation range.

The oscillator block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is

intended to be connected to either a crystal or an external clock source. The selection of loop controlled

Pierce oscillator or full swing Pierce oscillator/external clock depends on the XCLKS signal which is

sampled during reset. The XTAL pin is an output signal that provides crystal circuit feedback.

A buffered EXTAL signal becomes the internal clock. To improve noise immunity, the oscillator is

and V

power supply pins.

DDPLL

SSPLL

6.4.1

Gain Control

A closed loop control system will be utilized whereby the ampliﬁer is modulated to keep the output

waveform sinusoidal and to limit the oscillation amplitude. The output peak to peak voltage will be kept

above twice the maximum hysteresis level of the input buffer. Electrical speciﬁcation details are provided

in the Electrical Characteristics appendix.

6.4.2

Clock Monitor

The clock monitor circuit is based on an internal RC time delay so that it can operate without any MCU

clocks. If no OSCCLK edges are detected within this RC time delay, the clock monitor indicates failure

which asserts self-clock mode or generates a system reset depending on the state of SCME bit. If the clock

monitor is disabled or the presence of clocks is detected no failure is indicated.The clock monitor function

is enabled/disabled by the CME control bit, described in the CRG block description chapter.

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Chapter 6 Pierce Oscillator (S12XOSCLCPV1)

6.4.3

Wait Mode Operation

During wait mode, XOSC is not impacted.

6.4.4

Stop Mode Operation

XOSC is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled.

During pseudo-stop mode, XOSC is not impacted.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 6 Pierce Oscillator (S12XOSCLCPV1)

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Chapter 7

Analog-to-Digital Converter (ATD10B16CV4)

7.1

Introduction

The ATD10B16C is a 16-channel, 10-bit, multiplexed input successive approximation analog-to-digital

converter. Refer to the Electrical Speciﬁcations chapter for ATD accuracy.

7.1.1

Features

•

8-/10-bit resolution

7 µs, 10-bit single conversion time

Sample buffer ampliﬁer

Programmable sample time

Left/right justiﬁed, signed/unsigned result data

External trigger control

Conversion completion interrupt generation

Analog input multiplexer for 16 analog input channels

Analog/digital input pin multiplexing

1 to 16 conversion sequence lengths

Continuous conversion mode

Multiple channel scans

Conﬁgurable external trigger functionality on any AD channel or any of four additional trigger

inputs. The four additional trigger inputs can be chip external or internal. Refer to device

speciﬁcation for availability and connectivity

•

Conﬁgurable location for channel wrap around (when converting multiple channels in a sequence)

7.1.2

Modes of Operation

There is software programmable selection between performing single or continuous conversion on a

single channel or multiple channels.

7.1.3

Block Diagram

Refer to Figure 7-1 for a block diagram of the ATD0B16C block.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

Bus Clock

Clock

ATD clock

ATD10B16C

Prescaler

Trigger

Mux

ETRIG0

ETRIG1

ETRIG2

Sequence Complete

Interrupt

Mode and

Timing Control

ETRIG3

(see Device Overview

chapter for availability

and connectivity)

ATDDIEN

ATDCTL1

Results

ATD 0

ATD 1

ATD 2

ATD 3

ATD 4

ATD 5

ATD 6

ATD 7

ATD 8

ATD 9

ATD 10

ATD 11

ATD 12

ATD 13

ATD 14

ATD 15

PORTAD

DDA

SSA

Successive

Approximation

and DAC

AN15

AN14

AN13

AN12

AN11

AN10

AN9

Sample & Hold

AN8

Comparator

Analog

MUX

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

Figure 7-1. ATD10B16C Block Diagram

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

7.2

External Signal Description

This section lists all inputs to the ATD10B16C block.

7.2.1

ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input

Channel x Pins

This pin serves as the analog input channel x. It can also be conﬁgured as general-purpose digital input

and/or external trigger for the ATD conversion.

7.2.2

ETRIG3, ETRIG2, ETRIG1, ETRIG0 — External Trigger Pins

These inputs can be conﬁgured to serve as an external trigger for the ATD conversion.

Refer to the Device Overview chapter for availability and connectivity of these inputs.

7.2.3

V , V — High Reference Voltage Pin, Low Reference Voltage Pin

is the high reference voltage, V is the low reference voltage for ATD conversion.

7.2.4

, V

— Analog Circuitry Power Supply Pins

DDA

These pins are the power supplies for the analog circuitry of the MC9S12XDP512 block.

SSA

7.3

Memory Map and Register Deﬁnition

This section provides a detailed description of all registers accessible in the ATD10B16C.

7.3.1

Module Memory Map

Table 7-1 gives an overview of all ATD10B16C registers

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

Table 7-1. MC9S12XDP512 Memory Map

Address Offset

Use

Access

0x0000

0x0001

ATD Control Register 0 (ATDCTL0)

ATD Control Register 1 (ATDCTL1)

ATD Control Register 2 (ATDCTL2)

ATD Control Register 3 (ATDCTL3)

ATD Control Register 4 (ATDCTL4)

ATD Control Register 5 (ATDCTL5)

ATD Status Register 0 (ATDSTAT0)

Unimplemented

R/W

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

0x0008

ATD Test Register 0 (ATDTEST0)

0x0009

ATD Test Register 1 (ATDTEST1)

ATD Status Register 2 (ATDSTAT2)

R/W

0x000A

0x000B

ATD Status Register 1 (ATDSTAT1)

0x000C

ATD Input Enable Register 0 (ATDDIEN0)

ATD Input Enable Register 1 (ATDDIEN1)

Port Data Register 0 (PORTAD0)

R/W

0x000D

0x000E

0x000F

Port Data Register 1 (PORTAD1)

0x0010, 0x0011

0x0012, 0x0013

0x0014, 0x0015

0x0016, 0x0017

0x0018, 0x0019

0x001A, 0x001B

0x001C, 0x001D

0x001E, 0x001F

0x0020, 0x0021

0x0022, 0x0023

0x0024, 0x0025

0x0026, 0x0027

0x0028, 0x0029

0x002A, 0x002B

0x002C, 0x002D

0x002E, 0x002F

ATD Result Register 0 (ATDDR0H, ATDDR0L)

ATD Result Register 1 (ATDDR1H, ATDDR1L)

ATD Result Register 2 (ATDDR2H, ATDDR2L)

ATD Result Register 3 (ATDDR3H, ATDDR3L)

ATD Result Register 4 (ATDDR4H, ATDDR4L)

ATD Result Register 5 (ATDDR5H, ATDDR5L)

ATD Result Register 6 (ATDDR6H, ATDDR6L)

ATD Result Register 7 (ATDDR7H, ATDDR7L)

ATD Result Register 8 (ATDDR8H, ATDDR8L)

ATD Result Register 9 (ATDDR9H, ATDDR9L)

ATD Result Register 10 (ATDDR10H, ATDDR10L)

ATD Result Register 11 (ATDDR11H, ATDDR11L)

ATD Result Register 12 (ATDDR12H, ATDDR12L)

ATD Result Register 13 (ATDDR13H, ATDDR13L)

ATD Result Register 14 (ATDDR14H, ATDDR14L)

ATD Result Register 15 (ATDDR15H, ATDDR15L)

R/W

ATDTEST0 is intended for factory test purposes only.

NOTE

is deﬁned at the MCU level and the Address Offset is deﬁned at the module

level.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

7.3.2

This section describes in address order all the ATD10B16C registers and their individual bits.

Name

Bit 7

Bit 0

0x0000

ATDCTL0

WRAP3

WRAP2

WRAP1

WRAP0

0x0001

ATDCTL1

ETRIGSEL

ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0

ASCIF

0x0002

ATDCTL2

ADPU

AFFC

S8C

AWAI

S4C

ETRIGLE

S2C

ETRIGP

ETRIGE

ASCIE

FRZ1

PRS1

0x0003

ATDCTL3

S1C

FIFO

FRZ0

PRS0

0x0004

ATDCTL4

SRES8

DJM

SMP1

SMP0

SCAN

ETORF

PRS4

PRS3

PRS2

0x0005

ATDCTL5

DSGN

MULT

0x0006

ATDSTAT0

CC3

CC2

CC1

CC0

SCF

FIFOR

0x0007

Unimplemented

0x0008

Unimplemented

ATDTEST0

0x0009

ATDTEST1

Unimplemented

CCF12

0x000A

ATDSTAT2

CCF15

CCF7

CCF14

CCF6

CCF13

CCF5

CCF11

CCF3

CCF10

CCF2

CCF9

CCF1

CCF8

0x000B

ATDSTAT1

CCF4

CCF0

IEN8

0x000C

ATDDIEN0

IEN15

IEN14

IEN13

IEN12

IEN11

IEN10

IEN9

= Unimplemented or Reserved

u = Unaffected

Figure 7-2. ATD Register Summary

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

Bit 7

Bit 0

IEN0

Name

0x000D

ATDDIEN1

IEN7

IEN6

IEN5

IEN4

IEN3

IEN2

IEN1

PTAD9

0x000E

PTAD15

PTAD14

PTAD13

PTAD12

PTAD11

PTAD10

PTAD8

PORTAD0

0x000F

PTAD7

PTAD6

PTAD5

PTAD4

PTAD3

PTAD2

PTAD1

PTAD0

PORTAD1

R BIT 9 MSB

BIT 7 MSB

BIT 8

BIT 6

BIT 7

BIT 5

BIT 6

BIT 4

BIT 5

BIT 3

BIT 4

BIT 2

BIT 3

BIT 1

BIT 2

BIT 0

0x0010–0x002F

ATDDRxH–

ATDDRxL

BIT 1

BIT 0

= Unimplemented or Reserved

u = Unaffected

Figure 7-2. ATD Register Summary (continued)

7.3.2.1

ATD Control Register 0 (ATDCTL0)

Writes to this register will abort current conversion sequence but will not start a new sequence.

Module Base + 0x0000

WRAP3

WRAP2

WRAP1

WRAP0

Reset

= Unimplemented or Reserved

Figure 7-3. ATD Control Register 0 (ATDCTL0)

Read: Anytime

Write: Anytime

Table 7-2. ATDCTL0 Field Descriptions

Description

Field

3:0

Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing

WRAP[3:0] multi-channel conversions. The coding is summarized in Table 7-3.

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

Table 7-3. Multi-Channel Wrap Around Coding

Multiple Channel Conversions

(MULT = 1) Wrap Around to AN0

after Converting

WRAP3

WRAP2

WRAP1

WRAP0

Reserved

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

AN12

AN13

AN14

AN15

7.3.2.2

ATD Control Register 1 (ATDCTL1)

Writes to this register will abort current conversion sequence but will not start a new sequence.

Module Base + 0x0001

ETRIGSEL

ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0

Reset

= Unimplemented or Reserved

Figure 7-4. ATD Control Register 1 (ATDCTL1)

Read: Anytime

Write: Anytime

Table 7-4. ATDCTL1 Field Descriptions

Description

Field

External Trigger Source Select — This bit selects the external trigger source to be either one of the AD

ETRIGSEL channels or one of the ETRIG[3:0] inputs. See device speciﬁcation for availability and connectivity of

ETRIG[3:0] inputs. If ETRIG[3:0] input option is not available, writing a 1 to ETRISEL only sets the bit but has

no effect, that means one of the AD channels (selected by ETRIGCH[3:0]) remains the source for external

trigger. The coding is summarized in Table 7-5.

3:0

External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG[3:0] inputs

ETRIGCH[3:0] as source for the external trigger. The coding is summarized in Table 7-5.

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

Table 7-5. External Trigger Channel Select Coding

ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0

External Trigger Source

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

AN12

AN13

AN14

AN15

ETRIG0

ETRIG1

ETRIG2

ETRIG3

Reserved

Only if ETRIG[3:0] input option is available (see device speciﬁcation), else ETRISEL is ignored, that means

external trigger source remains on one of the AD channels selected by ETRIGCH[3:0]

7.3.2.3

ATD Control Register 2 (ATDCTL2)

This register controls power down, interrupt and external trigger. Writes to this register will abort current

conversion sequence but will not start a new sequence.

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

Module Base + 0x0002

ASCIF

ADPU

AFFC

AWAI

ETRIGLE

ETRIGP

ETRIGE

ASCIE

Reset

= Unimplemented or Reserved

Figure 7-5. ATD Control Register 2 (ATDCTL2)

Read: Anytime

Write: Anytime

Table 7-6. ATDCTL2 Field Descriptions

Description

Field

ATD Power Down — This bit provides on/off control over the ATD10B16C block allowing reduced MCU power

ADPU

consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time

period after ADPU bit is enabled.

0 Power down ATD

1 Normal ATD functionality

ATD Fast Flag Clear All

AFFC

0 ATD ﬂag clearing operates normally (read the status register ATDSTAT1 before reading the result register

to clear the associate CCF ﬂag).

1 Changes all ATD conversion complete ﬂags to a fast clear sequence. Any access to a result register will

cause the associate CCF ﬂag to clear automatically.

ATD Power Down in Wait Mode — When entering Wait Mode this bit provides on/off control over the

ATD10B16C block allowing reduced MCU power. Because analog electronic is turned off when powered down,

the ATD requires a recovery time period after exit from Wait mode.

AWAI

0 ATD continues to run in Wait mode

1 Halt conversion and power down ATD during Wait mode

After exiting Wait mode with an interrupt conversion will resume. But due to the recovery time the result of

this conversion should be ignored.

External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See

ETRIGLE

Table 7-7 for details.

External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 7-7 for

ETRIGP

details.

External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of

ETRIGE

the ETRIG[3:0] inputs as described in Table 7-5. If external trigger source is one of the AD channels, the digital

input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with

external events.

0 Disable external trigger

1 Enable external trigger

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

Table 7-6. ATDCTL2 Field Descriptions (continued)

Field

Description

ATD Sequence Complete Interrupt Enable

ASCIE

0 ATD Sequence Complete interrupt requests are disabled.

1 A T D Interrupt will be requested whenever ASCIF = 1 is set.

ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF ﬂag equals the SCF ﬂag (see

Section 7.3.2.7, “ATD Status Register 0 (ATDSTAT0)”), else ASCIF reads zero. Writes have no effect.

0 No ATD interrupt occurred

ASCIF

1 ATD sequence complete interrupt pending

Table 7-7. External Trigger Conﬁgurations

ETRIGLE

ETRIGP

External Trigger Sensitivity

Falling Edge

Ring Edge

Low Level

High Level

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

7.3.2.4

ATD Control Register 3 (ATDCTL3)

This register controls the conversion sequence length, FIFO for results registers and behavior in Freeze

Mode. Writes to this register will abort current conversion sequence but will not start a new sequence.

Module Base + 0x0003

S8C

S4C

S2C

S1C

FIFO

FRZ1

FRZ0

Reset

= Unimplemented or Reserved

Figure 7-6. ATD Control Register 3 (ATDCTL3)

Read: Anytime

Write: Anytime

Table 7-8. ATDCTL3 Field Descriptions

Description

Field

S8C

Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 7-9 shows

all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12

Family.

S4C

Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 7-9 shows

all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12

Family.

S2C

Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 7-9 shows

all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12

Family.

S1C

Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 7-9 shows

all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12

Family.

Result Register FIFO Mode —If this bit is zero (non-FIFO mode), the A/D conversion results map into the

result registers based on the conversion sequence; the result of the ﬁrst conversion appears in the ﬁrst result

FIFO

If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or ending of a conversion

sequence; conversion results are placed in consecutive result registers between sequences. The result

in ATDSTAT0 can be used to determine where in the result register ﬁle, the current conversion result will be

placed.

Finally, which result registers hold valid data can be tracked using the conversion complete ﬂags. Fast ﬂag clear

mode may or may not be useful in a particular application to track valid data.

0 Conversion results are placed in the corresponding result register up to the selected sequence length.

1 Conversion results are placed in consecutive result registers (wrap around at end).

1:0

FRZ[1:0]

Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the

ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond

to a breakpoint as shown in Table 7-10. Leakage onto the storage node and comparator reference capacitors

may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze

period.

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

Table 7-9. Conversion Sequence Length Coding

Number of Conversions

per Sequence

S8C

S4C

S2C

S1C

Table 7-10. ATD Behavior in Freeze Mode (Breakpoint)

FRZ1

FRZ0

Behavior in Freeze Mode

Continue conversion

Reserved

Finish current conversion, then freeze

Freeze Immediately

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

7.3.2.5

ATD Control Register 4 (ATDCTL4)

This register selects the conversion clock frequency, the length of the second phase of the sample time and

the resolution of the A/D conversion (i.e., 8-bits or 10-bits). Writes to this register will abort current

conversion sequence but will not start a new sequence.

Module Base + 0x0004

SRES8

SMP1

SMP0

PRS4

PRS3

PRS2

PRS1

PRS0

Reset

Figure 7-7. ATD Control Register 4 (ATDCTL4)

Read: Anytime

Write: Anytime

Table 7-11. ATDCTL4 Field Descriptions

Description

Field

A/D Resolution Select — This bit selects the resolution of A/D conversion results as either 8 or 10 bits. The

SRES8

A/D converter has an accuracy of 10 bits. However, if low resolution is required, the conversion can be speeded

up by selecting 8-bit resolution.

0 10 bit resolution

1 8 bit resolution

6:5

SMP[1:0]

Sample Time Select —These two bits select the length of the second phase of the sample time in units of ATD

conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler value

(bits PRS4-0). The sample time consists of two phases. The ﬁrst phase is two ATD conversion clock cycles

long and transfers the sample quickly (via the buffer ampliﬁer) onto the A/D machine’s storage node. The

second phase attaches the external analog signal directly to the storage node for ﬁnal charging and high

accuracy. Table 7-12 lists the lengths available for the second sample phase.

4:0

ATD Clock Prescaler — These 5 bits are the binary value prescaler value PRS. The ATD conversion clock

PRS[4:0]

frequency is calculated as follows:

[BusClock]

ATDclock =

× 0.5

--------------------------------

[PRS + 1]

Note: The maximum ATD conversion clock frequency is half the bus clock. The default (after reset) prescaler

value is 5 which results in a default ATD conversion clock frequency that is bus clock divided by 12.

Table 7-13 illustrates the divide-by operation and the appropriate range of the bus clock.

Table 7-12. Sample Time Select

SMP1

SMP0

Length of 2nd Phase of Sample Time

2 A/D conversion clock periods

4 A/D conversion clock periods

8 A/D conversion clock periods

16 A/D conversion clock periods

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

Table 7-13. Clock Prescaler Values

Total Divisor

Value

Prescale Value

Max. Bus Clock

Min. Bus Clock

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Divide by 2

Divide by 4

4 MHz

8 MHz

1 MHz

2 MHz

Divide by 6

12 MHz

16 MHz

20 MHz

24 MHz

28 MHz

32 MHz

36 MHz

40 MHz

44 MHz

48 MHz

52 MHz

56 MHz

60 MHz

64 MHz

68 MHz

72 MHz

76 MHz

80 MHz

84 MHz

88 MHz

92 MHz

96 MHz

100 MHz

104 MHz

108 MHz

112 MHz

116 MHz

120 MHz

124 MHz

128 MHz

3 MHz

Divide by 8

4 MHz

Divide by 10

Divide by 12

Divide by 14

Divide by 16

Divide by 18

Divide by 20

Divide by 22

Divide by 24

Divide by 26

Divide by 28

Divide by 30

Divide by 32

Divide by 34

Divide by 36

Divide by 38

Divide by 40

Divide by 42

Divide by 44

Divide by 46

Divide by 48

Divide by 50

Divide by 52

Divide by 54

Divide by 56

Divide by 58

Divide by 60

Divide by 62

Divide by 64

5 MHz

6 MHz

7 MHz

8 MHz

9 MHz

10 MHz

11 MHz

12 MHz

13 MHz

14 MHz

15 MHz

16 MHz

17 MHz

18 MHz

19 MHz

20 MHz

21 MHz

22 MHz

23 MHz

24 MHz

25 MHz

26 MHz

27 MHz

28 MHz

29 MHz

30 MHz

31 MHz

32 MHz

Maximum ATD conversion clock frequency is 2 MHz. The maximum allowed bus clock frequency is

shown in this column.

Minimum ATD conversion clock frequency is 500 kHz. The minimum allowed bus clock frequency is

shown in this column.

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

7.3.2.6

ATD Control Register 5 (ATDCTL5)

This register selects the type of conversion sequence and the analog input channels sampled. Writes to this

enabled (ETRIGE = 1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence

which will then occur on each trigger event. Start of conversion means the beginning of the sampling

phase.

Module Base + 0x0005

DJM

DSGN

SCAN

MULT

Reset

Figure 7-8. ATD Control Register 5 (ATDCTL5)

Read: Anytime

Write: Anytime

Table 7-14. ATDCTL5 Field Descriptions

Description

Field

DJM

Result Register Data Justiﬁcation — This bit controls justiﬁcation of conversion data in the result registers.

See Section 7.3.2.16, “ATD Conversion Result Registers (ATDDRx)” for details.

0 Left justiﬁed data in the result registers.

1 Right justiﬁed data in the result registers.

Result Register Data Signed or Unsigned Representation — This bit selects between signed and unsigned

conversion data representation in the result registers. Signed data is represented as 2’s complement. Signed

data is not available in right justiﬁcation. See <st-bold>7.3.2.16 ATD Conversion Result Registers (ATDDRx)

for details.

DSGN

0 Unsigned data representation in the result registers.

1 Signed data representation in the result registers.

Table 7-15 summarizes the result data formats available and how they are set up using the control bits.

Table 7-16 illustrates the difference between the signed and unsigned, left justiﬁed output codes for an input

signal range between 0 and 5.12 Volts.

Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed

continuously or only once. If external trigger is enabled (ETRIGE=1) setting this bit has no effect, that means

each trigger event starts a single conversion sequence.

SCAN

0 Single conversion sequence

1 Continuous conversion sequences (scan mode)

Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the

speciﬁed analog input channel for an entire conversion sequence. The analog channel is selected by channel

selection code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller

samples across channels. The number of channels sampled is determined by the sequence length value (S8C,

S4C, S2C, S1C). The ﬁrst analog channel examined is determined by channel selection code (CC, CB, CA

control bits); subsequent channels sampled in the sequence are determined by incrementing the channel

selection code or wrapping around to AN0 (channel 0.

MULT

0 Sample only one channel

1 Sample across several channels

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

Table 7-14. ATDCTL5 Field Descriptions (continued)

Field

Description

3:0

C[D:A}

Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are

sampled and converted to digital codes. Table 7-17 lists the coding used to select the various analog input

channels.

In the case of single channel conversions (MULT = 0), this selection code speciﬁed the channel to be examined.

In the case of multiple channel conversions (MULT = 1), this selection code represents the ﬁrst channel to be

examined in the conversion sequence. Subsequent channels are determined by incrementing the channel

selection code or wrapping around to AN0 (after converting the channel deﬁned by the Wrap Around Channel

Select Bits WRAP[3:0] in ATDCTL0). In case starting with a channel number higher than the one deﬁned by

WRAP[3:0] the ﬁrst wrap around will be AN15 to AN0.

Table 7-15. Available Result Data Formats.

Result Data Formats

Description and Bus Bit Mapping

SRES8

DJM

DSGN

8-bit / left justiﬁed / unsigned — bits 15:8

8-bit / left justiﬁed / signed — bits 15:8

8-bit / right justiﬁed / unsigned — bits 7:0

10-bit / left justiﬁed / unsigned — bits 15:6

10-bit / left justiﬁed / signed -— bits 15:6

10-bit / right justiﬁed / unsigned — bits 9:0

Table 7-16. Left Justiﬁed, Signed and Unsigned ATD Output Codes.

Input Signal

Signed

8-Bit Codes

Unsigned

8-Bit Codes

Signed

10-Bit Codes

Unsigned

10-Bit Codes

= 0 Volts

= 5.12 Volts

5.120 Volts

5.100

7FC0

7F00

7E00

FFC0

FF00

FE00

5.080

2.580

2.560

2.540

0100

0000

FF00

8100

8000

7F00

0.020

0.000

8100

8000

0100

0000

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

Table 7-17. Analog Input Channel Select Coding

Analog Input

Channel

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

AN12

AN13

AN14

AN15

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

7.3.2.7

ATD Status Register 0 (ATDSTAT0)

This read-only register contains the Sequence Complete Flag, overrun ﬂags for external trigger and FIFO

mode, and the conversion counter.

Module Base + 0x0006

CC3

CC2

CC1

CC0

SCF

ETORF

FIFOR

Reset

= Unimplemented or Reserved

Figure 7-9. ATD Status Register 0 (ATDSTAT0)

Read: Anytime

Write: Anytime (No effect on CC[3:0])

Table 7-18. ATDSTAT0 Field Descriptions

Field

Description

SCF

Sequence Complete Flag — This ﬂag is set upon completion of a conversion sequence. If conversion

sequences are continuously performed (SCAN = 1), the ﬂag is set after each one is completed. This ﬂag is

cleared when one of the following occurs:

• Write “1” to SCF

• Write to ATDCTL5 (a new conversion sequence is started)

• If AFFC = 1 and read of a result register

0 Conversion sequence not completed

1 Conversion sequence has completed

External Trigger Overrun Flag —While in edge trigger mode (ETRIGLE = 0), if additional active edges are

detected while a conversion sequence is in process the overrun ﬂag is set. This ﬂag is cleared when one of the

following occurs:

ETORF

• Write “1” to ETORF

• Write to ATDCTL0,1,2,3,4 (a conversion sequence is aborted)

• Write to ATDCTL5 (a new conversion sequence is started)

0 No External trigger over run error has occurred

1 External trigger over run error has occurred

FIFO Over Run Flag — This bit indicates that a result register has been written to before its associated

conversion complete ﬂag (CCF) has been cleared. This ﬂag is most useful when using the FIFO mode because

the ﬂag potentially indicates that result registers are out of sync with the input channels. However, it is also

practical for non-FIFO modes, and indicates that a result register has been over written before it has been read

(i.e., the old data has been lost). This ﬂag is cleared when one of the following occurs:

• Write “1” to FIFOR

FIFOR

• Start a new conversion sequence (write to ATDCTL5 or external trigger)

0 No over run has occurred

1 Overrun condition exists (result register has been written while associated CCFx ﬂag remained set)

3:0

CC[3:0}

Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion

counter points to the result register that will receive the result of the current conversion. For example, CC3 = 0,

CC2 = 1, CC1 = 1, CC0 = 0 indicates that the result of the current conversion will be in ATD Result Register 6.

If in non-FIFO mode (FIFO = 0) the conversion counter is initialized to zero at the begin and end of the

conversion sequence. If in FIFO mode (FIFO = 1) the register counter is not initialized. The conversion

counters wraps around when its maximum value is reached.

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

7.3.2.8

Reserved Register 0 (ATDTEST0)

Module Base + 0x0008

Reset

= Unimplemented or Reserved

u = Unaffected

Figure 7-10. Reserved Register 0 (ATDTEST0)

Read: Anytime, returns unpredictable values

Write: Anytime in special modes, unimplemented in normal modes

NOTE

Writing to this register when in special modes can alter functionality.

7.3.2.9

ATD Test Register 1 (ATDTEST1)

This register contains the SC bit used to enable special channel conversions.

Module Base + 0x0009

Reset

= Unimplemented or Reserved

u = Unaffected

Figure 7-11. Reserved Register 1 (ATDTEST1)

Read: Anytime, returns unpredictable values for bit 7 and bit 6

Write: Anytime

NOTE

Writing to this register when in special modes can alter functionality.

Table 7-19. ATDTEST1 Field Descriptions

Description

Field

Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using

CC, CB, and CA of ATDCTL5. Table 7-20 lists the coding.

0 Special channel conversions disabled

1 Special channel conversions enabled

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

Table 7-20. Special Channel Select Coding

Analog Input Channel

Reserved

(V +V ) / 2

Reserved

7.3.2.10 ATD Status Register 2 (ATDSTAT2)

This read-only register contains the Conversion Complete Flags CCF15 to CCF8.

Module Base + 0x000A

CCF15

CCF14

CCF13

CCF12

CCF11

CCF10

CCF9

CCF8

Reset

= Unimplemented or Reserved

Figure 7-12. ATD Status Register 2 (ATDSTAT2)

Read: Anytime

Write: Anytime, no effect

Table 7-21. ATDSTAT2 Field Descriptions

Description

Field

7:0

CCF[15:8]

Conversion Complete Flag Bits — A conversion complete ﬂag is set at the end of each conversion in a

conversion sequence. The ﬂags are associated with the conversion position in a sequence (and also the result

is available in result register ATDDR8; CCF9 is set when the tenth conversion in a sequence is complete and

the result is available in ATDDR9, and so forth. A ﬂag CCFx (x = 15, 14, 13, 12, 11, 10, 9, 8) is cleared when

one of the following occurs:

• Write to ATDCTL5 (a new conversion sequence is started)

• If AFFC = 0 and read of ATDSTAT2 followed by read of result register ATDDRx

• If AFFC = 1 and read of result register ATDDRx

In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing

by methods B) or C) will be overwritten by the set.

0 Conversion number x not completed

1 Conversion number x has completed, result ready in ATDDRx

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

7.3.2.11 ATD Status Register 1 (ATDSTAT1)

This read-only register contains the Conversion Complete Flags CCF7 to CCF0

Module Base + 0x000B

CCF7

CCF6

CCF5

CCF4

CCF3

CCF2

CCF1

CCF0

Reset

= Unimplemented or Reserved

Figure 7-13. ATD Status Register 1 (ATDSTAT1)

Read: Anytime

Write: Anytime, no effect

Table 7-22. ATDSTAT1 Field Descriptions

Description

Field

7:0

CCF[7:0]

Conversion Complete Flag Bits — A conversion complete ﬂag is set at the end of each conversion in a

conversion sequence. The ﬂags are associated with the conversion position in a sequence (and also the result

available in result register ATDDR0; CCF1 is set when the second conversion in a sequence is complete and

the result is available in ATDDR1, and so forth. A CCF ﬂag is cleared when one of the following occurs:

• Write to ATDCTL5 (a new conversion sequence is started)

• If AFFC = 0 and read of ATDSTAT1 followed by read of result register ATDDRx

• If AFFC = 1 and read of result register ATDDRx

In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing

by methods B) or C) will be overwritten by the set.

Conversion number x not completed

Conversion number x has completed, result ready in ATDDRx

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

7.3.2.12 ATD Input Enable Register 0 (ATDDIEN0)

Module Base + 0x000C

IEN15

IEN14

IEN13

IEN12

IEN11

IEN10

IEN9

IEN8

Reset

Figure 7-14. ATD Input Enable Register 0 (ATDDIEN0)

Read: Anytime

Write: anytime

Table 7-23. ATDDIEN0 Field Descriptions

Description

Field

7:0

IEN[15:8]

ATD Digital Input Enable on Channel Bits — This bit controls the digital input buffer from the analog input

pin (ANx) to PTADx data register.

0 Disable digital input buffer to PTADx

1 Enable digital input buffer to PTADx.

Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while

simultaneously using it as an analog port, there is potentially increased power consumption because the

digital input buffer maybe in the linear region.

7.3.2.13 ATD Input Enable Register 1 (ATDDIEN1)

Module Base + 0x000D

IEN7

IEN6

IEN5

IEN4

IEN3

IEN2

IEN1

IEN0

Reset

Figure 7-15. ATD Input Enable Register 1 (ATDDIEN1)

Read: Anytime

Write: Anytime

Table 7-24. ATDDIEN1 Field Descriptions

Description

Field

7:0

IEN[7:0]

ATD Digital Input Enable on Channel Bits — This bit controls the digital input buffer from the analog input

pin (ANx) to PTADx data register.

0 Disable digital input buffer to PTADx

1 Enable digital input buffer to PTADx.

Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while

simultaneously using it as an analog port, there is potentially increased power consumption because the

digital input buffer maybe in the linear region.

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

7.3.2.14 Port Data Register 0 (PORTAD0)

The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs

AN[15:8].

Module Base + 0x000E

PTAD15

PTAD14

PTAD13

PTAD12

PTAD11

PTAD10

PTAD9

PTAD8

Reset

Function

AN15

AN14

AN13

AN12

AN11

AN10

AN9

AN8

= Unimplemented or Reserved

Figure 7-16. Port Data Register 0 (PORTAD0)

Read: Anytime

Write: Anytime, no effect

The A/D input channels may be used for general-purpose digital input.

Table 7-25. PORTAD0 Field Descriptions

Field

Description

A/D Channel x (ANx) Digital Input Bits— If the digital input buffer on the ANx pin is enabled (IENx = 1) or

7:0

PTAD[15:8] channel x is enabled as external trigger (ETRIGE = 1, ETRIGCH[3-0] = x, ETRIGSEL = 0) read returns the

logic level on ANx pin (signal potentials not meeting V or V speciﬁcations will have an indeterminate value)).

If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns

a “1”.

Reset sets all PORTAD0 bits to “1”.

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

7.3.2.15 Port Data Register 1 (PORTAD1)

The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs

AN7-0.

Module Base + 0x000F

PTAD7

PTAD6

PTAD5

PTAD4

PTAD3

PTAD2

PTAD1

PTAD0

Reset

Function

AN 7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

= Unimplemented or Reserved

Figure 7-17. Port Data Register 1 (PORTAD1)

Read: Anytime

Write: Anytime, no effect

The A/D input channels may be used for general-purpose digital input.

Table 7-26. PORTAD1 Field Descriptions

Field

Description

7:0

A/D Channel x (ANx) Digital Input Bits — If the digital input buffer on the ANx pin is enabled (IENx=1) or

PTAD[7:8]

channel x is enabled as external trigger (ETRIGE = 1, ETRIGCH[3-0] = x, ETRIGSEL = 0) read returns the

logic level on ANx pin (signal potentials not meeting V or V speciﬁcations will have an indeterminate value)).

If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns

a “1”.

Reset sets all PORTAD1 bits to “1”.

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

7.3.2.16 ATD Conversion Result Registers (ATDDRx)

The A/D conversion results are stored in 16 read-only result registers. The result data is formatted in the

result registers bases on two criteria. First there is left and right justiﬁcation; this selection is made using

the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using

the DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement format and only exists in left

justiﬁed format. Signed data selected for right justiﬁed format is ignored.

Read: Anytime

Write: Anytime in special mode, unimplemented in normal modes

7.3.2.16.1

Left Justiﬁed Result Data

Module Base + 0x0010 = ATDDR0H

0x0012 = ATDDR1H

0x0018 = ATDDR4H

0x001A = ATDDR5H

0x001C = ATDDR6H

0x001E = ATDDR7H

0x0020 = ATDDR8H

0x0022 = ATDDR9H

0x0024 = ATDDR10H

0x0026 = ATDDR11H

0x0028 = ATDDR12H

0x002A = ATDDR13H

0x002C = ATDDR14H

0x002E = ATDDR15H

0x0014 = ATDDR2H

0x0016 = ATDDR3H

R (10-BIT) BIT 9 MSB

R (8-BIT) BIT 7 MSB

BIT 8

BIT 6

BIT 7

BIT 5

BIT 6

BIT 4

BIT 5

BIT 3

BIT 4

BIT 2

BIT 3

BIT 1

BIT 2

BIT 0

Reset

= Unimplemented or Reserved

Figure 7-18. Left Justiﬁed, ATD Conversion Result Register x, High Byte (ATDDRxH)

Module Base + 0x0011 = ATDDR0L

0x0013 = ATDDR1L

0x0019 = ATDDR4L

0x001B = ATDDR5L

0x001D = ATDDR6L

0x001F = ATDDR7L

0x0021 = ATDDR8L

0x0023 = ATDDR9L

0x0025 = ATDDR10L

0x0027 = ATDDR11L

0x0029 = ATDDR12L

0x002B = ATDDR13L

0x002D = ATDDR14L

0x002F = ATDDR15L

0x0015 = ATDDR2L

0x0017 = ATDDR3L

R (10-BIT)

R (8-BIT)

BIT 1

BIT 0

Reset

= Unimplemented or Reserved

u = Unaffected

Figure 7-19. Left Justiﬁed, ATD Conversion Result Register x, Low Byte (ATDDRxL)

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

7.3.2.16.2

Right Justiﬁed Result Data

Module Base + 0x0010 = ATDDR0H,

0x0012 = ATDDR1H,

0x0018 = ATDDR4H,

0x001A = ATDDR5H,

0x001C = ATDDR6H,

0x001E = ATDDR7H

0x0020 = ATDDR8H,

0x0022 = ATDDR9H,

0x0024 = ATDDR10H,

0x0026 = ATDDR11H

0x0028 = ATDDR12H,

0x002A = ATDDR13H,

0x002C = ATDDR14H,

0x002E = ATDDR15H

0x0014 = ATDDR2H,

0x0016 = ATDDR3H

R (10-BIT)

R (8-BIT)

BIT 9 MSB

BIT 8

Reset

= Unimplemented or Reserved

Figure 7-20. Right Justiﬁed, ATD Conversion Result Register x, High Byte (ATDDRxH)

Module Base + 0x0011 = ATDDR0L,

0x0013 = ATDDR1L,

0x0019 = ATDDR4L,

0x001B = ATDDR5L,

0x001D = ATDDR6L,

0x001F = ATDDR7L

0x0021 = ATDDR8L,

0x0023 = ATDDR9L,

0x0025 = ATDDR10L,

0x0027 = ATDDR11L

0x0029 = ATDDR12L,

0x002B = ATDDR13L,

0x002D = ATDDR14L,

0x002F = ATDDR15L

0x0015 = ATDDR2L,

0x0017 = ATDDR3L

R (10-BIT)

R (8-BIT) BIT 7 MSB

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Reset

= Unimplemented or Reserved

Figure 7-21. Right Justiﬁed, ATD Conversion Result Register x, Low Byte (ATDDRxL)

7.4

Functional Description

The ATD10B16C is structured in an analog and a digital sub-block.

7.4.1

Analog Sub-block

The analog sub-block contains all analog electronics required to perform a single conversion. Separate

power supplies V and V allow to isolate noise of other MCU circuitry from the analog sub-block.

DDA

SSA

7.4.1.1

Sample and Hold Machine

The sample and hold (S/H) machine accepts analog signals from the external world and stores them as

capacitor charge on a storage node.

The sample process uses a two stage approach. During the ﬁrst stage, the sample ampliﬁer is used to

quickly charge the storage node.The second stage connects the input directly to the storage node to

complete the sample for high accuracy.

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

When not sampling, the sample and hold machine disables its own clocks. The analog electronics continue

drawing their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks

and the analog power consumption.

The input analog signals are unipolar and must fall within the potential range of V

to VDDA.

SSA

7.4.1.2

Analog Input Multiplexer

The analog input multiplexer connects one of the 16 external analog input channels to the sample and hold

machine.

7.4.1.3

Sample Buffer Ampliﬁer

The sample ampliﬁer is used to buffer the input analog signal so that the storage node can be quickly

charged to the sample potential.

7.4.1.4

Analog-to-Digital (A/D) Machine

The A/D machine performs analog to digital conversions. The resolution is program selectable at either 8

or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the

stored analog sample potential with a series of digitally generated analog potentials. By following a binary

search algorithm, the A/D machine locates the approximating potential that is nearest to the sampled

potential.

When not converting the A/D machine disables its own clocks. The analog electronics continue drawing

quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog

power consumption.

Only analog input signals within the potential range of V to V (A/D reference potentials) will result

in a non-railed digital output codes.

7.4.2

Digital Sub-Block

This subsection explains some of the digital features in more detail. See register descriptions for all details.

7.4.2.1

External Trigger Input

The external trigger feature allows the user to synchronize ATD conversions to the external environment

events rather than relying on software to signal the ATD module when ATD conversions are to take place.

The external trigger signal (out of reset ATD channel 15, conﬁgurable in ATDCTL1) is programmable to

be edge or level sensitive with polarity control. Table 7-27 gives a brief description of the different

combinations of control bits and their effect on the external trigger function.

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

Table 7-27. External Trigger Control Bits

ETRIGLE ETRIGP ETRIGE SCAN

Description

Ignores external trigger. Performs one conversion sequence and stops.

Ignores external trigger. Performs continuous conversion sequences.

Falling edge triggered. Performs one conversion sequence per trigger.

Rising edge triggered. Performs one conversion sequence per trigger.

Trigger active low. Performs continuous conversions while trigger is active.

Trigger active high. Performs continuous conversions while trigger is active.

During a conversion, if additional active edges are detected the overrun error ﬂag ETORF is set.

In either level or edge triggered modes, the ﬁrst conversion begins when the trigger is received. In both

cases, the maximum latency time is one bus clock cycle plus any skew or delay introduced by the trigger

circuitry.

After ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be

triggered externally.

If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion

sequence, this does not constitute an overrun. Therefore, the ﬂag is not set. If the trigger remains asserted

in level mode while a sequence is completing, another sequence will be triggered immediately.

7.4.2.2

General-Purpose Digital Input Port Operation

The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are

multiplexed and sampled to supply signals to the A/D converter. As digital inputs, they supply external

input data that can be accessed through the digital port registers (PORTAD0 & PORTAD1) (input-only).

The analog/digital multiplex operation is performed in the input pads. The input pad is always connected

to the analog inputs of the ATD10B16C. The input pad signal is buffered to the digital port registers. This

buffer can be turned on or off with the ATDDIEN0 & ATDDIEN1 register. This is important so that the

buffer does not draw excess current when analog potentials are presented at its input.

7.4.3

Operation in Low Power Modes

The ATD10B16C can be conﬁgured for lower MCU power consumption in three different ways:

•

Stop Mode

Stop Mode: This halts A/D conversion. Exit from Stop mode will resume A/D conversion, But due

to the recovery time the result of this conversion should be ignored.

Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power

standby mode. This halts any conversion sequence in progress. During recovery from stop mode,

there must be a minimum delay for the stop recovery time t before initiating a new ATD

conversion sequence.

•

Wait Mode

Wait Mode with AWAI = 1: This halts A/D conversion. Exit from Wait mode will resume A/D

conversion, but due to the recovery time the result of this conversion should be ignored.

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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)

Entering wait mode, the ATD conversion either continues or halts for low power depending on the

logical value of the AWAIT bit.

•

Freeze Mode

Writing ADPU = 0 (Note that all ATD registers remain accessible.): This aborts any A/D

conversion in progress.

In freeze mode, the ATD10B16C will behave according to the logical values of the FRZ1 and FRZ0

bits. This is useful for debugging and emulation.

NOTE

The reset value for the ADPU bit is zero. Therefore, when this module is

reset, it is reset into the power down state.

7.5

Resets

At reset the ATD10B16C is in a power down state. The reset state of each individual bit is listed within

Section 7.3, “Memory Map and Register Deﬁnition,” which details the registers and their bit ﬁelds.

7.6

Interrupts

The interrupt requested by the ATD10B16C is listed in Table 7-28. Refer to MCU speciﬁcation for related

vector address and priority.

Table 7-28. ATD Interrupt Vectors

Interrupt Source

CCR Mask

Local Enable

Sequence Complete Interrupt

I bit

ASCIE in ATDCTL2

See Section 7.3.2, “Register Descriptions,” for further details.

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Chapter 8

Analog-to-Digital Converter (ATD10B8CV3)

8.1

Introduction

The ATD10B8C is an 8-channel, 10-bit, multiplexed input successive approximation analog-to-digital

converter. Refer to device electrical speciﬁcations for ATD accuracy.

8.1.1

Features

•

8/10-bit resolution

7 µsec, 10-bit single conversion time

Sample buffer ampliﬁer

Programmable sample time

Left/right justiﬁed, signed/unsigned result data

External trigger control

Conversion completion interrupt generation

Analog input multiplexer for 8 analog input channels

Analog/digital input pin multiplexing

1-to-8 conversion sequence lengths

Continuous conversion mode

Multiple channel scans

Conﬁgurable external trigger functionality on any AD channel or any of four additional external

trigger inputs. The four additional trigger inputs can be chip external or internal. Refer to the device

overview chapter for availability and connectivity.

•

Conﬁgurable location for channel wrap around (when converting multiple channels in a sequence).

8.1.2

Modes of Operation

8.1.2.1

Conversion Modes

There is software programmable selection between performing single or continuous conversion on a single

channel or multiple channels.

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

8.1.2.2

MCU Operating Modes

•

Stop mode

Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power

standby mode. This aborts any conversion sequence in progress. During recovery from stop mode,

there must be a minimum delay for the stop recovery time t before initiating a new ATD

conversion sequence.

•

Wait mode

Entering wait mode the ATD conversion either continues or aborts for low power depending on the

logical value of the AWAIT bit.

Freeze mode

In freeze mode the ATD will behave according to the logical values of the FRZ1 and FRZ0 bits.

This is useful for debugging and emulation.

8.1.3

Block Diagram

Figure 8-1 shows a block diagram of the ATD.

8.2

External Signal Description

This section lists all inputs to the ATD block.

8.2.1

ANx (x = 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input Pin

This pin serves as the analog input channel x. It can also be conﬁgured as general purpose digital port pin

and/or external trigger for the ATD conversion.

8.2.2

ETRIG3, ETRIG2, ETRIG1, and ETRIG0 — External Trigger Pins

These inputs can be conﬁgured to serve as an external trigger for the ATD conversion.

Refer to the device overview chapter for availability and connectivity of these inputs.

8.2.3

and V — High and Low Reference Voltage Pins

is the high reference voltage and V is the low reference voltage for ATD conversion.

8.2.4

and V

— Power Supply Pins

DDA

SSA

These pins are the power supplies for the analog circuitry of the ATD block.

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

Bus Clock

ATD clock

Clock

Prescaler

ATD10B8C

Trigger

Mux

ETRIG0

Sequence Complete

Mode and

Timing Control

ETRIG1

ETRIG2

ETRIG3

Interrupt

(See Device Overview

chapter for availability

and connectivity)

ATDDIEN

ATDCTL1

PORTAD

Results

ATD 0

DDA

SSA

ATD 1

ATD 2

ATD 3

ATD 4

ATD 5

ATD 6

ATD 7

Successive

Approximation

and DAC

AN7

AN6

AN5

AN4

AN3

–

Sample & Hold

Comparator

Analog

MUX

AN2

AN1

AN0

Figure 8-1. ATD Block Diagram

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

8.3

Memory Map and Register Deﬁnition

This section provides a detailed description of all registers accessible in the ATD.

8.3.1

Module Memory Map

Figure 8-2 gives an overview of all ATD registers.

NOTE

is deﬁned at the MCU level and the Address Offset is deﬁned at the module

level.

8.3.2

This section describes in address order all the ATD registers and their individual bits.

Name

Bit 7

Bit 0

0x0000

ATDCTL0

WRAP2

WRAP1

WRAP0

0x0001

ATDCTL1

ETRIGSEL

ETRIGCH2 ETRIGCH1 ETRIGCH0

ASCIF

0x0002

ATDCTL2

ADPU

AFFC

S8C

AWAI

S4C

ETRIGLE

S2C

ETRIGP

S1C

ETRIGE

ASCIE

FRZ1

PRS1

0x0003

ATDCTL3

FIFO

FRZ0

PRS0

0x0004

ATDCTL4

SRES8

DJM

SMP1

SMP0

SCAN

ETORF

PRS4

PRS3

PRS2

0x0005

ATDCTL5

DSGN

MULT

0x0006

ATDSTAT0

CC2

CC1

CC0

SCF

FIFOR

0x0007

Unimplemente

0x0008

ATDTEST0

0x0009

ATDTEST1

= Unimplemented or Reserved

Figure 8-2. ATD Register Summary (Sheet 1 of 5)

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

Name

Bit 7

Bit 0

0x000A

Unimplemente

0x000B

CCF7

CCF6

CCF5

CCF4

CCF3

CCF2

CCF1

CCF0

ATDSTAT1

0x000C

Unimplemente

0x000D

ATDDIEN

IEN7

IEN6

IEN5

IEN4

IEN3

IEN2

IEN1

IEN0

0x000E

Unimplemente

0x000F

PTAD7

PTAD6

PTAD5

PTAD4

PTAD3

PTAD2

PTAD1

PTAD0

PORTAD

Left Justiﬁed Result Data

Note: The read portion of the left justiﬁed result data registers has been divided to show the bit position when reading 10-bit and

8-bit conversion data. For more detailed information refer to Section 8.3.2.13, “ATD Conversion Result Registers

(ATDDRx)”.

0x0010

ATDDR0H

10-BIT

8-BIT

BIT 9 MSB

BIT 7 MSB

BIT 8

BIT 6

BIT 7

BIT 5

BIT 6

BIT 4

BIT 5

BIT 3

BIT 4

BIT 2

BIT 3

BIT 1

BIT 2

BIT 0

0x0011

ATDDR0L

10-BIT

8-BIT

BIT 1

BIT 0

0x0012

ATDDR1H

10-BIT

8-BIT

BIT 9 MSB

BIT 7 MSB

BIT 8

BIT 6

BIT 7

BIT 5

BIT 6

BIT 4

BIT 5

BIT 3

BIT 4

BIT 2

BIT 3

BIT 1

BIT 2

BIT 0

0x0013

ATDDR1L

10-BIT

8-BIT

BIT 1

BIT 0

0x0014

ATDDR2H

10-BIT

8-BIT

BIT 9 MSB

BIT 7 MSB

BIT 8

BIT 6

BIT 7

BIT 5

BIT 6

BIT 4

BIT 5

BIT 3

BIT 4

BIT 2

BIT 3

BIT 1

BIT 2

BIT 0

0x0015

ATDDR2L

10-BIT

8-BIT

BIT 1

BIT 0

= Unimplemented or Reserved

Figure 8-2. ATD Register Summary (Sheet 2 of 5)

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

Bit 7

Bit 0

Name

0x0016

ATDDR3H

10-BIT

8-BIT

BIT 9 MSB

BIT 7 MSB

BIT 8

BIT 6

BIT 7

BIT 5

BIT 6

BIT 4

BIT 5

BIT 3

BIT 4

BIT 2

BIT 3

BIT 1

BIT 2

BIT 0

0x0017

ATDDR3L

10-BIT

8-BIT

BIT 1

BIT 0

0x0018

ATDDR4H

10-BIT

8-BIT

BIT 9 MSB

BIT 7 MSB

BIT 8

BIT 6

BIT 7

BIT 5

BIT 6

BIT 4

BIT 5

BIT 3

BIT 4

BIT 2

BIT 3

BIT 1

BIT 2

BIT 0

0x0019

ATDDR4L

10-BIT

8-BIT

BIT 1

BIT 0

0x001A

ATDD45H

10-BIT

8-BIT

BIT 9 MSB

BIT 7 MSB

BIT 8

BIT 6

BIT 7

BIT 5

BIT 6

BIT 4

BIT 5

BIT 3

BIT 4

BIT 2

BIT 3

BIT 1

BIT 2

BIT 0

0x001B

ATDD45L

10-BIT

8-BIT

BIT 1

BIT 0

0x001C

ATDD46H

10-BIT

8-BIT

BIT 9 MSB

BIT 7 MSB

BIT 8

BIT 6

BIT 7

BIT 5

BIT 6

BIT 4

BIT 5

BIT 3

BIT 4

BIT 2

BIT 3

BIT 1

BIT 2

BIT 0

0x001D

ATDDR6L

10-BIT

8-BIT

BIT 1

BIT 0

0x001E

ATDD47H

10-BIT

8-BIT

BIT 9 MSB

BIT 7 MSB

BIT 8

BIT 6

BIT 7

BIT 5

BIT 6

BIT 4

BIT 5

BIT 3

BIT 4

BIT 2

BIT 3

BIT 1

BIT 2

BIT 0

0x001F

ATDD47L

10-BIT

8-BIT

BIT 1

BIT 0

Right Justiﬁed Result Data

Note: The read portion of the right justiﬁed result data registers has been divided to show the bit position when reading 10-bit

and 8-bit conversion data. For more detailed information refer to Section 8.3.2.13, “ATD Conversion Result Registers

(ATDDRx)”.

0x0010

ATDDR0H

10-BIT

8-BIT

BIT 9 MSB

BIT 8

= Unimplemented or Reserved

Figure 8-2. ATD Register Summary (Sheet 3 of 5)

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

Name

Bit 7

Bit 0

0x0011

ATDDR0L

10-BIT

8-BIT

BIT 7

BIT 7 MSB

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0x0012

ATDDR1H

10-BIT

8-BIT

BIT 9 MSB

BIT 8

0x0013

ATDDR1L

10-BIT

8-BIT

BIT 7

BIT 7 MSB

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0x0014

ATDDR2H

10-BIT

8-BIT

BIT 9 MSB

BIT 8

0x0015

ATDDR2L

10-BIT

8-BIT

BIT 7

BIT 7 MSB

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0x0016

ATDDR3H

10-BIT

8-BIT

BIT 9 MSB

BIT 8

0x0017

ATDDR3L

10-BIT

8-BIT

BIT 7

BIT 7 MSB

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0x0018

ATDDR4H

10-BIT

8-BIT

BIT 9 MSB

BIT 8

0x0019

ATDDR4L

10-BIT

8-BIT

BIT 7

BIT 7 MSB

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0x001A

ATDD45H

10-BIT

8-BIT

BIT 9 MSB

BIT 8

0x001B

ATDD45L

10-BIT

8-BIT

BIT 7

BIT 7 MSB

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0x001C

ATDD46H

10-BIT

8-BIT

BIT 9 MSB

BIT 8

= Unimplemented or Reserved

Figure 8-2. ATD Register Summary (Sheet 4 of 5)

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

Bit 7

Bit 0

Name

0x001D

ATDDR6L

10-BIT

8-BIT

BIT 7

BIT 7 MSB

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0x001E

ATDD47H

10-BIT

8-BIT

BIT 9 MSB

BIT 8

0x001F

ATDD47L

10-BIT

8-BIT

BIT 7

BIT 7 MSB

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

= Unimplemented or Reserved

Figure 8-2. ATD Register Summary (Sheet 5 of 5)

8.3.2.1

ATD Control Register 0 (ATDCTL0)

Writes to this register will abort current conversion sequence but will not start a new sequence.

Module Base + 0x0000

WRAP2

WRAP1

WRAP0

Reset

= Unimplemented or Reserved

Figure 8-3. ATD Control Register 0 (ATDCTL0)

Read: Anytime

Write: Anytime

Table 8-1. ATDCTL0 Field Descriptions

Description

Field

2–0

Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing

WRAP[2:0] multi-channel conversions. The coding is summarized in Table 8-2.

Table 8-2. Multi-Channel Wrap Around Coding

Multiple Channel Conversions (MULT = 1)

Wrap Around to AN0 after Converting

WRAP2

WRAP1

WRAP0

Reserved

AN1

AN2

AN3

AN4

AN5

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

Table 8-2. Multi-Channel Wrap Around Coding

Multiple Channel Conversions (MULT = 1)

Wrap Around to AN0 after Converting

WRAP2

WRAP1

WRAP0

AN6

AN7

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

8.3.2.2

ATD Control Register 1 (ATDCTL1)

Writes to this register will abort current conversion sequence but will not start a new sequence.

Module Base + 0x0001

ETRIGSEL

ETRIGCH2 ETRIGCH1 ETRIGCH0

Reset

= Unimplemented or Reserved

Figure 8-4. ATD Control Register 1 (ATDCTL1)

Read: Anytime

Write: Anytime

Table 8-3. ATDCTL1 Field Descriptions

Description

Field

External Trigger Source Select — This bit selects the external trigger source to be either one of the AD

ETRIGSEL channels or one of the ETRIG3–0 inputs. See the device overview chapter for availability and connectivity of

ETRIG3–0 inputs. If ETRIG3–0 input option is not available, writing a 1 to ETRISEL only sets the bit but has

not effect, that means still one of the AD channels (selected by ETRIGCH2–0) is the source for external trigger.

The coding is summarized in Table 8-4.

2–0

External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3–0 inputs

ETRIGCH[2:0] as source for the external trigger. The coding is summarized in Table 8-4.

Table 8-4. External Trigger Channel Select Coding

ETRIGSEL ETRIGCH2 ETRIGCH1 ETRIGCH0

External trigger source is

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

ETRIG0

ETRIG1

ETRIG2

ETRIG3

Reserved

Only if ETRIG3–0 input option is available (see device overview chapter), else ETRISEL is

ignored, that means external trigger source is still on one of the AD channels selected by

ETRIGCH2–0

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

8.3.2.3

ATD Control Register 2 (ATDCTL2)

This register controls power down, interrupt and external trigger. Writes to this register will abort current

conversion sequence but will not start a new sequence.

Module Base + 0x0002

ASCIF

ADPU

AFFC

AWAI

ETRIGLE

ETRIGP

ETRIGE

ASCIE

Reset

= Unimplemented or Reserved

Figure 8-5. ATD Control Register 2 (ATDCTL2)

Read: Anytime

Write: Anytime

Table 8-5. ATDCTL2 Field Descriptions

Description

Field

ATD Power Up — This bit provides on/off control over the ATD block allowing reduced MCU power

ADPU

consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time

period after ADPU bit is enabled.

0 Power down ATD

1 Normal ATD functionality

ATD Fast Flag Clear All

AFFC

0 ATD ﬂag clearing operates normally (read the status register ATDSTAT1 before reading the result register to

clear the associate CCF ﬂag).

1 Changes all ATD conversion complete ﬂags to a fast clear sequence. Any access to a result register will

cause the associate CCF ﬂag to clear automatically.

ATD Power Down in Wait Mode — When entering wait mode this bit provides on/off control over the ATD block

allowing reduced MCU power. Because analog electronic is turned off when powered down, the ATD requires

a recovery time period after exit from Wait mode.

AWAI

0 ATD continues to run in Wait mode

1 Halt conversion and power down ATD during wait mode

After exiting wait mode with an interrupt conversion will resume. But due to the recovery time the result of

this conversion should be ignored.

External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See

ETRIGLE

Table 8-6 for details.

External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 8-6 for

ETRIGP

details.

External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of

the ETRIG3–0 inputs as described in Table 8-4. If external trigger source is one of the AD channels, the digital

input buffer of this channel is enabled. The external trigger allows to synchronize sample and ATD conversions

processes with external events.

ETRIGE

0 Disable external trigger

1 Enable external trigger

Note: If using one of the AD channel as external trigger (ETRIGSEL = 0) the conversion results for this channel

have no meaning while external trigger mode is enabled.

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

Table 8-5. ATDCTL2 Field Descriptions (continued)

Field

Description

ATD Sequence Complete Interrupt Enable

ASCIE

0 ATD Sequence Complete interrupt requests are disabled.

1 A T D Interrupt will be requested whenever ASCIF = 1 is set.

ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF ﬂag equals the SCF ﬂag (see

Section 8.3.2.7, “ATD Status Register 0 (ATDSTAT0)”), else ASCIF reads zero. Writes have no effect.

0 No ATD interrupt occurred

ASCIF

1 ATD sequence complete interrupt pending

Table 8-6. External Trigger Conﬁgurations

ETRIGLE

ETRIGP

External Trigger Sensitivity

Falling edge

Rising edge

Low level

High level

8.3.2.4

ATD Control Register 3 (ATDCTL3)

This register controls the conversion sequence length, FIFO for results registers and behavior in freeze

mode. Writes to this register will abort current conversion sequence but will not start a new sequence.

Module Base + 0x0003

S8C

S4C

S2C

S1C

FIFO

FRZ1

FRZ0

Reset

= Unimplemented or Reserved

Figure 8-6. ATD Control Register 3 (ATDCTL3)

Read: Anytime

Write: Anytime

Table 8-7. ATDCTL3 Field Descriptions

Description

Field

6–3

Conversion Sequence Length — These bits control the number of conversions per sequence. Table 8-8 shows

S8C, S4C, all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12

S2C, S1C Family.

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

Table 8-7. ATDCTL3 Field Descriptions (continued)

Field

Description

Result Register FIFO Mode — If this bit is zero (non-FIFO mode), the A/D conversion results map into the result

registers based on the conversion sequence; the result of the ﬁrst conversion appears in the ﬁrst result register,

the second result in the second result register, and so on.

FIFO

If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or end of a conversion

sequence; conversion results are placed in consecutive result registers between sequences. The result register

counter wraps around when it reaches the end of the result register ﬁle. The conversion counter value in

ATDSTAT0 can be used to determine where in the result register ﬁle, the current conversion result will be placed.

Finally, which result registers hold valid data can be tracked using the conversion complete ﬂags. Fast ﬂag clear

mode may or may not be useful in a particular application to track valid data.

0 Conversion results are placed in the corresponding result register up to the selected sequence length.

1 Conversion results are placed in consecutive result registers (wrap around at end).

1–0

FRZ[1:0]

Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the

ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond

to a breakpoint as shown in Table 8-9. Leakage onto the storage node and comparator reference capacitors may

compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.

Table 8-8. Conversion Sequence Length Coding

Number of Conversions

S8C

S4C

S2C

S1C

per Sequence

Table 8-9. ATD Behavior in Freeze Mode (Breakpoint)

FRZ1

FRZ0

Behavior in Freeze Mode

Continue conversion

Reserved

Finish current conversion, then freeze

Freeze Immediately

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

8.3.2.5

ATD Control Register 4 (ATDCTL4)

This register selects the conversion clock frequency, the length of the second phase of the sample time and

the resolution of the A/D conversion (i.e.: 8-bits or 10-bits). Writes to this register will abort current

conversion sequence but will not start a new sequence.

Module Base + 0x0004

SRES8

SMP1

SMP0

PRS4

PRS3

PRS2

PRS1

PRS0

Reset

Figure 8-7. ATD Control Register 4 (ATDCTL4)

Read: Anytime

Write: Anytime

Table 8-10. ATDCTL4 Field Descriptions

Description

Field

A/D Resolution Select — This bit selects the resolution of A/D conversion results as either 8 or 10 bits. The

SRES8

A/D converter has an accuracy of 10 bits; however, if low resolution is required, the conversion can be speeded

up by selecting 8-bit resolution.

0 10-bit resolution

8-bit resolution

6–5

SMP[1:0]

Sample Time Select — These two bits select the length of the second phase of the sample time in units of

ATD conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler value

(bits PRS4–0). The sample time consists of two phases. The ﬁrst phase is two ATD conversion clock cycles

long and transfers the sample quickly (via the buffer ampliﬁer) onto the A/D machine’s storage node. The

second phase attaches the external analog signal directly to the storage node for ﬁnal charging and high

accuracy. Table 8-11 lists the lengths available for the second sample phase.

4–0

ATD Clock Prescaler — These 5 bits are the binary value prescaler value PRS. The ATD conversion clock

PRS[4:0]

frequency is calculated as follows:

[BusClock]

ATDclock =

× 0.5

--------------------------------

[PRS + 1]

Note: The maximum ATD conversion clock frequency is half the bus clock. The default (after reset) prescaler

value is 5 which results in a default ATD conversion clock frequency that is bus clock divided by 12.

Table 8-12 illustrates the divide-by operation and the appropriate range of the bus clock.

Table 8-11. Sample Time Select

SMP1

SMP0

Length of 2nd Phase of Sample Time

2 A/D conversion clock periods

4 A/D conversion clock periods

8 A/D conversion clock periods

16 A/D conversion clock periods

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

Table 8-12. Clock Prescaler Values

Total Divisor

Value

Prescale Value

Max. Bus Clock

Min. Bus Clock

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Divide by 2

Divide by 4

Divide by 6

4 MHz

8 MHz

1 MHz

2 MHz

3 MHz

4 MHz

5 MHz

6 MHz

7 MHz

8 MHz

9 MHz

12 MHz

16 MHz

20 MHz

24 MHz

28 MHz

32 MHz

36 MHz

40 MHz

44 MHz

48 MHz

52 MHz

56 MHz

60 MHz

64 MHz

68 MHz

72 MHz

76 MHz

80 MHz

84 MHz

88 MHz

92 MHz

96 MHz

100 MHz

104 MHz

108 MHz

112 MHz

116 MHz

120 MHz

124 MHz

128 MHz

Divide by 8

Divide by 10

Divide by 12

Divide by 14

Divide by 16

Divide by 18

Divide by 20

Divide by 22

Divide by 24

Divide by 26

Divide by 28

Divide by 30

Divide by 32

Divide by 34

Divide by 36

Divide by 38

Divide by 40

Divide by 42

Divide by 44

Divide by 46

Divide by 48

Divide by 50

Divide by 52

Divide by 54

Divide by 56

Divide by 58

Divide by 60

Divide by 62

Divide by 64

10 MHz

11 MHz

12 MHz

13 MHz

14 MHz

15 MHz

16 MHz

17 MHz

18 MHz

19 MHz

20 MHz

21 MHz

22 MHz

23 MHz

24 MHz

25 MHz

26 MHz

27 MHz

28 MHz

29 MHz

30 MHz

31 MHz

32 MHz

Maximum ATD conversion clock frequency is 2 MHz. The maximum allowed bus clock frequency is

shown in this column.

Minimum ATD conversion clock frequency is 500 kHz. The minimum allowed bus clock frequency is

shown in this column.

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

8.3.2.6

ATD Control Register 5 (ATDCTL5)

This register selects the type of conversion sequence and the analog input channels sampled. Writes to this

Module Base + 0x0005

DJM

DSGN

SCAN

MULT

Reset

= Unimplemented or Reserved

Figure 8-8. ATD Control Register 5 (ATDCTL5)

Read: Anytime

Write: Anytime

Table 8-13. ATDCTL5 Field Descriptions

Description

Field

DJM

Result Register Data Justiﬁcation — This bit controls justiﬁcation of conversion data in the result registers.

See Section 8.3.2.13, “ATD Conversion Result Registers (ATDDRx),” for details.

0 Left justiﬁed data in the result registers

1 Right justiﬁed data in the result registers

Result Register Data Signed or Unsigned Representation — This bit selects between signed and unsigned

conversion data representation in the result registers. Signed data is represented as 2’s complement. Signed

data is not available in right justiﬁcation. See Section 8.3.2.13, “ATD Conversion Result Registers (ATDDRx),”

for details.

DSGN

0 Unsigned data representation in the result registers

1 Signed data representation in the result registers

Table 8-14 summarizes the result data formats available and how they are set up using the control bits.

Table 8-15 illustrates the difference between the signed and unsigned, left justiﬁed output codes for an input

signal range between 0 and 5.12 Volts.

Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed

continuously or only once.

SCAN

0 Single conversion sequence

1 Continuous conversion sequences (scan mode)

Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the speciﬁed

analog input channel for an entire conversion sequence. The analog channel is selected by channel selection

code (control bits CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples

across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C,

S2C, S1C). The ﬁrst analog channel examined is determined by channel selection code (CC, CB, CA control

bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection

code.

MULT

0 Sample only one channel

1 Sample across several channels

2–0

Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are

CC, CB, CA sampled and converted to digital codes. Table 8-16 lists the coding used to select the various analog input

channels. In the case of single channel scans (MULT = 0), this selection code speciﬁed the channel examined.

In the case of multi-channel scans (MULT = 1), this selection code represents the ﬁrst channel to be examined

in the conversion sequence. Subsequent channels are determined by incrementing channel selection code;

selection codes that reach the maximum value wrap around to the minimum value.

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

Table 8-14. Available Result Data Formats

Result Data Formats

Description and Bus Bit Mapping

SRES8

DJM

DSGN

8-bit / left justiﬁed / unsigned — bits 8–15

8-bit / left justiﬁed / signed — bits 8–15

8-bit / right justiﬁed / unsigned — bits 0–7

10-bit / left justiﬁed / unsigned — bits 6–15

10-bit / left justiﬁed / signed — bits 6–15

10-bit / right justiﬁed / unsigned — bits 0–9

Table 8-15. Left Justiﬁed, Signed, and Unsigned ATD Output Codes

Input Signal

Signed

8-Bit

Unsigned

8-Bit

Signed

10-Bit

Unsigned

10-Bit

= 0 Volts

= 5.12 Volts

Codes

5.120 Volts

5.100

7FC0

7F00

7E00

FFC0

FF00

FE00

5.080

2.580

2.560

2.540

0100

0000

FF00

8100

8000

7F00

0.020

0.000

8100

8000

0100

0000

Table 8-16. Analog Input Channel Select Coding

Analog Input

Channel

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

8.3.2.7

ATD Status Register 0 (ATDSTAT0)

This read-only register contains the sequence complete ﬂag, overrun ﬂags for external trigger and FIFO

mode, and the conversion counter.

Module Base + 0x0006

CC2

CC1

CC0

SCF

ETORF

FIFOR

Reset

= Unimplemented or Reserved

Figure 8-9. ATD Status Register 0 (ATDSTAT0)

Read: Anytime

Write: Anytime (No effect on (CC2, CC1, CC0))

Table 8-17. ATDSTAT0 Field Descriptions

Field

Description

SCF

Sequence Complete Flag — This ﬂag is set upon completion of a conversion sequence. If conversion

sequences are continuously performed (SCAN = 1), the ﬂag is set after each one is completed. This ﬂag is

cleared when one of the following occurs:

A) Write “1” to SCF

B) Write to ATDCTL5 (a new conversion sequence is started)

C) If AFFC=1 and read of a result register

0 Conversion sequence not completed

1 Conversion sequence has completed

External Trigger Overrun Flag — While in edge trigger mode (ETRIGLE = 0), if additional active edges are

detected while a conversion sequence is in process the overrun ﬂag is set. This ﬂag is cleared when one of the

following occurs:

ETORF

A) Write “1” to ETORF

B) Write to ATDCTL2, ATDCTL3 or ATDCTL4 (a conversion sequence is aborted)

C) Write to ATDCTL5 (a new conversion sequence is started)

0 No External trigger over run error has occurred

1 External trigger over run error has occurred

FIFO Over Run Flag — This bit indicates that a result register has been written to before its associated

conversion complete ﬂag (CCF) has been cleared. This ﬂag is most useful when using the FIFO mode because

the ﬂag potentially indicates that result registers are out of sync with the input channels. However, it is also

practical for non-FIFO modes, and indicates that a result register has been over written before it has been read

(i.e., the old data has been lost). This ﬂag is cleared when one of the following occurs:

A) Write “1” to FIFOR

FIFOR

B) Start a new conversion sequence (write to ATDCTL5 or external trigger)

0 No over run has occurred

1 An over run condition exists

2–0

CC[2:0]

Conversion Counter — These 3 read-only bits are the binary value of the conversion counter. The conversion

counter points to the result register that will receive the result of the current conversion. E.g. CC2 = 1, CC1 = 1,

CC0 = 0 indicates that the result of the current conversion will be in ATD result register 6. If in non-FIFO mode

(FIFO = 0) the conversion counter is initialized to zero at the begin and end of the conversion sequence. If in

FIFO mode (FIFO = 1) the register counter is not initialized. The conversion counters wraps around when its

maximum value is reached.

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

8.3.2.8

Reserved Register (ATDTEST0)

Module Base + 0x0008

Reset

= Unimplemented or Reserved

Figure 8-10. Reserved Register (ATDTEST0)

Read: Anytime, returns unpredictable values

Write: Anytime in special modes, unimplemented in normal modes

NOTE

Writing to this register when in special modes can alter functionality.

8.3.2.9

ATD Test Register 1 (ATDTEST1)

This register contains the SC bit used to enable special channel conversions.

Module Base + 0x0009

Reset

= Unimplemented or Reserved

Figure 8-11. ATD Test Register 1 (ATDTEST1)

Read: Anytime, returns unpredictable values for Bit7 and Bit6

Write: Anytime

Table 8-18. ATDTEST1 Field Descriptions

Field

Description

Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CC,

CB and CA of ATDCTL5. Table 8-19 lists the coding.

0 Special channel conversions disabled

1 Special channel conversions enabled

Note: Always write remaining bits of ATDTEST1 (Bit7 to Bit1) zero when writing SC bit. Not doing so might result

in unpredictable ATD behavior.

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

Table 8-19. Special Channel Select Coding

Analog Input Channel

Reserved

(V +V ) / 2

Reserved

8.3.2.10 ATD Status Register 1 (ATDSTAT1)

This read-only register contains the conversion complete ﬂags.

Module Base + 0x000B

CCF7

CCF6

CCF5

CCF4

CCF3

CCF2

CCF1

CCF0

Reset

= Unimplemented or Reserved

Figure 8-12. ATD Status Register 1 (ATDSTAT1)

Read: Anytime

Write: Anytime, no effect

Table 8-20. ATDSTAT1 Field Descriptions

Description

Field

7–0

CCF[7:0]

Conversion Complete Flag x (x = 7, 6, 5, 4, 3, 2, 1, 0) — A conversion complete ﬂag is set at the end of each

conversion in a conversion sequence. The ﬂags are associated with the conversion position in a sequence (and

also the result register number). Therefore, CCF0 is set when the ﬁrst conversion in a sequence is complete and

the result is available in result register ATDDR0; CCF1 is set when the second conversion in a sequence is

complete and the result is available in ATDDR1, and so forth. A ﬂag CCFx (x = 7, 6, 5, 4, 3, 2,1, 70) is cleared

when one of the following occurs:

A) Write to ATDCTL5 (a new conversion sequence is started)

B) If AFFC=0 and read of ATDSTAT1 followed by read of result register ATDDRx

C) If AFFC=1 and read of result register ATDDRx

In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing by

methods B) or C) will be overwritten by the set.

0 Conversion number x not completed

1 Conversion number x has completed, result ready in ATDDRx

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

8.3.2.11 ATD Input Enable Register (ATDDIEN)

Module Base + 0x000D

IEN7

IEN6

IEN5

IEN4

IEN3

IEN2

IEN1

IEN0

Reset

Figure 8-13. ATD Input Enable Register (ATDDIEN)

Read: Anytime

Write: Anytime

Table 8-21. ATDDIEN Field Descriptions

Description

Field

7–0

IEN[7:0]

ATD Digital Input Enable on channel x (x = 7, 6, 5, 4, 3, 2, 1, 0) — This bit controls the digital input buffer from

the analog input pin (ANx) to PTADx data register.

0 Disable digital input buffer to PTADx

1 Enable digital input buffer to PTADx.

Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while

simultaneously using it as an analog port, there is potentially increased power consumption because the

digital input buffer maybe in the linear region.

8.3.2.12 Port Data Register (PORTAD)

The data port associated with the ATD can be conﬁgured as general-purpose I/O or input only, as speciﬁed

in the device overview. The port pins are shared with the analog A/D inputs AN7–0.

Module Base + 0x000F

PTAD7

PTAD6

PTAD5

PTAD4

PTAD3

PTAD2

PTAD1

PTAD0

Reset

Function

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

= Unimplemented or Reserved

Figure 8-14. Port Data Register (PORTAD)

Read: Anytime

Write: Anytime, no effect

The A/D input channels may be used for general purpose digital input.

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

Table 8-22. PORTAD Field Descriptions

Field

Description

7–0

A/D Channel x (ANx) Digital Input (x = 7, 6, 5, 4, 3, 2, 1, 0) — If the digital input buffer on the ANx pin is enabled

PTAD[7:0] (IENx = 1) or channel x is enabled as external trigger (ETRIGE = 1,ETRIGCH[2–0] = x,ETRIGSEL = 0) read

returns the logic level on ANx pin (signal potentials not meeting V or V speciﬁcations will have an

indeterminate value).

If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns

a “1”.

Reset sets all PORTAD0 bits to “1”.

8.3.2.13 ATD Conversion Result Registers (ATDDRx)

The A/D conversion results are stored in 8 read-only result registers. The result data is formatted in the

result registers based on two criteria. First there is left and right justiﬁcation; this selection is made using

the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using

the DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement format and only exists in left

justiﬁed format. Signed data selected for right justiﬁed format is ignored.

Read: Anytime

Write: Anytime in special mode, unimplemented in normal modes

8.3.2.13.1 Left Justiﬁed Result Data

Module Base + 0x0010 = ATDDR0H, 0x0012 = ATDDR1H, 0x0014 = ATDDR2H, 0x0016 = ATDDR3H

Module Base + 0x0018 = ATDDR4H, 0x001A = ATDDR5H, 0x001C = ATDDR6H, 0x001E = ATDDR7H

BIT 9 MSB

BIT 7 MSB

BIT 8

BIT 6

BIT 7

BIT 5

BIT 6

BIT 4

BIT 5

BIT 3

BIT 4

BIT 2

BIT 3

BIT 1

BIT 2

BIT 0

10-bit data

8-bit data

Reset

= Unimplemented or Reserved

Figure 8-15. Left Justiﬁed, ATD Conversion Result Register, High Byte (ATDDRxH)

Module Base + 0x0011 = ATDDR0L, 0x0013 = ATDDR1L, 0x0015 = ATDDR2L, 0x0017 = ATDDR3L

Module Base + 0x0019 = ATDDR4L, 0x001B = ATDDR5L, 0x001D = ATDDR6L, 0x001F = ATDDR7L

BIT 1

BIT 0

Reset

= Unimplemented or Reserved

Figure 8-16. Left Justiﬁed, ATD Conversion Result Register, Low Byte (ATDDRxL)

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

8.3.2.13.2 Right Justiﬁed Result Data

Module Base + 0x0010 = ATDDR0H, 0x0012 = ATDDR1H, 0x0014 = ATDDR2H, 0x0016 = ATDDR3H

Module Base + 0x0018 = ATDDR4H, 0x001A = ATDDR5H, 0x001C = ATDDR6H, 0x001E = ATDDR7H

BIT 9 MSB

BIT 8

10-bit data

8-bit data

Reset

= Unimplemented or Reserved

Figure 8-17. Right Justiﬁed, ATD Conversion Result Register, High Byte (ATDDRxH)

Module Base + 0x0011 = ATDDR0L, 0x0013 = ATDDR1L, 0x0015 = ATDDR2L, 0x0017 = ATDDR3L

Module Base + 0x0019 = ATDDR4L, 0x001B = ATDDR5L, 0x001D = ATDDR6L, 0x001F = ATDDR7L

BIT 7

BIT 7 MSB

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

10-bit data

8-bit data

Reset

= Unimplemented or Reserved

Figure 8-18. Right Justiﬁed, ATD Conversion Result Register, Low Byte (ATDDRxL)

8.4

Functional Description

The ATD is structured in an analog and a digital sub-block.

8.4.1

Analog Sub-Block

The analog sub-block contains all analog electronics required to perform a single conversion. Separate

power supplies V and V allow to isolate noise of other MCU circuitry from the analog sub-block.

DDA

SSA

8.4.1.1

Sample and Hold Machine

The sample and hold (S/H) machine accepts analog signals from the external surroundings and stores them

as capacitor charge on a storage node.

The sample process uses a two stage approach. During the ﬁrst stage, the sample ampliﬁer is used to

quickly charge the storage node.The second stage connects the input directly to the storage node to

complete the sample for high accuracy.

When not sampling, the sample and hold machine disables its own clocks. The analog electronics still draw

their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the

analog power consumption.

The input analog signals are unipolar and must fall within the potential range of V

to V

SSA

DDA

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

8.4.1.2

Analog Input Multiplexer

The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold

machine.

8.4.1.3

Sample Buffer Ampliﬁer

The sample ampliﬁer is used to buffer the input analog signal so that the storage node can be quickly

charged to the sample potential.

8.4.1.4

Analog-to-Digital (A/D) Machine

The A/D Machine performs analog to digital conversions. The resolution is program selectable at either 8

or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the

stored analog sample potential with a series of digitally generated analog potentials. By following a binary

search algorithm, the A/D machine locates the approximating potential that is nearest to the sampled

potential.

When not converting the A/D machine disables its own clocks. The analog electronics still draws quiescent

current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power

consumption.

Only analog input signals within the potential range of V to V (A/D reference potentials) will result

in a non-railed digital output codes.

8.4.2

Digital Sub-Block

This subsection explains some of the digital features in more detail. See register descriptions for all details.

8.4.2.1

External Trigger Input

The external trigger feature allows the user to synchronize ATD conversions to the external environment

events rather than relying on software to signal the ATD module when ATD conversions are to take place.

The external trigger signal (out of reset ATD channel 7, conﬁgurable in ATDCTL1) is programmable to

be edge or level sensitive with polarity control. Table 8-23 gives a brief description of the different

combinations of control bits and their effect on the external trigger function.

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

Table 8-23. External Trigger Control Bits

ETRIGLE

ETRIGP

ETRIGE

SCAN

Description

Ignores external trigger. Performs one

conversion sequence and stops.

Ignores external trigger. Performs

continuous conversion sequences.

Falling edge triggered. Performs one

conversion sequence per trigger.

Rising edge triggered. Performs one

conversion sequence per trigger.

Trigger active low. Performs

continuous conversions while trigger

is active.

Trigger active high. Performs

continuous conversions while trigger

is active.

During a conversion, if additional active edges are detected the overrun error ﬂag ETORF is set.

In either level or edge triggered modes, the ﬁrst conversion begins when the trigger is received. In both

cases, the maximum latency time is one bus clock cycle plus any skew or delay introduced by the trigger

circuitry.

NOTE

The conversion results for the external trigger ATD channel 7 have no

meaning while external trigger mode is enabled.

Once ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be

triggered externally.

If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion

sequence, this does not constitute an overrun; therefore, the ﬂag is not set. If the trigger is left asserted in

level mode while a sequence is completing, another sequence will be triggered immediately.

8.4.2.2

General Purpose Digital Input Port Operation

The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are

multiplexed and sampled to supply signals to the A/D converter. As digital inputs, they supply external

input data that can be accessed through the digital port register PORTAD (input-only).

The analog/digital multiplex operation is performed in the input pads. The input pad is always connected

to the analog inputs of the ATD. The input pad signal is buffered to the digital port registers. This buffer

can be turned on or off with the ATDDIEN register. This is important so that the buffer does not draw

excess current when analog potentials are presented at its input.

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Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)

8.4.2.3

Low Power Modes

The ATD can be conﬁgured for lower MCU power consumption in 3 different ways:

1. Stop mode: This halts A/D conversion. Exit from stop mode will resume A/D conversion, but due

to the recovery time the result of this conversion should be ignored.

2. Wait mode with AWAI = 1: This halts A/D conversion. Exit from wait mode will resume A/D

conversion, but due to the recovery time the result of this conversion should be ignored.

3. Writing ADPU = 0 (Note that all ATD registers remain accessible.): This aborts any A/D

conversion in progress.

Note that the reset value for the ADPU bit is zero. Therefore, when this module is reset, it is reset into the

power down state.

8.5

Resets

At reset the ATD is in a power down state. The reset state of each individual bit is listed within the Register

Description section (see Section 8.3, “Memory Map and Register Deﬁnition”), which details the registers

and their bit-ﬁeld.

8.6

Interrupts

The interrupt requested by the ATD is listed in Table 8-24. Refer to the device overview chapter for related

vector address and priority.

Table 8-24. ATD Interrupt Vectors

CCR

Mask

Interrupt Source

Local Enable

Sequence complete

interrupt

I bit

ASCIE in ATDCTL2

See register descriptions for further details.

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Chapter 9

XGATE (S12XGATEV2)

9.1

Introduction

The XGATE module is a peripheral co-processor that allows autonomous data transfers between the

MCU’s peripherals and the internal memories. It has a built in RISC core that is able to pre-process the

transferred data and perform complex communication protocols.

The XGATE module is intended to increase the MCU’s data throughput by lowering the S12X_CPU’s

interrupt load.

Figure 9-1 gives an overview on the XGATE architecture.

This document describes the functionality of the XG A T E module, including:

•

XGATE registers (Section 9.3, “Memory Map and Register Deﬁnition”)

XGATE RISC core (Section 9.4.1, “XGATE RISC Core”)

Hardware semaphores (Section 9.4.4, “Semaphores”)

Interrupt handling (Section 9.5, “Interrupts”)

Debug features (Section 9.6, “Debug Mode”)

Security (Section 9.7, “Security”)

Instruction set (Section 9.8, “Instruction Set”)

9.1.1

Features

The XGATE module includes these features:

•

Data movement between various targets (i.e Flash, RAM, and peripheral modules)

Data manipulation through built in RISC core

Provides up to 112 XGATE channels

— 104 hardware triggered channels

— 8 software triggered channels

•

Hardware semaphores which are shared between the S12X_CPU and the XGATE module

Able to trigger S12X_CPU interrupts upon completion of an XGATE transfer

Software error detection to catch erratic application code

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Chapter 9 XGATE (S12XGATEV2)

9.1.2

Modes of Operation

There are four run modes on S12X devices.

•

Run mode, wait mode, stop mode

The XGATE is able to operate in all of these three system modes. Clock activity will be

automatically stopped when the XGATE module is idle.

•

Freeze mode (BDM active)

In freeze mode all clocks of the XGATE module may be stopped, depending on the module

configuration (see Section 9.3.2.1, “XGATE Control Register (XGMCTL)”).

9.1.3

Block Diagram

Figure Figure 9-1 shows a block diagram of the XGATE.

Peripheral Interrupts

S12X_INT

XGATE

Interrupt Flags

Semaphores

Software

RISC Core

Triggers

Software Triggers

S12X_DBG

S12X_MMC

Peripherals

Figure 9-1. XGATE Block Diagram

9.2

External Signal Description

The XGATE module has no external pins.

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Chapter 9 XGATE (S12XGATEV2)

9.3

Memory Map and Register Deﬁnition

This section provides a detailed description of address space and registers used by the XGATE module.

The memory map for the XGATE module is given below in Table 9-1.The address listed for each register

is the sum of a base address and an address offset. The base address is deﬁned at the SoC level and the

address offset is deﬁned at the module level. Reserved registers read zero. Write accesses to the reserved

registers have no effect.

9.3.1

Module Memory Map

Table 9-1. Module Memory Map

Address Offset

Use

Access

0x0000, 0x0001

0x0002

XGATE Module Control Register (XGMCTL)

XGATE Channel ID Register (XGCHID)

Read/Write

1,2

Read/Write

0x0003

0x0004, 0x0005

Reserved

None

0x0006, 0x0007

XGATE Vector Base Address (XGVBR)

Read/Write

0x0008, 0x0009,

0x000A, 0x000B,

0x000C, 0x000D,

0x000E, 0x000F,

0x0010, 0x0011,

0x0012, 0x0013,

0x0014, 0x0015,

0x0016, 0x0017

XGATE Interrupt Flag Vector (XGIF)

0x0018, 0x0019

0x001A, 0x001B

0x001C

XGATE Software Trigger Register (XGSWT)

XGATE Semaphore Register (XGSEM)

Reserved

Read/Write

None

1,4

0x001D

XGATE Condition Code Register (XGCCR)

XGATE Program Counter (XGPC)

Reserved

Read/Write

None

0x001E, 0x001F

0x0020, 0x0021

0x0022, 0x0023

0x0024, 0x0025

0x0026, 0x0027

0x0028, 0x0029

0x002A,0x002B

0x002C, 0x002D

0x002E, 0x002F

XGATE Register 1 (XGR1)

XGATE Register 2 (XGR2)

XGATE Register 3 (XGR3)

XGATE Register 4 (XGR4)

XGATE Register 5 (XGR5)

XGATE Register 6 (XGR6)

XGATE Register 7 (XGR7)

Read/Write

0x0030, 0x0031,

0x0032, 0x0033,

0x0034, 0x0035,

0x0036, 0x0037,

0x0038, 0x0039

Reserved

None

Certain bits are not writable.

Write only if in Debug Mode.

See Section 9.4.4, “Semaphores”

Read and Write only if in Debug Mode.

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Chapter 9 XGATE (S12XGATEV2)

9.3.2

This section consists of register descriptions in address order. Each description includes a standard register

diagram with an associated ﬁgure number. Details of register bit and ﬁeld function follow the register

diagrams, in bit order.

Name

0x0000

XGMCTL

FACT

SWEIF

XGE XGFRZ XGDBG XGSS

XGIE

XG XG

FRZM DBGM

FACTM

SWEIFM

XGEM

XGSSM

XGIEM

0x0002

XGCHID[6:0]

XGMCHID

0x0003

Reserved

0x0004

Reserved

0x0005

Reserved

0x0006

XGVBR

XGVBR[15:1]

127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112

0x0008

XGIF

XGIF_78 XGF_77 XGIF_76 XGIF_75 XGIF_74 XGIF_73 XGIF_72 XGIF_71 XGIF_70

111 110 109 108 107 106 105 104 103 102 101 100

0x000A

XGIF

XGIF_6E XGIF_6D XGIF_6C XGIF_6B XGIF_6A XGIF_69 XGIF_68 XGF_67 XGIF_66 XGIF_65 XGIF_64 XGIF_63 XGIF_62 XGIF_61 XGIF_60

W ^XGIF_6F

0x000C

XGIF

XGIF_5E XGIF_5D XGIF_5C XGIF_5B XGIF_5A XGIF_59 XGIF_58 XGF_57 XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50

W ^XGIF_5F

0x000E

XGIF

XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48 XGF _47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40

W ^XGIF_4F

= Unimplemented or Reserved

Figure 9-2. XGATE Register Summary (Sheet 1 of 3)

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Chapter 9 XGATE (S12XGATEV2)

Name

0x0010

XGIF

XGIF_3E XGIF_3D XGIF_3C XGIF_3B XGIF_3A XGIF_39 XGIF_38 XGF _37 XGIF_36 XGIF_35 XGIF_34 XGIF_33 XGIF_32 XGIF_31 XGIF_30

W ^XGIF_3F

0x0012

XGIF

XGIF_2E XGIF_2D XGIF_2C XGIF_2B XGIF_2A XGIF_29 XGIF_28 XGF _27 XGIF_26 XGIF_25 XGIF_24 XGIF_23 XGIF_22 XGIF_21 XGIF_20

W ^XGIF_2F

0x0014

XGIF

XGIF_1E XGIF_1D XGIF_1C XGIF_1B XGIF_1A XGIF_19 XGIF_18 XGF _17 XGIF_16 XGIF_15 XGIF_14 XGIF_13 XGIF_12 XGIF_11 XGIF_10

W ^XGIF_1F

0x0016

XGIF

XGIF_0E XGIF_0D XGIF_0C XGIF_0B XGIF_0A XGIF_09

W ^XGIF_0F

0x0018

XGSWTM

XGSWT[7:0]

XGSEM[7:0]

XGSWTM[7:0]

0x001A

XGSEMM

XGSEMM[7:0]

0x001C

Reserved

0x001D

XGCCR

XGN XGZ XGV XGC

0x001E

XGPC

0x0020

Reserved

0x0021

Reserved

0x0022

XGR1

XGR2

0x0024

XGR2

= Unimplemented or Reserved

Figure 9-2. XGATE Register Summary (Sheet 2 of 3)

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Chapter 9 XGATE (S12XGATEV2)

Name

0x0026

XGR3

0x0028

XGR4

XGR5

XGR6

XGR7

0x002A

XGR5

0x002C

XGR6

0x002E

XGR7

= Unimplemented or Reserved

Figure 9-2. XGATE Register Summary (Sheet 3 of 3)

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Chapter 9 XGATE (S12XGATEV2)

9.3.2.1

XGATE Control Register (XGMCTL)

All module level switches and flags are located in the module control register Figure 9-3.

Module Base +0x00000

SWEIF

XGE XGFRZ XGDBG XGSS XGFACT

XGIE

XG XG

FRZM DBGM SSM FACTM

SWEIFM

XGEM

XGIEM

Reset

= Unimplemented or Reserved

Figure 9-3. XGATE Control Register (XGMCTL)

Read: Anytime

Write: Anytime

Table 9-2. XGMCTL Field Descriptions (Sheet 1 of 3)

Description

Field

XGE Mask — This bit controls the write access to the XGE bit. The XGE bit can only be set or cleared if a "1" is

XGEM

written to the XGEM bit in the same register access.

Read:

This bit will always read "0".

Write:

0 Disable write access to the XGE in the same bus cycle

1 Enable write access to the XGE in the same bus cycle

XGFRZ Mask — This bit controls the write access to the XGFRZ bit. The XGFRZ bit can only be set or cleared

XGFRZM if a "1" is written to the XGFRZM bit in the same register access.

Read:

This bit will always read "0".

Write:

0 Disable write access to the XGFRZ in the same bus cycle

1 Enable write access to the XGFRZ in the same bus cycle

XGDBG Mask — This bit controls the write access to the XGDBG bit. The XGDBG bit can only be set or cleared

XGDBGM if a "1" is written to the XGDBGM bit in the same register access.

Read:

This bit will always read "0".

Write:

0 Disable write access to the XGDBG in the same bus cycle

1 Enable write access to the XGDBG in the same bus cycle

XGSS Mask — This bit controls the write access to the XGSS bit. The XGSS bit can only be set or cleared if a

XGSSM

"1" is written to the XGSSM bit in the same register access.

Read:

This bit will always read "0".

Write:

0 Disable write access to the XGSS in the same bus cycle

1 Enable write access to the XGSS in the same bus cycle

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Chapter 9 XGATE (S12XGATEV2)

Table 9-2. XGMCTL Field Descriptions (Sheet 2 of 3)

Description

Field

XGFACT Mask — This bit controls the write access to the XGFACT bit. The XGFACT bit can only be set or

XGFACTM cleared if a "1" is written to the XGFACTM bit in the same register access.

Read:

This bit will always read "0".

Write:

0 Disable write access to the XGFACT in the same bus cycle

1 Enable write access to the XGFACT in the same bus cycle

XGSWEIF Mask — This bit controls the write access to the XGSWEIF bit. The XGSWEIF bit can only be cleared

XGSWEIFM if a "1" is written to the XGSWEIFM bit in the same register access.

Read:

This bit will always read "0".

Write:

0 Disable write access to the XGSWEIF in the same bus cycle

1 Enable write access to the XGSWEIF in the same bus cycle

XGIE Mask — This bit controls the write access to the XGIE bit. The XGIE bit can only be set or cleared if a "1"

XGIEM

is written to the XGIEM bit in the same register access.

Read:

This bit will always read "0".

Write:

0 Disable write access to the XGIE in the same bus cycle

1 Enable write access to the XGIE in the same bus cycle

XGATE Module Enable — This bit enables the XGATE module. If the XGATE module is disabled, pending

XGE

XGATE requests will be ignored. The thread that is executed by the RISC core while the XGE bit is cleared will

continue to run.

Read:

0 XGATE module is disabled

1 XGATE module is enabled

Write:

0 Disable XGATE module

1 Enable XGATE module

Halt XGATE in Freeze Mode — The XGFRZ bit controls the XGATE operation in Freeze Mode (BDM active).

XGFRZ

Read:

0 RISC core operates normally in Freeze (BDM active)

1 RISC core stops in Freeze Mode (BDM active)

Write:

0 Don’t stop RISC core in Freeze Mode (BDM active)

1 Stop RISC core in Freeze Mode (BDM active)

XGATE Debug Mode — This bit indicates that the XGATE is in Debug Mode (see Section 9.6, “Debug Mode”).

XGDBG

Debug Mode can be entered by Software Breakpoints (BRK instruction), Tagged or Forced Breakpoints (see

S12X_DBG Section), or by writing a "1" to this bit.

Read:

0 RISC core is not in Debug Mode

1 RISC core is in Debug Mode

Write:

0 Leave Debug Mode

1 Enter Debug Mode

Note: Freeze Mode and Software Error Interrupts have no effect on the XGDBG bit.

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Chapter 9 XGATE (S12XGATEV2)

Table 9-2. XGMCTL Field Descriptions (Sheet 3 of 3)

Description

Field

XGATE Single Step — This bit forces the execution of a single instruction if the XGATE is in DEBUG Mode and

XGSS

no software error has occurred (XGSWEIF cleared).

Read:

0 No single step in progress

1 Single step in progress

Write

0 No effect

1 Execute a single RISC instruction

Note: Invoking a Single Step will cause the XGATE to temporarily leave Debug Mode until the instruction has

been executed.

Fake XGATE Activity — This bit forces the XGATE to ﬂag activity to the MCU even when it is idle. When it is set

XGFACT

the MCU will never enter system stop mode which assures that peripheral modules will be clocked during XGATE

idle periods

Read:

0 XGATE will only ﬂag activity if it is not idle or in debug mode.

1 XGATE will always signal activity to the MCU.

Write:

0 Only ﬂag activity if not idle or in debug mode.

1 Always signal XGATE activity.

XGATE Software Error Interrupt Flag — This bit signals a pending Software Error Interrupt. It is set if the RISC

XGSWEIF core detects an error condition (see Section 9.4.5, “Software Error Detection”). The RISC core is stopped while

this bit is set. Clearing this bit will terminate the current thread and cause the XGATE to become idle.

Read:

0 Software Error Interrupt is not pending

1 Software Error Interrupt is pending if XGIE is set

Write:

0 No effect

1 Clears the XGSWEIF bit

XGATE Interrupt Enable — This bit acts as a global interrupt enable for the XGATE module

XGIE

Read:

0 All XGATE interrupts disabled

1 All XGATE interrupts enabled

Write:

0 Disable all XGATE interrupts

1 Enable all XGATE interrupts

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 9 XGATE (S12XGATEV2)

9.3.2.2

XGATE Channel ID Register (XGCHID)

The XGATE channel ID register (Figure 9-4 ) shows the identiﬁer of the XGATE channel that is currently

active. This register will read “$00” if the XGATE module is idle. In debug mode this register can be used

to start and terminate threads (see Section 9.6.1, “Debug Features”).

Module Base +0x0002

XGCHID[6:0]

Reset

= Unimplemented or Reserved

Figure 9-4. XGATE Channel ID Register (XGCHID)

Read: Anytime

Write: In Debug Mode

Table 9-3. XGCHID Field Descriptions

Description

Field

6–0

Request Identiﬁer — ID of the currently active channel

XGCHID[6:0]

9.3.2.3

XGATE Vector Base Ad dress Register (XGVBR)

The vector base address register (Figure 9-5 and Figure 9-6) determines the location of the XGATE vector

block.

Module Base +0x0006

XGVBR[15:1]

Reset

= Unimplemented or Reserved

Figure 9-5. XGATE Vector Base Address Register (XGVBR)

Read: Anytime

Write: Only if the module is disabled (XGE = 0) and idle (XGCHID = $00))

Table 9-4. XGVBR Field Descriptions

Field

Description

Vector Base Address — The XGVBR register holds the start address of the vector block in the XGATE

15–1

XBVBR[15:1] memory map.

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Chapter 9 XGATE (S12XGATEV2)

9.3.2.4

XGATE Channel Interrupt Flag Vector (XGIF)

The interrupt ﬂag vector (Figure 9-6) provides access to the interrupt ﬂags bits of each channel. Each ﬂag

may be cleared by writing a "1" to its bit location.

Module Base +0x0008

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

XGIF_78 XGF_77 XGIF_76 XGIF_75 XGIF_74 XGIF_73 XGIF_72 XGIF_71 XGIF_70

Reset

111

110

109

108

107

106

105

104

103

102

101

100

XGIF_6F XGIF_6E XGIF_6D XGIF_6C XGIF_6B XGIF_6A XGIF_69 XGIF_68 XGF_67 XGIF_66 XGIF_65 XGIF_64 XGIF_63 XGIF_62 XGIF_61 XGIF_60

Reset

XGIF_5F XGIF_5E XGIF_5D XGIF_5C XGIF_5B XGIF_5A XGIF_59 XGIF_58 XGF_57 XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50

Reset

XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48 XGF _47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40

Reset

XGIF_3F XGIF_3E XGIF_3D XGIF_3C XGIF_3B XGIF_3A XGIF_39 XGIF_38 XGF _37 XGIF_36 XGIF_35 XGIF_34 XGIF_33 XGIF_32 XGIF_31 XGIF_30

Reset

XGIF_2F XGIF_2E XGIF_2D XGIF_2C XGIF_2B XGIF_2A XGIF_29 XGIF_28 XGF _27 XGIF_26 XGIF_25 XGIF_24 XGIF_23 XGIF_22 XGIF_21 XGIF_20

Reset

XGIF_1F XGIF_1E XGIF_1D XGIF_1C XGIF_1B XGIF_1A XGIF_19 XGIF_18 XGF _17 XGIF_16 XGIF_15 XGIF_14 XGIF_13 XGIF_12 XGIF_11 XGIF_10

Reset

XGIF_0F XGIF_0E XGIF_0D XGIF_0C XGIF_0B XGIF_0A XGIF_09

Reset

= Unimplemented or Reserved

Figure 9-6. XGATE Channel Interrupt Flag Vector (XGIF)

Read: Anytime

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Chapter 9 XGATE (S12XGATEV2)

Write: Anytime

Table 9-5. XGIV Field Descriptions

Description

Field

127–9

Channel Interrupt Flags — These bits signal pending channel interrupts. They can only be set by the RISC

XGIF[78:9]

core. Each ﬂag can be cleared by writing a "1" to its bit location. Unimplemented interrupt ﬂags will always read

"0". Refer to Section “Interrupts” of the SoC Guide for a list of implemented Interrupts.

Read:

0 Channel interrupt is not pending

1 Channel interrupt is pending if XGIE is set

Write:

0 No effect

1 Clears the interrupt ﬂag

NOTE

Suggested Mnemonics for accessing the interrupt ﬂag vector on a word

basis are:

XGIF_7F_70 (XGIF[127:112]),

XGIF_6F_60 (XGIF[111:96]),

XGIF_5F_50 (XGIF[95:80]),

XGIF_4F_40 (XGIF[79:64]),

XGIF_3F_30 (XGIF[63:48]),

XGIF_2F_20 (XGIF[47:32]),

XGIF_1F_10 (XGIF[31:16]),

XGIF_0F_00 (XGIF[15:0])

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Chapter 9 XGATE (S12XGATEV2)

9.3.2.5

XGATE Software Trigger Register (XGSWT)

The eight software triggers of the XGATE module can be set and cleared through the XGATE software

trigger register (Figure 9-7). The upper byte of this register, the software trigger mask, controls the write

access to the lower byte, the software trigger bits. These bits can be set or cleared if a "1" is written to the

associated mask in the same bus cycle.

Module Base +0x00018

XGSWT[7:0]

XGSWTM[7:0]

Reset

Figure 9-7. XGATE Software Trigger Register (XGSWT)

Read: Anytime

Write: Anytime

Table 9-6. XGSWT Field Descriptions

Description

Field

15–8

Software Trigger Mask — These bits control the write access to the XGSWT bits. Each XGSWT bit can only

XGSWTM[7:0] be written if a "1" is written to the corresponding XGSWTM bit in the same access.

Read:

These bits will always read "0".

Write:

0 Disable write access to the XGSWT in the same bus cycle

1 Enable write access to the corresponding XGSWT bit in the same bus cycle

7–0

Software Trigger Bits — These bits act as interrupt ﬂags that are able to trigger XGATE software channels.

XGSWT[7:0] They can only be set and cleared by software.

Read:

0 No software trigger pending

1 Software trigger pending if the XGIE bit is set

Write:

0 Clear Software Trigger

1 Set Software Trigger

NOTE

The XGATE channel IDs that are associated with the eight software triggers

are determined on chip integration level. (see Section “Interrupts” of the Soc

Guide)

XGATE software triggers work like any peripheral interrupt. They can be

used as XGATE requests as well as S12X_CPU interrupts. The target of the

software trigger must be selected in the S12X_INT module.

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Chapter 9 XGATE (S12XGATEV2)

9.3.2.6

XGATE Semaphore Register (XGSEM)

The XGATE provides a set of eight hardware semaphores that can be shared between the S12X_CPU and

the XGATE RISC core. Each semaphore can either be unlocked, locked by the S12X_CPU or locked by

the RISC core. The RISC core is able to lock and unlock a semaphore through its SSEM and CSEM

instructions. The S12X_CPU has access to the semaphores through the XGATE semaphore register

(Figure 9-8). Refer to section Section 9.4.4, “Semaphores” for details.

Module Base +0x0001A

XGSEM[7:0]

XGSEMM[7:0]

Reset

Figure 9-8. XGATE Semaphore Register (XGSEM)

Read: Anytime

Write: Anytime (see Section 9.4.4, “Semaphores”)

Table 9-7. XGSEM Field Descriptions

Field

Description

15–8

Semaphore Mask — These bits control the write access to the XGSEM bits.

XGSEMM[7:0] Read:

These bits will always read "0".

Write:

0 Disable write access to the XGSEM in the same bus cycle

1 Enable write access to the XGSEM in the same bus cycle

7–0

Semaphore Bits — These bits indicate whether a semaphore is locked by the S12X_CPU. A semaphore can

XGSEM[7:0] be attempted to be set by writing a "1" to the XGSEM bit and to the corresponding XGSEMM bit in the same

write access. Only unlocked semaphores can be set. A semaphore can be cleared by writing a "0" to the

XGSEM bit and a "1" to the corresponding XGSEMM bit in the same write access.

Read:

0 Semaphore is unlocked or locked by the RISC core

1 Semaphore is locked by the S12X_CPU

Write:

0 Clear semaphore if it was locked by the S12X_CPU

1 Attempt to lock semaphore by the S12X_CPU

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Chapter 9 XGATE (S12XGATEV2)

9.3.2.7

XGATE Condition Code Register (XGCCR)

The XGCCR register (Figure 9-9) provides access to the RISC core’s condition code register.

Module Base +0x001D

XGN

XGZ

XGV

XGC

Reset

= Unimplemented or Reserved

Figure 9-9. XGATE Condition Code Register (XGCCR)

Read: In debug mode if unsecured

Write: In debug mode if unsecured

Table 9-8. XGCCR Field Descriptions

Field

Description

XGN

Sign Flag — The RISC core’s Sign ﬂag

Zero Flag — The RISC core’s Zero ﬂag

XGZ

XGV

Overﬂow Flag — The RISC core’s Overﬂow ﬂag

Carry Flag — The RISC core’s Carry ﬂag

XGC

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Chapter 9 XGATE (S12XGATEV2)

9.3.2.8

XGATE Program Counter Register (XGPC)

The XGPC register (Figure 9-10) provides access to the RISC core’s program counter.

Module Base +0x0001E

XGPC

Reset

Figure 9-10. XGATE Program Counter Register (XGPC)

Figure 9-11.

Read: In debug mode if unsecured

Write: In debug mode if unsecured

Table 9-9. XGPC Field Descriptions

Description

Field

15–0

Program Counter — The RISC core’s program counter

XGPC[15:0]

9.3.2.9

XGATE Register 1 (XGR1)

The XGR1 register (Figure 9-12) provides access to the RISC core’s register 1.

Module Base +0x00022

XGR1

Reset

Figure 9-12. XGATE Register 1 (XGR1)

Read: In debug mode if unsecured

Write: In debug mode if unsecured

Table 9-10. XGR1 Field Descriptions

Field

Description

15–0

XGATE Register 1 — The RISC core’s register 1

XGR1[15:0]

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Chapter 9 XGATE (S12XGATEV2)

9.3.2.10 XGATE Register 2 (XGR2)

The XGR2 register (Figure 9-13) provides access to the RISC core’s register 2.

Module Base +0x00024

XGR2

Reset

Figure 9-13. XGATE Register 2 (XGR2)

Read: In debug mode if unsecured

Write: In debug mode if unsecured

Table 9-11. XGR2 Field Descriptions

Field

Description

15–0

XGATE Register 2 — The RISC core’s register 2

XGR2[15:0]

9.3.2.11 XGATE Register 3 (XGR3)

The XGR3 register (Figure 9-14) provides access to the RISC core’s register 3.

Module Base +0x00026

XGR3

Reset

Figure 9-14. XGATE Register 3 (XGR3)

Read: In debug mode if unsecured

Write: In debug mode if unsecured

Table 9-12. XGR3 Field Descriptions

Field

Description

15–0

XGATE Register 3 — The RISC core’s register 3

XGR3[15:0]

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Chapter 9 XGATE (S12XGATEV2)

9.3.2.12 XGATE Register 4 (XGR4)

The XGR4 register (Figure 9-15) provides access to the RISC core’s register 4.

Module Base +0x00028

XGR4

Reset

Figure 9-15. XGATE Register 4 (XGR4)

Read: In debug mode if unsecured

Write: In debug mode if unsecured

Table 9-13. XGR4 Field Descriptions

Field

Description

15–0

XGATE Register 4 — The RISC core’s register 4

XGR4[15:0]

9.3.2.13 XGATE Register 5 (XGR5)

The XGR5 register (Figure 9-16) provides access to the RISC core’s register 5.

Module Base +0x0002A

XGR5

Reset

Figure 9-16. XGATE Register 5 (XGR5)

Read: In debug mode if unsecured

Write: In debug mode if unsecured

Table 9-14. XGR5 Field Descriptions

Field

Description

15–0

XGATE Register 5 — The RISC core’s register 5

XGR5[15:0]

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Chapter 9 XGATE (S12XGATEV2)

9.3.2.14 XGATE Register 6 (XGR6)

The XGR6 register (Figure 9-17) provides access to the RISC core’s register 6.

Module Base +0x0002C

XGR6

Reset

Figure 9-17. XGATE Register 6 (XGR6)

Read: In debug mode if unsecured

Write: In debug mode if unsecured

Table 9-15. XGR6 Field Descriptions

Field

Description

15–0

XGATE Register 6 — The RISC core’s register 6

XGR6[15:0]

9.3.2.15 XGATE Register 7 (XGR7)

The XGR7 register (Figure 9-18) provides access to the RISC core’s register 7.

Module Base +0x0002E

XGR7

Reset

Figure 9-18. XGATE Register 7 (XGR7)

Read: In debug mode if unsecured

Write: In debug mode if unsecured

Table 9-16. XGR7 Field Descriptions

Field

Description

15–0

XGATE Register 7 — The RISC core’s register 7

XGR7[15:0]

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Chapter 9 XGATE (S12XGATEV2)

9.4

Functional Description

The core of the XGATE module is a RISC processor which is able to access the MCU’s internal memories

and peripherals (see Figure 9-1). The RISC processor always remains in an idle state until it is triggered

by an XGATE request. Then it executes a code sequence that is associated with the request and optionally

triggers an interrupt to the S12X_CPU upon completion. Code sequences are not interruptible. A new

XGATE request can only be serviced when the previous sequence is ﬁnished and the RISC core becomes

idle.

The XGATE module also provides a set of hardware semaphores which are necessary to ensure data

consistency whenever RAM locations or peripherals are shared with the S12X_CPU.

The following sections describe the components of the XGATE module in further detail.

9.4.1

XGATE RISC Core

The RISC core is a 16-bit processor with an instruction set that is well suited for data transfers, bit

manipulations, and simple arithmetic operations (see Section 9.8, “Instruction Set”).

It is able to access the MCU’s internal memories and peripherals without blocking these resources from

the S12X_CPU . Whenever the S12X_CPU and the RISC core access the same resource, the RISC core

will be stalled until the resource becomes available again .

The XGATE offers a high access rate to the MCU’s internal RAM. Depending on the bus load, the RISC

core can perform up to two RAM accesses per S12X_CPU bus cycle. A minimum throughput of one RAM

access per S12X_CPU bus cycle is guaranteed.

Bus accesses to peripheral registers or ﬂash are slower. A transfer rate of one bus access per S12X_CPU

cycle can not be exceeded.

The XGATE module is intended to execute short interrupt service routines that are triggered by peripheral

modules or by software.

1. With the exception of PRR registers (see Section “S12X_MMC”).

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Chapter 9 XGATE (S12XGATEV2)

9.4.2

Programmer’s Model

Program Counter

Condition

Code

N Z V C

(Variable Pointer)

R0 = 0

Figure 9-19. Programmer’s Model

The programmer’s model of the XGATE RISC core is shown in Figure 9-19. The processor offers a set of

seven general purpose registers (R1 - R7), which serve as accumulators and index registers. An additional

eighth register (R0) is tied to the value “$0000”. Register R1 has an additional functionality. It is preloaded

with the initial variable pointer of the channel’s service request vector (see Figure 9-20). The initial content

of the remaining general purpose registers is undeﬁned.

The 16 bit program counter allows the addressing of a 64 kbyte address space.

The condition code register contains four bits: the sign bit (S), the zero ﬂag (Z), the overﬂow ﬂag (V), and

the carry bit (C). The initial content of the condition code register is undeﬁned.

9.4.3

Memory Map

The XGATE’s RISC core is able to access an address space of 64K bytes. The allocation of memory blocks

within this address space is determined on chip level. Refer to the S12X_MMC Section for a detailed

information.

The XG A T E vector block assigns a start address and a v ariable pointer to each XG ATE channel. Its

position in the XGATE memory map can be adjusted through the XGVBR register (see Section 9.3.2.3,

“XGATE Vector Base Address Register (XGVBR)”). Figure 9-20 shows the layout of the vector block.

Each vector consists of two 16-bit words. The ﬁrst contains the start address of the service routine. This

value will be loaded into the program counter before a service routine is executed. The second word is a

pointer to the service routine’s variable space. This value will be loaded into register R1 before a service

routine is executed.

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Chapter 9 XGATE (S12XGATEV2)

XGVBR

+$0000

unused

Code

+$0024

Channel $09 Initial Program Counter

Channel $09 Initial Variable Pointer

Channel $0A Initial Program Counter

Channel $0A Initial Variable Pointer

Channel $0B Initial Program Counter

Channel $0B Initial Variable Pointer

Channel $0C Initial Program Counter

Channel $0C Initial Variable Pointer

+$0028

+$002C

+$0030

Variables

Code

+$01E0

Variables

Channel $78 Initial Program Counter

Channel $78 Initial Variable Pointer

Figure 9-20. XGATE Vector Block

9.4.4

Semaphores

The XGATE module offers a set of eight hardware semaphores. These semaphores provide a mechanism

to protect system resources that are shared between two concurrent threads of program execution; one

thread running on the S12X_CPU and one running on the XGATE RISC core.

Each semaphore can only be in one of the three states: “Unlocked”, “Locked by S12X_CPU”, and “Locked

by XGATE”. The S12X_CPU can check and change a semaphore’s state through the XGATE semaphore

this through its SSEM and CSEM instructions.

If the S12X_CPU and the RISC core attempt to lock an unlocked semaphore at the same time, it will be

locked by the S12X_CPU.

Figure 9-21 illustrates the valid state transitions.

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Chapter 9 XGATE (S12XGATEV2)

%1 ⇒ XGSEM

%0 ⇒ XGSEM

SSEM Instruction

CSEM Instruction

SSEM Instruction

LOCKED BY

XGATE

LOCKED BY

S12X_CPU

UNLOCKED

%0 ⇒ XGSEM

CSEM Instruction

Figure 9-21. Semaphore State Transitions

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Chapter 9 XGATE (S12XGATEV2)

Figure 9-22 gives an example of the typical usage of the XGATE hardware semaphores.

Two concurrent threads are running on the system. One is running on the S12X_CPU and the other is

running on the RISC core. They both have a critical section of code that accesses the same system resource.

To guarantee that the system resource is only accessed by one thread at a time, the critical code sequence

must be embedded in a semaphore lock/release sequence as shown.

S12X_CPU

XGATE

.........

%1 ⇒ XGSEMx

XGSEM ≡ %1?

SSEM

BCC?

critical

code

sequence

critical

code

sequence

XGSEM ⇒ %0

CSEM

.........

Figure 9-22. Algorithm for Locking and Releasing Semaphores

9.4.5

Software Error Detection

The XGATE module will immediately terminate program execution after detecting an error condition

caused by erratic application code. There are three error conditions:

•

Execution of an illegal opcode

Illegal vector or opcode fetches

Illegal load or store accesses

All opcodes which are not listed in section Section 9.8, “Instruction Set” are illegal opcodes. Illegal vector

and opcode fetches as well as illegal load and store accesses are deﬁned on chip level. Refer to the

S12X_MMC Section for a detailed information.

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Chapter 9 XGATE (S12XGATEV2)

9.5

Interrupts

9.5.1

Incoming Interrupt Requests

XGATE threads are triggered by interrupt requests which are routed to the XGATE module (see

S12X_INT Section). Only a subset of the MCU’s interrupt requests can be routed to the XGATE. Which

speciﬁc interrupt requests these are and which channel ID they are assigned to is documented in Section

“Interrupts” of the SoC Guide.

9.5.2

Outgoing Interrupt Requests

There are three types of interrupt requests which can be triggered by the XGATE module:

4. Channel interrupts

For each XGATE channel there is an associated interrupt ﬂag in the XGATE interrupt ﬂag vector

(XGIF, see Section 9.3.2.4, “XGATE Channel Interrupt Flag Vector (XGIF)”). These ﬂags can be

set through the "SIF" instruction by the RISC core. They are typically used to ﬂag an interrupt to

the S12X_CPU when the XGATE has completed one of its tasks.

5. Software triggers

Software triggers are interrupt ﬂags, which can be set and cleared by software (see Section 9.3.2.5,

“XGATE Software Trigger Register (XGSWT)”). They are typically used to trigger XGATE tasks

by the S12X_CPU software. However these interrupts can also be routed to the S12X_CPU (see

S12X_INT Section) and triggered by the XGATE software.

6. Software error interrupt

The software error interrupt signals to the S12X_CPU the detection of an error condition in the

XGATE application code (see Section 9.4.5, “Software Error Detection”).

All XGATE interrupts can be disabled by the XGIE bit in the XGATE module control register (XGMCTL,

see Section 9.3.2.1, “XGATE Control Register (XGMCTL)”).

9.6

Debug Mode

The XGATE debug mode is a feature to allow debugging of application code.

9.6.1

Debug Features

In debug mode the RISC core will be halted and the following debug features will be enabled:

•

Read and Write accesses to RISC core registers (XGCCR, XGPC, XGR1–XGR7)

All RISC core registers can be modified. Leaving debug mode will cause the RISC core to continue

program execution with the modified register values.

1. Only possible if MCU is unsecured

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Chapter 9 XGATE (S12XGATEV2)

•

Single Stepping

Writing a "1" to the XGSS bit will call the RISC core to execute a single instruction. All RISC core

registers will be updated accordingly.

Write accesses to the XGCHID register

Three operations can be performed by writing to the XGCHID register:

– Change of channel ID

If a non-zero value is written to the XGCHID while a thread is active (XGCHID ≠ $00), then

the current channel ID will be changed without any inﬂuence on the program counter or the

other RISC core registers.

– Start of a thread

If a non-zero value is written to the XGCHID while the XGATE is idle (XGCHID = $00),

then the thread that is associated with the new channel ID will be executed upon leaving

debug mode.

– Termination of a thread

If zero is written to the XGCHID while a thread is active (XGCHID ≠ $00), then the current

thread will be terminated and the XGATE will become idle.

9.6.2

Entering Debug Mode

Debug mode can be entered in four ways:

1. Setting XGDBG to "1"

Writing a "1" to XGDBG and XGDBGM in the same write access causes the XGATE to enter

debug mode upon completion of the current instruction.

NOTE

After writing to the XGDBG bit the XGATE will not immediately enter

debug mode. Depending on the instruction that is executed at this time there

may be a delay of several clock cycles. The XGDBG will read "0" until

debug mode is entered.

2. Software breakpoints

XGATE programs which are stored in the internal RAM allow the use of software breakpoints. A

software breakpoint is set by replacing an instruction of the program code with the "BRK"

instruction.

As soon as the program execution reaches the "BRK" instruction, the XGATE enters debug mode.

Additionally a software breakpoint request is sent to the S12X_DBG module (see section 4.9 of

the S12X_DBG Section).

Upon entering debug mode, the program counter will point to the "BRK" instruction. The other

RISC core registers will hold the result of the previous instruction.

To resume program execution, the "BRK" instruction must be replaced by the original instruction

before leaving debug mode.

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Chapter 9 XGATE (S12XGATEV2)

3. Tagged Breakpoints

The S12X_DBG module is able to place tags on fetched opcodes. The XGATE is able to enter

debug mode right before a tagged opcode is executed (see section 4.9 of the S12X_DBG Section).

Upon entering debug mode, the program counter will point to the tagged instruction. The other

RISC core registers will hold the result of the previous instruction.

4. Forced Breakpoints

Forced breakpoints are triggered by the S12X_DBG module (see section 4.9 of the S12X_DBG

Section). When a forced breakpoint occurs, the XGATE will enter debug mode upon completion

of the current instruction.

9.6.3

Leaving Debug Mode

Debug mode can only be left by setting the XGDBG bit to "0". If a thread is active (XGCHID has not been

cleared in debug mode), program execution will resume at the value of XGPC.

9.7

Security

In order to protect XGATE application code on secured S12X devices, a few restrictions in the debug

features have been made. These are:

•

Registers XGCCR, XGPC, and XGR1–XGR7 will read zero on a secured device

Registers XGCCR, XGPC, and XGR1–XGR7 can not be written on a secured device

Single stepping is not possible on a secured device

9.8

Instruction Set

9.8.1

Addressing Modes

For the ease of implementation the architecture is a strict Load/Store RISC machine, which means all

operations must have one of the eight general purpose registers R0 … R7 as their source as well their

destination.

All word accesses must work with a word aligned address, that is A[0] = 0!

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Chapter 9 XGATE (S12XGATEV2)

9.8.1.1

Naming Conventions

Destination register, allowed range is R0–R7

Low byte of the destination register, bits [7:0]

High byte of the destination register, bits [15:8]

Source register, allowed range is R0–R7

Low byte of the source register, bits [7:0]

High byte of the source register, bits[15:8]

RD.L

RD.H

RS, RS1, RS2

RS.L, RS1.L, RS2.L

RS.H, RS1.H, RS2.H

Base register for indexed addressing modes, allowed

range is R0–R7

Offset register for indexed addressing modes with

RI+

Offset register for indexed addressing modes with

Allowed range is R0–R7 (R0+ is equivalent to R0)

–RI

Offset register for indexed addressing modes with

Allowed range is R0–R7 (–R0 is equivalent to R0)

NOTE

Even though register R1 is intended to be used as a pointer to the variable

segment, it may be used as a general purpose data register as well.

Selecting R0 as destination register will discard the result of the instruction.

Only the condition code register will be updated

9.8.1.2

Inherent Addressing Mode (INH)

Instructions that use this addressing mode either have no operands or all operands are in internal XGATE

registers:.

Examples

BRK

RTS

9.8.1.3

Immediate 3-Bit Wide (IMM3)

Operands for immediate mode instructions are included in the instruction stream and are fetched into the

instruction queue along with the rest of the 16 Bit instruction. The ’#’ symbol is used to indicate an

immediate addressing mode operand. This address mode is used for semaphore instructions.

Examples:

CSEM

SSEM

; Unlock semaphore 1

; Lock Semaphore 3

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Chapter 9 XGATE (S12XGATEV2)

9.8.1.4

Immediate 4-Bit Wide (IMM4)

The 4-bit wide immediate addressing mode is supported by all shift instructions.

RD = RD ∗ imm4

Examples:

LSL

LSR

R4,#1

R4,#3

; R4 = R4 << 1; shift register R4 by 1 bit to the left

; R4 = R4 >> 3; shift register R4 by 3 bits to the right

9.8.1.5

Immediate 8-Bit Wide (IMM8)

The 8-bit wide immediate addressing mode is supported by four major commands (ADD, SUB, LD,

CMP).

RD = RD ∗ imm8

Examples:

ADDL

SUBL

LDH

R1,#1

R2,#2

R3,#3

R4,#4

; adds an 8 Bit value to register R1

; subtracts an 8 Bit value from register R2

; loads an 8 bit immediate into the high byte of Register R3

; compares the low byte of register R4 with an immediate value

CMPL

9.8.1.6

Immediate 16-Bit Wide (IMM16)

The 16-bit wide immediate addressing mode is a construct to simplify assembler code. Instructions which

offer this mode are translated into two opcodes using the eight bit wide immediate addressing mode.

RD = RD ∗ imm16

Examples:

LDW

ADD

R4,#$1234

R4,#$5678

; translated to LDL R4,#$34; LDH R4,#$12

; translated to ADDL R4,#$78; ADDH R4,#$56

9.8.1.7

Monadic Addressing (MON)

In this addressing mode only one operand is explicitly given. This operand can either be the source (f(RD)),

the target (RD = f()), or both source and target of the operation (RD = f(RD)).

Examples:

JAL

SIF

; PC = R1, R1 = PC+2

; Trigger IRQ associated with the channel number in R2.L

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Chapter 9 XGATE (S12XGATEV2)

9.8.1.8

Dyadic Addressing (DYA)

In this mode the result of an operation between two registers is stored in one of the registers used as

operands.

RD = RD ∗ RS is the general register to register format, with register RD being the ﬁrst operand and RS

the second. RD and RS can be any of the 8 general purpose registers R0 … R7. If R0 is used as the

destination register, only the condition code ﬂags are updated. This addressing mode is used only for shift

operations with a variable shift value

Examples:

LSL

LSR

R4,R5

; R4 = R4 << R5

; R4 = R4 >> R5

9.8.1.9

Triadic Addressing (TRI)

In this mode the result of an operation between two or three registers is stored into a third one.

RD = RS1 ∗ RS2 is the general format used in the order RD, RS1, RS1. RD, RS1, RS2 can be any of the

8 general purpose registers R0 … R7. If R0 is used as the destination register RD, only the condition code

ﬂags are updated. This addressing mode is used for all arithmetic and logical operations.

Examples:

ADC

SUB

R5,R6,R7

; R5 = R6 + R7 + Carry

; R5 = R6 - R7

9.8.1.10 Relative Addressing 9-Bit Wide (REL9)

A 9-bit signed word address offset is included in the instruction word. This addressing mode is used for

conditional branch instructions.

Examples:

BCC

BEQ

REL9

; PC = PC + 2 + (REL9 << 1)

9.8.1.11 Relative Addressing 10-Bit Wide (REL10)

An 11-bit signed word address offset is included in the instruction word. This addressing mode is used for

the unconditional branch instruction.

Examples:

BRA

REL10

; PC = PC + 2 + (REL10 << 1)

9.8.1.12 Index Register plus Immediate Offset (IDO5)

(RS, #offset5) provides an unsigned offset from the base register.

Examples:

LDB

STW

R4,(R1,#offset) ; loads a byte from R1+offset into R4

R4,(R1,#offset) ; stores R4 as a word to R1+offset

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Chapter 9 XGATE (S12XGATEV2)

9.8.1.13 Index Register plus Register Offset (IDR)

For load and store instructions (RS, RI) provides a variable offset in a register.

Examples:

LDB

STW

R4,(R1,R2)

; loads a byte from R1+R2 into R4

; stores R4 as a word to R1+R2

9.8.1.14 Index Register plus Register Offset with Post-increment (IDR+)

[RS, RI+] provides a variable offset in a register, which is incremented after accessing the memory. In case

of a byte access the index register will be incremented by one. In case of a word access it will be

incremented by two.

Examples:

LDB

STW

R4,(R1,R2+)

; loads a byte from R1+R2 into R4, R2+=1

; stores R4 as a word to R1+R2, R2+=2

9.8.1.15 Index Register plus Register Offset with Pre-decrement (–IDR)

[RS, -RI] provides a variable offset in a register, which is decremented before accessing the memory. In

case of a byte access the index register will be decremented by one. In case of a word access it will be

decremented by two.

Examples:

LDB

STW

R4,(R1,-R2)

; R2 -=1, loads a byte from R1+R2 into R4

; R2 -=2, stores R4 as a word to R1+R2

9.8.2

Instruction Summary and Usage

Load & Store Instructions

9.8.2.1

Any register can be loaded either with an immediate or from the address space using indexed addressing

modes.

LDL

LDW

RD,#IMM8

RD,(RB,RI)

; loads an immediate 8 bit value to the lower byte of RD

; loads data using RB+RI as effective address

LDB

RD,(RB, RI+)

; loads data using RB+RI as effective address

; followed by an increment of RI depending on

; the size of the operation

The same set of modes is available for the store instructions

STB

RS,(RB, RI)

; stores data using RB+RI as effective address

STW

RS,(RB, RI+)

; stores data using RB+RI as effective address

; followed by an increment of RI depending on

; the size of the operation.

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Chapter 9 XGATE (S12XGATEV2)

9.8.2.2

Logic and Arithmetic Instructions

All logic and arithmetic instructions support the 8-bit immediate addressing mode (IMM8: RD = RD ∗

#IMM8) and the triadic addressing mode (TRI: RD = RS1 ∗ RS2).

All arithmetic is considered as signed, sign, overﬂow, zero and carry ﬂag will be updated. The carry will

not be affected for logical operations.

ADDL

ANDH

R2,#1

R4,#$FE

; increment R2

; R4.H = R4.H & $FE, clear lower bit of higher byte

ADD

SUB

R3,R4,R5

; R3 = R4 + R5

; R3 = R4 - R5

AND

R3,R4,R5

; R3 = R4 & R5 logical AND on the whole word

; R3 = R4 | R5

9.8.2.3

This group comprises transfers from and to some special registers

TFR

R3,CCR

; transfers the condition code register to the low byte of

; register R3

Branch Instructions

The branch offset is +255 words or -256 words counted from the beginning of the next instruction. Since

instructions have a ﬁxed 16 bit width, the branch offsets are word aligned by shifting the offset value by 2.

BEQ

label

; if Z flag = 1 branch to label

An unconditional branch allows a +511 words or -512 words branch distance.

BRA

label

9.8.2.4

Shift Instructions

Shift operations allow the use of a 4 bit wide immediate value to identify a shift width within a 16 bit word.

For shift operations a value of 0 does not shift at all, while a value of 15 shifts the register RD by 15 bits.

In a second form the shift value is contained in the bits 3:0 of the register RS.

Examples:

LSL

LSR

ASR

R4,#1

R4,#3

R4,R2

; R4 = R4 << 1; shift register R4 by 1 bit to the left

; R4 = R4 >> 3; shift register R4 by 3 bits to the right

; R4 = R4 >> R2;arithmetic shift register R4 right by the amount

;

of bits contained in R2[3:0].

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Chapter 9 XGATE (S12XGATEV2)

9.8.2.5

Bit Field Operations

This addressing mode is used to identify the position and size of a bit ﬁeld for insertion or extraction. The

width and offset are coded in the lower byte of the source register 2, RS2. The content of the upper byte is

ignored. An offset of 0 denotes the right most position and a width of 0 denotes 1 bit. These instructions

are very useful to extract, insert, clear, set or toggle portions of a 16 bit word.

RS2

RS1

W4=3, O4=2

Bit Field Extract

Bit Field Insert

Figure 9-23. Bit Field Addressing

BFEXT

R3,R4,R5 ; R5: W4 bits offset O4, will be extracted from R4 into R3

9.8.2.6

Special Instructions for DMA Usage

The XGATE offers a number of additional instructions for ﬂag manipulation, program ﬂow control and

debugging:

1. SIF: Set a channel interrupt flag

2. SSEM: Test and set a hardware semaphore

3. CSEM: Clear a hardware semaphore

4. BRK: Software breakpoint

5. NOP: No Operation

6. RTS: Terminate the current thread

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Chapter 9 XGATE (S12XGATEV2)

9.8.3

Cycle Notation

Table 9-17 show the XGATE access detail notation. Each code letter equals one XGATE cycle. Each letter

implies additional wait cycles if memories or peripherals are not accessible. Memories or peripherals are

not accessible if they are blocked by the S12X_CPU. In addition to this Peripherals are only accessible

every other XGATE cycle. Uppercase letters denote 16-bit operations. Lowercase letters denote 8-bit

operations. The XGATE is able to perform two bus or wait cycles per S12X_CPU cycle.

Table 9-17. Access Detail Notation

V— Vector fetch: always an aligned word read, lasts for at least one RISC core cycle

P— Program word fetch: always an aligned word read, lasts for at least one RISC core cycle

r— 8-bit data read: lasts for at least one RISC core cycle

R— 16-bit data read: lasts for at least one RISC core cycle

w— 8-bit data write: lasts for at least one RISC core cycle

W— 16-bit data write: lasts for at least one RISC core cycle

A— Alignment cycle: no read or write, lasts for zero or one RISC core cycles

f— Free cycle: no read or write, lasts for one RISC core cycles

Special Cases

PP/P— Branch: PPif branch taken, Pif not

9.8.4

Thread Execution

When the RISC core is triggered by an interrupt request (see Figure 9-1) it ﬁrst executes a vector fetch

sequence which performs three bus accesses:

1. A V-cycle to fetch the initial content of the program counter.

2. A V-cycle to fetch the initial content of the data segment pointer (R1).

3. A P-cycle to load the initial opcode.

Afterwards a sequence of instructions (thread) is executed which is terminated by an "RTS" instruction. If

further interrupt requests are pending after a thread has been terminated, a new vector fetch will be

performed. Otherwise the RISC core will idle until a new interrupt request is received. A thread can not be

interrupted by an interrupt request.

9.8.5

Instruction Glossary

This section describes the XGATE instruction set in alphabetical order.

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Chapter 9 XGATE (S12XGATEV2)

Add with Carry

ADC

Operation

RS1 + RS2 + C ⇒ RD

Adds the content of register RS1, the content of register RS2 and the value of the Carry bit using binary

addition and stores the result in the destination register RD. The Zero Flag is also carried forward from the

previous operation allowing 32 and more bit additions.

Example:

ADC

BCC

R6,R2,R2

R7,R3,R3 ; R7:R6 = R5:R4 + R3:R2

; conditional branch on 32 bit addition

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000 and Z was set before this operation; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the operation; cleared otherwise.

RS1[15] & RS2[15] & RD[15]

| RS1[15] & RS2[15] & RD[15]

new

C: Set if there is a carry from bit 15 of the result; cleared otherwise.

RS1[15] & RS2[15] | RS1[15] & RD[15]

| RS2[15] & RD[15]

new

Code and CPU Cycles

Address

Mode

Source Form

ADC RD, RS1, RS2

Machine Code

RD RS1

Cycles

TRI

RS2

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Chapter 9 XGATE (S12XGATEV2)

Add without Carry

ADD

Operation

RS1 + RS2 ⇒ RDRD + IMM16 ⇒ RD (translates to ADDL RD, #IMM16[7:0]; ADDH RD, #[15:8])

Performs a 16-bit addition and stores the result in the destination register RD.

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the operation; cleared otherwise.

RS1[15] & RS2[15] & RD[15]

| RS1[15] & RS2[15] & RD[15]

new

RD[15] & IMM16[15] & RD[15]

| RD[15] & IMM16[15] & RD[15]

old new

old

new

C: Set if there is a carry from bit 15 of the result; cleared otherwise.

RS1[15] & RS2[15] | RS1[15] & RD[15]

| RS2[15] & RD[15]

new

RD[15] & IMM16[15] | RD[15] & RD[15]

| IMM16[15] & RD[15]

new

old

new

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

ADD RD, RS1, RS2

ADD RD, #IMM16

TRI

RS1

RS2

IMM8

IMM16[7:0]

IMM16[15:8]

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Chapter 9 XGATE (S12XGATEV2)

Add Immediate 8-Bit Constant

(High Byte)

ADDH

Operation

RD + IMM8:$00 ⇒ RD

Adds the content of high byte of register RD and a signed immediate 8-Bit constant using binary addition

and stores the result in the high byte of the destination register RD. This instruction can be used after an

ADDL for a 16-bit immediate addition.

Example:

ADDL

ADDH

R2,#LOWBYTE

R2,#HIGHBYTE

; R2 = R2 + 16 Bit immediate

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the operation; cleared otherwise.

RD[15] & IMM8[7] & RD[15]

| RD[15] & IMM8[7] & RD[15]

old

new

old new

C: Set if there is a carry from the bit 15 of the result; cleared otherwise.

RD[15] & IMM8[7] | RD[15] & RD[15]

| IMM8[7] & RD[15]

old

new

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

ADDH RD, #IMM8

IMM8

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Chapter 9 XGATE (S12XGATEV2)

Add Immediate 8-Bit Constant

(Low Byte)

ADDL

Operation

RD + $00:IMM8 ⇒ RD

Adds the content of register RD and an unsigned immediate 8-Bit constant using binary addition and stores

the result in the destination register RD. This instruction must be used ﬁrst for a 16-bit immediate addition

in conjunction with the ADDH instruction.

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the 8-bit operation; cleared otherwise.

RD[15] & RD[15]

old

new

C: Set if there is a carry from bit 7 to bit 8 of the result; cleared otherwise.

RD[15] & RD[15]

old

new

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

ADDL RD, #IMM8

IMM8

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Chapter 9 XGATE (S12XGATEV2)

Logical AND

AND

Operation

RS1 & RS2 ⇒ RDRD & IMM16 ⇒ RD (translates to ANDL RD, #IMM[7:0]; ANDH RD,

#IMM16[15:8])

Performs a bit wise logical AND of two 16-bit values and stores the result in the destination register RD.

Remark: There is no complement to the BITH and BITL functions. This can be imitated by using R0 as a

destination register. AND R0, RS1, RS2 performs a bit wise test without storing a result.

CCR Effects

∆

—

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

AND RD, RS1, RS2

AND RD, #IMM16

TRI

RS1

RS2

IMM8

IMM16[7:0]

IMM16[15:8]

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Chapter 9 XGATE (S12XGATEV2)

Logical AND Immediate 8-Bit Constant

(High Byte)

ANDH

Operation

RD.H & IMM8 ⇒ RD.H

Performs a bit wise logical AND between the high byte of register RD and an immediate 8-Bit constant

and stores the result in the destination register RD.H. The low byte of RD is not affected.

CCR Effects

∆

—

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the 8-bit result is $00; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

ANDH RD, #IMM8

IMM8

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Chapter 9 XGATE (S12XGATEV2)

Logical AND Immediate 8-Bit Constant

(Low Byte)

ANDL

Operation

RD.L & IMM8 ⇒ RD.L

Performs a bit wise logical AND between the low byte of register RD and an immediate 8-Bit constant and

stores the result in the destination register RD.L. The high byte of RD is not affected.

CCR Effects

∆

—

N: Set if bit 7 of the result is set; cleared otherwise.

Z: Set if the 8-Bit result is $00; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

ANDL RD, #IMM8

IMM8

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Chapter 9 XGATE (S12XGATEV2)

Arithmetic Shift Right

ASR

Operation

b15

n = RS or IMM4

Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become ﬁlled

with the sign bit (RD[15]). The carry ﬂag will be updated to the bit contained in RD[n-1] before the shift

for n > 0.

n can range from 0 to 16.

In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is

equal to 0.

In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS

is greater than 15.

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the operation; cleared otherwise.

RD[15] ^ RD[15]

old

new

C: Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

ASR RD, #IMM4

ASR RD, RS

IMM4

DYA

IMM4

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Chapter 9 XGATE (S12XGATEV2)

Branch if Carry Cleared

(Same as BHS)

BCC

Operation

If C = 0, then PC + $0002 + (REL9 << 1) ⇒ PC

Tests the Carry ﬂag and branches if C = 0.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

BCC REL9

REL9

PP/P

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Chapter 9 XGATE (S12XGATEV2)

Branch if Carry Set

(Same as BLO)

BCS

Operation

If C = 1, then PC + $0002 + (REL9 << 1) ⇒ PC

Tests the Carry ﬂag and branches if C = 1.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

BCS REL9

REL9

PP/P

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Chapter 9 XGATE (S12XGATEV2)

Branch if Equal

BEQ

Operation

If Z = 1, then PC + $0002 + (REL9 << 1) ⇒ PC

Tests the Zero ﬂag and branches if Z = 1.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

BEQ REL9

REL9

PP/P

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Chapter 9 XGATE (S12XGATEV2)

Bit Field Extract

BFEXT

Operation

RS1[(o+w):o] ⇒ RD[w:0]; 0 ⇒ RD[15:(w+1)]

w = (RS2[7:4])

o = (RS2[3:0])

Extracts w+1 bits from register RS1 starting at position o and writes them right aligned into register RD.

The remaining bits in RD will be cleared. If (o+w) > 15 only bits [15:o] get extracted.

RS2

RS1

W4=3, O4=2

Bit Field Extract

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

RD RS1

Cycles

BFEXT RD, RS1, RS2

TRI

RS2

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Chapter 9 XGATE (S12XGATEV2)

Bit Field Find First One

BFFO

Operation

FirstOne (RS) ⇒ RD;

Searches the ﬁrst “1” beginning from the MSB=15 down to LSB=0 in register RS and places the result into

the destination register RD. The upper bits of RD are cleared. In case the content of RS is equal to $0000,

RD will be cleared and the carry ﬂag will be set. This is used to distinguish a “1” in position 0 versus no

“1” in the whole RS register at all.

CCR Effects

∆

N: 0; cleared.

Z: Set if the result is $0000; cleared otherwise.

V: 0; cleared.

C: Set if RS = $0000 ; cleared otherwise.

Before executing the instruction

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

RD RS

Cycles

BFFO RD, RS

DYA

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Chapter 9 XGATE (S12XGATEV2)

Bit Field Insert

BFINS

Operation

RS1[w:0] ⇒ RD[(w+o):o];

w = (RS2[7:4])

o = (RS2[3:0])

Extracts w+1 bits from register RS1 starting at position 0 and writes them into register RD at position o.

The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0 as a RS1,

this command can be used to clear bits.

RS2

RS1

Bit Field Insert

W4=3, O4=2

CCR Effects

∆

—

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

RD RS1

Cycles

BFINS RD, RS1, RS2

TRI

RS2

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Chapter 9 XGATE (S12XGATEV2)

Bit Field Insert and Invert

BFINSI

Operation

!RS1[w:0] ⇒ RD[w+o:o];

w = (RS2[7:4])

o = (RS2[3:0])

Extracts w+1 bits from register RS1 starting at position 0, inverts them and writes into register RD at

position o. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0

as a RS1, this command can be used to set bits.

RS2

RS1

Inverted Bit Field Insert

W4=3, O4=2

CCR Effects

∆

—

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

RD RS1

Cycles

BFINSI RD, RS1, RS2

TRI

RS2

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Chapter 9 XGATE (S12XGATEV2)

Bit Field Insert and XNOR

BFINSX

Operation

!(RS1[w:0] ^ RD[w+o:o]) ⇒ RD[w+o:o];

w = (RS2[7:4])

o = (RS2[3:0])

Extracts w+1 bits from register RS1 starting at position 0, performs an XNOR with RD[w+o:o] and writes

the bits back. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using

R0 as a RS1, this command can be used to toggle bits.

RS2

RS1

Bit Field Insert XNOR

W4=3, O4=2

CCR Effects

∆

—

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

RD RS1

Cycles

BFINSX RD, RS1, RS2

TRI

RS2

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Chapter 9 XGATE (S12XGATEV2)

Branch if Greater than or Equal to Zero

BGE

Operation

If N ^ V = 0, then PC + $0002 + (REL9 << 1) ⇒ PC

Branch instruction to compare signed numbers.

Branch if RS1 ≥ RS2:

SUB

R0,RS1,RS2

BGE

REL9

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

BGE REL9

REL9

PP/P

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Chapter 9 XGATE (S12XGATEV2)

Branch if Greater than Zero

BGT

Operation

If Z | (N ^ V) = 0, then PC + $0002 + (REL9 << 1) ⇒ PC

Branch instruction to compare signed numbers.

Branch if RS1 > RS2:

SUB

R0,RS1,RS2

BGE

REL9

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

BGT REL9

REL9

PP/P

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Chapter 9 XGATE (S12XGATEV2)

Branch if Higher

BHI

Operation

If C | Z = 0, then PC + $0002 + (REL9 << 1) ⇒ PC

Branch instruction to compare unsigned numbers.

Branch if RS1 > RS2:

SUB

R0,RS1,RS2

BHI

REL9

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

BHI REL9

REL9

PP/P

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Chapter 9 XGATE (S12XGATEV2)

Branch if Higher or Same

(Same as BCC)

BHS

Operation

If C = 0, then PC + $0002 + (REL9 << 1) ⇒ PC

Branch instruction to compare unsigned numbers.

Branch if RS1 ≥ RS2:

SUB

R0,RS1,RS2

BHS

REL9

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

BHS REL9

REL9

PP/P

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Chapter 9 XGATE (S12XGATEV2)

Bit Test Immediate 8-Bit Constant

(High Byte)

BITH

Operation

RD.H & IMM8 ⇒ NONE

Performs a bit wise logical AND between the high byte of register RD and an immediate 8-Bit constant.

Only the condition code ﬂags get updated, but no result is written back

CCR Effects

∆

—

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the 8-bit result is $00; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

BITH RD, #IMM8

IMM8

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Chapter 9 XGATE (S12XGATEV2)

Bit Test Immediate 8-Bit Constant

(Low Byte)

BITL

Operation

RD.L & IMM8 ⇒ NONE

Performs a bit wise logical AND between the low byte of register RD and an immediate 8-Bit constant.

Only the condition code ﬂags get updated, but no result is written back.

CCR Effects

∆

—

N: Set if bit 7 of the result is set; cleared otherwise.

Z: Set if the 8-bit result is $00; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

BITL RD, #IMM8

IMM8

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Chapter 9 XGATE (S12XGATEV2)

Branch if Less or Equal to Zero

BLE

Operation

If Z | (N ^ V) = 1, then PC + $0002 + (REL9 << 1) ⇒ PC

Branch instruction to compare signed numbers.

Branch if RS1 ≤ RS2:

SUB

R0,RS1,RS2

BLE

REL9

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

BLE REL9

REL9

PP/P

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Chapter 9 XGATE (S12XGATEV2)

Branch if Carry Set

(Same as BCS)

BLO

Operation

If C = 1, then PC + $0002 + (REL9 << 1) ⇒ PC

Branch instruction to compare unsigned numbers.

Branch if RS1 < RS2:

SUB

R0,RS1,RS2

BLO

REL9

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

BLO REL9

REL9

PP/P

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Chapter 9 XGATE (S12XGATEV2)

Branch if Lower or Same

BLS

Operation

If C | Z = 1, then PC + $0002 + (REL9 << 1) ⇒ PC

Branch instruction to compare unsigned numbers.

Branch if RS1 ≤ RS2:

SUB

R0,RS1,RS2

BLS

REL9

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

BLS REL9

REL9

PP/P

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Chapter 9 XGATE (S12XGATEV2)

Branch if Lower than Zero

BLT

Operation

If N ^ V = 1, then PC + $0002 + (REL9 << 1) ⇒ PC

Branch instruction to compare signed numbers.

Branch if RS1 < RS2:

SUB

R0,RS1,RS2

BLT

REL9

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

BLT REL9

REL9

PP/P

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Chapter 9 XGATE (S12XGATEV2)

Branch if Minus

BMI

Operation

If N = 1, then PC + $0002 + (REL9 << 1) ⇒ PC

Tests the Sign ﬂag and branches if N = 1.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

BMI REL9

REL9

PP/P

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Chapter 9 XGATE (S12XGATEV2)

Branch if Not Equal

BNE

Operation

If Z = 0, then PC + $0002 + (REL9 << 1) ⇒ PC

Tests the Zero ﬂag and branches if Z = 0.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

BNE REL9

REL9

PP/P

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Chapter 9 XGATE (S12XGATEV2)

Branch if Plus

BPL

Operation

If N = 0, then PC + $0002 + (REL9 << 1) ⇒ PC

Tests the Sign ﬂag and branches if N = 0.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

BPL REL9

REL9

PP/P

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Chapter 9 XGATE (S12XGATEV2)

Branch Always

BRA

Operation

PC + $0002 + (REL10 << 1) ⇒ PC

Branches always

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

BRA REL10

REL10

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Chapter 9 XGATE (S12XGATEV2)

Break

BRK

Operation

Put XGATE into Debug Mode (see Section 9.6.2, “Entering Debug Mode”)and signals a Software

breakpoint to the S12X_DBG module (see section 4.9 of the S12X_DBG Section).

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

BRK

INH

PAff

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Chapter 9 XGATE (S12XGATEV2)

Branch if Overflow Cleared

BVC

Operation

If V = 0, then PC + $0002 + (REL9 << 1) ⇒ PC

Tests the Overﬂow ﬂag and branches if V = 0.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

BVC REL9

REL9

PP/P

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Chapter 9 XGATE (S12XGATEV2)

Branch if Overflow Set

BVS

Operation

If V = 1, then PC + $0002 + (REL9 << 1) ⇒ PC

Tests the Overﬂow ﬂag and branches if V = 1.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

BVS REL9

REL9

PP/P

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Chapter 9 XGATE (S12XGATEV2)

Compare

CMP

Operation

RS2 – RS1 ⇒ NONE (translates to SUB R0, RS1, RS2)

RD – IMM16 ⇒ NONE (translates to CMPL RD, #IMM16[7:0]; CPCH RD, #IMM16[15:8])

Subtracts two 16-bit values and discards the result.

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the operation; cleared otherwise.

RS1[15] & RS2[15] & result[15] | RS1[15] & RS2[15] & result[15]

RD[15] & IMM16[15] & result[15] | RD[15] & IMM16[15] & result[15]

C: Set if there is a carry from the bit 15 of the result; cleared otherwise.

RS1[15] & RS2[15] | RS1[15] & result[15] | RS2[15] & result[15]

RD[15] & IMM16[15] | RD[15] & result[15] | IMM16[15] & result[15]

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

CMP RS1, RS2

CMP RS, #IMM16

TRI

RS1

RS2

IMM8

IMM16[7:0]

IMM16[15:8]

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Chapter 9 XGATE (S12XGATEV2)

Compare Immediate 8-Bit Constant

(Low Byte)

CMPL

Operation

RS.L – IMM8 ⇒ NONE, only condition code ﬂags get updated

Subtracts the 8-Bit constant IMM8 contained in the instruction code from the low byte of the source

Remark: There is no equivalent operation using triadic addressing. Comparing the values of two registers

can be performed by using the subtract instruction with R0 as destination register.

CCR Effects

∆

N: Set if bit 7 of the result is set; cleared otherwise.

Z: Set if the 8-bit result is $00; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the 8-bit operation; cleared otherwise.

RS[7] & IMM8[7] & result[7] | RS[7] & IMM8[7] & result[7]

C: Set if there is a carry from the Bit 7 to Bit 8 of the result; cleared otherwise.

RS[7] & IMM8[7] | RS[7] & result[7] | IMM8[7] & result[7]

Code and CPU Cycles

Address

Mode

Source Form

CMPL RS, #IMM8

Machine Code

Cycles

IMM8

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Chapter 9 XGATE (S12XGATEV2)

One’s Complement

COM

Operation

~RS ⇒ RD (translates to XNOR RD, R0, RS)

~RD ⇒ RD (translates to XNOR RD, R0, RD)

Performs a one’s complement on a general purpose register.

CCR Effects

∆

—

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

COM RD, RS

COM RD

TRI

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Chapter 9 XGATE (S12XGATEV2)

Compare with Carry

CPC

Operation

RS2 – RS1 − Χ ⇒ NONE (translates to SBC R0, RS1, RS2)

Subtracts the carry bit and the content of register RS2 from the content of register RS1 using binary

subtraction and discards the result.

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the operation; cleared otherwise.

RS1[15] & RS2[15] & result[15] | RS1[15] & RS2[15] & result[15]

C: Set if there is a carry from the bit 15 of the result; cleared otherwise.

RS1[15] & RS2[15] | RS1[15] & result[15] | RS2[15] & result[15]

Code and CPU Cycles

Address

Mode

Source Form

CPC RS1, RS2

Machine Code

RS1

Cycles

TRI

RS2

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Chapter 9 XGATE (S12XGATEV2)

Compare Immediate 8-Bit Constant with

Carry (High Byte)

CPCH

Operation

RS.H - IMM8 - C ⇒ NONE, only condition code ﬂags get updated

Subtracts the carry bit and the 8-Bit constant IMM8 contained in the instruction code from the high byte

of the source register RD using binary subtraction and updates the condition code register accordingly. The

carry bit and Zero bits are taken into account to allow a 16-Bit compare in the form of

CMPL

CPCH

BCC

R2,#LOWBYTE

R2,#HIGHBYTE

; branch condition

Remark: There is no equivalent operation using triadic addressing. Comparing the values of two registers

can be performed by using the subtract instruction with R0 as destination register.

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $00 and Z was set before this operation; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the operation; cleared otherwise.

RS[15] & IMM8[7] & result[15] | RS[15] & IMM8[7] & result[15]

C: Set if there is a carry from the bit 15 of the result; cleared otherwise.

RS[15] & IMM8[7] | RS[15] & result[15] | IMM8[7] & result[15]

Code and CPU Cycles

Address

Mode

Source Form

CPCH RD, #IMM8

Machine Code

Cycles

IMM8

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Chapter 9 XGATE (S12XGATEV2)

Clear Semaphore

CSEM

Operation

Unlocks a semaphore that was locked by the RISC core.

In monadic address mode, bits RS[2:0] select the semaphore to be cleared.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

CSEM #IMM3

CSEM RS

IMM3

MON

IMM3

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Chapter 9 XGATE (S12XGATEV2)

Logical Shift Left with Carry

CSL

Operation

n bits

n = RS or IMM4

Shifts the bits in register RD n positions to the left. The lower n bits of the register RD become ﬁlled with

the carry ﬂag. The carry ﬂag will be updated to the bit contained in RD[16-n] before the shift for n > 0.

n can range from 0 to 16.

In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is

equal to 0.

In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS

is greater than 15.

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the operation; cleared otherwise.

RD[15] ^ RD[15]

old

new

C: Set if n > 0 and RD[16-n] = 1; if n = 0 unaffected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

CSL RD, #IMM4

CSL RD, RS

IMM4

DYA

IMM4

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Chapter 9 XGATE (S12XGATEV2)

Logical Shift Right with Carry

CSR

Operation

n bits

n = RS or IMM4

Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become ﬁlled

with the carry ﬂag. The carry ﬂag will be updated to the bit contained in RD[n-1] before the shift for n > 0.

n can range from 0 to 16.

In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is

equal to 0.

In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS

is greater than 15.

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the operation; cleared otherwise.

RD[15] ^ RD[15]

old

new

C: Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

CSR RD, #IMM4

CSR RD, RS

IMM4

DYA

IMM4

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Chapter 9 XGATE (S12XGATEV2)

Jump and Link

JAL

Operation

PC + $0002 ⇒ RD; RD ⇒ PC

Jumps to the address stored in RD and saves the return address in RD.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

JAL RD

MON

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Chapter 9 XGATE (S12XGATEV2)

Load Byte from Memory

(Low Byte)

LDB

Operation

M[RB, #OFFS5] ⇒ RD.L; $00 ⇒ RD.H

M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H

M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H; RI+1 ⇒ RI;

RI-1 ⇒ RI; M[RS, RI] ⇒ RD.L; $00 ⇒ RD.H

Loads a byte from memory into the low byte of register RD. The high byte is cleared.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

LDB RD, (RB, #OFFS5)

LDB RD, (RS, RI)

IDO5

IDR

OFFS5

LDB RD, (RS, RI+)

LDB RD, (RS, -RI)

IDR+

-IDR

1.If the same general purpose register is used as index (RI) and destination register (RD), the content of the register will not

be incremented after the data move: M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H

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Chapter 9 XGATE (S12XGATEV2)

Load Immediate 8-Bit Constant

(High Byte)

LDH

Operation

IMM8 ⇒ RD.H;

Loads an eight bit immediate constant into the high byte of register RD. The low byte is not affected.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

LDH RD, #IMM8

IMM8

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Chapter 9 XGATE (S12XGATEV2)

Load Immediate 8-Bit Constant

(Low Byte)

LDL

Operation

IMM8 ⇒ RD.L; $00 ⇒ RD.H

Loads an eight bit immediate constant into the low byte of register RD. The high byte is cleared.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

LDL RD, #IMM8

IMM8

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Chapter 9 XGATE (S12XGATEV2)

Load Word from Memory

LDW

Operation

M[RB, #OFFS5] ⇒ RD

M[RB, RI] ⇒ RD

M[RB, RI] ⇒ RD; RI+2 ⇒ RI

RI-2 ⇒ RI; M[RS, RI] ⇒ RD

IMM16 ⇒RD (translates to LDL RD, #IMM16[7:0]; LDH RD, #IMM16[15:8])

Loads a 16-bit value into the register RD.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

LDW RD, (RB, #OFFS5)

LDW RD, (RB, RI)

LDW RD, (RB, RI+)

LDW RD, (RB, -RI)

LDW RD, #IMM16

IDO5

IDR

OFFS5

IDR+

-IDR

IMM8

IMM16[7:0]

IMM16[15:8]

1. If the same general purpose register is used as index (RI) and destination register (RD), the content of the register will not be

incremented after the data move: M[RB, RI] ⇒ RD

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Chapter 9 XGATE (S12XGATEV2)

Logical Shift Left

LSL

Operation

n bits

n = RS or IMM4

Shifts the bits in register RD n positions to the left. The lower n bits of the register RD become ﬁlled with

zeros. The carry ﬂag will be updated to the bit contained in RD[16-n] before the shift for n > 0.

n can range from 0 to 16.

In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is

equal to 0.

In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS

is greater than 15.

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the operation; cleared otherwise.

RD[15] ^ RD[15]

old

new

C: Set if n > 0 and RD[16-n] = 1; if n = 0 unaffected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

LSL RD, #IMM4

LSL RD, RS

IMM4

DYA

IMM4

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Chapter 9 XGATE (S12XGATEV2)

Logical Shift Right

LSR

Operation

n bits

n = RS or IMM4

Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become ﬁlled

with zeros. The carry ﬂag will be updated to the bit contained in RD[n-1] before the shift for n > 0.

n can range from 0 to 16.

In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is

equal to 0.

In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS

is greater than 15.

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the operation; cleared otherwise.

RD[15] ^ RD[15]

old

new

C: Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

LSR RD, #IMM4

LSR RD, RS

IMM4

DYA

IMM4

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Chapter 9 XGATE (S12XGATEV2)

Move Register Content

MOV

Operation

RS ⇒ RD (translates to OR RD, R0, RS)

Copies the content of RS to RD.

CCR Effects

∆

—

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

MOV RD, RS

TRI

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Chapter 9 XGATE (S12XGATEV2)

Two’s Complement

NEG

Operation

–RS ⇒ RD (translates to SUB RD, R0, RS)

–RD ⇒ RD (translates to SUB RD, R0, RD)

Performs a two’s complement on a general purpose register.

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the operation; cleared otherwise.

RS[15] & RD[15]

new

C: Set if there is a carry from the bit 15 of the result; cleared otherwise

RS[15] | RD[15]

new

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

NEG RD, RS

NEG RD

TRI

0 0 0 1 1

0 0 0

0 0

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Chapter 9 XGATE (S12XGATEV2)

No Operation

NOP

Operation

No Operation for one cycle.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

NOP

INH

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Chapter 9 XGATE (S12XGATEV2)

Logical OR

Operation

RS1 | RS2 ⇒ RDRD | IMM16⇒ RD (translates to ORL RD, #IMM16[7:0]; ORH RD, #IMM16[15:8]

Performs a bit wise logical OR between two 16-bit values and stores the result in the destination

CCR Effects

∆

—

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

OR RD, RS1, RS2

OR RD, #IMM16

TRI

RS1

RS2

IMM8

IMM16[7:0]

IMM16[15:8]

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Chapter 9 XGATE (S12XGATEV2)

Logical OR Immediate 8-Bit Constant

(High Byte)

ORH

Operation

RD.H | IMM8 ⇒ RD.H

Performs a bit wise logical OR between the high byte of register RD and an immediate 8-Bit constant and

stores the result in the destination register RD.H. The low byte of RD is not affected.

CCR Effects

∆

—

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the 8-Bit result is $00; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

ORH RD, #IMM8

IMM8

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Chapter 9 XGATE (S12XGATEV2)

Logical OR Immediate 8-Bit Constant

(Low Byte)

ORL

Operation

RD.L | IMM8 ⇒ RD.L

Performs a bit wise logical OR between the low byte of register RD and an immediate 8-Bit constant and

stores the result in the destination register RD.L. The high byte of RD is not affected.

CCR Effects

∆

—

N: Set if bit 7 of the result is set; cleared otherwise.

Z: Set if the 8-Bit result is $00; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

ORL RD, #IMM8

IMM8

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Chapter 9 XGATE (S12XGATEV2)

Calculate Parity

PAR

Operation

Calculates the number of ones in the register RD. The Carry ﬂag will be set if the number is odd, otherwise

it will be cleared.

CCR Effects

∆

N: 0; cleared.

Z: Set if RD is $0000; cleared otherwise.

V: 0; cleared.

C: Set if there the number of ones in the register RD is odd; cleared otherwise.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

PAR, RD

MON

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Chapter 9 XGATE (S12XGATEV2)

Rotate Left

ROL

Operation

n bits

n = RS or IMM4

Rotates the bits in register RD n positions to the left. The lower n bits of the register RD are ﬁlled with the

upper n bits. Two source forms are available. In the ﬁrst form, the parameter n is contained in the

instruction code as an immediate operand. In the second form, the parameter is contained in the lower bits

of the source register RS[3:0]. All other bits in RS are ignored. If n is zero, no shift will take place and the

CCR Effects

∆

—

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

ROL RD, #IMM4

ROL RD, RS

IMM4

DYA

IMM4

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Chapter 9 XGATE (S12XGATEV2)

Rotate Right

ROR

Operation

n bits

n = RS or IMM4

Rotates the bits in register RD n positions to the right. The upper n bits of the register RD are ﬁlled with

the lower n bits. Two source forms are available. In the ﬁrst form, the parameter n is contained in the

instruction code as an immediate operand. In the second form, the parameter is contained in the lower bits

of the source register RS[3:0]. All other bits in RS are ignored. If n is zero no shift will take place and the

CCR Effects

∆

—

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

ROR RD, #IMM4

ROR RD, RS

IMM4

DYA

IMM4

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Chapter 9 XGATE (S12XGATEV2)

Return to Scheduler

RTS

Operation

Terminates the current thread of program execution and remains idle until a new thread is started by the

hardware scheduler.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

RTS

INH

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Chapter 9 XGATE (S12XGATEV2)

Subtract with Carry

SBC

Operation

RS1 - RS2 - C ⇒ RD

Subtracts the content of register RS2 and the value of the Carry bit from the content of register RS1 using

binary subtraction and stores the result in the destination register RD. Also the zero ﬂag is carried forward

from the previous operation allowing 32 and more bit subtractions.

Example:

SUB

SBC

BCC

R6,R4,R2

R7,R5,R3

; R7:R6 = R5:R4 - R3:R2

; conditional branch on 32 bit subtraction

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000 and Z was set before this operation; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the operation; cleared otherwise.

RS1[15] & RS2[15] & RD[15]

| RS1[15] & RS2[15] & RD[15]

new

C: Set if there is a carry from bit 15 of the result; cleared otherwise.

RS1[15] & RS2[15] | RS1[15] & RD[15]

| RS2[15] & RD[15]

new

Code and CPU Cycles

Address

Mode

Source Form

SBC RD, RS1, RS2

Machine Code

RD RS1

Cycles

TRI

RS2

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Chapter 9 XGATE (S12XGATEV2)

Set Semaphore

SSEM

Operation

Attempts to set a semaphore. The state of the semaphore will be stored in the Carry-Flag:

1 = Semaphore is locked by the RISC core

0 = Semaphore is locked by the S12X_CPU

In monadic address mode, bits RS[2:0] select the semaphore to be set.

CCR Effects

—

∆

N: Not affected.

Z: Not affected.

V: Not affected.

C: Set if semaphore is locked by the RISC core; cleared otherwise.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

SSEM #IMM3

SSEM RS

IMM3

MON

IMM3

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Chapter 9 XGATE (S12XGATEV2)

Sign Extend Byte to Word

SEX

Operation

The result in RD is the 16-bit sign extended representation of the original two’s complement number in the

low byte of RD.L.

CCR Effects

∆

—

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

SEX RD

MON

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Chapter 9 XGATE (S12XGATEV2)

Set Interrupt Flag

SIF

Operation

Sets the Interrupt Flag of an XGATE Channel. This instruction supports two source forms. If inherent

address mode is used, then the interrupt flag of the current channel (XGCHID) will be set. If the monadic

address form is used, the interrupt ﬂag associated with the channel id number contained in RS[6:0] is set.

The content of RS[15:7] is ignored.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

SIF

INH

SIF RS

MON

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Chapter 9 XGATE (S12XGATEV2)

Store Byte to Memory

(Low Byte)

STB

Operation

RS.L⇒ M[RB, #OFFS5]

RS.L⇒ M[RB, RI]

RS.L⇒ M[RB, RI]; RI+1 ⇒ RI;

RI–1 ⇒ RI; RS.L ⇒ M[RB, RI]

Stores the low byte of register RD to memory.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

STB RS, (RB, #OFFS5),

STB RS, (RB, RI)

IDO5

IDR

OFFS5

STB RS, (RB, RI+)

STB RS, (RB, -RI)

IDR+

-IDR

1. If the same general purpose register is used as index (RI) and source register (RS), the unmodiﬁed content of the source

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Chapter 9 XGATE (S12XGATEV2)

Store Word to Memory

STW

Operation

RS ⇒ M[RB, #OFFS5]

RS ⇒ M[RB, RI]

RS ⇒ M[RB, RI]; RI+2 ⇒ RI;

RI–2 ⇒ RI; RS ⇒ M[RB, RI]

Stores the content of register RS to memory.

CCR Effects

—

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

STW RS, (RB, #OFFS5)

STW RS, (RB, RI)

IDO5

IDR

OFFS5

STW RS, (RB, RI+)

STW RS, (RB, -RI)

IDR+

-IDR

1. If the same general purpose register is used as index (RI) and source register (RS), the unmodiﬁed content of the source

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Chapter 9 XGATE (S12XGATEV2)

Subtract without Carry

SUB

Operation

RS1 – RS2 ⇒ RDRD − IMM16 ⇒ RD (translates to SUBL RD, #IMM16[7:0]; SUBH RD, #IMM[15:8])

Subtracts two 16-bit values and stores the result in the destination register RD.

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the operation; cleared otherwise.

RS1[15] & RS2[15] & RD[15]

| RS1[15] & RS2[15] & RD[15]

new

C: Set if there is a carry from the bit 15 of the result; cleared otherwise.

RS1[15] & RS2[15] | RS1[15] & RD[15]

| RS2[15] & RD[15]

new

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

RD RS1

Cycles

SUB RD, RS1, RS2

TRI

RS2

SUB RD, #IMM16

IMM8

IMM16[7:0]

IMM16[15:8]

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Chapter 9 XGATE (S12XGATEV2)

Subtract Immediate 8-Bit Constant

(High Byte)

SUBH

Operation

RD – IMM8:$00 ⇒ RD

Subtracts a signed immediate 8-Bit constant from the content of high byte of register RD and using binary

subtraction and stores the result in the high byte of destination register RD. This instruction can be used

after an SUBL for a 16-bit immediate subtraction.

Example:

SUBL

SUBH

R2,#LOWBYTE

R2,#HIGHBYTE

; R2 = R2 - 16 Bit immediate

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the operation; cleared otherwise.

RD[15] & IMM8[7] & RD[15]

| RD[15] & IMM8[7] & RD[15]

old

new

old new

C: Set if there is a carry from the bit 15 of the result; cleared otherwise.

RD[15] & IMM8[7] | RD[15] & RD[15]

| IMM8[7] & RD[15]

old

new

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

SUBH RD, #IMM8

IMM8

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Chapter 9 XGATE (S12XGATEV2)

Subtract Immediate 8-Bit Constant

(Low Byte)

SUBL

Operation

RD – $00:IMM8 ⇒ RD

Subtracts an immediate 8 Bit constant from the content of register RD using binary subtraction and stores

the result in the destination register RD.

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the 8-bit operation; cleared otherwise.

RD[15] & RD[15]

old

new

C: Set if there is a carry from the bit 7 to bit 8 of the result; cleared otherwise.

RD[15] & RD[15]

old

new

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

SUBL RD, #IMM8

IMM8

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Chapter 9 XGATE (S12XGATEV2)

Transfer from and to Special Registers

TFR

Operation

TFR RD,CCR: CCR ⇒ RD[3:0], 0 ⇒ RD[15:4]

TFR CCR,RD: RD[3:0] ⇒ CCR

TFR RD,PC: PC+4 ⇒ RD

Transfers the content of one RISC core register to another.

The TFR RD,PC instruction can be used to implement relative subroutine calls.

Example:

TFR

BRA

R7,PC

SUBR

;Return address (RETADDR) is stored in R7

;Relative branch to subroutine (SUBR)

RETADDR ...

SUBR

...

JAL

;Jump to return address (RETADDR)

CCR Effects

TFR RD,CCR, TFR RD,PC:

TFR CCR,RS:

—

∆

N: Not affected.

Z: Not affected.

V: Not affected.

C: Not affected.

N: RS[3].

Z: RS[2].

V: RS[1].

C: RS[0].

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

Cycles

TFR RD,CCR

TFR CCR,RS

TFR RD,PC

CCR ⇒ RD

RS ⇒ CCR

PC+4 ⇒ RD

MON

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Chapter 9 XGATE (S12XGATEV2)

Test Register

TST

Operation

RS – 0 ⇒ NONE (translates to SUB R0, RS, R0)

Subtracts zero from the content of register RS using binary subtraction and discards the result.

CCR Effects

∆

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: Set if a two´s complement overﬂow resulted from the operation; cleared otherwise.

RS[15] & result[15]

C: Set if there is a carry from the bit 15 of the result; cleared otherwise.

RS1[15] & result[15]

Code and CPU Cycles

Address

Mode

Source Form

Machine Code

RS1

Cycles

TST RS

TRI

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Chapter 9 XGATE (S12XGATEV2)

Logical Exclusive NOR

XNOR

Operation

~(RS1 ^ RS2) ⇒ RD~(RD ^ IMM16) ⇒ RD

(translates to XNOR RD, #IMM[15:8]; XNOR RD, #IMM16[7:0])

Performs a bit wise logical exclusive NOR between two 16-bit values and stores the result in the

destination register RD.

Remark: Using R0 as a source registers will calculate the one’s complement of the other source register.

Using R0 as both source operands will ﬁll RD with $FFFF.

CCR Effects

∆

—

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the result is $0000; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

XNOR RD, RS1, RS2

XNOR RD, #IMM16

TRI

RS1

RS2

IMM8

IMM16[7:0]

IMM16[15:8]

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Chapter 9 XGATE (S12XGATEV2)

Logical Exclusive NOR Immediate

8-Bit Constant (High Byte)

XNORH

Operation

~(RD.H ^ IMM8) ⇒ RD.H

Performs a bit wise logical exclusive NOR between the high byte of register RD and an immediate 8-Bit

constant and stores the result in the destination register RD.H. The low byte of RD is not affected.

CCR Effects

∆

—

N: Set if bit 15 of the result is set; cleared otherwise.

Z: Set if the 8-bit result is $00; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

XNORH RD, #IMM8

IMM8

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Chapter 9 XGATE (S12XGATEV2)

Logical Exclusive NOR Immediate

8-Bit Constant (Low Byte)

XNORL

Operation

~(RD.L ^ IMM8) ⇒ RD.L

Performs a bit wise logical exclusive NOR between the low byte of register RD and an immediate 8-Bit

constant and stores the result in the destination register RD.L. The high byte of RD is not affected.

CCR Effects

∆

—

N: Set if bit 7 of the result is set; cleared otherwise.

Z: Set if the 8-bit result is $00; cleared otherwise.

V: 0; cleared.

C: Not affected.

Code and CPU Cycles

Address

Source Form

Mode

Machine Code

Cycles

XNORL RD, #IMM8

IMM8

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Chapter 9 XGATE (S12XGATEV2)

9.8.6

Instruction Coding

Table 9-18 summarizes all XGATE instructions in the order of their machine coding.

Table 9-18. Instruction Set Summary (Sheet 1 of 3)

Functionality

15 14 13 12 11 10

Return to Scheduler and Others

BRK

NOP

RTS

SIF

Semaphore Instructions

CSEM IMM3

IMM3

CSEM RS

SSEM IMM3

SSEM RS

Single Register Instructions

SEX RD

PAR RD

JAL RD

SIF RS

Special Move instructions

TFR RD,CCR

TFR CCR,RS

TFR RD,PC

Shift instructions Dyadic

BFFO RD, RS

ASR RD, RS

CSL RD, RS

CSR RD, RS

LSL RD, RS

LSR RD, RS

ROL RD, RS

ROR RD, RS

Shift instructions immediate

ASR RD, #IMM4

CSL RD, #IMM4

CSR RD, #IMM4

LSL RD, #IMM4

LSR RD, #IMM4

ROL RD, #IMM4

ROR RD, #IMM4

IMM4

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Chapter 9 XGATE (S12XGATEV2)

Functionality

Table 9-18. Instruction Set Summary (Sheet 2 of 3)

15 14 13 12 11 10

Logical Triadic

AND RD, RS1, RS2

OR RD, RS1, RS2

XNOR RD, RS1, RS2

Arithmetic Triadic

SUB RD, RS1, RS2

SBC RD, RS1, RS2

ADD RD, RS1, RS2

ADC RD, RS1, RS2

Branches

RS1

RS2

For compare use SUB R0,Rs1,Rs2

RS1

RS2

BCC REL9

BCS REL9

BNE REL9

BEQ REL9

BPL REL9

BMI REL9

BVC REL9

BVS REL9

BHI REL9

BLS REL9

BGE REL9

BLT REL9

BGT REL9

BLE REL9

BRA REL10

REL9

REL10

Load and Store Instructions

LDB RD, (RB, #OFFS5)

LDW RD, (RB, #OFFS5)

STB RS, (RB, #OFFS5)

STW RS, (RB, #OFFS5)

LDB RD, (RB, RI)

LDW RD, (RB, RI)

STB RS, (RB, RI)

STW RS, (RB, RI)

LDB RD, (RB, RI+)

LDW RD, (RB, RI+)

STB RS, (RB, RI+)

STW RS, (RB, RI+)

LDB RD, (RB, –RI)

LDW RD, (RB, –RI)

STB RS, (RB, –RI)

STW RS, (RB, –RI)

Bit Field Instructions

BFEXT RD, RS1, RS2

BFINS RD, RS1, RS2

BFINSI RD, RS1, RS2

BFINSX RD, RS1, RS2

Logic Immediate Instructions

ANDL RD, #IMM8

OFFS5

RS1

RS2

IMM8

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Chapter 9 XGATE (S12XGATEV2)

Table 9-18. Instruction Set Summary (Sheet 3 of 3)

Functionality

ANDH RD, #IMM8

BITL RD, #IMM8

BITH RD, #IMM8

ORL RD, #IMM8

ORH RD, #IMM8

15 14 13 12 11 10

IMM8

XNORL RD, #IMM8

XNORH RD, #IMM8

Arithmetic Immediate Instructions

SUBL RD, #IMM8

SUBH RD, #IMM8

CMPL RS, #IMM8

CPCH RS, #IMM8

ADDL RD, #IMM8

ADDH RD, #IMM8

LDL RD, #IMM8

IMM8

LDH RD, #IMM8

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Chapter 9 XGATE (S12XGATEV2)

9.9

Initialization and Application Information

9.9.1

Initialization

The recommended initialization of the XGATE is as follows:

1. Clear the XGE bit to suppress any incoming service requests.

2. Make sure that no thread is running on the XGATE. This can be done in several ways:

a) Poll the XGCHID register until it reads $00. Also poll XGDBG and XGSWEIF to make sure

that the XGATE has not been stopped.

b) Enter Debug Mode by setting the XGDBG bit. Clear the XGCHID register. Clear the XGDBG

bit.

The recommended method is a).

3. Set the XGVBR register to the lowest address of the XGATE vector space.

4. Clear all Channel ID ﬂags.

5. Copy XGATE vectors and code into the RAM.

6. Initialize the S12X_INT module.

7. Enable the XGATE by setting the XGE bit.

The following code example implements the XGATE initialization sequence.

9.9.2

Code Example (Transmit "Hello World!" on SCI)

CPU

;###########################################

;# SYMBOLS

;###########################################

S12

SCI_REGS

SCIBDH

SCICR2

SCISR1

SCIDRL

TIE

SCI_VEC

EQU

$00C8

;SCI register space

;SCI Baud Rate Register

;SCI Control Register 2

;SCI Status Register 1

;SCI Control Register 2

;TIE bit mask

;TE bit mask

;RE bit mask

;SCI vector number

SCI_REGS+$00

SCI_REGS+$03

SCI_REGS+$04

SCI_REGS+$07

$80

$08

$04

$D6

INT_REGS

INT_CFADDR

INT_CFDATA

RQST

EQU

$0120

;S12X_INT register space

INT_REGS+$07

INT_REGS+$08

$80

;Interrupt Configuration Address Register

;Interrupt Configuration Data Registers

;RQST bit mask

XGATE_REGS

XGMCTL

XGMCTL_CLEAR

XGEM

XGDBGM

XGE

EQU

$0380

;XGATE register space

XGATE_REGS+$00 ;XGATE Module Control Register

$F902

$8000

$2000

$0080

$0020

$0002

XGDBG

XGSWEIF

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Chapter 9 XGATE (S12XGATEV2)

XGCHID

XGVBR

XGIF

XGSWT

XGSEM

EQU

XGATE_REGS+$02 ;XGATE Channel ID Register

XGATE_REGS+$06 ;XGATE Vector Base Register

XGATE_REGS+$08 ;XGATE Interrupt Flag Vector

XGATE_REGS+$18 ;XGATE Software Trigger Register

XGATE_REGS+$1A ;XGATE Semaphore Register

RPAGE

EQU

$0016

RAM_SIZE

EQU

20*$400

;20k RAM

RAM_START_GLOBAL

RAM_START_XGATE

RAM_START_S12

RPAGE_VALUE

$10_0000-RAM_SIZE

$1_0000-RAM_SIZE

$1000

RAM_START_GLOBAL>>12

XGATE_VECTORS

XGATE_DATA

EQU

RAM_START_S12

RAM_START_S12+(4*128)

XGATE_OFFSET

BUS_FREQ_HZ

EQU

(RAM_START_XGATE+(4*128))-XGATE_DATA_BEGIN

40_000000

;###########################################

;# RESET VECTOR

;###########################################

ORG

$FFFE

START_OF_CODE

ORG

$3000

START_OF_CODE

;###########################################

;# INITIALIZE SCI

;###########################################

INIT_SCI

MOVW

MOVB

#(BUS_FREQ_HZ/(16*9600)), SCIBDH

#(TIE|TE|RE), SCICR2 ;enable tx buffer empty interrupt

;set baud rate

;###########################################

;# INITIALIZE S12X_INT

;###########################################

SEI

INIT_INT

;disable interrupts

MOVB

#(SCI_VEC&$F0), INT_CFADDR ;switch SCI interrupts to XGATE

#RQST|$01, INT_CFDATA+((SCI_VEC&$0F)>>1)

;###########################################

;# INITIALIZE XGATE

;###########################################

INIT_XGATE

MOVW

#XGMCTL_CLEAR, XGMCTL

;clear all XGMCTL bits

BRSET XGCHID, $FF, INIT_XGATE ;wait until current thread is done

MOVW

#$10000-RAM_SIZE, XGVBR ;set vector base register

LDX

LDD

STD

#XGIF

#$FFFF

2,X+

;clear all channel interrupt flags

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Chapter 9 XGATE (S12XGATEV2)

STD

2,X+

MOVW

#$FF00, XGSWT

;clear all software triggers

;###########################################

;# INITIALIZE XGATE VECTOR SPACE

;###########################################

INIT_XGATE_VECTOR_SPACE MOVB

#(RAM_START_GLOBAL>>12), RPAGE ;set all vectors to dummy

service routine

LDX

#128

LDY

LDD

#RAM_START_S12

#XGATE_DUMMY+XGATE_OFFSET

INIT_XGATE_VECTOR_SPACE_LOOP

STD

4,Y+

DBNE

X,INIT_XGATE_VECTOR_SPACE_LOOP

;set SCI INTERRUPT VECTOR

MOVW #XGATE_CODE_BEGIN+XGATE_OFFSET,RAM_START_S12+(2*SCI_VEC)

#XGATE_DATA_BEGIN+XGATE_OFFSET, RAM_START_S12+(2*SCI_VEC)+2

MOVW

;###########################################

COPY XGATE CODE

;###########################################

COPY_XGATE_CODE

COPY_XGATE_CODE_LOOP

LDX

#XGATE_DATA_BEGIN

2,X+, 2,Y+

MOVW

CPX

#XGATE_CODE_END

COPY_XGATE_CODE_LOOP

BLS

;###########################################

;# START XGATE

;###########################################

START_XGATE

MOVB

BRA

#(XGE|XGDBGM|XGSWEIF), XGMCTL ;enable XGATE

CPU

XGATE

;###########################################

;# XGATE DATA

;###########################################

ALIGN 1

XGATE_DATA_BEGIN

XGATE_DATA_SCI_PTR

XGATE_DATA_MSG_IDX

XGATE_DATA_MSG

FCC

SCI_REGS

XGATE_DATA_MSG-XGATE_DATA_BEGIN

"Hello World!"

$0D

;pointer to SCI register space

;string pointer

;ASCII string

;CR

XGATE_DATA_END

;###########################################

;# XGATE CODE

;###########################################

ALIGN 1

XGATE_CODE_BEGIN

LDW

LDB

STB

LDB

R2,(R1,#(XGATE_DATA_SCI_PTR-XGATE_DATA_BEGIN));SCI -> R2

R3,(R1,#(XGATE_DATA_MSG_IDX-XGATE_DATA_BEGIN));msg -> R3

R4,(R1,R3+)

;curr. char -> R4

R3,(R1,#(XGATE_DATA_MSG_IDX-XGATE_DATA_BEGIN));R3 -> idx

R0,(R2,#(SCISR1-SCI_REGS))

;initiate SCI transmit

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Chapter 9 XGATE (S12XGATEV2)

STB

CMPL

BEQ

RTS

LDL

STB

LDL

STB

RTS

EQU

R4,(R2,#(SCIDRL-SCI_REGS))

R4,#$0D

XGATE_CODE_DONE

;initiate SCI transmit

XGATE_CODE_DONE

R4,#$00

R4,(R2,#(SCICR2-SCI_REGS))

R3,#(XGATE_DATA_MSG-XGATE_DATA_BEGIN);reset R3

R3,(R1,#(XGATE_DATA_MSG_IDX-XGATE_DATA_BEGIN))

;disable SCI interrupts

XGATE_CODE_END

XGATE_DUMMY

XGATE_CODE_END

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Chapter 10

Security (S12X9SECV2)

10.1 Introduction

This speciﬁcation describes the function of the security mechanism in the S12X chip family

(MC9S12XDP512).

10.1.1 Features

The user must be reminded that part of the security must lie with the application code. An extreme example

would be application code that dumps the contents of the internal memory. This would defeat the purpose

of security. At the same time, the user may also wish to put a backdoor in the application program. An

example of this is the user downloads a security key through the SCI, which allows access to a

programming routine that updates parameters stored in another section of the Flash memory.

The security features of the S12X chip family (in secure mode) are:

•

Protect the contents of non-volatile memories (Flash, EEPROM)

Execution of NVM commands is restricted

Disable access to internal memory via background debug module (BDM)

Disable access to internal Flash/EEPROM in expanded modes

Disable debugging features for CPU and XGATE

Table 10-1 gives an overview over availability of security relevant features in unsecure and secure modes.

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Chapter 10 Security (S12X9SECV2)

Table 10-1. Features Availability in Unsecure and Secure Modes

Unsecure Mode

Secure Mode

Flash Array Access

EEPROM Array Access

NVM Commands

BDM

✔

—

✔

—

✔

—

✔

—

✔

—

✔

—

✔

—

✔

—

✔

—

✔

—

✔

DBG Module Trace

XGATE Debugging

External Bus Interface

—

Internal status visible

multiplexed on

—

✔

—

external bus

Internal accesses visible

on external bus

—

✔

—

✔

Availability of Flash arrays in the memory map depends on ROMCTL/EROMCTL pins and/or the state of

the ROMON/EROMON bits in the MMCCTL1 register. Please refer to the S12X_MMC block guide for

detailed information.

Restricted NVM command set only. Please refer to the FTX/EETX block guides for detailed information.

BDM hardware commands restricted to peripheral registers only.

10.1.2 Modes of Operation

10.1.3 Securing the Microcontroller

Once the user has programmed the Flash and EEPROM, the chip can be secured by programming the

security bits located in the options/security byte in the Flash memory array. These non-volatile bits will

keep the device secured through reset and power-down.

The options/security byte is located at address 0xFF0F (= global address 0x7F_FF0F) in the Flash memory

array. This byte can be erased and programmed like any other Flash location. Two bits of this byte are used

for security (SEC[1:0]). On devices which have a memory page window, the Flash options/security byte

is also available at address 0xBF0F by selecting page 0x3F with the PPAGE register. The contents of this

byte are copied into the Flash security register (FSEC) during a reset sequence.

0xFF0F KEYEN1 KEYEN0

NV5

NV4

NV3

NV2

SEC1

SEC0

Figure 10-1. Flash Options/Security Byte

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Chapter 10 Security (S12X9SECV2)

The meaning of the bits KEYEN[1:0] is shown in Table 10-2. Please refer to Section 10.1.5.1,

“Unsecuring the MCU Using the Backdoor Key Access” for more information.

Table 10-2. Backdoor Key Access Enable Bits

Backdoor Key

KEYEN[1:0]

Access Enabled

0 (disabled)

1 (enabled)

0 (disabled)

The meaning of the security bits SEC[1:0] is shown in Table 10-3. For security reasons, the state of device

security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to

SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put

the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’.

Table 10-3. Security Bits

SEC[1:0]

Security State

1 (secured)

0 (unsecured)

1 (secured)

NOTE

Please refer to the Flash block guide (FTX) for actual security conﬁguration

(in section “Flash Module Security”).

10.1.4 Operation of the Secured Microcontroller

By securing the device, unauthorized access to the EEPROM and Flash memory contents can be prevented.

However, it must be understood that the security of the EEPROM and Flash memory contents also depends

on the design of the application program. For example, if the application has the capability of downloading

code through a serial port and then executing that code (e.g. an application containing bootloader code),

then this capability could potentially be used to read the EEPROM and Flash memory contents even when

the microcontroller is in the secure state. In this example, the security of the application could be enhanced

by requiring a challenge/response authentication before any code can be downloaded.

Secured operation has the following effects on the microcontroller:

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 10 Security (S12X9SECV2)

10.1.4.1 Normal Single Chip Mode (NS)

•

Background debug module (BDM) operation is completely disabled.

Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide

(FTX) for details.

•

Tracing code execution using the DBG module is disabled.

Debugging XGATE code (breakpoints, single-stepping) is disabled.

10.1.4.2 Special Single Chip Mode (SS)

•

BDM ﬁrmware commands are disabled.

BDM hardware commands are restricted to the register space.

Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide

(FTX) for details.

•

Tracing code execution using the DBG module is disabled.

Debugging XGATE code (breakpoints, single-stepping) is disabled.

Special single chip mode means BDM is active after reset. The availability of BDM ﬁrmware commands

depends on the security state of the device. The BDM secure ﬁrmware ﬁrst performs a blank check of both

the Flash memory and the EEPROM. If the blank check succeeds, security will be temporarily turned off

and the state of the security bits in the appropriate Flash memory location can be changed If the blank

check fails, security will remain active, only the BDM hardware commands will be enabled, and the

accessible memory space is restricted to the peripheral register area. This will allow the BDM to be used

to erase the EEPROM and Flash memory without giving access to their contents. After erasing both Flash

memory and EEPROM, another reset into special single chip mode will cause the blank check to succeed

and the options/security byte can be programmed to “unsecured” state via BDM.

While the BDM is executing the blank check, the BDM interface is completely blocked, which means that

all BDM commands are temporarily blocked.

10.1.4.3 Expanded Modes (NX, ES, EX, and ST)

•

BDM operation is completely disabled.

Internal Flash memory and EEPROM are disabled.

Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide

(FTX) for details.

•

Tracing code execution using the DBG module is disabled.

Debugging XGATE code (breakpoints, single-stepping) is disabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 10 Security (S12X9SECV2)

10.1.5 Unsecuring the Microcontroller

Unsecuring the microcontroller can be done by three different methods:

1. Backdoor key access

2. Reprogramming the security bits

3. Complete memory erase (special modes)

10.1.5.1 Unsecuring the MCU Using the Backdoor Key Access

In normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key

access method. This method requires that:

•

The backdoor key at 0xFF00–0xFF07 (= global addresses 0x7F_FF00–0x7F_FF07) has been

programmed to a valid value.

•

The KEYEN[1:0] bits within the Flash options/security byte select ‘enabled’.

In single chip mode, the application program programmed into the microcontroller must be

designed to have the capability to write to the backdoor key locations.

The backdoor key values themselves would not normally be stored within the application data, which

means the application program would have to be designed to receive the backdoor key values from an

external source (e.g. through a serial port). It is not possible to download the backdoor keys using

background debug mode.

The backdoor key access method allows debugging of a secured microcontroller without having to erase

the Flash. This is particularly useful for failure analysis.

NOTE

No word of the backdoor key is allowed to have the value 0x0000 or

0xFFFF.

10.1.5.2 Backdoor Key Access Sequence

These are the necessary steps for a successful backdoor key access sequence:

1. Set the KEYACC bit in the Flash conﬁguration register FCNFG.

2. Write the ﬁrst 16-bit word of the backdoor key to 0xFF00 (0x7F_FF00).

3. Write the second 16-bit word of the backdoor key to 0xFF02 (0x7F_FF02).

4. Write the third 16-bit word of the backdoor key to 0xFF04 (0x7F_FF04).

5. Write the fourth 16-bit word of the backdoor key to 0xFF06 (0x7F_FF06).

6. Clear the KEYACC bit in the Flash Conﬁguration register FCNFG.

NOTE

Flash cannot be read while KEYACC is set. Therefore the code for the

backdoor key access sequence must execute from RAM.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 10 Security (S12X9SECV2)

If all four 16-bit words match the Flash contents at 0xFF00–0xFF07 (0x7F_FF00–0x7F_FF07), the

microcontroller will be unsecured and the security bits SEC[1:0] in the Flash Security register FSEC will

be forced to the unsecured state (‘10’). The contents of the Flash options/security byte are not changed by

this procedure, and so the microcontroller will revert to the secure state after the next reset unless further

action is taken as detailed below.

If any of the four 16-bit words does not match the Flash contents at 0xFF00–0xFF07

(0x7F_FF00–0x7F_FF07), the microcontroller will remain secured.

10.1.6 Reprogramming the Security Bits

In normal single chip mode (NS), security can also be disabled by erasing and reprogramming the security

bits within Flash options/security byte to the unsecured value. Because the erase operation will erase the

entire sector from 0xFE00–0xFFFF (0x7F_FE00–0x7F_FFFF), the backdoor key and the interrupt vectors

will also be erased; this method is not recommended for normal single chip mode. The application

software can only erase and program the Flash options/security byte if the Flash sector containing the Flash

options/security byte is not protected (see Flash protection). Thus Flash protection is a useful means of

preventing this method. The microcontroller will enter the unsecured state after the next reset following

the programming of the security bits to the unsecured value.

This method requires that:

•

The application software previously programmed into the microcontroller has been designed to

have the capability to erase and program the Flash options/security byte, or security is ﬁrst disabled

using the backdoor key method, allowing BDM to be used to issue commands to erase and program

the Flash options/security byte.

•

The Flash sector containing the Flash options/security byte is not protected.

10.1.7 Complete Memory Erase (Special Modes)

The microcontroller can be unsecured in special modes by erasing the entire EEPROM and Flash memory

contents.

When a secure microcontroller is reset into special single chip mode (SS), the BDM ﬁrmware veriﬁes

whether the EEPROM and Flash memory are erased. If any EEPROM or Flash memory address is not

erased, only BDM hardware commands are enabled. BDM hardware commands can then be used to write

to the EEPROM and Flash registers to mass erase the EEPROM and all Flash memory blocks.

When next reset into special single chip mode, the BDM ﬁrmware will again verify whether all EEPROM

and Flash memory are erased, and this being the case, will enable all BDM commands, allowing the Flash

options/security byte to be programmed to the unsecured value. The security bits SEC[1:0] in the Flash

security register will indicate the unsecure state following the next reset.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 10 Security (S12X9SECV2)

Special single chip erase and unsecure sequence:

1. Reset into special single chip mode.

2. Write an appropriate value to the ECLKDIV register for correct timing.

3. Write 0xFF to the EPROT register to disable protection.

4. Write 0x30 to the ESTAT register to clear the PVIOL and ACCERR bits.

5. Write 0x0000 to the EDATA register (0x011A–0x011B).

6. Write 0x0000 to the EADDR register (0x0118–0x0119).

7. Write 0x41 (mass erase) to the ECMD register.

8. Write 0x80 to the ESTAT register to clear CBEIF.

9. Write an appropriate value to the FCLKDIV register for correct timing.

10. Write 0x00 to the FCNFG register to select Flash block 0.

11. Write 0x10 to the FTSTMOD register (0x0102) to set the WRALL bit, so the following writes

affect all Flash blocks.

12. Write 0xFF to the FPROT register to disable protection.

13. Write 0x30 to the FSTAT register to clear the PVIOL and ACCERR bits.

14. Write 0x0000 to the FDATA register (0x010A–0x010B).

15. Write 0x0000 to the FADDR register (0x0108–0x0109).

16. Write 0x41 (mass erase) to the FCMD register.

17. Write 0x80 to the FSTAT register to clear CBEIF.

18. Wait until all CCIF ﬂags are set.

19. Reset back into special single chip mode.

20. Write an appropriate value to the FCLKDIV register for correct timing.

21. Write 0x00 to the FCNFG register to select Flash block 0.

22. Write 0xFF to the FPROT register to disable protection.

23. Write 0xFFBE to Flash address 0xFF0E.

24. Write 0x20 (program) to the FCMD register.

25. Write 0x80 to the FSTAT register to clear CBEIF.

26. Wait until the CCIF ﬂag in FSTAT is are set.

27. Reset into any mode.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 10 Security (S12X9SECV2)

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11

Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.1 Introduction

The HCS12 enhanced capture timer module has the features of the HCS12 standard timer module

enhanced by additional features in order to enlarge the ﬁeld of applications, in particular for automotive

ABS applications.

This design speciﬁcation describes the standard timer as well as the additional features.

The basic timer consists of a 16-bit, software-programmable counter driven by a prescaler. This timer can

be used for many purposes, including input waveform measurements while simultaneously generating an

output waveform. Pulse widths can vary from microseconds to many seconds.

A full access for the counter registers or the input capture/output compare registers will take place in one

clock cycle. Accessing high byte and low byte separately for all of these registers will not yield the same

result as accessing them in one word.

11.1.1 Features

•

16-bit buffer register for four input capture (IC) channels.

Four 8-bit pulse accumulators with 8-bit buffer registers associated with the four buffered IC

channels. Conﬁgurable also as two 16-bit pulse accumulators.

•

16-bit modulus down-counter with 8-bit prescaler.

Four user-selectable delay counters for input noise immunity increase.

11.1.2 Modes of Operation

•

Stop — Timer and modulus counter are off since clocks are stopped.

Freeze — Timer and modulus counter keep on running, unless the TSFRZ bit in the TSCR1 register

is set to one.

•

Wait — Counters keep on running, unless the TSWAI bit in the TSCR1 register is set to one.

Normal — Timer and modulus counter keep on running, unless the TEN bit in the TSCR1 register

or the MCEN bit in the MCCTL register are cleared.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.1.3 Block Diagram

Channel 0

Input Capture

Output Compare

Channel 1

Prescaler

Bus Clock

IOC0

IOC1

16-bit Counter

Input Capture

Modulus Counter

Output Compare

16-Bit Modulus Counter

Interrupt

Channel 2

Input Capture

Timer Overflow

Interrupt

Timer Channel 0

Interrupt

IOC2

IOC3

Output Compare

Channel 3

Input Capture

Output Compare

Registers

Channel 4

Input Capture

IOC4

IOC5

Output Compare

Channel 5

Input Capture

Output Compare

Timer Channel 7

Interrupt

Channel 6

Input Capture

PA Overflow

16-Bit

IOC6

IOC7

Interrupt

Output Compare

Pulse Accumulator A

PA Input

Interrupt

PB Overflow

Channel 7

Input Capture

16-Bit

Pulse Accumulator B

Interrupt

Output Compare

Figure 11-1. ECT Block Diagram

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.2 External Signal Description

The ECT module has a total of eight external pins.

11.2.1 IOC7 — Input Capture and Output Compare Channel 7

This pin serves as input capture or output compare for channel 7.

11.2.2 IOC6 — Input Capture and Output Compare Channel 6

This pin serves as input capture or output compare for channel 6.

11.2.3 IOC5 — Input Capture and Output Compare Channel 5

This pin serves as input capture or output compare for channel 5.

11.2.4 IOC4 — Input Capture and Output Compare Channel 4

This pin serves as input capture or output compare for channel 4.

11.2.5 IOC3 — Input Capture and Output Compare Channel 3

This pin serves as input capture or output compare for channel 3.

11.2.6 IOC2 — Input Capture and Output Compare Channel 2

This pin serves as input capture or output compare for channel 2.

11.2.7 IOC1 — Input Capture and Output Compare Channel 1

This pin serves as input capture or output compare for channel 1.

11.2.8 IOC0 — Input Capture and Output Compare Channel 0

This pin serves as input capture or output compare for channel 0.

NOTE

For the description of interrupts see Section 11.4.3, “Interrupts”.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all memory and registers.

11.3.1 Module Memory Map

The memory map for the ECT module is given below in Table 11-1. The address listed for each register is

the address offset. The total address for each register is the sum of the base address for the ECT module

and the address offset for each register.

Table 11-1. MC9S12XDP512 Memory Map

Address

Offset

Access

0x0000

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

0x0008

0x0009

0x000A

0x000B

0x000C

0x000D

0x000E

0x000F

0x0010

0x0011

0x0012

0x0013

0x0014

0x0015

0x0016

0x0017

0x0018

0x0019

0x001A

0x001B

0x001C

0x001D

Timer Input Capture/Output Compare Select (TIOS)

Timer Compare Force Register (CFORC)

R/W

Output Compare 7 Mask Register (OC7M)

R/W

Output Compare 7 Data Register (OC7D)

Timer Count Register High (TCNT)

R/W

Timer Count Register Low (TCNT)

R/W

Timer System Control Register 1 (TSCR1)

R/W

Timer Toggle Overﬂow Register (TTOV)

Timer Control Register 1 (TCTL1)

Timer Control Register 2 (TCTL2)

Timer Control Register 3 (TCTL3)

Timer Control Register 4 (TCTL4)

Timer Interrupt Enable Register (TIE)

Timer System Control Register 2 (TSCR2)

Main Timer Interrupt Flag 1 (TFLG1)

Main Timer Interrupt Flag 2 (TFLG2)

Timer Input Capture/Output Compare Register 0 High (TC0)

Timer Input Capture/Output Compare Register 0 Low (TC0)

Timer Input Capture/Output Compare Register 1 High (TC1)

Timer Input Capture/Output Compare Register 1 Low (TC1)

Timer Input Capture/Output Compare Register 2 High (TC2)

Timer Input Capture/Output Compare Register 2 Low (TC2)

Timer Input Capture/Output Compare Register 3 High (TC3)

Timer Input Capture/Output Compare Register 3 Low (TC3)

Timer Input Capture/Output Compare Register 4 High (TC4)

Timer Input Capture/Output Compare Register 4 Low (TC4)

Timer Input Capture/Output Compare Register 5 High (TC5)

Timer Input Capture/Output Compare Register 5 Low (TC5)

Timer Input Capture/Output Compare Register 6 High (TC6)

Timer Input Capture/Output Compare Register 6 Low (TC6)

R/W

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

Table 11-1. MC9S12XDP512 Memory Map (continued)

Address

Offset

Access

0x001E

0x001F

0x0020

0x0021

0x0022

0x0023

0x0024

0x0025

0x0026

0x0027

0x0028

0x0029

0x002A

0x002B

0x002C

0x002D

0x002E

0x002F

0x0030

0x0031

0x0032

0x0033

0x0034

0x0035

0x0036

0x0037

0x0038

0x0039

0x003A

0x003B

0x003C

0x003D

0x003E

0x003F

Timer Input Capture/Output Compare Register 7 High (TC7)

Timer Input Capture/Output Compare Register 7 Low (TC7)

16-Bit Pulse Accumulator A Control Register (PACTL)

Pulse Accumulator A Flag Register (PAFLG)

R/W

Pulse Accumulator Count Register 3 (PACN3)

Pulse Accumulator Count Register 2 (PACN2)

Pulse Accumulator Count Register 1 (PACN1)

Pulse Accumulator Count Register 0 (PACN0)

16-Bit Modulus Down Counter Register (MCCTL)

16-Bit Modulus Down Counter Flag Register (MCFLG)

Input Control Pulse Accumulator Register (ICPAR)

Delay Counter Control Register (DLYCT)

Input Control Overwrite Register (ICOVW)

Input Control System Control Register (ICSYS)

Reserved

R/W

Timer Test Register (TIMTST)

R/W

Precision Timer Prescaler Select Register (PTPSR)

Precision Timer Modulus Counter Prescaler Select Register (PTMCPSR)

16-Bit Pulse Accumulator B Control Register (PBCTL)

16-Bit Pulse Accumulator B Flag Register (PBFLG)

8-Bit Pulse Accumulator Holding Register 3 (PA3H)

8-Bit Pulse Accumulator Holding Register 2 (PA2H)

8-Bit Pulse Accumulator Holding Register 1 (PA1H)

8-Bit Pulse Accumulator Holding Register 0 (PA0H)

Modulus Down-Counter Count Register High (MCCNT)

Modulus Down-Counter Count Register Low (MCCNT)

Timer Input Capture Holding Register 0 High (TC0H)

Timer Input Capture Holding Register 0 Low (TC0H)

Timer Input Capture Holding Register 1 High(TC1H)

Timer Input Capture Holding Register 1 Low (TC1H)

Timer Input Capture Holding Register 2 High (TC2H)

Timer Input Capture Holding Register 2 Low (TC2H)

Timer Input Capture Holding Register 3 High (TC3H)

Timer Input Capture Holding Register 3 Low (TC3H)

R/W

Always read 0x0000.

Only writable in special modes (test_mode = 1).

Writes to these registers have no meaning or effect during input capture.

May be written once when not in test00mode but writes are always permitted when test00mode is enabled.

Writes have no effect.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2 Register Descriptions

This section consists of register descriptions in address order. Each description includes a standard register

diagram with an associated ﬁgure number. Details of register bit and ﬁeld function follow the register

diagrams, in bit order.

Name

Bit 7

Bit 0

0x0000

TIOS

IOS7

IOS6

IOS5

IOS4

IOS3

IOS2

IOS1

IOS0

0x0001

CFORC

FOC7

FOC6

FOC5

FOC4

FOC3

FOC2

FOC1

FOC0

0x0002

OC7M

OC7M7

OC7D7

TCNT15

TCNT7

TEN

OC7M6

OC7D6

TCNT14

TCNT6

TSWAI

TOV6

OC7M5

OC7D5

TCNT13

TCNT5

TSFRZ

TOV5

OC7M4

OC7D4

TCNT12

TCNT4

TFFCA

TOV4

OC7M3

OC7D3

TCNT11

TCNT3

PRNT

TOV3

OC7M2

OC7D2

TCNT10

OC7M1

OC7D1

TCNT9

OC7M0

OC7D0

TCNT8

0x0003

OC7D

0x0004

TCNT (High)

0x0005

TCNT (Low)

TCNT2

TCNT1

TCNT0

0x0006

TSCR1

0x0007

TTOF

TOV7

TOV2

OL5

TOV1

OM4

TOV0

OL4

0x0008

TCTL1

OM7

OL7

OM6

OL6

OM5

0x0009

TCTL2

OM3

OL3

OM2

OL2

OM1

OL1

OM0

OL0

0x000A

TCTL3

EDG7B

EDG3B

C7I

EDG7A

EDG3A

C6I

EDG6B

EDG2B

C5I

EDG6A

EDG2A

C4I

EDG5B

EDG1B

C3I

EDG5A

EDG1A

C2I

EDG4B

EDG0B

C1I

EDG4A

EDG0A

C0I

0x000B

TCTL4

0x000C

TIE

= Unimplemented or Reserved

Figure 11-2. ECT Register Summary (Sheet 1 of 5)

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

Name

Bit 7

Bit 0

0x000D

TSCR2

TOI

TCRE

PR2

PR1

PR0

0x000E

TFLG1

C7F

TOF

C6F

C5F

C4F

C3F

C2F

C1F

C0F

0x000F

TFLG2

0x0010

TC0 (High)

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 9

Bit 1

Bit 9

Bit 1

Bit 9

Bit 1

Bit 9

Bit 1

Bit 9

Bit 1

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

0x0011

TC0 (Low)

0x0012

TC1 (High)

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

0x0013

TC1 (Low)

0x0014

TC2 (High)

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

0x0015

TC2 (Low)

0x0016

TC3 (High)

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

0x0017

TC3 (Low)

0x0018

TC4 (High)

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

0x0019

TC4 (Low)

0x001A

TC5 (High)

Bit 15

Bit 7

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

0x001B

TC5 (Low)

= Unimplemented or Reserved

Figure 11-2. ECT Register Summary (Sheet 2 of 5)

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

Bit 7

Bit 0

Name

0x001C

TC6 (High)

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

0x001D

TC6 (Low)

Bit 7

Bit 6

Bit 14

Bit 6

Bit 5

Bit 13

Bit 5

Bit 4

Bit 12

Bit 4

Bit 3

Bit 11

Bit 3

Bit 2

Bit 10

Bit 2

Bit 1

Bit 9

Bit 0

Bit 8

Bit 0

PAI

0x001E

TC7 (High)

Bit 15

0x001F

TC7 (Low)

Bit 7

Bit 1

0x0020

PACTL

PAEN

PAMOD

PEDGE

CLK1

CLK0

PA0VI

PA0VF

0x0021

PAFLG

PAIF

0x0022

PACN3

PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) PACNT1(9) PACNT0(8)

0x0023

PACN2

PACNT7

PACNT6

PACNT5

PACNT4

PACNT3

PACNT2

PACNT1

PACNT0

0x0024

PACN1

PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) PACNT1(9) PACNT0(8)

0x0025

PACN0

PACNT7

MCZI

PACNT6

PACNT5

PACNT4

PACNT3

PACNT2

PACNT1

PACNT0

0x0026

MCCTL

MODMC

RDMCL

MCEN

POLF2

MCPR1

POLF1

MCPR0

POLF0

ICLAT

FLMC

0x0027

MCFLG

POLF3

MCZF

0x0028

ICPAR

PA3EN

DLY3

PA2EN

DLY2

PA1EN

DLY1

PA0EN

DLY0

0x0029

DLYCT

DLY7

DLY6

DLY5

DLY4

0x002A

ICOVW

NOVW7

NOVW6

NOVW5

NOVW4

NOVW3

NOVW2

NOVW1

NOVW0

= Unimplemented or Reserved

Figure 11-2. ECT Register Summary (Sheet 3 of 5)

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

Name

Bit 7

Bit 0

0x002B

ICSYS

SH37

SH26

SH15

SH04

TFMOD

PACMX

BUFEN

LATQ

0x002C

Reserved

0x002D

TIMTST

Timer Test Register

0x002E

PTPSR

PTPS7

PTPS6

PTPS5

PTPS4

PTPS3

PTPS2

PTPS1

PTMPS1

PBOVI

PTPS0

0x002F

PTMCPSR

PTMPS7

PTMPS6

PTMPS5

PTMPS4

PTMPS3

PTMPS2

PTMPS0

0x0030

PBCTL

PBEN

0x0031

PBFLG

PBOVF

PA3H1

0x0032

PA3H

PA3H7

PA2H7

PA1H7

PA0H7

PA3H6

PA2H6

PA1H6

PA0H6

PA3H5

PA2H5

PA1H5

PA0H5

PA3H4

PA2H4

PA1H4

PA0H4

PA3H3

PA2H3

PA1H3

PA0H3

PA3H2

PA2H2

PA1H2

PA0H2

PA3H0

PA2H0

PA1H0

PA0H0

0x0033

PA2H

PA2H1

PA1H1

PA0H1

0x0034

PA1H

0x0035

PA0H

0x0036

MCCNT

(High)

MCCNT15 MCCNT14 MCCNT13 MCCNT12 MCCNT11 MCCNT10

MCCNT9

MCCNT8

0x0037

MCCNT

(Low)

MCCNT7

TC15

MCCNT6

TC14

MCCNT5

TC13

MCCNT4

TC12

MCCNT3

TC11

MCCNT2

TC10

MCCNT1

TC9

MCCNT9

TC8

0x0038

TC0H (High)

0x0039

TC7

TC6

TC5

TC4

TC3

TC2

TC1

TC0

TC0H (Low)

= Unimplemented or Reserved

Figure 11-2. ECT Register Summary (Sheet 4 of 5)

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

Bit 7

Bit 0

Name

0x003A

TC15

TC14

TC13

TC12

TC11

TC10

TC9

TC8

TC1H (High)

0x003B

TC1H (Low)

TC7

TC15

TC7

TC6

TC14

TC6

TC5

TC13

TC5

TC4

TC12

TC4

TC3

TC11

TC3

TC2

TC10

TC2

TC1

TC9

TC1

TC9

TC1

TC0

TC8

TC0

TC8

TC0

0x003C

TC2H (High)

0x003D

TC2H (Low)

0x003E

TC3H (High)

TC15

TC7

TC14

TC6

TC13

TC5

TC12

TC4

TC11

TC3

TC10

TC2

0x003F

TC3H (Low)

= Unimplemented or Reserved

Figure 11-2. ECT Register Summary (Sheet 5 of 5)

11.3.2.1 Timer Input Capture/Output Compare Select Register (TIOS)

Module Base + 0x0000

IOS7

IOS6

IOS5

IOS4

IOS3

IOS2

IOS1

IOS0

Reset

Figure 11-3. Timer Input Capture/Output Compare Register (TIOS)

Read or write: Anytime

All bits reset to zero.

Table 11-2. TIOS Field Descriptions

Description

Field

7:0

IOS[7:0]

Input Capture or Output Compare Channel Conﬁguration

0 The corresponding channel acts as an input capture.

1 The corresponding channel acts as an output compare.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.2 Timer Compare Force Register (CFORC)

Module Base + 0x0001

FOC7

FOC6

FOC5

FOC4

FOC3

FOC2

FOC1

FOC0

Reset

Figure 11-4. Timer Compare Force Register (CFORC)

Read or write: Anytime but reads will always return 0x0000 (1 state is transient).

All bits reset to zero.

Table 11-3. CFORC Field Descriptions

Field

Description

7:0

FOC[7:0]

Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set

causes the action which is programmed for output compare “x” to occur immediately. The action taken is the

same as if a successful comparison had just taken place with the TCx register except the interrupt ﬂag does not

get set.

Note: A successful channel 7 output compare overrides any channel 6:0 compares. If a forced output compare

on any channel occurs at the same time as the successful output compare, then the forced output compare

action will take precedence and the interrupt ﬂag will not get set.

11.3.2.3 Output Compare 7 Mask Register (OC7M)

Module Base + 0x0002

OC7M7

OC7M6

OC7M5

OC7M4

OC7M3

OC7M2

OC7M1

OC7M0

Reset

Figure 11-5. Output Compare 7 Mask Register (OC7M)

Read or write: Anytime

All bits reset to zero.

Table 11-4. OC7M Field Descriptions

Description

Field

7:0

Output Compare Mask Action for Channel 7:0

OC7M[7:0] 0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on

a successful channel 7 output compare, even if the corresponding pin is setup for output compare.

1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a

successful channel 7 output compare.

Note: The corresponding channel must also be setup for output compare (IOSx = 1) for data to be transferred

from the output compare 7 data register to the timer port.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.4 Output Compare 7 Data Register (OC7D)

Module Base + 0x0003

OC7D7

OC7D6

OC7D5

OC7D4

OC7D3

OC7D2

OC7D1

OC7D0

Reset

Figure 11-6. Output Compare 7 Data Register (OC7D)

Read or write: Anytime

All bits reset to zero.

Table 11-5. OC7D Field Descriptions

Description

Field

7:0

Output Compare 7 Data Bits — A channel 7 output compare can cause bits in the output compare 7 data

OC7D[7:0] register to transfer to the timer port data register depending on the output compare 7 mask register.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.5 Timer Count Register (TCNT)

Module Base + 0x0004

TCNT15

TCNT14

TCNT13

TCNT12

TCNT11

TCNT10

TCNT9

TCNT8

Reset

Figure 11-7. Timer Count Register High (TCNT)

Module Base + 0x0005

TCNT7

TCNT6

TCNT5

TCNT4

TCNT3

TCNT2

TCNT1

TCNT0

Reset

Figure 11-8. Timer Count Register Low (TCNT)

Read: Anytime

Write: Has no meaning or effect

All bits reset to zero.

Table 11-6. TCNT Field Descriptions

Description

Field

15:0

Timer Counter Bits — The 16-bit main timer is an up counter. A read to this register will return the current value

TCNT[15:0] of the counter. Access to the counter register will take place in one clock cycle.

Note: A separate read/write for high byte and low byte in test mode will give a different result than accessing

them as a word. The period of the ﬁrst count after a write to the TCNT registers may be a different size

because the write is not synchronized with the prescaler clock.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.6 Timer System Control Register 1 (TSCR1)

Module Base + 0x0006

TEN

TSWAI

TSFRZ

TFFCA

PRNT

Reset

= Unimplemented or Reserved

Figure 11-9. Timer System Control Register 1 (TSCR1)

Read or write: Anytime except PRNT bit is write once

All bits reset to zero.

Table 11-7. TSCR1 Field Descriptions

Field

Description

Timer Enable

TEN

0 Disables the main timer, including the counter. Can be used for reducing power consumption.

1 Allows the timer to function normally.

Note: If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator since the ÷64 is

generated by the timer prescaler.

Timer Module Stops While in Wait

TSWAI

0 Allows the timer module to continue running during wait.

1 Disables the timer counter, pulse accumulators and modulus down counter when the MCU is in wait mode.

Timer interrupts cannot be used to get the MCU out of wait.

Timer and Modulus Counter Stop While in Freeze Mode

TSFRZ

0 Allows the timer and modulus counter to continue running while in freeze mode.

1 Disables the timer and modulus counter whenever the MCU is in freeze mode. This is useful for emulation.

The pulse accumulators do not stop in freeze mode.

Timer Fast Flag Clear All

TFFCA

0 Allows the timer ﬂag clearing to function normally.

1 A read from an input capture or a write to the output compare channel registers causes the corresponding

channel ﬂag, CxF, to be cleared in the TFLG1 register. Any access to the TCNT register clears the TOF ﬂag

in the TFLG2 register. Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF ﬂags in the

PAFLG register. Any access to the PACN1 and PACN0 registers clears the PBOVF ﬂag in the PBFLG register.

Any access to the MCCNT register clears the MCZF ﬂag in the MCFLG register. This has the advantage of

eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental ﬂag

clearing due to unintended accesses.

Note: The ﬂags cannot be cleared via the normal ﬂag clearing mechanism (writing a one to the ﬂag) when

TFFCA = 1.

Precision Timer

PRNT

0 Enables legacy timer. Only bits DLY0 and DLY1 of the DLYCT register are used for the delay selection of the

delay counter. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler selection.

MCPR0 and MCPR1 bits of the MCCTL register are used for modulus down counter prescaler selection.

1 Enables precision timer. All bits in the DLYCT register are used for the delay selection, all bits of the PTPSR

prescaler Precision Timer Modulus Counter Prescaler selection.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.7 Timer Toggle On Overﬂow Register 1 (TTOV)

Module Base + 0x0007

TOV7

TOV6

TOV5

TOV4

TOV3

TOV2

TOV1

TOV0

Reset

Figure 11-10. Timer Toggle On Overﬂow Register 1 (TTOV)

Read or write: Anytime

All bits reset to zero.

Table 11-8. TTOV Field Descriptions

Description

Field

7:0

TOV[7:0]

Toggle On Overﬂow Bits — TOV97:0] toggles output compare pin on timer counter overﬂow. This feature only

takes effect when in output compare mode. When set, it takes precedence over forced output compare but not

channel 7 override events.

0 Toggle output compare pin on overﬂow feature disabled.

1 Toggle output compare pin on overﬂow feature enabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)

Module Base + 0x0008

OM7

OL7

OM6

OL6

OM5

OL5

OM4

OL4

Reset

Figure 11-11. Timer Control Register 1 (TCTL1)

Module Base + 0x0009

OM3

OL3

OM2

OL2

OM1

OL1

OM0

OL0

Reset

Figure 11-12. Timer Control Register 2 (TCTL2)

Read or write: Anytime

All bits reset to zero.

Table 11-9. TCTL1/TCTL2 Field Descriptions

Description

Field

OM[7:0]

7, 5, 3, 1

OMx — Output Mode

OLx — Output Level

These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful

OCx compare. When either OMx or OLx is one, the pin associated with OCx becomes an output tied to OCx.

See Table 11-10.

OL[7:0]

6, 4, 2, 0

Table 11-10. Compare Result Output Action

OMx

OLx

Action

Timer disconnected from output pin logic

Toggle OCx output line

Clear OCx output line to zero

Set OCx output line to one

NOTE

To enable output action by OMx and OLx bits on timer port, the

corresponding bit in OC7M should be cleared.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.9 Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4)

Module Base + 0x000A

EDG7B

EDG7A

EDG6B

EDG6A

EDG5B

EDG5A

EDG4B

EDG4A

Reset

Figure 11-13. Timer Control Register 3 (TCTL3)

Module Base + 0x000B

EDG3B

EDG3A

EDG2B

EDG2A

EDG1B

EDG1A

EDG0B

EDG0A

Reset

Figure 11-14. Timer Control Register 4 (TCTL4)

Read or write: Anytime

All bits reset to zero.

Table 11-11. TCTL3/TCTL4 Field Descriptions

Description

Field

EDG[7:0]B Input Capture Edge Control — These eight pairs of control bits conﬁgure the input capture edge detector

7, 5, 3, 1

circuits for each input capture channel. The four pairs of control bits in TCTL4 also conﬁgure the input capture

edge control for the four 8-bit pulse accumulators PAC0–PAC3.EDG0B and EDG0A in TCTL4 also determine the

active edge for the 16-bit pulse accumulator PACB. See Table 11-12.

EDG[7:0]A

6, 4, 2, 0

Table 11-12. Edge Detector Circuit Conﬁguration

EDGxB

EDGxA

Conﬁguration

Capture disabled

Capture on rising edges only

Capture on falling edges only

Capture on any edge (rising or falling)

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.10 Timer Interrupt Enable Register (TIE)

Module Base + 0x000C

C7I

C6I

C5I

C4I

C3I

C2I

C1I

C0I

Reset

Figure 11-15. Timer Interrupt Enable Register (TIE)

Read or write: Anytime

All bits reset to zero.

The bits C7I–C0I correspond bit-for-bit with the ﬂags in the TFLG1 status register.

Table 11-13. TIE Field Descriptions

Field

Description

Input Capture/Output Compare “x” Interrupt Enable

7:0

C[7:0]I

0 The corresponding ﬂag is disabled from causing a hardware interrupt.

1 The corresponding ﬂag is enabled to cause an interrupt.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.11 Timer System Control Register 2 (TSCR2)

Module Base + 0x000D

TOI

TCRE

PR2

PR1

PR0

Reset

= Unimplemented or Reserved

Figure 11-16. Timer System Control Register 2 (TSCR2)

Read or write: Anytime

All bits reset to zero.

Table 11-14. TSCR2 Field Descriptions

Description

Field

TOI

Timer Overﬂow Interrupt Enable

0 Timer overﬂow interrupt disabled.

1 Hardware interrupt requested when TOF ﬂag set.

Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful channel 7 output

compare. This mode of operation is similar to an up-counting modulus counter.

0 Counter reset disabled and counter free runs.

TCRE

1 Counter reset by a successful output compare on channel 7.

Note: If register TC7 = 0x0000 and TCRE = 1, then the TCNT register will stay at 0x0000 continuously. If register

TC7 = 0xFFFF and TCRE = 1, the TOF ﬂag will never be set when TCNT is reset from 0xFFFF to 0x0000.

2:0

PR[2:0]

Timer Prescaler Select — These three bits specify the division rate of the main Timer prescaler when the PRNT

bit of register TSCR1 is set to 0. The newly selected prescale factor will not take effect until the next synchronized

edge where all prescale counter stages equal zero. See Table 11-15.

Table 11-15. Prescaler Selection

PR2

PR1

PR0

Prescale Factor

128

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)

Module Base + 0x000E

C7F

C6F

C5F

C4F

C3F

C2F

C1F

C0F

Reset

Figure 11-17. Main Timer Interrupt Flag 1 (TFLG1)

Read: Anytime

Write used in the ﬂag clearing mechanism. Writing a one to the ﬂag clears the ﬂag. Writing a zero will not

affect the current status of the bit.

NOTE

When TFFCA = 1, the ﬂags cannot be cleared via the normal ﬂag clearing

mechanism (writing a one to the ﬂag). Reference Section 11.3.2.6, “Timer

System Control Register 1 (TSCR1)”.

All bits reset to zero.

TFLG1 indicates when interrupt conditions have occurred. The ﬂags can be cleared via the normal ﬂag

clearing mechanism (writing a one to the ﬂag) or via the fast ﬂag clearing mechanism (reference TFFCA

bit in Section 11.3.2.6, “Timer System Control Register 1 (TSCR1)”).

Use of the TFMOD bit in the ICSYS register in conjunction with the use of the ICOVW register allows a

timer interrupt to be generated after capturing two values in the capture and holding registers, instead of

generating an interrupt for every capture.

Table 11-16. TFLG1 Field Descriptions

Field

Description

7:0

C[7:0]F

Input Capture/Output Compare Channel “x” Flag — A CxF ﬂag is set when a corresponding input capture or

output compare is detected. C0F can also be set by 16-bit Pulse Accumulator B (PACB). C3F–C0F can also be

set by 8-bit pulse accumulators PAC3–PAC0.

If the delay counter is enabled, the CxF ﬂag will not be set until after the delay.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)

Module Base + 0x000F

TOF

Reset

= Unimplemented or Reserved

Figure 11-18. Main Timer Interrupt Flag 2 (TFLG2)

Read: Anytime

Write used in the ﬂag clearing mechanism. Writing a one to the ﬂag clears the ﬂag. Writing a zero will not

affect the current status of the bit.

NOTE

When TFFCA = 1, the ﬂag cannot be cleared via the normal ﬂag clearing

mechanism (writing a one to the ﬂag). Reference Section 11.3.2.6, “Timer

System Control Register 1 (TSCR1)”.

All bits reset to zero.

TFLG2 indicates when interrupt conditions have occurred. The ﬂag can be cleared via the normal ﬂag

clearing mechanism (writing a one to the ﬂag) or via the fast ﬂag clearing mechanism (Reference TFFCA

bit in Section 11.3.2.6, “Timer System Control Register 1 (TSCR1)”).

Table 11-17. TFLG2 Field Descriptions

Field

Description

Timer Overﬂow Flag — Set when 16-bit free-running timer overﬂows from 0xFFFF to 0x0000.

TOF

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.14 Timer Input Capture/Output Compare Registers 0–7

Module Base + 0x0010

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Reset

Figure 11-19. Timer Input Capture/Output Compare Register 0 High (TC0)

Module Base + 0x0011

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Figure 11-20. Timer Input Capture/Output Compare Register 0 Low (TC0)

Module Base + 0x0012

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Reset

Figure 11-21. Timer Input Capture/Output Compare Register 1 High (TC1)

Module Base + 0x0013

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Figure 11-22. Timer Input Capture/Output Compare Register 1 Low (TC1)

Module Base + 0x0014

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Reset

Figure 11-23. Timer Input Capture/Output Compare Register 2 High (TC2)

Module Base + 0x0015

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Figure 11-24. Timer Input Capture/Output Compare Register 2 Low (TC2)

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

Module Base + 0x0016

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Reset

Figure 11-25. Timer Input Capture/Output Compare Register 3 High (TC3)

Module Base + 0x0017

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Figure 11-26. Timer Input Capture/Output Compare Register 3 Low (TC3)

Module Base + 0x0018

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Reset

Figure 11-27. Timer Input Capture/Output Compare Register 4 High (TC4)

Module Base + 0x0019

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Figure 11-28. Timer Input Capture/Output Compare Register 4 Low (TC4)

Module Base + 0x001A

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Reset

Figure 11-29. Timer Input Capture/Output Compare Register 5 High (TC5)

Module Base + 0x001B

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Figure 11-30. Timer Input Capture/Output Compare Register 5 Low (TC5)

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

Module Base + 0x001C

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Reset

Figure 11-31. Timer Input Capture/Output Compare Register 6 High (TC6)

Module Base + 0x001D

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Figure 11-32. Timer Input Capture/Output Compare Register 6 Low (TC6)

Module Base + 0x001E

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Reset

Figure 11-33. Timer Input Capture/Output Compare Register 7 High (TC7)

Module Base + 0x001F

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Figure 11-34. Timer Input Capture/Output Compare Register 7 Low (TC7)

Read: Anytime

Write anytime for output compare function. Writes to these registers have no meaning or effect during

input capture.

All bits reset to zero.

Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the

free-running counter when a deﬁned transition is sensed by the corresponding input capture edge detector

or to trigger an output action for output compare.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.15 16-Bit Pulse Accumulator A Control Register (PACTL)

Module Base + 0x0020

PAEN

PAMOD

PEDGE

CLK1

CLK0

PAOVI

PAI

Reset

= Unimplemented or Reserved

Figure 11-35. 16-Bit Pulse Accumulator Control Register (PACTL)

Read: Anytime

Write: Anytime

All bits reset to zero.

Table 11-18. PACTL Field Descriptions

Description

Field

Pulse Accumulator A System Enable — PAEN is independent from TEN. With timer disabled, the pulse

accumulator can still function unless pulse accumulator is disabled.

PAEN

0 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and PAC2 can be enabled when their related enable

bits in ICPAR are set. Pulse Accumulator Input Edge Flag (PAIF) function is disabled.

1 16-Bit Pulse Accumulator A system enabled. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded

to form the PACA 16-bit pulse accumulator. When PACA in enabled, the PACN3 and PACN2 registers contents

are respectively the high and low byte of the PACA. PA3EN and PA2EN control bits in ICPAR have no effect.

Pulse Accumulator Input Edge Flag (PAIF) function is enabled. The PACA shares the input pin with IC7.

Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1).

PAMOD

0 Event counter mode

1 Gated time accumulation mode

Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator A is enabled

PEDGE

(PAEN = 1). Refer to Table 11-19.

For PAMOD bit = 0 (event counter mode).

0 Falling edges on PT7 pin cause the count to be incremented

1 Rising edges on PT7 pin cause the count to be incremented

For PAMOD bit = 1 (gated time accumulation mode).

0 PT7 input pin high enables bus clock divided by 64 to Pulse Accumulator and the trailing falling edge on PT7

sets the PAIF ﬂag.

1 PT7 input pin low enables bus clock divided by 64 to Pulse Accumulator and the trailing rising edge on PT7

sets the PAIF ﬂag.

If the timer is not active (TEN = 0 in TSCR1), there is no divide-by-64 since the ÷64 clock is generated by the

timer prescaler.

3:2

Clock Select Bits — For the description of PACLK please refer to Figure 11-70.

CLK[1:0]

If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input

clock to the timer counter. The change from one selected clock to the other happens immediately after these bits

are written. Refer to Table 11-20.

Pulse Accumulator A Overﬂow Interrupt Enable

0 Interrupt inhibited

PAOVI

1 Interrupt requested if PAOVF is set

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

Table 11-18. PACTL Field Descriptions (continued)

Field

Description

PAI

Pulse Accumulator Input Interrupt Enable

0 Interrupt inhibited

1 Interrupt requested if PAIF is set

Table 11-19. Pin Action

PAMOD

PEDGE

Pin Action

Falling edge

Rising edge

Divide by 64 clock enabled with pin high level

Divide by 64 clock enabled with pin low level

Table 11-20. Clock Selection

Clock Source

CLK1

CLK0

Use timer prescaler clock as timer counter clock

Use PACLK as input to timer counter clock

Use PACLK/256 as timer counter clock frequency

Use PACLK/65536 as timer counter clock frequency

11.3.2.16 Pulse Accumulator A Flag Register (PAFLG)

Module Base + 0x0021

PAOVF

PAIF

Reset

= Unimplemented or Reserved

Figure 11-36. Pulse Accumulator A Flag Register (PAFLG)

Read: Anytime

Write used in the ﬂag clearing mechanism. Writing a one to the ﬂag clears the ﬂag. Writing a zero will not

affect the current status of the bit.

NOTE

When TFFCA = 1, the ﬂags cannot be cleared via the normal ﬂag clearing

mechanism (writing a one to the ﬂag). Reference Section 11.3.2.6, “Timer

System Control Register 1 (TSCR1)”.

All bits reset to zero.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

PAFLG indicates when interrupt conditions have occurred. The ﬂags can be cleared via the normal ﬂag

clearing mechanism (writing a one to the ﬂag) or via the fast ﬂag clearing mechanism (Reference TFFCA

bit in Section 11.3.2.6, “Timer System Control Register 1 (TSCR1)”).

Table 11-21. PAFLG Field Descriptions

Field

Description

Pulse Accumulator A Overﬂow Flag — Set when the 16-bit pulse accumulator A overﬂows from 0xFFFF to

PAOVF

0x0000, or when 8-bit pulse accumulator 3 (PAC3) overﬂows from 0x00FF to 0x0000.

When PACMX = 1, PAOVF bit can also be set if 8-bit pulse accumulator 3 (PAC3) reaches 0x00FF followed by

an active edge on PT3.

PAIF

Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the PT7 input pin. In event

mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at

the PT7 input pin triggers PAIF.

11.3.2.17 Pulse Accumulators Count Registers (PACN3 and PACN2)

Module Base + 0x0022

PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) PACNT1(9) PACNT0(8)

Reset

Figure 11-37. Pulse Accumulators Count Register 3 (PACN3)

Module Base + 0x0023

PACNT7

PACNT6

PACNT5

PACNT4

PACNT3

PACNT2

PACNT1

PACNT0

Reset

Figure 11-38. Pulse Accumulators Count Register 2 (PACN2)

Read: Anytime

Write: Anytime

All bits reset to zero.

The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse

accumulator. When PACA in enabled (PAEN = 1 in PACTL), the PACN3 and PACN2 registers contents

are respectively the high and low byte of the PACA.

When PACN3 overﬂows from 0x00FF to 0x0000, the interrupt ﬂag PAOVF in PAFLG is set.

Full count register access will take place in one clock cycle.

NOTE

A separate read/write for high byte and low byte will give a different result

than accessing them as a word.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

533

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

When clocking pulse and write to the registers occurs simultaneously, write

takes priority and the register is not incremented.

11.3.2.18 Pulse Accumulators Count Registers (PACN1 and PACN0)

Module Base + 0x0024

PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) PACNT1(9) PACNT0(8)

Reset

Figure 11-39. Pulse Accumulators Count Register 1 (PACN1)

Module Base + 0x0025

PACNT7

PACNT6

PACNT5

PACNT4

PACNT3

PACNT2

PACNT1

PACNT0

Reset

Figure 11-40. Pulse Accumulators Count Register 0 (PACN0)

Read: Anytime

Write: Anytime

All bits reset to zero.

The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse

accumulator. When PACB in enabled, (PBEN = 1 in PBCTL) the PACN1 and PACN0 registers contents

are respectively the high and low byte of the PACB.

When PACN1 overﬂows from 0x00FF to 0x0000, the interrupt ﬂag PBOVF in PBFLG is set.

Full count register access will take place in one clock cycle.

NOTE

A separate read/write for high byte and low byte will give a different result

than accessing them as a word.

When clocking pulse and write to the registers occurs simultaneously, write

takes priority and the register is not incremented.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.19 16-Bit Modulus Down-Counter Control Register (MCCTL)

Module Base + 0x0026

MCZI

MODMC

RDMCL

MCEN

MCPR1

MCPR0

ICLAT

FLMC

Reset

Figure 11-41. 16-Bit Modulus Down-Counter Control Register (MCCTL)

Read: Anytime

Write: Anytime

All bits reset to zero.

Table 11-22. MCCTL Field Descriptions

Description

Field

Modulus Counter Underﬂow Interrupt Enable

0 Modulus counter interrupt is disabled.

MCZI

1 Modulus counter interrupt is enabled.

Modulus Mode Enable

MODMC

0 The modulus counter counts down from the value written to it and will stop at 0x0000.

1 Modulus mode is enabled. When the modulus counter reaches 0x0000, the counter is loaded with the latest

value written to the modulus count register.

Note: For proper operation, the MCEN bit should be cleared before modifying the MODMC bit in order to reset

the modulus counter to 0xFFFF.

Read Modulus Down-Counter Load

RDMCL

0 Reads of the modulus count register (MCCNT) will return the present value of the count register.

1 Reads of the modulus count register (MCCNT) will return the contents of the load register.

Input Capture Force Latch Action — When input capture latch mode is enabled (LATQ and BUFEN bit in

ICSYS are set), a write one to this bit immediately forces the contents of the input capture registers TC0 to TC3

and their corresponding 8-bit pulse accumulators to be latched into the associated holding registers. The pulse

accumulators will be automatically cleared when the latch action occurs.

ICLAT

Writing zero to this bit has no effect. Read of this bit will always return zero.

Force Load Register into the Modulus Counter Count Register — This bit is active only when the modulus

FLMC

down-counter is enabled (MCEN = 1).

A write one into this bit loads the load register into the modulus counter count register (MCCNT). This also resets

the modulus counter prescaler.

Write zero to this bit has no effect. Read of this bit will return always zero.

Modulus Down-Counter Enable

MCEN

0 Modulus counter disabled. The modulus counter (MCCNT) is preset to 0xFFFF. This will prevent an early

interrupt ﬂag when the modulus down-counter is enabled.

1 Modulus counter is enabled.

1:0

Modulus Counter Prescaler Select — These two bits specify the division rate of the modulus counter prescaler

MCPR[1:0] when PRNT of TSCR1 is set to 0. The newly selected prescaler division rate will not be effective until a load of

the load register into the modulus counter count register occurs.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

Table 11-23. Modulus Counter Prescaler Select

MCPR1

MCPR0

Prescaler Division

11.3.2.20 16-Bit Modulus Down-Counter FLAG Register (MCFLG)

Module Base + 0x0027

POLF3

POLF2

POLF1

POLF0

MCZF

Reset

= Unimplemented or Reserved

Figure 11-42. 16-Bit Modulus Down-Counter FLAG Register (MCFLG)

Read: Anytime

Write only used in the ﬂag clearing mechanism for bit 7. Writing a one to bit 7 clears the ﬂag. Writing a

zero will not affect the current status of the bit.

NOTE

When TFFCA = 1, the ﬂag cannot be cleared via the normal ﬂag clearing

mechanism (writing a one to the ﬂag). Reference Section 11.3.2.6, “Timer

System Control Register 1 (TSCR1)”.

All bits reset to zero.

Table 11-24. MCFLG Field Descriptions

Field

Description

Modulus Counter Underﬂow Flag — The ﬂag is set when the modulus down-counter reaches 0x0000.

MCZF

The ﬂag indicates when interrupt conditions have occurred. The ﬂag can be cleared via the normal ﬂag clearing

mechanism (writing a one to the ﬂag) or via the fast ﬂag clearing mechanism (Reference TFFCA bit in

Section 11.3.2.6, “Timer System Control Register 1 (TSCR1)”).

3:0

First Input Capture Polarity Status — These are read only bits. Writes to these bits have no effect.

POLF[3:0]

Each status bit gives the polarity of the ﬁrst edge which has caused an input capture to occur after capture latch

has been read.

Each POLFx corresponds to a timer PORTx input.

0 The ﬁrst input capture has been caused by a falling edge.

1 The ﬁrst input capture has been caused by a rising edge.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.21 ICPAR — Input Control Pulse Accumulators Register (ICPAR)

Module Base + 0x0028

PA3EN

PA2EN

PA1EN

PA0EN

Reset

= Unimplemented or Reserved

Figure 11-43. Input Control Pulse Accumulators Register (ICPAR)

Read: Anytime

Write: Anytime.

All bits reset to zero.

The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if PAEN in PACTL is cleared. If PAEN

is set, PA3EN and PA2EN have no effect.

The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if PBEN in PBCTL is cleared. If PBEN

is set, PA1EN and PA0EN have no effect.

Table 11-25. ICPAR Field Descriptions

Field

Description

3:0

8-Bit Pulse Accumulator ‘x’ Enable

PA[3:0]EN 0 8-Bit Pulse Accumulator is disabled.

1 8-Bit Pulse Accumulator is enabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.22 Delay Counter Control Register (DLYCT)

Module Base + 0x0029

DLY7

DLY6

DLY5

DLY4

DLY3

DLY2

DLY1

DLY0

Reset

Figure 11-44. Delay Counter Control Register (DLYCT)

Read: Anytime

Write: Anytime

All bits reset to zero.

Table 11-26. DLYCT Field Descriptions

Description

Field

7:0

Delay Counter Select — When the PRNT bit of TSCR1 register is set to 0, only bits DLY0, DLY1 are used to

DLY[7:0]

calculate the delay.Table 11-27 shows the delay settings in this case.

When the PRNT bit of TSCR1 register is set to 1, all bits are used to set a more precise delay. Table 11-28 shows

the delay settings in this case. After detection of a valid edge on an input capture pin, the delay counter counts

the pre-selected number of [(dly_cnt + 1)*4]bus clock cycles, then it will generate a pulse on its output if the level

of input signal, after the preset delay, is the opposite of the level before the transition.This will avoid reaction to

narrow input pulses.

Delay between two active edges of the input signal period should be longer than the selected counter delay.

Note: It is recommended to not write to this register while the timer is enabled, that is when TEN is set in register

TSCR1.

Table 11-27. Delay Counter Select when PRNT = 0

DLY1

DLY0

Delay

Disabled

256 bus clock cycles

512 bus clock cycles

1024 bus clock cycles

Table 11-28. Delay Counter Select Examples when PRNT = 1

DLY7

DLY6

DLY5

DLY4

DLY3

DLY2

DLY1

DLY0

Delay

Disabled (bypassed)

8 bus clock cycles

12 bus clock cycles

16 bus clock cycles

20 bus clock cycles

24 bus clock cycles

28 bus clock cycles

32 bus clock cycles

64 bus clock cycles

128 bus clock cycles

256 bus clock cycles

512 bus clock cycles

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

Table 11-28. Delay Counter Select Examples when PRNT = 1

DLY7

DLY6

DLY5

DLY4

DLY3

DLY2

DLY1

DLY0

Delay

1024 bus clock cycles

11.3.2.23 Input Control Overwrite Register (ICOVW)

Module Base + 0x002A

NOVW7

NOVW6

NOVW5

NOVW4

NOVW3

NOVW2

NOVW1

NOVW0

Reset

Figure 11-45. Input Control Overwrite Register (ICOVW)

Read: Anytime

Write: Anytime

All bits reset to zero.

Table 11-29. ICOVW Field Descriptions

Description

Field

7:0

No Input Capture Overwrite

NOVW[7:0] 0 The contents of the related capture register or holding register can be overwritten when a new input capture

or latch occurs.

1 The related capture register or holding register cannot be written by an event unless they are empty (see

Section 11.4.1.1, “IC Channels”). This will prevent the captured value being overwritten until it is read or

latched in the holding register.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.24 Input Control System Control Register (ICSYS)

Module Base + 0x002B

SH37

SH26

SH15

SH04

TFMOD

PACMX

BUFEN

LATQ

Reset

Figure 11-46. Input Control System Register (ICSYS)

Read: Anytime

Write: Once in normal modes

All bits reset to zero.

Table 11-30. ICSYS Field Descriptions

Description

Field

7:4

SHxy

Share Input action of Input Capture Channels x and y

0 Normal operation

1 The channel input ‘x’ causes the same action on the channel ‘y’. The port pin ‘x’ and the corresponding edge

detector is used to be active on the channel ‘y’.

Timer Flag Setting Mode — Use of the TFMOD bit in conjunction with the use of the ICOVW register allows a

timer interrupt to be generated after capturing two values in the capture and holding registers instead of

generating an interrupt for every capture.

TFMOD

By setting TFMOD in queue mode, when NOVWx bit is set and the corresponding capture and holding registers

are emptied, an input capture event will ﬁrst update the related input capture register with the main timer

contents. At the next event, the TCx data is transferred to the TCxH register, the TCx is updated and the CxF

interrupt ﬂag is set. In all other input capture cases the interrupt ﬂag is set by a valid external event on PTx.

0 The timer ﬂags C3F–C0F in TFLG1 are set when a valid input capture transition on the corresponding port pin

occurs.

1 If in queue mode (BUFEN = 1 and LATQ = 0), the timer ﬂags C3F–C0F in TFLG1 are set only when a latch

on the corresponding holding register occurs. If the queue mode is not engaged, the timer ﬂags C3F–C0F are

set the same way as for TFMOD = 0.

8-Bit Pulse Accumulators Maximum Count

PACMX

0 Normal operation. When the 8-bit pulse accumulator has reached the value 0x00FF, with the next active edge,

it will be incremented to 0x0000.

1 When the 8-bit pulse accumulator has reached the value 0x00FF, it will not be incremented further. The value

0x00FF indicates a count of 255 or more.

IC Buffer Enable

BUFFEN

0 Input capture and pulse accumulator holding registers are disabled.

1 Input capture and pulse accumulator holding registers are enabled. The latching mode is deﬁned by LATQ

control bit.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

Table 11-30. ICSYS Field Descriptions (continued)

Field

Description

Input Control Latch or Queue Mode Enable — The BUFEN control bit should be set in order to enable the IC

LATQ

and pulse accumulators holding registers. Otherwise LATQ latching modes are disabled.

Write one into ICLAT bit in MCCTL, when LATQ and BUFEN are set will produce latching of input capture and

pulse accumulators registers into their holding registers.

0 Queue mode of Input Capture is enabled. The main timer value is memorized in the IC register by a valid input

pin transition. With a new occurrence of a capture, the value of the IC register will be transferred to its holding

1 Latch mode is enabled. Latching function occurs when modulus down-counter reaches zero or a zero is

written into the count register MCCNT (see Section 11.4.1.1.2, “Buffered IC Channels”). With a latching event

the contents of IC registers and 8-bit pulse accumulators are transferred to their holding registers. 8-bit pulse

accumulators are cleared.

11.3.2.25 Precision Timer Prescaler Select Register (PTPSR)

Module Base + 0x002E

PTPS7

PTPS6

PTPS5

PTPS4

PTPS3

PTPS2

PTPS1

PTPS0

Reset

Figure 11-47. Precision Timer Prescaler Select Register (PTPSR)

Read: Anytime

Write: Anytime

All bits reset to zero.

Table 11-31. PTPSR Field Descriptions

Description

Field

7:0

Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler.

PTPS[7:0] These are effective only when the PRNT bit of TSCR1 is set to 1. Table 11-32 shows some selection examples

in this case.

The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter

stages equal zero.

Table 11-32. Precision Timer Prescaler Selection Examples when PRNT = 1

Prescale

PTPS7

PTPS6

PTPS5

PTPS4

PTPS3

PTPS2

PTPS1

PTPS0

Factor

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

Table 11-32. Precision Timer Prescaler Selection Examples when PRNT = 1

Prescale

Factor

PTPS7

PTPS6

PTPS5

PTPS4

PTPS3

PTPS2

PTPS1

PTPS0

128

256

11.3.2.26 Precision Timer Modulus Counter Prescaler Select Register (PTMCPSR)

Module Base + 0x002F

PTMPS7

PTMPS6

PTMPS5

PTMPS4

PTMPS3

PTMPS2

PTMPS1

PTMPS0

Reset

Figure 11-48. Precision Timer Modulus Counter Prescaler Select Register (PTMCPSR)

Read: Anytime

Write: Anytime

All bits reset to zero.

Table 11-33. PTMCPSR Field Descriptions

Description

Field

7:0

Precision Timer Modulus Counter Prescaler Select Bits — These eight bits specify the division rate of the

PTMPS[7:0] modulus counter prescaler. These are effective only when the PRNT bit of TSCR1 is set to 1. Table 11-34 shows

some possible division rates.

The newly selected prescaler division rate will not be effective until a load of the load register into the modulus

counter count register occurs.

Table 11-34. Precision Timer Modulus Counter Prescaler Select Examples when PRNT = 1

Prescaler

PTMPS7

PTMPS6

PTMPS5

PTMPS4

PTMPS3

PTMPS2

PTMPS1

PTMPS0

Division

Rate

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

Table 11-34. Precision Timer Modulus Counter Prescaler Select Examples when PRNT = 1 (continued)

Prescaler

PTMPS7

PTMPS6

PTMPS5

PTMPS4

PTMPS3

PTMPS2

PTMPS1

PTMPS0

Division

Rate

128

256

11.3.2.27 16-Bit Pulse Accumulator B Control Register (PBCTL)

Module Base + 0x0030

PBEN

PBOVI

Reset

= Unimplemented or Reserved

Figure 11-49. 16-Bit Pulse Accumulator B Control Register (PBCTL)

Read: Anytime

Write: Anytime

All bits reset to zero.

Table 11-35. PBCTL Field Descriptions

Description

Field

Pulse Accumulator B System Enable — PBEN is independent from TEN. With timer disabled, the pulse

accumulator can still function unless pulse accumulator is disabled.

0 16-bit pulse accumulator system disabled. 8-bit PAC1 and PAC0 can be enabled when their related enable

bits in ICPAR are set.

PBEN

1 Pulse accumulator B system enabled. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form

the PACB 16-bit pulse accumulator B. When PACB is enabled, the PACN1 and PACN0 registers contents are

respectively the high and low byte of the PACB.

PA1EN and PA0EN control bits in ICPAR have no effect.

The PACB shares the input pin with IC0.

Pulse Accumulator B Overﬂow Interrupt Enable

0 Interrupt inhibited

PBOVI

1 Interrupt requested if PBOVF is set

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.28 Pulse Accumulator B Flag Register (PBFLG)

Module Base + 0x0031

PBOVF

Reset

= Unimplemented or Reserved

Figure 11-50. Pulse Accumulator B Flag Register (PBFLG)

Read: Anytime

Write used in the ﬂag clearing mechanism. Writing a one to the ﬂag clears the ﬂag. Writing a zero will not

affect the current status of the bit.

NOTE

When TFFCA = 1, the ﬂag cannot be cleared via the normal ﬂag clearing

mechanism (writing a one to the ﬂag). Reference Section 11.3.2.6, “Timer

System Control Register 1 (TSCR1)”.

All bits reset to zero.

PBFLG indicates when interrupt conditions have occurred. The ﬂag can be cleared via the normal ﬂag

clearing mechanism (writing a one to the ﬂag) or via the fast ﬂag clearing mechanism (Reference TFFCA

bit in Section 11.3.2.6, “Timer System Control Register 1 (TSCR1)”).

Table 11-36. PBFLG Field Descriptions

Field

Description

Pulse Accumulator B Overﬂow Flag — This bit is set when the 16-bit pulse accumulator B overﬂows from

PBOVF

0xFFFF to 0x0000, or when 8-bit pulse accumulator 1 (PAC1) overﬂows from 0x00FF to 0x0000.

When PACMX = 1, PBOVF bit can also be set if 8-bit pulse accumulator 1 (PAC1) reaches 0x00FF and an active

edge follows on PT1.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.29 8-Bit Pulse Accumulators Holding Registers (PA3H–PA0H)

Module Base + 0x0032

PA3H7

PA3H6

PA3H5

PA3H4

PA3H3

PA3H2

PA3H1

PA3H0

Reset

= Unimplemented or Reserved

Figure 11-51. 8-Bit Pulse Accumulators Holding Register 3 (PA3H)

Module Base + 0x0033

PA2H7

PA2H6

PA2H5

PA2H4

PA2H3

PA2H2

PA2H1

PA2H0

Reset

= Unimplemented or Reserved

Figure 11-52. 8-Bit Pulse Accumulators Holding Register 2 (PA2H)

Module Base + 0x0034

PA1H7

PA1H6

PA1H5

PA1H4

PA1H3

PA1H2

PA1H1

PA1H0

Reset

= Unimplemented or Reserved

Figure 11-53. 8-Bit Pulse Accumulators Holding Register 1 (PA1H)

Module Base + 0x0035

PA0H7

PA0H6

PA0H5

PA0H4

PA0H3

PA0H2

PA0H1

PA0H0

Reset

= Unimplemented or Reserved

Figure 11-54. 8-Bit Pulse Accumulators Holding Register 0 (PA0H)

Read: Anytime.

Write: Has no effect.

All bits reset to zero.

These registers are used to latch the value of the corresponding pulse accumulator when the related bits in

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.30 Modulus Down-Counter Count Register (MCCNT)

Module Base + 0x0036

MCCNT15

MCCNT14

MCCNT13

MCCNT12

MCCNT11

MCCNT10

MCCNT9

MCCNT8

Reset

Figure 11-55. Modulus Down-Counter Count Register High (MCCNT)

Module Base + 0x0037

MCCNT7

MCCNT6

MCCNT5

MCCNT4

MCCNT3

MCCNT2

MCCNT1

MCCNT9

Reset

Figure 11-56. Modulus Down-Counter Count Register Low (MCCNT)

Read: Anytime

Write: Anytime.

All bits reset to one.

A full access for the counter register will take place in one clock cycle.

NOTE

A separate read/write for high byte and low byte will give different results

than accessing them as a word.

If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT register will return the present value

of the count register. If the RDMCL bit is set, reads of the MCCNT will return the contents of the load

If a 0x0000 is written into MCCNT when LATQ and BUFEN in ICSYS register are set, the input capture

and pulse accumulator registers will be latched.

With a 0x0000 write to the MCCNT, the modulus counter will stay at zero and does not set the MCZF ﬂag

in MCFLG register.

If the modulus down counter is enabled (MCEN = 1) and modulus mode is enabled (MODMC = 1), a write

to MCCNT will update the load register with the value written to it. The count register will not be updated

with the new value until the next counter underﬂow.

If modulus mode is not enabled (MODMC = 0), a write to MCCNT will clear the modulus prescaler and

will immediately update the counter register with the value written to it and down-counts to 0x0000 and

stops.

The FLMC bit in MCCTL can be used to immediately update the count register with the new value if an

immediate load is desired.

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.3.2.31 Timer Input Capture Holding Registers 0–3 (TCxH)

Module Base + 0x0038

TC15

TC14

TC13

TC12

TC11

TC10

TC9

TC8

Reset

= Unimplemented or Reserved

Figure 11-57. Timer Input Capture Holding Register 0 High (TC0H)

Module Base + 0x0039

TC7

TC6

TC5

TC4

TC3

TC2

TC1

TC0

Reset

= Unimplemented or Reserved

Figure 11-58. Timer Input Capture Holding Register 0 Low (TC0H)

Module Base + 0x003A

TC15

TC14

TC13

TC12

TC11

TC10

TC9

TC8

Reset

= Unimplemented or Reserved

Figure 11-59. Timer Input Capture Holding Register 1 High (TC1H)

Module Base + 0x003B

TC7

TC6

TC5

TC4

TC3

TC2

TC1

TC0

Reset

= Unimplemented or Reserved

Figure 11-60. Timer Input Capture Holding Register 1 Low (TC1H)

Module Base + 0x003C

TC15

TC14

TC13

TC12

TC11

TC10

TC9

TC8

Reset

= Unimplemented or Reserved

Figure 11-61. Timer Input Capture Holding Register 2 High (TC2H)

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

Module Base + 0x003D

TC7

TC6

TC5

TC4

TC3

TC2

TC1

TC0

Reset

= Unimplemented or Reserved

Figure 11-62. Timer Input Capture Holding Register 2 Low (TC2H)

Module Base + 0x003E

TC15

TC14

TC13

TC12

TC11

TC10

TC9

TC8

Reset

= Unimplemented or Reserved

Figure 11-63. Timer Input Capture Holding Register 3 High (TC3H)

Module Base + 0x003F

TC7

TC6

TC5

TC4

TC3

TC2

TC1

TC0

Reset

= Unimplemented or Reserved

Figure 11-64. Timer Input Capture Holding Register 3 Low (TC3H)

Read: Anytime

Write: Has no effect.

All bits reset to zero.

These registers are used to latch the value of the input capture registers TC0–TC3. The corresponding

IOSx bits in TIOS should be cleared (see Section 11.4.1.1, “IC Channels”).

11.4 Functional Description

This section provides a complete functional description of the ECT block, detailing the operation of the

design from the end user perspective in a number of subsections.

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

16-Bit Free-Running

16 BIT MAIN TIMER

16-Bit Load Register

÷ 1, 2, ..., 128

Main Timer

÷ 1, 4, 8, 16

16-Bit Modulus

Down Counter

Bus Clock

Modulus Prescaler

Bus Clock

Timer Prescaler

RESET

Comparator

Pin Logic

Delay

Counter

TC0 Capture/Compare Reg.

PAC0

EDG0

EDG1

EDG2

EDG3

TC0H Hold Reg.

PA0H Hold Reg.

RESET

Comparator

Delay

Counter

TC1 Capture/Compare Reg.

PAC1

TC1H Hold Reg.

PA1H Hold Reg.

RESET

Comparator

Delay

Counter

TC2 Capture/Compare Reg.

PAC2

TC2H Hold Reg.

PA2H Hold Reg.

RESET

Comparator

Delay

Counter

TC3 Capture/Compare Reg.

PAC3

TC3H Hold Reg.

PA3H Hold Reg.

Comparator

EDG4

TC4 Capture/Compare Reg.

MUX

ICLAT, LATQ, BUFEN

(Force Latch)

EDG0

SH04

Comparator

Pin Logic

EDG5

EDG1

TC5 Capture/Compare Reg.

Write 0x0000

to Modulus Counter

SH15

LATQ

(MDC Latch Enable)

Comparator

EDG6

TC6 Capture/Compare Reg.

MUX

EDG2

SH26

Comparator

EDG7

TC7 Capture/Compare Reg.

EDG3

SH37

Figure 11-65. Detailed Timer Block Diagram in Latch Mode when PRNT = 0

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

16-Bit Free-Running

16 BIT MAIN TIMER

16-Bit Load Register

÷ 1, 2,3, ..., 256

Main Timer

÷ 1, 2,3, ..., 256

16-Bit Modulus

Down Counter

Bus Clock

Modulus Prescaler

Bus Clock

Timer Prescaler

RESET

Comparator

Pin Logic

Delay

Counter

TC0 Capture/Compare Reg.

PAC0

EDG0

8, 12, 16, ..., 1024

TC0H Hold Reg.

PA0H Hold Reg.

RESET

Comparator

Delay

Counter

TC1 Capture/Compare Reg.

PAC1

EDG1

8, 12, 16, ..., 1024

TC1H Hold Reg.

PA1H Hold Reg.

RESET

Comparator

Delay

Counter

TC2 Capture/Compare Reg.

PAC2

EDG2

8, 12, 16, ..., 1024

TC2H Hold Reg.

PA2H Hold Reg.

RESET

Comparator

Delay

Counter

TC3 Capture/Compare Reg.

PAC3

EDG3

8, 12, 16, ..., 1024

TC3H Hold Reg.

PA3H Hold Reg.

Comparator

EDG4

MUX

TC4 Capture/Compare Reg.

ICLAT, LATQ, BUFEN

(Force Latch)

EDG0

SH04

Comparator

Pin Logic

EDG5

TC5 Capture/Compare Reg.

Write 0x0000

to Modulus Counter

MUX

EDG1

SH15

LATQ

(MDC Latch Enable)

Comparator

EDG6

TC6 Capture/Compare Reg.

EDG2

SH26

Comparator

EDG7

TC7 Capture/Compare Reg.

EDG3

SH37

Figure 11-66. Detailed Timer Block Diagram in Latch Mode when PRNT = 1

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

÷1, 2, ..., 128

Timer

Prescaler

16-Bit Free-Running

16-Bit Load Register

Bus Clock

16 BIT MAIN TIMER

Main Timer

÷ 1, 4, 8, 16

16-Bit Modulus

Down Counter

Modulus

Prescaler

Bus Clock

RESET

Comparator

Pin Logic

Delay

Counter

TC0 Capture/Compare Reg.

PAC0

EDG0

EDG1

EDG2

EDG3

TC0H Hold Reg.

PA0H Hold Reg.

RESET

Comparator

Delay

Counter

TC1 Capture/Compare Reg.

PAC1

TC1H Hold Reg.

PA1H Hold Reg.

RESET

Comparator

Delay

Counter

TC2 Capture/Compare Reg.

PAC2

PA2H Hold Reg.

TC2H Hold Reg.

RESET

Comparator

Delay

Counter

TC3 Capture/Compare Reg.

PAC3

TC3H Hold Reg.

PA3H Hold Reg.

Comparator

LATQ, BUFEN

(Queue Mode)

EDG4

EDG0

TC4 Capture/Compare Reg.

MUX

SH04

EDG5

EDG1

Read TC3H

Hold Reg.

Comparator

Pin Logic

TC5 Capture/Compare Reg.

MUX

Read TC2H

Hold Reg.

SH15

Comparator

EDG6

EDG2

TC6 Capture/Compare Reg.

MUX

Read TC1H

Hold Reg.

SH26

Comparator

Read TC0H

Hold Reg.

EDG7

TC7 Capture/Compare Reg.

MUX

EDG3

SH37

Figure 11-67. Detailed Timer Block Diagram in Queue Mode when PRNT = 0

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

÷1, 2, 3, ... 256

16-Bit Free-Running

Timer

Prescaler

16-Bit Load Register

Bus Clock

÷ 1, 2, 3, ... 256

16 BIT MAIN TIMER

Main Timer

16-Bit Modulus

Down Counter

Modulus

Prescaler

Bus Clock

RESET

Comparator

Pin Logic

Delay

Counter

TC0 Capture/Compare Reg.

PAC0

EDG0

8, 12, 16, ... 1024

TC0H Hold Reg.

PA0H Hold Reg.

RESET

Comparator

Pin Logic

Delay

Counter

TC1 Capture/Compare Reg.

PAC1

EDG1

8, 12, 16, ... 1024

TC1H Hold Reg.

PA1H Hold Reg.

RESET

Comparator

Delay

Counter

TC2 Capture/Compare Reg.

PAC2

EDG2

8, 12, 16, ... 1024

PA2H Hold Reg.

TC2H Hold Reg.

RESET

Comparator

Delay

Counter

TC3 Capture/Compare Reg.

PAC3

EDG3

8, 12, 16, ... 1024

TC3H Hold Reg.

PA3H Hold Reg.

Comparator

LATQ, BUFEN

Pin Logic

EDG4

MUX

TC4 Capture/Compare Reg.

(Queue Mode)

EDG0

SH04

EDG5

EDG1

Read TC3H

Hold Reg.

Comparator

TC5 Capture/Compare Reg.

MUX

Read TC2H

Hold Reg.

SH15

Comparator

Pin Logic

EDG6

EDG2

TC6 Capture/Compare Reg.

MUX

Read TC1H

Hold Reg.

SH26

Comparator

Read TC0H

Hold Reg.

EDG7

TC7 Capture/Compare Reg.

MUX

EDG3

SH37

Figure 11-68. Detailed Timer Block Diagram in Queue Mode when PRNT = 1

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

Load Holding Register and Reset Pulse Accumulator

8, 12,16, ..., 1024

Delay Counter

EDG0

8-Bit PAC0 (PACN0)

Edge Detector

PA0H Holding

Interrupt

8, 12,16, ..., 1024

Delay Counter

EDG1

8-Bit PAC1 (PACN1)

PA1H Holding

8, 12,16, ..., 1024

Delay Counter

EDG2

8-Bit PAC2 (PACN2)

PA2H Holding

Interrupt

8, 12,16, ..., 1024

Delay Counter

EDG3

8-Bit PAC3 (PACN3)

PA3H Holding

Figure 11-69. 8-Bit Pulse Accumulators Block Diagram

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

TIMCLK (Timer Clock)

CLK1

4:1 MUX

CLK0

Clock Select

(PAMOD)

Prescaled Clock

(PCLK)

Edge Detector

Interrupt

8-Bit PAC3

(PACN3)

8-Bit PAC2

(PACN2)

MUX

PACA

Divide by 64

Bus Clock

Interrupt

8-Bit PAC1

(PACN1)

8-Bit PAC0

(PACN0)

Delay Counter

Edge Detector

PACB

Figure 11-70. 16-Bit Pulse Accumulators Block Diagram

16-Bit Main Timer

Edge

Detector

Delay

Counter

Set CxF

Interrupt

TCx Input

Capture Register

TCxH I.C.

Holding Register

BUFEN • LATQ • TFMOD

Figure 11-71. Block Diagram for Port 7 with Output Compare/Pulse Accumulator A

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.4.1 Enhanced Capture Timer Modes of Operation

The enhanced capture timer has 8 input capture, output compare (IC/OC) channels, same as on the HC12

standard timer (timer channels TC0 to TC7). When channels are selected as input capture by selecting the

IOSx bit in TIOS register, they are called input capture (IC) channels.

Four IC channels (channels 7–4) are the same as on the standard timer with one capture register each that

memorizes the timer value captured by an action on the associated input pin.

Four other IC channels (channels 3–0), in addition to the capture register, also have one buffer each called

a holding register. This allows two different timer values to be saved without generating any interrupts.

Four 8-bit pulse accumulators are associated with the four buffered IC channels (channels 3–0). Each pulse

accumulator has a holding register to memorize their value by an action on its external input. Each pair of

pulse accumulators can be used as a 16-bit pulse accumulator.

The 16-bit modulus down-counter can control the transfer of the IC registers and the pulse accumulators

contents to the respective holding registers for a given period, every time the count reaches zero.

The modulus down-counter can also be used as a stand-alone time base with periodic interrupt capability.

11.4.1.1 IC Channels

The IC channels are composed of four standard IC registers and four buffered IC channels.

•

An IC register is empty when it has been read or latched into the holding register.

A holding register is empty when it has been read.

11.4.1.1.1

Non-Buffered IC Channels

The main timer value is memorized in the IC register by a valid input pin transition. If the corresponding

NOVWx bit of the ICOVW register is cleared, with a new occurrence of a capture, the contents of IC

the capture register cannot be written unless it is empty. This will prevent the captured value from being

overwritten until it is read.

11.4.1.1.2

Buffered IC Channels

There are two modes of operations for the buffered IC channels:

1. IC latch mode (LATQ = 1)

The main timer value is memorized in the IC register by a valid input pin transition (see

Figure 11-65 and Figure 11-66).

The value of the buffered IC register is latched to its holding register by the modulus counter for a

given period when the count reaches zero, by a write 0x0000 to the modulus counter or by a write

to ICLAT in the MCCTL register.

If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a

capture, the contents of IC register are overwritten by the new value. In case of latching, the

contents of its holding register are overwritten.

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding

This will prevent the captured value from being overwritten until it is read or latched in the holding

2. IC Queue Mode (LATQ = 0)

The main timer value is memorized in the IC register by a valid input pin transition (see

Figure 11-67 and Figure 11-68).

If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a

capture, the value of the IC register will be transferred to its holding register and the IC register

memorizes the new timer value.

If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding

In queue mode, reads of the holding register will latch the corresponding pulse accumulator value

to its holding register.

11.4.1.1.3

Delayed IC Channels

There are four delay counters in this module associated with IC channels 0–3. The use of this feature is

explained in the diagram and notes below.

BUS CLOCK

253 254

255 256

DLY_CNT

INPUT ON

CH0–3

Rejected

Accepted

255 Cycles

255.5 Cycles

INPUT ON

CH0–3

INPUT ON

CH0–3

INPUT ON

CH0–3

256 Cycles

Figure 11-72. Channel Input Validity with Delay Counter Feature

In Figure 11-72 a delay counter value of 256 bus cycles is considered.

1. Input pulses with a duration of (DLY_CNT – 1) cycles or shorter are rejected.

2. Input pulses with a duration between (DLY_CNT – 1) and DLY_CNT cycles may be rejected or

accepted, depending on their relative alignment with the sample points.

3. Input pulses with a duration between (DLY_CNT – 1) and DLY_CNT cycles may be rejected or

accepted, depending on their relative alignment with the sample points.

4. Input pulses with a duration of DLY_CNT or longer are accepted.

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.4.1.2 OC Channel Initialization

Internal register whose output drives OCx when TIOS is set, can be force loaded with a desired data by

writing to CFORC register before OCx is conﬁgured for output compare action. This allows a glitch free

switch over of port from general purpose I/O to timer output once the output compare is enabled.

11.4.1.3 Pulse Accumulators

There are four 8-bit pulse accumulators with four 8-bit holding registers associated with the four IC

buffered channels 3–0. A pulse accumulator counts the number of active edges at the input of its channel.

The minimum pulse width for the PAI input is greater than two bus clocks.The maximum input frequency

on the pulse accumulator channel is one half the bus frequency or Eclk.

The user can prevent the 8-bit pulse accumulators from counting further than 0x00FF by utilizing the

PACMX control bit in the ICSYS register. In this case, a value of 0x00FF means that 255 counts or more

have occurred.

Each pair of pulse accumulators can be used as a 16-bit pulse accumulator (see Figure 11-70).

To operate the 16-bit pulse accumulators A and B (PACA and PACB) independently of input capture or

output compare 7 and 0 respectively, the user must set the corresponding bits: IOSx = 1, OMx = 0, and

OLx = 0. OC7M7 or OC7M0 in the OC7M register must also be cleared.

There are two modes of operation for the pulse accumulators:

•

Pulse accumulator latch mode

The value of the pulse accumulator is transferred to its holding register when the modulus

down-counter reaches zero, a write 0x0000 to the modulus counter or when the force latch control

bit ICLAT is written.

At the same time the pulse accumulator is cleared.

Pulse accumulator queue mode

•

When queue mode is enabled, reads of an input capture holding register will transfer the contents

of the associated pulse accumulator to its holding register.

At the same time the pulse accumulator is cleared.

11.4.1.4 Modulus Down-Counter

The modulus down-counter can be used as a time base to generate a periodic interrupt. It can also be used

to latch the values of the IC registers and the pulse accumulators to their holding registers.

The action of latching can be programmed to be periodic or only once.

11.4.1.5 Precision Timer

By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this

case, it is possible to set additional prescaler settings for the main timer counter and modulus down counter

and enhance delay counter settings compared to the settings in the present ECT timer.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.4.1.6 Flag Clearing Mechanisms

The ﬂags in the ECT can be cleared one of two ways:

1. Normal ﬂag clearing mechanism (TFFCA = 0)

Any of the ECT ﬂags can be cleared by writing a one to the ﬂag.

2. Fast ﬂag clearing mechanism (TFFCA = 1)

With the timer fast ﬂag clear all (TFFCA) enabled, the ECT ﬂags can only be cleared by accessing

the various registers associated with the ECT modes of operation as described below. The ﬂags

cannot be cleared via the normal ﬂag clearing mechanism. This fast ﬂag clearing mechanism has

the advantage of eliminating the software overhead required by a separate clear sequence. Extra

care must be taken to avoid accidental ﬂag clearing due to unintended accesses.

— Input capture

A read from an input capture channel register causes the corresponding channel ﬂag, CxF, to

be cleared in the TFLG1 register.

— Output compare

A write to the output compare channel register causes the corresponding channel flag, CxF, to

be cleared in the TFLG1 register.

— Timer counter

Any access to the TCNT register clears the TOF flag in the TFLG2 register.

— Pulse accumulator A

Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the

PAFLG register.

— Pulse accumulator B

Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register.

— Modulus down counter

Any access to the MCCNT register clears the MCZF flag in the MCFLG register.

11.4.2 Reset

The reset state of each individual bit is listed within the register description section (Section 11.3,

“Memory Map and Register Deﬁnition”) which details the registers and their bit-ﬁelds.

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Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)

11.4.3 Interrupts

This section describes interrupts originated by the ECT block. The MCU must service the interrupt

requests. Table 11-37 lists the interrupts generated by the ECT to communicate with the MCU.

Table 11-37. ECT Interrupts

Interrupt Source

Timer channel 7–0

Description

Active high timer channel interrupts 7–0

Active high modulus counter interrupt

Active high pulse accumulator B interrupt

Active high pulse accumulator A input interrupt

Pulse accumulator overﬂow interrupt

Timer 0verﬂow interrupt

Modulus counter underﬂow

Pulse accumulator B overﬂow

Pulse accumulator A input

Pulse accumulator A overﬂow

Timer overﬂow

The ECT only originates interrupt requests. The following is a description of how the module makes a

request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt

number are chip dependent.

11.4.3.1 Channel [7:0] Interrupt

This active high output will be asserted by the module to request a timer channel 7–0 interrupt to be

serviced by the system controller.

11.4.3.2 Modulus Counter Interrupt

This active high output will be asserted by the module to request a modulus counter underﬂow interrupt to

be serviced by the system controller.

11.4.3.3 Pulse Accumulator B Overﬂow Interrupt

This active high output will be asserted by the module to request a timer pulse accumulator B overﬂow

interrupt to be serviced by the system controller.

11.4.3.4 Pulse Accumulator A Input Interrupt

This active high output will be asserted by the module to request a timer pulse accumulator A input

interrupt to be serviced by the system controller.

11.4.3.5 Pulse Accumulator A Overﬂow Interrupt

This active high output will be asserted by the module to request a timer pulse accumulator A overﬂow

interrupt to be serviced by the system controller.

11.4.3.6 Timer Overﬂow Interrupt

This active high output will be asserted by the module to request a timer overﬂow interrupt to be serviced

by the system controller.

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Chapter 12

Pulse-Width Modulator (S12PWM8B8CV1)

12.1 Introduction

The PWM deﬁnition is based on the HC12 PWM deﬁnitions. It contains the basic features from the HC11

with some of the enhancements incorporated on the HC12: center aligned output mode and four available

clock sources.The PWM module has eight channels with independent control of left and center aligned

outputs on each channel.

Each of the eight channels has a programmable period and duty cycle as well as a dedicated counter. A

ﬂexible clock select scheme allows a total of four different clock sources to be used with the counters. Each

of the modulators can create independent continuous waveforms with software-selectable duty rates from

0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs.

12.1.1 Features

The PWM block includes these distinctive features:

•

Eight independent PWM channels with programmable period and duty cycle

Dedicated counter for each PWM channel

Programmable PWM enable/disable for each channel

Software selection of PWM duty pulse polarity for each channel

Period and duty cycle are double buffered. Change takes effect when the end of the effective period

is reached (PWM counter reaches zero) or when the channel is disabled.

•

Programmable center or left aligned outputs on individual channels

Eight 8-bit channel or four 16-bit channel PWM resolution

Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies

Programmable clock select logic

Emergency shutdown

12.1.2 Modes of Operation

There is a software programmable option for low power consumption in wait mode that disables the input

clock to the prescaler.

In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is

useful for emulation.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

12.1.3 Block Diagram

Figure 12-1 shows the block diagram for the 8-bit 8-channel PWM block.

PWM8B8C

PWM Channels

Channel 7

PWM7

PWM6

Period and Duty

Counter

Channel 6

Period and Duty

PWM Clock

Bus Clock

Clock Select

Control

Channel 5

PWM5

PWM4

PWM3

PWM2

Period and Duty

Counter

Channel 4

Period and Duty

Channel 3

Period and Duty

Enable

Channel 2

Polarity

Period and Duty

Alignment

Channel 1

PWM1

PWM0

Period and Duty

Counter

Channel 0

Period and Duty

Figure 12-1. PWM Block Diagram

12.2 External Signal Description

The PWM module has a total of 8 external pins.

12.2.1 PWM7 — PWM Channel 7

This pin serves as waveform output of PWM channel 7 and as an input for the emergency shutdown

feature.

12.2.2 PWM6 — PWM Channel 6

This pin serves as waveform output of PWM channel 6.

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

12.2.3 PWM5 — PWM Channel 5

This pin serves as waveform output of PWM channel 5.

12.2.4 PWM4 — PWM Channel 4

This pin serves as waveform output of PWM channel 4.

12.2.5 PWM3 — PWM Channel 3

This pin serves as waveform output of PWM channel 3.

12.2.6 PWM3 — PWM Channel 2

This pin serves as waveform output of PWM channel 2.

12.2.7 PWM3 — PWM Channel 1

This pin serves as waveform output of PWM channel 1.

12.2.8 PWM3 — PWM Channel 0

This pin serves as waveform output of PWM channel 0.

12.3 Memory Map and Register Deﬁnition

This section describes in detail all the registers and register bits in the PWM module.

The special-purpose registers and register bit functions that are not normally available to device end users,

such as factory test control registers and reserved registers, are clearly identiﬁed by means of shading the

appropriate portions of address maps and register diagrams. Notes explaining the reasons for restricting

access to the registers and functions are also explained in the individual register descriptions.

12.3.1 Module Memory Map

This section describes the content of the registers in the PWM module. The base address of the PWM

module is determined at the MCU level when the MCU is deﬁned. The register decode map is ﬁxed and

begins at the ﬁrst address of the module address offset. The ﬁgure below shows the registers associated

with the PWM and their relative offset from the base address. The register detail description follows the

order they appear in the register map.

Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented

functions are indicated by shading the bit. .

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

NOTE

is deﬁned at the MCU level and the Address Offset is deﬁned at the module

level.

12.3.2 Register Descriptions

This section describes in detail all the registers and register bits in the PWM module.

Name

Bit 7

Bit 0

0x0000

PWME

PWME7

PWME6

PWME5

PWME4

PWME3

PWME2

PWME1

PWME0

0x0001

PWMPOL

PPOL7

PPOL6

PCLKL6

PCKB2

CAE6

PPOL5

PCLK5

PCKB1

CAE5

PPOL4

PCLK4

PCKB0

CAE4

PPOL3

PPOL2

PCLK2

PCKA2

CAE2

PPOL1

PCLK1

PCKA1

PPOL0

PCLK0

PCKA0

0x0002

PWMCLK

PCLK7

PCLK3

0x0003

PWMPRCLK

0x0004

PWMCAE

CAE7

CAE3

CAE1

CAE0

0x0005

PWMCTL

CON67

CON45

CON23

CON01

PSWAI

PFRZ

0x0006

PWMTST

0x0007

PWMPRSC

0x0008

PWMSCLA

Bit 7

Bit 0

0x0009

PWMSCLB

Bit 7

Bit 0

0x000A

PWMSCNTA

= Unimplemented or Reserved

Figure 12-2. PWM Register Summary (Sheet 1 of 3)

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

Name

Bit 7

Bit 0

0x000B

PWMSCNTB

0x000C

PWMCNT0

Bit 7

Bit 0

0x000D

PWMCNT1

Bit 7

Bit 0

0x000E

PWMCNT2

Bit 7

Bit 0

0x000F

PWMCNT3

Bit 7

Bit 0

0x0010

PWMCNT4

Bit 7

Bit 0

0x0011

PWMCNT5

Bit 7

Bit 0

0x0012

PWMCNT6

Bit 7

Bit 0

0x0013

PWMCNT7

Bit 7

Bit 0

0x0014

PWMPER0

Bit 7

Bit 0

0x0015

PWMPER1

0x0016

PWMPER2

0x0017

PWMPER3

0x0018

PWMPER4

0x0019

PWMPER5

= Unimplemented or Reserved

Figure 12-2. PWM Register Summary (Sheet 2 of 3)

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

Bit 7

Bit 0

Name

0x001A

PWMPER6

Bit 7

Bit 0

0x001B

PWMPER7

Bit 7

PWMIF

Bit 0

0x001C

PWMDTY0

0x001D

PWMDTY1

0x001E

PWMDTY2

0x001F

PWMDTY3

0x0010

PWMDTY4

0x0021

PWMDTY5

0x0022

PWMDTY6

0x0023

PWMDTY7

0x0024

PWMSDN

PWM7IN

PWMIE

PWMLVL

PWM7INL PWM7ENA

PWMRSTRT

= Unimplemented or Reserved

Figure 12-2. PWM Register Summary (Sheet 3 of 3)

Intended for factory test purposes only.

12.3.2.1 PWM Enable Register (PWME)

Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx

bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM

waveform is not available on the associated PWM output until its clock source begins its next cycle due to

the synchronization of PWMEx and the clock source.

NOTE

The ﬁrst PWM cycle after enabling the channel can be irregular.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits

set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the

low order PWMEx bit.In this case, the high order bytes PWMEx bits have no effect and their

corresponding PWM output lines are disabled.

While in run mode, if all eight PWM channels are disabled (PWME7–0 = 0), the prescaler counter shuts

off for power savings.

Module Base + 0x0000

PWME7

PWME6

PWME5

PWME4

PWME3

PWME2

PWME1

PWME0

Reset

Figure 12-3. PWM Enable Register (PWME)

Read: Anytime

Write: Anytime

Table 12-1. PWME Field Descriptions

Description

Field

Pulse Width Channel 7 Enable

PWME7

0 Pulse width channel 7 is disabled.

1 Pulse width channel 7 is enabled. The pulse modulated signal becomes available at PWM output bit 7 when

its clock source begins its next cycle.

Pulse Width Channel 6 Enable

PWME6

0 Pulse width channel 6 is disabled.

1 Pulse width channel 6 is enabled. The pulse modulated signal becomes available at PWM output bit6 when

its clock source begins its next cycle. If CON67=1, then bit has no effect and PWM output line 6 is disabled.

Pulse Width Channel 5 Enable

PWME5

0 Pulse width channel 5 is disabled.

1 Pulse width channel 5 is enabled. The pulse modulated signal becomes available at PWM output bit 5 when

its clock source begins its next cycle.

Pulse Width Channel 4 Enable

PWME4

0 Pulse width channel 4 is disabled.

1 Pulse width channel 4 is enabled. The pulse modulated signal becomes available at PWM, output bit 4 when

its clock source begins its next cycle. If CON45 = 1, then bit has no effect and PWM output bit4 is disabled.

Pulse Width Channel 3 Enable

PWME3

0 Pulse width channel 3 is disabled.

1 Pulse width channel 3 is enabled. The pulse modulated signal becomes available at PWM, output bit 3 when

its clock source begins its next cycle.

Pulse Width Channel 2 Enable

PWME2

0 Pulse width channel 2 is disabled.

1 Pulse width channel 2 is enabled. The pulse modulated signal becomes available at PWM, output bit 2 when

its clock source begins its next cycle. If CON23 = 1, then bit has no effect and PWM output bit2 is disabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

Table 12-1. PWME Field Descriptions (continued)

Field

Description

Pulse Width Channel 1 Enable

PWME1

Pulse width channel 1 is disabled.

Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when

its clock source begins its next cycle.

Pulse Width Channel 0 Enable

PWME0

0 Pulse width channel 0 is disabled.

1 Pulse width channel 0 is enabled. The pulse modulated signal becomes available at PWM, output bit 0 when

its clock source begins its next cycle. If CON01 = 1, then bit has no effect and PWM output line0 is disabled.

12.3.2.2 PWM Polarity Register (PWMPOL)

The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the

PWMPOL register. If the polarity bit is one, the PWM channel output is high at the beginning of the cycle

and then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts

low and then goes high when the duty count is reached.

Module Base + 0x0001

PPOL7

PPOL6

PPOL5

PPOL4

PPOL3

PPOL2

PPOL1

PPOL0

Reset

Figure 12-4. PWM Polarity Register (PWMPOL)

Read: Anytime

Write: Anytime

NOTE

PPOLx register bits can be written anytime. If the polarity is changed while

a PWM signal is being generated, a truncated or stretched pulse can occur

during the transition

Table 12-2. PWMPOL Field Descriptions

Description

Field

7–0

Pulse Width Channel 7–0 Polarity Bits

PPOL[7:0] 0 PWM channel 7–0 outputs are low at the beginning of the period, then go high when the duty count is

reached.

1 PWM channel 7–0 outputs are high at the beginning of the period, then go low when the duty count is

reached.

12.3.2.3 PWM Clock Select Register (PWMCLK)

Each PWM channel has a choice of two clocks to use as the clock source for that channel as described

below.

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

Module Base + 0x0002

PCLK7

PCLKL6

PCLK5

PCLK4

PCLK3

PCLK2

PCLK1

PCLK0

Reset

Figure 12-5. PWM Clock Select Register (PWMCLK)

Read: Anytime

Write: Anytime

NOTE

changed while a PWM signal is being generated, a truncated or stretched

pulse can occur during the transition.

Table 12-3. PWMCLK Field Descriptions

Description

Field

Pulse Width Channel 7 Clock Select

PCLK7

0 Clock B is the clock source for PWM channel 7.

1 Clock SB is the clock source for PWM channel 7.

Pulse Width Channel 6 Clock Select

PCLK6

0 Clock B is the clock source for PWM channel 6.

1 Clock SB is the clock source for PWM channel 6.

Pulse Width Channel 5 Clock Select

PCLK5

0 Clock A is the clock source for PWM channel 5.

1 Clock SA is the clock source for PWM channel 5.

Pulse Width Channel 4 Clock Select

PCLK4

0 Clock A is the clock source for PWM channel 4.

1 Clock SA is the clock source for PWM channel 4.

Pulse Width Channel 3 Clock Select

PCLK3

0 Clock B is the clock source for PWM channel 3.

1 Clock SB is the clock source for PWM channel 3.

Pulse Width Channel 2 Clock Select

PCLK2

0 Clock B is the clock source for PWM channel 2.

1 Clock SB is the clock source for PWM channel 2.

Pulse Width Channel 1 Clock Select

PCLK1

0 Clock A is the clock source for PWM channel 1.

1 Clock SA is the clock source for PWM channel 1.

Pulse Width Channel 0 Clock Select

PCLK0

0 Clock A is the clock source for PWM channel 0.

1 Clock SA is the clock source for PWM channel 0.

12.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK)

This register selects the prescale clock source for clocks A and B independently.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

Module Base + 0x0003

PCKB2

PCKB1

PCKB0

PCKA2

PCKA1

PCKA0

Reset

= Unimplemented or Reserved

Figure 12-6. PWM Prescale Clock Select Register (PWMPRCLK)

Read: Anytime

Write: Anytime

NOTE

PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock

pre-scale is changed while a PWM signal is being generated, a truncated or

stretched pulse can occur during the transition.

Table 12-4. PWMPRCLK Field Descriptions

Description

Field

6–4

Prescaler Select for Clock B — Clock B is one of two clock sources which can be used for channels 2, 3, 6, or

PCKB[2:0] 7. These three bits determine the rate of clock B, as shown in T a ble 12-5.

2–0 Prescaler Select for Clock A — Clock A is one of two clock sources which can be used for channels 0, 1, 4 or

PCKA[2:0] 5. These three bits determine the rate of clock A, as shown in Table 12-6.

Table 12-5. Clock B Prescaler Selects

PCKB2

PCKB1

PCKB0

Value of Clock B

Bus clock

Bus clock / 2

Bus clock / 4

Bus clock / 8

Bus clock / 16

Bus clock / 32

Bus clock / 64

Bus clock / 128

Table 12-6. Clock A Prescaler Selects

PCKA2

PCKA1

PCKA0

Value of Clock A

Bus clock

Bus clock / 2

Bus clock / 4

Bus clock / 8

Bus clock / 16

Bus clock / 32

Bus clock / 64

Bus clock / 128

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

12.3.2.5 PWM Center Align Enable Register (PWMCAE)

The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned

outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be

center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See

Section 12.4.2.5, “Left Aligned Outputs” and Section 12.4.2.6, “Center Aligned Outputs” for a more

detailed description of the PWM output modes.

Module Base + 0x0004

CAE7

CAE6

CAE5

CAE4

CAE3

CAE2

CAE1

CAE0

Reset

Figure 12-7. PWM Center Align Enable Register (PWMCAE)

Read: Anytime

Write: Anytime

NOTE

Write these bits only when the corresponding channel is disabled.

Table 12-7. PWMCAE Field Descriptions

Description

Field

7–0

CAE[7:0]

Center Aligned Output Modes on Channels 7–0

0 Channels 7–0 operate in left aligned output mode.

1 Channels 7–0 operate in center aligned output mode.

12.3.2.6 PWM Control Register (PWMCTL)

The PWMCTL register provides for various control of the PWM module.

Module Base + 0x0005

CON67

CON45

CON23

CON01

PSWAI

PFRZ

Reset

= Unimplemented or Reserved

Figure 12-8. PWM Control Register (PWMCTL)

Read: Anytime

Write: Anytime

There are three control bits for concatenation, each of which is used to concatenate a pair of PWM

channels into one 16-bit channel. When channels 6 and 7are concatenated, channel 6 registers become the

high order bytes of the double byte channel. When channels 4 and 5 are concatenated, channel 4 registers

become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are

concatenated, channel 0 registers become the high order bytes of the double byte channel.

See Section 12.4.2.7, “PWM 16-Bit Functions” for a more detailed description of the concatenation PWM

Function.

NOTE

Change these bits only when both corresponding channels are disabled.

Table 12-8. PWMCTL Field Descriptions

Field

Description

Concatenate Channels 6 and 7

CON67

0 Channels 6 and 7 are separate 8-bit PWMs.

1 Channels 6 and 7 are concatenated to create one 16-bit PWM channel. Channel 6 becomes the high order

byte and channel 7 becomes the low order byte. Channel 7 output pin is used as the output for this 16-bit

PWM (bit 7 of port PWMP). Channel 7 clock select control-bit determines the clock source, channel 7 polarity

bit determines the polarity, channel 7 enable bit enables the output and channel 7 center aligned enable bit

determines the output mode.

Concatenate Channels 4 and 5

CON45

0 Channels 4 and 5 are separate 8-bit PWMs.

1 Channels 4 and 5 are concatenated to create one 16-bit PWM channel. Channel 4 becomes the high order

byte and channel 5 becomes the low order byte. Channel 5 output pin is used as the output for this 16-bit

PWM (bit 5 of port PWMP). Channel 5 clock select control-bit determines the clock source, channel 5 polarity

bit determines the polarity, channel 5 enable bit enables the output and channel 5 center aligned enable bit

determines the output mode.

Concatenate Channels 2 and 3

CON23

0 Channels 2 and 3 are separate 8-bit PWMs.

1 Channels 2 and 3 are concatenated to create one 16-bit PWM channel. Channel 2 becomes the high order

byte and channel 3 becomes the low order byte. Channel 3 output pin is used as the output for this 16-bit

PWM (bit 3 of port PWMP). Channel 3 clock select control-bit determines the clock source, channel 3 polarity

bit determines the polarity, channel 3 enable bit enables the output and channel 3 center aligned enable bit

determines the output mode.

Concatenate Channels 0 and 1

CON01

0 Channels 0 and 1 are separate 8-bit PWMs.

1 Channels 0 and 1 are concatenated to create one 16-bit PWM channel. Channel 0 becomes the high order

byte and channel 1 becomes the low order byte. Channel 1 output pin is used as the output for this 16-bit

PWM (bit 1 of port PWMP). Channel 1 clock select control-bit determines the clock source, channel 1 polarity

bit determines the polarity, channel 1 enable bit enables the output and channel 1 center aligned enable bit

determines the output mode.

PWM Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling

the input clock to the prescaler.

PSWAI

0 Allow the clock to the prescaler to continue while in wait mode.

1 Stop the input clock to the prescaler whenever the MCU is in wait mode.

PWM Counters Stop in Freeze Mode — In freeze mode, there is an option to disable the input clock to the

prescaler by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode,

the input clock to the prescaler is disabled. This feature is useful during emulation as it allows the PWM function

to be suspended. In this way, the counters of the PWM can be stopped while in freeze mode so that once normal

program ﬂow is continued, the counters are re-enabled to simulate real-time operations. Since the registers can

still be accessed in this mode, to re-enable the prescaler clock, either disable the PFRZ bit or exit freeze mode.

0 Allow PWM to continue while in freeze mode.

PFREZ

1 Disable PWM input clock to the prescaler whenever the part is in freeze mode. This is useful for emulation.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

12.3.2.7 Reserved Register (PWMTST)

This register is reserved for factory testing of the PWM module and is not available in normal modes.

Module Base + 0x0006

Reset

= Unimplemented or Reserved

Figure 12-9. Reserved Register (PWMTST)

Read: Always read $00 in normal modes

Write: Unimplemented in normal modes

NOTE

Writing to this register when in special modes can alter the PWM

functionality.

12.3.2.8 Reserved Register (PWMPRSC)

This register is reserved for factory testing of the PWM module and is not available in normal modes.

Module Base + 0x0007

Reset

= Unimplemented or Reserved

Figure 12-10. Reserved Register (PWMPRSC)

Read: Always read $00 in normal modes

Write: Unimplemented in normal modes

NOTE

Writing to this register when in special modes can alter the PWM

functionality.

12.3.2.9 PWM Scale A Register (PWMSCLA)

PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is

generated by taking clock A, dividing it by the value in the PWMSCLA register and dividing that by two.

Clock SA = Clock A / (2 * PWMSCLA)

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

NOTE

When PWMSCLA = $00, PWMSCLA value is considered a full scale value

of 256. Clock A is thus divided by 512.

Any value written to this register will cause the scale counter to load the new scale value (PWMSCLA).

Module Base + 0x0008

Bit 7

Bit 0

Reset

Figure 12-11. PWM Scale A Register (PWMSCLA)

Read: Anytime

Write: Anytime (causes the scale counter to load the PWMSCLA value)

12.3.2.10 PWM Scale B Register (PWMSCLB)

PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB. Clock SB is

generated by taking clock B, dividing it by the value in the PWMSCLB register and dividing that by two.

Clock SB = Clock B / (2 * PWMSCLB)

NOTE

When PWMSCLB = $00, PWMSCLB value is considered a full scale value

of 256. Clock B is thus divided by 512.

Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB).

Module Base + 0x0009

Bit 7

Bit 0

Reset

Figure 12-12. PWM Scale B Register (PWMSCLB)

Read: Anytime

Write: Anytime (causes the scale counter to load the PWMSCLB value).

12.3.2.11 Reserved Registers (PWMSCNTx)

The registers PWMSCNTA and PWMSCNTB are reserved for factory testing of the PWM module and are

not available in normal modes.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

Module Base + 0x000A, 0x000B

Reset

= Unimplemented or Reserved

Figure 12-13. Reserved Registers (PWMSCNTx)

Read: Always read $00 in normal modes

Write: Unimplemented in normal modes

NOTE

Writing to these registers when in special modes can alter the PWM

functionality.

12.3.2.12 PWM Channel Counter Registers (PWMCNTx)

Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source.

The counter can be read at any time without affecting the count or the operation of the PWM channel. In

left aligned output mode, the counter counts from 0 to the value in the period register - 1. In center aligned

output mode, the counter counts from 0 up to the value in the period register and then back down to 0.

Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up,

the immediate load of both duty and period registers with values from the buffers, and the output to change

according to the polarity bit. The counter is also cleared at the end of the effective period (see

Section 12.4.2.5, “Left Aligned Outputs” and Section 12.4.2.6, “Center Aligned Outputs” for more

details). When the channel is disabled (PWMEx = 0), the PWMCNTx register does not count. When a

channel becomes enabled (PWMEx = 1), the associated PWM counter starts at the count in the

PWMCNTx register. For more detailed information on the operation of the counters, see Section 12.4.2.4,

“PWM Timer Counters”.

In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or

high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by

16-bit access to maintain data coherency.

NOTE

Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur.

Module Base + 0x000C = PWMCNT0, 0x000D = PWMCNT1, 0x000E = PWMCNT2, 0x000F = PWMCNT3

Module Base + 0x0010 = PWMCNT4, 0x0011 = PWMCNT5, 0x0012 = PWMCNT6, 0x0013 = PWMCNT7

Bit 7

Bit 0

Reset

Figure 12-14. PWM Channel Counter Registers (PWMCNTx)

Read: Anytime

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

Write: Anytime (any value written causes PWM counter to be reset to $00).

12.3.2.13 PWM Channel Period Registers (PWMPERx)

There is a dedicated period register for each channel. The value in this register determines the period of

the associated PWM channel.

The period registers for each channel are double buffered so that if they change while the channel is

enabled, the change will NOT take effect until one of the following occurs:

•

The effective period ends

The counter is written (counter resets to $00)

The channel is disabled

In this way, the output of the PWM will always be either the old waveform or the new waveform, not some

variation in between. If the channel is not enabled, then writes to the period register will go directly to the

latches as well as the buffer.

NOTE

Reads of this register return the most recent value written. Reads do not

necessarily return the value of the currently active period due to the double

buffering scheme.

See Section 12.4.2.3, “PWM Period and Duty” for more information.

To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA,

or SB) and multiply it by the value in the period register for that channel:

•

Left aligned output (CAEx = 0)

PWMxPeriod=ChannelClockPeriod*PWMPERxCenterAlignedOutput(CAEx=1)

PWMx Period = Channel Clock Period * (2 * PWMPERx)

For boundary case programming values, please refer to Section 12.4.2.8, “PWM Boundary Cases”.

Module Base + 0x0014 = PWMPER0, 0x0015 = PWMPER1, 0x0016 = PWMPER2, 0x0017 = PWMPER3

Module Base + 0x0018 = PWMPER4, 0x0019 = PWMPER5, 0x001A = PWMPER6, 0x001B = PWMPER7

Bit 7

Bit 0

Reset

Figure 12-15. PWM Channel Period Registers (PWMPERx)

Read: Anytime

Write: Anytime

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

12.3.2.14 PWM Channel Duty Registers (PWMDTYx)

There is a dedicated duty register for each channel. The value in this register determines the duty of the

associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value

a match occurs and the output changes state.

The duty registers for each channel are double buffered so that if they change while the channel is enabled,

the change will NOT take effect until one of the following occurs:

•

The effective period ends

The counter is written (counter resets to $00)

The channel is disabled

In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform,

not some variation in between. If the channel is not enabled, then writes to the duty register will go directly

to the latches as well as the buffer.

NOTE

Reads of this register return the most recent value written. Reads do not

necessarily return the value of the currently active duty due to the double

buffering scheme.

See Section 12.4.2.3, “PWM Period and Duty” for more information.

NOTE

Depending on the polarity bit, the duty registers will contain the count of

either the high time or the low time. If the polarity bit is one, the output starts

high and then goes low when the duty count is reached, so the duty registers

contain a count of the high time. If the polarity bit is zero, the output starts

low and then goes high when the duty count is reached, so the duty registers

contain a count of the low time.

To calculate the output duty cycle (high time as a% of period) for a particular channel:

•

Polarity = 0 (PPOL x =0)

Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%

Polarity = 1 (PPOLx = 1)

•

Duty Cycle = [PWMDTYx / PWMPERx] * 100%

For boundary case programming values, please refer to Section 12.4.2.8, “PWM Boundary Cases”.

Module Base + 0x001C = PWMDTY0, 0x001D = PWMDTY1, 0x001E = PWMDTY2, 0x001F = PWMDTY3

Module Base + 0x0020 = PWMDTY4, 0x0021 = PWMDTY5, 0x0022 = PWMDTY6, 0x0023 = PWMDTY7

Bit 7

Bit 0

Reset

Figure 12-16. PWM Channel Duty Registers (PWMDTYx)

Read: Anytime

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

Write: Anytime

12.3.2.15 PWM Shutdown Register (PWMSDN)

The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency

cases. For proper operation, channel 7 must be driven to the active level for a minimum of two bus clocks.

Module Base + 0x0024

PWM7IN

PWMIF

PWMIE

PWMLVL

PWM7INL

PWM7ENA

PWMRSTRT

Reset

= Unimplemented or Reserved

Figure 12-17. PWM Shutdown Register (PWMSDN)

Read: Anytime

Write: Anytime

Table 12-9. PWMSDN Field Descriptions

Description

Field

PWM Interrupt Flag — Any change from passive to asserted (active) state or from active to passive state will

be ﬂagged by setting the PWMIF ﬂag = 1. The ﬂag is cleared by writing a logic 1 to it. Writing a 0 has no effect.

0 No change on PWM7IN input.

PWMIF

1 Change on PWM7IN input

PWM Interrupt Enable — If interrupt is enabled an interrupt to the CPU is asserted.

0 PWM interrupt is disabled.

PWMIE

1 PWM interrupt is enabled.

PWM Restart — The PWM can only be restarted if the PWM channel input 7 is de-asserted. After writing a logic

PWMRSTRT 1 to the PWMRSTRT bit (trigger event) the PWM channels start running after the corresponding counter passes

next “counter == 0” phase. Also, if the PWM7ENA bit is reset to 0, the PWM do not start before the counter

passes $00. The bit is always read as “0”.

PWM Shutdown Output Level If active level as deﬁned by the PWM7IN input, gets asserted all enabled PWM

channels are immediately driven to the level deﬁned by PWMLVL.

0 PWM outputs are forced to 0

PWMLVL

1 Outputs are forced to 1.

PWM Channel 7 Input Status — This reﬂects the current status of the PWM7 pin.

PWM7IN

PWM Shutdown Active Input Level for Channel 7 — If the emergency shutdown feature is enabled

PWM7INL (PWM7ENA = 1), this bit determines the active level of the PWM7channel.

0 Active level is low

1 Active level is high

PWM Emergency Shutdown Enable — If this bit is logic 1, the pin associated with channel 7 is forced to input

PWM7ENA and the emergency shutdown feature is enabled. All the other bits in this register are meaningful only if

PWM7ENA = 1.

0 PWM emergency feature disabled.

1 PWM emergency feature is enabled.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

12.4 Functional Description

12.4.1 PWM Clock Select

There are four available clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These

four clocks are based on the bus clock.

Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA

uses clock A as an input and divides it further with a reloadable counter. Similarly, clock SB uses clock B

as an input and divides it further with a reloadable counter. The rates available for clock SA are software

selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are

available for clock SB. Each PWM channel has the capability of selecting one of two clocks, either the

pre-scaled clock (clock A or B) or the scaled clock (clock SA or SB).

The block diagram in Figure 12-18 shows the four different clocks and how the scaled clocks are created.

12.4.1.1 Prescale

The input clock to the PWM prescaler is the bus clock. It can be disabled whenever the part is in freeze

mode by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze

mode (freeze mode signal active) the input clock to the prescaler is disabled. This is useful for emulation

in order to freeze the PWM. The input clock can also be disabled when all eight PWM channels are

disabled (PWME7-0 = 0). This is useful for reducing power by disabling the prescale counter.

Clock A and clock B are scaled values of the input clock. The value is software selectable for both clock

A and clock B and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the bus clock. The value

selected for clock A is determined by the PCKA2, PCKA1, PCKA0 bits in the PWMPRCLK register. The

value selected for clock B is determined by the PCKB2, PCKB1, PCKB0 bits also in the PWMPRCLK

12.4.1.2 Clock Scale

The scaled A clock uses clock A as an input and divides it further with a user programmable value and

then divides this by 2. The scaled B clock uses clock B as an input and divides it further with a user

programmable value and then divides this by 2. The rates available for clock SA are software selectable to

be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock

SB.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

Clock A

Clock to

PWM Ch 0

Clock A/2, A/4, A/6,....A/512

PCLK0

Count = 1

Load

8-Bit Down

Counter

Clock to

PWM Ch 1

PCLK1

Clock SA

DIV 2

PWMSCLA

Clock to

PWM Ch 2

PCLK2

Clock to

PWM Ch 3

PCLK3

Clock B

Clock to

PWM Ch 4

Clock B/2, B/4, B/6,....B/512

PCLK4

Count = 1

8-Bit Down

Counter

Clock to

PWM Ch 5

Load

Clock SB

PCLK5

PWMSCLB

DIV 2

Clock to

PWM Ch 6

PCLK6

Clock to

PWM Ch 7

PCLK7

Prescale

Scale

Clock Select

Figure 12-18. PWM Clock Select Block Diagram

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale

value from the scale register (PWMSCLA). When the down counter reaches one, a pulse is output and the

8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater

range with only a slight reduction in granularity. Clock SA equals clock A divided by two times the value

in the PWMSCLA register.

NOTE

Clock SA = Clock A / (2 * PWMSCLA)

When PWMSCLA = $00, PWMSCLA value is considered a full scale value

of 256. Clock A is thus divided by 512.

Similarly, clock B is used as an input to an 8-bit down counter followed by a divide by two producing clock

SB. Thus, clock SB equals clock B divided by two times the value in the PWMSCLB register.

NOTE

Clock SB = Clock B / (2 * PWMSCLB)

When PWMSCLB = $00, PWMSCLB value is considered a full scale value

of 256. Clock B is thus divided by 512.

As an example, consider the case in which the user writes $FF into the PWMSCLA register. Clock A for

this case will be E divided by 4. A pulse will occur at a rate of once every 255x4 E cycles. Passing this

through the divide by two circuit produces a clock signal at an E divided by 2040 rate. Similarly, a value

of $01 in the PWMSCLA register when clock A is E divided by 4 will produce a clock at an E divided by

8 rate.

Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded.

Otherwise, when changing rates the counter would have to count down to $01 before counting at the proper

rate. Forcing the associated counter to re-load the scale register value every time PWMSCLA or

PWMSCLB is written prevents this.

NOTE

Writing to the scale registers while channels are operating can cause

irregularities in the PWM outputs.

12.4.1.3 Clock Select

Each PWM channel has the capability of selecting one of two clocks. For channels 0, 1, 4, and 5 the clock

choices are clock A or clock SA. For channels 2, 3, 6, and 7 the choices are clock B or clock SB. The clock

selection is done with the PCLKx control bits in the PWMCLK register.

NOTE

Changing clock control bits while channels are operating can cause

irregularities in the PWM outputs.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

581

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

12.4.2 PWM Channel Timers

The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period

the period register and the value in the counter. The duty is controlled by a match between the duty register

and the counter value and causes the state of the output to change during the period. The starting polarity

of the output is also selectable on a per channel basis. Shown below in Figure 12-19 is the block diagram

for the PWM timer.

Clock Source

From Port PWMP

8-Bit Counter

Data Register

Gate

PWMCNTx

(Clock Edge

Sync)

Up/Down

Reset

8-bit Compare =

PWMDTYx

To Pin

Driver

8-bit Compare =

PWMPERx

PPOLx

CAEx

PWMEx

Figure 12-19. PWM Timer Channel Block Diagram

12.4.2.1 PWM Enable

Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx

bits are set (PWMEx = 1), the associated PWM output signal is enabled immediately. However, the actual

PWM waveform is not available on the associated PWM output until its clock source begins its next cycle

due to the synchronization of PWMEx and the clock source. An exception to this is when channels are

concatenated. Refer to Section 12.4.2.7, “PWM 16-Bit Functions” for more detail.

NOTE

The ﬁrst PWM cycle after enabling the channel can be irregular.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high.

There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an

edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count.

12.4.2.2 PWM Polarity

Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. This is shown

on the block diagram as a mux select of either the Q output or the Q output of the PWM output ﬂip ﬂop.

When one of the bits in the PWMPOL register is set, the associated PWM channel output is high at the

beginning of the waveform, then goes low when the duty count is reached. Conversely, if the polarity bit

is zero, the output starts low and then goes high when the duty count is reached.

12.4.2.3 PWM Period and Duty

Dedicated period and duty registers exist for each channel and are double buffered so that if they change

while the channel is enabled, the change will NOT take effect until one of the following occurs:

•

The effective period ends

The counter is written (counter resets to $00)

The channel is disabled

In this way, the output of the PWM will always be either the old waveform or the new waveform, not some

variation in between. If the channel is not enabled, then writes to the period and duty registers will go

directly to the latches as well as the buffer.

A change in duty or period can be forced into effect “immediately” by writing the new value to the duty

and/or period registers and then writing to the counter. This forces the counter to reset and the new duty

and/or period values to be latched. In addition, since the counter is readable, it is possible to know where

the count is with respect to the duty value and software can be used to make adjustments

NOTE

When forcing a new period or duty into effect immediately, an irregular

PWM cycle can occur.

Depending on the polarity bit, the duty registers will contain the count of

either the high time or the low time.

12.4.2.4 PWM Timer Counters

Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (see

Section 12.4.1, “PWM Clock Select” for the available clock sources and rates). The counter compares to

two registers, a duty register and a period register as shown in Figure 12-19. When the PWM counter

matches the duty register, the output ﬂip-ﬂop changes state, causing the PWM waveform to also change

state. A match between the PWM counter and the period register behaves differently depending on what

output mode is selected as shown in Figure 12-19 and described in Section 12.4.2.5, “Left Aligned

Outputs” and Section 12.4.2.6, “Center Aligned Outputs”.

MC9S12XDP512 Data Sheet, Rev. 2.11

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583

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

Each channel counter can be read at anytime without affecting the count or the operation of the PWM

channel.

Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up,

the immediate load of both duty and period registers with values from the buffers, and the output to change

according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops. When a

channel becomes enabled (PWMEx = 1), the associated PWM counter continues from the count in the

PWMCNTx register. This allows the waveform to continue where it left off when the channel is

re-enabled. When the channel is disabled, writing “0” to the period register will cause the counter to reset

on the next selected clock.

NOTE

If the user wants to start a new “clean” PWM waveform without any

“history” from the old waveform, the user must write to channel counter

(PWMCNTx) prior to enabling the PWM channel (PWMEx = 1).

Generally, writes to the counter are done prior to enabling a channel in order to start from a known state.

However, writing a counter can also be done while the PWM channel is enabled (counting). The effect is

similar to writing the counter when the channel is disabled, except that the new period is started

immediately with the output set according to the polarity bit.

NOTE

Writing to the counter while the channel is enabled can cause an irregular

PWM cycle to occur.

The counter is cleared at the end of the effective period (see Section 12.4.2.5, “Left Aligned Outputs” and

Section 12.4.2.6, “Center Aligned Outputs” for more details).

Table 12-10. PWM Timer Counter Conditions

Counter Clears ($00)

Counter Counts

Counter Stops

When PWMCNTx register written to

any value

When PWM channel is enabled

(PWMEx = 1). Counts from last value in

PWMCNTx.

When PWM channel is disabled

(PWMEx = 0)

Effective period ends

12.4.2.5 Left Aligned Outputs

The PWM timer provides the choice of two types of outputs, left aligned or center aligned. They are

selected with the CAEx bits in the PWMCAE register. If the CAEx bit is cleared (CAEx = 0), the

corresponding PWM output will be left aligned.

In left aligned output mode, the 8-bit counter is conﬁgured as an up counter only. It compares to two

registers, a duty register and a period register as shown in the block diagram in Figure 12-19. When the

PWM counter matches the duty register the output ﬂip-ﬂop changes state causing the PWM waveform to

also change state. A match between the PWM counter and the period register resets the counter and the

output ﬂip-ﬂop, as shown in Figure 12-19, as well as performing a load from the double buffer period and

duty register to the associated registers, as described in Section 12.4.2.3, “PWM Period and Duty”. The

counter counts from 0 to the value in the period register – 1.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

NOTE

Changing the PWM output mode from left aligned to center aligned output

(or vice versa) while channels are operating can cause irregularities in the

PWM output. It is recommended to program the output mode before

enabling the PWM channel.

PPOLx = 0

PPOLx = 1

PWMDTYx

Period = PWMPERx

Figure 12-20. PWM Left Aligned Output Waveform

To calculate the output frequency in left aligned output mode for a particular channel, take the selected

clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register

for that channel.

•

PWMx Frequency = Clock (A, B, SA, or SB) / PWMPERx

PWMx Duty Cycle (high time as a% of period):

— Polarity = 0 (PPOLx = 0)

•

Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%

— Polarity = 1 (PPOLx = 1)

Duty Cycle = [PWMDTYx / PWMPERx] * 100%

As an example of a left aligned output, consider the following case:

Clock Source = E, where E = 10 MHz (100 ns period)

PPOLx = 0

PWMPERx = 4

PWMDTYx = 1

PWMx Frequency = 10 MHz/4 = 2.5 MHz

PWMx Period = 400 ns

PWMx Duty Cycle = 3/4 *100% = 75%

The output waveform generated is shown in Figure 12-21.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

E = 100 ns

Duty Cycle = 75%

Period = 400 ns

Figure 12-21. PWM Left Aligned Output Example Waveform

12.4.2.6 Center Aligned Outputs

For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the

corresponding PWM output will be center aligned.

The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is

equal to $00. The counter compares to two registers, a duty register and a period register as shown in the

block diagram in Figure 12-19. When the PWM counter matches the duty register, the output ﬂip-ﬂop

changes state, causing the PWM waveform to also change state. A match between the PWM counter and

the period register changes the counter direction from an up-count to a down-count. When the PWM

counter decrements and matches the duty register again, the output ﬂip-ﬂop changes state causing the

PWM output to also change state. When the PWM counter decrements and reaches zero, the counter

direction changes from a down-count back to an up-count and a load from the double buffer period and

duty registers to the associated registers is performed, as described in Section 12.4.2.3, “PWM Period and

Duty”. The counter counts from 0 up to the value in the period register and then back down to 0. Thus the

effective period is PWMPERx*2.

NOTE

Changing the PWM output mode from left aligned to center aligned output

(or vice versa) while channels are operating can cause irregularities in the

PWM output. It is recommended to program the output mode before

enabling the PWM channel.

PPOLx = 0

PPOLx = 1

PWMDTYx

PWMPERx

PWMDTYx

PWMPERx

Period = PWMPERx*2

Figure 12-22. PWM Center Aligned Output Waveform

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

To calculate the output frequency in center aligned output mode for a particular channel, take the selected

clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period

•

PWMx Frequency = Clock (A, B, SA, or SB) / (2*PWMPERx)

PWMx Duty Cycle (high time as a% of period):

— Polarity = 0 (PPOLx = 0)

Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%

— Polarity = 1 (PPOLx = 1)

Duty Cycle = [PWMDTYx / PWMPERx] * 100%

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

As an example of a center aligned output, consider the following case:

Clock Source = E, where E = 10 MHz (100 ns period)

PPOLx = 0

PWMPERx = 4

PWMDTYx = 1

PWMx Frequency = 10 MHz/8 = 1.25 MHz

PWMx Period = 800 ns

PWMx Duty Cycle = 3/4 *100% = 75%

Shown in Figure 12-23 is the output waveform generated.

E = 100 ns

DUTY CYCLE = 75%

PERIOD = 800 ns

Figure 12-23. PWM Center Aligned Output Example Waveform

12.4.2.7 PWM 16-Bit Functions

The PWM timer also has the option of generating 8-channels of 8-bits or 4-channels of 16-bits for greater

PWM resolution. This 16-bit channel option is achieved through the concatenation of two 8-bit channels.

The PWMCTL register contains four control bits, each of which is used to concatenate a pair of PWM

channels into one 16-bit channel. Channels 6 and 7 are concatenated with the CON67 bit, channels 4 and

5 are concatenated with the CON45 bit, channels 2 and 3 are concatenated with the CON23 bit, and

channels 0 and 1 are concatenated with the CON01 bit.

NOTE

Change these bits only when both corresponding channels are disabled.

When channels 6 and 7 are concatenated, channel 6 registers become the high order bytes of the double

byte channel, as shown in Figure 12-24. Similarly, when channels 4 and 5 are concatenated, channel 4

registers become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated,

channel 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are

concatenated, channel 0 registers become the high order bytes of the double byte channel.

When using the 16-bit concatenated mode, the clock source is determined by the low order 8-bit channel

clock select control bits. That is channel 7 when channels 6 and 7 are concatenated, channel 5 when

channels 4 and 5 are concatenated, channel 3 when channels 2 and 3 are concatenated, and channel 1 when

channels 0 and 1 are concatenated. The resulting PWM is output to the pins of the corresponding low order

8-bit channel as also shown in Figure 12-24. The polarity of the resulting PWM output is controlled by the

PPOLx bit of the corresponding low order 8-bit channel as well.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

Clock Source 7

High

Low

PWMCNT6

PWCNT7

PWM7

Period/Duty Compare

Clock Source 5

Clock Source 3

Clock Source 1

High

Low

PWMCNT4

PWCNT5

PWM5

PWM3

PWM1

Period/Duty Compare

High

Low

PWMCNT2

PWCNT3

Period/Duty Compare

High

Low

PWMCNT0

PWCNT1

Period/Duty Compare

Figure 12-24. PWM 16-Bit Mode

Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the

corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order

bytes PWMEx bits have no effect and their corresponding PWM output is disabled.

In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or

high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by

16-bit access to maintain data coherency.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by

the low order CAEx bit. The high order CAEx bit has no effect.

Table 12-11 is used to summarize which channels are used to set the various control bits when in 16-bit

mode.

Table 12-11. 16-bit Concatenation Mode Summary

PWMx

Output

CONxx

PWMEx

PPOLx

PCLKx

CAEx

CON67

CON45

CON23

CON01

PWME7

PWME5

PWME3

PWME1

PPOL7

PPOL5

PPOL3

PPOL1

PCLK7

PCLK5

PCLK3

PCLK1

CAE7

CAE5

CAE3

CAE1

PWM7

PWM5

PWM3

PWM1

12.4.2.8 PWM Boundary Cases

Table 12-12 summarizes the boundary conditions for the PWM regardless of the output mode (left aligned

or center aligned) and 8-bit (normal) or 16-bit (concatenation).

Table 12-12. PWM Boundary Cases

PWMDTYx

PWMPERx

PPOLx

PWMx Output

$00

>$00

Always low

(indicates no duty)

$00

>$00

Always high

Always low

(indicates no duty)

$00

(indicates no period)

$00

(indicates no period)

>= PWMPERx

Always high

Always low

Counter = $00 and does not count.

12.5 Resets

The reset state of each individual bit is listed within the Section 12.3.2, “Register Descriptions” which

details the registers and their bit-ﬁelds. All special functions or modes which are initialized during or just

following reset are described within this section.

•

The 8-bit up/down counter is conﬁgured as an up counter out of reset.

All the channels are disabled and all the counters do not count.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

12.6 Interrupts

The PWM module has only one interrupt which is generated at the time of emergency shutdown, if the

corresponding enable bit (PWMIE) is set. This bit is the enable for the interrupt. The interrupt ﬂag PWMIF

is set whenever the input level of the PWM7 channel changes while PWM7ENA = 1 or when PWMENA

is being asserted while the level at PWM7 is active.

In stop mode or wait mode (with the PSWAI bit set), the emergency shutdown feature will drive the PWM

outputs to their shutdown output levels but the PWMIF ﬂag will not be set.

A description of the registers involved and affected due to this interrupt is explained in Section 12.3.2.15,

“PWM Shutdown Register (PWMSDN)”.

The PWM block only generates the interrupt and does not service it. The interrupt signal name is PWM

interrupt signal.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

591

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Chapter 12 Pulse-Width Modulator (S12PWM8B8CV1)

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 13

Inter-Integrated Circuit (MC9S12XDP512) Block Description

13.1 Introduction

The inter-IC bus (IIC) is a two-wire, bidirectional serial bus that provides a simple, efﬁcient method of data

exchange between devices. Being a two-wire device, the IIC bus minimizes the need for large numbers of

connections between devices, and eliminates the need for an address decoder.

This bus is suitable for applications requiring occasional communications over a short distance between a

number of devices. It also provides ﬂexibility, allowing additional devices to be connected to the bus for

further expansion and system development.

The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is

capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The

maximum communication length and the number of devices that can be connected are limited by a

maximum bus capacitance of 400 pF.

13.1.1 Features

The IIC module has the following key features:

•

Compatible with I2C bus standard

Multi-master operation

Software programmable for one of 256 different serial clock frequencies

Software selectable acknowledge bit

Interrupt driven byte-by-byte data transfer

Arbitration lost interrupt with automatic mode switching from master to slave

Calling address identiﬁcation interrupt

Start and stop signal generation/detection

Repeated start signal generation

Acknowledge bit generation/detection

Bus busy detection

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

13.1.2 Modes of Operation

The IIC functions the same in normal, special, and emulation modes. It has two low power modes: wait

and stop modes.

13.1.3 Block Diagram

The block diagram of the IIC module is shown in Figure 13-1.

IIC

Start

Stop

Arbitration

Registers

Control

Interrupt

In/Out

Data

Shift

SCL

Clock

Control

bus_clock

SDA

Address

Compare

Figure 13-1. IIC Block Diagram

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

13.2 External Signal Description

The MC9S12XDP512 module has two external pins.

13.2.1 IIC_SCL — Serial Clock Line Pin

This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus speciﬁcation.

13.2.2 IIC_SDA — Serial Data Line Pin

This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus speciﬁcation.

13.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all memory and registers for the IIC module.

13.3.1 Module Memory Map

The memory map for the IIC module is given below in Table 13-1. The address listed for each register is

the address offset.The total address for each register is the sum of the base address for the IIC module and

the address offset for each register.

Table 13-1. IIC Memory Map

Address

Offset

Use

Access

0x0000

0x0001

0x0002

0x0003

0x0004

IIC-Bus Address Register (IBAD)

R/W

IIC-Bus Frequency Divider Register (IBFD)

IIC-Bus Control Register (IBCR)

IIC-Bus Status Register (IBSR)

IIC-Bus Data I/O Register (IBDR)

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

13.3.2 Register Descriptions

This section consists of register descriptions in address order. Each description includes a standard register

diagram with an associated ﬁgure number. Details of register bit and ﬁeld function follow the register

diagrams, in bit order.

Name

Bit 7

Bit 0

0x0000

IBAD

ADR7

ADR6

ADR5

ADR4

ADR3

ADR2

ADR1

0x0001

IBFD

IBC7

IBC6

IBC5

IBC4

Tx/Rx

IBAL

IBC3

IBC2

IBC1

IBC0

0x0002

IBCR

IBEN

TCF

IBIE

MS/SL

IBB

TXAK

IBSWAI

RXAK

RSTA

0x0003

IBSR

IAAS

SRW

IBIF

0x0004

IBDR

= Unimplemented or Reserved

Figure 13-2. IIC Register Summary

13.3.2.1 IIC Address Register (IBAD)

Offset Module Base +0x0000

ADR7

ADR6

ADR5

ADR4

ADR3

ADR2

ADR1

Reset

= Unimplemented or Reserved

Figure 13-3. IIC Bus Address Register (IBAD)

Read and write anytime

This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not

the address sent on the bus during the address transfer.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

Table 13-2. IBAD Field Descriptions

Field

Description

7:1

Slave Address — Bit 1 to bit 7 contain the speciﬁc slave address to be used by the IIC bus module.The default

ADR[7:1]

mode of IIC bus is slave mode for an address match on the bus.

Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0.

Reserved

13.3.2.2 IIC Frequency Divider Register (IBFD)

Offset Module Base + 0x0001

IBC7

IBC6

IBC5

IBC4

IBC3

IBC2

IBC1

IBC0

Reset

= Unimplemented or Reserved

Figure 13-4. IIC Bus Frequency Divider Register (IBFD)

Read and write anytime

Table 13-3. IBFD Field Descriptions

Description

Field

7:0

IBC[7:0]

I Bus Clock Rate 7:0 — This ﬁeld is used to prescale the clock for bit rate selection. The bit clock generator is

implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and

IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown

in Table 13-4.

Table 13-4. I-Bus Tap and Prescale Values

IBC2-0

(bin)

SCL Tap

(clocks)

SDA Tap

(clocks)

000

001

010

011

100

101

110

111

IBC5-3

(bin)

scl2start

(clocks)

scl2stop

(clocks)

scl2tap

(clocks)

tap2tap

(clocks)

000

001

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

IBC5-3

(bin)

scl2start

(clocks)

scl2stop

(clocks)

scl2tap

(clocks)

tap2tap

(clocks)

010

011

100

101

110

111

126

129

126

128

Table 13-5. Multiplier Factor

IBC7-6

MUL

RESERVED

The number of clocks from the falling edge of SCL to the ﬁrst tap (Tap[1]) is deﬁned by the values shown

IBC5-3

in the scl2tap column of Table 13-4, all subsequent tap points are separated by 2

as shown in the

tap2tap column in Table 13-4. The SCL Tap is used to generated the SCL period and the SDA Tap is used

to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time.

IBC7–6 deﬁnes the multiplier factor MUL. The values of MUL are shown in the Table 13-5.

SCL Divider

SCL

SDA Hold

SDA

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

SDA

SCL

SCL Hold(stop)

SCL Hold(start)

START condition

STOP condition

Figure 13-5. SCL Divider and SDA Hold

The equation used to generate the divider values from the IBFD bits is:

SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)}

The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in

Table 13-6. The equation used to generate the SDA Hold value from the IBFD bits is:

SDA Hold = MUL x {scl2tap + [(SDA_Tap - 1) x tap2tap] + 3}

The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is:

SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap]

SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap]

Table 13-6. IIC Divider and Hold Values (Sheet 1 of 5)

IBC[7:0]

(hex)

SCL Divider

(clocks)

SDA Hold

(clocks)

SCL Hold

(start)

SCL Hold

(stop)

MUL=1

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

Table 13-6. IIC Divider and Hold Values (Sheet 2 of 5)

IBC[7:0]

(hex)

SCL Divider

(clocks)

SDA Hold

(clocks)

SCL Hold

(start)

SCL Hold

(stop)

104

128

112

128

144

160

192

240

160

192

224

256

288

320

384

480

320

384

448

512

576

640

768

960

640

768

896

1024

1152

1280

1536

1920

1280

1536

1792

2048

2304

2560

118

121

110

126

142

158

190

238

158

190

222

254

286

318

382

478

318

382

446

510

574

638

766

958

638

766

894

1022

1150

1278

113

129

145

161

193

241

161

193

225

257

289

321

385

481

321

385

449

513

577

641

769

961

641

769

897

1025

1153

1281

129

193

257

129

257

385

MC9S12XDP512 Data Sheet, Rev. 2.11

600

Freescale Semiconductor

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

Table 13-6. IIC Divider and Hold Values (Sheet 3 of 5)

IBC[7:0]

(hex)

SCL Divider

(clocks)

SDA Hold

(clocks)

SCL Hold

(start)

SCL Hold

(stop)

3072

3840

513

1534

1918

1537

1921

MUL=2

130

112

136

112

128

144

160

176

208

256

160

192

224

256

288

320

384

480

320

384

448

512

576

640

768

960

640

768

106

130

116

108

124

140

156

188

236

156

188

220

252

284

316

380

476

316

380

114

130

146

162

194

242

162

194

226

258

290

322

386

482

322

386

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

Table 13-6. IIC Divider and Hold Values (Sheet 4 of 5)

IBC[7:0]

(hex)

SCL Divider

(clocks)

SDA Hold

(clocks)

SCL Hold

(start)

SCL Hold

(stop)

896

130

194

258

130

258

386

514

258

514

770

1026

444

508

450

514

1024

1152

1280

1536

1920

1280

1536

1792

2048

2304

2560

3072

3840

2560

3072

3584

4096

4608

5120

6144

7680

572

578

636

642

764

770

956

962

636

642

764

770

892

898

1020

1148

1276

1532

1916

1276

1532

1788

2044

2300

2556

3068

3836

1026

1154

1282

1538

1922

1282

1538

1794

2050

2306

2562

3074

3842

MUL=4

104

112

120

136

160

112

128

144

160

176

192

224

272

192

224

256

288

320

352

100

116

140

100

116

132

148

164

180

120

104

120

136

152

MC9S12XDP512 Data Sheet, Rev. 2.11

602

Freescale Semiconductor

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

Table 13-6. IIC Divider and Hold Values (Sheet 5 of 5)

IBC[7:0]

(hex)

SCL Divider

(clocks)

SDA Hold

(clocks)

SCL Hold

(start)

SCL Hold

(stop)

416

512

184

232

212

260

320

152

164

384

184

196

448

216

228

512

248

260

576

100

132

280

292

640

312

324

768

376

388

960

472

484

640

312

324

768

376

388

896

132

196

260

132

260

388

516

260

516

772

1028

516

1028

1540

2052

440

452

1024

1152

1280

1536

1920

1280

1536

1792

2048

2304

2560

3072

3840

2560

3072

3584

4096

4608

5120

6144

7680

5120

6144

7168

8192

9216

10240

12288

15360

504

516

568

580

632

644

760

772

952

964

632

644

760

772

888

900

1016

1144

1272

1528

1912

1272

1528

1784

2040

2296

2552

3064

3832

2552

3064

3576

4088

4600

5112

6136

7672

1028

1156

1284

1540

1924

1284

1540

1796

2052

2308

2564

3076

3844

2564

3076

3588

4100

4612

5124

6148

7684

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

603

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

13.3.2.3 IIC Control Register (IBCR)

Offset Module Base + 0x0002

IBEN

IBIE

MS/SL

Tx/Rx

TXAK

IBSWAI

RSTA

Reset

= Unimplemented or Reserved

Figure 13-6. IIC Bus Control Register (IBCR)

Read and write anytime

Table 13-7. IBCR Field Descriptions

Description

Field

I-Bus Enable — This bit controls the software reset of the entire IIC bus module.

IBEN

0 The module is reset and disabled. This is the power-on reset situation. When low the interface is held in reset

but registers can be accessed

1 The IIC bus module is enabled.This bit must be set before any other IBCR bits have any effect

If the IIC bus module is enabled in the middle of a byte transfer the interface behaves as follows: slave mode

ignores the current transfer on the bus and starts operating whenever a subsequent start condition is detected.

Master mode will not be aware that the bus is busy, hence if a start cycle is initiated then the current bus cycle

may become corrupt. This would ultimately result in either the current bus master or the IIC bus module losing

arbitration, after which bus operation would return to normal.

I-Bus Interrupt Enable

IBIE

Interrupts from the IIC bus module are disabled. Note that this does not clear any currently pending interrupt

condition

1 Interrupts from the IIC bus module are enabled. An IIC bus interrupt occurs provided the IBIF bit in the status

Master/Slave Mode Select Bit — Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START

MS/SL

signal is generated on the bus, and the master mode is selected. When this bit is changed from 1 to 0, a STOP

signal is generated and the operation mode changes from master to slave.A STOP signal should only be

generated if the IBIF ﬂag is set. MS/SL is cleared without generating a STOP signal when the master loses

arbitration.

0 Slave Mode

1 Master Mode

Transmit/Receive Mode Select Bit — This bit selects the direction of master and slave transfers. When

Tx/Rx

addressed as a slave this bit should be set by software according to the SRW bit in the status register. In master

mode this bit should be set according to the type of transfer required. Therefore, for address cycles, this bit will

always be high.

0 Receive

1 Transmit

Transmit Acknowledge Enable — This bit speciﬁes the value driven onto SDA during data acknowledge cycles

for both master and slave receivers. The IIC module will always acknowledge address matches, provided it is

enabled, regardless of the value of TXAK. Note that values written to this bit are only used when the IIC bus is a

receiver, not a transmitter.

TXAK

0 An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte data

1 No acknowledge signal response is sent (i.e., acknowledge bit = 1)

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

Table 13-7. IBCR Field Descriptions (continued)

Field

Description

Repeat Start — Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is the

current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong time, if the bus

is owned by another master, will result in loss of arbitration.

RSTA

1 Generate repeat start cycle

Reserved — Bit 1 of the IBCR is reserved for future compatibility. This bit will always read 0.

RESERVED

I Bus Interface Stop in Wait Mode

IBSWAI

0 IIC bus module clock operates normally

1 Halt IIC bus module clock generation in wait mode

Wait mode is entered via execution of a CPU WAI instruction. In the event that the IBSWAI bit is set, all

clocks internal to the IIC will be stopped and any transmission currently in progress will halt.If the CPU

were woken up by a source other than the IIC module, then clocks would restart and the IIC would resume

from where was during the previous transmission. It is not possible for the IIC to wake up the CPU when

its internal clocks are stopped.

If it were the case that the IBSWAI bit was cleared when the WAI instruction was executed, the IIC internal

clocks and interface would remain alive, continuing the operation which was currently underway. It is also

possible to conﬁgure the IIC such that it will wake up the CPU via an interrupt at the conclusion of the

current operation. See the discussion on the IBIF and IBIE bits in the IBSR and IBCR, respectively.

13.3.2.4 IIC Status Register (IBSR)

Offset Module Base + 0x0003

TCF

IAAS

IBB

SRW

RXAK

IBAL

IBIF

Reset

= Unimplemented or Reserved

Figure 13-7. IIC Bus Status Register (IBSR)

This status register is read-only with exception of bit 1 (IBIF) and bit 4 (IBAL), which are software

clearable.

Table 13-8. IBSR Field Descriptions

Field

Description

Data Transferring Bit — While one byte of data is being transferred, this bit is cleared. It is set by the falling

TCF

edge of the 9th clock of a byte transfer. Note that this bit is only valid during or immediately following a transfer

to the IIC module or from the IIC module.

0 Transfer in progress

1 Transfer complete

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

Table 13-8. IBSR Field Descriptions (continued)

Field

Description

Addressed as a Slave Bit — When its own speciﬁc address (I-bus address register) is matched with the calling

address, this bit is set.The CPU is interrupted provided the IBIE is set.Then the CPU needs to check the SRW

bit and set its Tx/Rx mode accordingly.Writing to the I-bus control register clears this bit.

0 Not addressed

IAAS

1 Addressed as a slave

Bus Busy Bit

IBB

0 This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a STOP signal is

detected, IBB is cleared and the bus enters idle state.

1 Bus is busy

IBAL

Arbitration Lost — The arbitration lost bit (IBAL) is set by hardware when the arbitration procedure is lost.

Arbitration is lost in the following circumstances:

1. SDA sampled low when the master drives a high during an address or data transmit cycle.

2. SDA sampled low when the master drives a high during the acknowledge bit of a data receive cycle.

3. A start cycle is attempted when the bus is busy.

4. A repeated start cycle is requested in slave mode.

5. A stop condition is detected when the master did not request it.

This bit must be cleared by software, by writing a one to it. A write of 0 has no effect on this bit.

Reserved — Bit 3 of IBSR is reserved for future use. A read operation on this bit will return 0.

RESERVED

Slave Read/Write — When IAAS is set this bit indicates the value of the R/W command bit of the calling address

sent from the master

SRW

This bit is only valid when the I-bus is in slave mode, a complete address transfer has occurred with an address

match and no other transfers have been initiated.

Checking this bit, the CPU can select slave transmit/receive mode according to the command of the master.

0 Slave receive, master writing to slave

1 Slave transmit, master reading from slave

IBIF

I-Bus Interrupt — The IBIF bit is set when one of the following conditions occurs:

— Arbitration lost (IBAL bit set)

— Byte transfer complete (TCF bit set)

— Addressed as slave (IAAS bit set)

It will cause a processor interrupt request if the IBIE bit is set. This bit must be cleared by software, writing a one

to it. A write of 0 has no effect on this bit.

Received Acknowledge — The value of SDA during the acknowledge bit of a bus cycle. If the received

acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the completion of 8

bits data transmission on the bus. If RXAK is high, it means no acknowledge signal is detected at the 9th clock.

0 Acknowledge received

RXAK

1 No acknowledge received

MC9S12XDP512 Data Sheet, Rev. 2.11

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Freescale Semiconductor

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

13.3.2.5 IIC Data I/O Register (IBDR)

Offset Module Base + 0x0004

Reset

Figure 13-8. IIC Bus Data I/O Register (IBDR)

In master transmit mode, when data is written to the IBDR a data transfer is initiated. The most signiﬁcant

bit is sent ﬁrst. In master receive mode, reading this register initiates next byte data receiving. In slave

mode, the same functions are available after an address match has occurred.Note that the Tx/Rx bit in the

IBCR must correctly reﬂect the desired direction of transfer in master and slave modes for the transmission

to begin. For instance, if the IIC is conﬁgured for master transmit but a master receive is desired, then

reading the IBDR will not initiate the receive.

Reading the IBDR will return the last byte received while the IIC is conﬁgured in either master receive or

slave receive modes. The IBDR does not reﬂect every byte that is transmitted on the IIC bus, nor can

software verify that a byte has been written to the IBDR correctly by reading it back.

In master transmit mode, the ﬁrst byte of data written to IBDR following assertion of MS/SL is used for

the address transfer and should com.prise of the calling address (in position D7:D1) concatenated with the

required R/W bit (in position D0).

13.4 Functional Description

This section provides a complete functional description of the MC9S12XDP512.

13.4.1

I-Bus Protocol

The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices

connected to it must have open drain or open collector outputs. Logic AND function is exercised on both

lines with external pull-up resistors. The value of these resistors is system dependent.

Normally, a standard communication is composed of four parts: START signal, slave address transmission,

data transfer and STOP signal. They are described brieﬂy in the following sections and illustrated in

Figure 13-9.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

MSB

LSB

MSB

LSB

SCL

SDA

AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W

XXX

D7 D6 D5 D4 D3 D2 D1 D0

Start

Signal

Calling Address

Read/ Ack

Bit

Data Byte

No Stop

Ack Signal

Bit

Write

MSB

LSB

MSB

LSB

SCL

SDA

AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W

Start

Signal

Calling Address

Read/ Ack

Bit

Repeated

Start

Signal

New Calling Address

No Stop

Ack Signal

Bit

Read/

Write

Figure 13-9. IIC-Bus Transmission Signals

13.4.1.1 START Signal

When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical

high), a master may initiate communication by sending a START signal.As shown in Figure 13-9, a

START signal is deﬁned as a high-to-low transition of SDA while SCL is high. This signal denotes the

beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves

out of their idle states.

SDA

SCL

START Condition

STOP Condition

Figure 13-10. Start and Stop Conditions

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

13.4.1.2 Slave Address Transmission

The ﬁrst byte of data transfer immediately after the START signal is the slave address transmitted by the

master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired

direction of data transfer.

1 = Read transfer, the slave transmits data to the master.

0 = Write transfer, the master transmits data to the slave.

Only the slave with a calling address that matches the one transmitted by the master will respond by

sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 13-9).

No two slaves in the system may have the same address. If the IIC bus is master, it must not transmit an

address that is equal to its own slave address. The IIC bus cannot be master and slave at the same

time.However, if arbitration is lost during an address cycle the IIC bus will revert to slave mode and operate

correctly even if it is being addressed by another master.

13.4.1.3 Data Transfer

As soon as successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a

direction speciﬁed by the R/W bit sent by the calling master

All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address

information for the slave device.

Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while

SCL is high as shown in Figure 13-9. There is one clock pulse on SCL for each data bit, the MSB being

transferred ﬁrst. Each data byte has to be followed by an acknowledge bit, which is signalled from the

receiving device by pulling the SDA low at the ninth clock. So one complete data byte transfer needs nine

clock pulses.

If the slave receiver does not acknowledge the master, the SDA line must be left high by the slave. The

master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to

commence a new calling.

If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end

of data' to the slave, so the slave releases the SDA line for the master to generate STOP or START signal.

13.4.1.4 STOP Signal

The master can terminate the communication by generating a STOP signal to free the bus. However, the

master may generate a START signal followed by a calling command without generating a STOP signal

ﬁrst. This is called repeated START. A STOP signal is deﬁned as a low-to-high transition of SDA while

SCL at logical 1 (see Figure 13-9).

The master can generate a STOP even if the slave has generated an acknowledge at which point the slave

must release the bus.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

13.4.1.5 Repeated START Signal

As shown in Figure 13-9, a repeated START signal is a START signal generated without ﬁrst generating a

STOP signal to terminate the communication. This is used by the master to communicate with another

slave or with the same slave in different mode (transmit/receive mode) without releasing the bus.

13.4.1.6 Arbitration Procedure

The Inter-IC bus is a true multi-master bus that allows more than one master to be connected on it. If two

or more masters try to control the bus at the same time, a clock synchronization procedure determines the

bus clock, for which the low period is equal to the longest clock low period and the high is equal to the

shortest one among the masters. The relative priority of the contending masters is determined by a data

arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits

logic 0. The losing masters immediately switch over to slave receive mode and stop driving SDA output.

In this case the transition from master to slave mode does not generate a STOP condition. Meanwhile, a

status bit is set by hardware to indicate loss of arbitration.

13.4.1.7 Clock Synchronization

Because wire-AND logic is performed on SCL line, a high-to-low transition on SCL line affects all the

devices connected on the bus. The devices start counting their low period and as soon as a device's clock

has gone low, it holds the SCL line low until the clock high state is reached.However, the change of low to

high in this device clock may not change the state of the SCL line if another device clock is within its low

period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices

with shorter low periods enter a high wait state during this time (see Figure 13-10). When all devices

concerned have counted off their low period, the synchronized clock SCL line is released and pulled high.

There is then no difference between the device clocks and the state of the SCL line and all the devices start

counting their high periods.The ﬁrst device to complete its high period pulls the SCL line low again.

Start Counting High Period

WAIT

SCL1

SCL2

SCL

Internal Counter Reset

Figure 13-11. IIC-Bus Clock Synchronization

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

13.4.1.8 Handshaking

The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold

the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces

the master clock into wait states until the slave releases the SCL line.

13.4.1.9 Clock Stretching

The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After

the master has driven SCL low the slave can drive SCL low for the required period and then release it.If

the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low

period is stretched.

13.4.2 Operation in Run Mode

This is the basic mode of operation.

13.4.3 Operation in Wait Mode

IIC operation in wait mode can be conﬁgured. Depending on the state of internal bits, the IIC can operate

normally when the CPU is in wait mode or the IIC clock generation can be turned off and the IIC module

enters a power conservation state during wait mode. In the later case, any transmission or reception in

progress stops at wait mode entry.

13.4.4 Operation in Stop Mode

The IIC is inactive in stop mode for reduced power consumption. The STOP instruction does not affect IIC

13.5 Resets

The reset state of each individual bit is listed in Section 13.3, “Memory Map and Register Deﬁnition,”

which details the registers and their bit-ﬁelds.

13.6 Interrupts

MC9S12XDP512 uses only one interrupt vector.

Table 13-9. Interrupt Summary

Interrupt Offset

Vector

Priority

Source

Description

IIC

—

IBAL, TCF, IAAS When either of IBAL, TCF or IAAS bits is set

Interrupt

bits in IBSR

may cause an interrupt based on arbitration

lost, transfer complete or address detect

conditions

Internally there are three types of interrupts in IIC. The interrupt service routine can determine the interrupt

type by reading the status register.

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

IIC Interrupt can be generated on

1. Arbitration lost condition (IBAL bit set)

2. Byte transfer condition (TCF bit set)

3. Address detect condition (IAAS bit set)

The IIC interrupt is enabled by the IBIE bit in the IIC control register. It must be cleared by writing 0 to

the IBF bit in the interrupt service routine.

13.7 Initialization/Application Information

13.7.1 IIC Programming Examples

13.7.1.1 Initialization Sequence

Reset will put the IIC bus control register to its default status. Before the interface can be used to transfer

serial data, an initialization procedure must be carried out, as follows:

1. Update the frequency divider register (IBFD) and select the required division ratio to obtain SCL

frequency from system clock.

2. Update the IIC bus address register (IBAD) to deﬁne its slave address.

3. Set the IBEN bit of the IIC bus control register (IBCR) to enable the IIC interface system.

4. Modify the bits of the IIC bus control register (IBCR) to select master/slave mode, transmit/receive

mode and interrupt enable or not.

13.7.1.2 Generation of START

After completion of the initialization procedure, serial data can be transmitted by selecting the 'master

transmitter' mode. If the device is connected to a multi-master bus system, the state of the IIC bus busy bit

(IBB) must be tested to check whether the serial bus is free.

If the bus is free (IBB=0), the start condition and the ﬁrst byte (the slave address) can be sent. The data

written to the data register comprises the slave calling address and the LSB set to indicate the direction of

transfer required from the slave.

The bus free time (i.e., the time between a STOP condition and the following START condition) is built

into the hardware that generates the START cycle. Depending on the relative frequencies of the system

clock and the SCL period it may be necessary to wait until the IIC is busy after writing the calling address

to the IBDR before proceeding with the following instructions. This is illustrated in the following example.

An example of a program which generates the START signal and transmits the ﬁrst byte of data (slave

address) is shown below:

CHFLAG

TXSTART

BRSET

BSET

IBSR,#$20,*

IBCR,#$30

;WAIT FOR IBB FLAG TO CLEAR

;SET TRANSMIT AND MASTER MODE;i.e. GENERATE START CONDITION

MOVB

CALLING,IBDR ;TRANSMIT THE CALLING ADDRESS, D0=R/W

IBFREE

BRCLR IBSR,#$20,*

;WAIT FOR IBB FLAG TO SET

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

13.7.1.3 Post-Transfer Software Response

Transmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte

communication is ﬁnished. The IIC bus interrupt bit (IBIF) is set also; an interrupt will be generated if the

interrupt function is enabled during initialization by setting the IBIE bit. Software must clear the IBIF bit

in the interrupt routine ﬁrst. The TCF bit will be cleared by reading from the IIC bus data I/O register

(IBDR) in receive mode or writing to IBDR in transmit mode.

Software may service the IIC I/O in the main program by monitoring the IBIF bit if the interrupt function

is disabled. Note that polling should monitor the IBIF bit rather than the TCF bit because their operation

is different when arbitration is lost.

Note that when an interrupt occurs at the end of the address cycle the master will always be in transmit

mode, i.e. the address is transmitted. If master receive mode is required, indicated by R/W bit in IBDR,

then the Tx/Rx bit should be toggled at this stage.

During slave mode address cycles (IAAS=1), the SRW bit in the status register is read to determine the

direction of the subsequent transfer and the Tx/Rx bit is programmed accordingly. For slave mode data

cycles (IAAS=0) the SRW bit is not valid, the Tx/Rx bit in the control register should be read to determine

the direction of the current transfer.

The following is an example of a software response by a 'master transmitter' in the interrupt routine.

ISR

BCLR

IBSR,#$02

;CLEAR THE IBIF FLAG

BRCLR

BRSET

MOVB

IBCR,#$20,SLAVE

IBCR,#$10,RECEIVE

IBSR,#$01,END

DATABUF,IBDR

;BRANCH IF IN SLAVE MODE

;BRANCH IF IN RECEIVE MODE

;IF NO ACK, END OF TRANSMISSION

;TRANSMIT NEXT BYTE OF DATA

TRANSMIT

13.7.1.4 Generation of STOP

A data transfer ends with a STOP signal generated by the 'master' device. A master transmitter can simply

generate a STOP signal after all the data has been transmitted. The following is an example showing how

a stop condition is generated by a master transmitter.

MASTX

TST

BEQ

TXCNT

END

;GET VALUE FROM THE TRANSMITING COUNTER

;END IF NO MORE DATA

BRSET

MOVB

DEC

IBSR,#$01,END

DATABUF,IBDR

TXCNT

;END IF NO ACK

;TRANSMIT NEXT BYTE OF DATA

;DECREASE THE TXCNT

;EXIT

BRA

EMASTX

END

EMASTX

BCLR

RTI

IBCR,#$20

;GENERATE A STOP CONDITION

;RETURN FROM INTERRUPT

If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not

acknowledging the last byte of data which can be done by setting the transmit acknowledge bit (TXAK)

before reading the 2nd last byte of data. Before reading the last byte of data, a STOP signal must be

generated ﬁrst. The following is an example showing how a STOP signal is generated by a master receiver.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

MASR

DEC

BEQ

MOVB

DEC

BNE

RXCNT

ENMASR

RXCNT,D1

NXMAR

IBCR,#$08

;DECREASE THE RXCNT

;LAST BYTE TO BE READ

;CHECK SECOND LAST BYTE

;TO BE READ

;NOT LAST OR SECOND LAST

;SECOND LAST, DISABLE ACK

;TRANSMITTING

LAMAR

BSET

BRA

NXMAR

ENMASR

NXMAR

BCLR

MOVB

RTI

IBCR,#$20

IBDR,RXBUF

;LAST ONE, GENERATE ‘STOP’ SIGNAL

;READ DATA AND STORE

13.7.1.5 Generation of Repeated START

At the end of data transfer, if the master continues to want to communicate on the bus, it can generate

another START signal followed by another slave address without ﬁrst generating a STOP signal. A

program example is as shown.

RESTART

BSET

IBCR,#$04

;ANOTHER START (RESTART)

MOVB

CALLING,IBDR

;TRANSMIT THE CALLING ADDRESS;D0=R/W

13.7.1.6 Slave Mode

In the slave interrupt service routine, the module addressed as slave bit (IAAS) should be tested to check

if a calling of its own address has just been received. If IAAS is set, software should set the transmit/receive

mode select bit (Tx/Rx bit of IBCR) according to the R/W command bit (SRW). Writing to the IBCR

clears the IAAS automatically. Note that the only time IAAS is read as set is from the interrupt at the end

of the address cycle where an address match occurred, interrupts resulting from subsequent data transfers

will have IAAS cleared. A data transfer may now be initiated by writing information to IBDR, for slave

transmits, or dummy reading from IBDR, in slave receive mode. The slave will drive SCL low in-between

byte transfers, SCL is released when the IBDR is accessed in the required mode.

In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the

next byte of data. Setting RXAK means an 'end of data' signal from the master receiver, after which it must

be switched from transmitter mode to receiver mode by software. A dummy read then releases the SCL

line so that the master can generate a STOP signal.

13.7.1.7 Arbitration Lost

If several masters try to engage the bus simultaneously, only one master wins and the others lose

arbitration. The devices which lost arbitration are immediately switched to slave receive mode by the

hardware. Their data output to the SDA line is stopped, but SCL continues to be generated until the end of

the byte during which arbitration was lost. An interrupt occurs at the falling edge of the ninth clock of this

transfer with IBAL=1 and MS/SL=0. If one master attempts to start transmission while the bus is being

engaged by another master, the hardware will inhibit the transmission; switch the MS/SL bit from 1 to 0

without generating STOP condition; generate an interrupt to CPU and set the IBAL to indicate that the

attempt to engage the bus is failed. When considering these cases, the slave service routine should test the

IBAL ﬁrst and the software should clear the IBAL bit if it is set.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description

Clear

IBIF

Master

Mode

Arbitration

Tx/Rx

Lost

Last Byte

Transmitted

Clear IBAL

Last

Byte To Be Read

RXAK=0

IAAS=1

Data Transfer

Address Transfer

(Read)

End Of

Addr Cycle

(Master Rx)

2nd Last

Byte To Be Read

SRW=1

TX/RX

(Write)

ACK From

Receiver

Write Next

Byte To IBDR

Generate

Stop Signal

Set TX

Mode

Set TXAK =1

Read Data

From IBDR

And Store

Tx Next

Byte

Write Data

To IBDR

Switch To

Rx Mode

Set RX

Mode

Switch To

Rx Mode

Read Data

From IBDR

And Store

Dummy Read

From IBDR

Generate

Stop Signal

Dummy Read

From IBDR

Dummy Read

From IBDR

RTI

Figure 13-12. Flow-Chart of Typical IIC Interrupt Routine

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 14

Freescale’s Scalable Controller Area Network

(S12MSCANV3)

14.1 Introduction

Freescale’s scalable controller area network (S12MSCANV3) deﬁnition is based on the MSCAN12

deﬁnition, which is the speciﬁc implementation of the MSCAN concept targeted for the M68HC12

microcontroller family.

The module is a communication controller implementing the CAN 2.0A/B protocol as deﬁned in the

Bosch speciﬁcation dated September 1991. For users to fully understand the MSCAN speciﬁcation, it is

recommended that the Bosch speciﬁcation be read ﬁrst to familiarize the reader with the terms and

concepts contained within this document.

Though not exclusively intended for automotive applications, CAN protocol is designed to meet the

speciﬁc requirements of a vehicle serial data bus: real-time processing, reliable operation in the EMI

environment of a vehicle, cost-effectiveness, and required bandwidth.

MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simpliﬁed

application software.

14.1.1 Glossary

ACK: Acknowledge of CAN message

CAN: Controller Area Network

CRC: Cyclic Redundancy Code

EOF: End of Frame

FIFO: First-In-First-Out Memory

IFS: Inter-Frame Sequence

SOF: Start of Frame

CPU bus: CPU related read/write data bus

CAN bus: CAN protocol related serial bus

oscillator clock: Direct clock from external oscillator

bus clock: CPU bus realated clock

CAN clock: CAN protocol related clock

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

14.1.2 Block Diagram

MSCAN

CANCLK

Oscillator Clock

Tq Clk

MUX

Presc.

Bus Clock

RXCAN

TXCAN

Receive/

Transmit

Engine

Transmit Interrupt Req.

Receive Interrupt Req.

Errors Interrupt Req.

Wake-Up Interrupt Req.

Message

Filtering

and

Control

and

Status

Buffering

Conﬁguration

Registers

Wake-Up

Low Pass Filter

Figure 14-1. MSCAN Block Diagram

14.1.3 Features

The basic features of the MSCAN are as follows:

•

Implementation of the CAN protocol — Version 2.0A/B

— Standard and extended data frames

— Zero to eight bytes data length

— Programmable bit rate up to 1 Mbps

— Support for remote frames

•

Five receive buffers with FIFO storage scheme

Three transmit buffers with internal prioritization using a “local priority” concept

Flexible maskable identiﬁer ﬁlter supports two full-size (32-bit) extended identiﬁer ﬁlters, or four

16-bit ﬁlters, or eight 8-bit ﬁlters

•

Programmable wakeup functionality with integrated low-pass ﬁlter

Programmable loopback mode supports self-test operation

Programmable listen-only mode for monitoring of CAN bus

Programmable bus-off recovery functionality

Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states

(warning, error passive, bus-off)

•

Programmable MSCAN clock source either bus clock or oscillator clock

Internal timer for time-stamping of received and transmitted messages

1. Depending on the actual bit timing and the clock jitter of the PLL.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

•

Three low-power modes: sleep, power down, and MSCAN enable

Global initialization of conﬁguration registers

14.1.4 Modes of Operation

The following modes of operation are speciﬁc to the MSCAN. See Section 14.4, “Functional Description,”

for details.

•

Listen-Only Mode

MSCAN Sleep Mode

MSCAN Initialization Mode

MSCAN Power Down Mode

14.2 External Signal Description

The MSCAN uses two external pins:

14.2.1 RXCAN — CAN Receiver Input Pin

RXCAN is the MSCAN receiver input pin.

14.2.2 TXCAN — CAN Transmitter Output Pin

TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the

CAN bus:

0 = Dominant state

1 = Recessive state

14.2.3 CAN System

A typical CAN system with MSCAN is shown in Figure 14-2. Each CAN station is connected physically

to the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current

needed for the CAN bus and has current protection against defective CAN or defective stations.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

CAN node 2

CAN node n

CAN node 1

MCU

CAN Controller

(MSCAN)

TXCAN

RXCAN

Transceiver

CAN_H

CAN_L

CAN Bus

Figure 14-2. CAN System

14.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all registers accessible in the MSCAN.

14.3.1 Module Memory Map

Table 14-1 gives an overview on all registers and their individual bits in the MSCAN memory map. The

determined at the MCU level and can be found in the Memory block description chapter. The address offset

is deﬁned at the module level.

The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is

determined at the MCU level when the MCU is deﬁned. The register decode map is ﬁxed and begins at the

ﬁrst address of the module address offset.

Table 14-1 shows the individual registers associated with the MSCAN and their relative offset from the

base address. The detailed register descriptions follow in the order they appear in the register map.

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

Table 14-1. MSCAN Memory Map

Offset

Address

Access

0x0000

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

0x0008

0x0009

0x000A

0x000B

0x000C

0x000D

0x000E

0x000F

0x0010

0x0011

0x0012

0x0013

0x0014

0x0015

0x0016

0x0017

0x0018

0x0019

0x001A

0x001B

0x001C

0x001D

0x001E

0x001F

MSCAN Control Register 0 (CANCTL0)

R/W

MSCAN Control Register 1 (CANCTL1)

R/W

MSCAN Bus Timing Register 0 (CANBTR0)

R/W

MSCAN Bus Timing Register 1 (CANBTR1)

MSCAN Receiver Flag Register (CANRFLG)

R/W

MSCAN Receiver Interrupt Enable Register (CANRIER)

MSCAN T r ansmitter Flag Register (CANTFLG)

MSCAN T r ansmitter Interrupt Enable Register (CANTIER)

MSCAN T r ansmitter Message Abort Request Register (CAN TARQ)

MSCAN T r ansmitter Message Abort Acknowledge Register (CANTAAK)

MSCAN Transmit Buffer Selection Register (CANTBSEL)

MSCAN Identiﬁer Acceptance Control Register (CANIDAC)

RESERVED

R/W

MSCAN Miscellaneous Register (CANMISC)

R/W

MSCAN Receive Error Counter (CANRXERR)

MSCAN Transmit Error Counter (CANTXERR)

MSCAN Identiﬁer Acceptance Register 0(CANIDAR0)

MSCAN Identiﬁer Acceptance Register 1(CANIDAR1)

MSCAN Identiﬁer Acceptance Register 2 (CANIDAR2)

MSCAN Identiﬁer Acceptance Register 3 (CANIDAR3)

MSCAN Identiﬁer Mask Register 0 (CANIDMR0)

MSCAN Identiﬁer Mask Register 1 (CANIDMR1)

MSCAN Identiﬁer Mask Register 2 (CANIDMR2)

MSCAN Identiﬁer Mask Register 3 (CANIDMR3)

MSCAN Identiﬁer Acceptance Register 4 (CANIDAR4)

MSCAN Identiﬁer Acceptance Register 5 (CANIDAR5)

MSCAN Identiﬁer Acceptance Register 6 (CANIDAR6)

MSCAN Identiﬁer Acceptance Register 7 (CANIDAR7)

MSCAN Identiﬁer Mask Register 4 (CANIDMR4)

MSCAN Identiﬁer Mask Register 5 (CANIDMR5)

MSCAN Identiﬁer Mask Register 6 (CANIDMR6)

MSCAN Identiﬁer Mask Register 7 (CANIDMR7)

Foreground Receive Buffer (CANRXFG)

R/W

0x0020

-0x002F

0x0030

Foreground Transmit Buffer (CANTXFG)

R /W

-0x003F

Refer to detailed register description for write access restrictions on per bit basis.

Reserved bits and unused bits within the TX- and RX-buffers (CANTXFG, CANRXFG) will be read

as “x”, because of RAM-based implementation.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

14.3.2 Register Descriptions

This section describes in detail all the registers and register bits in the MSCAN module. Each description

includes a standard register diagram with an associated ﬁgure number. Details of register bit and ﬁeld

function follow the register diagrams, in bit order. All bits of all registers in this module are completely

synchronous to internal clocks during a register read.

14.3.2.1 MSCAN Control Register 0 (CANCTL0)

The CANCTL0 register provides various control bits of the MSCAN module as described below.

Module Base + 0x0000

RXACT

SYNCH

RXFRM

CSWAI

TIME

WUPE

SLPRQ

INITRQ

Reset:

= Unimplemented

Figure 14-3. MSCAN Control Register 0 (CANCTL0)

NOTE

The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the

reset state when the initialization mode is active (INITRQ = 1 and

INITAK = 1). This register is writable again as soon as the initialization

mode is exited (INITRQ = 0 and INITAK = 0).

Read: Anytime

Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM

(which is set by the module only), and INITRQ (which is also writable in initialization mode).

Table 14-2. CANCTL0 Register Field Descriptions

Field

Description

Received Frame Flag — This bit is read and clear only. It is set when a receiver has received a valid message

correctly, independently of the ﬁlter conﬁguration. After it is set, it remains set until cleared by software or reset.

Clearing is done by writing a 1. Writing a 0 is ignored. This bit is not valid in loopback mode.

0 No valid message was received since last clearing this ﬂag

RXFRM

1 A valid message was received since last clearing of this ﬂag

Receiver Active Status — This read-only ﬂag indicates the MSCAN is receiving a message. The ﬂag is

RXACT

controlled by the receiver front end. This bit is not valid in loopback mode.

0 MSCAN is transmitting or idle

1 MSCAN is receiving a message (including when arbitration is lost)

CAN Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling all

the clocks at the CPU bus interface to the MSCAN module.

CSWAI

0 The module is not affected during wait mode

1 The module ceases to be clocked during wait mode

Synchronized Status — This read-only ﬂag indicates whether the MSCAN is synchronized to the CAN bus and

able to participate in the communication process. It is set and cleared by the MSCAN.

0 MSCAN is not synchronized to the CAN bus

SYNCH

1 MSCAN is synchronized to the CAN bus

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

Table 14-2. CANCTL0 Register Field Descriptions (continued)

Field

Description

Timer Enable — This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate.

If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the

active TX/RX buffer. As soon as a message is acknowledged on the CAN bus, the time stamp will be written to

the highest bytes (0x000E, 0x000F) in the appropriate buffer (see Section 14.3.3, “Programmer’s Model of

Message Storage”). The internal timer is reset (all bits set to 0) when disabled. This bit is held low in initialization

mode.

TIME

0 Disable internal MSCAN timer

1 Enable internal MSCAN timer

Wake-Up Enable — This conﬁguration bit allows the MSCAN to restart from sleep mode when trafﬁc on CAN is

detected (see Section 14.4.6.4, “MSCAN Sleep Mode”).

WUPE

0 Wake-up disabled — The MSCAN ignores trafﬁc on CAN

1 Wake-up enabled — The MSCAN is able to restart

Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving

mode (see Section 14.4.6.4, “MSCAN Sleep Mode ”). The sleep mode request is serviced when the CAN bus is

idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry

to sleep mode by setting SLPAK = 1 (see Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). Sleep

mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN

detects activity on the CAN bus and clears SLPRQ itself.

SLPRQ

0 Running — The MSCAN functions normally

1 Sleep mode request — The MSCAN enters sleep mode when CAN bus idle

Initialization Mode Request — When this bit is set by the CPU, the MSCAN skips to initialization mode (see

Section 14.4.6.5, “MSCAN Initialization Mode ”). Any ongoing transmission or reception is aborted and

synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1

(Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1)”).

6,7

INITRQ

The following registers enter their hard reset state and restore their default values: CANCTL0 , CANRFLG ,

CANRIER , CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL.

The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be

written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the

error counters are not affected by initialization mode.

When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the

MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN

is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits.

Writing to otherbits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after

initialization mode is exited, which is INITRQ = 0 and INITAK = 0.

0 Normal operation

1 MSCAN in initialization mode

The MSCAN must be in normal mode for this bit to become set.

See the Bosch CAN 2.0A/B speciﬁcation for a detailed deﬁnition of transmitter and receiver states.

In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when

the CPU enters wait (CSWAI = 1) or stop mode (see Section 14.4.6.2, “Operation in Wait Mode” and Section 14.4.6.3,

“Operation in Stop Mode ”).

The CPU has to make sure that the WUPE register and the WUPIE wake-up interrupt enable register (see Section 14.3.2.6,

“MSCAN Receiver Interrupt Enable Register (CANRIER)) is enabled, if the recovery mechanism from stop or wait is required.

The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1).

The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1).

In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when

the initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode

(SLPRQ = 1 and SLPAK = 1) before requesting initialization mode.

Not including WUPE, INITRQ, and SLPRQ.

TSTAT1 and TSTAT0 are not affected by initialization mode.

RSTAT1 and RSTAT0 are not affected by initialization mode.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

14.3.2.2 MSCAN Control Register 1 (CANCTL1)

The CANCTL1 register provides various control bits and handshake status information of the MSCAN

module as described below.

Module Base 0x0001

SLPAK

INITAK

CANE

CLKSRC

LOOPB

LISTEN

BORM

WUPM

Reset:

= Unimplemented

Figure 14-4. MSCAN Control Register 1 (CANCTL1)

Read: Anytime

Write: Anytime when INITRQ = 1 and INITAK = 1, except CANE which is write once in normal and

anytime in special system operation modes when the MSCAN is in initialization mode (INITRQ = 1 and

INITAK = 1).

Table 14-3. CANCTL1 Register Field Descriptions

Field

Description

MSCAN Enable

CANE

0 MSCAN module is disabled

1 MSCAN module is enabled

MSCAN Clock Source — This bit deﬁnes the clock source for the MSCAN module (only for systems with a clock

generation module; Section 14.4.3.2, “Clock System,” and Section Figure 14-42., “MSCAN Clocking Scheme,”).

0 MSCAN clock source is the oscillator clock

CLKSRC

1 MSCAN clock source is the bus clock

Loopback Self Test Mode — When this bit is set, the MSCAN performs an internal loopback which can be used

for self test operation. The bit stream output of the transmitter is fed back to the receiver internally. The RXCAN

input pin is ignored and the TXCAN output goes to the recessive state (logic 1). The MSCAN behaves as it does

normally when transmitting and treats its own transmitted message as a message received from a remote node.

In this state, the MSCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge ﬁeld to ensure

proper reception of its own message. Both transmit and receive interrupts are generated.

0 Loopback self test disabled

LOOPB

1 Loopback self test enabled

Listen Only Mode — This bit conﬁgures the MSCAN as a CAN bus monitor. When LISTEN is set, all valid CAN

messages with matching ID are received, but no acknowledgement or error frames are sent out (see

Section 14.4.5.4, “Listen-Only Mode”). In addition, the error counters are frozen. Listen only mode supports

applications which require “hot plugging” or throughput analysis. The MSCAN is unable to transmit any

messages when listen only mode is active.

LISTEN

0 Normal operation

1 Listen only mode activated

Bus-Off Recovery Mode — This bits conﬁgures the bus-off state recovery mode of the MSCAN. Refer to

Section 14.5.2, “Bus-Off Recovery,” for details.

BORM

0 Automatic bus-off recovery (see Bosch CAN 2.0A/B protocol speciﬁcation)

1 Bus-off recovery upon user request

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

Table 14-3. CANCTL1 Register Field Descriptions (continued)

Field

Description

Wake-Up Mode — If WUPE in CANCTL0 is enabled, this bit deﬁnes whether the integrated low-pass ﬁlter is

applied to protect the MSCAN from spurious wake-up (see Section 14.4.6.4, “MSCAN Sleep Mode”).

0 MSCAN wakes up the CPU after any recessive to dominant edge on the CAN bus

WUPM

1 MSCAN wakes up the CPU only in case of a dominant pulse on the CAN bus that has a length of T

wup

Sleep Mode Acknowledge — This ﬂag indicates whether the MSCAN module has entered sleep mode (see

Section 14.4.6.4, “MSCAN Sleep Mode”). It is used as a handshake ﬂag for the SLPRQ sleep mode request.

Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will

clear the ﬂag if it detects activity on the CAN bus while in sleep mode.

SLPAK

0 Running — The MSCAN operates normally

1 Sleep mode active — The MSCAN has entered sleep mode

Initialization Mode Acknowledge — This ﬂag indicates whether the MSCAN module is in initialization mode

(see Section 14.4.6.5, “MSCAN Initialization Mode”). It is used as a handshake ﬂag for the INITRQ initialization

mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1,

CANBTR0, CANBTR1, CANIDAC, CANIDAR0–CANIDAR7, and CANIDMR0–CANIDMR7 can be written only by

the CPU when the MSCAN is in initialization mode.

INITAK

0 Running — The MSCAN operates normally

1 Initialization mode active — The MSCAN has entered initialization mode

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

14.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0)

The CANBTR0 register conﬁgures various CAN bus timing parameters of the MSCAN module.

Module Base + 0x0002

SJW1

SJW0

BRP5

BRP4

BRP3

BRP2

BRP1

BRP0

Reset:

Figure 14-5. MSCAN Bus Timing Register 0 (CANBTR0)

Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

Table 14-4. CANBTR0 Register Field Descriptions

Field

Description

7:6

SJW[1:0]

Synchronization Jump Width — The synchronization jump width deﬁnes the maximum number of time quanta

(Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the

CAN bus (see Table 14-5).

5:0

Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing

BRP[5:0]

(see Table 14-6).

Table 14-5. Synchronization Jump Width

SJW1

SJW0

Synchronization Jump Width

1 Tq clock cycle

2 Tq clock cycles

3 Tq clock cycles

4 Tq clock cycles

Table 14-6. Baud Rate Prescaler

BRP5

BRP4

BRP3

BRP2

BRP1

BRP0

Prescaler value (P)

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

14.3.2.4 MSCAN Bus Timing Register 1 (CANBTR1)

The CANBTR1 register conﬁgures various CAN bus timing parameters of the MSCAN module.

Module Base + 0x0003

SAMP

TSEG22

TSEG21

TSEG20

TSEG13

TSEG12

TSEG11

TSEG10

Reset:

Figure 14-6. MSCAN Bus Timing Register 1 (CANBTR1)

Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

Table 14-7. CANBTR1 Register Field Descriptions

Field

Description

Sampling — This bit determines the number of CAN bus samples taken per bit time.

SAMP

0 One sample per bit.

1 Three samples per bit .

If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If

SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit

rates, it is recommended that only one sample is taken per bit time (SAMP = 0).

6:4

Time Segment 2 — Time segments within the bit time ﬁx the number of clock cycles per bit time and the location

TSEG2[2:0] of the sample point (see Figure 14-43). Time segment 2 (TSEG2) values are programmable as shown in

Table 14-8.

3:0

Time Segment 1 — Time segments within the bit time ﬁx the number of clock cycles per bit time and the location

TSEG1[3:0] of the sample point (see Figure 14-43). Time segment 1 (TSEG1) values are programmable as shown in

Table 14-9.

In this case, PHASE_SEG1 must be at least 2 time quanta (Tq).

Table 14-8. Time Segment 2 Values

TSEG22

TSEG21

TSEG20

Time Segment 2

1 Tq clock cycle

2 Tq clock cycles

7 Tq clock cycles

8 Tq clock cycles

This setting is not valid. Please refer to Table 14-36 for valid settings.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Table 14-9. Time Segment 1 Values

TSEG13

TSEG12

TSEG11

TSEG10

Time segment 1

1 Tq clock cycle

2 Tq clock cycles

3 Tq clock cycles

4 Tq clock cycles

15 Tq clock cycles

16 Tq clock cycles

This setting is not valid. Please refer to Table 14-36 for valid settings.

The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time

quanta (Tq) clock cycles per bit (as shown in Table 14-8 and Table 14-9).

Eqn. 14-1

(Prescaler value)

-----------------------------------------------------

Bit Time=

• (1 + TimeSegment1 + TimeSegment2)

CANCLK

14.3.2.5 MSCAN Receiver Flag Register (CANRFLG)

A ﬂag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition

which caused the setting is no longer valid. Every ﬂag has an associated interrupt enable bit in the

CANRIER register.

Module Base + 0x0004

RSTAT1

RSTAT0

TSTAT1

TSTAT0

WUPIF

CSCIF

OVRIF

RXF

Reset:

= Unimplemented

Figure 14-7. MSCAN Receiver Flag Register (CANRFLG)

NOTE

The CANRFLG register is held in the reset state when the initialization

mode is active (INITRQ = 1 and INITAK = 1). This register is writable again

as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0).

Read: Anytime

Write: Anytime when out of initialization mode, except RSTAT[1:0] and TSTAT[1:0] ﬂags which are

read-only; write of 1 clears ﬂag; write of 0 is ignored.

1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode.

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Table 14-10. CANRFLG Register Field Descriptions

Field

Description

Wake-Up Interrupt Flag — If the MSCAN detects CAN bus activity while in sleep mode (see Section 14.4.6.4,

“MSCAN Sleep Mode,”) and WUPE = 1 in CANTCTL0 (see Section 14.3.2.1, “MSCAN Control Register 0

(CANCTL0)”), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this ﬂag is set.

WUPIF

No wake-up activity observed while in sleep mode

MSCAN detected activity on the CAN bus and requested wake-up

CAN Status Change Interrupt Flag — This ﬂag is set when the MSCAN changes its current CAN bus status

due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional

4-bit (RS T A T [1:0], TS TAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the

system on the actual CAN bus status (see Section 14.3.2.6, “MSCAN Receiver Interrupt Enable Register

(CANRIER)”). If not masked, an error interrupt is pending while this ﬂag is set. CSCIF provides a blocking

interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no CAN

status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is asserted,

which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status until the

current CSCIF interrupt is cleared again.

CSCIF

No change in CAN bus status occurred since last interrupt

MSCAN changed current CAN bus status

5:4

Receiver Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. As

RSTAT[1:0] soon as the status change interrupt ﬂag (CSCIF) is set, these bits indicate the appropriate receiver related CAN

bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is:

RxOK: 0 ≤ receive error counter ≤ 96

RxWRN: 96 < receive error counter ≤ 127

RxERR: 127 < receive error counter

Bus-off : transmit error counter > 255

3:2

Transmitter Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN.

TSTAT[1:0] As soon as the status change interrupt ﬂag (CSCIF) is set, these bits indicate the appropriate transmitter related

CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is:

TxOK: 0 ≤ transmit error counter ≤ 96

TxWRN: 96 < transmit error counter ≤ 127

TxERR: 127 < transmit error counter ≤ 255

Bus-Off: transmit error counter > 255

Overrun Interrupt Flag — This ﬂag is set when a data overrun condition occurs. If not masked, an error interrupt

OVRIF

is pending while this ﬂag is set.

No data overrun condition

A data overrun detected

RXF

Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO. This

ﬂag indicates whether the shifted buffer is loaded with a correctly received message (matching identiﬁer,

matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message

from the RxFG buffer in the receiver FIFO, the RXF ﬂag must be cleared to release the buffer. A set RXF ﬂag

prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt

is pending while this ﬂag is set.

No new message available within the RxFG

The receiver FIFO is not empty. A new message is available in the RxFG

Redundant Information for the most critical CAN bus status which is “bus-off”. This only occurs if the Tx error counter exceeds

a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state

skips to RxOK too. Refer also to TSTAT[1:0] coding in this register.

To ensure data integrity, do not read the receive buffer registers while the RXF ﬂag is cleared. For MCUs with dual CPUs,

reading the receive buffer registers while the RXF ﬂag is cleared may result in a CPU fault condition.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

14.3.2.6 MSCAN Receiver Interrupt Enable Register (CANRIER)

This register contains the interrupt enable bits for the interrupt ﬂags described in the CANRFLG register.

Module Base + 0x0005

WUPIE

CSCIE

RSTATE1

RSTATE0

TSTATE1

TSTATE0

OVRIE

RXFIE

Reset:

Figure 14-8. MSCAN Receiver Interrupt Enable Register (CANRIER)

NOTE

The CANRIER register is held in the reset state when the initialization mode

is active (INITRQ=1 and INITAK=1). This register is writable when not in

initialization mode (INITRQ=0 and INITAK=0).

The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization

mode.

Read: Anytime

Write: Anytime when not in initialization mode

Table 14-11. CANRIER Register Field Descriptions

Field

Description

Wake-Up Interrupt Enable

WUPIE

No interrupt request is generated from this event.

A wake-up event causes a Wake-Up interrupt request.

CAN Status Change Interrupt Enable

CSCIE

No interrupt request is generated from this event.

A CAN Status Change event causes an error interrupt request.

5:4

Receiver Status Change Enable — These RSTAT enable bits control the sensitivity level in which receiver state

RSTATE[1:0] changes are causing CSCIF interrupts. Independent of the chosen sensitivity level the RSTAT ﬂags continue to

indicate the actual receiver state and are only updated if no CSCIF interrupt is pending.

00 Do not generate any CSCIF interrupt caused by receiver state changes.

01 Generate CSCIF interrupt only if the receiver enters or leaves “bus-off” state. Discard other receiver state

changes for generating CSCIF interrupt.

10 Generate CSCIF interrupt only if the receiver enters or leaves “RxErr” or “bus-off” state. Discard other

receiver state changes for generating CSCIF interrupt.

11 Generate CSCIF interrupt on all state changes.

3:2

Transmitter Status Change Enable — These TSTAT enable bits control the sensitivity level in which transmitter

TSTATE[1:0] state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level, the TSTAT ﬂags

continue to indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending.

00 Do not generate any CSCIF interrupt caused by transmitter state changes.

01 Generate CSCIF interrupt only if the transmitter enters or leaves “bus-off” state. Discard other transmitter

state changes for generating CSCIF interrupt.

10 Generate CSCIF interrupt only if the transmitter enters or leaves “TxErr” or “bus-off” state. Discard other

transmitter state changes for generating CSCIF interrupt.

11 Generate CSCIF interrupt on all state changes.

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

Table 14-11. CANRIER Register Field Descriptions (continued)

Field

Description

Overrun Interrupt Enable

OVRIE

No interrupt request is generated from this event.

An overrun event causes an error interrupt request.

Receiver Full Interrupt Enable

RXFIE

No interrupt request is generated from this event.

A receive buffer full (successful message reception) event causes a receiver interrupt request.

WUPIE and WUPE (see Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0)”) must both be enabled if the recovery

mechanism from stop or wait is required.

Bus-off state is deﬁned by the CAN standard (see Bosch CAN 2.0A/B protocol speciﬁcation: for only transmitters. Because the

only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK,

the coding of the RXSTAT[1:0] ﬂags deﬁne an additional bus-off state for the receiver (see Section 14.3.2.5, “MSCAN Receiver

Flag Register (CANRFLG)”).

14.3.2.7 MSCAN Transmitter Flag Register (CANTFLG)

The transmit buffer empty ﬂags each have an associated interrupt enable bit in the CANTIER register.

Module Base + 0x0006

TXE2

TXE1

TXE0

Reset:

= Unimplemented

Figure 14-9. MSCAN Transmitter Flag Register (CANTFLG)

NOTE

The CANTFLG register is held in the reset state when the initialization

mode is active (INITRQ = 1 and INITAK = 1). This register is writable when

not in initialization mode (INITRQ = 0 and INITAK = 0).

Read: Anytime

Write: Anytime for TXEx ﬂags when not in initialization mode; write of 1 clears ﬂag, write of 0 is ignored

MC9S12XDP512 Data Sheet, Rev. 2.11

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Table 14-12. CANTFLG Register Field Descriptions

Field

Description

2:0

TXE[2:0]

Transmitter Buffer Empty — This ﬂag indicates that the associated transmit message buffer is empty, and thus

not scheduled for transmission. The CPU must clear the ﬂag after a message is set up in the transmit buffer and

is due for transmission. The MSCAN sets the ﬂag after the message is sent successfully. The ﬂag is also set by

the MSCAN when the transmission request is successfully aborted due to a pending abort request (see

Section 14.3.2.9, “MSCAN Transmitter Message Abort Request Register (CAN T A RQ)”). If not masked, a

transmit interrupt is pending while this ﬂag is set.

Clearing a TXEx ﬂag also clears the corresponding AB T A Kx (see Section 14.3.2.10, “MSCAN T r ansmitter

Message Abort Acknowledge Register (CAN T A AK)”). When a TXEx ﬂag is set, the corresponding ABTRQx bit

is cleared (see Section 14.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”).

When listen-mode is active (see Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1)”) the TXEx ﬂags

cannot be cleared and no transmission is started.

Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared

(TXEx = 0) and the buffer is scheduled for transmission.

0 The associated message buffer is full (loaded with a message due for transmission)

1 The associated message buffer is empty (not scheduled)

14.3.2.8 MSCAN Transmitter Interrupt Enable Register (CANTIER)

This register contains the interrupt enable bits for the transmit buffer empty interrupt ﬂags.

Module Base + 0x0007

TXEIE2

TXEIE1

TXEIE0

Reset:

= Unimplemented

Figure 14-10. MSCAN Transmitter Interrupt Enable Register (CANTIER)

NOTE

The CANTIER register is held in the reset state when the initialization mode

is active (INITRQ = 1 and INITAK = 1). This register is writable when not

in initialization mode (INITRQ = 0 and INITAK = 0).

Read: Anytime

Write: Anytime when not in initialization mode

Table 14-13. CANTIER Register Field Descriptions

Field

Description

2:0

Transmitter Empty Interrupt Enable

TXEIE[2:0] 0 No interrupt request is generated from this event.

1 A transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt

request.

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14.3.2.9 MSCAN Transmitter Message Abort Request Register (CANTARQ)

The CANTARQ register allows abort request of queued messages as described below.

Module Base + 0x0008

ABTRQ2

ABTRQ1

ABTRQ0

Reset:

= Unimplemented

Figure 14-11. MSCAN Transmitter Message Abort Request Register (CANTARQ)

NOTE

The CANTARQ register is held in the reset state when the initialization

mode is active (INITRQ = 1 and INITAK = 1). This register is writable when

not in initialization mode (INITRQ = 0 and INITAK = 0).

Read: Anytime

Write: Anytime when not in initialization mode

Table 14-14. CANTARQ Register Field Descriptions

Field

Description

Abort Request — The CPU sets the ABTRQx bit to request that a scheduled message buffer (TXEx = 0) be

2:0

ABTRQ[2:0] aborted. The MSCAN grants the request if the message has not already started transmission, or if the

transmission is not successful (lost arbitration or error). When a message is aborted, the associated TXE (see

Section 14.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and abort acknowledge ﬂags (ABTAK, see

Section 14.3.2.10, “MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)”) are set and a

transmit interrupt occurs if enabled. The CPU cannot reset ABTRQx. ABTRQx is reset whenever the associated

TXE ﬂag is set.

0 No abort request

1 Abort request pending

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

14.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)

The CANTAAK register indicates the successful abort of a queued message, if requested by the

appropriate bits in the CANTARQ register.

Module Base + 0x0009

ABTAK2

ABTAK1

ABTAK0

Reset:

= Unimplemented

Figure 14-12. MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)

NOTE

The CANTAAK register is held in the reset state when the initialization

mode is active (INITRQ = 1 and INITAK = 1).

Read: Anytime

Write: Unimplemented for ABTAKx ﬂags

Table 14-15. CANTAAK Register Field Descriptions

Field

Description

Abort Acknowledge — This ﬂag acknowledges that a message was aborted due to a pending abort request

2:0

ABTAK[2:0] from the CPU. After a particular message buffer is ﬂagged empty, this ﬂag can be used by the application

software to identify whether the message was aborted successfully or was sent anyway. The ABTAKx ﬂag is

cleared whenever the corresponding TXE ﬂag is cleared.

0 The message was not aborted.

1 The message was aborted.

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14.3.2.11 MSCAN Transmit Buffer Selection Register (CANTBSEL)

The CANTBSEL register allows the selection of the actual transmit message buffer, which then will be

accessible in the CANTXFG register space.

Module Base + 0x000A

TX2

TX1

TX0

Reset:

= Unimplemented

Figure 14-13. MSCAN Transmit Buffer Selection Register (CANTBSEL)

NOTE

The CANTBSEL register is held in the reset state when the initialization

mode is active (INITRQ = 1 and INITAK=1). This register is writable when

not in initialization mode (INITRQ = 0 and INITAK = 0).

Read: Find the lowest ordered bit set to 1, all other bits will be read as 0

Write: Anytime when not in initialization mode

Table 14-16. CANTBSEL Register Field Descriptions

Field

Description

2:0

TX[2:0]

Transmit Buffer Select — The lowest numbered bit places the respective transmit buffer in the CANTXFG

buffer TX1). Read and write accesses to the selected transmit buffer will be blocked, if the corresponding TXEx

bit is cleared and the buffer is scheduled for transmission (see Section 14.3.2.7, “MSCAN Transmitter Flag

0 The associated message buffer is deselected

1 The associated message buffer is selected, if lowest numbered bit

The following gives a short programming example of the usage of the CANTBSEL register:

To get the next available transmit buffer, application software must read the CANTFLG register and write

this value back into the CANTBSEL register. In this example Tx buffers TX1 and TX2 are available. The

value read from CANTFLG is therefore 0b0000_0110. When writing this value back to CANTBSEL, the

Tx buffer TX1 is selected in the CANTXFG because the lowest numbered bit set to 1 is at bit position 1.

Reading back this value out of CANTBSEL results in 0b0000_0010, because only the lowest numbered

bit position set to 1 is presented. This mechanism eases the application software the selection of the next

available Tx buffer.

•

LDD CANTFLG; value read is 0b0000_0110

STD CANTBSEL; value written is 0b0000_0110

LDD CANTBSEL; value read is 0b0000_0010

If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG registers.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

14.3.2.12 MSCAN Identiﬁer Acceptance Control Register (CANIDAC)

The CANIDAC register is used for identiﬁer acceptance control as described below.

Module Base + 0x000B

IDHIT2

IDHIT1

IDHIT0

IDAM1

IDAM0

Reset:

= Unimplemented

Figure 14-14. MSCAN Identiﬁer Acceptance Control Register (CANIDAC)

Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are

read-only

Table 14-17. CANIDAC Register Field Descriptions

Field

Description

5:4

Identiﬁer Acceptance Mode — The CPU sets these ﬂags to deﬁne the identiﬁer acceptance ﬁlter organization

IDAM[1:0] (see Section 14.4.3, “Identiﬁer Acceptance Filter”). Table 14-18 summarizes the different settings. In ﬁlter closed

mode, no message is accepted such that the f oreground buffer is never reloaded.

2:0

Identiﬁer Acceptance Hit Indicator — The MSCAN sets these ﬂags to indicate an identiﬁer acceptance hit (see

IDHIT[2:0] Section 14.4.3, “Identiﬁer Acceptance Filter”). Table 14-19 summarizes the different settings.

Table 14-18. Identiﬁer Acceptance Mode Settings

IDAM1

IDAM0

Identiﬁer Acceptance Mode

Two 32-bit acceptance ﬁlters

Four 16-bit acceptance ﬁlters

Eight 8-bit acceptance ﬁlters

Filter closed

Table 14-19. Identiﬁer Acceptance Hit Indication

IDHIT2

IDHIT1

IDHIT0

Identiﬁer Acceptance Hit

Filter 0 hit

Filter 1 hit

Filter 2 hit

Filter 3 hit

Filter 4 hit

Filter 5 hit

Filter 6 hit

Filter 7 hit

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a

message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.

14.3.2.13 MSCAN Reserved Register

This register is reserved for factory testing of the MSCAN module and is not available in normal system

operation modes.

Module Base + 0x000C

Reset:

= Unimplemented

Figure 14-15. MSCAN Reserved Register

Read: Always read 0x0000 in normal system operation modes

Write: Unimplemented in normal system operation modes

NOTE

Writing to this register when in special modes can alter the MSCAN

functionality.

14.3.2.14 MSCAN Miscellaneous Register (CANMISC)

This register provides additional features.

Module Base + 0x000D

BOHOLD

Reset:

= Unimplemented

Figure 14-16. MSCAN Miscellaneous Register (CANMISC)

Read: Anytime

Write: Anytime; write of ‘1’ clears ﬂag; write of ‘0’ ignored

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Table 14-20. CANMISC Register Field Descriptions

Field

Description

Bus-off State Hold Until User Request — If BORM is set in Section 14.3.2.2, “MSCAN Control Register 1

BOHOLD (CANCTL1), this bit indicates whether the module has entered the bus-off state. Clearing this bit requests the

recovery from bus-off. Refer to Section 14.5.2, “Bus-Off Recovery,” for details.

0 Module is not bus-off or recovery has been requested by user in bus-off state

1 Module is bus-off and holds this state until user request

14.3.2.15 MSCAN Receive Error Counter (CANRXERR)

This register reﬂects the status of the MSCAN receive error counter.

Module Base + 0x000E

RXERR7

RXERR6

RXERR5

RXERR4

RXERR3

RXERR2

RXERR1

RXERR0

Reset:

= Unimplemented

Figure 14-17. MSCAN Receive Error Counter (CANRXERR)

Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and

INITAK = 1)

Write: Unimplemented

NOTE

Reading this register when in any other mode other than sleep or

initialization mode may return an incorrect value. For MCUs with dual

CPUs, this may result in a CPU fault condition.

Writing to this register when in special modes can alter the MSCAN

functionality.

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

14.3.2.16 MSCAN Transmit Error Counter (CANTXERR)

This register reﬂects the status of the MSCAN transmit error counter.

Module Base + 0x000F

TXERR7

TXERR6

TXERR5

TXERR4

TXERR3

TXERR2

TXERR1

TXERR0

Reset:

= Unimplemented

Figure 14-18. MSCAN Transmit Error Counter (CANTXERR)

Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and

INITAK = 1)

Write: Unimplemented

NOTE

Reading this register when in any other mode other than sleep or

initialization mode, may return an incorrect value. For MCUs with dual

CPUs, this may result in a CPU fault condition.

Writing to this register when in special modes can alter the MSCAN

functionality.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

14.3.2.17 MSCAN Identiﬁer Acceptance Registers (CANIDAR0-7)

On reception, each message is written into the background receive buffer. The CPU is only signalled to

read the message if it passes the criteria in the identiﬁer acceptance and identiﬁer mask registers

(accepted); otherwise, the message is overwritten by the next message (dropped).

The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see Section 14.3.3.1,

“Identiﬁer Registers (IDR0–IDR3)”) of incoming messages in a bit by bit manner (see Section 14.4.3,

“Identiﬁer Acceptance Filter”).

For extended identiﬁers, all four acceptance and mask registers are applied. For standard identiﬁers, only

the ﬁrst two (CANIDAR0/1, CANIDMR0/1) are applied.

Module Base + 0x0010 (CANIDAR0)

0x0011 (CANIDAR1)

0x0012 (CANIDAR2)

0x0013 (CANIDAR3)

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

Reset

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

Reset

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

Reset

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

Reset

Figure 14-19. MSCAN Identiﬁer Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3

Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

Table 14-21. CANIDAR0–CANIDAR3 Register Field Descriptions

Field

Description

7:0

AC[7:0]

Acceptance Code Bits — AC[7:0] comprise a user-deﬁned sequence of bits with which the corresponding bits

of the related identiﬁer register (IDRn) of the receive message buffer are compared. The result of this comparison

is then masked with the corresponding identiﬁer mask register.

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Module Base + 0x0018 (CANIDAR4)

0x0019 (CANIDAR5)

0x001A (CANIDAR6)

0x001B (CANIDAR7)

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

Reset

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

Reset

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

Reset

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

Reset

Figure 14-20. MSCAN Identiﬁer Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7

Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

Table 14-22. CANIDAR4–CANIDAR7 Register Field Descriptions

Field

Description

7:0

AC[7:0]

Acceptance Code Bits — AC[7:0] comprise a user-deﬁned sequence of bits with which the corresponding bits

of the related identiﬁer register (IDRn) of the receive message buffer are compared. The result of this comparison

is then masked with the corresponding identiﬁer mask register.

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

14.3.2.18 MSCAN Identiﬁer Mask Registers (CANIDMR0–CANIDMR7)

The identiﬁer mask register speciﬁes which of the corresponding bits in the identiﬁer acceptance register

are relevant for acceptance ﬁltering. To receive standard identiﬁers in 32 bit ﬁlter mode, it is required to

program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.”

To receive standard identiﬁers in 16 bit ﬁlter mode, it is required to program the last three bits (AM[2:0])

in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.”

Module Base + 0x0014 (CANIDMR0)

0x0015 (CANIDMR1)

0x0016 (CANIDMR2)

0x0017 (CANIDMR3)

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

Reset

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

Reset

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

Reset

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

Reset

Figure 14-21. MSCAN Identiﬁer Mask Registers (First Bank) — CANIDMR0–CANIDMR3

Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

Table 14-23. CANIDMR0–CANIDMR3 Register Field Descriptions

Field

Description

7:0

AM[7:0]

Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in

the identiﬁer acceptance register must be the same as its identiﬁer bit before a match is detected. The message

is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identiﬁer

acceptance register does not affect whether or not the message is accepted.

0 Match corresponding acceptance code register and identiﬁer bits

1 Ignore corresponding acceptance code register bit

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Module Base + 0x001C (CANIDMR4)

0x001D (CANIDMR5)

0x001E (CANIDMR6)

0x001F (CANIDMR7)

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

Reset

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

Reset

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

Reset

AM7

AM6

AM5

AM4

AM3

AM2

AM1

AM0

Reset

Figure 14-22. MSCAN Identiﬁer Mask Registers (Second Bank) — CANIDMR4–CANIDMR7

Read: Anytime

Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)

Table 14-24. CANIDMR4–CANIDMR7 Register Field Descriptions

Field

Description

7:0

AM[7:0]

Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in

the identiﬁer acceptance register must be the same as its identiﬁer bit before a match is detected. The message

is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identiﬁer

acceptance register does not affect whether or not the message is accepted.

0 Match corresponding acceptance code register and identiﬁer bits

1 Ignore corresponding acceptance code register bit

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

14.3.3 Programmer’s Model of Message Storage

The following section details the organization of the receive and transmit message buffers and the

associated control registers.

To simplify the programmer interface, the receive and transmit message buffers have the same outline.

Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure.

An additional transmit buffer priority register (TBPR) is deﬁned for the transmit buffers. Within the last

two bytes of this memory map, the MSCAN stores a special 16-bit time stamp, which is sampled from an

internal timer after successful transmission or reception of a message. This feature is only available for

transmit and receiver buffers, if the TIME bit is set (see Section 14.3.2.1, “MSCAN Control Register 0

(CANCTL0)”).

The time stamp register is written by the MSCAN. The CPU can only read these registers.

Table 14-25. Message Buffer Organization

Offset

Address

Access

0x00X0

0x00X1

0x00X2

0x00X3

0x00X4

0x00X5

0x00X6

0x00X7

0x00X8

0x00X9

0x00XA

0x00XB

0x00XC

0x00XD

0x00XE

0x00XF

Identiﬁer Register 0

Identiﬁer Register 1

Identiﬁer Register 2

Identiﬁer Register 3

Data Segment Register 0

Data Segment Register 1

Data Segment Register 2

Data Segment Register 3

Data Segment Register 4

Data Segment Register 5

Data Segment Register 6

Data Segment Register 7

Data Length Register

Transmit Buffer Priority Register

Time Stamp Register (High Byte)

Time Stamp Register (Low Byte)

Not applicable for receive buffers

Read-only for CPU

Figure 14-23 shows the common 13-byte data structure of receive and transmit buffers for extended

identiﬁers. The mapping of standard identiﬁers into the IDR registers is shown in Figure 14-24.

All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation .

All reserved or unused bits of the receive and transmit buffers always read ‘x’.

1. Exception: The transmit priority registers are 0 out of reset.

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Name

Bit 7

Bit0

0x00X0

IDR0

ID28

ID27

ID26

ID25

ID24

ID23

ID22

ID21

0x00X1

IDR1

ID20

ID14

ID6

ID19

ID13

ID5

ID18

ID12

ID4

SRR (=1)

ID11

ID3

IDE (=1)

ID10

ID2

ID17

ID9

ID16

ID8

ID15

ID7

0x00X2

IDR2

0x00X3

IDR3

ID1

ID0

RTR

DB0

DLC0

0x00X4

DSR0

DB7

DB6

DB5

DB4

DB3

DLC3

DB2

DLC2

DB1

DLC1

0x00X5

DSR1

0x00X6

DSR2

0x00X7

DSR3

0x00X8

DSR4

0x00X9

DSR5

0x00XA

DSR6

0x00XB

DSR7

0x00XC

DLR

= Unused, always read ‘x’

Figure 14-23. Receive/Transmit Message Buffer — Extended Identiﬁer Mapping

Read: For transmit buffers, anytime when TXEx ﬂag is set (see Section 14.3.2.7, “MSCAN Transmitter

Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see

Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). For receive buffers,

only when RXF ﬂag is set (see Section 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”).

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Write: For transmit buffers, anytime when TXEx ﬂag is set (see Section 14.3.2.7, “MSCAN Transmitter

Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see

Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Unimplemented for

receive buffers.

Reset: Undeﬁned (0x00XX) because of RAM-based implementation

Name

Bit 7

Bit 0

IDR0

0x00X0

ID10

ID9

ID8

ID7

ID6

ID5

ID4

ID3

IDR1

0x00X1

ID2

ID1

ID0

RTR

IDE (=0)

IDR2

0x00X2

IDR3

0x00X3

= Unused, always read ‘x’

Figure 14-24. Receive/Transmit Message Buffer — Standard Identiﬁer Mapping

14.3.3.1 Identiﬁer Registers (IDR0–IDR3)

The identiﬁer registers for an extended format identiﬁer consist of a total of 32 bits; ID[28:0], SRR, IDE,

and RTR bits. The identiﬁer registers for a standard format identiﬁer consist of a total of 13 bits; ID[10:0],

RTR, and IDE bits.

14.3.3.1.1

IDR0–IDR3 for Extended Identiﬁer Mapping

Module Base + 0x00X1

ID28

ID27

ID26

ID25

ID24

ID23

ID22

ID21

Reset:

Figure 14-25. Identiﬁer Register 0 (IDR0) — Extended Identiﬁer Mapping

Table 14-26. IDR0 Register Field Descriptions — Extended

Description

Field

7:0

ID[28:21]

Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the

most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an

identiﬁer is deﬁned to be highest for the smallest binary number.

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Module Base + 0x00X1

ID20

ID19

ID18

SRR (=1)

IDE (=1)

ID17

ID16

ID15

Reset:

Figure 14-26. Identiﬁer Register 1 (IDR1) — Extended Identiﬁer Mapping

Table 14-27. IDR1 Register Field Descriptions — Extended

Description

Field

7:5

ID[20:18]

Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the

most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an

identiﬁer is deﬁned to be highest for the smallest binary number.

Substitute Remote Request — This ﬁxed recessive bit is used only in extended format. It must be set to 1 by

SRR

the user for transmission buffers and is stored as received on the CAN bus for receive buffers.

IDE

ID Extended — This ﬂag indicates whether the extended or standard identiﬁer format is applied in this buffer. In

the case of a receive buffer, the ﬂag is set as received and indicates to the CPU how to process the buffer

identiﬁer registers. In the case of a transmit buffer, the ﬂag indicates to the MSCAN what type of identiﬁer to send.

0 Standard format (11 bit)

1 Extended format (29 bit)

2:0

ID[17:15]

Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the

most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an

identiﬁer is deﬁned to be highest for the smallest binary number.

Module Base + 0x00X2

ID14

ID13

ID12

ID11

ID10

ID9

ID8

ID7

Reset:

Figure 14-27. Identiﬁer Register 2 (IDR2) — Extended Identiﬁer Mapping

Table 14-28. IDR2 Register Field Descriptions — Extended

Description

Field

7:0

ID[14:7]

Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the

most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an

identiﬁer is deﬁned to be highest for the smallest binary number.

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Module Base + 0x00X3

ID6

ID5

ID4

ID3

ID2

ID1

ID0

RTR

Reset:

Figure 14-28. Identiﬁer Register 3 (IDR3) — Extended Identiﬁer Mapping

Table 14-29. IDR3 Register Field Descriptions — Extended

Description

Field

7:1

ID[6:0]

Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the

most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an

identiﬁer is deﬁned to be highest for the smallest binary number.

Remote Transmission Request — This ﬂag reﬂects the status of the remote transmission request bit in the

RTR

CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the

transmission of an answering frame in software. In the case of a transmit buffer, this ﬂag deﬁnes the setting of

the RTR bit to be sent.

0 Data frame

1 Remote frame

14.3.3.1.2

IDR0–IDR3 for Standard Identiﬁer Mapping

Module Base + 0x00X0

ID10

ID9

ID8

ID7

ID6

ID5

ID4

ID3

Reset:

Figure 14-29. Identiﬁer Register 0 — Standard Mapping

Table 14-30. IDR0 Register Field Descriptions — Standard

Description

Field

7:0

ID[10:3]

Standard Format Identiﬁer — The identiﬁers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the

most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an

identiﬁer is deﬁned to be highest for the smallest binary number. See also ID bits in Table 14-31.

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Module Base + 0x00X1

ID2

ID1

ID0

RTR

IDE (=0)

Reset:

= Unused; always read ‘x’

Figure 14-30. Identiﬁer Register 1 — Standard Mapping

Table 14-31. IDR1 Register Field Descriptions

Description

Field

7:5

ID[2:0]

Standard Format Identiﬁer — The identiﬁers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the

most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an

identiﬁer is deﬁned to be highest for the smallest binary number. See also ID bits in Table 14-30.

Remote Transmission Request — This ﬂag reﬂects the status of the Remote Transmission Request bit in the

RTR

CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the

transmission of an answering frame in software. In the case of a transmit buffer, this ﬂag deﬁnes the setting of

the RTR bit to be sent.

0 Data frame

1 Remote frame

IDE

ID Extended — This ﬂag indicates whether the extended or standard identiﬁer format is applied in this buffer. In

the case of a receive buffer, the ﬂag is set as received and indicates to the CPU how to process the buffer

identiﬁer registers. In the case of a transmit buffer, the ﬂag indicates to the MSCAN what type of identiﬁer to send.

0 Standard format (11 bit)

1 Extended format (29 bit)

Module Base + 0x00X2

Reset:

= Unused; always read ‘x’

Figure 14-31. Identiﬁer Register 2 — Standard Mapping

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Module Base + 0x00X3

Reset:

= Unused; always read ‘x’

Figure 14-32. Identiﬁer Register 3 — Standard Mapping

14.3.3.2 Data Segment Registers (DSR0-7)

The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received.

The number of bytes to be transmitted or received is determined by the data length code in the

corresponding DLR register.

Module Base + 0x0004 (DSR0)

0x0005 (DSR1)

0x0006 (DSR2)

0x0007 (DSR3)

0x0008 (DSR4)

0x0009 (DSR5)

0x000A (DSR6)

0x000B (DSR7)

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Reset:

Figure 14-33. Data Segment Registers (DSR0–DSR7) — Extended Identiﬁer Mapping

Table 14-32. DSR0–DSR7 Register Field Descriptions

Field

Description

7:0

Data bits 7:0

DB[7:0]

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14.3.3.3 Data Length Register (DLR)

This register keeps the data length ﬁeld of the CAN frame.

Module Base + 0x00XB

DLC3

DLC2

DLC1

DLC0

Reset:

= Unused; always read “x”

Figure 14-34. Data Length Register (DLR) — Extended Identiﬁer Mapping

Table 14-33. DLR Register Field Descriptions

Description

Field

3:0

DLC[3:0]

Data Length Code Bits — The data length code contains the number of bytes (data byte count) of the respective

message. During the transmission of a remote frame, the data length code is transmitted as programmed while

the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame.

Table 14-34 shows the effect of setting the DLC bits.

Table 14-34. Data Length Codes

Data Length Code

Data Byte

Count

DLC3

DLC2

DLC1

DLC0

14.3.3.4 Transmit Buffer Priority Register (TBPR)

This register deﬁnes the local priority of the associated message buffer. The local priority is used for the

internal prioritization process of the MSCAN and is deﬁned to be highest for the smallest binary number.

The MSCAN implements the following internal prioritization mechanisms:

•

All transmission buffers with a cleared TXEx ﬂag participate in the prioritization immediately

before the SOF (start of frame) is sent.

•

The transmission buffer with the lowest local priority ﬁeld wins the prioritization.

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In cases of more than one buffer having the same lowest priority, the message buffer with the lower index

number wins.

Module Base + 0xXXXD

PRIO7

PRIO6

PRIO5

PRIO4

PRIO3

PRIO2

PRIO1

PRIO0

Reset:

Figure 14-35. Transmit Buffer Priority Register (TBPR)

Read: Anytime when TXEx ﬂag is set (see Section 14.3.2.7, “MSCAN Transmitter Flag Register

(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 14.3.2.11,

“MSCAN Transmit Buffer Selection Register (CANTBSEL)”).

Write: Anytime when TXEx ﬂag is set (see Section 14.3.2.7, “MSCAN Transmitter Flag Register

(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 14.3.2.11,

“MSCAN Transmit Buffer Selection Register (CANTBSEL)”).

14.3.3.5 Time Stamp Register (TSRH–TSRL)

If the TIME bit is enabled, the MSCAN will write a special time stamp to the respective registers in the

active transmit or receive buffer as soon as a message has been acknowledged on the CAN bus (see

Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). The time stamp is written on the bit sample

point for the recessive bit of the ACK delimiter in the CAN frame. In case of a transmission, the CPU can

only read the time stamp after the respective transmit buffer has been ﬂagged empty.

The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer

overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The

CPU can only read the time stamp registers.

Module Base + 0xXXXE

TSR15

TSR14

TSR13

TSR12

TSR11

TSR10

TSR9

TSR8

Reset:

Figure 14-36. Time Stamp Register — High Byte (TSRH)

Module Base + 0xXXXF

TSR7

TSR6

TSR5

TSR4

TSR3

TSR2

TSR1

TSR0

Reset:

Figure 14-37. Time Stamp Register — Low Byte (TSRL)

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Read: Anytime when TXEx ﬂag is set (see Section 14.3.2.7, “MSCAN Transmitter Flag Register

(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 14.3.2.11,

“MSCAN Transmit Buffer Selection Register (CANTBSEL)”).

Write: Unimplemented

14.4 Functional Description

14.4.1 General

This section provides a complete functional description of the MSCAN. It describes each of the features

and modes listed in the introduction.

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14.4.2 Message Storage

CAN

Receive / Transmit

Engine

CPU12

Memory Mapped

I/O

Rx0

Rx1

Rx2

MSCAN

Rx3

Rx4

RXF

CPU bus

Receiver

TXE0

Tx0

PRIO

TXE1

Tx1

CPU bus

MSCAN

PRIO

TXE2

Tx2

PRIO

Transmitter

Figure 14-38. User Model for Message Buffer Organization

MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad

range of network applications.

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14.4.2.1 Message Transmit Background

Modern application layer software is built upon two fundamental assumptions:

•

Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus

between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the

previous message and only release the CAN bus in case of lost arbitration.

•

The internal message queue within any CAN node is organized such that the highest priority

message is sent out ﬁrst, if more than one message is ready to be sent.

The behavior described in the bullets above cannot be achieved with a single transmit buffer. That buffer

must be reloaded immediately after the previous message is sent. This loading process lasts a ﬁnite amount

of time and must be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted

stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts

with short latencies to the transmit interrupt.

A double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending

and, therefore, reduces the reactiveness requirements of the CPU. Problems can arise if the sending of a

message is ﬁnished while the CPU re-loads the second buffer. No buffer would then be ready for

transmission, and the CAN bus would be released.

At least three transmit buffers are required to meet the ﬁrst of the above requirements under all

circumstances. The MSCAN has three transmit buffers.

The second requirement calls for some sort of internal prioritization which the MSCAN implements with

the “local priority” concept described in Section 14.4.2.2, “Transmit Structures.”

14.4.2.2 Transmit Structures

The MSCAN triple transmit buffer scheme optimizes real-time performance by allowing multiple

messages to be set up in advance. The three buffers are arranged as shown in Figure 14-38.

All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see

Section 14.3.3, “Programmer’s Model of Message Storage”). An additional Section 14.3.3.4, “Transmit

Buffer Priority Register (TBPR) contains an 8-bit local priority ﬁeld (PRIO) (see Section 14.3.3.4,

“Transmit Buffer Priority Register (TBPR)”). The remaining two bytes are used for time stamping of a

message, if required (see Section 14.3.3.5, “Time Stamp Register (TSRH–TSRL)”).

To transmit a message, the CPU must identify an available transmit buffer, which is indicated by a set

transmitter buffer empty (TXEx) ﬂag (see Section 14.3.2.7, “MSCAN Transmitter Flag Register

(CANTFLG)”). If a transmit buffer is available, the CPU must set a pointer to this buffer by writing to the

CANTBSEL register (see Section 14.3.2.11, “MSCAN Transmit Buffer Selection Register

(CANTBSEL)”). This makes the respective buffer accessible within the CANTXFG address space (see

Section 14.3.3, “Programmer’s Model of Message Storage”). The algorithmic feature associated with the

CANTBSEL register simpliﬁes the transmit buffer selection. In addition, this scheme makes the handler

software simpler because only one address area is applicable for the transmit process, and the required

address space is minimized.

The CPU then stores the identiﬁer, the control bits, and the data content into one of the transmit buffers.

Finally, the buffer is ﬂagged as ready for transmission by clearing the associated TXE ﬂag.

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The MSCAN then schedules the message for transmission and signals the successful transmission of the

buffer by setting the associated TXE ﬂag. A transmit interrupt (see Section 14.4.8.2, “Transmit Interrupt”)

is generated when TXEx is set and can be used to drive the application software to re-load the buffer.

If more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration,

the MSCAN uses the local priority setting of the three buffers to determine the prioritization. For this

purpose, every transmit buffer has an 8-bit local priority ﬁeld (PRIO). The application software programs

this ﬁeld when the message is set up. The local priority reﬂects the priority of this particular message

relative to the set of messages being transmitted from this node. The lowest binary value of the PRIO ﬁeld

is deﬁned to be the highest priority. The internal scheduling process takes place whenever the MSCAN

arbitrates for the CAN bus. This is also the case after the occurrence of a transmission error.

When a high priority message is scheduled by the application software, it may become necessary to abort

a lower priority message in one of the three transmit buffers. Because messages that are already in

transmission cannot be aborted, the user must request the abort by setting the corresponding abort request

bit (ABTRQ) (see Section 14.3.2.9, “MSCAN Transmitter Message Abort Request Register

(CANTARQ)”.) The MSCAN then grants the request, if possible, by:

1. Setting the corresponding abort acknowledge ﬂag (ABTAK) in the CANTAAK register.

2. Setting the associated TXE ﬂag to release the buffer.

3. Generating a transmit interrupt. The transmit interrupt handler software can determine from the

setting of the ABTAK ﬂag whether the message was aborted (ABTAK = 1) or sent (ABTAK = 0).

14.4.2.3 Receive Structures

The received messages are stored in a ﬁve stage input FIFO. The ﬁve message buffers are alternately

mapped into a single memory area (see Figure 14-38). The background receive buffer (RxBG) is

exclusively associated with the MSCAN, but the foreground receive buffer (RxFG) is addressable by the

CPU (see Figure 14-38). This scheme simpliﬁes the handler software because only one address area is

applicable for the receive process.

All receive buffers have a size of 15 bytes to store the CAN control bits, the identiﬁer (standard or

extended), the data contents, and a time stamp, if enabled (see Section 14.3.3, “Programmer’s Model of

Message Storage”)[<f-helvetica><st-bold>1.].

The receiver full ﬂag (RXF) (see Section 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”)

signals the status of the foreground receive buffer. When the buffer contains a correctly received message

with a matching identiﬁer, this ﬂag is set.

On reception, each message is checked to see whether it passes the ﬁlter (see Section 14.4.3, “Identiﬁer

Acceptance Filter”) and simultaneously is written into the active RxBG. After successful reception of a

valid message, the MSCAN shifts the content of RxBG into the receiver FIFO , sets the RXF ﬂag, and

generates a receive interrupt (see Section 14.4.8.3, “Receive Interrupt”) to the CPU . The user’s receive

handler must read the received message from the RxFG and then reset the RXF ﬂag to acknowledge the

interrupt and to release the foreground buffer. A new message, which can follow immediately after the IFS

1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also.

2. Only if the RXF ﬂag is not set.

3. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also.

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

ﬁeld of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid

message in its RxBG (wrong identiﬁer, transmission errors, etc.) the actual contents of the buffer will be

over-written by the next message. The buffer will then not be shifted into the FIFO.

When the MSCAN module is transmitting, the MSCAN receives its own transmitted messages into the

background receive buffer, RxBG, but does not shift it into the receiver FIFO, generate a receive interrupt,

or acknowledge its own messages on the CAN bus. The exception to this rule is in loopback mode (see

Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1)”) where the MSCAN treats its own messages

exactly like all other incoming messages. The MSCAN receives its own transmitted messages in the event

that it loses arbitration. If arbitration is lost, the MSCAN must be prepared to become a receiver.

An overrun condition occurs when all receive message buffers in the FIFO are ﬁlled with correctly

received messages with accepted identiﬁers and another message is correctly received from the CAN bus

with an accepted identiﬁer. The latter message is discarded and an error interrupt with overrun indication

is generated if enabled (see Section 14.4.8.5, “Error Interrupt”). The MSCAN remains able to transmit

messages while the receiver FIFO being ﬁlled, but all incoming messages are discarded. As soon as a

receive buffer in the FIFO is available again, new valid messages will be accepted.

14.4.3 Identiﬁer Acceptance Filter

The MSCAN identiﬁer acceptance registers (see Section 14.3.2.12, “MSCAN Identiﬁer Acceptance

Control Register (CANIDAC)”) deﬁne the acceptable patterns of the standard or extended identiﬁer

(ID[10:0] or ID[28:0]). Any of these bits can be marked ‘don’t care’ in the MSCAN identiﬁer mask

registers (see Section 14.3.2.18, “MSCAN Identiﬁer Mask Registers (CANIDMR0–CANIDMR7)”).

A ﬁlter hit is indicated to the application software by a set receive buffer full ﬂag (RXF = 1) and three bits

in the CANIDAC register (see Section 14.3.2.12, “MSCAN Identiﬁer Acceptance Control Register

(CANIDAC)”). These identiﬁer hit ﬂags (IDHIT[2:0]) clearly identify the ﬁlter section that caused the

acceptance. They simplify the application software’s task to identify the cause of the receiver interrupt. If

more than one hit occurs (two or more ﬁlters match), the lower hit has priority.

A very ﬂexible programmable generic identiﬁer acceptance ﬁlter has been introduced to reduce the CPU

interrupt loading. The ﬁlter is programmable to operate in four different modes (see Bosch CAN 2.0A/B

protocol speciﬁcation):

•

Two identiﬁer acceptance ﬁlters, each to be applied to:

— The full 29 bits of the extended identiﬁer and to the following bits of the CAN 2.0B frame:

– Remote transmission request (RTR)

– Identiﬁer extension (IDE)

– Substitute remote request (SRR)

— The 11 bits of the standard identiﬁer plus the RTR and IDE bits of the CAN 2.0A/B messages .

This mode implements two ﬁlters for a full length CAN 2.0B compliant extended identiﬁer.

Figure 14-39 shows how the ﬁrst 32-bit ﬁlter bank (CANIDAR0–CANIDAR3,

CANIDMR0–CANIDMR3) produces a ﬁlter 0 hit. Similarly, the second ﬁlter bank

(CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces a ﬁlter 1 hit.

1.Although this mode can be used for standard identifiers, it is recommended to use the four or eight identifier acceptance

filters for standard identifiers

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

•

Four identiﬁer acceptance ﬁlters, each to be applied to

— a) the 14 most signiﬁcant bits of the extended identiﬁer plus the SRR and IDE bits of CAN 2.0B

messages or

— b) the 11 bits of the standard identiﬁer, the RTR and IDE bits of CAN 2.0A/B messages.

Figure 14-40 shows how the ﬁrst 32-bit ﬁlter bank (CANIDAR0–CANIDA3,

CANIDMR0–3CANIDMR) produces ﬁlter 0 and 1 hits. Similarly, the second ﬁlter bank

(CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces ﬁlter 2 and 3 hits.

•

Eight identiﬁer acceptance ﬁlters, each to be applied to the ﬁrst 8 bits of the identiﬁer. This mode

implements eight independent ﬁlters for the ﬁrst 8 bits of a CAN 2.0A/B compliant standard

identiﬁer or a CAN 2.0B compliant extended identiﬁer. Figure 14-41 shows how the ﬁrst 32-bit

ﬁlter bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces ﬁlter 0 to 3 hits.

Similarly, the second ﬁlter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7)

produces ﬁlter 4 to 7 hits.

Closed ﬁlter. No CAN message is copied into the foreground buffer RxFG, and the RXF ﬂag is

never set.

CAN 2.0B

Extended Identiﬁer

ID28

ID10

IDR0

ID21 ID20

ID3 ID2

IDR1

ID15 ID14

IDR2

ID7 ID6

IDR3

RTR

ID3

CAN 2.0A/B

Standard Identiﬁer

IDE

ID10

ID3 ID10

AM7

AC7

CANIDMR0

CANIDAR0

AM0 AM7

AC0 AC7

CANIDMR1

CANIDAR1

AM0 AM7

AC0 AC7

CANIDMR2

CANIDAR2

AM0 AM7

AC0 AC7

CANIDMR3

CANIDAR3

AM0

AC0

ID Accepted (Filter 0 Hit)

Figure 14-39. 32-bit Maskable Identiﬁer Acceptance Filter

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CAN 2.0B

Extended Identiﬁer

ID28

ID10

IDR0

ID21 ID20

ID3 ID2

IDR1

ID15 ID14

IDE ID10

IDR2

ID7 ID6

IDR3

RTR

ID3

CAN 2.0A/B

Standard Identiﬁer

ID3 ID10

AM7

AC7

CANIDMR0

CANIDAR0

AM0 AM7

AC0 AC7

CANIDMR1

CANIDAR1

AM0

AC0

ID Accepted (Filter 0 Hit)

AM7

AC7

CANIDMR2

CANIDAR2

AM0 AM7

AC0 AC7

CANIDMR3

AM0

AC0

CANIDAR3

ID Accepted (Filter 1 Hit)

Figure 14-40. 16-bit Maskable Identiﬁer Acceptance Filters

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CAN 2.0B

Extended Identiﬁer ID28

IDR0

ID21 ID20

ID3 ID2

IDR1

ID15 ID14

IDE ID10

IDR2

ID7 ID6

IDR3

RTR

ID3

CAN 2.0A/B

ID10

ID3 ID10

Standard Identiﬁer

AM7

AC7

CIDMR0

CIDAR0

AM0

AC0

ID Accepted (Filter 0 Hit)

AM7

AC7

CIDMR1

AM0

AC0

CIDAR1

ID Accepted (Filter 1 Hit)

AM7

AC7

CIDMR2

AM0

AC0

CIDAR2

ID Accepted (Filter 2 Hit)

AM7

AC7

CIDMR3

AM0

AC0

CIDAR3

ID Accepted (Filter 3 Hit)

Figure 14-41. 8-bit Maskable Identiﬁer Acceptance Filters

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14.4.3.1 Protocol Violation Protection

The MSCAN protects the user from accidentally violating the CAN protocol through programming errors.

The protection logic implements the following features:

•

The receive and transmit error counters cannot be written or otherwise manipulated.

All registers which control the conﬁguration of the MSCAN cannot be modiﬁed while the MSCAN

is on-line. The MSCAN has to be in Initialization Mode. The corresponding INITRQ/INI TAK

handshake bits in the CANCTL0/CANCTL1 registers (see Section 14.3.2.1, “MSCAN Control

— MSCAN control 1 register (CANCTL1)

— MSCAN bus timing registers 0 and 1 (CANBTR0, CANBTR1)

— MSCAN identiﬁer acceptance control register (CANIDAC)

— MSCAN identiﬁer acceptance registers (CANIDAR0–CANIDAR7)

— MSCAN identiﬁer mask registers (CANIDMR0–CANIDMR7)

•

The TXCAN pin is immediately forced to a recessive state when the MSCAN goes into the power

down mode or initialization mode (see Section 14.4.6.6, “MSCAN Power Down Mode,” and

Section 14.4.6.5, “MSCAN Initialization Mode”).

The MSCAN enable bit (CANE) is writable only once in normal system operation modes, which

provides further protection against inadvertently disabling the MSCAN.

14.4.3.2 Clock System

Figure 14-42 shows the structure of the MSCAN clock generation circuitry.

MSCAN

Bus Clock

Time quanta clock (Tq)

CANCLK

Prescaler

(1 .. 64)

CLKSRC

Oscillator Clock

Figure 14-42. MSCAN Clocking Scheme

The clock source bit (CLKSRC) in the CANCTL1 register (14.3.2.2/14-624) deﬁnes whether the internal

CANCLK is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock.

The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the

CAN protocol are met. Additionally, for high CAN bus rates (1 Mbps), a 45% to 55% duty cycle of the

clock is required.

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If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the

bus clock due to jitter considerations, especially at the faster CAN bus rates.

For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal

oscillator (oscillator clock).

A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the

atomic unit of time handled by the MSCAN.

Eqn. 14-2

CANCLK

= -----------------------------------------------------

(Prescaler value)

A bit time is subdivided into three segments as described in the Bosch CAN speciﬁcation. (see

Figure 14-43):

•

SYNC_SEG: This segment has a ﬁxed length of one time quantum. Signal edges are expected to

happen within this section.

Time Segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN

standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta.

Time Segment 2: This segment represents the PHASE_SEG2 of the CAN standard. It can be

programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long.

Eqn. 14-3

Bit Rate= --------------------------------------------------------------------------------

(number of Time Quanta)

NRZ Signal

Time Segment 1

Time Segment 2

(PHASE_SEG2)

SYNC_SEG

(PROP_SEG + PHASE_SEG1)

4 ... 16

2 ... 8

8 ... 25 Time Quanta

= 1 Bit Time

Transmit Point

Sample Point

(single or triple sampling)

Figure 14-43. Segments within the Bit Time

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Table 14-35. Time Segment Syntax

Syntax

Description

System expects transitions to occur on the CAN bus during this

period.

SYNC_SEG

A node in transmit mode transfers a new value to the CAN bus at

this point.

Transmit Point

Sample Point

A node in receive mode samples the CAN bus at this point. If the

three samples per bit option is selected, then this point marks the

position of the third sample.

The synchronization jump width (see the Bosch CAN speciﬁcation for details) can be programmed in a

range of 1 to 4 time quanta by setting the SJW parameter.

The SYNC_SEG, TSEG1, TSEG2, and SJW parameters are set by programming the MSCAN bus timing

registers (CANBTR0, CANBTR1) (see Section 14.3.2.3, “MSCAN Bus Timing Register 0 (CANBTR0)”

and Section 14.3.2.4, “MSCAN Bus Timing Register 1 (CANBTR1)”).

Table 14-36 gives an overview of the CAN compliant segment settings and the related parameter values.

NOTE

It is the user’s responsibility to ensure the bit time settings are in compliance

with the CAN standard.

Table 14-36. CAN Standard Compliant Bit Time Segment Settings

Synchronization

Time Segment 1

TSEG1

Time Segment 2

TSEG2

SJW

Jump Width

5 .. 10

4 .. 11

5 .. 12

6 .. 13

7 .. 14

8 .. 15

9 .. 16

4 .. 9

3 .. 10

4 .. 11

5 .. 12

6 .. 13

7 .. 14

8 .. 15

1 .. 2

1 .. 3

1 .. 4

0 .. 1

0 .. 2

0 .. 3

14.4.4 Timer Link

The MSCAN generates an internal time stamp whenever a valid frame is received or transmitted and the

TIME bit is enabled. Because the CAN speciﬁcation deﬁnes a frame to be valid if no errors occur before

the end of frame (EOF) ﬁeld is transmitted successfully, the actual value of an internal timer is written at

EOF to the appropriate time stamp position within the transmit buffer. For receive frames, the time stamp

is written to the receive buffer.

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14.4.5 Modes of Operation

14.4.5.1 Normal Modes

The MSCAN module behaves as described within this speciﬁcation in all normal system operation modes.

14.4.5.2 Special Modes

The MSCAN module behaves as described within this speciﬁcation in all special system operation modes.

14.4.5.3 Emulation Modes

In all emulation modes, the MSCAN module behaves just like normal system operation modes as

described within this speciﬁcation.

14.4.5.4 Listen-Only Mode

In an optional CAN bus monitoring mode (listen-only), the CAN node is able to receive valid data frames

and valid remote frames, but it sends only “recessive” bits on the CAN bus. In addition, it cannot start a

transmision. If the MAC sub-layer is required to send a “dominant” bit (ACK bit, overload ﬂag, or active

error ﬂag), the bit is rerouted internally so that the MAC sub-layer monitors this “dominant” bit, although

the CAN bus may remain in recessive state externally.

14.4.5.5 Security Modes

The MSCAN module has no security features.

14.4.6 Low-Power Options

If the MSCAN is disabled (CANE = 0), the MSCAN clocks are stopped for power saving.

If the MSCAN is enabled (CANE = 1), the MSCAN has two additional modes with reduced power

consumption, compared to normal mode: sleep and power down mode. In sleep mode, power consumption

is reduced by stopping all clocks except those to access the registers from the CPU side. In power down

mode, all clocks are stopped and no power is consumed.

Table 14-37 summarizes the combinations of MSCAN and CPU modes. A particular combination of

modes is entered by the given settings on the CSWAI and SLPRQ/SLPAK bits.

For all modes, an MSCAN wake-up interrupt can occur only if the MSCAN is in sleep mode (SLPRQ = 1

and SLPAK = 1), wake-up functionality is enabled (WUPE = 1), and the wake-up interrupt is enabled

(WUPIE = 1).

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Table 14-37. CPU vs. MSCAN Operating Modes

MSCAN Mode

Reduced Power Consumption

CPU Mode

Normal

Disabled

(CANE=0)

Sleep

Power Down

CSWAI = X

SLPRQ = 1

SLPAK = 1

CSWAI = X

SLPRQ = X

SLPAK = X

CSWAI = X

RUN

SLPRQ = 0

SLPAK = 0

CSWAI = 0

SLPRQ = 0

SLPAK = 0

CSWAI = 0

SLPRQ = 1

SLPAK = 1

CSWAI = 1

SLPRQ = X

SLPAK = X

CSWAI = X

SLPRQ = X

SLPAK = X

WAIT

CSWAI = X

SLPRQ = X

SLPAK = X

CSWAI = X

SLPRQ = X

SLPAK = X

STOP

‘X’ means don’t care.

14.4.6.1 Operation in Run Mode

As shown in Table 14-37, only MSCAN sleep mode is available as low power option when the CPU is in

run mode.

14.4.6.2 Operation in Wait Mode

The WAI instruction puts the MCU in a low power consumption stand-by mode. If the CSWAI bit is set,

additional power can be saved in power down mode because the CPU clocks are stopped. After leaving

this power down mode, the MSCAN restarts its internal controllers and enters normal mode again.

While the CPU is in wait mode, the MSCAN can be operated in normal mode and generate interrupts

(registers can be accessed via background debug mode). The MSCAN can also operate in any of the

low-power modes depending on the values of the SLPRQ/SLPAK and CSWAI bits as seen in Table 14-37.

14.4.6.3 Operation in Stop Mode

The STOP instruction puts the MCU in a low power consumption stand-by mode. In stop mode, the

MSCAN is set in power down mode regardless of the value of the SLPRQ/SLPAK and CSWAI bits

Table 14-37.

14.4.6.4 MSCAN Sleep Mode

The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the

CANCTL0 register. The time when the MSCAN enters sleep mode depends on a ﬁxed synchronization

delay and its current activity:

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•

If there are one or more message buffers scheduled for transmission (TXEx = 0), the MSCAN will

continue to transmit until all transmit message buffers are empty (TXEx = 1, transmitted

successfully or aborted) and then goes into sleep mode.

•

If the MSCAN is receiving, it continues to receive and goes into sleep mode as soon as the CAN

bus next becomes idle.

If the MSCAN is neither transmitting nor receiving, it immediately goes into sleep mode.

Bus Clock Domain

CAN Clock Domain

SLPRQ

Flag

SYNC

SLPRQ

sync.

SLPRQ

CPU

Sleep Request

SLPAK

Flag

sync.

SLPAK

MSCAN

in Sleep Mode

Figure 14-44. Sleep Request / Acknowledge Cycle

NOTE

The application software must avoid setting up a transmission (by clearing

one or more TXEx ﬂag(s)) and immediately request sleep mode (by setting

SLPRQ). Whether the MSCAN starts transmitting or goes into sleep mode

directly depends on the exact sequence of operations.

If sleep mode is active, the SLPRQ and SLPAK bits are set (Figure 14-44). The application software must

use SLPAK as a handshake indication for the request (SLPRQ) to go into sleep mode.

When in sleep mode (SLPRQ = 1 and SLPAK = 1), the MSCAN stops its internal clocks. However, clocks

that allow register accesses from the CPU side continue to run.

If the MSCAN is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits

due to the stopped clocks. The TXCAN pin remains in a recessive state. If RXF = 1, the message can be

read and RXF can be cleared. Shifting a new message into the foreground buffer of the receiver FIFO

(RxFG) does not take place while in sleep mode.

It is possible to access the transmit buffers and to clear the associated TXE ﬂags. No message abort takes

place while in sleep mode.

If the WUPE bit in CANCLT0 is not asserted, the MSCAN will mask any activity it detects on CAN. The

RXCAN pin is therefore held internally in a recessive state. This locks the MSCAN in sleep mode

(Figure 14-45).

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The MSCAN is able to leave sleep mode (wake up) only when:

•

CAN bus activity occurs and WUPE = 1

•

the CPU clears the SLPRQ bit

NOTE

The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and

SLPAK = 1) is active.

After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a

consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received.

The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode

was entered. All pending actions will be executed upon wake-up; copying of RxBG into RxFG, message

aborts and message transmissions. If the MSCAN remains in bus-off state after sleep mode was exited, it

continues counting the 128 occurrences of 11 consecutive recessive bits.

CAN Activity

(CAN Activity & WUPE) | SLPRQ

Wait

StartUp

for Idle

CAN Activity

SLPRQ

CAN Activity &

SLPRQ

Sleep

Idle

(CAN Activity & WUPE) |

CAN Activity

CAN Activity &

SLPRQ

CAN Activity

Tx/Rx

Message

Active

CAN Activity

Figure 14-45. Simpliﬁed State Transitions for Entering/Leaving Sleep Mode

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

14.4.6.5 MSCAN Initialization Mode

In initialization mode, any on-going transmission or reception is immediately aborted and synchronization

to the CAN bus is lost, potentially causing CAN protocol violations. To protect the CAN bus system from

fatal consequences of violations, the MSCAN immediately drives the TXCAN pin into a recessive state.

NOTE

The user is responsible for ensuring that the MSCAN is not active when

initialization mode is entered. The recommended procedure is to bring the

MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before setting the

INITRQ bit in the CANCTL0 register. Otherwise, the abort of an on-going

message can cause an error condition and can impact other CAN bus

devices.

In initialization mode, the MSCAN is stopped. However, interface registers remain accessible. This mode

is used to reset the CANCTL0, CANRFLG, CANRIER, CANTFLG, CANTIER, CANTARQ,

CANTAAK, and CANTBSEL registers to their default values. In addition, the MSCAN enables the

conﬁguration of the CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR,

CANIDMR message ﬁlters. See Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0),” for a

detailed description of the initialization mode.

Bus Clock Domain

CAN Clock Domain

INIT

Flag

SYNC

INITRQ

sync.

INITRQ

CPU

Init Request

INITAK

Flag

sync.

INITAK

Figure 14-46. Initialization Request/Acknowledge Cycle

Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by

using a special handshake mechanism. This handshake causes additional synchronization delay (see

Section Figure 14-46., “Initialization Request/Acknowledge Cycle”).

If there is no message transfer ongoing on the CAN bus, the minimum delay will be two additional bus

clocks and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the

INITAK ﬂag is set. The application software must use INITAK as a handshake indication for the request

(INITRQ) to go into initialization mode.

NOTE

The CPU cannot clear INITRQ before initialization mode (INITRQ = 1 and

INITAK = 1) is active.

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14.4.6.6 MSCAN Power Down Mode

The MSCAN is in power down mode (Table 14-37) when

•

CPU is in stop mode

•

CPU is in wait mode and the CSWAI bit is set

When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and

receptions, potentially causing CAN protocol violations. To protect the CAN bus system from fatal

consequences of violations to the above rule, the MSCAN immediately drives the TXCAN pin into a

recessive state.

NOTE

The user is responsible for ensuring that the MSCAN is not active when

power down mode is entered. The recommended procedure is to bring the

MSCAN into Sleep mode before the STOP or WAI instruction (if CSWAI

is set) is executed. Otherwise, the abort of an ongoing message can cause an

error condition and impact other CAN bus devices.

In power down mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in

sleep mode before power down mode became active, the module performs an internal recovery cycle after

powering up. This causes some ﬁxed delay before the module enters normal mode again.

14.4.6.7 Programmable Wake-Up Function

The MSCAN can be programmed to wake up the MSCAN as soon as CAN bus activity is detected (see

control bit WUPE in Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). The sensitivity to

existing CAN bus action can be modiﬁed by applying a low-pass ﬁlter function to the RXCAN input line

while in sleep mode (see control bit WUPM in Section 14.3.2.2, “MSCAN Control Register 1

(CANCTL1)”).

This feature can be used to protect the MSCAN from wake-up due to short glitches on the CAN bus lines.

Such glitches can result from—for example—electromagnetic interference within noisy environments.

14.4.7 Reset Initialization

The reset state of each individual bit is listed in Section 14.3.2, “Register Descriptions,” which details all

the registers and their bit-ﬁelds.

14.4.8 Interrupts

This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated

ﬂags. Each interrupt is listed and described separately.

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14.4.8.1 Description of Interrupt Operation

The MSCAN supports four interrupt vectors (see Table 14-38 ), any of which can be individually masked

(for details see sections from Section 14.3.2.6, “MSCAN Receiver Interrupt Enable Register

(CANRIER),” to Section 14.3.2.8, “MSCAN Transmitter Interrupt Enable Register (CANTIER)”).

NOTE

The dedicated interrupt vector addresses are deﬁned in the Resets and

Interrupts chapter.

Table 14-38. Interrupt Vectors

Interrupt Source

CCR Mask

Local Enable

CANRIER (WUPIE)

Wake-Up Interrupt (WUPIF)

Error Interrupts Interrupt (CSCIF, OVRIF)

Receive Interrupt (RXF)

I bit

CANRIER (CSCIE, OVRIE)

CANRIER (RXFIE)

Transmit Interrupts (TXE[2:0])

CANTIER (TXEIE[2:0])

14.4.8.2 Transmit Interrupt

At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message

for transmission. The TXEx ﬂag of the empty message buffer is set.

14.4.8.3 Receive Interrupt

A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO.

This interrupt is generated immediately after receiving the EOF symbol. The RXF ﬂag is set. If there are

multiple messages in the receiver FIFO, the RXF ﬂag is set as soon as the next message is shifted to the

foreground buffer.

14.4.8.4 Wake-Up Interrupt

A wake-up interrupt is generated if activity on the CAN bus occurs during MSCN internal sleep mode.

WUPE (see Section 14.3.2.1, “MSCAN Control Register 0 (CANCTL0)”) must be enabled.

14.4.8.5 Error Interrupt

An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition

occurrs. Section 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG) indicates one of the following

conditions:

•

Overrun — An overrun condition of the receiver FIFO as described in Section 14.4.2.3, “Receive

Structures,” occurred.

•

CAN Status Change — The actual value of the transmit and receive error counters control the

CAN bus state of the MSCAN. As soon as the error counters skip into a critical range

(Tx/Rx-warning, Tx/Rx-error, bus-off) the MSCAN ﬂags an error condition. The status change,

which caused the error condition, is indicated by the TSTAT and RSTAT ﬂags (see

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Section 14.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)” and Section 14.3.2.6, “MSCAN

Receiver Interrupt Enable Register (CANRIER)”).

14.4.8.6 Interrupt Acknowledge

Interrupts are directly associated with one or more status ﬂags in either the Section 14.3.2.5, “MSCAN

Receiver Flag Register (CANRFLG)” or the Section 14.3.2.7, “MSCAN Transmitter Flag Register

(CANTFLG).” Interrupts are pending as long as one of the corresponding ﬂags is set. The ﬂags in

CANRFLG and CANTFLG must be reset within the interrupt handler to handshake the interrupt. The ﬂags

are reset by writing a 1 to the corresponding bit position. A ﬂag cannot be cleared if the respective

condition prevails.

NOTE

It must be guaranteed that the CPU clears only the bit causing the current

interrupt. For this reason, bit manipulation instructions (BSET) must not be

used to clear interrupt ﬂags. These instructions may cause accidental

clearing of interrupt ﬂags which are set after entering the current interrupt

service routine.

14.4.8.7 Recovery from Stop or Wait

The MSCAN can recover from stop or wait via the wake-up interrupt. This interrupt can only occur if the

MSCAN was in sleep mode (SLPRQ = 1 and SLPAK = 1) before entering power down mode, the wake-up

option is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1).

14.5 Initialization/Application Information

14.5.1 MSCAN initialization

The procedure to initially start up the MSCAN module out of reset is as follows:

1. Assert CANE

2. Write to the conﬁguration registers in initialization mode

3. Clear INITRQ to leave initialization mode and enter normal mode

If the conﬁguration of registers which are writable in initialization mode needs to be changed only when

the MSCAN module is in normal mode:

1. Bring the module into sleep mode by setting SLPRQ and awaiting SLPAK to assert after the CAN

bus becomes idle.

2. Enter initialization mode: assert INITRQ and await INITAK

3. Write to the conﬁguration registers in initialization mode

4. Clear INITRQ to leave initialization mode and continue in normal mode

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Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)

14.5.2 Bus-Off Recovery

The bus-off recovery is user conﬁgurable. The bus-off state can either be left automatically or on user

request.

For reasons of backwards compatibility, the MSCAN defaults to automatic recovery after reset. In this

case, the MSCAN will become error active again after counting 128 occurrences of 11 consecutive

recessive bits on the CAN bus (See the Bosch CAN speciﬁcation for details).

If the MSCAN is conﬁgured for user request (BORM set in Section 14.3.2.2, “MSCAN Control Register

1 (CANCTL1)”), the recovery from bus-off starts after both independent events have become true:

•

128 occurrences of 11 consecutive recessive bits on the CAN bus have been monitored

BOHOLD in Section 14.3.2.14, “MSCAN Miscellaneous Register (CANMISC) has been cleared

by the user

These two events may occur in any order.

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Chapter 15

Serial Communication Interface (S12MC9S12XDP512V5)

15.1 Introduction

This block guide provides an overview of the serial communication interface (SCI) module.

The SCI allows asynchronous serial communications with peripheral devices and other CPUs.

15.1.1 Features

The SCI includes these distinctive features:

•

Full-duplex or single-wire operation

Standard mark/space non-return-to-zero (NRZ) format

Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths

13-bit baud rate selection

Programmable 8-bit or 9-bit data format

Separately enabled transmitter and receiver

Programmable polarity for transmitter and receiver

Programmable transmitter output parity

Two receiver wakeup methods:

— Idle line wakeup

— Address mark wakeup

•

Interrupt-driven operation with eight flags:

— Transmitter empty

— Transmission complete

— Receiver full

— Idle receiver input

— Receiver overrun

— Noise error

— Framing error

— Parity error

— Receive wakeup on active edge

— Transmit collision detect supporting LIN

— Break Detect supporting LIN

Receiver framing error detection

•

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

•

Hardware parity checking

1/16 bit-time noise detection

15.1.2 Modes of Operation

The SCI functions the same in normal, special, and emulation modes. It has two low power modes, wait

and stop modes.

•

Run mode

Wait mode

Stop mode

15.1.3 Block Diagram

Figure 15-1 is a high level block diagram of the SCI module, showing the interaction of various function

blocks.

SCI Data Register

RXD Data In

Infrared

Decoder

Receive Shift Register

IDLE

Receive

Interrupt

Generation

RDRF/OR

BRKD

Receive & Wakeup

Control

SCI

Interrupt

Request

RXEDG

Bus Clock

Baud Rate

Generator

BERR

Data Format Control

Transmit Control

Transmit

Interrupt

Generation

TDRE

1/16

Infrared

Encoder

Data Out TXD

Transmit Shift Register

SCI Data Register

Figure 15-1. SCI Block Diagram

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.2 External Signal Description

The SCI module has a total of two external pins.

15.2.1 TXD — Transmit Pin

The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high

impedance anytime the transmitter is disabled.

15.2.2 RXD — Receive Pin

The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high. This input is

ignored when the receiver is disabled and should be terminated to a known voltage.

15.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all the SCI registers.

15.3.1 Module Memory Map and Register Deﬁnition

The memory map for the SCI module is given below in Table 1-1. The address listed for each register is

the address offset. The total address for each register is the sum of the base address for the SCI module and

the address offset for each register.

Table 15-1. MC9S12XDP512 Memory Map

Address

Offset

Name

Access

0x0000

0x0001

0x0002

0x000a

0x001a

0x002a

SCI Baud Rate Register High (SCIBDH)

R/W

SCI Baud Rate Register Low (SCIBDL)

SCI Control Register1 (SCICR1)

SCI Alternative Status Register 1 (SCIASR1)

SCI Alternative Control Register 1 (SCIACR1)

SCI Alternative Control Register 2 (SCIACR2)

SCI Control Register 2 (SCICR2)

0x0003

0x0004

0x0005

0x0006

0x0007

SCI Status Register 1 (SCISR1)

SCI Status Register 2(SCISR2)

R/W

SCI Data Register High (SCIDRH)

SCI Data Register Low (SCIDRL)

Those registers are accessible if the AMAP bit in the SCISR2 register is set to zero

Those registers are accessible if the AMAP bit in the SCISR2 register is set to one

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15.3.2 Register Descriptions

This section consists of register descriptions in address order. Each description includes a standard register

diagram with an associated ﬁgure number. Writes to a reserved register locations do not have any effect

and reads of these locations return a zero. Details of register bit and ﬁeld function follow the register

diagrams, in bit order.

Name

Bit 7

Bit 0

0x0000

SCIBDH

IREN

TNP1

TNP0

SBR12

SBR11

SBR10

SBR9

SBR8

0x0001

SCIBDL

SBR7

LOOPS

SBR6

SBR5

SBR4

SBR3

SBR2

ILT

SBR1

SBR0

0x0002

SCISWAI

RSRC

WAKE

SCICR1

0x000a

SCIASR1

RXEDGIF

BERRV

BERRIF

BERRIE

BERRM0

BKDIF

BKDIE

BKDFE

0x001a

SCIACR1

RXEDGIE

0x002a

SCIACR2

BERRM1

0x0003

SCICR2

TIE

TCIE

RIE

ILIE

RWU

SBK

0x0004

TDRE

RDRF

IDLE

SCISR1

0x0005

SCISR2

RAF

AMAP

TXPOL

RXPOL

BRK13

TXDIR

0x0006

SCIDRH

0x0007

SCIDRL

1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero.

2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one.

= Unimplemented or Reserved

Figure 15-2. MC9S12XDP512 Register Summary

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.3.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL)

Module Base + 0x0000

IREN

TNP1

TNP0

SBR12

SBR11

SBR10

SBR9

SBR8

Reset

Figure 15-3. SCI Baud Rate Register (SCIBDH)

Module Base + 0x0001

SBR7

SBR6

SBR5

SBR4

SBR3

SBR2

SBR1

SBR0

Reset

Figure 15-4. SCI Baud Rate Register (SCIBDL)

Read: Anytime, if AMAP = 0. If only SCIBDH is written to, a read will not return the correct data until

SCIBDL is written to as well, following a write to SCIBDH.

Write: Anytime, if AMAP = 0.

NOTE

Those two registers are only visible in the memory map if AMAP = 0 (reset

condition).

The SCI baud rate register is used by to determine the baud rate of the SCI, and to control the infrared

modulation/demodulation submodule.

Table 15-2. SCIBDH and SCIBDL Field Descriptions

Field

Description

Infrared Enable Bit — This bit enables/disables the infrared modulation/demodulation submodule.

IREN

0 IR disabled

1 IR enabled

6:5

Transmitter Narrow Pulse Bits — These bits enable whether the SCI transmits a 1/16, 3/16, 1/32 or 1/4 narrow

TNP[1:0]

pulse. See Table 15-3.

4:0

7:0

SCI Baud Rate Bits — The baud rate for the SCI is determined by the bits in this register. The baud rate is

calculated two different ways depending on the state of the IREN bit.

SBR[12:0] The formulas for calculating the baud rate are:

When IREN = 0 then,

SCI baud rate = SCI bus clock / (16 x SBR[12:0])

When IREN = 1 then,

SCI baud rate = SCI bus clock / (32 x SBR[12:1])

Note: The baud rate generator is disabled after reset and not started until the TE bit or the RE bit is set for the

ﬁrst time. The baud rate generator is disabled when (SBR[12:0] = 0 and IREN = 0) or (SBR[12:1] = 0 and

IREN = 1).

Note: Writing to SCIBDH has no effect without writing to SCIBDL, because writing to SCIBDH puts the data in

a temporary location until SCIBDL is written to.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

677

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

Table 15-3. IRSCI Transmit Pulse Width

TNP[1:0]

Narrow Pulse Width

1/4

1/32

1/16

3/16

15.3.2.2 SCI Control Register 1 (SCICR1)

Module Base + 0x0002

LOOPS

SCISWAI

RSRC

WAKE

ILT

Reset

Figure 15-5. SCI Control Register 1 (SCICR1)

Read: Anytime, if AMAP = 0.

Write: Anytime, if AMAP = 0.

NOTE

This register is only visible in the memory map if AMAP = 0 (reset

condition).

Table 15-4. SCICR1 Field Descriptions

Description

Field

Loop Select Bit — LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI

and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must

be enabled to use the loop function.

LOOPS

0 Normal operation enabled

1 Loop operation enabled

The receiver input is determined by the RSRC bit.

SCI Stop in Wait Mode Bit — SCISWAI disables the SCI in wait mode.

SCISWAI 0 SCI enabled in wait mode

1 SCI disabled in wait mode

Receiver Source Bit — When LOOPS = 1, the RSRC bit determines the source for the receiver shift register

RSRC

input. See Table 15-5.

0 Receiver input internally connected to transmitter output

1 Receiver input connected externally to transmitter

Data Format Mode Bit — MODE determines whether data characters are eight or nine bits long.

0 One start bit, eight data bits, one stop bit

1 One start bit, nine data bits, one stop bit

Wakeup Condition Bit — WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the

WAKE

most signiﬁcant bit position of a received data character or an idle condition on the RXD pin.

0 Idle line wakeup

1 Address mark wakeup

MC9S12XDP512 Data Sheet, Rev. 2.11

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Freescale Semiconductor

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

Table 15-4. SCICR1 Field Descriptions (continued)

Field

Description

ILT

Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The

counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of

logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the

stop bit avoids false idle character recognition, but requires properly synchronized transmissions.

0 Idle character bit count begins after start bit

1 Idle character bit count begins after stop bit

Parity Enable Bit — PE enables the parity function. When enabled, the parity function inserts a parity bit in the

most signiﬁcant bit position.

0 Parity function disabled

1 Parity function enabled

Parity Type Bit — PT determines whether the SCI generates and checks for even parity or odd parity. With even

parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an

odd number of 1s clears the parity bit and an even number of 1s sets the parity bit.

1 Even parity

1 Odd parity

Table 15-5. Loop Functions

LOOPS

RSRC

Function

Normal operation

Loop mode with transmitter output internally connected to receiver input

Single-wire mode with TXD pin connected to receiver input

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.3.2.3 SCI Alternative Status Register 1 (SCIASR1)

Module Base + 0x000a

BERRV

RXEDGIF

BERRIF

BKDIF

Reset

= Unimplemented or Reserved

Figure 15-6. SCI Alternative Status Register 1 (SCIASR1)

Read: Anytime, if AMAP = 1

Write: Anytime, if AMAP = 1

Table 15-6. SCIASR1 Field Descriptions

Description

Field

Receive Input Active Edge Interrupt Flag — RXEDGIF is asserted, if an active edge (falling if RXPOL = 0,

RXEDGIF rising if RXPOL = 1) on the RXD input occurs. RXEDGIF bit is cleared by writing a “1” to it.

0 No active receive on the receive input has occurred

1 An active edge on the receive input has occurred

Bit Error Value — BERRV reﬂects the state of the RXD input when the bit error detect circuitry is enabled and

a mismatch to the expected value happened. The value is only meaningful, if BERRIF = 1.

0 A low input was sampled, when a high was expected

BERRV

1 A high input reassembled, when a low was expected

Bit Error Interrupt Flag — BERRIF is asserted, when the bit error detect circuitry is enabled and if the value

sampled at the RXD input does not match the transmitted value. If the BERRIE interrupt enable bit is set an

interrupt will be generated. The BERRIF bit is cleared by writing a “1” to it.

0 No mismatch detected

BERRIF

1 A mismatch has occurred

Break Detect Interrupt Flag — BKDIF is asserted, if the break detect circuitry is enabled and a break signal is

BKDIF

received. If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing

a “1” to it.

0 No break signal was received

1 A break signal was received

MC9S12XDP512 Data Sheet, Rev. 2.11

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Freescale Semiconductor

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.3.2.4 SCI Alternative Control Register 1 (SCIACR1)

Module Base + 0x001a

RXEDGIE

BERRIE

BKDIE

Reset

= Unimplemented or Reserved

Figure 15-7. SCI Alternative Control Register 1 (SCIACR1)

Read: Anytime, if AMAP = 1

Write: Anytime, if AMAP = 1

Table 15-7. SCIACR1 Field Descriptions

Description

Field

Receive Input Active Edge Interrupt Enable — RXEDGIE enables the receive input active edge interrupt ﬂag,

RSEDGIE RXEDGIF, to generate interrupt requests.

0 RXEDGIF interrupt requests disabled

1 RXEDGIF interrupt requests enabled

Bit Error Interrupt Enable — BERRIE enables the bit error interrupt ﬂag, BERRIF, to generate interrupt

BERRIE

requests.

0 BERRIF interrupt requests disabled

1 BERRIF interrupt requests enabled

Break Detect Interrupt Enable — BKDIE enables the break detect interrupt ﬂag, BKDIF, to generate interrupt

BKDIE

requests.

0 BKDIF interrupt requests disabled

1 BKDIF interrupt requests enabled

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

681

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.3.2.5 SCI Alternative Control Register 2 (SCIACR2)

Module Base + 0x002a

BERRM1

BERRM0

BKDFE

Reset

= Unimplemented or Reserved

Figure 15-8. SCI Alternative Control Register 2 (SCIACR2)

Read: Anytime, if AMAP = 1

Write: Anytime, if AMAP = 1

Table 15-8. SCIACR2 Field Descriptions

Description

Field

2:1

Bit Error Mode — Those two bits determines the functionality of the bit error detect feature. See Table 15-9.

BERRM[1:0]

Break Detect Feature Enable — BKDFE enables the break detect circuitry.

0 Break detect circuit disabled

BKDFE

1 Break detect circuit enabled

Table 15-9. Bit Error Mode Coding

BERRM1

BERRM0

Function

Bit error detect circuit is disabled

Receive input sampling occurs during the 9th time tick of a transmitted bit

(refer to Figure 15-19)

Receive input sampling occurs during the 13th time tick of a transmitted bit

(refer to Figure 15-19)

Reserved

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.3.2.6 SCI Control Register 2 (SCICR2)

Module Base + 0x0003

TIE

TCIE

RIE

ILIE

RWU

SBK

Reset

Figure 15-9. SCI Control Register 2 (SCICR2)

Read: Anytime

Write: Anytime

Table 15-10. SCICR2 Field Descriptions

Description

Field

Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty ﬂag, TDRE, to generate

TIE

interrupt requests.

0 TDRE interrupt requests disabled

1 TDRE interrupt requests enabled

Transmission Complete Interrupt Enable Bit — TCIE enables the transmission complete ﬂag, TC, to generate

TCIE

interrupt requests.

0 TC interrupt requests disabled

1 TC interrupt requests enabled

RIE

Receiver Full Interrupt Enable Bit — RIE enables the receive data register full ﬂag, RDRF, or the overrun ﬂag,

OR, to generate interrupt requests.

0 RDRF and OR interrupt requests disabled

1 RDRF and OR interrupt requests enabled

ILIE

Idle Line Interrupt Enable Bit — ILIE enables the idle line ﬂag, IDLE, to generate interrupt requests.

0 IDLE interrupt requests disabled

1 IDLE interrupt requests enabled

Transmitter Enable Bit — TE enables the SCI transmitter and conﬁgures the TXD pin as being controlled by

the SCI. The TE bit can be used to queue an idle preamble.

0 Transmitter disabled

1 Transmitter enabled

Receiver Enable Bit — RE enables the SCI receiver.

0 Receiver disabled

1 Receiver enabled

Receiver Wakeup Bit — Standby state

RWU

0 Normal operation.

1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes

the receiver by automatically clearing RWU.

Send Break Bit — Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s

SBK

if BRK13 is set). Toggling implies clearing the SBK bit before the break character has ﬁnished transmitting. As

long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13

or 14 bits).

0 No break characters

1 Transmit break characters

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.3.2.7 SCI Status Register 1 (SCISR1)

The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also,

these registers can be polled by the MCU to check the status of these bits. The ﬂag-clearing procedures

require that the status register be read followed by a read or write to the SCI data register.It is permissible

to execute other instructions between the two steps as long as it does not compromise the handling of I/O,

but the order of operations is important for ﬂag clearing.

Module Base + 0x0004

TDRE

RDRF

IDLE

Reset

= Unimplemented or Reserved

Figure 15-10. SCI Status Register 1 (SCISR1)

Read: Anytime

Write: Has no meaning or effect

Table 15-11. SCISR1 Field Descriptions

Description

Field

Transmit Data Register Empty Flag — TDRE is set when the transmit shift register receives a byte from the

SCI data register. When TDRE is 1, the transmit data register (SCIDRH/L) is empty and can receive a new value

to transmit.Clear TDRE by reading SCI status register 1 (SCISR1), with TDRE set and then writing to SCI data

TDRE

0 No byte transferred to transmit shift register

1 Byte transferred to transmit shift register; transmit data register empty

Transmit Complete Flag — TC is set low when there is a transmission in progress or when a preamble or break

character is loaded. TC is set high when the TDRE ﬂag is set and no data, preamble, or break character is being

transmitted.When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1

(SCISR1) with TC set and then writing to SCI data register low (SCIDRL). TC is cleared automatically when data,

preamble, or break is queued and ready to be sent. TC is cleared in the event of a simultaneous set and clear of

the TC ﬂag (transmission not complete).

0 Transmission in progress

1 No transmission in progress

Receive Data Register Full Flag — RDRF is set when the data in the receive shift register transfers to the SCI

data register. Clear RDRF by reading SCI status register 1 (SCISR1) with RDRF set and then reading SCI data

RDRF

0 Data not available in SCI data register

1 Received data available in SCI data register

IDLE

Idle Line Flag — IDLE is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M =1) appear

on the receiver input. Once the IDLE ﬂag is cleared, a valid frame must again set the RDRF ﬂag before an idle

condition can set the IDLE ﬂag.Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then

reading SCI data register low (SCIDRL).

0 Receiver input is either active now or has never become active since the IDLE ﬂag was last cleared

1 Receiver input has become idle

Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE ﬂag.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Freescale Semiconductor

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

Table 15-11. SCISR1 Field Descriptions (continued)

Field

Description

Overrun Flag — OR is set when software fails to read the SCI data register before the receive shift register

receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the

second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected.

Clear OR by reading SCI status register 1 (SCISR1) with OR set and then reading SCI data register low

(SCIDRL).

0 No overrun

1 Overrun

Note: OR ﬂag may read back as set when RDRF ﬂag is clear. This may happen if the following sequence of

events occurs:

1. After the ﬁrst frame is received, read status register SCISR1 (returns RDRF set and OR ﬂag clear);

2. Receive second frame without reading the ﬁrst frame in the data register (the second frame is not

received and OR ﬂag is set);

3. Read data register SCIDRL (returns ﬁrst frame and clears RDRF ﬂag in the status register);

4. Read status register SCISR1 (returns RDRF clear and OR set).

Event 3 may be at exactly the same time as event 2 or any time after. When this happens, a dummy

SCIDRL read following event 4 will be required to clear the OR ﬂag if further frames are to be received.

Noise Flag — NF is set when the SCI detects noise on the receiver input. NF bit is set during the same cycle as

the RDRF ﬂag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1(SCISR1),

and then reading SCI data register low (SCIDRL).

0 No noise

1 Noise

Framing Error Flag — FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle

as the RDRF ﬂag but does not get set in the case of an overrun. FE inhibits further data reception until it is

cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register

low (SCIDRL).

0 No framing error

1 Framing error

Parity Error Flag — PF is set when the parity enable bit (PE) is set and the parity of the received data does not

match the parity type bit (PT). PF bit is set during the same cycle as the RDRF ﬂag but does not get set in the

case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low

(SCIDRL).

0 No parity error

1 Parity error

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

685

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.3.2.8 SCI Status Register 2 (SCISR2)

Module Base + 0x0005

RAF

AMAP

TXPOL

RXPOL

BRK13

TXDIR

Reset

= Unimplemented or Reserved

Figure 15-11. SCI Status Register 2 (SCISR2)

Read: Anytime

Write: Anytime

Table 15-12. SCISR2 Field Descriptions

Description

Field

Alternative Map — This bit controls which registers sharing the same address space are accessible. In the reset

condition the SCI behaves as previous versions. Setting AMAP=1 allows the access to another set of control and

status registers and hides the baud rate and SCI control Register 1.

AMAP

0 The registers labelled SCIBDH (0x000),SCIBDL (0x001), SCICR1 (0x0002) are accessible

1 The registers labelled SCIASR1 (0x000a),SCIACR1 (0x001a), SCIACR2 (0x0002a) are accessible

Transmit Polarity — This bit control the polarity of the transmitted data. In NRZ format, a one is represented by

a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA

format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal

polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for

inverted polarity.

TXPOL

0 Normal polarity

1 Inverted polarity

Receive Polarity — This bit control the polarity of the received data. In NRZ format, a one is represented by a

mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA

format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal

polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for

inverted polarity.

RXPOL

0 Normal polarity

1 Inverted polarity

Break Transmit Character Length — This bit determines whether the transmit break character is 10 or 11 bit

respectively 13 or 14 bits long. The detection of a framing error is not affected by this bit.

0 Break character is 10 or 11 bit long

BRK13

1 Break character is 13 or 14 bit long

Transmitter Pin Data Direction in Single-Wire Mode — This bit determines whether the TXD pin is going to

be used as an input or output, in the single-wire mode of operation. This bit is only relevant in the single-wire

mode of operation.

TXDIR

0 TXD pin to be used as an input in single-wire mode

1 TXD pin to be used as an output in single-wire mode

RAF

Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start

bit search. RAF is cleared when the receiver detects an idle character.

0 No reception in progress

1 Reception in progress

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.3.2.9 SCI Data Registers (SCIDRH, SCIDRL)

Module Base + 0x0006

Reset

= Unimplemented or Reserved

Figure 15-12. SCI Data Registers (SCIDRH)

Module Base + 0x0007

Reset

Figure 15-13. SCI Data Registers (SCIDRL)

Read: Anytime; reading accesses SCI receive data register

Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect

Table 15-13. SCIDRH and SCIDRL Field Descriptions

Field

Description

SCIDRH

Received Bit 8 — R8 is the ninth data bit received when the SCI is conﬁgured for 9-bit data format (M = 1).

Transmit Bit 8 — T8 is the ninth data bit transmitted when the SCI is conﬁgured for 9-bit data format (M = 1).

SCIDRH

SCIDRL

7:0

R7:R0 — Received bits seven through zero for 9-bit or 8-bit data formats

T7:T0 — Transmit bits seven through zero for 9-bit or 8-bit formats

R[7:0]

T[7:0]

NOTE

If the value of T8 is the same as in the previous transmission, T8 does not

have to be rewritten.The same value is transmitted until T8 is rewritten

In 8-bit data format, only SCI data register low (SCIDRL) needs to be

accessed.

When transmitting in 9-bit data format and using 8-bit write instructions,

write ﬁrst to SCI data register high (SCIDRH), then SCIDRL.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

687

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.4 Functional Description

This section provides a complete functional description of the SCI block, detailing the operation of the

design from the end user perspective in a number of subsections.

Figure 15-14 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial

communication between the CPU and remote devices, including other CPUs. The SCI transmitter and

receiver operate independently, although they use the same baud rate generator. The CPU monitors the

status of the SCI, writes the data to be transmitted, and processes received data.

IREN

SCI Data

Infrared

Receive

Decoder

Ir_RXD

RXD

SCRXD

Receive

Shift Register

RAF

IDLE

RDRF

IDLE

ILIE

RWU

Receive

and Wakeup

Control

LOOPS

RSRC

RIE

TIE

WAKE

ILT

Bus

Clock

Baud Rate

Generator

Data Format

Control

TDRE

SCI

Interrupt

Request

SBR12:SBR0

TCIE

Transmit

Control

RXEDGIE

÷16

LOOPS

SBK

Active Edge

Detect

RXEDGIF

BKDIF

RSRC

Transmit

Shift Register

Break Detect

RXD

BKDIE

SCI Data

BKDFE

LIN Transmit

Collision

Detect

BERRIF

BERRIE

SCTXD

R16XCLK

R32XCLK

BERRM[1:0]

Infrared

Transmit

Encoder

Ir_TXD

TXD

TNP[1:0]

IREN

Figure 15-14. Detailed SCI Block Diagram

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.4.1 Infrared Interface Submodule

This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow

pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer

speciﬁcation deﬁnes a half-duplex infrared communication link for exchange data. The full standard

includes data rates up to 16 Mbits/s. This design covers only data rates between 2.4 Kbits/s and 115.2

Kbits/s.

The infrared submodule consists of two major blocks: the transmit encoder and the receive decoder. The

SCI transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow pulse

for every zero bit. No pulse is transmitted for every one bit. When receiving data, the IR pulses should be

detected using an IR photo diode and transformed to CMOS levels by the IR receive decoder (external

from the MCU). The narrow pulses are then stretched by the infrared submodule to get back to a serial bit

stream to be received by the SCI.The polarity of transmitted pulses and expected receive pulses can be

inverted so that a direct connection can be made to external IrDA transceiver modules that uses active low

pulses.

The infrared submodule receives its clock sources from the SCI. One of these two clocks are selected in

the infrared submodule in order to generate either 3/16, 1/16, 1/32 or 1/4 narrow pulses during

transmission. The infrared block receives two clock sources from the SCI, R16XCLK and R32XCLK,

which are conﬁgured to generate the narrow pulse width during transmission. The R16XCLK and

R32XCLK are internal clocks with frequencies 16 and 32 times the baud rate respectively. Both

R16XCLK and R32XCLK clocks are used for transmitting data. The receive decoder uses only the

R16XCLK clock.

15.4.1.1 Infrared Transmit Encoder

The infrared transmit encoder converts serial bits of data from transmit shift register to the TXD pin. A

narrow pulse is transmitted for a zero bit and no pulse for a one bit. The narrow pulse is sent in the middle

of the bit with a duration of 1/32, 1/16, 3/16 or 1/4 of a bit time. A narrow high pulse is transmitted for a

zero bit when TXPOL is cleared, while a narrow low pulse is transmitted for a zero bit when TXPOL is set.

15.4.1.2 Infrared Receive Decoder

The infrared receive block converts data from the RXD pin to the receive shift register. A narrow pulse is

expected for each zero received and no pulse is expected for each one received. A narrow high pulse is

expected for a zero bit when RXPOL is cleared, while a narrow low pulse is expected for a zero bit when

RXPOL is set. This receive decoder meets the edge jitter requirement as deﬁned by the IrDA serial infrared

physical layer speciﬁcation.

15.4.2 LIN Support

This module provides some basic support for the LIN protocol. At ﬁrst this is a break detect circuitry

making it easier for the LIN software to distinguish a break character from an incoming data stream. As a

further addition is supports a collision detection at the bit level as well as cancelling pending transmissions.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.4.3 Data Format

The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data

format where zeroes are represented by light pulses and ones remain low. See Figure 15-15 below.

8-Bit Data Format

(Bit M in SCICR1 Clear)

Possible

Parity

Start

Bit

Start

Bit

Standard

SCI Data

STOP

Bit

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Infrared

SCI Data

9-Bit Data Format

(Bit M in SCICR1 Set)

POSSIBLE

PARITY

Bit

START

Bit

Start

Bit

Standard

SCI Data

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

STOP

Bit

Infrared

SCI Data

Figure 15-15. SCI Data Formats

Each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit.

Clearing the M bit in SCI control register 1 conﬁgures the SCI for 8-bit data characters. A frame with eight

data bits has a total of 10 bits. Setting the M bit conﬁgures the SCI for nine-bit data characters. A frame

with nine data bits has a total of 11 bits.

Table 15-14. Example of 8-Bit Data Formats

Start

Bit

Data

Bits

Address

Bits

Parity

Bits

Stop

Bit

The address bit identiﬁes the frame as an address

character. See Section 15.4.6.6, “Receiver Wakeup”.

When the SCI is conﬁgured for 9-bit data characters, the ninth data bit is the T8 bit in SCI data register

high (SCIDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it.

A frame with nine data bits has a total of 11 bits.

Table 15-15. Example of 9-Bit Data Formats

Start

Bit

Data

Bits

Address

Bits

Parity

Bits

Stop

Bit

The address bit identiﬁes the frame as an address

character. See Section 15.4.6.6, “Receiver Wakeup”.

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.4.4 Baud Rate Generation

A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the

transmitter. The value from 0 to 8191 written to the SBR12:SBR0 bits determines the bus clock divisor.

The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is

synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the

transmitter. The receiver has an acquisition rate of 16 samples per bit time.

Baud rate generation is subject to one source of error:

•

Integer division of the bus clock may not give the exact target frequency.

Table 15-16 lists some examples of achieving target baud rates with a bus clock frequency of 25 MHz.

When IREN = 0 then,

SCI baud rate = SCI bus clock / (16 * SCIBR[12:0])

Table 15-16. Baud Rates (Example: Bus Clock = 25 MHz)

Bits

SBR[12:0]

Receiver

Clock (Hz)

Transmitter

Clock (Hz)

Target

Baud Rate

Error

(%)

609,756.1

308,642.0

153,374.2

76,687.1

38,402.5

19,201.2

9600.6

38,109.8

19,290.1

9585.9

4792.9

2400.2

1200.1

600.0

38,400

19,200

9,600

4,800

2,400

1,200

600

.76

.47

.16

.15

.01

.00

163

326

651

1302

2604

5208

10417

14204

4800.0

300.0

300

2400.0

150.0

150

1760.1

110.0

110

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.4.5 Transmitter

Internal Bus

Bus

Clock

÷ 16

Baud Divider

SCI Data Registers

SBR12:SBR0

TXPOL

11-Bit Transmit Register

SCTXD

LOOP

CONTROL

To Receiver

Parity

Generation

LOOPS

RSRC

TIE

TDRE IRQ

TC IRQ

TDRE

Transmitter Control

TCIE

SBK

BERRM[1:0]

SCTXD

SCRXD

BERRIF

TCIE

Transmit

Collision Detect

BER IRQ

(From Receiver)

Figure 15-16. Transmitter Block Diagram

15.4.5.1 Transmitter Character Length

The SCI transmitter can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI

control register 1 (SCICR1) determines the length of data characters. When transmitting 9-bit data, bit T8

in SCI data register high (SCIDRH) is the ninth bit (bit 8).

15.4.5.2 Character Transmission

To transmit data, the MCU writes the data bits to the SCI data registers (SCIDRH/SCIDRL), which in turn

are transferred to the transmitter shift register. The transmit shift register then shifts a frame out through

the TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data

registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit

shift register.

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

The SCI also sets a ﬂag, the transmit data register empty ﬂag (TDRE), every time it transfers data from the

buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this ﬂag by

writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting

out the ﬁrst byte.

To initiate an SCI transmission:

1. Conﬁgure the SCI:

a) Select a baud rate. Write this value to the SCI baud registers (SCIBDH/L) to begin the baud

rate generator. Remember that the baud rate generator is disabled when the baud rate is zero.

Writing to the SCIBDH has no effect without also writing to SCIBDL.

b) Write to SCICR1 to conﬁgure word length, parity, and other conﬁguration bits

(LOOPS,RSRC,M,WAKE,ILT,PE,PT).

c) Enable the transmitter, interrupts, receive, and wake up as required, by writing to the SCICR2

be shifted out of the transmitter shift register.

2. Transmit Procedure for each byte:

a) Poll the TDRE ﬂag by reading the SCISR1 or responding to the TDRE interrupt. Keep in mind

that the TDRE bit resets to one.

b) If the TDRE ﬂag is set, write the data to be transmitted to SCIDRH/L, where the ninth bit is

written to the T8 bit in SCIDRH if the SCI is in 9-bit data format. A new transmission will not

result until the TDRE ﬂag has been cleared.

3. Repeat step 2 for each subsequent transmission.

NOTE

The TDRE ﬂag is set when the shift register is loaded with the next data to

be transmitted from SCIDRH/L, which happens, generally speaking, a little

over half-way through the stop bit of the previous frame. Speciﬁcally, this

transfer occurs 9/16ths of a bit time AFTER the start of the stop bit of the

previous frame.

Writing the TE bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic

1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from

the SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least

signiﬁcant bit position of the transmit shift register. A logic 1 stop bit goes into the most signiﬁcant bit

position.

Hardware supports odd or even parity. When parity is enabled, the most signiﬁcant bit (MSB) of the data

character is the parity bit.

The transmit data register empty ﬂag, TDRE, in SCI status register 1 (SCISR1) becomes set when the SCI

data register transfers a byte to the transmit shift register. The TDRE ﬂag indicates that the SCI data

control register 2 (SCICR2) is also set, the TDRE ﬂag generates a transmitter interrupt request.

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic

1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal

goes low and the transmit signal goes idle.

If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register

continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE

to go high after the last frame before clearing TE.

To separate messages with preambles with minimum idle line time, use this sequence between messages:

1. Write the last byte of the ﬁrst message to SCIDRH/L.

2. Wait for the TDRE ﬂag to go high, indicating the transfer of the last frame to the transmit shift

3. Queue a preamble by clearing and then setting the TE bit.

4. Write the ﬁrst byte of the second message to SCIDRH/L.

15.4.5.3 Break Characters

Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCICR2) loads the transmit shift

Break character length depends on the M bit in SCI control register 1 (SCICR1). As long as SBK is at logic

1, transmitter logic continuously loads break characters into the transmit shift register. After software

clears the SBK bit, the shift register ﬁnishes transmitting the last break character and then transmits at least

one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit

of the next frame.

The SCI recognizes a break character when there are 10 or 11(M = 0 or M = 1) consecutive zero received.

Depending if the break detect feature is enabled or not receiving a break character has these effects on SCI

registers.

If the break detect feature is disabled (BKDFE = 0):

•

Sets the framing error flag, FE

Sets the receive data register full flag, RDRF

Clears the SCI data registers (SCIDRH/L)

May set the overrun flag, OR, noise flag, NF, parity error flag, PE, or the receiver active flag, RAF

(see 3.4.4 and 3.4.5 SCI Status Register 1 and 2)

If the break detect feature is enabled (BKDFE = 1) there are two scenarios

The break is detected right from a start bit or is detected during a byte reception.

•

Sets the break detect interrupt flag, BLDIF

Does not change the data register full flag, RDRF or overrun flag OR

Does not change the framing error flag FE, parity error flag PE.

Does not clear the SCI data registers (SCIDRH/L)

May set noise flag NF, or receiver active flag RAF.

1. A Break character in this context are either 10 or 11 consecutive zero received bits

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Figure 15-17 shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit,

while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there

will be no byte transferred to the receive buffer and the RDRF ﬂag will not be modiﬁed. Also no framing

error or parity error will be ﬂagged from this transfer. In RXD_2 case, however the break signal starts later

during the transmission. At the expected stop bit position the byte received so far will be transferred to the

receive buffer, the receive data register full ﬂag will be set, a framing error and if enabled and appropriate

a parity error will be set. Once the break is detected the BRKDIF ﬂag will be set.

Start Bit Position

Stop Bit Position

BRKDIF = 1

RXD_1

. . .

Zero Bit Counter

FE = 1

BRKDIF = 1

RXD_2

. . .

Zero Bit Counter

Figure 15-17. Break Detection if BRKDFE = 1 (M = 0)

15.4.5.4 Idle Characters

An idle character (or preamble) contains all logic 1s and has no start, stop, or parity bit. Idle character

length depends on the M bit in SCI control register 1 (SCICR1). The preamble is a synchronizing idle

character that begins the ﬁrst transmission initiated after writing the TE bit from 0 to 1.

If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the

transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle

character to be sent after the frame currently being transmitted.

NOTE

When queueing an idle character, return the TE bit to logic 1 before the stop

bit of the current frame shifts out through the TXD pin. Setting TE after the

stop bit appears on TXD causes data previously written to the SCI data

TDRE ﬂag is set and immediately before writing the next byte to the SCI

data register.

If the TE bit is clear and the transmission is complete, the SCI is not the

master of the TXD pin

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.4.5.5 LIN Transmit Collision Detection

This module allows to check for collisions on the LIN bus.

LIN Physical Interface

Synchronizer Stage

Receive Shift

Compare

RXD Pin

Bit Error

LIN Bus

Bus Clock

Sample

Point

Transmit Shift

TXD Pin

Figure 15-18. Collision Detect Principle

If the bit error circuit is enabled (BERRM[1:0] = 0:1 or = 1:0]), the error detect circuit will compare the

transmitted and the received data stream at a point in time and ﬂag any mismatch. The timing checks run

when transmitter is active (not idle). As soon as a mismatch between the transmitted data and the received

data is detected the following happens:

•

The next bit transmitted will have a high level (TXPOL = 0) or low level (TXPOL = 1)

The transmission is aborted and the byte in transmit buffer is discarded.

the transmit data register empty and the transmission complete flag will be set

The bit error interrupt flag, BERRIF, will be set.

No further transmissions will take place until the BERRIF is cleared.

10 11 12 13 14 15

Output Transmit

Shift Register

Input Receive

Shift Register

BERRM[1:0] = 0:1

BERRM[1:0] = 1:1

Compare Sample Points

Figure 15-19. Timing Diagram Bit Error Detection

If the bit error detect feature is disabled, the bit error interrupt ﬂag is cleared.

NOTE

The RXPOL and TXPOL bit should be set the same when transmission

collision detect feature is enabled, otherwise the bit error interrupt ﬂag may

be set incorrectly.

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.4.6 Receiver

Internal Bus

SBR12:SBR0

SCI Data Register

Bus

Clock

Baud Divider

11-Bit Receive Shift Register

RXPOL

Data

Recovery

SCRXD

Loop

Control

From TXD Pin

or Transmitter

RAF

LOOPS

RSRC

WAKE

ILT

RWU

Wakeup

Logic

Parity

Checking

Idle IRQ

IDLE

ILIE

RDRF/OR

IRQ

BRKDFE

RDRF

RIE

Break

Detect Logic

BRKDIF

BRKDIE

Break IRQ

Active Edge

Detect Logic

RXEDGIF

RXEDGIE

RX Active Edge IRQ

Figure 15-20. SCI Receiver Block Diagram

15.4.6.1 Receiver Character Length

The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI

control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in

SCI data register high (SCIDRH) is the ninth bit (bit 8).

15.4.6.2 Character Reception

During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register

is the read-only buffer between the internal data bus and the receive shift register.

After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the

SCI data register. The receive data register full ﬂag, RDRF, in SCI status register 1 (SCISR1) becomes set,

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control

15.4.6.3 Data Sampling

The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust

for baud rate mismatch, the RT clock (see Figure 15-21) is re-synchronized:

•

After every start bit

After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit

samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and

RT10 samples returns a valid logic 0)

To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic

1s.When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.

Start Bit

LSB

RXD

Samples

Start Bit

Qualiﬁcation

Start Bit

Veriﬁcation

Data

Sampling

RT Clock

RT CLock Count

Reset RT Clock

Figure 15-21. Receiver Data Sampling

To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.

Figure 15-17 summarizes the results of the start bit veriﬁcation samples.

Table 15-17. Start Bit Veriﬁcation

RT3, RT5, and RT7 Samples

Start Bit Veriﬁcation

Noise Flag

000

001

010

011

100

101

110

111

Yes

If start bit veriﬁcation is not successful, the RT clock is reset and a new search for a start bit begins.

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To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and

RT10. Table 15-18 summarizes the results of the data bit samples.

Table 15-18. Data Bit Recovery

RT8, RT9, and RT10 Samples

Data Bit Determination

Noise Flag

000

001

010

011

100

101

110

111

NOTE

The RT8, RT9, and RT10 samples do not affect start bit veriﬁcation. If any

or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a

successful start bit veriﬁcation, the noise ﬂag (NF) is set and the receiver

assumes that the bit is a start bit (logic 0).

To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 15-19

summarizes the results of the stop bit samples.

Table 15-19. Stop Bit Recovery

RT8, RT9, and RT10 Samples

Framing Error Flag

Noise Flag

000

001

010

011

100

101

110

111

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In Figure 15-22 the veriﬁcation samples RT3 and RT5 determine that the ﬁrst low detected was noise and

not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise ﬂag

is not set because the noise occurred before the start bit was found.

Start Bit

LSB

RXD

Samples

RT Clock

RT Clock Count

Reset RT Clock

Figure 15-22. Start Bit Search Example 1

In Figure 15-23, veriﬁcation sample at RT3 is high. The RT3 sample sets the noise ﬂag. Although the

perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data

recovery is successful.

Perceived Start Bit

Actual Start Bit

LSB

RXD

Samples

RT Clock

RT Clock Count

Reset RT Clock

Figure 15-23. Start Bit Search Example 2

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In Figure 15-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample

at RT5 is high. The RT5 sample sets the noise ﬂag. Although this is a worst-case misalignment of perceived

bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.

Perceived Start Bit

Actual Start Bit

LSB

RXD

Samples

RT Clock

RT Clock Count

Reset RT Clock

Figure 15-24. Start Bit Search Example 3

Figure 15-25 shows the effect of noise early in the start bit time. Although this noise does not affect proper

synchronization with the start bit time, it does set the noise ﬂag.

Perceived and Actual Start Bit

LSB

RXD

Samples

RT Clock

RT Clock Count

Reset RT Clock

Figure 15-25. Start Bit Search Example 4

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Figure 15-26 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample

after the reset is low but is not preceded by three high samples that would qualify as a falling edge.

Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may

set the framing error ﬂag.

Start Bit

LSB

No Start Bit Found

RXD

Samples

RT Clock

RT Clock Count

Reset RT Clock

Figure 15-26. Start Bit Search Example 5

In Figure 15-27, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the

noise ﬂag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are

ignored.

Start Bit

LSB

RXD

Samples

RT Clock

RT Clock Count

Reset RT Clock

Figure 15-27. Start Bit Search Example 6

15.4.6.4 Framing Errors

If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it

sets the framing error ﬂag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE ﬂag

because a break character has no stop bit. The FE ﬂag is set at the same time that the RDRF ﬂag is set.

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.4.6.5 Baud Rate Tolerance

A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated

bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside

the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical

values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the

RT8, RT9, and RT10 stop bit samples are a logic zero.

As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge

within the frame. Re synchronization within frames will correct a misalignment between transmitter bit

times and receiver bit times.

15.4.6.5.1

Slow Data Tolerance

Figure 15-28 shows how much a slow received frame can be misaligned without causing a noise error or

a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data

samples at RT8, RT9, and RT10.

MSB

Stop

Receiver

RT Clock

Data

Samples

Figure 15-28. Slow Data

Let’s take RTr as receiver RT clock and RTt as transmitter RT clock.

For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles +7 RTr cycles = 151 RTr cycles

to start data sampling of the stop bit.

With the misaligned character shown in Figure 15-28, the receiver counts 151 RTr cycles at the point when

the count of the transmitting device is 9 bit times x 16 RTt cycles = 144 RTt cycles.

The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data

character with no errors is:

((151 – 144) / 151) x 100 = 4.63%

For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 7 RTr cycles = 167 RTr cycles

to start data sampling of the stop bit.

With the misaligned character shown in Figure 15-28, the receiver counts 167 RTr cycles at the point when

the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles.

The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit

character with no errors is:

((167 – 160) / 167) X 100 = 4.19%

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.4.6.5.2

Fast Data Tolerance

Figure 15-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10

instead of RT16 but is still sampled at RT8, RT9, and RT10.

Stop

Idle or Next Frame

Receiver

RT Clock

Data

Samples

Figure 15-29. Fast Data

For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles + 10 RTr cycles = 154 RTr cycles

to ﬁnish data sampling of the stop bit.

With the misaligned character shown in Figure 15-29, the receiver counts 154 RTr cycles at the point when

the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles.

The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit

character with no errors is:

((160 – 154) / 160) x 100 = 3.75%

For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 10 RTr cycles = 170 RTr cycles

to ﬁnish data sampling of the stop bit.

With the misaligned character shown in Figure 15-29, the receiver counts 170 RTr cycles at the point when

the count of the transmitting device is 11 bit times x 16 RTt cycles = 176 RTt cycles.

The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit

character with no errors is:

((176 – 170) /176) x 100 = 3.40%

15.4.6.6 Receiver Wakeup

To enable the SCI to ignore transmissions intended only for other receivers in multiple-receiver systems,

the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register 2

(SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will

still load the receive data into the SCIDRH/L registers, but it will not set the RDRF ﬂag.

The transmitting device can address messages to selected receivers by including addressing information in

the initial frame or frames of each message.

The WAKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby

state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark

wakeup.

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.4.6.6.1

Idle Input line Wakeup (WAKE = 0)

In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The

initial frame or frames of every message contain addressing information. All receivers evaluate the

addressing information, and receivers for which the message is addressed process the frames that follow.

Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The

RWU bit remains set and the receiver remains on standby until another idle character appears on the RXD

pin.

Idle line wakeup requires that messages be separated by at least one idle character and that no message

contains idle characters.

The idle character that wakes a receiver does not set the receiver idle bit, IDLE, or the receive data register

full ﬂag, RDRF.

The idle line type bit, ILT, determines whether the receiver begins counting logic 1s as idle character bits

after the start bit or after the stop bit. ILT is in SCI control register 1 (SCICR1).

15.4.6.6.2

Address Mark Wakeup (WAKE = 1)

In this wakeup method, a logic 1 in the most signiﬁcant bit (MSB) position of a frame clears the RWU bit

and wakes up the SCI. The logic 1 in the MSB position marks a frame as an address frame that contains

addressing information. All receivers evaluate the addressing information, and the receivers for which the

message is addressed process the frames that follow.Any receiver for which a message is not addressed can

set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on

standby until another address frame appears on the RXD pin.

The logic 1 MSB of an address frame clears the receiver’s RWU bit before the stop bit is received and sets

the RDRF ﬂag.

Address mark wakeup allows messages to contain idle characters but requires that the MSB be reserved

for use in address frames.

NOTE

With the WAKE bit clear, setting the RWU bit after the RXD pin has been

idle can cause the receiver to wake up immediately.

15.4.7 Single-Wire Operation

Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is

disconnected from the SCI. The SCI uses the TXD pin for both receiving and transmitting.

Transmitter

TXD

Receiver

RXD

Figure 15-30. Single-Wire Operation (LOOPS = 1, RSRC = 1)

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Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control

the RSRC bit connects the TXD pin to the receiver. Both the transmitter and receiver must be enabled

(TE = 1 and RE = 1).The TXDIR bit (SCISR2[1]) determines whether the TXD pin is going to be used as

an input (TXDIR = 0) or an output (TXDIR = 1) in this mode of operation.

NOTE

In single-wire operation data from the TXD pin is inverted if RXPOL is set.

15.4.8 Loop Operation

In loop operation the transmitter output goes to the receiver input. The RXD pin is disconnected from the

SCI.

Transmitter

TXD

Receiver

RXD

Figure 15-31. Loop Operation (LOOPS = 1, RSRC = 0)

Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1

(SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Clearing the RSRC

bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled

(TE = 1 and RE = 1).

NOTE

In loop operation data from the transmitter is not recognized by the receiver

if RXPOL and TXPOL are not the same.

15.5 Initialization/Application Information

15.5.1 Reset Initialization

See Section 15.3.2, “Register Descriptions”.

15.5.2 Modes of Operation

15.5.2.1 Run Mode

Normal mode of operation.

To initialize a SCI transmission, see Section 15.4.5.2, “Character Transmission”.

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.5.2.2 Wait Mode

SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1

(SCICR1).

•

If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode.

If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation

state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver

enable bit, RE, or the transmitter enable bit, TE.

If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The

transmission or reception resumes when either an internal or external interrupt brings the CPU out

of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and

resets the SCI.

15.5.2.3 Stop Mode

The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not

affect the SCI register states, but the SCI bus clock will be disabled. The SCI operation resumes from

where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset

aborts any transmission or reception in progress and resets the SCI.

The receive input active edge detect circuit is still active in stop mode. An active edge on the receive input

can be used to bring the CPU out of stop mode.

15.5.3 Interrupt Operation

This section describes the interrupt originated by the SCI block.The MCU must service the interrupt

requests. Table 15-20 lists the eight interrupt sources of the SCI.

Table 15-20. SCI Interrupt Sources

Interrupt

Source

Local Enable

Description

TDRE

SCISR1[7]

TIE

Active high level. Indicates that a byte was transferred from SCIDRH/L to the

transmit shift register.

SCISR1[6]

SCISR1[5]

TCIE

RIE

Active high level. Indicates that a transmit is complete.

RDRF

Active high level. The RDRF interrupt indicates that received data is available

in the SCI data register.

SCISR1[3]

SCISR1[4]

Active high level. This interrupt indicates that an overrun condition has occurred.

Active high level. Indicates that receiver input has become idle.

IDLE

ILIE

RXEDGIF SCIASR1[7]

RXEDGIE

Active high level. Indicates that an active edge (falling for RXPOL = 0, rising for

RXPOL = 1) was detected.

BERRIF SCIASR1[1]

BERRIE

BRKDIE

Active high level. Indicates that a mismatch between transmitted and received data

in a single wire application has happened.

BKDIF

SCIASR1[0]

Active high level. Indicates that a break character has been received.

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15.5.3.1 Description of Interrupt Operation

The SCI only originates interrupt requests. The following is a description of how the SCI makes a request

and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are

chip dependent. The SCI only has a single interrupt line (SCI Interrupt Signal, active high operation) and

all the following interrupts, when generated, are ORed together and issued through that port.

15.5.3.1.1

TDRE Description

The TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCI

data register. A TDRE interrupt indicates that the transmit data register (SCIDRH/L) is empty and that a

new byte can be written to the SCIDRH/L for transmission.Clear TDRE by reading SCI status register 1

with TDRE set and then writing to SCI data register low (SCIDRL).

15.5.3.1.2

TC Description

The TC interrupt is set by the SCI when a transmission has been completed. Transmission is completed

when all bits including the stop bit (if transmitted) have been shifted out and no data is queued to be

transmitted. No stop bit is transmitted when sending a break character and the TC ﬂag is set (providing

there is no more data queued for transmission) when the break character has been shifted out. A TC

interrupt indicates that there is no transmission in progress. TC is set high when the TDRE ﬂag is set and

no data, preamble, or break character is being transmitted. When TC is set, the TXD pin becomes idle

(logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data

be sent.

15.5.3.1.3

RDRF Description

The RDRF interrupt is set when the data in the receive shift register transfers to the SCI data register. A

RDRF interrupt indicates that the received data has been transferred to the SCI data register and that the

byte can now be read by the MCU. The RDRF interrupt is cleared by reading the SCI status register one

(SCISR1) and then reading SCI data register low (SCIDRL).

15.5.3.1.4

OR Description

The OR interrupt is set when software fails to read the SCI data register before the receive shift register

receives the next frame. The newly acquired data in the shift register will be lost in this case, but the data

already in the SCI data registers is not affected. The OR interrupt is cleared by reading the SCI status

15.5.3.1.5

IDLE Description

The IDLE interrupt is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M = 1)

appear on the receiver input. Once the IDLE is cleared, a valid frame must again set the RDRF ﬂag before

an idle condition can set the IDLE ﬂag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE

set and then reading SCI data register low (SCIDRL).

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Chapter 15 Serial Communication Interface (S12MC9S12XDP512V5)

15.5.3.1.6

RXEDGIF Description

The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the

RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1.

15.5.3.1.7

BERRIF Description

The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single

wire application like LIN was detected. Clear BERRIF by writing a “1” to the SCIASR1 SCI alternative

status register 1. This ﬂag is also cleared if the bit error detect feature is disabled.

15.5.3.1.8

BKDIF Description

The BKDIF interrupt is set when a break signal was received. Clear BKDIF by writing a “1” to the

SCIASR1 SCI alternative status register 1. This ﬂag is also cleared if break detect feature is disabled.

15.5.4 Recovery from Wait Mode

The SCI interrupt request can be used to bring the CPU out of wait mode.

15.5.5 Recovery from Stop Mode

An active edge on the receive input can be used to bring the CPU out of stop mode.

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Chapter 16

Serial Peripheral Interface (S12SPIV4)

16.1 Introduction

The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral

devices. Software can poll the SPI status ﬂags or the SPI operation can be interrupt driven.

16.1.1 Features

The MC9S12XDP512 includes these distinctive features:

•

Master mode and slave mode

Bidirectional mode

Slave select output

Mode fault error ﬂag with CPU interrupt capability

Double-buffered data register

Serial clock with programmable polarity and phase

Control of SPI operation during wait mode

16.1.2 Modes of Operation

The SPI functions in three modes: run, wait, and stop.

•

Run mode

This is the basic mode of operation.

Wait mode

•

SPI operation in wait mode is a conﬁgurable low power mode, controlled by the SPISWAI bit

located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in

run mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock

generation turned off. If the SPI is conﬁgured as a master, any transmission in progress stops, but

is resumed after CPU goes into run mode. If the SPI is conﬁgured as a slave, reception and

transmission of a byte continues, so that the slave stays synchronized to the master.

•

Stop mode

The SPI is inactive in stop mode for reduced power consumption. If the SPI is conﬁgured as a

master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI

is conﬁgured as a slave, reception and transmission of a byte continues, so that the slave stays

synchronized to the master.

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

This is a high level description only, detailed descriptions of operating modes are contained in

Section 16.4.7, “Low Power Mode Options”.

16.1.3 Block Diagram

Figure 16-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control and

data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.

SPI

SPI Control Register 1

BIDIROE

SPI Control Register 2

SPC0

SPI Status Register

SPIF

Slave

Control

CPOL

CPHA

MOSI

MODF SPTEF

Phase +

Polarity

Control

SCK In

Interrupt Control

Slave Baud Rate

SPI

Interrupt

Request

Master Baud Rate

Phase +

Polarity

Control

SCK Out

Port

Control

Logic

SCK

Baud Rate Generator

Counter

Master

Control

Bus Clock

Baud Rate

Prescaler

Clock Select

Shift

Clock

Sample

Clock

SPPR

SPR

Shifter

LSBFE=0

LSBFE=1

SPI Baud Rate Register

Data In

LSBFE=1

MSB

SPI Data Register

LSB

LSBFE=0

Data Out

LSBFE=0

LSBFE=1

Figure 16-1. SPI Block Diagram

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

16.2 External Signal Description

This section lists the name and description of all ports including inputs and outputs that do, or may, connect

off chip. The MC9S12XDP512 module has a total of four external pins.

16.2.1 MOSI — Master Out/Slave In Pin

This pin is used to transmit data out of the SPI module when it is conﬁgured as a master and receive data

when it is conﬁgured as slave.

16.2.2 MISO — Master In/Slave Out Pin

This pin is used to transmit data out of the SPI module when it is conﬁgured as a slave and receive data

when it is conﬁgured as master.

16.2.3 SS — Slave Select Pin

This pin is used to output the select signal from the SPI module to another peripheral with which a data

transfer is to take place when it is conﬁgured as a master and it is used as an input to receive the slave select

signal when the SPI is conﬁgured as slave.

16.2.4 SCK — Serial Clock Pin

In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.

16.3 Memory Map and Register Deﬁnition

This section provides a detailed description of address space and registers used by the SPI.

The memory map for the MC9S12XDP512 is given in Table 16-1. The address listed for each register is

the sum of a base address and an address offset. The base address is deﬁned at the SoC level and the address

offset is deﬁned at the module level. Reads from the reserved bits return zeros and writes to the reserved

bits have no effect.

16.3.1 Module Memory Map

Table 16-1. MC9S12XDP512V4 Memory Map

Address

Use

Access

0x___0

0x___1

0x___2

0x___3

0x___4

0x___5

0x___6

0x___7

SPI Control Register 1 (SPICR1)

SPI Control Register 2 (SPICR2)

SPI Baud Rate Register (SPIBR)

SPI Status Register (SPISR)

Reserved

Read / Write

Read

2 3

—

SPI Data Register (SPIDR)

Reserved

Read / Write

2 3

—

2 3

Reserved

—

Certain bits are non-writable.

Writes to this register are ignored.

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

Reading from this register returns all zeros.

16.3.2 Register Descriptions

This section consists of register descriptions in address order. Each description includes a standard register

diagram with an associated ﬁgure number. Details of register bit and ﬁeld function follow the register

diagrams, in bit order.

Name

Bit 7

SPIE

SPE

SPTIE

CPHA

Bit 0

0x___0

SPICR1

MSTR

CPOL

SSOE

LSBFE

0x___1

SPICR2

MODFEN

BIDIROE

SPISWAI

SPC0

0x___2

SPIBR

SPPR2

SPPR1

SPTEF

SPPR0

MODF

SPR2

SPR1

SPR0

0x___3

SPISR

SPIF

0x___4

Reserved

0x___5

SPIDR

Bit 7

Bit 0

0x___6

Reserved

0x___7

Reserved

= Unimplemented or Reserved

Figure 16-2. SPI Register Summary

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

16.3.2.1 SPI Control Register 1 (SPICR1)

Module Base +0x___0

SPIE

SPE

SPTIE

MSTR

CPOL

CPHA

SSOE

LSBFE

Reset

Figure 16-3. SPI Control Register 1 (SPICR1)

Read: Anytime

Write: Anytime

Table 16-2. SPICR1 Field Descriptions

Description

Field

SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status ﬂag is set.

SPIE

0 SPI interrupts disabled.

1 SPI interrupts enabled.

SPE

SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system

functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset.

0 SPI disabled (lower power consumption).

1 SPI enabled, port pins are dedicated to SPI functions.

SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF ﬂag is set.

0 SPTEF interrupt disabled.

SPTIE

1 SPTEF interrupt enabled.

SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode.

Switching the SPI from master to slave or vice versa forces the SPI system into idle state.

0 SPI is in slave mode.

MSTR

1 SPI is in master mode.

SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI

modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a

transmission in progress and force the SPI system into idle state.

CPOL

0 Active-high clocks selected. In idle state SCK is low.

1 Active-low clocks selected. In idle state SCK is high.

SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will

abort a transmission in progress and force the SPI system into idle state.

CPHA

0 Sampling of data occurs at odd edges (1,3,5,...,15) of the SCK clock.

1 Sampling of data occurs at even edges (2,4,6,...,16) of the SCK clock.

Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by

asserting the SSOE as shown in Table 16-3. In master mode, a change of this bit will abort a transmission in

progress and force the SPI system into idle state.

SSOE

LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and

writes of the data register always have the MSB in bit 7. In master mode, a change of this bit will abort a

transmission in progress and force the SPI system into idle state.

LSBFE

0 Data is transferred most signiﬁcant bit ﬁrst.

1 Data is transferred least signiﬁcant bit ﬁrst.

MC9S12XDP512 Data Sheet, Rev. 2.11

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

Table 16-3. SS Input / Output Selection

MODFEN

SSOE

Master Mode

Slave Mode

SS not used by SPI

SS input

SS input with MODF feature

SS is slave select output

16.3.2.2 SPI Control Register 2 (SPICR2)

Module Base +0x___1

MODFEN

BIDIROE

SPISWAI

SPC0

Reset

= Unimplemented or Reserved

Figure 16-4. SPI Control Register 2 (SPICR2)

Read: Anytime

Write: Anytime; writes to the reserved bits have no effect

Table 16-4. SPICR2 Field Descriptions

Field

Description

Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and

MODFEN MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an

input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin

conﬁguration, refer to Table 16-5. In master mode, a change of this bit will abort a transmission in progress and

force the SPI system into idle state.

0 SS port pin is not used by the SPI.

1 SS port pin with MODF feature.

Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer

of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output

buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0

set, a change of this bit will abort a transmission in progress and force the SPI into idle state.

0 Output buffer disabled.

BIDIROE

1 Output buffer enabled.

SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.

0 SPI clock operates normally in wait mode.

SPISWAI

1 Stop SPI clock generation when in wait mode.

Serial Pin Control Bit 0 — This bit enables bidirectional pin conﬁgurations as shown in Table 16-5. In master

SPC0

mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state.

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

Table 16-5. Bidirectional Pin Conﬁgurations

Pin Mode

SPC0

BIDIROE

MISO

MOSI

Master Mode of Operation

Normal

Master In

Master Out

Master In

Bidirectional

MISO not used by SPI

Master I/O

Slave Mode of Operation

Normal

Slave Out

Slave In

Bidirectional

MOSI not used by SPI

Slave I/O

16.3.2.3 SPI Baud Rate Register (SPIBR)

Module Base +0x___2

SPPR2

SPPR1

SPPR0

SPR2

SPR1

SPR0

Reset

= Unimplemented or Reserved

Figure 16-5. SPI Baud Rate Register (SPIBR)

Read: Anytime

Write: Anytime; writes to the reserved bits have no effect

Table 16-6. SPIBR Field Descriptions

Field

Description

SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in T a ble 16-7. In master

6–4

SPPR[2:0] mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state.

2–0

SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in Table 16-7. In master mode,

SPR[2:0]

a change of these bits will abort a transmission in progress and force the SPI system into idle state.

The baud rate divisor equation is as follows:

(SPR + 1)

BaudRateDivisor = (SPPR + 1) • 2

Eqn. 16-1

Eqn. 16-2

The baud rate can be calculated with the following equation:

Baud Rate = BusClock / BaudRateDivisor

NOTE

For maximum allowed baud rates, please refer to the SPI Electrical

Speciﬁcation in the Electricals chapter of this data sheet.

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

Table 16-7. Example SPI Baud Rate Selection (25 MHz Bus Clock)

Baud Rate

Divisor

SPPR2

SPPR1

SPPR0

SPR2

SPR1

SPR0

Baud Rate

12.5 MHz

6.25 MHz

3.125 MHz

1.5625 MHz

781.25 kHz

390.63 kHz

195.31 kHz

97.66 kHz

6.25 MHz

128

256

3.125 MHz

1.5625 MHz

781.25 kHz

390.63 kHz

195.31 kHz

97.66 kHz

48.83 kHz

4.16667 MHz

2.08333 MHz

1.04167 MHz

520.83 kHz

260.42 kHz

130.21 kHz

65.10 kHz

32.55 kHz

3.125 MHz

1.5625 MHz

781.25 kHz

390.63 kHz

195.31 kHz

97.66 kHz

48.83 kHz

24.41 kHz

2.5 MHz

128

256

512

192

384

768

128

256

512

1024

1.25 MHz

625 kHz

312.5 kHz

156.25 kHz

78.13 kHz

39.06 kHz

160

320

640

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

Table 16-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (continued)

Baud Rate

Divisor

SPPR2

SPPR1

SPPR0

SPR2

SPR1

SPR0

Baud Rate

1280

19.53 kHz

2.08333 MHz

1.04167 MHz

520.83 kHz

260.42 kHz

130.21 kHz

65.10 kHz

192

384

768

1536

32.55 kHz

16.28 kHz

1.78571 MHz

892.86 kHz

446.43 kHz

223.21 kHz

111.61 kHz

55.80 kHz

112

224

448

896

1792

27.90 kHz

13.95 kHz

1.5625 MHz

781.25 kHz

390.63 kHz

195.31 kHz

97.66 kHz

128

256

512

1024

2048

48.83 kHz

24.41 kHz

12.21 kHz

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

16.3.2.4 SPI Status Register (SPISR)

Module Base +0x___3

SPIF

SPTEF

MODF

Reset

= Unimplemented or Reserved

Figure 16-6. SPI Status Register (SPISR)

Read: Anytime

Write: Has no effect

Table 16-8. SPISR Field Descriptions

Description

Field

SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI data register.

SPIF

This bit is cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI data

0 Transfer not yet complete.

1 New data copied to SPIDR.

SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. To clear

this bit and place data into the transmit data register, SPISR must be read with SPTEF = 1, followed by a write

to SPIDR. Any write to the SPI data register without reading SPTEF = 1, is effectively ignored.

0 SPI data register not empty.

SPTEF

1 SPI data register empty.

Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is conﬁgured as a master and mode

fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in

Section 16.3.2.2, “SPI Control Register 2 (SPICR2)”. The ﬂag is cleared automatically by a read of the SPI status

0 Mode fault has not occurred.

MODF

1 Mode fault has occurred.

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

16.3.2.5 SPI Data Register (SPIDR)

Module Base +0x___5

Bit 7

Bit 0

Reset

Figure 16-7. SPI Data Register (SPIDR)

Read: Anytime; normally read only when SPIF is set

Write: Anytime

The SPI data register is both the input and output register for SPI data. A write to this register

allows a data byte to be queued and transmitted. For an SPI conﬁgured as a master, a queued data

byte is transmitted immediately after the previous transmission has completed. The SPI transmitter

empty ﬂag SPTEF in the SPISR register indicates when the SPI data register is ready to accept new

data.

Received data in the SPIDR is valid when SPIF is set.

If SPIF is cleared and a byte has been received, the received byte is transferred from the receive

shift register to the SPIDR and SPIF is set.

If SPIF is set and not serviced, and a second byte has been received, the second received byte is

kept as valid byte in the receive shift register until the start of another transmission. The byte in the

SPIDR does not change.

If SPIF is set and a valid byte is in the receive shift register, and SPIF is serviced before the start of

a third transmission, the byte in the receive shift register is transferred into the SPIDR and SPIF

remains set (see Figure 16-8).

If SPIF is set and a valid byte is in the receive shift register, and SPIF is serviced after the start of

a third transmission, the byte in the receive shift register has become invalid and is not transferred

into the SPIDR (see Figure 16-9).

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

Data A Received

Data B Received

Data C Received

SPIF Serviced

Receive Shift Register

Data B

Data A

Data C

SPIF

Data C

SPI Data Register

Data B

Data A

= Unspeciﬁed

= Reception in progress

Figure 16-8. Reception with SPIF Serviced in Time

Data A Received

Data B Received

Data C Received

Data B Lost

SPIF Serviced

Receive Shift Register

SPIF

Data B

Data C

Data A

SPI Data Register

Data A

= Unspeciﬁed

= Reception in progress

Figure 16-9. Reception with SPIF Serviced too Late

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

16.4 Functional Description

The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral

devices. Software can poll the SPI status ﬂags or SPI operation can be interrupt driven.

The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set,

the four associated SPI port pins are dedicated to the SPI function as:

•

Slave select (SS)

Serial clock (SCK)

Master out/slave in (MOSI)

Master in/slave out (MISO)

The main element of the SPI system is the SPI data register. The 8-bit data register in the master and the

8-bit data register in the slave are linked by the MOSI and MISO pins to form a distributed 16-bit register.

When a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the

S-clock from the master, so data is exchanged between the master and the slave. Data written to the master

SPI data register becomes the output data for the slave, and data read from the master SPI data register after

a transfer operation is the input data from the slave.

A read of SPISR with SPTEF = 1 followed by a write to SPIDR puts data into the transmit data register.

When a transfer is complete and SPIF is cleared, received data is moved into the receive data register. This

8-bit data register acts as the SPI receive data register for reads and as the SPI transmit data register for

writes. A single SPI register address is used for reading data from the read data buffer and for writing data

to the transmit data register.

The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI control register 1

(SPICR1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply

selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally

different protocols by sampling data on odd numbered SCK edges or on even numbered SCK edges (see

Section 16.4.3, “Transmission Formats”).

The SPI can be conﬁgured to operate as a master or as a slave. When the MSTR bit in SPI control register1

is set, master mode is selected, when the MSTR bit is clear, slave mode is selected.

NOTE

A change of CPOL or MSTR bit while there is a received byte pending in

the receive shift register will destroy the received byte and must be avoided.

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

16.4.1 Master Mode

The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate

transmissions. A transmission begins by writing to the master SPI data register. If the shift register is

empty, the byte immediately transfers to the shift register. The byte begins shifting out on the MOSI pin

under the control of the serial clock.

•

S-clock

The SPR2, SPR1, and SPR0 baud rate selection bits, in conjunction with the SPPR2, SPPR1, and

SPPR0 baud rate preselection bits in the SPI baud rate register, control the baud rate generator and

determine the speed of the transmission. The SCK pin is the SPI clock output. Through the SCK

pin, the baud rate generator of the master controls the shift register of the slave peripheral.

•

MOSI, MISO pin

In master mode, the function of the serial data output pin (MOSI) and the serial data input pin

(MISO) is determined by the SPC0 and BIDIROE control bits.

SS pin

If MODFEN and SSOE are set, the SS pin is conﬁgured as slave select output. The SS output

becomes low during each transmission and is high when the SPI is in idle state.

If MODFEN is set and SSOE is cleared, the SS pin is conﬁgured as input for detecting mode fault

error. If the SS input becomes low this indicates a mode fault error where another master tries to

drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by

clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional

mode). So the result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a

transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is

forced into idle state.

This mode fault error also sets the mode fault (MODF) ﬂag in the SPI status register (SPISR). If

the SPI interrupt enable bit (SPIE) is set when the MODF ﬂag becomes set, then an SPI interrupt

sequence is also requested.

When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After

the delay, SCK is started within the master. The rest of the transfer operation differs slightly,

depending on the clock format speciﬁed by the SPI clock phase bit, CPHA, in SPI control register 1

(see Section 16.4.3, “Transmission Formats”).

NOTE

A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or

BIDIROE with SPC0 set, SPPR2-SPPR0 and SPR2-SPR0 in master mode

will abort a transmission in progress and force the SPI into idle state. The

remote slave cannot detect this, therefore the master must ensure that the

remote slave is returned to idle state.

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

16.4.2 Slave Mode

The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear.

•

SCK clock

In slave mode, SCK is the SPI clock input from the master.

MISO, MOSI pin

•

In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI)

is determined by the SPC0 bit and BIDIROE bit in SPI control register 2.

•

SS pin

The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI

must be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is

forced into idle state.

The SS input also controls the serial data output pin, if SS is high (not selected), the serial data

output pin is high impedance, and, if SS is low, the ﬁrst bit in the SPI data register is driven out of

the serial data output pin. Also, if the slave is not selected (SS is high), then the SCK input is

ignored and no internal shifting of the SPI shift register occurs.

Although the SPI is capable of duplex operation, some SPI peripherals are capable of only

receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin.

NOTE

When peripherals with duplex capability are used, take care not to

simultaneously enable two receivers whose serial outputs drive the same

system slave’s serial data output line.

As long as no more than one slave device drives the system slave’s serial data output line, it is possible for

several slaves to receive the same transmission from a master, although the master would not receive return

information from all of the receiving slaves.

If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at

the serial data input pin to be latched. Even numbered edges cause the value previously latched from the

serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.

If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to

be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift

into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.

When CPHA is set, the ﬁrst edge is used to get the ﬁrst data bit onto the serial data output pin. When CPHA

is clear and the SS input is low (slave selected), the ﬁrst bit of the SPI data is driven out of the serial data

output pin. After the eighth shift, the transfer is considered complete and the received data is transferred

into the SPI data register. To indicate transfer is complete, the SPIF ﬂag in the SPI status register is set.

NOTE

A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or

BIDIROE with SPC0 set in slave mode will corrupt a transmission in

progress and must be avoided.

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

16.4.3 Transmission Formats

During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially)

simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two

serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that

are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave select

line can be used to indicate multiple-master bus contention.

MASTER SPI

SLAVE SPI

MISO

MOSI

MISO

MOSI

SHIFT REGISTER

SCK

BAUD RATE

GENERATOR

Figure 16-10. Master/Slave Transfer Block Diagram

16.4.3.1 Clock Phase and Polarity Controls

Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase

and polarity.

The CPOL clock polarity control bit speciﬁes an active high or low clock and has no signiﬁcant effect on

the transmission format.

The CPHA clock phase control bit selects one of two fundamentally different transmission formats.

Clock phase and polarity should be identical for the master SPI device and the communicating slave

device. In some cases, the phase and polarity are changed between transmissions to allow a master device

to communicate with peripheral slaves having different requirements.

16.4.3.2 CPHA = 0 Transfer Format

The ﬁrst edge on the SCK line is used to clock the ﬁrst data bit of the slave into the master and the ﬁrst

data bit of the master into the slave. In some peripherals, the ﬁrst bit of the slave’s data is available at the

slave’s data out pin as soon as the slave is selected. In this format, the ﬁrst SCK edge is issued a half cycle

after SS has become low.

A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value

previously latched from the serial data input pin is shifted into the LSB or MSB of the shift register,

depending on LSBFE bit.

After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of

the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK

line, with data being latched on odd numbered edges and shifted on even numbered edges.

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and

is transferred to the parallel SPI data register after the last bit is shifted in.

After the 16th (last) SCK edge:

•

Data that was previously in the master SPI data register should now be in the slave data register and

the data that was in the slave data register should be in the master.

•

The SPIF ﬂag in the SPI status register is set, indicating that the transfer is complete.

Figure 16-11 is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for

CPOL = 0 and CPOL = 1. The diagram may be interpreted as a master or slave timing diagram because

the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal

is the output from the slave and the MOSI signal is the output from the master. The SS pin of the master

must be either high or reconﬁgured as a general-purpose output not affecting the SPI.

End of Idle State

Begin of Idle State

Begin

End

Transfer

10 11 12 13 14 15 16

SCK Edge Number

SCK (CPOL = 0)

SCK (CPOL = 1)

SAMPLE I

MOSI/MISO

CHANGE O

MOSI pin

CHANGE O

MISO pin

SEL SS (O)

Master only

SEL SS (I)

MSB ﬁrst (LSBFE = 0): MSB

LSB ﬁrst (LSBFE = 1): LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

LSB Minimum 1/2 SCK

for t , t , t

MSB

t = Minimum leading time before the ﬁrst SCK edge

t = Minimum trailing time after the last SCK edge

t = Minimum idling time between transfers (minimum SS high time)

t , t , and t are guaranteed for the master mode and required for the slave mode.

Figure 16-11. SPI Clock Format 0 (CPHA = 0)

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the

SPI data register is not transmitted; instead the last received byte is transmitted. If the SS line is deasserted

for at least minimum idle time (half SCK cycle) between successive transmissions, then the content of the

SPI data register is transmitted.

In master mode, with slave select output enabled the SS line is always deasserted and reasserted between

successive transfers for at least minimum idle time.

16.4.3.3 CPHA = 1 Transfer Format

Some peripherals require the ﬁrst SCK edge before the ﬁrst data bit becomes available at the data out pin,

the second edge clocks data into the system. In this format, the ﬁrst SCK edge is issued by setting the

CPHA bit at the beginning of the 8-cycle transfer operation.

The ﬁrst edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This ﬁrst

edge commands the slave to transfer its ﬁrst data bit to the serial data input pin of the master.

A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the

master and slave.

When the third edge occurs, the value previously latched from the serial data input pin is shifted into the

LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master

data is coupled out of the serial data output pin of the master to the serial input pin on the slave.

This process continues for a total of 16 edges on the SCK line with data being latched on even numbered

edges and shifting taking place on odd numbered edges.

Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and

is transferred to the parallel SPI data register after the last bit is shifted in.

After the 16th SCK edge:

•

Data that was previously in the SPI data register of the master is now in the data register of the

slave, and data that was in the data register of the slave is in the master.

•

The SPIF ﬂag bit in SPISR is set indicating that the transfer is complete.

Figure 16-12 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or

slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master

and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the

master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or

reconﬁgured as a general-purpose output not affecting the SPI.

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

End of Idle State

SCK Edge Number

SCK (CPOL = 0)

Begin

End

Begin of Idle State

Transfer

10 11 12 13 14 15 16

SCK (CPOL = 1)

SAMPLE I

MOSI/MISO

CHANGE O

MOSI pin

CHANGE O

MISO pin

SEL SS (O)

Master only

SEL SS (I)

MSB ﬁrst (LSBFE = 0): MSB

LSB ﬁrst (LSBFE = 1): LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

LSB Minimum 1/2 SCK

for t , t , t

MSB

t = Minimum leading time before the ﬁrst SCK edge, not required for back-to-back transfers

t = Minimum trailing time after the last SCK edge

t = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers

Figure 16-12. SPI Clock Format 1 (CPHA = 1)

The SS line can remain active low between successive transfers (can be tied low at all times). This format

is sometimes preferred in systems having a single ﬁxed master and a single slave that drive the MISO data

line.

•

Back-to-back transfers in master mode

In master mode, if a transmission has completed and a new data byte is available in the SPI data

The SPI interrupt request ﬂag (SPIF) is common to both the master and slave modes. SPIF gets set one

half SCK cycle after the last SCK edge.

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

16.4.4 SPI Baud Rate Generation

Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2,

SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in

the SPI baud rate.

The SPI clock rate is determined by the product of the value in the baud rate preselection bits

(SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor

equation is shown in Equation 16-3.

(SPR + 1)

BaudRateDivisor = (SPPR + 1) • 2

Eqn. 16-3

When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection

bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor

becomes 4. When the selection bits are 010, the module clock divisor becomes 8, etc.

When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When

the preselection bits are 010, the divisor is multiplied by 3, etc. See Table 16-7 for baud rate calculations

for all bit conditions, based on a 25 MHz bus clock. The two sets of selects allows the clock to be divided

by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc.

The baud rate generator is activated only when the SPI is in master mode and a serial transfer is taking

place. In the other cases, the divider is disabled to decrease I current.

NOTE

For maximum allowed baud rates, please refer to the SPI Electrical

Speciﬁcation in the Electricals chapter of this data sheet.

16.4.5 Special Features

16.4.5.1 SS Output

The SS output feature automatically drives the SS pin low during transmission to select external devices

and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin

is connected to the SS input pin of the external device.

The SS output is available only in master mode during normal SPI operation by asserting SSOE and

MODFEN bit as shown in Table 16-3.

The mode fault feature is disabled while SS output is enabled.

NOTE

Care must be taken when using the SS output feature in a multimaster

system because the mode fault feature is not available for detecting system

errors between masters.

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

16.4.5.2 Bidirectional Mode (MOMI or SISO)

The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (see Table 16-9). In

this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit

decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and

the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and

MOSI pin in slave mode are not used by the SPI.

Table 16-9. Normal Mode and Bidirectional Mode

When SPE = 1

Master Mode MSTR = 1

Slave Mode MSTR = 0

Serial Out

Serial In

MOSI

MISO

MOSI

MISO

Normal Mode

SPC0 = 0

SPI

Serial Out

Serial In

SPI

Serial Out

MOMI

Bidirectional Mode

SPC0 = 1

BIDIROE

SPI

BIDIROE

Serial In

Serial Out

SISO

The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is conﬁgured as an output,

serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift

•

The SCK is output for the master mode and input for the slave mode.

The SS is the input or output for the master mode, and it is always the input for the slave mode.

The bidirectional mode does not affect SCK and SS functions.

NOTE

In bidirectional master mode, with mode fault enabled, both data pins MISO

and MOSI can be occupied by the SPI, though MOSI is normally used for

transmissions in bidirectional mode and MISO is not used by the SPI. If a

mode fault occurs, the SPI is automatically switched to slave mode. In this

case MISO becomes occupied by the SPI and MOSI is not used. This must

be considered, if the MISO pin is used for another purpose.

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

16.4.6 Error Conditions

The SPI has one error condition:

•

Mode fault error

16.4.6.1 Mode Fault Error

If the SS input becomes low while the SPI is conﬁgured as a master, it indicates a system error where more

than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not

permitted in normal operation, the MODF bit in the SPI status register is set automatically, provided the

MODFEN bit is set.

In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by

the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case

the SPI system is conﬁgured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur

in slave mode.

If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output

buffer is disabled. So SCK, MISO, and MOSI pins are forced to be high impedance inputs to avoid any

possibility of conﬂict with another output driver. A transmission in progress is aborted and the SPI is

forced into idle state.

If the mode fault error occurs in the bidirectional mode for a SPI system conﬁgured in master mode, output

enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in

the bidirectional mode for SPI system conﬁgured in slave mode.

The mode fault ﬂag is cleared automatically by a read of the SPI status register (with MODF set) followed

by a write to SPI control register 1. If the mode fault ﬂag is cleared, the SPI becomes a normal master or

slave again.

NOTE

If a mode fault error occurs and a received data byte is pending in the receive

shift register, this data byte will be lost.

16.4.7 Low Power Mode Options

16.4.7.1 SPI in Run Mode

In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a

low-power, disabled state. SPI registers remain accessible, but clocks to the core of this module are

disabled.

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

16.4.7.2 SPI in Wait Mode

SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI control register 2.

•

If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode

If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation

state when the CPU is in wait mode.

– If SPISWAI is set and the SPI is configured for master, any transmission and reception in

progress stops at wait mode entry. The transmission and reception resumes when the SPI exits

wait mode.

– If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in

progress continues if the SCK continues to be driven from the master. This keeps the slave

synchronized to the master and the SCK.

If the master transmits several bytes while the slave is in wait mode, the slave will continue to

send out bytes consistent with the operation mode at the start of wait mode (i.e., if the slave is

currently sending its SPIDR to the master, it will continue to send the same byte. Else if the

slave is currently sending the last received byte from the master, it will continue to send each

previous master byte).

NOTE

Care must be taken when expecting data from a master while the slave is in

wait or stop mode. Even though the shift register will continue to operate,

the rest of the SPI is shut down (i.e., a SPIF interrupt will not be generated

until exiting stop or wait mode). Also, the byte from the shift register will

not be copied into the SPIDR register until after the slave SPI has exited wait

or stop mode. In slave mode, a received byte pending in the receive shift

SPIDR copy is generated only if wait mode is entered or exited during a

tranmission. If the slave enters wait mode in idle mode and exits wait mode

in idle mode, neither a SPIF nor a SPIDR copy will occur.

16.4.7.3 SPI in Stop Mode

Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held

high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the

transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is

exchanged correctly. In slave mode, the SPI will stay synchronized with the master.

The stop mode is not dependent on the SPISWAI bit.

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Chapter 16 Serial Peripheral Interface (S12SPIV4)

16.4.7.4 Reset

The reset values of registers and signals are described in Section 16.3, “Memory Map and Register

Deﬁnition”, which details the registers and their bit ﬁelds.

•

If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit

garbage, or the byte last received from the master before the reset.

•

Reading from the SPIDR after reset will always read a byte of zeros.

16.4.7.5 Interrupts

The MC9S12XDP512 only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The

following is a description of how the MC9S12XDP512 makes a request and how the MCU should

acknowledge that request. The interrupt vector offset and interrupt priority are chip dependent.

The interrupt ﬂags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request.

16.4.7.5.1

MODF

MODF occurs when the master detects an error on the SS pin. The master SPI must be conﬁgured for the

MODF feature (see Table 16-3). After MODF is set, the current transfer is aborted and the following bit is

changed:

•

MSTR = 0, The master bit in SPICR1 resets.

The MODF interrupt is reﬂected in the status register MODF ﬂag. Clearing the ﬂag will also clear the

interrupt. This interrupt will stay active while the MODF ﬂag is set. MODF has an automatic clearing

process which is described in Section 16.3.2.4, “SPI Status Register (SPISR)”.

16.4.7.5.2

SPIF

SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does

not clear until it is serviced. SPIF has an automatic clearing process, which is described in

Section 16.3.2.4, “SPI Status Register (SPISR)”.

16.4.7.5.3

SPTEF

SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear

until it is serviced. SPTEF has an automatic clearing process, which is described in Section 16.3.2.4, “SPI

Status Register (SPISR)”.

MC9S12XDP512 Data Sheet, Rev. 2.11

734

Freescale Semiconductor

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Chapter 17

Voltage Regulator (S12VREG3V3V5)

17.1 Introduction

Module VREG_3V3 is a dual output voltage regulator that provides two separate 2.5V (typical) supplies

differing in the amount of current that can be sourced. The regulator input voltage range is from 3.3V up

to 5V (typical).

17.1.1 Features

Module VREG_3V3 includes these distinctive features:

•

Two parallel, linear voltage regulators

— Bandgap reference

•

Low-voltage detect (LVD) with low-voltage interrupt (LVI)

Power-on reset (POR)

Low-voltage reset (LVR)

Autonomous periodical interrupt (API)

17.1.2 Modes of Operation

There are three modes VREG_3V3 can operate in:

1. Full performance mode (FPM) (MCU is not in stop mode)

The regulator is active, providing the nominal supply voltage of 2.5 V with full current sourcing

capability at both outputs. Features LVD (low-voltage detect), LVR (low-voltage reset), and POR

(power-on reset) are available. The API is available.

2. Reduced power mode (RPM) (MCU is in stop mode)

The purpose is to reduce power consumption of the device. The output voltage may degrade to a

lower value than in full performance mode, additionally the current sourcing capability is

substantially reduced. Only the POR is available in this mode, LVD and LVR are disabled. The API

is available.

3. Shutdown mode

Controlled by VREGEN (see device level speciﬁcation for connectivity of VREGEN).

This mode is characterized by minimum power consumption. The regulator outputs are in a

high-impedance state, only the POR feature is available, LVD and LVR are disabled. The API

internal RC oscillator clock is not available.

This mode must be used to disable the chip internal regulator VREG_3V3, i.e., to bypass the

VREG_3V3 to use external supplies.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

735

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Chapter 17 Voltage Regulator (S12VREG3V3V5)

17.1.3 Block Diagram

Figure 17-1 shows the function principle of VREG_3V3 by means of a block diagram. The regulator core

REG consists of two parallel subblocks, REG1 and REG2, providing two independent output voltages.

DDPLL

SSPLL

REG2

REG1

DDR

VBG

DDA

LVR

LVD

POR

LVR

POR

SSA

REGEN

CTRL

LVI

API

Rate

Select

API

Bus Clock

LVD: Low-Voltage Detect

LVR: Low-Voltage Reset

POR: Power-On Reset

REG: Regulator Core

CTRL: Regulator Control

API: Auto. Periodical Interrupt

Figure 17-1. VREG_3V3 Block Diagram

MC9S12XDP512 Data Sheet, Rev. 2.11

736

Freescale Semiconductor

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Chapter 17 Voltage Regulator (S12VREG3V3V5)

17.2 External Signal Description

Due to the nature of VREG_3V3 being a voltage regulator providing the chip internal power supply

voltages, most signals are power supply signals connected to pads.

Table 17-1 shows all signals of VREG_3V3 associated with pins.

Table 17-1. Signal Properties

Name

Function

Reset State

Pull Up

Power input (positive supply)

Quiet input (positive supply)

Quiet input (ground)

—

DDR

DDA

SSA

Primary output (positive supply)

Primary output (ground)

Secondary output (positive supply)

Secondary output (ground)

Optional Regulator Enable

DDPLL

SSPLL

(optional)

REGEN

NOTE

Check device level speciﬁcation for connectivity of the signals.

17.2.1 VDDR — Regulator Power Input Pins

Signal V

is the power input of VREG_3V3. All currents sourced into the regulator loads ﬂow through

DDR

this pin. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between V

and V

DDR

SSR

(if V

is not available V ) can smooth ripple on V

SSR

DDR

For entering Shutdown Mode, pin V

should also be tied to ground on devices without VREGEN pin.

DDR

17.2.2 VDDA, VSSA — Regulator Reference Supply Pins

Signals V

which are supposed to be relatively quiet, are used to supply the analog parts of the

DDA SSA,

regulator. Internal precision reference circuits are supplied from these signals. A chip external decoupling

capacitor (100 nF...220 nF, X7R ceramic) between V

supply.

and V

can further improve the quality of this

DDA

SSA

17.2.3 VDD, VSS — Regulator Output1 (Core Logic) Pins

Signals V /V are the primary outputs of VREG_3V3 that provide the power supply for the core logic.

DD SS

These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R

ceramic).

In Shutdown Mode an external supply driving V /V can replace the voltage regulator.

DD SS

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

737

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Chapter 17 Voltage Regulator (S12VREG3V3V5)

17.2.4 VDDPLL, VSSPLL — Regulator Output2 (PLL) Pins

Signals V

are the secondary outputs of VREG_3V3 that provide the power supply for the

DDPLL SSPLL

PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors

(100 nF...220 nF, X7R ceramic).

In Shutdown Mode, an external supply driving V

can replace the voltage regulator.

DDPLL SSPLL

17.2.5 V

Optional Regulator Enable Pin

REGEN —

This optional signal is used to shutdown VREG_3V3. In that case, V /V and V

/V must be

DDPLL SSPLL

DD SS

provided externally. Shutdown mode is entered with VREGEN being low. If VREGEN is high, the

VREG_3V3 is either in Full Performance Mode or in Reduced Power Mode.

For the connectivity of VREGEN, see device speciﬁcation.

NOTE

Switching from FPM or RPM to shutdown of VREG_3V3 and vice versa

is not supported while MCU is powered.

17.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all registers accessible in VREG_3V3.

If enabled in the system, the VREG_3V3 will abort all read and write accesses to reserved registers within

it’s memory slice.

17.3.1 Module Memory Map

Table 17-2 provides an overview of all used registers.

Table 17-2. Memory Map

Address

Offset

Use

Access

0x_00

0x_01

0x_02

0x_03

0x_04

0x_05

0x_06

0x_07

HT Control Register (VREGHTCL)

Control Register (VREGCTRL)

—

R/W

—

Autonomous Periodical Interrupt Control Register (VREGAPICL)

Autonomous Periodical Interrupt Trimming Register (VREGAPITR)

Autonomous Periodical Interrupt Period High (VREGAPIRH)

Autonomous Periodical Interrupt Period Low (VREGAPIRL)

Reserved 06

Reserved 07

—

MC9S12XDP512 Data Sheet, Rev. 2.11

738

Freescale Semiconductor

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Chapter 17 Voltage Regulator (S12VREG3V3V5)

17.3.2 Register Descriptions

This section describes all the VREG_3V3 registers and their individual bits.

17.3.2.1 HT Control Register (VREGHTCL)

The VREGHTCL is reserved for test purposes. This register should not be written.

Module Base + 0x_00

Reset

= Unimplemented or Reserved

Figure 17-2. HT Control Register (VREGHTCL)

17.3.2.2 Control Register (VREGCTRL)

The VREGCTRL register allows the conﬁguration of the VREG_3V3 low-voltage detect features.

Module Base + 0x_01

LVDS

LVIE

LVIF

Reset

= Unimplemented or Reserved

Figure 17-3. Control Register (VREGCTRL)

Table 17-3. VREGCTRL Field Descriptions

Description

Field

Low-Voltage Detect Status Bit — This read-only status bit reﬂects the input voltage. Writes have no effect.

LVDS

0 Input voltage V

1 Input voltage V

is above level V

is below level V

or RPM or shutdown mode.

and FPM.

DDA

LVID

LVIA

Low-Voltage Interrupt Enable Bit

LVIE

0 Interrupt request is disabled.

1 Interrupt will be requested whenever LVIF is set.

LVIF

Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This ﬂag can only be cleared by

writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.

0 No change in LVDS bit.

1 LVDS bit has changed.

Note: On entering the Reduced Power Mode the LVIF is not cleared by the VREG_3V3.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

739

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Chapter 17 Voltage Regulator (S12VREG3V3V5)

17.3.2.3 Autonomous Periodical Interrupt Control Register (VREGAPICL)

The VREGAPICL register allows the conﬁguration of the VREG_3V3 autonomous periodical interrupt

features.

Module Base + 0x_02

APICLK

APIFE

APIE

APIF

Reset

= Unimplemented or Reserved

Figure 17-4. Autonomous Periodical Interrupt Control Register (VREGAPICL)

Table 17-4. VREGAPICL Field Descriptions

Description

Field

Autonomous Periodical Interrupt Clock Select Bit — Selects the clock source for the API. Writable only if

APIFE = 0; APICLK cannot be changed if APIFE is set by the same write operation.

0 Autonomous periodical interrupt clock used as source.

APICLK

1 Bus clock used as source.

Autonomous Periodical Interrupt Feature Enable Bit — Enables the API feature and starts the API timer

when set.

APIFE

0 Autonomous periodical interrupt is disabled.

1 Autonomous periodical interrupt is enabled and timer starts running.

Autonomous Periodical Interrupt Enable Bit

0 API interrupt request is disabled.

APIE

1 API interrupt will be requested whenever APIF is set.

APIF

Autonomous Periodical Interrupt Flag — APIF is set to 1 when the in the API conﬁgured time has elapsed.

This ﬂag can only be cleared by writing a 1 to it. Clearing of the ﬂag has precedence over setting.

Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request.

0 API timeout has not yet occurred.

1 API timeout has occurred.

MC9S12XDP512 Data Sheet, Rev. 2.11

740

Freescale Semiconductor

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Chapter 17 Voltage Regulator (S12VREG3V3V5)

17.3.2.4 Autonomous Periodical Interrupt Trimming Register (VREGAPITR)

The VREGAPITR register allows to trim the API timeout period.

Module Base + 0x_03

APITR5

APITR4

APITR3

APITR2

APITR1

APITR0

Reset

1. Reset value is either 0 or preset by factory. See Device User Guide for details.

= Unimplemented or Reserved

Figure 17-5. Autonomous Periodical Interrupt Trimming Register (VREGAPITR)

Table 17-5. VREGAPITR Field Descriptions

Field

Description

7–2

Autonomous Periodical Interrupt Period Trimming Bits — See Table 17-6 for trimming effects.

APITR[5:0]

Table 17-6. Trimming Effect of APIT

Bit

Trimming Effect

APITR[5]

APITR[4]

APITR[3]

APITR[2]

APITR[1]

APITR[0]

Increases period

Decreases period less than APITR[5] increased it

Decreases period less than APITR[4]

Decreases period less than APITR[3]

Decreases period less than APITR[2]

Decreases period less than APITR[1]

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

741

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Chapter 17 Voltage Regulator (S12VREG3V3V5)

17.3.2.5 Autonomous Periodical Interrupt Rate High and Low Register

(VREGAPIRH / VREGAPIRL)

The VREGAPIRH and VREGAPIRL register allows the conﬁguration of the VREG_3V3 autonomous

periodical interrupt rate.

Module Base + 0x_04

APIR11

APIR10

APIR9

APIR8

Reset

= Unimplemented or Reserved

Figure 17-6. Autonomous Periodical Interrupt Rate High Register (VREGAPIRH)

Module Base + 0x_05

APIR7

APIR6

APIR5

APIR4

APIR3

APIR2

APIR1

APIR0

Reset

Figure 17-7. Autonomous Periodical Interrupt Rate Low Register (VREGAPIRL)

Table 17-7. VREGAPIRH / VREGAPIRL Field Descriptions

Description

Field

11-0

Autonomous Periodical Interrupt Rate Bits — These bits deﬁne the timeout period of the API. See Table 17-8

APIR[11:0] for details of the effect of the autonomous periodical interrupt rate bits. Writable only if APIFE = 0 of VREGAPICL

MC9S12XDP512 Data Sheet, Rev. 2.11

742

Freescale Semiconductor

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Chapter 17 Voltage Regulator (S12VREG3V3V5)

Table 17-8. Selectable Autonomous Periodical Interrupt Periods

APICLK

APIR[11:0]

Selected Period

000

001

002

003

004

005

.....

0.2 ms

0.4 ms

0.6 ms

0.8 ms

1.0 ms

1.2 ms

.....

FFD

FFE

FFF

000

001

002

003

004

005

.....

818.8 ms

819 ms

819.2 ms

2 * bus clock period

4 * bus clock period

6 * bus clock period

8 * bus clock period

10 * bus clock period

12 * bus clock period

.....

FFD

FFE

FFF

8188 * bus clock period

8190 * bus clock period

8192 * bus clock period

When trimmed within speciﬁed accuracy. See electrical speciﬁcations for details.

You can calculate the selected period depending of APICLK as:

Period = 2*(APIR[11:0] + 1) * 0.1 ms or period = 2*(APIR[11:0] + 1) * bus clock period

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

743

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Chapter 17 Voltage Regulator (S12VREG3V3V5)

17.3.2.6 Reserved_06

The Reserved_06 is reserved for test purposes.

Module Base + 0x_06

Reset

= Unimplemented or Reserved

Figure 17-8. Reserved_06

17.3.2.7 Reserved_07

The Reserved_07 is reserved for test purposes.

Module Base + 0x_07

Reset

= Unimplemented or Reserved

Figure 17-9. Reserved_07

17.4 Functional Description

17.4.1 General

Module VREG_3V3 is a voltage regulator, as depicted in Figure 17-1. The regulator functional elements

are the regulator core (REG), a low-voltage detect module (LVD), a control block (CTRL), a power-on

reset module (POR), and a low-voltage reset module (LVR).

17.4.2 Regulator Core (REG)

Respectively its regulator core has two parallel, independent regulation loops (REG1 and REG2) that differ

only in the amount of current that can be delivered.

The regulator is a linear regulator with a bandgap reference when operated in Full Performance Mode. It

acts as a voltage clamp in Reduced Power Mode. All load currents ﬂow from input V

to V or

DDR

. The reference circuits are supplied by V

and V

SSPLL

DDA

SSA

17.4.2.1 Full Performance Mode

In Full Performance Mode, the output voltage is compared with a reference voltage by an operational

ampliﬁer. The ampliﬁed input voltage difference drives the gate of an output transistor.

MC9S12XDP512 Data Sheet, Rev. 2.11

744

Freescale Semiconductor

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Chapter 17 Voltage Regulator (S12VREG3V3V5)

17.4.2.2 Reduced Power Mode

In Reduced Power Mode, the gate of the output transistor is connected directly to a reference voltage to

reduce power consumption.

17.4.3 Low-Voltage Detect (LVD)

Subblock LVD is responsible for generating the low-voltage interrupt (LVI). LVD monitors the input

voltage (V

–V ) and continuously updates the status ﬂag LVDS. Interrupt ﬂag LVIF is set whenever

DDA

SSA

status ﬂag LVDS changes its value. The LVD is available in FPM and is inactive in Reduced Power Mode

or Shutdown Mode.

17.4.4 Power-On Reset (POR)

This functional block monitors V . If V is below V

, POR is asserted; if V exceeds V

PORD

the POR is deasserted. POR asserted forces the MCU into Reset. POR Deasserted will trigger the power-on

sequence.

17.4.5 Low-Voltage Reset (LVR)

Block LVR monitors the primary output voltage V . If it drops below the assertion level (V

) signal,

LVRA

LVR asserts; if V rises above the deassertion level (V

) signal, LVR deasserts. The LVR function

LVRD

is available only in Full Performance Mode.

17.4.6 Regulator Control (CTRL)

This part contains the register block of VREG_3V3 and further digital functionality needed to control the

operating modes. CTRL also represents the interface to the digital core logic.

17.4.7 Autonomous Periodical Interrupt (API)

Subblock API can generate periodical interrupts independent of the clock source of the MCU. To enable

the timer, the bit APIFE needs to be set.

The API timer is either clocked by a trimmable internal RC oscillator or the bus clock. Timer operation

will freeze when MCU clock source is selected and bus clock is turned off. See CRG speciﬁcation for

details. The clock source can be selected with bit APICLK. APICLK can only be written when APIFE is

not set.

The APIR[11:0] bits determine the interrupt period. APIR[11:0] can only be written when APIFE is

cleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[11:0] bits. When

the conﬁgured time has elapsed, the ﬂag APIF is set. An interrupt, indicated by ﬂag APIF = 1, is triggered

if interrupt enable bit APIE = 1. The timer is started automatically again after it has set APIF.

The procedure to change APICLK or APIR[11:0] is ﬁrst to clear APIFE, then write to APICLK or

APIR[11:0], and afterwards set APIFE.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

745

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Chapter 17 Voltage Regulator (S12VREG3V3V5)

The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency

is desired.

See Table 17-6 for the trimming effect of APITR.

NOTE

The ﬁrst period after enabling the counter by APIFE might be reduced.

The API internal RC oscillator clock is not available if VREG_3V3 is in

Shutdown Mode.

17.4.8 Resets

This section describes how VREG_3V3 controls the reset of the MCU.The reset values of registers and

signals are provided in Section 17.3, “Memory Map and Register Deﬁnition”. Possible reset sources are

listed in Table 17-9.

Table 17-9. Reset Sources

Reset Source

Local Enable

Power-on reset

Always active

Low-voltage reset

Available only in Full Performance Mode

17.4.9 Description of Reset Operation

17.4.9.1 Power-On Reset (POR)

During chip power-up the digital core may not work if its supply voltage V is below the POR

deassertion level (V

). Therefore, signal POR, which forces the other blocks of the device into reset,

PORD

is kept high until V exceeds V

. The MCU will run the start-up sequence after POR deassertion.

PORD

The power-on reset is active in all operation modes of VREG_3V3.

17.4.9.2 Low-Voltage Reset (L V R)

For details on low-voltage reset, see Section 17.4.5, “Low-Voltage Reset (LVR)”.

17.4.10 Interrupts

This section describes all interrupts originated by VREG_3V3.

The interrupt vectors requested by VREG_3V3 are listed in Table 17-10. Vector addresses and interrupt

priorities are deﬁned at MCU level.

Table 17-10. Interrupt Vectors

Interrupt Source

Local Enable

Low-voltage interrupt (LVI)

LVIE = 1; available only in Full Performance

Mode

MC9S12XDP512 Data Sheet, Rev. 2.11

746

Freescale Semiconductor

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Chapter 17 Voltage Regulator (S12VREG3V3V5)

Table 17-10. Interrupt Vectors

Interrupt Source

Local Enable

APIE = 1

Autonomous periodical interrupt (API)

17.4.10.1 Low-Voltage Interrupt (LVI)

In FPM, VREG_3V3 monitors the input voltage V

. Whenever V

drops below level V

the

DDA

LVIA,

status bit LVDS is set to 1. On the other hand, LVDS is reset to 0 when V

rises above level V

. An

LVID

DDA

interrupt, indicated by ﬂag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable

bit LVIE = 1.

NOTE

On entering the Reduced Power Mode, the LVIF is not cleared by the

VREG_3V3.

17.4.10.2 Autonomous Periodical Interrupt (API)

As soon as the conﬁgured timeout period of the API has elapsed, the APIF bit is set. An interrupt, indicated

by ﬂag APIF = 1, is triggered if interrupt enable bit APIE = 1.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

747

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Chapter 17 Voltage Regulator (S12VREG3V3V5)

MC9S12XDP512 Data Sheet, Rev. 2.11

748

Freescale Semiconductor

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Chapter 18

Periodic Interrupt Timer (S12PIT24B4CV1)

18.1 Introduction

The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules

or raise periodic interrupts. Refer to Figure 18-1 for a simpliﬁed block diagram.

18.1.1 Features

The MC9S12XDP512 includes these features:

•

Four timers implemented as modulus down-counters with independent time-out periods.

Time-out periods selectable between 1 and 2 bus clock cycles. Time-out equals m*n bus clock

cycles with 1 <= m <= 256 and 1 <= n <= 65536.

•

Timers that can be enabled individually.

Four time-out interrupts.

Four time-out trigger output signals available to trigger peripheral modules.

Start of timer channels can be aligned to each other.

18.1.2 Modes of Operation

Refer to the SoC guide for a detailed explanation of the chip modes.

•

Run mode

This is the basic mode of operation.

Wait mode

•

PIT operation in wait mode is controlled by the PITSWAI bit located in the PITCFLMT register.

In wait mode, if the bus clock is globally enabled and if the PITSWAI bit is clear, the PIT operates

like in run mode. In wait mode, if the PITSWAI bit is set, the PIT module is stalled.

•

Stop mode

In full stop mode or pseudo stop mode, the PIT module is stalled.

Freeze mode

PIT operation in freeze mode is controlled by the PITFRZ bit located in the PITCFLMT register.

In freeze mode, if the PITFRZ bit is clear, the PIT operates like in run mode. In freeze mode, if the

PITFRZ bit is set, the PIT module is stalled.

MC9S12XDP512 Data Sheet, Rev. 2.11

Freescale Semiconductor

749

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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1)

18.1.3 Block Diagram

Figure 18-1 shows a block diagram of the PIT.

Interrupt 0

Trigger 0

Micro Time

Base 0

Time-Out 0

Time-Out 1

Time-Out 2

Time-Out 3

16-Bit Timer 0

16-Bit Timer 1

16-Bit Timer 2

16-Bit Timer 3

Interface

8-Bit

Micro Timer 0

Bus Clock

Interrupt 1

Trigger 1

Micro

8-Bit

Interrupt 2

Trigger 2

Time

Micro Timer 1

Base 1

Interrupt 3

Trigger 3

Figure 18-1. MC9S12XDP512 Block Diagram

18.2 External Signal Description

The PIT module has no external pins.

MC9S12XDP512 Data Sheet, Rev. 2.11

750

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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1)

18.3 Memory Map and Register Deﬁnition

This section provides a detailed description of address space and registers used by the PIT.

18.3.1 Module Memory Map

The memory map for the MC9S12XDP512 is given below in Table 1-1. The address listed for each register

is the sum of a base address and an address offset. The base address is deﬁned at the SoC level and the

address offset is deﬁned at the module level. Reads from the reserved bits return zeros and writes to the

reserved bits have no effect.

Table 18-1. MC9S12XDP512 Memory Map

Address

Offset

Use

Access

0x0000

0x0001

PIT Control and Force Load Micro Timer Register (PITCFLMT)

PIT Force Load Timer Register (PITFLT)

PIT Channel Enable Register (PITCE)

PIT Multiplex Register (PITMUX)

R/W

1,2

R/W

0x0002

R/W

0x0003

R/W

0x0004

PIT Interrupt Enable Register (PITINTE)

PIT Time-Out Flag Register (PITTF)

PIT Micro Timer Load Register 0 (PITMTLD0)

PIT Micro Timer Load Register 1 (PITMTLD1)

PIT Load Register 0 (PITLD0)

R/W

0x0005

R/W

0x0006

R/W

0x0007

0x0008, 0x0009

0x000A, 0x000B

0x000C, 0x000D

0x000E, 0x000F

0x0010, 0x0011

0x0012, 0x0013

0x0014, 0x0015

0x0016, 0x0017

0x0018 - 0x0027

PIT Count Register 0 (PITCNT0)

PIT Load Register 1 (PITLD1)

PIT Count Register 1 (PITCNT1)

PIT Load Register 2 (PITLD2)

PIT Count Register 2 (PITCNT2)

PIT Load Register 3 (PITLD3)

PIT Count Register 3 (PITCNT3)

Reserved Registers

Certain bits are non-writable.

Reading from this register returns all zeros.

Reading from these registers returns all zeros. Writing to these registers has no effect.

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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1)

18.3.2 Register Descriptions

This section consists of register descriptions in address order. Each description includes a standard register

diagram with an associated ﬁgure number. Details of register bit and ﬁeld function follow the register

diagrams, in bit order.

Name

Bit 7

PITE

PITSWAI

PITFRZ

Bit 0

0x0000

PITCFLMT

PFLMT1

PFLMT0

0x0001

PITFLT

PFLT3

PFLT2

PFLT1

PFLT0

0x0002

PITCE

PCE3

PMUX3

PINTE3

PTF3

PCE2

PMUX2

PINTE2

PTF2

PCE1

PMUX1

PINTE1

PTF1

PCE0

PMUX0

PINTE0

PTF0

0x0003

PITMUX

0x0004

PITINTE

0x0005

PITTF

0x0006

PITMTLD0

PMTLD7

PLD15

PMTLD6

PLD14

PMTLD5

PLD13

PMTLD4

PLD12

PMTLD3

PLD11

PLD3

PMTLD2

PLD10

PLD2

PMTLD1

PLD9

PMTLD0

PLD8

0x0007

PITMTLD1

0x0008

PITLD0 (High)

0x0009

PITLD0 (Low)

PLD7

PLD6

PLD5

PLD4

PLD1

PLD0

0x000A

PITCNT0 (High)

PCNT15

PCNT7

PLD15

PCNT14

PCNT6

PLD14

PCNT13

PCNT5

PLD13

PCNT12

PCNT4

PLD12

PCNT11

PCNT3

PLD11

PCNT10

PCNT2

PLD10

PCNT9

PCNT1

PLD9

PCNT8

PCNT0

PLD8

0x000B

PITCNT0 (Low)

0x000C

PITLD1 (High)

= Unimplemented or Reserved

Figure 18-2. PIT Register Summary (Sheet 1 of 2)

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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1)

Name

Bit 7

Bit 0

0x000D

PITLD1 (Low)

PLD7

PLD6

PLD5

PLD4

PLD3

PLD2

PLD1

PLD0

0x000E

PITCNT1 (High)

PCNT15

PCNT7

PLD15

PLD7

PCNT14

PCNT6

PLD14

PLD6

PCNT13

PCNT5

PLD13

PLD5

PCNT12

PCNT4

PLD12

PLD4

PCNT11

PCNT3

PLD11

PLD3

PCNT10

PCNT2

PLD10

PLD2

PCNT9

PCNT1

PLD9

PCNT8

PCNT0

PLD8

0x000F

PITCNT1 (Low)

0x0010

PITLD2 (High)

0x0011

PITLD2 (Low)

PLD1

PLD0

0x0012

PITCNT2 (High)

PCNT15

PCNT7

PLD15

PLD7

PCNT14

PCNT6

PLD14

PLD6

PCNT13

PCNT5

PLD13

PLD5

PCNT12

PCNT4

PLD12

PLD4

PCNT11

PCNT3

PLD11

PLD3

PCNT10

PCNT2

PLD10

PLD2

PCNT9

PCNT1

PLD9

PCNT8

PCNT0

PLD8

0x0013

PITCNT2 (Low)

0x0014

PITLD3 (High)

0x0015

PITLD3 (Low)

PLD1

PLD0

0x0016

PITCNT3 (High)

PCNT15

PCNT7

PCNT14

PCNT6

PCNT13

PCNT5

PCNT12

PCNT4

PCNT11

PCNT3

PCNT10

PCNT2

PCNT9

PCNT1

PCNT8

PCNT0

0x0017

PITCNT3 (Low)

= Unimplemented or Reserved

Figure 18-2. PIT Register Summary (Sheet 2 of 2)

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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1)

18.3.2.1 PIT Control and Force Load Micro Timer Register (PITCFLMT)

Module Base + 0x0000

PITE

PITSWAI

PITFRZ

PFLMT1

PFLMT0

Reset

= Unimplemented or Reserved

Figure 18-3. PIT Control and Force Load Micro Timer Register (PITCFLMT)

Read: Anytime

Write: Anytime; writes to the reserved bits have no effect

Table 18-2. PITCFLMT Field Descriptions

Field

Description

PITE

PIT Module Enable Bit — This bit enables the PIT module. If PITE is cleared, the PIT module is disabled and

ﬂag bits in the PITTF register are cleared. When PITE is set, individually enabled timers (PCE set) start

down-counting with the corresponding load register values.

0 PIT disabled (lower power consumption).

1 PIT is enabled.

PIT Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.

0 PIT operates normally in wait mode

PITSWAI

1 PIT clock generation stops and freezes the PIT module when in wait mode

PIT Counter Freeze while in Freeze Mode Bit — When during debugging a breakpoint (freeze mode) is

encountered it is useful in many cases to freeze the PIT counters to avoid e.g. interrupt generation. The PITFRZ

bit controls the PIT operation while in freeze mode.

PITFRZ

0 PIT operates normally in freeze mode

1 PIT counters are stalled when in freeze mode

1:0

PIT Force Load Bits for Micro Timer 1:0 — These bits have only an effect if the corresponding micro timer is

PFLMT[1:0] active and if the PIT module is enabled (PITE set). Writing a one into a PFLMT bit loads the corresponding 8-bit

micro timer load register into the 8-bit micro timer down-counter. Writing a zero has no effect. Reading these bits

will always return zero.

Note: A micro timer force load affects all timer channels that use the corresponding micro time base.

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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1)

18.3.2.2 PIT Force Load Timer Register (PITFLT)

Module Base + 0x0001

PFLT3

PFLT2

PFLT1

PFLT0

Reset

= Unimplemented or Reserved

Figure 18-4. PIT Force Load Timer Register (PITFLT)

Read: Anytime

Write: Anytime; writes to the reserved bits have no effect

Table 18-3. PITFLT Field Descriptions

Field

Description

PIT Force Load Bits for Timer 3-0 — These bits have only an effect if the corresponding timer channel (PCE

3:0

PFLT[3:0] set) is enabled and if the PIT module is enabled (PITE set). Writing a one into a PFLT bit loads the corresponding

16-bit timer load register into the 16-bit timer down-counter. Writing a zero has no effect. Reading these bits will

always return zero.

18.3.2.3 PIT Channel Enable Register (PITCE)

Module Base + 0x0002

PCE3

PCE2

PCE1

PCE0

Reset

= Unimplemented or Reserved

Figure 18-5. PIT Channel Enable Register (PITCE)

Read: Anytime

Write: Anytime; writes to the reserved bits have no effect

Table 18-4. PITCE Field Descriptions

Field

Description

3:0

PCE[3:0]

PIT Enable Bits for Timer Channel 3:0 — These bits enable the PIT channels 3-0. If PCE is cleared, the PIT

channel is disabled and the corresponding ﬂag bit in the PITTF register is cleared. When PCE is set, and if the

PIT module is enabled (PITE = 1) the 16-bit timer counter is loaded with the start count value and starts

down-counting.

0 The corresponding PIT channel is disabled.

1 The corresponding PIT channel is enabled.

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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1)

18.3.2.4 PIT Multiplex Register (PITMUX)

Module Base + 0x0003

PMUX3

PMUX2

PMUX1

PMUX0

Reset

= Unimplemented or Reserved

Figure 18-6. PIT Multiplex Register (PITMUX)

Read: Anytime

Write: Anytime; writes to the reserved bits have no effect

Table 18-5. PITMUX Field Descriptions

Field

Description

PIT Multiplex Bits for Timer Channel 3:0 — These bits select if the corresponding 16-bit timer is connected to

3:0

PMUX[3:0] micro time base 1 or 0. If PMUX is modiﬁed, the corresponding 16-bit timer is immediately switched to the other

micro time base.

0 The corresponding 16-bit timer counts with micro time base 0.

1 The corresponding 16-bit timer counts with micro time base 1.

18.3.2.5 PIT Interrupt Enable Register (PITINTE)

Module Base + 0x0004

PINTE3

PINTE2

PINTE1

PINTE0

Reset

= Unimplemented or Reserved

Figure 18-7. PIT Interrupt Enable Register (PITINTE)

Read: Anytime

Write: Anytime; writes to the reserved bits have no effect

Table 18-6. PITINTE Field Descriptions

Field

Description

PIT Time-out Interrupt Enable Bits for Timer Channel 3:0 — These bits enable an interrupt service request

3:0

PINTE[3:0] whenever the time-out ﬂag PTF of the corresponding PIT channel is set. When an interrupt is pending (PTF set)

enabling the interrupt will immediately cause an interrupt. To avoid this, the corresponding PTF ﬂag has to be

cleared ﬁrst.

0 Interrupt of the corresponding PIT channel is disabled.

1 Interrupt of the corresponding PIT channel is enabled.

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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1)

18.3.2.6 PIT Time-Out Flag Register (PITTF)

Module Base + 0x0005

PTF3

PTF2

PTF1

PTF0

Reset

= Unimplemented or Reserved

Figure 18-8. PIT Time-Out Flag Register (PITTF)

Read: Anytime

Write: Anytime (write to clear); writes to the reserved bits have no effect

Table 18-7. PITTF Field Descriptions

Field

Description

3:0

PTF[3:0]

PIT Time-out Flag Bits for Timer Channel 3:0 — PTF is set when the corresponding 16-bit timer modulus

down-counter and the selected 8-bit micro timer modulus down-counter have counted to zero. The ﬂag can be

cleared by writing a one to the ﬂag bit. Writing a zero has no effect. If ﬂag clearing by writing a one and ﬂag setting

happen in the same bus clock cycle, the ﬂag remains set. The ﬂag bits are cleared if the PIT module is disabled

or if the corresponding timer channel is disabled.

0 Time-out of the corresponding PIT channel has not yet occurred.

1 Time-out of the corresponding PIT channel has occurred.

18.3.2.7 PIT Micro Timer Load Register 0 to 1 (PITMTLD0–1)

Module Base + 0x0006

PMTLD7

PMTLD6

PMTLD5

PMTLD4

PMTLD3

PMTLD2

PMTLD1

PMTLD0

Reset

Figure 18-9. PIT Micro Timer Load Register 0 (PITMTLD0)

Module Base + 0x0007

PMTLD7

PMTLD6

PMTLD5

PMTLD4

PMTLD3

PMTLD2

PMTLD1

PMTLD0

Reset

Figure 18-10. PIT Micro Timer Load Register 1 (PITMTLD1)

Read: Anytime

Write: Anytime

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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1)

Table 18-8. PITMTLD0–1 Field Descriptions

Field

Description

7:0

PIT Micro Timer Load Bits 7:0 — These bits set the 8-bit modulus down-counter load value of the micro timers.

PMTLD[7:0] Writing a new value into the PITMTLD register will not restart the timer. When the micro timer has counted down

to zero, the PMTLD register value will be loaded. The PFLMT bits in the PITCFLMT register can be used to

immediately update the count register with the new value if an immediate load is desired.

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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1)

18.3.2.8 PIT Load Register 0 to 3 (PITLD0–3)

Module Base + 0x0008, 0x0009

PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0

Reset

Figure 18-11. PIT Load Register 0 (PITLD0)

Module Base + 0x000C, 0x000D

PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0

Reset

Figure 18-12. PIT Load Register 1 (PITLD1)

Module Base + 0x0010, 0x0011

PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0

Reset

Figure 18-13. PIT Load Register 2 (PITLD2)

Module Base + 0x0014, 0x0015

PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0

Reset

Figure 18-14. PIT Load Register 3 (PITLD3)

Read: Anytime

Write: Anytime

Table 18-9. PITLD0–3 Field Descriptions

Description

Field

15:0

PIT Load Bits 15:0 — These bits set the 16-bit modulus down-counter load value. Writing a new value into the

PLD[15:0] PITLD register must be a 16-bit access, to ensure data consistency. It will not restart the timer. When the timer

has counted down to zero the PTF time-out ﬂag will be set and the register value will be loaded. The PFLT bits

in the PITFLT register can be used to immediately update the count register with the new value if an immediate

load is desired.

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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1)

18.3.2.9 PIT Count Register 0 to 3 (PITCNT0–3)

Module Base + 0x000A, 0x000B

PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT

Reset

Figure 18-15. PIT Count Register 0 (PITCNT0)

Module Base + 0x000E, 0x000F

PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT

Reset

Figure 18-16. PIT Count Register 1 (PITCNT1)

Module Base + 0x0012, 0x0013

PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT

Reset

Figure 18-17. PIT Count Register 2 (PITCNT2)

Module Base + 0x0016, 0x0017

PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT

Reset

Figure 18-18. PIT Count Register 3 (PITCNT3)

Read: Anytime

Write: Has no meaning or effect

Table 18-10. PITCNT0–3 Field Descriptions

Field

Description

15:0

PIT Count Bits 15-0 — These bits represent the current 16-bit modulus down-counter value. The read access

PCNT[15:0] for the count register must take place in one clock cycle as a 16-bit access.

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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1)

18.4 Functional Description

Figure 18-19 shows a detailed block diagram of the PIT module. The main parts of the PIT are status,

control and data registers, two 8-bit down-counters, four 16-bit down-counters and an interrupt/trigger

interface.

PIT_24B4C

PFLT0

PMUX0

PITFLT Register

PITMUX Register

Timer 0

PITLD0 Register

PITCNT0 Register

time-out 0

PFLT1

PITMLD0 Register

8-Bit Micro Timer 0

Timer 1

Bus

[1]

Interrupt /

time-

out 1

PITLD1 Register

Clock

Trigger Interface

[0]

PITCNT1 Register

Hardware

Trigger

PFLT2

[2]

PITTF Register

Timer 2

PITMLD1 Register

8-Bit Micro Timer 1

time-

out 2

PITLD2 Register

[1]

PITCNT2 Register

Interrupt

Request

PITINTE Register

PITCFLMT Register

PFLT3

PFLMT

Timer 3

PITLD3 Register

PMUX3

PITCNT3 Register

Time-Out 3

Figure 18-19. MC9S12XDP512 Detailed Block Diagram

18.4.1 Timer

As shown in Figure 18-1and Figure 18-19, the 24-bit timers are built in a two-stage architecture with four

16-bit modulus down-counters and two 8-bit modulus down-counters. The 16-bit timers are clocked with

two selectable micro time bases which are generated with 8-bit modulus down-counters. Each 16-bit timer

is connected to micro time base 0 or 1 via the PMUX[3:0] bit setting in the PIT Multiplex (PITMUX)

A timer channel is enabled if the module enable bit PITE in the PIT control and force load micro timer

(PITCFLMT) register is set and if the corresponding PCE bit in the PIT channel enable (PITCE) register

is set. Two 8-bit modulus down-counters are used to generate two micro time bases. As soon as a micro

time base is selected for an enabled timer channel, the corresponding micro timer modulus down-counter

will load its start value as speciﬁed in the PITMTLD0 or PITMTLD1 register and will start down-counting.

Whenever the micro timer down-counter has counted to zero the PITMTLD register is reloaded and the

connected 16-bit modulus down-counters count one cycle.

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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1)

Whenever a 16-bit timer counter and the connected 8-bit micro timer counter have counted to zero, the

PITLD register is reloaded and the corresponding time-out ﬂag PTF in the PIT time-out ﬂag (PITTF)

micro timer load (PITMTLD) registers and the bus clock f

BUS

time-out period = (PITMTLD + 1) * (PITLD + 1) / f

BUS

For example, for a 40 MHz bus clock, the maximum time-out period equals:

256 * 65536 * 25 ns = 419.43 ms.

The current 16-bit modulus down-counter value can be read via the PITCNT register. The micro timer

down-counter values cannot be read.

The 8-bit micro timers can individually be restarted by writing a one to the corresponding force load micro

timer PFLMT bits in the PIT control and force load micro timer (PITCFLMT) register. The 16-bit timers

can individually be restarted by writing a one to the corresponding force load timer PFLT bits in the PIT

forceload timer (PITFLT) register. If desired, any group of timers and micro timers can be restarted at the

same time by using one 16-bit write to the adjacent PITCFLMT and PITFLT registers with the relevant

bits set, as shown in Figure 18-20.

Bus Clock

8-Bit Micro

Timer Counter

0001

0000

0001

0000

0001

0000

0001

PITCNT Register

8-Bit Force Load

16-Bit Force Load

PTF Flag

PITTRIG

Time-Out Period

After Restart

Time-Out Period

Note 1. The PTF ﬂag clearing depends on the software

Figure 18-20. PIT Trigger and Flag Signal Timing

18.4.2 Interrupt Interface

Each time-out event can be used to trigger an interrupt service request. For each timer channel, an

individual bit PINTE in the PIT interrupt enable (PITINTE) register exists to enable this feature. If PINTE

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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1)

is set, an interrupt service is requested whenever the corresponding time-out ﬂag PTF in the PIT time-out

ﬂag (PITTF) register is set. The ﬂag can be cleared by writing a one to the ﬂag bit.

NOTE

Be careful when resetting the PITE, PINTE or PITCE bits in case of pending

PIT interrupt requests, to avoid spurious interrupt requests.

18.4.3 Hardware Trigger

The PIT module contains four hardware trigger signal lines PITTRIG[3:0], one for each timer channel.

These signals can be connected on SoC level to peripheral modules enabling e.g. periodic ATD conversion

(please refer to the SoC Guide for the mapping of PITTRIG[3:0] signals to peripheral modules).

Whenever a timer channel time-out is reached, the corresponding PTF ﬂag is set and the corresponding

trigger signal PITTRIG triggers a rising edge. The trigger feature requires a minimum time-out period of

two bus clock cycles because the trigger is asserted high for at least one bus clock cycle. For load register

values PITLD = 0x0001 and PITMTLD = 0x0002 the ﬂag setting, trigger timing and a restart with force

load is shown in Figure 18-20.

18.5 Initialization/Application Information

18.5.1 Startup

Set the conﬁguration registers before the PITE bit in the PITCFLMT register is set. Before PITE is set, the

conﬁguration registers can be written in arbitrary order.

18.5.2 Shutdown

When the PITCE register bits, the PITINTE register bits or the PITE bit in the PITCFLMT register are

cleared, the corresponding PIT interrupt ﬂags are cleared. In case of a pending PIT interrupt request, a

spurious interrupt can be generated. Two strategies, which avoid spurious interrupts, are recommended:

1. Reset the PIT interrupt ﬂags only in an ISR. When entering the ISR, the I mask bit in the CCR is

set automatically. The I mask bit must not be cleared before the PIT interrupt ﬂags are cleared.

2. After setting the I mask bit with the SEI instruction, the PIT interrupt ﬂags can be cleared. Then

clear the I mask bit with the CLI instruction to re-enable interrupts.

18.5.3 Flag Clearing

A ﬂag is cleared by writing a one to the ﬂag bit. Always use store or move instructions to write a one in

certain bit positions. Do not use the BSET instructions. Do not use any C-constructs that compile to BSET

instructions. “BSET ﬂag_register, #mask” must not be used for ﬂag clearing because BSET is a

read-modify-write instruction which writes back the “bit-wise or” of the ﬂag_register and the mask into

the ﬂag_register. BSET would clear all ﬂag bits that were set, independent from the mask.

For example, to clear ﬂag bit 0 use: MOVB #$01,PITTF.

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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV1)

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Chapter 19

Background Debug Module (S12XBDMV2)

19.1 Introduction

This section describes the functionality of the background debug module (BDM) sub-block of the

HCS12X core platform.

The background debug module (BDM) sub-block is a single-wire, background debug system implemented

in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD

pin.

The BDM has enhanced capability for maintaining synchronization between the target and host while

allowing more ﬂexibility in clock rates. This includes a sync signal to determine the communication rate

and a handshake signal to indicate when an operation is complete. The system is backwards compatible to

the BDM of the S12 family with the following exceptions:

•

TAGGO command no longer supported by BDM

External instruction tagging feature now part of DBG module

BDM register map and register content extended/modiﬁed

Global page access functionality

Enabled but not active out of reset in emulation modes

CLKSW bit set out of reset in emulation mode.

Family ID readable from ﬁrmware ROM at global address 0x7FFF0F (value for HCS12X devices

is 0xC1)

19.1.1 Features

The BDM includes these distinctive features:

•

Single-wire communication with host development system

Enhanced capability for allowing more ﬂexibility in clock rates

SYNC command to determine communication rate

GO_UNTIL command

Hardware handshake protocol to increase the performance of the serial communication

Active out of reset in special single chip mode

Nine hardware commands using free cycles, if available, for minimal CPU intervention

Hardware commands not requiring active BDM

14 ﬁrmware commands execute from the standard BDM ﬁrmware lookup table

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Chapter 19 Background Debug Module (S12XBDMV2)

•

Software control of BDM operation during wait mode

Software selectable clocks

Global page access functionality

Enabled but not active out of reset in emulation modes

CLKSW bit set out of reset in emulation mode.

When secured, hardware commands are allowed to access the register space in special single chip

mode, if the Flash and EEPROM erase tests fail.

•

Family ID readable from ﬁrmware ROM at global address 0x7FFF0F (value for HCS12X devices

is 0xC1)

BDM hardware commands are operational until system stop mode is entered (all bus masters are

in stop mode)

19.1.2 Modes of Operation

BDM is available in all operating modes but must be enabled before ﬁrmware commands are executed.

Some systems may have a control bit that allows suspending the function during background debug mode.

19.1.2.1 Regular Run Modes

All of these operations refer to the part in run mode and not being secured. The BDM does not provide

controls to conserve power during run mode.

•

Normal modes

General operation of the BDM is available and operates the same in all normal modes.

Special single chip mode

•

In special single chip mode, background operation is enabled and active out of reset. This allows

programming a system with blank memory.

•

Emulation modes

In emulation mode, background operation is enabled but not active out of reset. This allows

debugging and programming a system in this mode more easily.

19.1.2.2 Secure Mode Operation

If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run

mode operation. Secure operation prevents access to Flash or EEPROM other than allowing erasure. For

more information please see Section 19.4.1, “Security”.

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Chapter 19 Background Debug Module (S12XBDMV2)

19.1.2.3 Low-Power Modes

The BDM can be used until all bus masters (e.g., CPU or XGATE) are in stop mode. When CPU is in a

low power mode (wait or stop mode) all BDM ﬁrmware commands as well as the hardware

BACKGROUND command can not be used respectively are ignored. In this case the CPU can not enter

BDM active mode, and only hardware read and write commands are available. Also the CPU can not enter

a low power mode during BDM active mode.

If all bus masters are in stop mode, the BDM clocks are stopped as well. When BDM clocks are disabled

and one of the bus masters exits from stop mode the BDM clocks will restart and BDM will have a soft

reset (clearing the instruction register, any command in progress and disable the ACK function). The BDM

is now ready to receive a new command.

19.1.3 Block Diagram

A block diagram of the BDM is shown in Figure 19-1.

Host

Serial

Interface

Data

System

16-Bit Shift Register

BKGD

Control

Address

Data

Bus Interface

and

Control Logic

TRACE

Instruction Code

and

Control

Clocks

BDMACT

Execution

ENBDM

SDV

Standard BDM Firmware

LOOKUP TABLE

Secured BDM Firmware

LOOKUP TABLE

UNSEC

CLKSW

BDMSTS

Figure 19-1. BDM Block Diagram

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Chapter 19 Background Debug Module (S12XBDMV2)

19.2 External Signal Description

A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate

with the BDM system. During reset, this pin is a mode select input which selects between normal and

special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the

background debug mode.

19.3 Memory Map and Register Deﬁnition

19.3.1 Module Memory Map

Table 19-1 shows the BDM memory map when BDM is active.

Table 19-1. BDM Memory Map

Size

Global Address

Module

(Bytes)

0x7FFF00–0x7FFF0B

0x7FFF0C–0x7FFF0E

0x7FFF0F

BDM registers

BDM ﬁrmware ROM

Family ID (part of BDM ﬁrmware ROM)

BDM ﬁrmware ROM

0x7FFF10–0x7FFFFF

240

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Chapter 19 Background Debug Module (S12XBDMV2)

19.3.2 Register Descriptions

A summary of the registers associated with the BDM is shown in Figure 19-2. Registers are accessed by

host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.

Global

Address

Name

Bit 7

Bit 0

0x7FFF00 Reserved

0x7FFF01

BDMSTS

BDMACT

SDV

TRACE

UNSEC

ENBDM

CLKSW

0x7FFF02 Reserved

0x7FFF03 Reserved

0x7FFF04 Reserved

0x7FFF05 Reserved

0x7FFF06 BDMCCRL

CCR7

CCR6

CCR5

CCR4

CCR3

CCR2

CCR1

CCR9

CCR0

CCR8

0x7FFF07 BDMCCRH R

CCR10

0x7FFF08 BDMGPR

0x7FFF09 Reserved

0x7FFF0A Reserved

0x7FFF0B Reserved

BGAE

BGP6

BGP5

BGP4

BGP3

BGP2

BGP1

BGP0

= Unimplemented, Reserved

= Indeterminate

= Implemented (do not alter)

= Always read zero

Figure 19-2. BDM Register Summary

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Chapter 19 Background Debug Module (S12XBDMV2)

19.3.2.1 BDM Status Register (BDMSTS)

BDMACT

SDV

TRACE

UNSEC

ENBDM

CLKSW

Reset

Special Single-Chip Mode

Emulation Modes

All Other Modes

= Unimplemented, Reserved

= Implemented (do not alter)

= Always read zero

ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but

fully erased (Flash and EEPROM). This is because the ENBDM bit is set by the standard ﬁrmware before a BDM command

can be fully transmitted and executed.

CLKSW is read as 1 by a debugging environment in emulation modes when the device is not secured and read as 0 when

secured.

UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased,

else it is 0 and can only be read if not secure (see also bit description).

Figure 19-3. BDM Status Register (BDMSTS)

Read: All modes through BDM operation when not secured

Write: All modes through BDM operation when not secured, but subject to the following:

— ENBDM should only be set via a BDM hardware command if the BDM ﬁrmware commands

are needed. (This does not apply in special single chip and emulation modes).

— BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by

the standard BDM ﬁrmware lookup table upon exit from BDM active mode.

— CLKSW can only be written via BDM hardware WRITE_BD commands.

— All other bits, while writable via BDM hardware or standard BDM ﬁrmware write commands,

should only be altered by the BDM hardware or standard ﬁrmware lookup table as part of BDM

command execution.

Table 19-2. BDMSTS Field Descriptions

Field

Description

Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made

active to allow ﬁrmware commands to be executed. When disabled, BDM cannot be made active but BDM

hardware commands are still allowed.

ENBDM

0 BDM disabled

1 BDM enabled

Note: ENBDM is set by the ﬁrmware out of reset in special single chip mode and by hardware in emulation

modes. In special single chip mode with the device secured, this bit will not be set by the ﬁrmware until

after the EEPROM and Flash erase verify tests are complete. In emulation modes with the device

secured, the BDM operations are blocked.

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Chapter 19 Background Debug Module (S12XBDMV2)

Table 19-2. BDMSTS Field Descriptions (continued)

Field

Description

BDM Active Status — This bit becomes set upon entering BDM. The standard BDM ﬁrmware lookup table is

BDMACT

then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the

standard BDM ﬁrmware as part of the exit sequence to return to user code and remove the BDM memory from

the map.

0 BDM not active

1 BDM active

SDV

Shift Data Valid — This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as

part of a ﬁrmware or hardware read command or after data has been received as part of a ﬁrmware or hardware

write command. It is cleared when the next BDM command has been received or BDM is exited. SDV is used

by the standard BDM ﬁrmware to control program ﬂow execution.

0 Data phase of command not complete

1 Data phase of command is complete

TRACE1 BDM Firmware Command is Being Executed — This bit gets set when a BDM TRACE1 ﬁrmware

command is ﬁrst recognized. It will stay set until BDM ﬁrmware is exited by one of the following BDM commands:

GO or GO_UNTIL.

TRACE

0 TRACE1 command is not being executed

1 TRACE1 command is being executed

Clock Switch — The CLKSW bit controls which clock the BDM operates with. It is only writable from a hardware

BDM command. A minimum delay of 150 cycles at the clock speed that is active during the data portion of the

command send to change the clock source should occur before the next command can be send. The delay

should be obtained no matter which bit is modiﬁed to effectively change the clock source (either PLLSEL bit or

CLKSW bit). This guarantees that the start of the next BDM command uses the new clock for timing subsequent

BDM communications.

CLKSW

Table 19-3 shows the resulting BDM clock source based on the CLKSW and the PLLSEL (PLL select in the CRG

module, the bit is part of the CLKSEL register) bits.

Note: The BDM alternate clock source can only be selected when CLKSW = 0 and PLLSEL = 1. The BDM serial

interface is now fully synchronized to the alternate clock source, when enabled. This eliminates frequency

restriction on the alternate clock which was required on previous versions. Refer to the device

speciﬁcation to determine which clock connects to the alternate clock source input.

Note: If the acknowledge function is turned on, changing the CLKSW bit will cause the ACK to be at the new

rate for the write command which changes it.

Note: In emulation mode, the CLKSW bit will be set out of RESET.

Unsecure — If the device is secured this bit is only writable in special single chip mode from the BDM secure

ﬁrmware. It is in a zero state as secure mode is entered so that the secure BDM ﬁrmware lookup table is enabled

and put into the memory map overlapping the standard BDM ﬁrmware lookup table.

UNSEC

The secure BDM ﬁrmware lookup table veriﬁes that the on-chip EEPROM and Flash EEPROM are erased. This

being the case, the UNSEC bit is set and the BDM program jumps to the start of the standard BDM ﬁrmware

lookup table and the secure BDM ﬁrmware lookup table is turned off. If the erase test fails, the UNSEC bit will

not be asserted.

0 System is in a secured mode.

1 System is in a unsecured mode.

Note: When UNSEC is set, security is off and the user can change the state of the secure bits in the on-chip

Flash EEPROM. Note that if the user does not change the state of the bits to “unsecured” mode, the

system will be secured again when it is next taken out of reset.After reset this bit has no meaning or effect

when the security byte in the Flash EEPROM is conﬁgured for unsecure mode.

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Chapter 19 Background Debug Module (S12XBDMV2)

Table 19-3. BDM Clock Sources

PLLSEL CLKSW

BDMCLK

Bus clock dependent on oscillator

Alternate clock (refer to the device speciﬁcation to determine the alternate clock source)

Bus clock dependent on the PLL

19.3.2.2 BDM CCR LOW Holding Register (BDMCCRL)

CCR7

CCR6

CCR5

CCR4

CCR3

CCR2

CCR1

CCR0

Reset

Special Single-Chip Mode

All Other Modes

Figure 19-4. BDM CCR LOW Holding Register (BDMCCRL)

Read: All modes through BDM operation when not secured

Write: All modes through BDM operation when not secured

NOTE

When BDM is made active, the CPU stores the content of its CCR register

in the BDMCCRL register. However, out of special single-chip reset, the

BDMCCRL is set to 0xD8 and not 0xD0 which is the reset value of the

CCR register in this CPU mode. Out of reset in all other modes the

BDMCCRL register is read zero.

When entering background debug mode, the BDM CCR LOW holding register is used to save the low byte

of the condition code register of the user’s program. It is also used for temporary storage in the standard

BDM ﬁrmware mode. The BDM CCR LOW holding register can be written to modify the CCR value.

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Chapter 19 Background Debug Module (S12XBDMV2)

19.3.2.3 BDM CCR HIGH Holding Register (BDMCCRH)

CCR10

CCR9

CCR8

Reset

= Unimplemented or Reserved

Figure 19-5. BDM CCR HIGH Holding Register (BDMCCRH)

Read: All modes through BDM operation when not secured

Write: All modes through BDM operation when not secured

When entering background debug mode, the BDM CCR HIGH holding register is used to save the high

byte of the condition code register of the user’s program. The BDM CCR HIGH holding register can be

written to modify the CCR value.

19.3.2.4 BDM Global Page Index Register (BDMGPR)

BGAE

BGP6

BGP5

BGP4

BGP3

BGP2

BGP1

BGP0

Reset

Figure 19-6. BDM Global Page Register (BDMGPR)

Read: All modes through BDM operation when not secured

Write: All modes through BDM operation when not secured

Table 19-4. BDMGPR Field Descriptions

Field

Description

BDM Global Page Access Enable Bit — BGAE enables global page access for BDM hardware and ﬁrmware

read/write instructions The BDM hardware commands used to access the BDM registers (READ_BD_ and

WRITE_BD_) can not be used for global accesses even if the BGAE bit is set.

0 BDM Global Access disabled

BGAE

1 BDM Global Access enabled

6–0

BDM Global Page Index Bits 6–0 — These bits deﬁne the extended address bits from 22 to 16. For more

BGP[6:0]

detailed information regarding the global page window scheme, please refer to the S12X_MMC Block Guide.

19.3.3 Family ID Assignment

The family ID is a 8-bit value located in the ﬁrmware ROM (at global address: 0x7FFF0F). The read-only

value is a unique family ID which is 0xC1 for S12X devices.

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Chapter 19 Background Debug Module (S12XBDMV2)

19.4 Functional Description

The BDM receives and executes commands from a host via a single wire serial interface. There are two

types of BDM commands: hardware and ﬁrmware commands.

Hardware commands are used to read and write target system memory locations and to enter active

background debug mode, see Section 19.4.3, “BDM Hardware Commands”. Target system memory

includes all memory that is accessible by the CPU.

Firmware commands are used to read and write CPU resources and to exit from active background debug

mode, see Section 19.4.4, “Standard BDM Firmware Commands”. The CPU resources referred to are the

accumulator (D), X index register (X), Y index register (Y), stack pointer (SP), and program counter (PC).

Hardware commands can be executed at any time and in any mode excluding a few exceptions as

highlighted (see Section 19.4.3, “BDM Hardware Commands”) and in secure mode (see Section 19.4.1,

“Security”). Firmware commands can only be executed when the system is not secure and is in active

background debug mode (BDM).

19.4.1 Security

If the user resets into special single chip mode with the system secured, a secured mode BDM ﬁrmware

lookup table is brought into the map overlapping a portion of the standard BDM ﬁrmware lookup table.

The secure BDM ﬁrmware veriﬁes that the on-chip EEPROM and Flash EEPROM are erased. This being

the case, the UNSEC and ENBDM bit will get set. The BDM program jumps to the start of the standard

BDM ﬁrmware and the secured mode BDM ﬁrmware is turned off and all BDM commands are allowed.

If the EEPROM or Flash do not verify as erased, the BDM ﬁrmware sets the ENBDM bit, without asserting

UNSEC, and the ﬁrmware enters a loop. This causes the BDM hardware commands to become enabled,

but does not enable the ﬁrmware commands. This allows the BDM hardware to be used to erase the

EEPROM and Flash.

BDM operation is not possible in any other mode than special single chip mode when the device is secured.

The device can only be unsecured via BDM serial interface in special single chip mode. For more

information regarding security, please see the S12X_9SEC Block Guide.

19.4.2 Enabling and Activating BDM

The system must be in active BDM to execute standard BDM ﬁrmware commands. BDM can be activated

only after being enabled. BDM is enabled by setting the ENBDM bit in the BDM status (BDMSTS)

interface, using a hardware command such as WRITE_BD_BYTE.

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Chapter 19 Background Debug Module (S12XBDMV2)

After being enabled, BDM is activated by one of the following :

•

Hardware BACKGROUND command

CPU BGND instruction

External instruction tagging mechanism

Breakpoint force or tag mechanism

When BDM is activated, the CPU ﬁnishes executing the current instruction and then begins executing the

ﬁrmware in the standard BDM ﬁrmware lookup table. When BDM is activated by a breakpoint, the type

of breakpoint used determines if BDM becomes active before or after execution of the next instruction.

NOTE

If an attempt is made to activate BDM before being enabled, the CPU

resumes normal instruction execution after a brief delay. If BDM is not

enabled, any hardware BACKGROUND commands issued are ignored by

the BDM and the CPU is not delayed.

In active BDM, the BDM registers and standard BDM ﬁrmware lookup table are mapped to addresses

0x7FFF00 to 0x7FFFFF. BDM registers are mapped to addresses 0x7FFF00 to 0x7FFF0B. The BDM uses

these registers which are readable anytime by the BDM. However, these registers are not readable by user

programs.

19.4.3 BDM Hardware Commands

Hardware commands are used to read and write target system memory locations and to enter active

background debug mode. Target system memory includes all memory that is accessible by the CPU such

as on-chip RAM, EEPROM, Flash EEPROM, I/O and control registers, and all external memory.

Hardware commands are executed with minimal or no CPU intervention and do not require the system to

be in active BDM for execution, although, they can still be executed in this mode. When executing a

hardware command, the BDM sub-block waits for a free bus cycle so that the background access does not

disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU is

momentarily frozen so that the BDM can steal a cycle. When the BDM ﬁnds a free cycle, the operation

does not intrude on normal CPU operation provided that it can be completed in a single cycle. However,

if an operation requires multiple cycles the CPU is frozen until the operation is complete, even though the

BDM found a free cycle.

The BDM hardware commands are listed in Table 19-5.

The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations

are not normally in the system memory map but share addresses with the application in memory. To

distinguish between physical memory locations that share the same address, BDM memory resources are

enabled just for the READ_BD and WRITE_BD access cycle. This allows the BDM to access BDM

locations unobtrusively, even if the addresses conﬂict with the application memory map.

1. BDM is enabled and active immediately out of special single-chip reset.

2. This method is provided by the S12X_DBG module.

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Chapter 19 Background Debug Module (S12XBDMV2)

Table 19-5. Hardware Commands

Opcode

(hex)

Command

Data

Description

BACKGROUND

None

Enter background mode if ﬁrmware is enabled. If enabled, an ACK will be

issued when the part enters active background mode.

ACK_ENABLE

ACK_DISABLE

READ_BD_BYTE

None

Enable Handshake. Issues an ACK pulse after the command is executed.

Disable Handshake. This command does not issue an ACK pulse.

16-bit address Read from memory with standard BDM ﬁrmware lookup table in map.

16-bit data out Odd address data on low byte; even address data on high byte.

READ_BD_WORD

READ_BYTE

16-bit address Read from memory with standard BDM ﬁrmware lookup table in map.

16-bit data out Must be aligned access.

16-bit address Read from memory with standard BDM ﬁrmware lookup table out of map.

16-bit data out Odd address data on low byte; even address data on high byte.

READ_WORD

WRITE_BD_BYTE

WRITE_BD_WORD

WRITE_BYTE

WRITE_WORD

NOTE:

16-bit address Read from memory with standard BDM ﬁrmware lookup table out of map.

16-bit data out Must be aligned access.

16-bit address Write to memory with standard BDM ﬁrmware lookup table in map.

16-bit data in Odd address data on low byte; even address data on high byte.

16-bit address Write to memory with standard BDM ﬁrmware lookup table in map.

16-bit data in Must be aligned access.

16-bit address Write to memory with standard BDM ﬁrmware lookup table out of map.

16-bit data in Odd address data on low byte; even address data on high byte.

16-bit address Write to memory with standard BDM ﬁrmware lookup table out of map.

16-bit data in Must be aligned access.

If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is

complete for all BDM WRITE commands.

19.4.4 Standard BDM Firmware Commands

Firmware commands are used to access and manipulate CPU resources. The system must be in active

BDM to execute standard BDM ﬁrmware commands, see Section 19.4.2, “Enabling and Activating

BDM”. Normal instruction execution is suspended while the CPU executes the ﬁrmware located in the

standard BDM ﬁrmware lookup table. The hardware command BACKGROUND is the usual way to

activate BDM.

As the system enters active BDM, the standard BDM ﬁrmware lookup table and BDM registers become

visible in the on-chip memory map at 0x7FFF00–0x7FFFFF, and the CPU begins executing the standard

BDM ﬁrmware. The standard BDM ﬁrmware watches for serial commands and executes them as they are

received.

The ﬁrmware commands are shown in Table 19-6.

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Chapter 19 Background Debug Module (S12XBDMV2)

Table 19-6. Firmware Commands

Opcode

(hex)

Command

Data

Description

READ_NEXT

16-bit data out Increment X index register by 2 (X = X + 2), then read word X points to.

16-bit data out Read program counter.

READ_PC

READ_D

READ_X

READ_Y

READ_SP

16-bit data out Read D accumulator.

16-bit data out Read X index register.

16-bit data out Read Y index register.

16-bit data out Read stack pointer.

WRITE_NEXT<f-hel

vetica><st-superscri

pt>

16-bit data in Increment X index register by 2 (X = X + 2), then write word to location

pointed to by X.

WRITE_PC

WRITE_D

WRITE_X

WRITE_Y

WRITE_SP

16-bit data in Write program counter.

16-bit data in Write D accumulator.

16-bit data in Write X index register.

16-bit data in Write Y index register.

16-bit data in Write stack pointer.

none

Go to user program. If enabled, ACK will occur when leaving active

background mode.

GO_UNTIL

Go to user program. If enabled, ACK will occur upon returning to active

background mode.

TRACE1

Execute one user instruction then return to active BDM. If enabled,

ACK will occur upon returning to active background mode.

TAGGO -> GO

(Previous enable tagging and go to user program.)

This command will be deprecated and should not be used anymore.

Opcode will be executed as a GO command.

If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is

complete for all BDM WRITE commands.

When the ﬁrmware command READ_NEXT or WRITE_NEXT is used to access the BDM address space the BDM resources

are accessed rather than user code. Writing BDM ﬁrmware is not possible.

System stop disables the ACK function and ignored commands will not have an ACK-pulse (e.g., CPU in stop or wait mode).

The GO_UNTIL command will not get an Acknowledge if CPU executes the wait or stop instruction before the “UNTIL”

condition (BDM active again) is reached (see Section 19.4.7, “Serial Interface Hardware Handshake Protocol” last Note).

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Chapter 19 Background Debug Module (S12XBDMV2)

19.4.5 BDM Command Structure

Hardware and ﬁrmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a

16-bit data word depending on the command. All the read commands return 16 bits of data despite the byte

or word implication in the command name.

8-bit reads return 16-bits of data, of which, only one byte will contain valid

data. If reading an even address, the valid data will appear in the MSB. If

reading an odd address, the valid data will appear in the LSB.

16-bit misaligned reads and writes are generally not allowed. If attempted

by BDM hardware command, the BDM will ignore the least signiﬁcant bit

of the address and will assume an even address from the remaining bits.

The following cycle count information is only valid when the external wait

function is not used (see wait bit of EBI sub-block). During an external wait

the BDM can not steal a cycle. Hence be careful with the external wait

function if the BDM serial interface is much faster than the bus, because of

the BDM soft-reset after time-out (see Section 19.4.11, “Serial

Communication Time Out”).

For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending

the address before attempting to obtain the read data. This is to be certain that valid data is available in the

BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait

150 bus clock cycles after sending the data to be written before attempting to send a new command. This

is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle

delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a

free cycle before stealing a cycle.

For ﬁrmware read commands, the external host should wait at least 48 bus clock cycles after sending the

command opcode and before attempting to obtain the read data. This includes the potential of extra cycles

when the access is external and stretched (+1 to maximum +7 cycles) or to registers of the PRU (port

replacement unit) in emulation mode. The 48 cycle wait allows enough time for the requested data to be

made available in the BDM shift register, ready to be shifted out.

NOTE

This timing has increased from previous BDM modules due to the new

capability in which the BDM serial interface can potentially run faster than

the bus. On previous BDM modules this extra time could be hidden within

the serial time.

For ﬁrmware write commands, the external host must wait 36 bus clock cycles after sending the data to be

written before attempting to send a new command. This is to avoid disturbing the BDM shift register

before the write has been completed.

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Chapter 19 Background Debug Module (S12XBDMV2)

The external host should wait at least for 76 bus clock cycles after a TRACE1 or GO command before

starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM

ﬁrmware lookup table and resume execution of the user code. Disturbing the BDM shift register

prematurely may adversely affect the exit from the standard BDM ﬁrmware lookup table.

NOTE

If the bus rate of the target processor is unknown or could be changing or the

external wait function is used, it is recommended that the ACK

(acknowledge function) is used to indicate when an operation is complete.

When using ACK, the delay times are automated.

Figure 19-7 represents the BDM command structure. The command blocks illustrate a series of eight bit

times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles

in the high state. The time for an 8-bit command is 8 × 16 target clock cycles.

8 Bits

AT ~16 TC/Bit

16 Bits

AT ~16 TC/Bit

150-BC

Delay

16 Bits

AT ~16 TC/Bit

Hardware

Read

Command

Address

Data

150-BC

Delay

Hardware

Write

Command

Address

Data

48-BC

DELAY

Firmware

Read

Command

Data

36-BC

DELAY

Firmware

Write

Command

Data

76-BC

Delay

GO,

TRACE

Command

BC = Bus Clock Cycles

TC = Target Clock Cycles

Figure 19-7. BDM Command Structure

1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See Section 19.4.6, “BDM Serial Interface”

and Section 19.3.2.1, “BDM Status Register (BDMSTS)” for information on how serial clock rate is selected.

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19.4.6 BDM Serial Interface

The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode

select input which selects between normal and special modes of operation. After reset, this pin becomes

the dedicated serial interface pin for the BDM.

The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see

Section 19.3.2.1, “BDM Status Register (BDMSTS)”. This clock will be referred to as the target clock in

the following explanation.

The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on

the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is

transmitted or received. Data is transferred most signiﬁcant bit (MSB) ﬁrst at 16 target clock cycles per

bit. The interface times out if 512 clock cycles occur between falling edges from the host.

The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all

times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically

drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide

brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host

for transmit cases and the target for receive cases.

The timing for host-to-target is shown in Figure 19-8 and that of target-to-host in Figure 19-9 and

Figure 19-10. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Since

the host and target are operating from separate clocks, it can take the target system up to one full clock

cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the

host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle

earlier. Synchronization between the host and target is established in this manner at the start of every bit

time.

Figure 19-8 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a

target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the

host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten

target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic

requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1

transmission.

Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven

signals.

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BDM Clock

(Target MCU)

Host

Transmit 1

Host

Transmit 0

Perceived

Target Senses Bit

Start of Bit Time

Earliest

Start of

Next Bit

10 Cycles

Synchronization

Uncertainty

Figure 19-8. BDM Host-to-Target Serial Bit Timing

The receive cases are more complicated. Figure 19-9 shows the host receiving a logic 1 from the target

system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the

host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the

BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must

release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the

perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it

started the bit time.

BDM Clock

(Target MCU)

Host

Drive to

High-Impedance

BKGD Pin

Target System

Speedup

Pulse

High-Impedance

Perceived

Start of Bit Time

R-C Rise

BKGD Pin

10 Cycles

Earliest

Start of

Next Bit

Host Samples

BKGD Pin

Figure 19-9. BDM Target-to-Host Serial Bit Timing (Logic 1)

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Chapter 19 Background Debug Module (S12XBDMV2)

Figure 19-10 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the

target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of

the bit time as perceived by the target. The host initiates the bit time but the target ﬁnishes it. Since the

target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then brieﬂy

drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after

starting the bit time.

BDM Clock

(Target MCU)

Host

High-Impedance

Speedup Pulse

Drive to

BKGD Pin

Target System

Drive and

Speedup Pulse

Perceived

Start of Bit Time

BKGD Pin

10 Cycles

Earliest

Start of

Next Bit

Host Samples

BKGD Pin

Figure 19-10. BDM Target-to-Host Serial Bit Timing (Logic 0)

19.4.7 Serial Interface Hardware Handshake Protocol

BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Since the BDM

clock source can be asynchronously related to the bus frequency, when CLKSW = 0, it is very helpful to

provide a handshake protocol in which the host could determine when an issued command is executed by

the CPU. The alternative is to always wait the amount of time equal to the appropriate number of cycles at

the slowest possible rate the clock could be running. This sub-section will describe the hardware

handshake protocol.

The hardware handshake protocol signals to the host controller when an issued command was successfully

executed by the target. This protocol is implemented by a 16 serial clock cycle low pulse followed by a

brief speedup pulse in the BKGD pin. This pulse is generated by the target MCU when a command, issued

by the host, has been successfully executed (see Figure 19-11). This pulse is referred to as the ACK pulse.

After the ACK pulse has ﬁnished: the host can start the bit retrieval if the last issued command was a read

command, or start a new command if the last command was a write command or a control command

(BACKGROUND, GO, GO_UNTIL or TRACE1). The ACK pulse is not issued earlier than 32 serial clock

cycles after the BDM command was issued. The end of the BDM command is assumed to be the 16th tick

of the last bit. This minimum delay assures enough time for the host to perceive the ACK pulse. Note also

that, there is no upper limit for the delay between the command and the related ACK pulse, since the

command execution depends upon the CPU bus frequency, which in some cases could be very slow

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Chapter 19 Background Debug Module (S12XBDMV2)

compared to the serial communication rate. This protocol allows a great ﬂexibility for the POD designers,

since it does not rely on any accurate time measurement or short response time to any event in the serial

communication.

BDM Clock

(Target MCU)

16 Cycles

Target

Transmits

ACK Pulse

High-Impedance

32 Cycles

High-Impedance

Speedup Pulse

Minimum Delay

From the BDM Command

BKGD Pin

Earliest

Start of

Next Bit

16th Tick of the

Last Command Bit

Figure 19-11. Target Acknowledge Pulse (ACK)

NOTE

If the ACK pulse was issued by the target, the host assumes the previous

command was executed. If the CPU enters wait or stop prior to executing a

hardware command, the ACK pulse will not be issued meaning that the

BDM command was not executed. After entering wait or stop mode, the

BDM command is no longer pending.

Figure 19-12 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE

instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the

address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed

(free or stolen) by the BDM and it executes the READ_BYTE operation. Having retrieved the data, the

BDM issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved.

After detecting the ACK pulse, the host initiates the byte retrieval process. Note that data is sent in the form

of a word and the host needs to determine which is the appropriate byte based on whether the address was

odd or even.

Target

Host

(2) Bytes are

Retrieved

New BDM

Command

BKGD Pin

READ_BYTE

Host

Byte Address

Target

Host

Target

BDM Issues the

ACK Pulse (out of scale)

BDM Executes the

READ_BYTE Command

BDM Decodes

the Command

Figure 19-12. Handshake Protocol at Command Level

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Chapter 19 Background Debug Module (S12XBDMV2)

Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK

handshake pulse is initiated by the target MCU by issuing a negative edge in the BKGD pin. The hardware

handshake protocol in Figure 19-11 speciﬁes the timing when the BKGD pin is being driven, so the host

should follow this timing constraint in order to avoid the risk of an electrical conﬂict in the BKGD pin.

NOTE

The only place the BKGD pin can have an electrical conﬂict is when one

side is driving low and the other side is issuing a speedup pulse (high). Other

“highs” are pulled rather than driven. However, at low rates the time of the

speedup pulse can become lengthy and so the potential conﬂict time

becomes longer as well.

The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not

acknowledge by an ACK pulse, the host needs to abort the pending command ﬁrst in order to be able to

issue a new BDM command. When the CPU enters wait or stop while the host issues a hardware command

(e.g., WRITE_BYTE), the target discards the incoming command due to the wait or stop being detected.

Therefore, the command is not acknowledged by the target, which means that the ACK pulse will not be

issued in this case. After a certain time the host (not aware of stop or wait) should decide to abort any

possible pending ACK pulse in order to be sure a new command can be issued. Therefore, the protocol

provides a mechanism in which a command, and its corresponding ACK, can be aborted.

NOTE

The ACK pulse does not provide a time out. This means for the GO_UNTIL

command that it can not be distinguished if a stop or wait has been executed

(command discarded and ACK not issued) or if the “UNTIL” condition

(BDM active) is just not reached yet. Hence in any case where the ACK

pulse of a command is not issued the possible pending command should be

aborted before issuing a new command. See the handshake abort procedure

described in Section 19.4.8, “Hardware Handshake Abort Procedure”.

19.4.8 Hardware Handshake Abort Procedure

The abort procedure is based on the SYNC command. In order to abort a command, which had not issued

the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving

it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a

speedup pulse. By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol,

see Section 19.4.9, “SYNC — Request Timed Reference Pulse”, and assumes that the pending command

and therefore the related ACK pulse, are being aborted. Therefore, after the SYNC protocol has been

completed the host is free to issue new BDM commands. For Firmware READ or WRITE commands it

can not be guaranteed that the pending command is aborted when issuing a SYNC before the

corresponding ACK pulse. There is a short latency time from the time the READ or WRITE access begins

until it is ﬁnished and the corresponding ACK pulse is issued. The latency time depends on the ﬁrmware

READ or WRITE command that is issued and if the serial interface is running on a different clock rate

than the bus. When the SYNC command starts during this latency time the READ or WRITE command

will not be aborted, but the corresponding ACK pulse will be aborted. A pending GO, TRACE1 or

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Chapter 19 Background Debug Module (S12XBDMV2)

GO_UNTIL command can not be aborted. Only the corresponding ACK pulse can be aborted by the

SYNC command.

Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in

the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command.

The ACK is actually aborted when a negative edge is perceived by the target in the BKGD pin. The short

abort pulse should have at least 4 clock cycles keeping the BKGD pin low, in order to allow the negative

edge to be detected by the target. In this case, the target will not execute the SYNC protocol but the pending

command will be aborted along with the ACK pulse. The potential problem with this abort procedure is

when there is a conﬂict between the ACK pulse and the short abort pulse. In this case, the target may not

perceive the abort pulse. The worst case is when the pending command is a read command (i.e.,

READ_BYTE). If the abort pulse is not perceived by the target the host will attempt to send a new

command after the abort pulse was issued, while the target expects the host to retrieve the accessed

memory byte. In this case, host and target will run out of synchronism. However, if the command to be

aborted is not a read command the short abort pulse could be used. After a command is aborted the target

assumes the next negative edge, after the abort pulse, is the ﬁrst bit of a new BDM command.

NOTE

The details about the short abort pulse are being provided only as a reference

for the reader to better understand the BDM internal behavior. It is not

recommended that this procedure be used in a real application.

Since the host knows the target serial clock frequency, the SYNC command (used to abort a command)

does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC

very close to the 128 serial clock cycles length. Providing a small overhead on the pulse length in order to

assure the SYNC pulse will not be misinterpreted by the target. See Section 19.4.9, “SYNC — Request

Timed Reference Pulse”.

Figure 19-13 shows a SYNC command being issued after a READ_BYTE, which aborts the

READ_BYTE command. Note that, after the command is aborted a new command could be issued by the

host computer.

READ_BYTE CMD is Aborted

by the SYNC Request

(Out of Scale)

SYNC Response

From the Target

(Out of Scale)

BKGD Pin READ_BYTE

Host

Memory Address

Target

READ_STATUS

New BDM Command

Host Target

Host

Target

BDM Decode

New BDM Command

and Starts to Execute

the READ_BYTE Command

Figure 19-13. ACK Abort Procedure at the Command Level

NOTE

Figure 19-13 does not represent the signals in a true timing scale

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Chapter 19 Background Debug Module (S12XBDMV2)

Figure 19-14 shows a conﬂict between the ACK pulse and the SYNC request pulse. This conﬂict could

occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode.

Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being

connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this

case, there is an electrical conﬂict between the ACK speedup pulse and the SYNC pulse. Since this is not

a probable situation, the protocol does not prevent this conﬂict from happening.

At Least 128 Cycles

BDM Clock

(Target MCU)

ACK Pulse

Target MCU

High-Impedance

Electrical Conﬂict

Drives to

BKGD Pin

Speedup Pulse

Host and

Target Drive

to BKGD Pin

Host

Drives SYNC

To BKGD Pin

Host SYNC Request Pulse

BKGD Pin

16 Cycles

Figure 19-14. ACK Pulse and SYNC Request Conﬂict

NOTE

This information is being provided so that the MCU integrator will be aware

that such a conﬂict could eventually occur.

The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE

BDM commands. This provides backwards compatibility with the existing POD devices which are not

able to execute the hardware handshake protocol. It also allows for new POD devices, that support the

hardware handshake protocol, to freely communicate with the target device. If desired, without the need

for waiting for the ACK pulse.

The commands are described as follows:

•

ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse

when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the

ACK pulse as a response.

•

ACK_DISABLE — disables the ACK pulse protocol. In this case, the host needs to use the worst

case delay time at the appropriate places in the protocol.

The default state of the BDM after reset is hardware handshake protocol disabled.

All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then

ready for reading out by the BKGD serial pin. All the write commands will ACK (if enabled) after the data

has been received by the BDM through the BKGD serial pin and when the data bus cycle is complete. See

Section 19.4.3, “BDM Hardware Commands” and Section 19.4.4, “Standard BDM Firmware Commands”

for more information on the BDM commands.

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Chapter 19 Background Debug Module (S12XBDMV2)

The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be

used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is

issued in response to this command, the host knows that the target supports the hardware handshake

protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued. In

this case, the ACK_ENABLE command is ignored by the target since it is not recognized as a valid

command.

The BACKGROUND command will issue an ACK pulse when the CPU changes from normal to

background mode. The ACK pulse related to this command could be aborted using the SYNC command.

The GO command will issue an ACK pulse when the CPU exits from background mode. The ACK pulse

related to this command could be aborted using the SYNC command.

The GO_UNTIL command is equivalent to a GO command with exception that the ACK pulse, in this

case, is issued when the CPU enters into background mode. This command is an alternative to the GO

command and should be used when the host wants to trace if a breakpoint match occurs and causes the

CPU to enter active background mode. Note that the ACK is issued whenever the CPU enters BDM, which

could be caused by a breakpoint match or by a BGND instruction being executed. The ACK pulse related

to this command could be aborted using the SYNC command.

The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode

after one instruction of the application program is executed. The ACK pulse related to this command could

be aborted using the SYNC command.

19.4.9 SYNC — Request Timed Reference Pulse

The SYNC command is unlike other BDM commands because the host does not necessarily know the

correct communication speed to use for BDM communications until after it has analyzed the response to

the SYNC command. To issue a SYNC command, the host should perform the following steps:

1. Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication

frequency (the lowest serial communication frequency is determined by the crystal oscillator or the

clock chosen by CLKSW.)

2. Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically

one cycle of the host clock.)

3. Remove all drive to the BKGD pin so it reverts to high impedance.

4. Listen to the BKGD pin for the sync response pulse.

Upon detecting the SYNC request from the host, the target performs the following steps:

1. Discards any incomplete command received or bit retrieved.

2. Waits for BKGD to return to a logic one.

3. Delays 16 cycles to allow the host to stop driving the high speedup pulse.

4. Drives BKGD low for 128 cycles at the current BDM serial communication frequency.

5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD.

6. Removes all drive to the BKGD pin so it reverts to high impedance.

The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed

for subsequent BDM communications. Typically, the host can determine the correct communication speed

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Chapter 19 Background Debug Module (S12XBDMV2)

within a few percent of the actual target speed and the communication protocol can easily tolerate speed

errors of several percent.

As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is

discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication. After the

SYNC response, the target will consider the next negative edge (issued by the host) as the start of a new

BDM command or the start of new SYNC request.

Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the

same as in a regular SYNC command. Note that one of the possible causes for a command to not be

acknowledged by the target is a host-target synchronization problem. In this case, the command may not

have been understood by the target and so an ACK response pulse will not be issued.

19.4.10 Instruction Tracing

When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM

ﬁrmware and executes a single instruction in the user code. Once this has occurred, the CPU is forced to

return to the standard BDM ﬁrmware and the BDM is active and ready to receive a new command. If the

TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or

tracing through the user code one instruction at a time.

If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but

no user instruction is executed. Once back in standard BDM ﬁrmware execution, the program counter

points to the ﬁrst instruction in the interrupt service routine.

Be aware when tracing through the user code that the execution of the user code is done step by step but

all peripherals are free running. Hence possible timing relations between CPU code execution and

occurrence of events of other peripherals no longer exist.

When tracing through user code which contains stop or wait instructions the following will happen when

the stop or wait instruction is traced:

The CPU enters stop or wait mode and the TRACE1 command can not be ﬁnished before leaving

the low power mode. This is the case because BDM active mode can not be entered after CPU

executed the stop instruction. However all BDM hardware commands except the BACKGROUND

command are operational after tracing a stop or wait instruction and still being in stop or wait

mode. If system stop mode is entered (all bus masters are in stop mode) no BDM command is

operational.

As soon as stop or wait mode is exited the CPU enters BDM active mode and the saved PC value

points to the entry of the corresponding interrupt service routine.

In case the handshake feature is enabled the corresponding ACK pulse of the TRACE1 command

will be discarded when tracing a stop or wait instruction. Hence there is no ACK pulse when BDM

active mode is entered as part of the TRACE1 command after CPU exited from stop or wait mode.

All valid commands sent during CPU being in stop or wait mode or after CPU exited from stop or

wait mode will have an ACK pulse. The handshake feature becomes disabled only when system

stop mode has been reached. Hence after a system stop mode the handshake feature must be

enabled again by sending the ACK_ENABLE command.

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Chapter 19 Background Debug Module (S12XBDMV2)

19.4.11 Serial Communication Time Out

The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If

BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command

was issued. In this case, the target will keep waiting for a rising edge on BKGD in order to answer the

SYNC request pulse. If the rising edge is not detected, the target will keep waiting forever without any

time-out limit.

Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as

a valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge

marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock

cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting

memory or the operating mode of the MCU. This is referred to as a soft-reset.

If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will

occur causing the command to be disregarded. The data is not available for retrieval after the time-out has

occurred. This is the expected behavior if the handshake protocol is not enabled. However, consider the

behavior where the BDM is running in a frequency much greater than the CPU frequency. In this case, the

command could time out before the data is ready to be retrieved. In order to allow the data to be retrieved

even with a large clock frequency mismatch (between BDM and CPU) when the hardware handshake

protocol is enabled, the time out between a read command and the data retrieval is disabled. Therefore, the

host could wait for more then 512 serial clock cycles and still be able to retrieve the data from an issued

read command. However, once the handshake pulse (ACK pulse) is issued, the time-out feature is

re-activated, meaning that the target will time out after 512 clock cycles. Therefore, the host needs to

retrieve the data within a 512 serial clock cycles time frame after the ACK pulse had been issued. After

that period, the read command is discarded and the data is no longer available for retrieval. Any negative

edge in the BKGD pin after the time-out period is considered to be a new command or a SYNC request.

Note that whenever a partially issued command, or partially retrieved data, has occurred the time out in the

serial communication is active. This means that if a time frame higher than 512 serial clock cycles is

observed between two consecutive negative edges and the command being issued or data being retrieved

is not complete, a soft-reset will occur causing the partially received command or data retrieved to be

disregarded. The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the

target as the start of a new BDM command, or the start of a SYNC request pulse.

ff12

READ_BACK

equ

$ff12

;S12X read back value to solve MUCts02411

;never touch data at this address !!!!

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Chapter 19 Background Debug Module (S12XBDMV2)

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Chapter 20

Debug (S12XDBGV2)

20.1 Introduction

The DBG module provides an on-chip trace buffer with ﬂexible triggering capability to allow non-intrusive

debug of application software. The DBG module is optimized for the HCS12X 16-bit architecture and

allows debugging of both CPU and XGATE module operations.

Typically the DBG module is used in conjunction with the BDM module, whereby the user conﬁgures the

DBG module for a debugging session over the BDM interface. Once conﬁgured the DBG module is armed

and the device leaves BDM mode returning control to the user program, which is then monitored by the

DBG module. Alternatively, the DBG module can be conﬁgured over a serial interface using SWI routines.

Comparators monitor the bus activity of the CPU and XGATE modules. When a match occurs, the control

logic can trigger the state sequencer to a new state or tag an opcode. A tag hit, which occurs when the

tagged opcode reaches the execution stage of the instruction queue, can also cause a state transition.

On a transition to the ﬁnal state, bus tracing is triggered and/or a breakpoint can be generated. Independent

of comparator matches, a transition to ﬁnal state with associated tracing and breakpoint can be triggered

by the external TAGHI and TAGLO signals. This is done by an XGATE module S/W breakpoint request

or by writing to the TRIG control bit.

The trace buffer is visible through a 2-byte window in the register address map and can be read out using

standard 16-bit word reads. Tracing is disabled when the MCU system is secured.

20.1.1 Glossary of Terms

COF: Change Of Flow. Change in the program ﬂow due to a conditional branch, indexed jump or interrupt.

BDM : Background Debug Mode

DUG: Device User Guide, describing the features of the device into which the DBG is integrated.

WORD: 16 bit data entity

Data Line : 64 bit data entity

XGATE : S12X family programmable Direct Memory Access Module

CPU : S12X_CPU module

Tag : Tags can be attached to XGATE or CPU opcodes as they enter the instruction pipe. If the tagged

opcode reaches the execution stage a tag hit occurs.

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Chapter 20 Debug (S12XDBGV2)

20.1.2 Features

•

Four comparators (A, B, C, and D):

— Comparators A and C compare the full address and the full 16-bit data bus

— Comparators A and C feature a data bus mask register

— Comparators B and D compare the full address bus only

— Each comparator can be conﬁgured to monitor either CPU or XGATE busses

— Each comparator features control of R/W and byte/word access cycles

— Comparisons can be used as triggers for the state sequencer

Three comparator modes:

•

— Simple address/data comparator match mode

— Inside address range mode, Addmin ≤ Address ≤ Addmax

— Outside address range match mode, Address < Addmin or Address > Addmax

Two types of triggers:

•

— Tagged: triggers just before a speciﬁc instruction begins execution

— Force: triggers on the ﬁrst instruction boundary after a match occurs.

Three types of breakpoints:

— CPU breakpoint entering BDM on breakpoint (BDM)

— CPU breakpoint executing SWI on breakpoint (SWI)

— XGATE breakpoint

•

Three trigger modes independent of comparators:

— External instruction tagging (associated with CPU instructions only)

— XGATE S/W breakpoint request

— TRIG bit immediate software trigger

Three trace modes:

— Normal: change of ﬂow (COF) bus information is stored (see Section 20.4.5.2.1, “Normal

Mode”) for change of ﬂow deﬁnition.

— Loop1: same as normal but inhibits consecutive duplicate source address entries

— Detail: address and data for all cycles except free cycles and opcode fetches are stored

4-stage state sequencer for trace buffer control:

•

— Tracing session trigger linked to ﬁnal state of state sequencer

— Begin, end, and mid alignment of tracing to trigger

20.1.3 Modes of Operation

The DBG module can be used in all MCU functional modes.

During BDM hardware accesses and when the BDM module is active, CPU monitoring is disabled. Thus

breakpoints, comparators and bus tracing mapped to the CPU are disabled but accessing the DBG registers,

including comparator registers, is still possible. While in active BDM or during hardware BDM accesses,

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Chapter 20 Debug (S12XDBGV2)

XGATE activity can still be compared, traced and can be used to generate a breakpoint to the XGATE

module. When the CPU enters active BDM mode through a BACKGROUND command, with the DBG

module armed, the DBG remains armed.

The DBG module tracing is disabled if the MCU is secure. Breakpoints can however still be generated if

the MCU is secure.

Table 20-1. Mode Dependent Restriction Summary

BDM

Enable

BDM

Active

MCU

Secure

Comparator Matches

Enabled

Breakpoints

Possible

Tagging

Possible

Tracing

Possible

Yes

Only SWI

Yes

Active BDM not possible when not enabled

Yes

XGATE only

20.1.4 Block Diagram

Figure 20-1 shows a block diagram of the debug module.