Excalibur electronic DJ Equipment A MNL NIOSPROG 011 User Manual

Table 5. Register Groups...............................................................................................................................2

Table 6. Programmer’s Model......................................................................................................................3

Table 7. Condition Code Flags .....................................................................................................................6

Table 8. Typical 32-bit Nios CPU Program/Data Memory at Address 0x0100...................................7

Table 9. N-bit-wide Peripheral at Address 0x0100 (32-bit Nios CPU) ...................................................7

Table 10. Instructions Using 5/16-bit Immediate Values ........................................................................11

Table 11. Instructions Using Full Width Register-indirect Addressing.................................................12

Table 12. Instructions Using Partial Width Register-indirect Addressing ............................................12

Table 13. Instructions Using Full Width Register-indirect with Offset Addressing............................13

Table 14. Instructions Using Partial Width Register-indirect with Offset Addressing .......................14

Table 15. BR Branch Delay Slot Example....................................................................................................23

Table 16. Notation Details.............................................................................................................................25

Table 17. 32-bit Major Opcode Table...........................................................................................................28

Table 18. GNU Compiler/Assembler Pseudo-instructions.....................................................................31

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Notes:

xii

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Overview

The Nios^TMembedded processor is a soft core CPU optimized for

programmable logic and system-on-a-programmable chip (SOPC)

integration. It is a configurable, general-purpose RISC processor that can

be combined with user logic and programmed into an Altera

Introduction

programmable logic device (PLD). The Nios CPU can be configured for a

wide range of applications. A 16-bit Nios CPU core running a small

program out of an on-chip ROM makes an effective sequencer or

controller, taking the place of a hard-coded state machine. A 32-bit Nios

CPU core with external FLASH program storage and large external main

memory is a powerful 32-bit embedded processor system.

Audience

This reference manual is for software and hardware engineers creating

system design modules using the Excalibur Development Kit, featuring

the Nios embedded processor. This manual assumes you are familiar with

electronics, microprocessors, and assembly language programming. To

become familiar with the conventions used with the Nios CPU, see

Table 16 on page 25.

The Nios CPU is a pipelined, single-issue RISC processor in which most

instructions run in a single clock cycle. The Nios instruction set is targeted

for compiled embedded applications. The 16-bit and 32-bit Nios CPU

have native-word sizes of 16 bits and 32 bits, respectively, meaning the

16-bit Nios CPU has a native-word size of a half-word, while the 32-bit

Nios CPU has a native-word size of a word. In Nios, byte refers to an 8-bit

quantity, half-word refers to a 16-bit quantity, and word refers to a 32-bit

quantity. The Nios family of soft core processors includes 32-bit and 16-bit

architecture variants.

Nios CPU

Overview

Table 4. Nios CPU Architecture

Nios CPU Details

32-bit Nios CPU

16-bit Nios CPU

Data bus size (bits)

ALU width (bits)

Internal register width (bits)

Address bus size (bits)

Instruction size (bits)

Logic cells (typical)

1700

1100

f_max(EP20K200E –1)

Up to 50MHz

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Overview

The Nios CPU ships with the GNUPro compiler and debugger from

Cygnus, an industry-standard open-source C/C++ compiler, linker and

debugger toolkit. The GNUPro toolkit includes a C/C++ compiler, macro-

assembler, linker, debugger, binary utilities, and libraries.

The Nios instruction set is tailored to support programs compiled from C

and C++. It includes a standard set of arithmetic and logical operations,

and instruction support for bit operations, byte extraction, data

movement, control flow modification, and conditionally executed

instructions, which can be useful in eliminating short conditional

branches.

Instruction Set

This section describes the organization of the Nios CPU general-purpose

registers and control registers. The Nios CPU architecture has a large

general-purpose register file, several machine-control registers, a

program counter, and the K register used for instruction prefixing.

Overview

General-Purpose Registers

The general-purpose registers are 32 bits wide in the 32-bit Nios CPU and

16 bits wide in the 16-bit Nios CPU. The register file size is configurable

and contains a total of either 128, 256, or 512 registers. The software can

access the registers using a 32-register-long sliding window that moves

with a 16-register granularity. This sliding window can traverse the entire

The register window is divided into four even sections as shown in

Table 5. The lowest eight registers (%r0-%r7) are global registers, also

known as %g0-%g7. These global registers do not change with the

movement or position of the window, but remain accessible as

(%g0-%g7). The top 24 registers (%r8-%r31) in the register file are

accessible through the current window.

Table 5. Register Groups

In registers

%r24-%r31 or %i0-%i7

%r16-%r23 or %L0-%L7

Local registers

Out registers

Global registers

%r8-%r15

%r0-%r7

or %o0-%o7

or %g0-%g7

The top eight registers (%i0-%i7) are known as in registers, the next eight

(%L0-%L7) as local registers, and the other eight (%o0-%o7) are known as

out registers. When a register window moves down 16-registers (as it does

for a SAVE instruction), the out registers become the in registers of the

new window position. Also, the local and in registers of the last window

position become inaccessible. See Table 6 for more detailed information.

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GettingOverview

Table 6. Programmer’s Model

16 15

%i7 %r31

SAVED return-address

%i6 %r30

%i5 %r29

%fp—frame pointer

%i4 %r28

%i3 %r27

%i2 %r26

%i1 %r25

%i0 %r24

%L7 %r23

%L6 %r22

%L5 %r21

%L4 %r20

%L3 %r19

%L2 %r18

Base-pointer 3 for STP/LDP (or general-purpose local)

Base-pointer 2 for STP/LDP (or general-purpose local)

Base-pointer 1 for STP/LDP (or general-purpose local)

Base-pointer 0 for STP/LDP (or general-purpose local)

current return-address

%L1 %r17

%L0 %r16

%o7 %r15

%o6 %r14

%o5 %r13

%o4 %r12

%o3 %r11

%o2 %r10

%o1 %r9

%o0 %r8

%sp-Stack Pointer

%g7 %r7

%g6 %r6

%g5 %r5

%g4 %r4

%g3 %r3

%g2 %r2

%g1 %r1

%g0 %r0

K REGISTER

16 15

32 31

%ctl9 CLR_IE

Any write (WRCTL) operation to this register sets STATUS[15] (IE)=0. Result of any read-operation (RCTL)

is undefined.

%ctl8 SET_IE

Any write (WRCTL) operation to this register sets STATUS[15] (IE)=1. Result of any read-operation (RCTL)

is undefined.

%ctl7

%ctl6

%ctl5

%ctl4

%ctl3

—

— reserved —

%ctl2 WVALID

%ctl1 ISTATUS

%ctl0 STATUS

HI_LIMIT

Saved Status

CWP

LO_LIMIT

IPRI

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Overview

The K Register

The K register is an 11-bit prefix value and is always set to 0 by every

instruction except PFX. A PFX instruction sets K directly from the IMM11

instruction field. Register K contains a non-zero value only for an

instruction immediately following PFX.

A PFX instruction disables interrupts for one cycle, so the two-instruction

PFX sequence is an atomic CPU operation. Also, PFX sequence instruction

pairs are skipped together by SKP-type conditional instructions.

The K register is not directly accessed by software, but is used indirectly.

A MOVI instruction, for example, transfers all 11 bits of K into bits 15..5 of

the destination register. This K-reading operation will only yield a non-

zero result when the previous instruction is PFX.

The Program Counter

The program counter (PC) register contains the byte-address of the

currently executing instruction. Since all instructions must be half-word-

aligned, the least-significant bit of the PC value is always 0.

The PC increments by two (PC ← PC + 2) after every instruction unlessthe

PC is explicitly set. The following instructions modify PC directly: BR,

BSR, CALL, JMP, LRET, RET and TRET. The PC is 33-bits wide in a 32-bit

Nios CPU and 17-bits wide in a 16-bit Nios CPU.

Control Registers

There are five defined control registers that are addressed independently

from the general-purpose registers. The RDCTL and WRCTL instructions

are the only instructions that can read or write to these control registers

(meaning %ctl0 is unrelated to %g0).

STATUS (%ctl0)

IPRI

CWP

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GettingOverview

Interrrupt Enable (IE)

IE is the interrupt enable bit. When IE=1, it enables external interrupts and

internal exceptions. IE=0 disables external interrupts and exceptions.

Software TRAP instructions will still execute normally even when IE=0.

Note that IE can be set directly without affecting the rest of the STATUS

registers. When the CPU is reset, IE is set to 0 (interrupts disabled).

Interrupt Priority (IPRI)

IPRI contains the current running interrupt priority. When an exception is

processed, the IPRI value is set to the exception number. See “Exceptions ”

on page 16 for more information. For external hardware interrupts, the

IPRI value is set directly from the 6-bit hardware interrupt number. For

TRAP instructions, the IPRI field is set directly from the IMM6 field of

the instruction. For internal exceptions, the IPRI field is set from the

pre-defined 6-bit exception number.

A hardware interrupt is not processed if its internal number is greater

than or equal to IPRI or IE=0. A TRAP instruction is processed

unconditionally. When the CPU is reset, IPRI is set to 63 (lowest-priority).

IPRI disables interrupts above a certain number. For example, if IPRI is 3,

then interrupts 0, 1 and 2 will be processed, but all others (interrupts 3-63)

are disabled.

Current Window Pointer (CWP)

CWP points to the base of the sliding register window in the general-

purpose register file. Incrementing CWP moves the register window up 16

registers. Decrementing CWP moves the register window down 16

registers. CWP is decremented by SAVE instructions and incremented by

RESTORE instructions.

Only specialized system software such as register window-management

facilities should directly write values to CWP through WRCTL. Software

will normally modify CWP by using SAVE and RESTORE instructions.

When the CPU is reset, CWP is set to the largest valid value, HI_LIMIT.

This means in a 256 register file size, there will be 16 register windows.

After reset, the WVALID register (%ct12) is set to 0x01C1, i.e., LO_LIMIT

= 1 and HI_ LIMIT =14. See “WVALID (%ctl2)” on page 6 for more

information.

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Overview

Condition Code Flags

Some instructions modify the condition code flags. These flags are the

four least significant bits of the status register as shown in Table 7.

Table 7. Condition Code Flags

Sign of result, or most significant bit

Arithmetic overflow—set if bit 31 of 32-bit result is different from

sign of result computed with unlimited precision.

Result is 0

Carry-out of addition, borrow-out of subtraction

ISTATUS (%ctl1)

ISTATUS is the saved copy of the STATUS register. When an exception is

processed, the value of the STATUS register is copied into the ISTATUS

See “Exceptions ” on page 16 for more information. A return-from-trap

(TRET) instruction automatically copies the ISTATUS register into the

STATUS register. Interrupts are disabled (IE=0) when an exception is

processed. Before re-enabling interrupts, an exception handler must

preserve the value of the ISTATUS register. When the CPU is reset,

ISTATUS is set to 0.

WVALID (%ctl2)

HI_LIMIT

LO_LIMIT

WVALID contains two values, HI_LIMIT and LOW_LIMIT. When a

SAVE instruction decrements CWP from LOW_LIMIT to LOW_LIMIT –1

a register window underflow (exception #1) is generated. When a

RESTORE instruction increments CWP from HI_LIMIT to HI_LIMIT +1, a

configurable and may be read-only or read/write. When the CPU is reset,

LO_LIMIT is set to 1 and HI_LIMIT is set to the highest valid window

pointer ((register file size / 16) – 2).

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GettingOverview

CLR_IE(%ctl8)

Any WRCTL operation to the CLR_IE register clears the IE bit in the

STATUS register (IE ← 0) and the WRCTL value is ignored. A RDCTL

operation from CLR_IE produces an undefined result.

SET_IE (%ctl9)

Any WRCTL operation to the SET_IE register sets the IE bit in the STATUS

from SET_IE produces an undefined result.

The Nios processor is little-endian. Data memory must occupy contiguous

native-words. If the physical memory device is narrower than the native-

word size, then the data bus should implement dynamic-bus sizing to

simulate full-width data to the Nios CPU. Peripherals present their

registers as native-word widths, padded by 0s in the most significant bits

if the registers happen to be smaller than native-words. Table 8 and

Table 9 show examples of the 32-bit Nios CPU native-word widths.

MemoryAccess

Overview

Table 8. Typical 32-bit Nios CPU Program/Data Memory at Address 0x0100

Address

Contents

16 15

24 23

0x0100

byte 3

byte 7

byte 2

byte 6

byte 1

byte 5

byte 9

byte 13

byte 0

byte 4

byte 8

byte 12

0x0104

0x0108

0x010c

byte 11

byte 15

byte 10

byte 14

Table 9. N-bit-wide Peripheral at Address 0x0100 (32-bit Nios CPU)

Address Contents

N-1

0x0100

(zero padding)

0x0104

0x0108

0x010c

(zero padding)

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Overview

Reading from Memory (or Peripherals)

The Nios CPU can only perform aligned memory accesses. A 32-bit read

operation can only read a full word starting at a byte address that is a

multiple of 4. A 16-bit read operation can only read a half-word starting at

a byte address that is a multiple of 2. Instructions which read from

memory always treat the low bit (16-bit Nios CPU) or low two bits (32-bit

Nios CPU) of the address as 0. Instructions are provided for extracting

particular bytes and half-words from words.

The simplest instruction that reads data from memory is the LD

instruction. A typical example of this instruction is LD %g3, [%o4]. The

first register operand, %g3, is the destination register, where data will be

loaded. The second register operand specifies a register containing an

address to read from. This address will be aligned to the nearest half-word

(16-bit Nios CPU) or word (32-bit Nios CPU) meaning the lowest bit (16-

bit Nios CPU) or two bits (32-bit Nios CPU) will be treated as if they are 0.

Quite often, however, software must read data smaller than the native

data size. The Nios CPU provides instructions for extracting individual

bytes (16-bit and 32-bit Nios CPU) and half-words (32-bit Nios CPU) from

native-words. The EXT8d instruction is used for extracting a byte, and the

EXT16d instruction is used for extracting a word. A typical example of the

EXT8d instruction is EXT8d %g3,%o4. The EXT8d instruction uses the

lowest bit (on 16-bit Nios CPU) or two bits (on 32-bit Nios CPU) of the

second register operand to extract a byte from the first register operand,

and replace the entire contents of the first register operand with that byte.

The assembly-language example in Code Example 1 shows how to read a

single byte from memory, even if the address of the byte is not native-

word-aligned.

Code Example 1: Reading a Single Byte from Memory

Contents of memory:

;

; 0x00001200

0x46

0x49

0x53

0x48

;Instructions executed on a 32-bit Nios CPU

; Let’s assume %o4 contains the address

x00001202

LD %g3,[%o4]

; %g3 gets the contents of address 0x1200,

; so %g3 contains 0x48534946

EXT8d %g3,%o4 ; %g3 gets replaced with byte 2 from %g3,

; so %g3 contains 0x00000053

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GettingOverview

Writing to Memory (or Peripherals)

The Nios CPU can perform aligned writes to memory in widths of byte,

half-word, or word (only the 32-bit Nios CPU can write a word). A word

(32-bit Nios CPU) can be written to any address that is a multiple of 4 in

one instruction. A half-word can be written to any address that is a

multiple of 2 in one instruction (16-bit Nios CPU) or two instructions

(32-bit Nios CPU). A byte can be written to any address in two

instructions.

On the 32-bit Nios CPU, the lowest byte of a register can be written only

to an address that is a multiple of 4; the middle-low byte of a register can

be written only as an address that is a multiple of 4, plus 1, and so on.

Similarly, on the 16-bit Nios CPU, the low byte of a register can be written

only to an even address and the high byte of a register can only be written

to an odd address.

The 32-bit Nios CPU can also write the low half-word of a register to an

address that is a multiple of four, and the high half-word of a register to

an address which is a multiple of 4, plus 2.

The ST instruction writes a full native-word to a native-word aligned

memory address from any register; the ST8d and ST16d (32-bit Nios CPU

only) instructions write a byte and half-word, respectively, with the

alignment constraints described above, from register %r0.

Often it is necessary for software to write a particular byte or half-word to

an arbitrary location in memory. The position within the source register

may not happen to correspond with the location in memory to be written.

The FILL8 and FILL16 (32-bit Nios CPU only) instructions will take the

lowest byte or half-word, respectively, of a register and replicate it across

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Overview

Code Example 2 shows how to write a single byte to memory, even if the

address of the byte is not native-word-aligned.

Code Example 2: Single Byte Written to Memory—Address is not Native-word-aligned

Instructions executed on a 32-bit Nios CPU

; Let’s assume %o4 contains the address 0x00001203

; and that %g3 contains the value 0x00000054

FILL8 %r0,%g3 ; (First operand can only be %r0)

; replicate low byte of %g3 across %r0

; so %r0 contains 0x54545454

ST8d [%o4],%r0 ; (Second operand can only be %r0)

; Stores the 3rd byte of %r0 to address 0x1203

Contents of memory after:

0x00001200

0x46

0x49

0x53

0x54

The topics in this section includes a description of the following

addressing modes:

Addressing

Modes

5/16-bit immediate

Full width register-indirect

Partial width register-indirect

Full width register-indirect with offset

Partial width register-indirect with offset

5/16-bit Immediate Value

Many arithmetic and logical instructions take a 5-bit immediate value as

an operand. The ADDI instruction, for example, has two operands: a

a constant from 0 to 31. To specify a constant value that requires from 6 to

16 bits (a number from 32 to 65535), the 11-bit K register can be set using

the PFX instruction, This value is concatenated with the 5-bit immediate

value. The PFX instruction must be used directly before the instruction it

modifies.

To support breaking 16-bit immediate constants into a PFX value and a

5-bit immediate value, the assembler provides the operators %hi() and

%lo(). %hi(x) extracts the 11 bits from bit 5 to bit 15 from constant x, and

%lo(x) extracts the 5 bits from bit 0 to bit 4 from constant x.

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GettingOverview

The following example shows an ADDI instruction being used both with

and without a PFX.

Code Example 3: The ADDI Instruction Used with/without a PFX

; Assume %g3 contains the value 0x0041

; Add 5 to %g3

ADDI %g3,5

; so %g3 now contains 0x0046

; Load K with upper 11 bits of 0x1234

PFX %hi(0x1234)

ADDI %g3,%lo(0x1234) ; Add low 5 bits of 0x1234 to %g3

; so the K register contained 0x0091

; and the immediate operand of the ADDI

; instruction contained 0x0011, which

; concatenated together make 0x1234

Besides arithmetic and logical instructions, several other instructions use

immediate-mode constants of various widths, and the constant is not

modified by the K register. See the description of each instruction in the

“32-Bit Instruction Set” for a precise explanation of its operation. Table 10

shows instructions using 5/16-bit immediate values.

Table 10. Instructions Using 5/16-bit Immediate Values

ADDI

CMPI

AND*

LSLI

OR*

ANDN*

LSRI

ASRI

MOVI

XOR*

MOVHI

SUBI

* AND, ANDN, OR, and XOR can only use PFX’d 16-bit immediate

values. These instructions act on two register operands if not preceded by

a PFX instruction.

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Overview

Full Width Register-Indirect

The LD and ST instructions can load and store, respectively, a full native-

word to or from a register using another register to specify the address.

The address is first aligned downward to a native-word aligned address,

as described in the “Memory Access Overview ” section. The K register is

treated as a signed offset, in native words, from the native-word aligned

value of the address register.

Table 11. Instructions Using Full Width Register-indirect Addressing

Instruction

Address Register

Data Register

Any

Partial Width Register-Indirect

There are no instructions that read a partial word. To read a partial word,

you must combine a full width register-indirect read instruction with an

extraction instruction, EXT8d, EXT8s, EXT16d (32-bit Nios CPU only) or

EXT16s (32-bit Nios CPU only).

Several instructions can write a partial word. Each of these instructions

has a static and a dynamic variant. The position within both the source

an addressing register. In the case of a static variant, the position within

both the source register and the native-word of memory is determined by

a 1- or 2-bit immediate operand to the instruction. As with full width

native words from the native-word aligned value of the address register.

The partial width register-indirect instructions all use %r0 as the source of

data to write. These instructions are convenient to use in conjunction with

the FILL8 or FILL16 (32-bit Nios CPU only) instructions.

Table 12. Instructions Using Partial Width Register-indirect Addressing

Instruction

Address Register

Data Register

Byte/Half-word Selection

ST8s

ST16s*

ST8d

Any

%r0

Immediate

Low bits of address register

ST16d*

* 32-bit Nios CPU only

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GettingOverview

Full Width Register-Indirect with Offset

The LDP, LDS, STP and STS instructions can load or store a full native-

word to or from a register using another register to specify an address,

and an immediate value to specify an offset, in native words, from that

address.

Unlike the LD and ST instructions, which can use any register to specify a

memory address, these instructions may each only use particular registers

for their address. The LDP and STP instructions may each only use the

STS instructions may only use the stack pointer, register %sp (equivalent

to %o6), as their address register. These instructions each take a signed

immediate index value that specifies an offset in native words from the

aligned address pointed in the address register.

Table 13. Instructions Using Full Width Register-indirect with Offset Addressing

Instruction

Address Register

Data Register

Offset Range without PFX

LDP

LDS

STP

STS

%L0, %L1, %L2, %L3

Any

-16..15 native-words

0..255 native-words

-16..15 native-words

0..255 native-words

%sp

%L0, %L1, %L2, %L3

%sp

Partial Width Register-Indirect with Offset

There are no instructions that read a partial word from memory. To read

a partial word, you must combine a full width indexed register-indirect

read instruction with an extraction instruction, EXT8d, EXT8s, EXT16d

(32-bit Nios CPU only) or EXT16s (32-bit Nios CPU only). The STS8s and

STS16s (Nios 32 only) use an immediate constant to specify a byte or half-

word offset, respectively, from the stack pointer to write the

correspondingly aligned partial width of the source register %r0.

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Overview

These instructions may each only use the stack pointer, register %sp

(equivalent to %o6), as their address register, and may only use register

%r0 (equivalent to %g0, but must be called %r0 in the assembly

instruction) as the data register. These instructions are convenient to use

with the FILL8 or FILL16 (32-bit Nios CPU only) instructions.

Table 14. Instructions Using Partial Width Register-indirect with Offset Addressing

Instruction

Address

Data Register

Byte/Half-word

Selection

Index Range

STS8s

%sp

%r0

Immediate

0..1023 bytes

STS16s*

0..511 half-words

*32-bit Nios CPU only

The topics in this section includes a description of the following:

Program-Flow

Control

Two relative-branch instructions (BR and BSR)

Two absolute-jump instructions (JMP and CALL)

Two trap instructions (TRET and TRAP)

Five conditional instructions (SKP, SKP0, SKP1, SKPRz and SKPRnz)

Relative-Branch Instructions

There are two relative-branch instructions: BR and BSR. The branch target

address is computed from the current program-counter (i.e. the address of

the BR instruction itself) and the IMM11 instruction field. Details of the

branch-offset computation are provided in the description of the BR and

BSR instructions. See “BR” on page 42 and “BSR” on page 43. BSR is

identical to BR except that the return-address is saved in %o7. Details of

the return-address computation are provided in the description of the BSR

instruction. Both BR and BSR are unconditional. Conditional branches are

implemented by preceding BR or BSR with a SKP-type instruction.

Both BR and BSR instructions have branch delay slot behavior: The

instruction immediately following a BR or BSR is executed after BR or

BSR, but before the instruction at the branch-target. See “Branch Delay

Slots ” on page 23 for more information. The branch range of the BR and

BSR instructions is forward by 2048 bytes, or backwards by 2046 bytes

relative to the address of the BR or BSR instruction.

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GettingOverview

Absolute-Jump Instructions

There are two absolute (computed) jump instructions: JMP and CALL.

The jump-target address is given by the contents of a general-purpose

the PC. CALL is identical to JMP except that the return-address is saved

in %o7. Details of the return-address computation are provided in the

description of the CALL instruction. Both JMP and CALL are

unconditional. Conditional jumps are implemented by preceding JMP or

CALL with a SKP-type instruction.

Both JMP and CALL instructions have branch delay slot behavior: The

instruction immediately following a JMP or CALL is executed after JMP

or CALL, but before the instruction at the jump-target. The LRET pseudo-

instruction, which is an assembler alias for JMP %o7, is conventionally

used to return from subroutines.

Trap Instructions

The Nios processor implements two instructions for software exception

processing: TRAP and TRET. See “TRAP” on page 102 and “TRET” on

page 103 for detailed descriptions of both these instructions. Unlike JMP

and CALL, neither TRAP nor TRET has a branch delay-slot: The

instruction immediately following TRAP is not executed until the

exception-handler returns. The instruction immediately following TRET

is not executed at all as part of TRET's operation.

Conditional Instructions

There are five conditional instructions (SKPs, SKP0, SKP1, SKPRz, and

SKPRnz). Each of these instructions has a converse assembler-alias

pseudo-instruction (IFs, IF0, IF1, IFRz, and IFRnz, respectively). Each of

these instructions tests a CPU-internal condition and then executes the

next instruction or not, depending on the outcome. The operation of all

five SKP-type instructions (and their pseudo-instruction aliases), are

identical except for the particular test performed. In each case, the

subsequent (conditionalized) instruction is fetched from memory

regardless of the test outcome. Depending on the outcome of the test, the

subsequent instruction is either executed or cancelled.

While SKP and IF type conditional instructions are often used to

conditionalize jump (JMP, CALL) and branch (BR, BSR) instructions, they

can be used to conditionalize any instruction. Conditionalized PFX

instructions (PFX immediately after a SKPx or IFx instruction) present a

special case; the next two instructions are either both cancelled or both

executed. PFX instruction pairs are conditionalized as an atomic unit.

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The topics in this section include a description of the following:

Exceptions

Exception vector table

How external hardware interrupts, internal exceptions, register

window underflow, register window overflow and TRAP

instructions are handled

Direct software exceptions (TRAP) and exception processing

sequence

Exception Handling Overview

The Nios processor allows up to 64 vectored exceptions. Exceptions can be

enabled or disabled globally by the IE control-bit in the STATUS register,

or selectively enabled on a priority basis by the IPRI field in the STATUS

hardware interrupts, internal exceptions or explicit software TRAP

instructions.

The Nios exception-processing model allows precise handling of all

internally generated exceptions. That is, the exception-transfer

mechanism leaves the exception-handling subroutine with enough

information to restore the status of the interrupted program as if nothing

had happened. Internal exceptions are generated if a SAVE or RESTORE

instruction causes a register-window underflow or overflow,

respectively.

Exception-handling subroutines always execute in a newly opened

handler does not need to manually preserve the interruptee’s register

contents.

Exception Vector Table

The exception vector table is a set of 64 exception-handler addresses. On a

32-bit Nios CPU each entry is 4 bytes and on a 16-bit Nios CPU each entry

is 2 bytes. The base-address of the exception vector table is configurable.

When the Nios CPU processes exception number n, it fetches the nth entry

from the exception vector table, doubles the fetched value and then loads

the results into the PC.

The exception vector table can physically reside in RAM or ROM,

depending on the hardware memory map of the target system. A ROM

exception vector table will not require run-time initialization.

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External Hardware Interrupt Sources

An external source can request a hardware interrupt by driving a 6-bit

interrupt number on the Nios CPU irq_number inputs while

simultaneously asserting true (1) the Nios CPU irq input pin. The Nios

CPU will process the indicated exception if the IE bit is true (1) and the

requested interrupt number is smaller than (higher priority than) the

current value in the IPRI field of the STATUS register. Control is

transferred to the exception handler whose number is given by the

irq_number inputs.

External logic for producing the irq_number input and for driving the irq

input pin is automatically generated by the Nios SOPC builder software

and included in the peripheral bus module PBM outside the CPU. An

interrupt-capable peripheral need only generate one or more interrupt-

request signals that are combined within the PBM to produce the Nios

irq_number and irq inputs.

The Nios irq input is level sensitive. The irq and irq_number inputs are

sampled at the rising edge of each clock. External sources that generate

interrupts should assert their irq output signals until the interrupt is

acknowledged by software (e.g. by writing a register inside the

interrupting peripheral to 0). Interrupts that are asserted and then de-

asserted before the Nios CPU core can begin processing the exception are

ignored.

Internal Exception Sources

There are two sources of internal exceptions: register window-overflow

and register window-underflow. The Nios processor architecture allows

precise exception handling for all internally generated exceptions. In each

case, it is possible for the exception handler to fix the exceptional

condition and make it behave as if the exception-generating instruction

had succeeded.

A register window underflow exception occurs whenever the lowest valid

issued. The SAVE instruction moves CWP below LO_LIMIT and %sp is

set per the normal operation of SAVE. A register window underflow

exception is generated, which transfers control to an exception-handling

subroutine before the instruction following SAVE is executed.

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When a SAVE instruction causes a register window underflow exception,

CWP is decremented only once before control is passed to the exception-

handling subroutine. The underflow exception handler will see CWP =

LO_LIMIT – 1. The register window underflow exception is exception

number 1. The CPU will not process a register window underflow

exception if interrupts are disabled (IE=0) or the current value in IPRI is

less than or equal to 1.

The action taken by the underflow exception-handler subroutine depends

upon the requirements of the system. For systems running larger or more

complex code, the underflow (and overflow) handlers can implement a

virtual register file that extends beyond the limits of the physical register

file. When an underflow occurs, the underflow handler might (for

example) save the current contents of the entire register file to memory

and re-start CWP back at HI_LIMIT, allowing room for code to continue

opening register windows. Many embedded systems, on the other hand,

might wish to tightly control stack usage and subroutine call-depth. Such

systems might implement an underflow handler that prints an error

message and exits the program.

The programmer determines the nature of and actions taken by the

development kit (SDK) includes, and automatically installs by default, a

the stack as temporary storage.

A register window underflow exception can only be generated by a SAVE

instruction. Directly writing CWP (via a WRCTL instruction) to a value

less than LO_LIMIT will not cause a register window underflow

exception. Executing a SAVE instruction when CWP is already below

LO_LIMIT will not generate a register window underflow exception.

A register window overflow exception occurs whenever the highest valid

is issued. Control is transferred to an exception-handling subroutine

before the instruction following RESTORE is executed.

When a register window overflow exception is taken, the exception

handler will see CWP at HI_LIMIT. You can think of CWP being

incremented by the RESTORE instruction, but then immediately

decremented as a consequence of normal exception processing. The

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The action taken by the overflow exception handler subroutine depends

upon the requirements of the system. For systems running larger or more

complex code, the overflow and underflow handlers can implement a

virtual register file that extends beyond the limits of the physical register

file. When an overflow occurs, such an overflow handler might (for

example) reload the entire contents of the physical register file from the

stack and restart CWP back at LO_LIMIT. Many embedded systems, on

the other hand, might wish to tightly control stack usage and subroutine

call depth. Such systems might implement an overflow handler that prints

an error message and exits the program.

The programmer determines the nature of and actions taken by the

automatically installs by default a register window overflow handler

which virtualizes the register file using the stack.

A register window overflow exception can only be generated by a

RESTORE instruction. Directly writing CWP (via a WRCTL instruction) to

a value greater than HI_LIMIT will not cause a register window overflow

exception. Executing a RESTORE instruction when CWP is already above

HI_LIMIT will not generate a register window overflow exception.

Direct Software Exceptions (TRAP Instructions)

Software can directly request that control be transferred to an exception

handler by issuing a TRAP instruction. The IMM6 field of the instruction

gives the exception number. TRAP instructions are always processed,

regardless of the setting of the IE or IPRI bits. TRAP instructions do not

have a delay slot. The instruction immediately following a TRAP is not

executed before control is transferred to the indicated exception-handler.

A reference to the instruction following TRAP will be saved in %o7, so

that a TRET instruction will transfer control back to the instruction

following TRAP at the conclusion of exception processing.

Exception Processing Sequence

When an exception is processed from any of the sources mentioned above,

the following sequence occurs:

1. The contents of the STATUS register are copied into the ISTATUS

2. CWP is decremented, opening a new window for use by the

exception-handler routine (This is not the case for register window

underflow exceptions, where CWP was already decremented by the

SAVE instruction that caused the exception).

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3. IE is set to 0, disabling interrupts.

4. IPRI is set with the 6-bit number of the exception.

5. The address of the next non-executed instruction in the interrupted

program is transferred into %o7.

6. The start-address of the exception handler is fetched from the

exception vector table and written into the PC.

7. After the exception handler finishes a TRET instruction is issued to

return control to the interrupted program.

All exception processing starts in a newly opened register window. This

process decreases the complexity and latency of exception handlers

because they are not responsible for maintaining the interruptee’s register

contents. An exception handler can freely use registers %o0..%L7 in the

newly opened window. An exception handler should not execute a SAVE

instruction upon entry. The use of SAVE and RESTORE from within

exception handlers is discussed later.

Because the transfer to exception handling always opens a new register

window, programs must always leave one register window available for

exceptions. Setting LO-LIMIT to 1 guarantees that one window is

available for exceptions (The reset value of LO_LIMIT is 1). Whenever a

program executes a SAVE instruction that would then use up the last

CWP = 0).

Correctly written software will never process an exception when CWP

is 0. CWP will only be 0 when an exception is being processed, and

exception handlers must take certain well-defined precautions before

re-enabling interrupts. See “Simple and Complex Exception Handlers ” on

page 21 for more information.

Status Preservation: ISTATUS Register

When an exception occurs, the interruptee’s STATUS register is copied

into the ISTATUS register. The STATUS register is then modified (IE set

to 0, IPRI set, CWP decremented). The original contents of the STATUS

processing returns control to the interruptee, the original program’s

STATUS register contents are restored from ISTATUS by the TRET

instruction.

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Interrupts are automatically disabled upon entry to an exception handler,

so there is no danger of ISTATUS being overwritten by a subsequent

interrupt or exception. The case of nested exception handlers (exception

handlers that use or re-enable exceptions) is discussed in detail below.

Nested exception handlers must explicitly preserve, maintain, and restore

the contents of the ISTATUS register before and after enabling subsequent

interrupts.

Return-Address

When an exception occurs, execution of the interrupted program is

temporarily suspended. The instruction in the interrupted program that

was preempted (i.e., the instruction that would have executed, but did not

yet execute) is taken as the return-location for exception processing.

The return-location is saved in %o7 (in the exception handler’s newly

opened register window) before control is transferred to the exception

handler. The value stored in %o7 is the byte-address of the return-

instruction right-shifted by one place. This value is suitable directly for

use as the target of a TRET instruction without modification. Exception

handlers will usually execute a TRET %o7 instruction to return control to

the interrupted program.

Simple and Complex Exception Handlers

The Nios processor architecture permits efficient, simple exception

handlers. The hardware itself accomplishes much of the status- and

exception handlers can substantially ignore all automatic aspects of

exception handling. Complex exception handlers (for example, nested

exception handlers) must follow additional precautions.

Simple Exception Handlers

An exception handler is considered simple if it obeys the following rules:

It does not re-enable interrupts.

It does not use SAVE or RESTORE (either directly or by calling

subroutines that use SAVE or RESTORE).

It does not use any TRAP instructions (or call any subroutines that

use TRAP instructions).

It does not alter the contents of registers %g0..%g7, or %i0..%i7.

Any exception handler that obeys these rules need not take special

precautions with ISTATUS or the return address in %o7. A simple

exception handler need not be concerned with CWP or register-window

management.

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Complex Exception Handlers

An exception handler is considered complex if it violates any of the

requirements of a simple exception handler, listed above. Complex

exception handlers allow nested exception handling and the execution of

more complex code (e.g. subroutines that SAVE and RESTORE). A

complex exception handler has the following additional responsibilities:

It must preserve the contents of ISTATUS before re-enabling

interrupts. For example, ISTATUS could be saved on the stack.

It must check CWP before re-enabling interrupts to be sure CWP is at

or above LO_LIMIT. If CWP is below LO_LIMIT, it must take an

action to open up more available register windows (e.g., save the

It must re-enable interrupts subject to the above two conditions

before executing any SAVE or RESTORE instructions or calling any

subroutines that execute any SAVE or RESTORE instructions.

Prior to returning control to the interruptee, it must restore the

contents of the ISTATUS register, including any adjustments to CWP

if the register-window has been deliberately shifted.

Prior to returning control to the interruptee, it must restore the

contents of the interruptee’s register window.

This topics in this section include a description of the following:

Pipeline

Implementation

Nios CPU pipeline

Exposed pipeline branch delay and direct CWP manipulation

Figure 4. Nios CPU Block Diagram

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Pipeline Operation

The Nios CPU is pipelined RISC architecture. The pipeline

implementation is hidden from software except for branch delay slots and

when CWP is modified by a WRCTL direct write. The pipeline stages

include:

Instruction Fetch—the Nios CPU issues an address, and the memory

subsystem then returns the instruction stored at the issued address.

Instruction Decode / Operand Fetch—the fetched instruction is

decoded. If there are register operands, they are read from the

destination address for BR and BSR instructions.

Execute—the operands and control bits are presented to the ALU.

The ALU then computes a result.

Write-back—the ALU result is written back into the destination

Branch Delay Slots

A branch delay slot is defined as the instruction immediately after a BR,

BSR, CALL, or JMP instruction. A branch delay slot is executed after the

branch instruction but before the branch-target instruction. Table 15

illustrates a branch delay-slot for a BR instruction.

Table 15. BR Branch Delay Slot Example

…

(a)

(b)

(c)

(d)

ADD %g2, %g3

BR Target

ADD %g4, %g5

ADD %g6, %g7

Branch Delay Slot

…

Target:

ADD %g8, %g9

(e)

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After branch instruction (b) is taken, instruction (c) is executed before

control is transferred to the branch target (e). The execution sequence of

the above code fragment would be (a), (b), (c), and (e). Instruction (c) is

instruction (b)’s branch delay slot. Instruction (d) is not executed. Most

instructions can be used as a branch delay slot except for those listed

below:

BSR

CALL

IF1

IF0

IFRnz

IFRz

IFS

JMP

LRET

PFX

RET

SKP1

SKP0

SKPRnz

SKPRz

SKPS

TRET

TRAP

Direct CWP Manipulation

Every WRCTL instruction that modifies the STATUS register (%ctl0) must

be followed by a NOP instruction.

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Table 16. Notation Details

Notation

Meaning

Notation

Meaning

X ← Y X is written with Y

X >> n The value X after being right-shifted n bit

positions

∅ ← e Expression e is evaluated, and the result

X << n The value X after being left-shifted n bit

positions

is discarded

RA One of the 32 visible registers, selected

by the 5-bit a-field of the instruction word

^bnX The n^thbyte (8-bit field) within the

full-width value X. ^b0X = X[7..0],

^b1X = X[15..8], ^b2X = X[23..16], and

^b3X = X[31..24]

RB One of the 32 visible registers, selected

by the 5-bit b-field of the instruction word

^hnX The n^thhalf-word (16-bit field) within the

full-width value X. ^h0X = X[15..0],

^h1X = X[31..16]

RP One of the 4 pointer-enabled (P-type)

registers, selected by the 2-bit p-field of

the instruction word

X & Y Bitwise logical AND

IMMn An n-bit immediate value, embedded in

the instruction word

X | Y Bitwise logical OR

The 11-bit value held in the K register. (K

can only be set by a PFX instruction)

X ⊕ Y Bitwise logical exclusive OR

~X Bitwise logical NOT (one’s complement)

0xnn.mm Hexadecimal notation (decimal points not

significant, added for clarity)

X : Y Bitwise-concatenation operator.

e.g.: (0x12 : 0x34) = 0x1234

|X| The absolute value of X

(i.e. –X if (X < 0), X otherwise).

{e1, e2} Conditional expression. Evaluates to e2

if previous instruction was PFX,

e1 otherwise

Mem32[X] The aligned 32-bit word value stored in

external memory, starting at byte address

σ(X) X after being sign-extended into a full

Mem16[X] The aligned 16-bit half-word value stored

in external memory, starting at byte-

address X

X[n] The n^thbit of X (n = 0 means LSB)

X[n..m] Consecutive bits n through m of X

align16(X) X & 0xFF.FE, which is the integer value X

forced into half-word alignment via

truncation

align32(X) X & 0xFF.FF.FF.FC, which is the integer

value X forced into full-word alignment via

truncation

The C (carry) flag in the STATUS register

CTLk One of the 2047 control registers selected

by K

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Instruction Format (Sheet 1 of 2)

Ri5

Ri4

op6

IMM5

IMM4

RPi5 15

op4

Ri6

Ri8

op5

IMM6

op3

IMM8

op6

IMM9

i10

i11

op6

IMM10

op5

IMM11

Ri1u 15

Ri2u 15

IMM1u

op6

op3u

op6

op3u

IMM2u

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Instruction Format (Sheet 2 of 2)

i8v

i6v

i4w

op6

op2v

IMM8v

IMM6v

op5w

IMM4w

op5w

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Table 17. 32-bit Major Opcode Table (Sheet 1 of 3)

Opcode

Mnemonic Format

Summary

000000

ADD

ADDI

SUB

SUBI

CMP

CMPI

LSL

Ri5

RA ← RA + RB

Flags affected: N, V, C, Z

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

RA ← RA + (0×00.00 : K : IMM5)

Flags affected: N, V, C, Z

RA ← RA – RB

Flags affected: N, V, C, Z

RA ← RA – (0×00.00 : K : IMM5)

Flags affected: N, V, C, Z

∅ ← RA – RB

Flags affected: N, V, C, Z

∅ ← RA – (0×00.00 : K : IMM5)

Flags affected: N, V, C, Z

RA ← (RA << RB [4..0]),

Zero-fill from right

LSLI

LSR

RA ← (RA << IMM5),

Zero-fill from right

RA ← (RA >> RB [4..0]),

Zero-fill from left

LSRI

ASR

ASRI

RA ← (R >> IMM5),

Zero-fill form left

RA ← (RA >> RB [4..0]),

Fill from left with RA[31]

RA ← (RA >> IMM5),

Fill from left with RA[31]

001100

001101

001110

MOV

MOVI

AND

Ri5

RA ← RB

RA ← (0×00.00 : K : IMM5)

Ri5

RA ← RA & {RB, (0×00.00 : K : IMM5)}

Flags affected: N, Z

001111

010000

010001

ANDN

RR,

Ri5

RA ← RA & ~({RB, (0×00.00 : K : IMM5)})

Flags affected: N, Z

RR,

Ri5

RA ← RA | {RB, (0×00.00 : K : IMM5)}

Flags affected: N, Z

XOR

RR,

Ri5

RA ← RA ⊕ {RB, (0×00.00 : K : IMM5)}

Flags affected: N, Z

010010

010011

010100

010101

010110

BGEN

EXT8d

SKP0

SKP1

Ri5

RA ← 2^IMM5

RA ← (0×00.00.00 : ^bnRA) where n = RB[1..0]

Skip next instruction if: (RA [IMM5] == 0)

Skip next instruction if: (RA [IMM5] == 1)

RA ← Mem32 [align32( RB + (σ(K) × 4))]

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Table 17. 32-bit Major Opcode Table (Sheet 2 of 3)

Opcode

Mnemonic Format

Summary

010111

011000

i10

Mem32 [align32( RB + (σ(K) × 4))] ← RA

^bnMem32 [align32(%sp + IMM10)] ← ^bn%r0

where n = IMM10[1..0]

STS8s

011001

STS16s

^hnMem32 [align32( %sp + IMM9 × 2)] ← ^hn%r0

where n = IMM9[0]

011010

011011

EXT16d

MOVHI

USR0

Ri5

RA ← (0×00.00 : ^hnRA) where n = RB[1]

^h1RA ← (K : IMM5), ^h0RA unaffected

Reserved for future use

011100

011101000

011101001

011101010

011101011

011101100

EXT8s

EXT16s

Ri1u

RA ← (0×00.00.00 : ^bnRA) where n = IMM2u

RA ← (0×00.00 : ^hnRA) where n = IMM1u

ST8s

ST16s

SAVE

TRAP

Ri1u

i8v

^bnMem32 [align32(RA + (σ(K) × 4))] ← ^bn%r0

where n = IMM2u

^hnMem32 [align32(RA + (σ(K) × 4))] ← ^hn%r0

011101101

01111000

where n = IMM1u

CWP ← CWP – 1; %sp ← %fp – (IMM8v × 4)

If (old-CWP == LO_LIMIT) {TRAP #1}

0111100100

i6v

ISTATUS ← STATUS; IE ← 0; CWP ← CWP – 1;

IPRI ← IMM6v; %r15 ← ((PC + 2) >> 1) ;

PC ← Mem32 [VECBASE + (IMM6v × 4)] × 2

01111100000

01111100001

01111100010

01111100011

01111100100

01111100101

NOT

NEG

RA ← ~RA

RA ← 0 – RA

RA ← |RA|

RA ← σ(^b0RA)

RA ← σ(^h0RA)

ABS

SEXT8

SEXT16

RLC

C ← msb (RA); RA ← (RA << 1) : C

Flag affected: C

01111100110

RRC

C ← RA[0]; RA ← C : (RA >> 1)

Flag affected: C

01111100111

01111101000

01111101001

01111101010

01111101011

01111101100

01111101101

01111101110

SWAP

USR1

RA ← ^h0RA : ^h1RA

Reserved for future use

USR2

USR3

USR4

RESTORE

TRET

CWP ← CWP + 1; if (old-CWP == HI_LIMIT) {TRAP #2}

PC ← (RA × 2); STATUS ← ISTATUS

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Table 17. 32-bit Major Opcode Table (Sheet 3 of 3)

Opcode

Mnemonic Format

Summary

01111101111

01111110000

ST8d

^bnMem32 [align32(RA +(σ(K) × 4))] ← ^bn%r0

where n = RA[1..0]

^hnMem32 [align32(RA + (σ(K) × 4))] ← ^hn%r0

01111110001

ST16d

where n = RA[1]

01111110010

01111110011

01111110100

FILL8

FILL16

MSTEP

%r0 ← (^b0RA : ^b0RA : ^b0RA : b⁰RA)

%r0 ← (^h0RA : ^h0RA)

if (%r0[31] == 1) then %r0 ← (%r0 << 1) + RA else %r0

← (%r0 << 1)

01111110101

01111110110

01111110111

01111111000

01111111001

01111111010

01111111011

01111111100

01111111101

01111111110

01111111111

100000

MUL

i4w

%r0 ← (%r0 & 0x0000.ffff) × (RA & 0x0000.ffff)

Skip next instruction if:(RA ==0)

Skip next instruction if condition encoded by IMM4w is true

CTLk ← RA

SKPRz

SKPS

WRCTL

RDCTL

SKPRnz

RA ← CTLk

Skip next instruction if: (RA ! = 0)

JMP

CALL

i11

PC ← (RA × 2)

R15 ←((PC + 4) >> 1); PC ← (RA × 2)

PC ← PC + ((σ(IMM11) + 1) × 2)

100001

100010

BSR

i11

PC ← PC + ((σ(IMM11) + 1) × 2);

%r15 ← ((PC + 4) >> 1)

10011

1010

1011

110

PFX

STP

LDP

STS

LDS

i11

RPi5

Ri8

K ← IMM11 (K set to zero after next instruction)

Mem32[align32(RP + (σ(K : IMM5) × 4))] ← RA

RA ← Mem32 [align32(RP + (σ(K : IMM5) × 4))]

Mem32[align32(%sp + (IMM8 × 4) )] ← RA

RA ← Mem32 [align32(%sp + (IMM8 × 4))]

111

Ri8

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The following pseudo-instructions are generated by nios-elf-gcc (GNU

compiler) and understood by nios-elf-as (GNU assembler).

Table 18. GNU Compiler/Assembler Pseudo-instructions

Psuedo-Instruction

Equivalent Instruction

Notes

LRET

RET

JMP %o7

JMP %i7

LRET has no operands

RET has no operands

NOP has no operands

NOP

MOV %g0,%g0

SKP1 %rA,IMM5

SKP0 %rA,IMM5

SKPRnz %rA

SKPRz %rA

SKPS cc_nc

SKPS cc_c

IF0 %rA,IMM5

IF1 %rA,IMM5

IFRz %rA

IFRnz %rA

IFS cc_c

IFS cc_nc

IFS cc_z

IFS cc_nz

IFS cc_mi

IFS cc_pl

IFS ccge

IFS cc_lt

IFS cc_le

IFS cc_gt

IFS cc_v

IFS cc_nv

IFS cc_ls

IFS cc_hi

SKPS cc_nz

SKPS cc_z

SKPS cc_pl

SKPS cc_mi

SKPS cc_lt

SKPS cc_ge

SKPS cc_gt

SKPS cc_le

SKPS cc_nv

SKPS cc_v

SKPS cc_hi

SKPS cc_ls

The following operators are understood by nios-elf-as. These operators

may be used with constants and symbolic addresses, and can be correctly

resolved either by the assembler or the linker.

Operator

Description

Operation

%lo(x)

%hi(x)

%xlo(x)

%xhi(x)

x@h

Extract low 5 bits of x.

Extract bits 5..15 of x.

Extract bits 16..20 of x.

Extract bits 21..31 of x.

Half-word address of x.

x & 0×0000001f

(x >> 5) & 0×000007ff

(x >> 1 (x >> 16) & 0×0000001f

(x >> 21) & 0×000007ff

x >> 1

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32-Bit Instruction Set

This section provides a detailed description of the 32-bit Nios CPU

instructions. The descriptions are arranged in alphabetical order

according to instruction mnemonic. Each instruction page includes the

following information:

Instruction mnemonic and description

Description of operation

Assembler syntax

Syntax example

Operation description

Prefix actions

Condition codes

Instruction format

Instruction fields

The ∆ symbol found in the condition code flags table indicates

flags are changed by the instruction.

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32-Bit Instruction Set

ABS

Absolute Value

Operation:

RA ← |RA|

Assembler Syntax:

Example:

ABS %rA

ABS %r6

Description:

Calculate the absolute value of RA; store the result in RA.

Flags: Unaffected

Condition Codes:

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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3232323232-Bit Instruction Set

ADD

Add Without Carry

Operation:

RA ← RA + RB

Assembler Syntax:

Example:

ADD %rA,%rB

ADD %L3,%g0 ; ADD %g0 to %L3

Description:

Adds the contents of register A to register B and stores the result in register A.

Flags:

Condition Codes:

∆

N: Result bit 31

V: Signed-arithmetic overflow

Z: Set if result is zero; cleared otherwise

C: Carry-out of addition

Instruction Format:

Instruction Fields:

A = Register index of RA operand

B = Register index of RB operand

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32-Bit Instruction Set

ADDI

Add Immediate

Operation:

RA ← RA + (0x00.00 : K : IMM5)

Assembler Syntax:

Example:

ADDI %rA,IMM5

Not preceded by PFX:

ADDI %L5,6 ; add 6 to %L5

Preceded by PFX:

PFX %hi(1000)

ADDI %g3,%lo(1000) ; ADD 1000 to %g3

Description:

Not preceded by PFX:

Adds 5-bit immediate value to register A, stores result in register A. IMM5 is in the

range [0..31].

Preceded by PFX:

The immediate operand is extended from 5 to 16 bits by concatenating the

contents of the K-register (11 bits) with IMM5 (5 bits). The 16-bit immediate value

(K : IMM5) is zero-extended to 32 bits and added to register A.

Condition Codes:

Flags:

∆

N: Result bit 31

V: Signed-arithmetic overflow

Z: Set if result is zero; cleared otherwise

C: Carry-out of addition

Instruction Format:

Instruction Fields:

Ri5

A = Register index of RA operand

IMM5 = 5-bit immediate value

IMM5

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3232323232-Bit Instruction Set

AND

Bitwise Logical AND

Operation:

Not preceded by PFX:

RA ← RA & RB

Preceded by PFX:

RA ← RA & (0x00.00 : K : IMM5)

Assembler Syntax:

Not preceded by PFX:

AND %rA,%rB

Preceded by PFX:

PFX %hi(const)

AND %rA,%lo(const)

Example:

Not preceded by PFX:

AND %g0,%g1 ; %g0 gets %g1 & %g0

Preceded by PFX:

PFX %hi(16383)

AND %g0,%lo(16383) ; AND %g0 with 16383

Description:

Not preceded by PFX:

Logically-AND the individual bits in RA with the corresponding bits in RB; store

the result in RA.

Preceded by PFX:

When prefixed, the RB operand is replaced by an immediate constant formed by

concatenating the contents of the K-register (11 bits) with IMM5 (5 bits). This

16-bit value (zero-extended to 32 bits) is bitwise-ANDed with RA, and the result

is written back into RA.

Condition Codes:

Flags:

∆

–

∆

–

N: Result bit 31

Z: Set if result is zero, cleared otherwise

Instruction Format:

Instruction Fields:

RR, Ri5

A = Register index of RA operand

B = Register index of RB operand

IMM5 = 5-bit immediate value

Not preceded by PFX (RR)

Preceded by PFX (Ri5)

IMM5

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32-Bit Instruction Set

ANDN

Bitwise Logical AND NOT

Operation:

Not preceded by PFX:

RA ← RA & ~RB

Preceded by PFX:

RA ← RA & ~(0x00.00 : K : IMM5)

Assembler Syntax:

Not preceded by PFX:

ANDN %rA,%rB

Preceded by PFX:

PFX %hi(const)

ANDN %rA,%lo(const)

Example:

Not preceded by PFX:

ANDN %g0,%g1 ; %g0 gets %g0 & ~%g1

Preceded by PFX:

PFX %hi(16384)

ANDN %g0,%lo(16384) ; clear bit 14 of %g0

Description:

Not preceded by PFX:

Logically-AND the individual bits in RA with the corresponding bits in the one’s-

complement of RB; store the result in RA.

Preceded by PFX:

When prefixed, the RB operand is replaced by an immediate constant formed by

concatenating the contents of the K-register (11 bits) with IMM5 (5 bits). This

16-bit value is zero-extended to 32 bits, then bitwise-inverted and bitwise-ANDed

with RA. The result is written back into RA.

Condition Codes:

Flags:

∆

–

∆

–

N: Result bit 31

Z: Set if result is zero, cleared otherwise

Instruction Format:

Instruction Fields:

RR, Ri5

A = Register index of operand RA

B = Register index of operand RB

IMM5 = 5-bit immediate value

Not preceded by PFX (RR)

Preceded by PFX (Ri5)

IMM5

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3232323232-Bit Instruction Set

ASR

Arithmetic Shift Right

Operation:

RA ← (RA >> RB[4..0]), fill from left with RA[31]

Assembler Syntax:

Example:

ASR %rA,%rB

ASR %L3,%g0 ; shift %L3 right by %g0 bits

Description:

Arithmetically shift right the value in RA by the value of RB; store the result in RA.

Bits 31..5 of RB are ignored. If the value in RB[4..0] is 31, RA will be zero or

negative one depending on the original sign of RA.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of RA operand

B = Register index of RB operand

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32-Bit Instruction Set

ASRI

Arithmetic Shift Right Immediate

Operation:

RA ← (RA >> IMM5), fill from left with RA[31]

Assembler Syntax:

Example:

ASRI %rA,IMM5

ASRI %i5,6 ; shift %i5 right 6 bits

Description:

Arithmetically shift right the contents of RA by IMM5 bits. If IMM5 is 31, RA will be

zero or negative one depending on the original sign of RA.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

Ri5

A = Register index of RA operand

IMM5 = 5-bit immediate value

IMM5

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3232323232-Bit Instruction Set

BGEN

Bit Generate

Operation:

RA ← 2^IMM5

Assembler Syntax:

Example:

BGEN %rA,IMM5

BGEN %g7,6 ; set %g7 to 64

Description:

Sets RA to an integer power-of-two with the exponent given by IMM5. This is

equivalent to setting a single bit in RA, and clearing the rest.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

Ri5

A = Register index of RA operand

IMM5 = 5-bit immediate value

IMM5

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32-Bit Instruction Set

Branch

Operation:

PC ← PC + ((σ(IMM11) + 1) << 1)

Assembler Syntax:

Example:

BR addr

BR MainLoop

NOP ; (delay slot)

Description:

The offset given by IMM11 is interpreted as a signed number of half-words

(instructions) relative to the instruction immediately following BR. Program control

is transferred to instruction at this offset.

Condition Codes:

Flags: Unaffected

−

Delay Slot Behavior:

The instruction immediately following BR (BR’s delay slot) is executed after BR,

but before the destination instruction. There are restrictions on which instructions

may be used as a delay slot. (Refer to “Branch Delay Slots” on page 23)

Instruction Format:

Instruction Fields:

i11

IMM11 = 11-bit immediate value

IMM11

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3232323232-Bit Instruction Set

BSR

Branch To Subroutine

Operation:

%o7 ← ((PC + 4) >> 1)

PC ← PC + ((σ(IMM11) + 1) << 1)

Assembler Syntax:

Example:

BSR addr

BSR SendCharacter

NOP ; (delay slot)

Description:

The offset given by IMM11 is interpreted as a signed number of half-words

(instructions) relative to the instruction immediately following BR. Program control

is transferred to instruction at this offset. The return-address is the address of the

BSR instruction plus four, which is the address of the second subsequent

instruction. The return-address is shifted right one bit and stored in %o7. The

right-shifted value stored in %o7 is a destination suitable for direct use by JMP

without modification.

Condition Codes:

Flags: Unaffected

−

Delay Slot Behavior:

The instruction immediately following BSR (BSR’s delay slot) is executed after

BSR, but before the destination instruction. There are restrictions on which

instructions may be used as a delay slot. (Refer to “Branch Delay Slots” on

page 23)

Instruction Format:

Instruction Fields:

i11

IMM11 = 11-bit immediate value

IMM11

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32-Bit Instruction Set

CALL

Call Subroutine

Operation:

%o7 ← ((PC + 4) >> 1)

PC ← (RA << 1)

Assembler Syntax:

Example:

CALL %rA

CALL %g0

NOP ; (delay slot)

Description:

The value of RA is shifted left by one and transferred into PC. RA contains the

address of the called subroutine right-shifted by one bit. The return-address is the

address of the second subsequent instruction. Return-address is shifted right one

bit and stored in %o7. The right-shifted value stored in %o7 is a destination

suitable for direct use by JMP without modification.

Condition Codes:

Flags: Unaffected

−

Delay Slot Behavior:

The instruction immediately following CALL (CALL’s delay slot) is executed after

CALL, but before the destination instruction. There are restrictions on which

instructions may be used as a delay slot. (Refer to “Branch Delay Slots” on

page 23)

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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3232323232-Bit Instruction Set

CMP

Compare

Operation:

∅ ← RA − RB

Assembler Syntax:

Example:

CMP %rA,%rB

CMP %g0,%g1 ; set flags by %g0 - %g1

Description:

Subtract the contents of RB from RA, and discard the result. Set the condition

codes according to the subtraction. Neither RA nor RB are altered.

Condition Codes:

Flags:

∆

N: Result bit 31

V: Signed-arithmetic overflow

Z: Set if result is zero; cleared otherwise

C: Set if there was a borrow from the subtraction; cleared otherwise

Instruction Format:

Instruction Fields:

A = Register index of RA operand

B = Register index of RB operand

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32-Bit Instruction Set

CMPI

Compare Immediate

Operation:

∅ ← RA – (0x00.00 : K : IMM5)

CMPI & %rA,IMM5

Assembler Syntax:

Example:

Not preceded by PFX:

CMPI %i3,24 ; compare %i3 to 24

Preceded by PFX:

PFX %hi(1000)

CMPI %i4,%lo(1000)

Description:

Not preceded by PFX:

Subtract a 5-bit immediate value given by IMM5 from RA, and discard the result.

Set the condition codes according to the subtraction. RA is not altered.

Preceded by PFX:

The Immediate operand is extended from 5 to 16 bits by concatenating the

contents of the K-register (11 bits) with IMM5 (5 bits). The 16-bit immediate value

(K : IMM5) is zero-extended to 32 bits and subtracted from RA. Condition codes

are set and the result is discarded. RA is not altered.

Condition Codes:

Flags:

∆

N: Result bit 31

V: Signed-arithmetic overflow

Z: Set if result is zero; cleared otherwise

C: Set if there was a borrow from the subtraction; cleared otherwise

Instruction Format:

Instruction Fields:

Ri5

A = Register index of RA operand

IMM5 = 5-bit immediate value

IMM5

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3232323232-Bit Instruction Set

EXT16d

Half-Word Extract (Dynamic)

RA ← (0x00.00 : ^hnRA) where n = RB[1]

Operation:

Assembler Syntax:

Example:

EXT16d %rA,%rB

LD %i3,[%i4] ; get 32 bits from [%i4 & 0xFF.FF.FF.FC]

EXT16d %i3,%i4 ; extract short int at %i4

Description:

Extracts one of the two half-words in RA. The half-word to-be-extracted is chosen

by bit 1 of RB. The selected half-word is written into bits 15..0 of RA, and the

more-significant bits 31..16 are set to zero.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

B = Register index of operand RB

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32-Bit Instruction Set

EXT16s

Half-Word Extract (Static)

RA ← (0x00.00 : ^hnRA) where n = IMM1

EXT16s %rA,IMM1

Operation:

Assembler Syntax:

Example:

EXT16s %L3,1 ; %L3 gets upper short int of itself

Description:

Extracts one of the two half-words in RA. The half-word to-be-extracted is chosen

by the one-bit immediate value IMM1. The selected half-word is written into bits

15..0 of RA, and the more significant bits 31..16 are set to zero.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

Ri1u

A = Register index of operand RA

IMM1 = 1-bit immediate value

IMM1

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3232323232-Bit Instruction Set

EXT8d

Byte-Extract (Dynamic)

RA ← (0x00.00.00 : ^bnRA) where n = RB[1..0]

Operation:

Assembler Syntax:

Example:

EXT8d %rA,%rB

LD %g4,[%i0] ; get 32 bits from [%i0 & 0xFF.FF.FF.FC]

EXT8d %g4,%i0 ; extract the particular byte at %i0

Description:

Extracts one of the four bytes in RA. The byte to-be-extracted is chosen by bits

1..0 of RB (byte 3 being the most-significant byte of RA). The selected byte is

written into bits 7..0 of RA, and the more-significant bits 31..8 are set to zero.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

B = Register index of operand RB

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32-Bit Instruction Set

EXT8s

Byte-Extract (Static)

RA ← (0x00.00.00 : ^bnRA) where n = IMM2

EXT8s %rA,IMM2

Operation:

Assembler Syntax:

Example:

EXT8s %g6,3 ; %g6 gets the 3rd byte of itself

Description:

Extracts one of the four bytes in RA. The byte to-be-extracted is chosen by the

immediate value IMM2 (byte 3 being the most-significant byte of RA). The

selected byte is written into bits 7..0 of RA, and the more-significant bits 31..8 are

set to zero.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

Ri2u

A = Register index of operand RA

IMM2 = 2-bit immediate value

IMM2

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3232323232-Bit Instruction Set

FILL16

Half-Word Fill

R0 ← (^h0RA : ^h0RA)

Operation:

Assembler Syntax:

Example:

FILL16 %r0,%rA

FILL16 %r0,%i3 ; %r0 gets 2 copies of %i3[0..15]

; first operand must be %r0

Description:

The least significant half-word of RA is copied into both half-word positions

in %r0. %r0 is the only allowed destination operand for FILL instructions.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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32-Bit Instruction Set

FILL8

Byte-Fill

R0 ← (^b0RA : ^b0RA : ^b0RA : ^b0RA)

Operation:

Assembler Syntax:

Example:

FILL8 %r0,%rA

FILL8 %r0,%o3 ; %r0 gets 4 copies of %o3[0..7]

; first operand must be %r0

Description:

The least-significant byte of RA is copied into all four byte-positions in %r0. %r0

is the only allowed destination operand for FILL instructions.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields

A = Register index of operand RA

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3232323232-Bit Instruction Set

IF0

Equivalent to SKP1 Instruction

if (RA[IMM5] = = 1)

then begin

Operation:

if (Mem16[PC + 2] is PFX)

then PC ← PC + 6

else PC ← PC + 4

end

Assembler Syntax:

Example:

IF0 %rA,IMM5

IF0 %o3,21 ; do if 21st bit of %o3 is zero

ADDI %g0,1 ; increment if 21st bit clear

Description:

Skip next instruction if the single bit RA[IMM5] is 1. If the next instruction is PFX,

then both PFX and the instruction following PFX are skipped together.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

Ri5

A = Register index of operand RA

IMM5 = 5-bit immediate value

IMM5

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32-Bit Instruction Set

IF1

Equivalent to SKP0 Instruction

if (RA[IMM5] = = 0)

then begin

if (Mem16[PC + 2] is PFX)

Operation:

then PC ← PC + 6

else PC ← PC + 4

end

Assembler Syntax:

Example:

IF1 %rA,IMM5

ADDI %g0,1 ; include if bit 7 was set

Description:

Skip next instruction if the single bit RA[IMM5] is 0. If the next instruction is PFX,

then both PFX and the instruction following PFX are skipped together.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

Ri5

A = Register index of operand RA

IMM5 = 5-bit immediate value

IMM5

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3232323232-Bit Instruction Set

IFRnz

Equivalent to SKPRz Instruction

if (RA = = 0)

then begin

Operation:

if (Mem16[PC + 2] is PFX)

then PC ← PC + 6

else PC ← PC + 4

end

Assembler Syntax:

Example:

IFRnz %rA

IFRnz %o3

BSR SendIt ; only call if %o3 is not 0

NOP ; (delay slot) executed in either case

Description:

Skip next instruction if RA is equal to zero. If the next instruction is PFX, then both

PFX and the instruction following PFX are skipped together.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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32-Bit Instruction Set

IFRz

Equivalent to SKPRnz Instruction

if (RA ! = 0)

then begin

if (Mem16[PC + 2] is PFX)

Operation:

then PC ← PC + 6

else PC ← PC + 4

end

Assembler Syntax:

Example:

IFRz %rA

IFRz %g3

BSR SendIt ; only call if %g3 is zero

NOP ; (delay slot) executed in either case

Description:

Skip next instruction if RA is not zero. If the next instruction is PFX, then both PFX

and the instruction following PFX are skipped together.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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3232323232-Bit Instruction Set

IFS

Conditionally Execute Next Instruction

if (condition IMM4 is false)

then begin

Operation:

if (Mem16[PC + 2] is PFX)

then PC ← PC + 6

else PC ← PC + 4

end

Assembler Syntax:

Example:

IFS cc_IMM4

IFS cc_ne

BSR SendIt ; only call if Z flag set

NOP ; (delay slot) executed in either case

Description:

Execute next instruction if specified condition is true, skip if condition is false. If

the next instruction is PFX, then both PFX and the instruction following PFX are

skipped together.

Condition Codes:

Settings:

cc_nc 0x0 (not C)

cc_c 0x1 (C)

These condition

codes have

different numeric

values for IFS and

SKPS instructions.

cc_nz 0x2 (not Z)

cc_z 0x3 (Z)

cc_pl 0x4 (not N)

cc_mi 0x5 (N)

cc_lt 0x6 (N xor V)

cc_ge 0x7 (not (N xor V))

cc_gt 0x8 (Not (Z or (N xor V)))

cc_le 0x9 (Z or (N xorV))

cc_nv 0xa (not V)

cc_v 0xb (V)

cc_hi 0xc (not (C or Z))

cc_la 0xd (C or Z)

Additional alias flags allowed:

cc_cs = cc_c cc_n = cc_mi

cc_eq = cc_z cc_vs = cc_v

cc_cc = cc_nc

cc_ne = cc_nz

cc_vc = cc_nv

cc_p = cc_pl

Codes mean execute if, e.g., ifs cc_eq means execute if equal

Instruction Format:

Instruction Fields:

i4w

IMM4 = 4-bit immediate value

IMM4

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32-Bit Instruction Set

JMP

Computed Jump

PC ← (RA << 1)

Operation:

Assembler Syntax:

Example:

JMP %rA

JMP %o7 ; return

NOP ; (delay slot)

Description:

Jump to the target-address given by (RA << 1). Note that the target address will

always be half-word aligned for any value of RA.

Condition Codes:

Flags: Unaffected

−

Delay Slot Behavior:

The instruction immediately following JMP (JMP’s delay slot) is executed after

JMP, but before the destination instruction. There are restrictions on which

instructions may be used as a delay slot. (Refer to “Branch Delay Slots” on

page 23)

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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3232323232-Bit Instruction Set

Load 32-bit Data From Memory

Operation:

Not preceded by PFX:

RA ← Mem32[align32(RB)]

Preceded by PFX:

RA ← Mem32[align32(RB + σ(K) × 4))]

Assembler Syntax:

Example:

LD %rA,[%rB]

Not preceded by PFX:

LD %g0,[%i3] ; load word at [%i3] into %g0

Preceded by PFX:

PFX 7

; word offset

LD %g0,[%i3] ; load word at [%i3+28] into %g0

Description:

Not preceded by PFX:

Loads a 32-bit data value from memory into RA. Data is always read from a word-

aligned address given by bits 31..2 of RB (the two LSBs of RB are ignored).

Preceded by PFX:

The value in K is sign-extended and used as a word-scaled, signed offset. This

offset is added to the base-address RB (bits 1..0 ignored), and data is read from

the resulting word-aligned address.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

B = Register index of operand RB

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32-Bit Instruction Set

LDP

Load 32-bit Data From Memory (Pointer Addressing Mode)

Operation:

Not preceded by PFX:

RA ← Mem32[align32(RP + (IMM5 × 4))]

Preceded by PFX:

RA ← Mem32[align32(RP + (σ(K : IMM5) × 4))]

Assembler Syntax:

Example:

LDP %rA,[%rP,IMM5]

Not preceded by PFX:

LDP %o3,[%L2,3] ; Load %o3 from [%L2 + 12]

; second register operand must be

; one of %L0, %L1, %L2, or %L3

Preceded by PFX:

PFX %hi(100)

LDP %o3,[%L2,%lo(100)] ; load %o3 from [%L2 + 400]

Description:

Not preceded by PFX:

Loads a 32-bit data value from memory into RA. Data is always read from a word-

aligned address given by bits 31..2 of RP (the two LSBs of RP are ignored) plus

a 5-bit, unsigned, word-scaled offset given by IMM5.

This instruction is similar to LD, but additionally allows a positive 5-bit offset to be

applied to any of four base-pointers in a single instruction. The base-pointer must

be one of the four registers: %L0, %L1, %L2, or %L3.

Preceded by PFX:

A 16-bit offset is formed by concatenating the 11-bit K-register with IMM5 (5 bits).

The 16-bit offset (K : IMM5) is sign-extended to 32 bits, multiplied by four, and

added to bits 31..2 of RP to yield a word-aligned effective address.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

RPi5

A = Register index of operand RA

IMM5 = 5-bit immediate value

P = Index of base-pointer register, less 16

IMM5

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3232323232-Bit Instruction Set

LDS

Load 32-bit Data From Memory (Stack Addressing Mode)

RA ← Mem32[align32(%sp + (IMM8 × 4))]

Operation:

Assembler Syntax:

Example:

LDS %rA,[%sp,IMM8]

LDS %o1,[%sp,3] ; load %o1 from stack + 12

; second register can only be %sp

Description:

Loads a 32-bit data value from memory into RA. Data is always read from a word-

aligned address given by bits 31..2 of %sp (the two LSBs of %sp are ignored) plus

an 8-bit, unsigned, word-scaled offset given by IMM8.

Conventionally, software uses %o6 (aka %sp) as a stack-pointer. LDS allows

single-instruction access to any data word at a known offset in a 1Kbyte range

above %sp.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

Ri8

A = Register index of operand RA

IMM8 = 8-bit immediate value

IMM8

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32-Bit Instruction Set

LRET

Equivalent to JMP %o7

PC ← (%o7 << 1)

Operation:

Assembler Syntax:

Example:

LRET

LRET ; return

NOP ; (delay slot)

Description:

Jump to the target-address given by (%o7 << 1). Note that the target address will

always be half-word aligned for any value of %o7.

Condition Codes:

Flags: Unaffected

−

Delay Slot Behavior:

The instruction immediately following LRET (LRET’s delay slot) is executed after

LRET, but before the destination instruction. There are restrictions on which

instructions may be used as a delay slot. (Refer to “Branch Delay Slots” on

page 23)

Instruction Format:

Instruction Fields:

None (always uses %o7)

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3232323232-Bit Instruction Set

LSL

Logical Shift Left

RA ← (RA << RB[4..0]), zero-fill from right

Operation:

Assembler Syntax:

Example:

LSL %rA,%rB

LSL %L3,%g0 ; Shift %L3 left by %g0 bits

Description:

The value in RA is shifted-left by the number of bits indicated by RB [4..0] (bits

31..5 of RB are ignored).

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of RA operand

B = Register index of RB operand

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32-Bit Instruction Set

LSLI

Logical Shift Left Immediate

RA ← (RA << IMM5), zero-fill from right

Operation:

Assembler Syntax:

Example:

LSLI %rA,IMM5

LSLI %i1,6 ; Shift %i1 left by 6 bits

The value in RA is shifted-left by the number of bits indicated by IMM5.

Description:

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

Ri5

A = Register index of RA operand

IMM5 = 5-bit immediate value

IMM5

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3232323232-Bit Instruction Set

LSR

Logical Shift Right

RA ← (RA >> RB[4..0]), zero-fill from left

Operation:

Assembler Syntax:

Example:

LSR %rA,%rB

LSR %L3,%g0 ; Shift %L3 right by %g0 bits

Description:

The value in RA is shifted-right by the number of bits indicated by RB [4..0] (bits

RB[31..5] are ignored). The result is zero-filled from the left.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of RA operand

B = Register index of RB operand

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32-Bit Instruction Set

LSRI

Logical Shift Right Immediate

RA ← (RA >> IMM5), zero-fill from left

Operation:

Assembler Syntax:

Example:

LSRI %rA,IMM5

LSRI %g1,6 ; Right-shift %g1 by 6 bits

Description:

The value in RA is shifted-right by the number of bits indicated by IMM5. The

result is left-filled with zero.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

Ri5

A = Register index of RA operand

IMM5 = 5-bit immediate value

IMM5

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3232323232-Bit Instruction Set

MOV

RA ← RB

Operation:

Assembler Syntax:

Example:

MOV %rA,%rB

MOV %o0,%L3 ; copy %L3 into %o0

Copy the contents of RB to RA.

Flags: Unaffected

Description:

Condition Codes:

−

Instruction Format:

Instruction Fields:

A = Register index of RA operand

B = Register index of RB operand

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32-Bit Instruction Set

MOVHI

Move Immediate Into High Half-Word

^h1RA ← (K : IMM5), ^h0RA unaffected

Operation:

Assembler Syntax:

Example:

MOVHI %rA,IMM5

Not preceded by PFX:

MOVHI %g3,23 ; upper 16 bits of %g3 get 23

Preceded by PFX:

PFX %hi(100)

MOVHI %g3,%lo(100) ; upper 16 bits of %g3 get 100

Description:

Not preceded by PFX:

Copy IMM5 to the most significant half-word (bits 31..16) of RA. The least

significant half-word (bits 15..0) is unaffected.

Preceded by PFX:

The immediate operand is extended from 5 to 16 bits by concatenating the

contents of the K-register (11 bits) with IMM5 (5 bits). The 16-bit immediate value

(K : IMM5) is copied into the most significant half-word (bits 31..16) of RA. The

least significant half-word (bits 15..0) is unaffected.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

Ri5

A = Register index of operand RA

IMM5 = 5-bit immediate value

IMM5

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3232323232-Bit Instruction Set

MOVI

Move Immediate

RA ← (0x00.00 : K : IMM5)

Operation:

Assembler Syntax:

Example:

MOVI %rA,IMM5

Not preceded by PFX:

MOVI %o3,7 ; load %o3 with 7

Preceded by PFX:

PFX %hi(301)

MOVI %o3,%lo(301) ; load %o3 with 301

Description:

Not preceded by PFX:

Loads register RA with a zero-extended 5-bit immediate value (in the range

[0..31]) given by IMM5.

Preceded by PFX:

Loads register RA with a zero-extended 16-bit immediate value (in the range

[0..65535]) given by (K : IMM5).

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

Ri5

A = Register index of RA operand

IMM5 = 5-bit immediate value

IMM5

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32-Bit Instruction Set

MSTEP

Multiply-Step

If (R0[31] = = 1)

Operation:

then R0 ← (R0 << 1) + RA

else R0 ← (R0 << 1)

MSTEP %rA

Assembler Syntax:

Example:

MSTEP %g1 ; accumulate partial-product

Description:

Implements a single step of an unsigned multiply. The multiplier in %r0 and

multiplicand in RA. Result is accumulated into %r0. RA is not affected.

The following code fragment implements a 16-bit × 16-bit into 32-bit multiply. On

entry, %r0 and %r1 contain the multiplier and multiplicand, respectively. The

result is left in %r0.

SWAP %r0 ; Move multiplier into place

MSTEP %r1

… A total of 16 MSTEPs …

MSTEP %r1

; 32-bit product left in %r0

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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3232323232-Bit Instruction Set

MUL

Multiply

Operation:

R0 ← (R0 & 0x0000.ffff) x (RA & 0x0000.ffff)

Assembler Syntax:

Example:

MUL %rA

MUL %i5

Description:

Multiply the low half-words of %r0 and %rA together, and put the 32 bit result into

%r0. This performs an integer multiplication of two signed 16-bit numbers to

produce a 32-bit signed result, or multiplication of two unsigned 16-bit numbers

to produce an unsigned 32-bit result.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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32-Bit Instruction Set

NEG

Arithmetic Negation

RA ← 0 – RA

Operation:

Assembler Syntax:

Example:

NEG %rA

NEG %o4

Description:

Negate the value of RA. Perform two’s complement negation of RA.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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3232323232-Bit Instruction Set

NOP

Equivalent to MOV %g0, %g0

Operation:

None

Assembler Syntax:

Example:

NOP

NOP ; do nothing

No operation.

Flags: Unaffected

Description:

Condition Codes:

−

Instruction Format:

Instruction Fields:

None

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32-Bit Instruction Set

NOT

Logical Not

RA ← ~RA

Operation:

Assembler Syntax:

Example:

NOT %rA

NOT %o4

Description:

Bitwise-invert the value of RA.

Flags: Unaffected

Condition Codes:

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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3232323232-Bit Instruction Set

Bitwise Logical OR

Operation:

Not preceded by PFX:

RA ← RA | RB

Preceded by PFX:

RA ← RA | (0x00.00 : K : IMM5)

Assembler Syntax:

Not preceded by PFX:

OR %rA,%rB

Preceded by PFX:

PFX %hi(const)

OR %ra,%lo(const)

Example:

Not preceded by PFX:

OR %i0,%i1; OR %i1 into %i0

Preceded by PFX:

PFX %hi(3333)

OR %i0,%lo(3333) ; OR %i0 with 3333

Description:

Not preceded by PFX:

Logically-OR the individual bits in RA with the corresponding bits in RB; store the

result in RA.

Preceded by PFX:

When prefixed, the RB operand is replaced by an immediate constant formed by

concatenating the contents of the K-register (11 bits) with IMM5 (5 bits). This

16-bit value is zero-extended to 32 bits, then bitwise-ORed with RA. The result is

written back into RA.

Condition Codes:

Flags:

∆

–

∆

–

N: Result bit 31

Z: Set if result is zero; cleared otherwise

RR, Ri5

Instruction Format:

Instruction Fields

A = Register index of operand RA

B = Register index of operand RB

IMM5 = 5-bit immediate value

Not preceded by PFX (RR)

Preceded by PFX (Ri5)

IMM5

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32-Bit Instruction Set

PFX

Prefix

K ← IMM11 (K set to zero by all other instructions)

PFX IMM11

Operation:

Assembler Syntax:

Example:

PFX 3 ; affects next instruction

Description:

Loads the 11-bit constant value IMM11 into the K-register. The value in the

K-register may affect the next instruction. K is set to zero after every instruction

other than PFX. The result of two consecutive PFX instructions is not defined.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

i11

IMM11 = 11-bit immediate value

IMM11

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3232323232-Bit Instruction Set

RDCTL

Read Control Register

RA ← CTLk

Operation:

Assembler Syntax:

Example:

RDCTL %rA

Not preceded by PFX:

RDCTL %g7 ; Loads %g7 from STATUS reg (%ctl0)

Preceded by PFX:

PFX 2

RDCTL %g7 ; Loads %g7 from WVALID reg (%ctl2)

Description:

Not preceded by PFX:

Loads RA with the current contents of the STATUS register (%ctl0).

Preceded by PFX:

Loads RA with the current contents of the control register selected by K. See

“Control Registers” on page 4. for a list of control registers and their indices.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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32-Bit Instruction Set

RESTORE

Restore Caller’s Register Window

CWP ← CWP + 1

Operation:

if (old-CWP = = HI_LIMIT)

then TRAP #2

Assembler Syntax:

Example:

RESTORE

RESTORE ; bump up the register window

Description:

Moves CWP up by one position in the register file. If CWP is equal to HI_LIMIT

(from the WVALID register) before the RESTORE instruction, then a window-

overflow trap (TRAP #2) is generated.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

None

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3232323232-Bit Instruction Set

RET

Equivalent to JMP %i7

PC ← (%i7 << 1)

RET

Operation:

Assembler Syntax:

Example:

RET ; return

RESTORE ; (restores caller’s register window)

Description:

Jump to the target-address given by (%i7 << 1). Note that the target address will

always be half-word aligned for any value of %i7.

Condition Codes:

Flags: Unaffected

−

Delay Slot Behavior:

The instruction immediately following RET (RET’s delay slot) is executed after

RET, but before the destination instruction. There are restrictions on which

instructions may be used as a delay slot (Refer to “Branch Delay Slots” on

page 23).

Instruction Format:

Instruction Fields:

None (always uses %i7)

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32-Bit Instruction Set

RLC

Rotate Left Through Carry

C ← RA[31]

Operation:

RA ← (RA << 1) : C

RLC %rA

Assembler Syntax:

Example:

RLC %i4 ; rotate %i4 left one bit

Description:

Rotates the bits of RA left by one position through the carry flag.

Condition Codes:

Flags:

–

∆

C: Bit 31 of RA before rotating

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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3232323232-Bit Instruction Set

RRC

Rotate Right Through Carry

C ← RA[0]

Operation:

RA ← C : (RA >> 1)

RRC %rA

Assembler Syntax:

Example:

RRC %i4 ; rotate %i4 right one bit

Description:

Rotates the bits of RA right by one position through the carry flag.

If Preceded by PFX:

Condition Codes:

Unaffected

Flags:

–

∆

C: Bit 0 of RA before rotating

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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32-Bit Instruction Set

SAVE

Save Caller’s Register Window

CWP ← CWP – 1

Operation:

%sp ← %fp – (IMM8 × 4)

If (old-CWP = = LO_LIMIT)

then TRAP #1

Assembler Syntax:

Example:

SAVE %sp,-IMM8

SAVE %sp,-23 ; start subroutine with new regs

; first operand can only be %sp

Description:

Moves CWP down by one position in the register file. If CWP is equal to LO_LIMIT

(from the WVALID register) before the SAVE instruction, then a window-

underflow trap (TRAP #1) is generated.

%sp (in the newly opened register window) is loaded with the value of %fp minus

IMM8 times 4. %fp in the new window is the same as %sp in the old (caller’s)

window.

SAVE is conventionally used upon entry to subroutines to open up a new,

disposable set of registers for the subroutine and simultaneously open up a stack-

frame.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

i8v

IMM8 = 8-bit immediate value

IMM8

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3232323232-Bit Instruction Set

SEXT16

Sign Extend 16-bit Value

RA ← σ(^h0RA)

Operation:

Assembler Syntax:

Example:

SEXT16 %rA

SEXT16 %g3 ; convert signed short to signed long

Replace bits 16..31 of RA with bit 15 of RA.

Flags: Unaffected

Description:

Condition Codes:

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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32-Bit Instruction Set

SEXT8

Sign Extend 8-bit Value

RA ← σ(^b0RA)

Operation:

Assembler Syntax:

Example:

SEXT8 %rA

SEXT8 %o3 ; convert signed byte to signed long

Replace bits 8..31 of RA with bit 7 of RA.

Flags: Unaffected

Description:

Condition Codes:

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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3232323232-Bit Instruction Set

SKP0

Skip If Register Bit Is 0

if (RA[IMM5] = = 0)

then begin

Operation:

if (Mem16[PC + 2] is PFX)

then PC ← PC + 6

else PC ← PC + 4

end

Assembler Syntax:

Example:

SKP0 %rA,IMM5

ADDI %g0, 1 ; include if bit 7 was set

Description:

Skip next instruction if the single bit RA[IMM5] is 0. If the next instruction is PFX,

then both PFX and the instruction following PFX are skipped together.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

Ri5

A = Register index of operand RA

IMM5 = 5-bit immediate value

IMM5

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32-Bit Instruction Set

SKP1

Skip If Register Bit Is 1

if (RA[IMM5] = = 1)

then begin

Operation:

if (Mem16[PC + 2] is PFX)

then PC ← PC + 6

else PC ← PC + 4

end

Assembler Syntax:

Example:

SKP1 %rA,IMM5

SKP1 %o3,21 ; skip if 21st bit of %o3 is set

ADDI %g0, 1 ; increment if 21st bit clear

Description:

Skip next instruction if the single bit RA[IMM5] is 1. If the next instruction is PFX,

then both PFX and the instruction following PFX are skipped together.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

Ri5

A = Register index of operand RA

IMM5 = 5-bit immediate value

IMM5

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3232323232-Bit Instruction Set

SKPRnz

Skip If Register Not Equal To 0

if (RA ! = 0)

then begin

Operation:

if (Mem16[PC + 2] is PFX)

then PC ← PC + 6

else PC ← PC + 4

end

Assembler Syntax:

Example:

SKPRnz %rA

SKPRnz %g3

BSR SendIt ; only call if %g3 is zero

NOP ; (delay slot) executed in either case

Description:

Skip next instruction if RA is not zero. If the next instruction is PFX, then both PFX

and the instruction following PFX are skipped together.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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32-Bit Instruction Set

SKPRz

Skip If Register Equals 0

if (RA = = 0)

then begin

Operation:

if (Mem16[PC + 2] is PFX)

then PC ← PC + 6

else PC ← PC + 4

end

Assembler Syntax:

Example:

SKPRz %rA

SKPRz %o3

BSR SendIt ; only call if %o3 is not 0

NOP ; (delay slot) executed in either case

Description:

Skip next instruction if RA is equal to zero. If the next instruction is PFX, then both

PFX and the instruction following PFX are skipped together.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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3232323232-Bit Instruction Set

SKPS

Skip On Condition Code

if (condition IMM4 is true)

then begin

Operation:

if (Mem16[PC + 2] is PFX)

then PC ← PC + 6

else PC ← PC + 4

end

Assembler Syntax:

Example:

SKPS cc_IMM4

SKPS cc_ne

BSR SendIt ; only call if Z flag clear

NOP ; (delay slot) executed in either case

Description:

Skip next instruction if specified condition is true. If the next instruction is PFX,

then both PFX and the instruction following PFX are skipped together.

Condition Codes:

Settings:

cc_c 0x0 (C)

cc_nc 0x1 (not C)

cc_z 0x2 (Z)

These condition

codes have

different numeric

values for IFS and

SKPS instructions.

cc_nz 0x3 (not Z)

cc_mi 0x4 (N)

cc_pl 0x5 (not N)

cc_ge 0x6 (not (N xor V))

cc_lt 0x7 (N xor V)

cc_le 0x8 (Z or (N xor V))

cc_gt 0x9 (Not (Z or (N xorV)))

cc_v 0xa (V)

cc_nv 0xb (not V)

cc_la 0xc (C or Z)

cc_hi 0xd (not (C or Z))

Additional alias flags allowed:

cc_cs = cc_c cc_n = cc_mi

cc_eq = cc_z cc_vs = cc_v

cc_cc = cc_nc

cc_ne = cc_nz

cc_vc = cc_nv

cc_p = cc_pl

Codes mean skip if, e.g., skps cc_eq means skip if equal

Instruction Format:

Instruction Fields:

i4w

IMM4 = 4-bit immediate value

IMM4

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32-Bit Instruction Set

Store 32-bit Data To Memory

Operation:

Not preceded by PFX:

Mem32[align32(RB)] ← RA

Preceded by PFX:

Mem32[align32(RB + (σ(K) × 4))] ← RA

Assembler Syntax:

Example:

ST [%rB],%rA

Not preceded by PFX:

ST [%g0],%i3 ; %g0 is pointer, %i3 stored

Preceded by PFX:

PFX 3

; word offset

ST [%g0],%i3 ; store to location %g0 + 12

Description:

Not preceded by PFX:

Stores the 32-bit data value in RA to memory. Data is always written to a word-

aligned address given by bits 31..2 of RB (the two LSBs of RB are ignored).

Preceded by PFX:

The value in K is sign-extended and used as a word-scaled, signed offset. This

offset is added to the base-pointer address RB (bits 1..0 ignored), and data is

written to the resulting word-aligned address.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields

A = Register index of operand RA

B = Register index of operand RB

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3232323232-Bit Instruction Set

ST16d

Store 16-Bit Data To Memory (Computed Half-Word Pointer Address)

Operation:

Not preceded by PFX :

^hnMem32[align32(RA)] ← ^hnR0 where n = RA[1]

Preceded by PFX:

^hnMem32[align32(RA + (σ(K) × 4))] ← ^hnR0 where n = RA[1]

Assembler Syntax:

Example:

ST16d [%rA],%r0

Not preceded by PFX:

FILL16 %r0,%g7 ; duplicate short of %g7 across %r0

ST16d [%o3],%r0 ; store %o3[1]th short int from

; %r0 to [%o3]

; second operand can only be %r0

Preceded by PFX:

FILL16 %r0,%g3

PFX 5

ST16d [%o3],%r0 ; same as above, offset

; 20 bytes in memory

Description:

Not preceded by PFX:

Stores one of the two half-words of %r0 to memory at the half-word-aligned

address given by RA. The bits RA[1] selects which half-word in %r0 get stored

(half-word 1 is the most-significant). RA[0] is ignored.

ST16d may be used in combination with FILL16 to implement a two-instruction

half-word-store operation. Given a half-word held in bits 15..0 of any register %rX,

the following sequence writes this half-word to memory at the half-word-aligned

address given by RA:

FILL16 %r0,%rX

ST16d [%rA],%r0

Preceded by PFX:

The value in K is sign-extended and used as a word-scaled, signed offset. This

offset is added to the base-address RA and data is written to the resulting byte-

address.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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32-Bit Instruction Set

ST16s

Store 16-Bit Data To Memory (Static Half-Word-Offset Address)

Operation:

Not preceded by PFX:

^hnMem32[align32(RA)] ← ^hnR0 where n = IMM1

Preceded by PFX:

^hnMem32[align32(RA + (σ(K) × 4))] ← ^hnR0 where n = IMM1

Assembler Syntax:

Example:

ST16s [%rA],%r0,IMM1

ST16s [%g8],%r0,1

Description:

Not preceded by PFX:

Stores one of the two half-words of %r0 to memory at the half-word-aligned

address given by (RA[31..2] + IMM1 × 2). The two bits RA[1..0] are ignored.

IMM2 selects which half-word of %r0 is stored (half-word #1 is most significant).

ST16s may be used in combination with FILL16 to implement a half-word-store

operation to a half-word-offset from a word-aligned base-address. Given a half-

word held in bits 15..0 of any register %rX, the following sequence writes this half-

word to memory at the half-word-aligned address given by (RA + Y × 2) (RA

presumed to hold a word-aligned pointer):

FILL16 %r0,%rX

PFX Y >> 2

ST16s [%rA],%r0,(Y >> 1) & 1

Preceded by PFX:

A 12-bit signed, half-word-scaled offset is formed by concatenating K with

IMM1.This offset (K : IMM1) is half-word-scaled (multiplied by 2), sign-extended

to 32 bits, and used as the half-word-offset for the ST-operation.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields

Ri1u

A = Register index of operand RA

IMM1 = 1-bit immediate value

IMM1

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3232323232-Bit Instruction Set

ST8d

Store 8-Bit Data To Memory (Computed Byte-Pointer Address)

Not preceded by PFX:

^bnMem32[align32(RA)] ← ^bnR0 where n = RA[1..0]

Operation:

Preceded by PFX:

^bnMem32[align32(RA + σ(K) × 4))] ← ^bnR0 where n = RA[1..0]

ST8d[%rA],%r0

Assembler Syntax:

Example:

Not preceded by PFX:

FILL8 %r0,%g7 ; duplicate low byte of %g7 across %r0

ST8d [%o3],%r0 ; store %o3[1..0]th byte from

; %r0 to [%o3]

; second operand can only be %r0

Preceded by PFX:

FILL8 %r0,%g3

PFX 5

ST8d [%o3],%r0 ; same as above, offset

; 20 bytes in memory

Description:

Not preceded by PFX:

Stores one of the four bytes of %r0 to memory at the byte-address given by RA.

The two bits RA[1..0] select which byte in %r0 get stored (byte 3 is the most-

significant).

ST8d may be used in combination with FILL8 to implement a two-instruction byte-

store operation. Given a byte held in bits 7..0 of any register %rX, the following

sequence writes this byte to memory at the byte-address given by RA:

FILL8 %r0,%rX

ST8d [%rA],%r0

Preceded by PFX:

The value in K is sign-extended and used as a word-scaled, signed offset. This

offset is added to the base-address RA and data is written to the resulting byte-

address.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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32-Bit Instruction Set

ST8s

Store 8-bit Data To Memory (Static Byte-Offset Address)

Operation:

Not preceded by PFX:

^bnMem32[align32(RA)] ← ^bnR0 where n = IMM2

Preceded by PFX:

^bnMem32[align32(RA + (σ(K) × 4))] ← ^bnR0 where n = IMM2

Assembler Syntax:

Example:

ST8s [%rA],%r0,IMM2

Not preceded by PFX:

MOVI %g4,12

ST8s [%g4],%r0,3 ; store high byte of %r0 to mem[15]

Preceded by PFX:

PFX 9

ST8s [%g4],%r0,2 ; store byte 2 of %r0 to

; mem[%g4 + 36 + 2]

Description:

Not preceded by PFX:

Stores one of the four bytes of %r0 to memory at the byte-address given by

(RA[31..2] plus IMM2). The two bits RA[1..0] are ignored. IMM2 selects which

byte of %r0 is stored (byte 3 is most significant).

ST8s may be used in combination with FILL8 to implement a byte-store operation

to a byte-offset from a word-aligned base pointer. Given a byte held in bits 7..0 of

any register %rX, the following sequence writes this byte to memory at the byte-

address given by (RA + Y ) (RA presumed to hold a word-aligned pointer):

FILL8 %r0,%rX

PFX Y >> 2

ST8s [%rA],%r0,Y & 3

Preceded by PFX:

A 13-bit signed, byte-scaled offset is formed by concatenating K with IMM2. This

offset (K : IMM2) is sign-extended to 32 bits and used as the byte-offset for the

ST-operation.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

Ri2u

A = Register index of operand RA

IMM2 = 2-bit immediate value

IMM2

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3232323232-Bit Instruction Set

STP

Store 32-bit Data To Memory (Pointer Addressing Mode)

Operation:

Not preceded by PFX:

Mem32[align32(RP + (IMM5 × 4))] ← RA

Preceded by PFX:

Mem32[align32(RP + (σ(K : IMM5) × 4))] ← RA

Assembler Syntax:

Example:

STP [%rP,IMM5],%rA

Not preceded by PFX:

STP [%L2,3],%g3 ; Store %g3 to location [%L2 + 12]

Preceded by PFX:

PFX %hi(102)

STP [%L2,%lo(102)],%g3 ; Store %g3 to

; location [%L2 + 408]

Description:

Not preceded by PFX:

Stores the 32-bit data value in RA to memory. Data is always written to a word-

aligned address given by bits [31..2] of RP (the two LSBs of RP are ignored) plus

a 5-bit, unsigned, word-scaled offset given by IMM5.

This instruction is similar to ST, but additionally allows a positive 5-bit offset to be

applied to any of four base-pointers in a single instruction. The base-pointer must

be one of the four registers: %L0, %L1, %L2, or %L3.

Preceded by PFX:

A 16-bit offset is formed by concatenating the 11-bit K-register with IMM5 (5 bits).

The 16-bit offset (K : IMM5) is sign-extended to 32 bits, multiplied by four, and

added to bits 31..2 of RP to yield a word-aligned effective address.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

RPi5

A = Register index of operand RA

IMM5 = 5-bit immediate value

P = Index of base-pointer register, less 16

IMM5

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32-Bit Instruction Set

STS

Store 32-bit Data To Memory (Stack Addressing Mode)

Mem32[align32(%sp + (IMM8 × 4))] ← RA

Operation:

Assembler Syntax:

Example:

STS [%sp,IMM8],%rA

STS [%sp,17],%i5 ; store %i5 at stack + 68

; first register can only be %sp

Description:

Stores the 32-bit value in RA to memory. Data is always written to a word-aligned

address given by bits 31..2 of %sp (the two LSBs of %sp are ignored) plus an 8-

bit, unsigned, word-scaled offset given by IMM8.

Conventionally, software uses %o6 (aka %sp) as a stack-pointer. STS allows

single-instruction access to any data word at a known offset in a 1Kbyte range

above %sp.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

Ri8

A = Register index for operand RA

IMM8 = 8-bit immediate value

IMM8

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3232323232-Bit Instruction Set

STS16s

Store 16-bit Data To Memory (Stack-Addressing Mode)

Operation:

^hnMem32[align32(%sp + IMM9 × 2)] ← ^hnR0 where n = IMM9[0]

Assembler Syntax:

Example:

STS16s [%sp,IMM9],%r0

STS16s [%sp,7],%r0 ; can only be %sp and %r0

Description:

Stores one of the two half-words of %r0 to memory at the half-word-aligned

address given by (%sp plus IMM9 × 2). The least-significant bit of IMM9 selects

which half-word of %r0 is stored (half-word 1 is most significant).

STS16s may be used in combination with FILL16 to implement a 16-bit store

operation to a half-word offset from the stack-pointer in a 1Kbyte range. Given a

half-word held in bits 15..0 of any register %rX, the following sequence writes this

half-word to memory at the half-word-offset Y from %sp (%sp presumed to hold

a word-aligned address):

FILL16 %r0,%rX

STS16s [%sp,Y],%r0

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

IMM9 = 9-bit immediate value

IMM9

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32-Bit Instruction Set

STS8s

Store 8-bit Data To Memory (Stack-Addressing Mode)

Operation:

^bnMem32[align32(%sp + IMM10)] ← ^bnR0 where n = IMM10[1..0]

Assembler Syntax:

Example:

STS8s [%sp,IMM10],%r0

STS8s [%sp,13],%r0 ; can only be %sp and %r0

Description:

Stores one of the four bytes of %r0 to memory at the byte-address given by (%sp

plus IMM10). The two least-significant bits of IMM10 selects which byte of %r0 is

stored (byte 3 is most significant).

STS8s may be used in combination with FILL8 to implement a byte-store

operation to a byte-offset from the stack-pointer in a 1Kbyte range. Given a byte

held in bits 7..0 of any register %rX, the following sequence writes this byte to

memory at the byte-offset Y from %sp (%sp presumed to hold a word-aligned

address):

FILL8 %r0,%rX

STS8s [%sp,Y],%r0

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

i10

IMM10 = 10-bit immediate value

IMM10

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3232323232-Bit Instruction Set

SUB

Subtract

RA ← RA − RB

Operation:

Assembler Syntax:

Example:

SUB %rA,%rB

SUB %i3,%g0 ; SUB %g0 from %i3

Description:

Subtracts the contents of RB from RA, stores result in RA.

Flags:

Condition Codes:

∆

N: Result bit 31

V: Signed-arithmetic overflow

Z: Set if result is zero; cleared otherwise

C: Set if there was a borrow from the subtraction; cleared otherwise

Instruction Format:

Instruction Fields:

A = Register index of RA operand

B = Register index of RB operand

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32-Bit Instruction Set

SUBI

Subtract Immediate

Operation:

RA ← RA − (0x00.00 : K : IMM5)

Assembler Syntax:

Example:

subi %rB,IMM5

Not preceded by PFX:

SUBI %L5,6 ; subtract 6 from %L5

Preceded by PFX:

PFX %hi(1000)

SUBI %o3,%lo(1000) ; subtract 1000 from %o3

Description:

Not preceded by PFX:

Subtracts the immediate value from the contents of RA. The immediate value is

in the range of [0..31].

Preceded by PFX:

The Immediate operand is extended from 5 to 16 bits by concatenating the

contents of the K-register (11 bits) with IMM5 (5 bits). The 16-bit immediate value

(K : IMM5) is zero-extended to 32 bits and subtracted from register A.

Condition Codes:

Flags:

∆

N: Result bit 31

V: Signed-arithmetic overflow

Z: Set if result is zero; cleared otherwise

C: Set if there was a borrow from the subtraction; cleared otherwise

Instruction Format:

Instruction Fields:

Ri5

A = Register index of RA operand

IMM5 = 5-bit immediate value

IMM5

100

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3232323232-Bit Instruction Set

SWAP

Swap Register Half-Words

RA ← ^h0RA : ^h1RA

Operation:

Assembler Syntax:

Example:

SWAP %rA

SWAP %g3 ; Exchange two half-words in %g3

Description:

Swaps (exchanges positions) of the two 16-bit half-word values in RA. Writes

result back into RA.

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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32-Bit Instruction Set

TRAP

Unconditional Trap

Operation:

ISTATUS ← STATUS

IE ← 0

CWP ← CWP − 1

IPRI ← IMM6

%o7 ← ((PC + 2) >> 1)

PC ← Mem32[VECBASE + (IMM6 × 4)] << 1

Assembler Syntax:

Example:

TRAP IMM6

TRAP 0 ; reset the board

Description:

CWP is decremented by one, opening a new register-window for the trap-handler.

Interruptsaredisabled (IE ← 0). The pre-TRAP STATUSregisteriscopied intothe

ISTATUS register.

Transfer execution to trap handler number IMM6. The address of the trap-handler

is read from the vector table which starts at the memory address VECBASE

(VECBASE is configurable). A 32-bit value is fetched from the word-aligned

address (VECBASE + IMM6 × 4). The fetched value is multiplied by two and

transferred into PC. The address of the instruction immediately following the

TRAP instruction is placed in %o7. The value in %o7 is suitable for use as a

return-address for TRET without modification. The return-address convention for

TRAP is different than BSR/CALL, because TRAP does not have a delay-slot.

A TRAP instruction will transfer execution to the indicated trap-handler even if the

IE bit in the STATUS register is 0.

Condition Codes:

Flags: Unaffected

−

Delay Slot Behavior:

TRAP does not have a delay slot. The instruction immediately following TRAP is

not executed before the target trap-handler. The return-address used by TRET

points to the instruction immediately following TRAP.

Instruction Format:

Instruction Fields:

i6v

IMM6 = 6-bit immediate value

IMM6

102

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3232323232-Bit Instruction Set

TRET

Trap Return

Operation:

PC ← (RA << 1)

STATUS ← ISTATUS

Assembler Syntax:

Example:

TRET %ra

TRET %o7 ; return from TRAP

Description:

Execution is transferred to the address given by (RA << 1). The value written in

%o7 by TRAP is suitable for use as a return-address without modification.

The value in ISTATUS is copied into the STATUS register (this restores the pre-

TRAP register window, because CWP is part of STATUS).

Condition Codes:

Flags: Unaffected

−

Instruction Format:

Instruction Fields:

A = Register index of operand RA

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32-Bit Instruction Set

WRCTL

Write Control Register

Operation:

CTLk ← RA

Assembler Syntax:

Example:

WRCTL %rA

Not preceded by PFX:

WRCTL %g7 ; writes %g7 to STATUS reg

NOP ; required

Preceded by PFX:

PFX 1

WRCTL %g7 ; writes %g7 to ISTATUS reg

Description:

Not preceded by PFX:

Loads the STATUS register with RA. WRTCL to STATUS must be followed by a

NOP instruction.

Preceded by PFX:

Writes the value in RA to the machine-control register selected by K. See the

programmer’s model for a list of the machine-control registers and their indices.

Condition Codes:

If the target of WRCTL is the STATUS register, then the condition-code flags are

directly set by the WRCTL operation from bits RA[3..0]. For any other WRCTL

target register, the condition codes are unaffected.

Instruction Format:

Instruction Fields:

A = Register index of operand RA

104

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3232323232-Bit Instruction Set

XOR

Bitwise Logical Exclusive OR

Operation:

Not preceded by PFX:

RA ← RA ⊕ RB

Preceded by PFX:

RA ← RA ⊕ (0x00.00 : K : IMM5)

Assembler Syntax:

Not preceded by PFX:

XOR %rA,%rB

Preceded by PFX:

PFX %hi(const)

XOR %rA,%lo(const)

Example:

Not preceded by PFX:

XOR %g0,%g1 ; XOR %g1 into %g0

Preceded by PFX:

PFX %hi(16383)

XOR %o0,%lo(16383) ; XOR %o0 with 16383

Description:

Not preceded by PFX:

Logically-exclusive-OR the individual bits in RA with the corresponding bits in RB;

store the result in RA.

Preceded by PFX:

When prefixed, the RB operand is replaced by an immediate constant formed by

concatenating the contents of the K-register (11 bits) with IMM5 (5 bits). This

16-bit value is zero-extended to 32 bits, then bitwise-exclusive-ORed with RA.

The result is written back into RA.

Condition Codes:

Flags:

∆

–

∆

–

N: Result bit 31

Z: Set if result is zero, cleared otherwise

RR, Ri5

Instruction Format:

Instruction Fields:

A = Register index of operand RA

B = Register index of operand RB

IMM5 = 5-bit immediate value

Not preceded by PFX (RR)

Preceded by PFX (Ri5)

IMM5

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Index

Numerics

5/16-bit Immediate Value 10

CALL instruction 44

Call Subroutine 44

CLR_IE(%ctl8) 7

About This Manual iii

ABS instruction 34

Absolute Value 34

Absolute-Jump Instructions 15

Arithmetic Negation 72

Arithmetic Shift Right 39

Arithmetic Shift Right Immediate 40

Complex Exception Handlers 22

Computed Jump 58

Condition Code Flags 6

Conditional Instructions 15

Conditionally Execute Next Instruction (IFS) 57

Control Registers 4

Current Window Pointer (CWP) 5

Direct CWP Manipulation 24

Direct Software Exceptions

(TRAP Instructions) 19

ASRI instruction 40

BGEN instruction 41

Bit Generate 41

Equivalent to JMP %i7 (RET) 79

Equivalent to JMP %o7 62

Bitwise Logical AND 37

Bitwise Logical AND NOT 38

Bitwise Logical Exclusive OR 105

Bitwise Logical OR 75

BR instruction 42

Equivalent to MOV %g0, %g0 (NOP) 73

Equivalent to SKP0 Instruction 54

Equivalent to SKP1 Instruction (IFO) 53

Equivalent to SKPRnz Instruction (IFRz) 56

Equivalent to SKPRz Instruction (IFRnz) 55

Exception Handling Overview 16

Exception Processing Sequence 19

Exception Vector Table 16

Branch 42

branch delay slot 14

Branch Delay Slots 23

branch delay slots 23

Branch To Subroutine 43

BSR instruction 43

Exceptions 16

EXT16D instruction 47

EXT16S instruction 48

Byte-Extract (Dynamic) 49

Byte-Extract (Static) 50

Byte-Fill 52

EXT8D instruction 49

EXT8S instruction 50

External Hardware Interrupt Sources 17

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Index

FILL16 instruction 51

Memory Access Overview 7

MOV instruction 67, 7 3

Move Immediate 69

Move Immediate Into High Half-Word 68

Full Width Register-Indirect with Offset 13

General-Purpose Registers 2

GNU Compiler/Assembler

Pseudo-Instructions 31

Multiply 71

Multiply-Step 70

Half-Word Extract (Dynamic) 47

Half-Word Extract (Static) 48

Half-Word Fill 51

NEG instruction 72

Nios CPU Block Diagram 22

Instruction Format 26

Instruction Set 2

Internal Exception Sources 17

Interrupt Enable (IE) 5

Interrupt Priority (IPRI) 5

ISTATUS (%ctl1) 6

OR instruction 75

Partial Width Register-Indirect 12

Partial Width Register-Indirect with Offset 13

PFX instruction 76

Pipeline Implementation 22

Pipeline Operation 23

Prefix 76

Program-Flow Control 14

Programmer ’s Model 3

RDCTL instruction 77

Read Control Register 77

Reading from Memory (or Peripherals) 8

Relative-Branch Instructions 14

Restore Caller ’s Register Window 78

RESTORE instruction 78

RET instruction 79

Load 32-bit Data From Memory 59

Load 32-bit Data From Memory

(Pointer Addressing Mode) 60

Load 32-bit Data From Memory

(Stack Addressing Mode) 61

Logical Not 74

Logical Shift Left 63

Logical Shift Left Immediate 64

Logical Shift Right 65

Logical Shift Right Immediate 66

Rotate Left Through Carry 80

LSLI instruction 64

LSR instruction 65

LSRI instruction 66

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Index

Rotate Right Through Carry 81

RRC instruction 81

Save Caller ’s Register Window 82

STS16s instruction 97

Sign Extend 16-bit Value 83

Sign Extend 8-bit Value 84

Simple and Complex Exception Handlers 21

Simple Exception Handlers 21

Skip If Register Bit Is 0 85

Skip If Register Bit Is 1 86

Skip If Register Equals 0 88

Skip If Register Not Equal To 0 87

Skip On Condition Code 89

SKP0 instruction 85

Subtract Immediate 100

SWAP instruction 101

Swap Register Half-Words 101

The K Register 4

The Program Counter 4

TRAP instruction 15, 102

Trap Return 103

TRET instruction 103

SKP1 instruction 53, 8 6

SKPRnz instruction 55, 8 7

SKPRz instruction 88

SKPS instruction 57, 8 9

ST instruction 90

Unconditional Trap 102

WRCTL instruction 104

Write Control Register 104

Writing to Memory (or Peripherals) 9

Status Preservation

ISTATUS Register 20

Store 16-Bit Data To Memory

(Static Half-Word-Offset Address) 92

Store 16-bit Data To Memory, Computed

Half-Word Pointer Address 91

Store 16-bit Data To Memory,

Stack-Addressing Mode 97

Store 32-bit Data To Memory 90

Store 32-bit Data To Memory

(Pointer Addressing Mode) 95

Store 32-bit Data To Memory

(Stack Addressing Mode) 96

Store 8-bit Data To Memory

(Stack-Addressing Mode) 98

Store 8-bit Data To Memory

(Static Byte-Offset Address) 94

Store 8-bit Data To Memory, Computed

Byte-Pointer Address 93

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Notes:

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