FUJITSU SEMICONDUCTOR
CM71-10113-1E
CONTROLLER MANUAL
FR20
32-Bit Micro Controller
MB91191/MB91192 Series
Hardware Manual
Download from Www.Somanuals.com. All Manuals Search And Download.
FR20
32-Bit Micro Controller
MB91191/MB91192 Series
Hardware Manual
FUJITSU LIMITED
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
PREFACE
■ Purpose of This Document and Intended Reader
The MB91191/MB91192 are developed as one of the "32-bit single-chip microcontroller FR20 series"
around the new RISC architecture CPU as its cores, and the specifications for these products are optimized
for structures on which high-performance CPU processing power is required.
The functions and operations of the MB91191/MB91192 are described in this document specifically for
engineers who actually develop products using the MB91191 and MB91192. Please read through this
manual. For more information on various instructions, refer to "Instruction Manual".
Trademarks
■ Trademarks
FR is the abbreviation of FUJITSU RISC controller, which is a product of Fujitsu LIMITED.
Embedded Algorithm TM is a registered trademark of Advanced Micro Devices, Inc.
Other system and product names used in this manual are trademarks of the related companies and
organizations.
i
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Organization of This Document
This manual contains the following 21 chapters and an appendix.
ii
Download from Www.Somanuals.com. All Manuals Search And Download.
iii
Download from Www.Somanuals.com. All Manuals Search And Download.
•
•
The contents of this document are subject to change without notice. Customers are advised to consult with
FUJITSU sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented
solely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device;
FUJITSU does not warrant proper operation of the device with respect to use based on such information. When you
develop equipment incorporating the device based on such information, you must assume any responsibility arising
out of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising out of the
use of the information.
•
•
Any information in this document, including descriptions of function and schematic diagrams, shall not be
construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or
any other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's
intellectual property right or other right by using such information. FUJITSU assumes no liability for any
infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general
use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but
are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers
that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to
death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control
in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial
satellite). Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages
arising in connection with above-mentioned uses of the products.
•
•
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy,
fire protection, and prevention of over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or technologies subject to certain restrictions on export
under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will
be required for export of those products from Japan.
Copyright© 2004 FUJITSU LIMITED All rights reserved
iv
Download from Www.Somanuals.com. All Manuals Search And Download.
How to Read This Document.
■ Format of This Book
The explanation concerning the main term used in this book is shown as follows.
Term Meaning
I-bus It is a bus of the width of 16 bits for an internal instruction. Because the FR20 series has
adopted internal Harvard Architecture, the instruction and data are the independent
buses. The bus converter is connected with I-BUS.
D-bus
C-bus
It is a data bus of the width of the internal 32 bits. An internal resource is connected
with D-bus.
It is an internal multiplex bus. The C-bus connects to the I-bus and D-bus via the switch.
The external interface module is connected with C-BUS. The external data bus
multiplexes data and instructions.
R-bus
It is a data bus of the width of the internal 16 bits. R-bus is connected with D-bus
through the adaptor.
Various I/O, the clock generation block, and the interruption controller are connected
with R-bus.
The R-bus is 16-bit width, so the address and data are multiplexed. If the CPU accesses
these resources, it takes a number of cycles.
E-unit
It is an operation execution unit.
φ
It is a system clock. It is a clock output from the clock generation block to the each
internal resource connected with R-bus. The system clock at the highest speed shows
the same cycle as source oscillation but is divided into 1, 1/2, 1/4, and 1/8 (or 1/2, 1/4,
1/8, and 1/16) by PCK1 and PCK0 of the clock generator GCR register.
θ
It is a system clock. It is an operation clock of resource and CPU connected with buses
other than R-bus.
The system clock at the highest speed shows the same cycle as source oscillation but is
divided into 1, 1/2, 1/4, and 1/8 (or 1/2, 1/4, 1/8, and 1/16) by CCK1 and CCK0 of the
clock generator GCR register.
v
Download from Www.Somanuals.com. All Manuals Search And Download.
vi
Download from Www.Somanuals.com. All Manuals Search And Download.
CONTENTS
CHAPTER 1 Overview of MB91191/MB91192 Series ..................................................... 1
1.1
1.2
1.3
1.4
1.5
1.6
Feature of MB91191/MB91192 Series ............................................................................................... 2
Block Diagram of All MB91191/MB91192 Series ............................................................................... 4
Package Dimension ............................................................................................................................ 5
Pin Assignment ................................................................................................................................... 7
Pin Function Description ..................................................................................................................... 9
I/O Circuit Type ................................................................................................................................. 15
CHAPTER 2 Handling Devices ...................................................................................... 17
2.1
Precautions When Handling Devices ............................................................................................... 18
2.2
Others ............................................................................................................................................... 22
CHAPTER 3 CPU ............................................................................................................ 23
3.1
3.2
3.3
Memory Space .................................................................................................................................. 24
CPU Architecture .............................................................................................................................. 26
Dedicated Registers ......................................................................................................................... 29
Program Status Register (PS) ..................................................................................................... 32
General-purpose Register ................................................................................................................ 36
Data Construction ............................................................................................................................. 37
Word Alignment ................................................................................................................................ 38
Memory Map ..................................................................................................................................... 39
Overview of Instructions ................................................................................................................... 40
Branch Command with Delay Slot ............................................................................................... 42
Branch Command without Delay Slot .......................................................................................... 44
EIT (Exception, Interruption, and Trap) ............................................................................................ 45
Interrupt Level of EIT ................................................................................................................... 46
Interrupt Stack Operation ............................................................................................................ 47
EIT Vector Table .......................................................................................................................... 48
Multiple EIT Processing ............................................................................................................... 49
Operation of EIT .......................................................................................................................... 51
3.3.1
3.4
3.5
3.6
3.7
3.8
3.8.1
3.8.2
3.9
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
3.10 Reset Sequence ............................................................................................................................... 55
3.11 Memory Access Mode ...................................................................................................................... 56
3.12 Clock Generation Section (Low Power Consumption Mechanism) .................................................. 59
3.12.1 Reset Factor Register (RSRR) and Watchdog Timer Cycle Control Register (WTCR) ............... 61
3.12.2 Standby Control Register (STCR) ............................................................................................... 63
3.12.3 Timebase Timer Clear Register (CTBR) ..................................................................................... 64
3.12.4 Gear Control Register (GCR) ...................................................................................................... 65
3.12.5 Watchdog Reset Generation Delay Register (WPR) ................................................................... 67
3.12.6 Reset Factor Retention ................................................................................................................ 68
3.12.7 Stop Status .................................................................................................................................. 70
3.12.8 Sleep Status ................................................................................................................................ 73
3.12.9 State Transition in Standby Mode ............................................................................................... 76
3.12.10 Gear Function .............................................................................................................................. 77
3.12.11 Clock Series Diagram .................................................................................................................. 80
vii
Download from Www.Somanuals.com. All Manuals Search And Download.
3.12.12 Clock Series of Peripheral Resource ........................................................................................... 81
3.12.13 Watchdog Function ...................................................................................................................... 82
CHAPTER 4 External Bus Interface .............................................................................. 85
4.1
4.2
4.3
4.4
4.5
Overview of External Bus Interface .................................................................................................. 86
Block Diagram .................................................................................................................................. 87
Area of Bus Interface ........................................................................................................................ 88
Bus Interface ..................................................................................................................................... 89
Register of External bus Interface .................................................................................................... 90
Area Selection Register (ASR) and Area Mask Register (AMR) ................................................. 91
Area Mode Register 1 (AMD1) .................................................................................................... 94
Little Endian Register (LER) ........................................................................................................ 96
Bus Operation ................................................................................................................................... 97
Relationship between Data Bus Width and Control Signal .......................................................... 98
Bus Access of Big Endian ........................................................................................................... 99
Bus Access of Little Endian ....................................................................................................... 104
Comparison between Big Endian and Little Endian for External Access .................................. 108
Bus Timing ...................................................................................................................................... 112
Program Example of External Bus Operation ................................................................................. 113
4.5.1
4.5.2
4.5.3
4.6
4.6.1
4.6.2
4.6.3
4.6.4
4.7
4.8
CHAPTER 5 I/O Port ..................................................................................................... 117
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Overview of I/O Port ....................................................................................................................... 118
Port 0 .............................................................................................................................................. 119
Port 1 .............................................................................................................................................. 121
Port 2, 3 .......................................................................................................................................... 123
Port 5 .............................................................................................................................................. 125
Port 6, 7 .......................................................................................................................................... 127
Port 4, 8, 9 ...................................................................................................................................... 131
Port A, B ......................................................................................................................................... 135
Port C, D ......................................................................................................................................... 137
CHAPTER 6 FG Input ................................................................................................... 141
6.1
6.2
6.3
6.4
Overview of FG Input ...................................................................................................................... 142
Capstan Input ................................................................................................................................. 143
Drum Input ...................................................................................................................................... 148
Reel Input ....................................................................................................................................... 152
CHAPTER 7 FRC Capture ............................................................................................ 157
7.1
7.2
7.3
Overview of FRC Capture ............................................................................................................... 158
Register of FRC Capture ................................................................................................................ 160
Operation of FRC Capture .............................................................................................................. 165
CHAPTER 8 Programmable Pulse Generator (PPG0, 1) ........................................... 167
8.1
8.2
8.3
8.4
Overview of Programmable Pulse Generator (PPG0, 1) ................................................................ 168
Register of Programmable Pulse Generator (PPG0, 1) .................................................................. 171
PPG Data RAM ............................................................................................................................... 173
Configuration of Frame Data .......................................................................................................... 174
viii
Download from Www.Somanuals.com. All Manuals Search And Download.
8.5
Operation of PPG ........................................................................................................................... 175
CHAPTER 9 Real Timing Generator (RTG) ................................................................ 177
9.1
9.2
9.3
Overview of Real Timing Generator (RTG) .................................................................................... 178
Register of Real Timing Generator (RTG) ...................................................................................... 181
Operation of Real Timing Generator (RTG) .................................................................................... 183
CHAPTER 10 Timer ........................................................................................................ 185
10.1 Overview of Timer ........................................................................................................................... 186
10.2 Overview of 16-bit Timer (Timer 0 to 4) .......................................................................................... 188
10.3 Register of 16-bit Timer (Timer 0 to 4) ............................................................................................ 190
10.4 Operation of 16-bit Timer (Timer 0 to 4) ......................................................................................... 193
10.5 Overview of 8-/16-bit Timer/Counter ............................................................................................... 195
10.6 Register of 8-/16-bit Timer/Counter ................................................................................................ 197
10.7 Operation of 8-/16-bit Timer/Counter .............................................................................................. 201
CHAPTER 11 12-bit PWM ............................................................................................... 203
11.1 Overview of 12-bit PWM ................................................................................................................. 204
11.2 Register of 12-bit PWM ................................................................................................................... 206
11.3 Operation of 12-bit PWM ................................................................................................................ 208
CHAPTER 12 8-bit Pulse Width Counter ...................................................................... 211
12.1 Overview of 8-bit Pulse Width Counter ........................................................................................... 212
12.2 Register of 8-bit Pulse Width Counter ............................................................................................ 213
12.3 Operation of 8-bit Pulse Width Counter .......................................................................................... 215
CHAPTER 13 External Interrupt .................................................................................... 217
13.1 Overview of External Interrupt ........................................................................................................ 218
13.2 External Interrupt 1 (Key Input Circuit) ........................................................................................... 219
13.3 External Interrupt (INT0 to 2) .......................................................................................................... 221
CHAPTER 14 Delayed Interrupt Module ....................................................................... 225
14.1 Overview of Delayed Interrupt Module ........................................................................................... 226
14.2 Delayed Interrupt Control Register (DICR) ..................................................................................... 227
14.3 Operation of Delayed Interrupt Module ........................................................................................... 228
CHAPTER 15 Interrupt Controller ................................................................................. 229
15.1 Overview of Interrupt Controller ...................................................................................................... 230
15.2 Interrupt Control Register (ICRxx) .................................................................................................. 232
15.3 Operation of Interrupt Controller ..................................................................................................... 233
CHAPTER 16 10-bit A/D Converter ............................................................................... 237
16.1 Overview of 10-bit A/D Converter ................................................................................................... 238
16.2 Register of 10-bit A/D Converter ..................................................................................................... 239
16.3 Operation of 10-bit A/D Converter .................................................................................................. 245
16.4 State Transition of 10-bit A/D Converter ......................................................................................... 247
ix
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 17 Serial I/O .................................................................................................. 249
17.1 Overview of Serial I/O ..................................................................................................................... 250
17.2 Register of Serial I/O ...................................................................................................................... 252
17.3 Serial Data RAM ............................................................................................................................. 256
17.4 Operation of Serial I/O .................................................................................................................... 257
CHAPTER 18 10-bit General-purpose Prescaler ......................................................... 261
18.1 Overview of 10-bit General-purpose Prescaler ............................................................................... 262
18.2 Register of 10-bit General-purpose Prescaler ................................................................................ 263
18.3 Operation of 10-bit General-purpose Prescaler .............................................................................. 265
CHAPTER 19 Bit Search Module ................................................................................... 267
19.1 Overview of Bit Search Module ...................................................................................................... 268
19.2 Register of Bit Search Module ........................................................................................................ 269
19.3 Operation of Bit Search Module ...................................................................................................... 271
CHAPTER 20 Wait Controller ........................................................................................ 275
20.1 Outline of Wait Control Section ....................................................................................................... 276
20.2 Wait Control Register (WAITC) ....................................................................................................... 277
CHAPTER 21 Flash Memory .......................................................................................... 279
21.1 Overview of Flash Memory ............................................................................................................. 280
21.2 Flash Memory Status Register (FSTR) ........................................................................................... 284
21.3 Operation of Flash Memory ............................................................................................................ 286
21.4 Flash Memory Auto Algorithm (Embedded Algorithm TM) ............................................................. 288
21.5 Auto Algorithm Execute State ......................................................................................................... 292
APPENDIX ......................................................................................................................... 297
Appendix A I/O Map ................................................................................................................................ 298
Appendix B Interrupt vector ..................................................................................................................... 306
Appendix C Measurement accuracy of peripheral circuit ........................................................................ 308
Appendix D Restrictions for Using MB91191/MB91192 series ............................................................... 309
Appendix E Instruction List ...................................................................................................................... 310
E.1 Instruction list of FR series ............................................................................................................. 314
x
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 1 Overview of MB91191/MB91192 Series
1.1
Feature of MB91191/MB91192 Series
The MB91191/MB91192 series is a single-chip microcontroller with a built-in peripheral I/
O resource suited to software servo control of VTRs that require high-speed CPU
processing, featuring a 32-bit RISC-CPU (FR20 series) at its core.
■ Feature of MB91191/MB91192 Series
● CPU
•
•
•
•
32-bit RISC (FR20), load/store architecture, 5 stages pipeline
32-bit general-purpose register x 16
One instruction/one cycle, 16-bit fixed length instructions (basic instruction)
Commands for memory to memory transfer, bit processing, and barrel shift, etc.: Commands suitable for
embedded applications
•
Commands for function entry/exit, command for multi loading/storing of register contents: Commands
supporting high-level languages
•
•
•
Register interlock function: Simplification of assembler description
Branch instruction with a delay slot: Decrease of overhead for branch processing
Support at internal into/instruction level of multipliers
- 32-bit multiplication with sign: 5 cycles
- 16-bit multiplication with sign: 3 cycles
•
Interruption (save of PC and PS): 6 cycles and 16 priority levels
● Bus interface
•
•
•
•
•
•
•
16-bit address output, 8-/16-bit data I/O
Basic bus cycle: 2 clock cycle
Support interface to various memories
Multiplexed data/address input/output
Auto-wait cycle: 0 to 7 cycles can be set randomly per area.
Unused data and address pins can be used as I/O ports.
Support of little endian mode
● Bit search module
•
1-cycle search for the change bit position of the first 1/0 from the MSB within a word
● Serial I/O
•
•
Internal buffer RAM x 3ch (up to 128 bytes can be transferred automatically)
Independent mode of the transmission/reception buffer (up to 64 bytes can be transferred automatically)
● A/D converter (Successive Approximation Type)
•
•
•
•
•
10-bit x 16ch
Successive approximation conversion method (conversion time: 8.4 µs @20MHz)
Channel scan function
Hardware and software conversion start functions
Internal FIFO (Software conversion: 6 stages, Hardware conversion: 6 stages)
2
Download from Www.Somanuals.com. All Manuals Search And Download.
● Timer
•
•
•
16-bit x 4ch
16-bit timer/Counter x 1ch (with square wave output)
8-/16-bit timer/Counter x 1ch (with square wave output)
● FG Input
•
Incorporates capstan, drum, and reel input circuit
● Capture
•
•
Internal 24-bit free-run counter (Minimum resolution = 50ns@20 MHz)
Internal FIFO (Data: 21-bit x 8, Detection: 8-bit x 8)
● Programmable pules generator
•
•
•
Internal buffer RAM (PPG0: 256 bytes, PPG1: 64 bytes)
Output timing precision: 800 ns (@20 MHz)
Includes an A/DC hardware start function
● Real time timing generator
•
•
•
RTG: incorporates 3 circuits
Output timing precision: 400 ns/800 ns selectable
Timing output ports: 5 ports
● PWM
•
•
12-bit PWM x 6ch (rate, multi-type)
Base frequency = 78.1 KHz/39.0 KHz (@20MHz) selectable
● PWC
•
•
8-bit PWC x 1ch (with mask input)
Measurement precision: 400 ns (@20 MHz)
● General-purpose Prescaler
•
•
•
10-bit prescaler x 1ch (with square wave and pulse outputs)
Dedicated internal oscillator circuit
Includes load function driven by PPG output
● Interrupt control
•
•
External interrupt input: 3 inputs
Key input interrupt: 8 inputs
3
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 1 Overview of MB91191/MB91192 Series
1.2
Block Diagram of All MB91191/MB91192 Series
Figure 1.2-1 shows the block diagram of all MB91191/MB91192 series.
■ Block Diagram of All MB91191/MB91192 Series
Figure 1.2-1 Block diagram of all MB91191/MB91192 series
P47
MD0
MD1
MD2
RST
Mode Control
P46/PPG18
P45/PPG17
P44/PPG16
P43/PPG15
P42/PPG14
P41/PPG13
P40/PPG12
P
O
R
T
RAM 256Byte PPG0
P37/D31
4
FR20 CPU Core
P
O
R
T
2
/
3
RAM 64Byte PPG1
Bit Search
P87/PPG11
P86/PPG10
P85/PPG09
P84/PPG08
P83/PPG07
P82/PPG06
P81/PPG05
P80/PPG04
I-bu s
I-bu s
D-bus
P30/D24
P27/D23
P
O
R
T
8
/
D-bus
C-bus
MB91191R :RAM 6KB
MB91192 :RAM 8KB
MB91F191A:RAM 6KB
MB91F192 :RAM 8KB
P20/D16
P57/A15
P
O
R
T
P94/PPG03
P93/PPG02
P92/PPG01
P91/PPG00
P90/PO
9
RAM 2KB
D-bus
R-bus
5
P50/A08
P60/RD
P61/WR0
P62/WR1
P63/ALE
P64
P65
P66/T5O1
PD0 /SI2
MB91191R : ROM 254KB
MB91192 : ROM 384KB
MB91F191A: FLASH 254KB
MB91F192 : FLASH 384KB
P
O
R
T
RAM
128Byte
Serial
ch0
PD1 /SO2
PD2 /SCK2
PD3 /SI1 /INT 2
PD4 /SO1
PD5 /SCK1
PD6 /SCS0
PD7/SI0
P
O
R
T
RAM
128Byte
Serial
ch1
6
P67/T4O
C
/
D
RAM
128Byte
Serial
ch2
P
O
R
T
PC0/SO0
PC1/SCK0
External Bus CTL
P70/XOUT
PC2/PWMS112/SC
PC3 /PWM11/SCS2
PC4 /PWM10
PC5 /PWM02
PC6 /PWM01
PC7 /PWM00
7
12bit PWM00-02
12bit PWM10-12
P17/RTO4
P16/RTO3
P15/RTO2
P14/RTO1
P13/RTO0
16bit Timer0-3
8/16bit Timer
P
O
R
T
Interrapt
Controler
INT2-0 (from por t1,D )
External-Interrapt
16bit RTGO-2
P12/EC5/INT1
1
P11/EC4/INT0
16bit Timer4
8bit PWC
RTO4-0 (t o port 1)
P10/PMSK
P07/EXI 2/PMI
P06/EXI1
P05/EXI 0
PA7/AN-F/KEY7
PA6/AN-E/KEY6
PA5/AN-D/KEY5
PA4/AN-C/KEY4
PA3/AN-B /KEY3
PA2/AN-A /KEY2
PA1/AN-9 /KEY1
PA0/AN-8 /KEY0
P
O
R
T
P04/CFG
P03/DFG
PO2/DPG
CFG
DFG
P
External-Interrapt
(Key input)
O
24bit FRC
0
R
P01/RFG0
RFG0
RFG1
T
P00/RFG1
A
/
B
10bit A/DC
PB7/AN-7
PB6/AN-6
PB5/AN-5
PB4/AN-4
PB3/AN-3
PB2/AN-2
PB1/AN-1
PB0/AN-0
fifo
29bit x 8
XO
X1
OSC
OSC
C-unit
fifo
(soft)
fifo
(hard)
OSCI
OSCO
10bit Programale
Prescaler
4
Download from Www.Somanuals.com. All Manuals Search And Download.
1.3
Package Dimension
MB91191/MB91192 series is available in one type of packages.
■ Package Dimension (LQFP-120)
Figure 1.3-1 Package Dimension of FTP-120-M05
FPT-120P-M05
120-pin plastic LQFP
Lead pitch
0.40 mm
14.0 × 14.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.62 g
Code
(Reference)
(FPT-120P-M05)
P-LFQFP120-14×14-0.40
120-pin plastic LQFP
(FPT-120P-M05)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00 0.20(.630 .008)SQ
14.00 0.10(.551 .004)SQ
*
90
61
91
60
0.08(.003)
Details of "A" part
1.50 +–00..1200
(Mounting height)
.059 +–..000048
INDEX
120
31
"A"
0~8˚
1
30
LEAD No.
0.10 0.10
(.004 .004)
(Stand off)
0.16 0.03
(.006 .001)
0.145 0.055
(.006 .002)
0.50 0.20
(.020 .008)
M
0.40(.016)
0.07(.003)
0.60 0.15
(.024 .006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2003 FUJITSU LIMITED F120006S-c-4-5
5
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 1 Overview of MB91191/MB91192 Series
■ Package Dimension (FLGA-144)
Figure 1.3-2 Package dimension of FLGA-144
1.10 0.10
(0.80)
11.00 0.05 S Q.
(INDEXAREA)
144
0.35 0.05
0.65
M
0.08
0.45
0.755 0.050
3
0.45 0. 05
6
Download from Www.Somanuals.com. All Manuals Search And Download.
1.4
Pin Assignment
■ Pin Assignment (LQFP-120)
Figure 1.4-1 Pin assignment of LQFP-120
60
55
50
45
40
35
PA0/AN-8/KEY0
PB7/AN-7
PB6/AN-6
PB5/AN-5
PB4/AN-4
PB3/AN-3
PB2/AN-2
PB1/AN-1
PB0/AN-0
AVDD
P93/PPG02
P94/PPG03
P80/PPG04
P81/PPG05
P82/PPG06
P83/PPG07
P84/PPG08
P85/PPG09
P86/PPG10
P87/PPG11
P40/PPG12
P41/PPG13
P42/PPG14
P43/PPG15
P44/PPG16
P45/PPG17
P46/PPG18
P47
95
100
105
110
115
120
AVRH
AVSS
V
SS
Top View
P17/RTO4
P16/RTO3
P15/RTO2
P14/RTO1
P13/RTO0
P12/EC5/IN T1
P11/EC4/IN T0
P10/PMSK
P07/EXI 2/PMI
P06/EXI1
P57
A15
A14
A13
A12
A11
A10
A09
A08
P57
P56
P55
P54
P53
P52
P51
P50
P56
P55
P54
P53
P05/EXI0
P52
P04/CFG
P51
P03/DFG
P50
P02/DPG
VSS
P01/RFG0
P00/RFG1
P37
P36
P35
D31/A07 D31/A15
D30/A06 D30/A14
D29/A05 D29/A13
V
DD
8bit MPX mode
16bi t MPX mode
7
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 1 Overview of MB91191/MB91192 Series
■ Pin Assignment (FLGA-144)
Figure 1.4-2 Pin assignment of FLGA-144
59
56
53
50
47
44
41
38
35
32
P94 P82 P85 P40 P43
P46 P56 P53 P 50 P36
58
55
52
49
46
45
42
39
36
33
P80 P83 P86 P41 P44
P45 P57 P54 P51 P37
62
63
61
60
57
54
51
48
43
40
37
34
31
P91 P90 P92
P93 P81 P84
P87 P42
P47 P55 P52 VSS P35
65
66
64
30 28
P34 P32
29
P33
OSCO OSCI VDD
68
69
67
27
25
26
PC7 PC6
VSS
P31 VDD P30
22
24
P 27
23
P26
71
PC4 PC3
74 75
PC1 PC0 PC2
72
70
PC5
P25
73
2 1
19
20
P 24 P22 P23
Top View
77
76
78
1 8
16
17
PD6 PD7 PD5
P21 P60 P20
80
79
81
1 3
15
14
PD3 PD4 PD2
P 63 P61
P62
83
82
84
1 0
12
11
PD0 PD1 PA7
P66
P64
P65
86
85
87
7
9
8
PA5 PA6 PA4
RST
P67 P70
4
6
5
89
88
90
PA2 PA3 PA1
MD2 MD0 MD1
91
94
97
100
103 108 111 114 117
VSS P13 P10 P05 P02
120
VDD X0
1
3
VSS
2
X1
PA0 PB5 PB2 AVDD
93
96
99
102 105 106 109 112 115
118
P01
PB6 PB3 PB0 AVSS P16
P15 P12 P07 P04
92
95
98
01 104
107 110 113 116
P14 P11 P06 P03
119
P00
PB7 PB4 PB1 AVRH P17
Note:
For the MB91191 series, the FLGA-144 package does not supply. It only supplies for the MB91192
series.
8
Download from Www.Somanuals.com. All Manuals Search And Download.
1.5
Pin Function Description
Table 1.5-1 lists the pin function of MB91191/MB91192 series.
The numbers shown in the tables has nothing to do with package pin numbers. For pin
■ Pin Function List
Table 1.5-1 Pin Function List
Pin No. (LQFP)
Pin name
Form
Function
1
2
3
4
5
6
7
X0(I)
X1(O)
Vss
A
-
It is crystal oscillation pin.
It is Vss pin.
MD2
MD1
MD0
RST
It is operating mode specification pin.
It is CMOS schmitt input.
B
B
C
It is reset input pin. It is CMOS schmitt input.
P70/XOUT
This pin is shared with clock output (X0/2, PCK/2). It is
CMOS input.
8
9
P67/T4O
This pin is shared with timer 4 square wave output. It is
CMOS input.
P66/T5O1
This pin is shared with timer 5 square wave output. It is
CMOS input.
10
11
12
P65
It is general-purpose I/O port. It is CMOS input.
It is general-purpose I/O port. It is CMOS input.
P64
P63/ALE/ALE
This pin is shared with address strobe output.
It is CMOS input.
C
13
14
15
16
P62/P62/WR1
P61/WR0/WR0
P60/RD /RD
This pin is shared with write strobe output 1.
It is CMOS input.
This pin is shared with write strobe output 0.
It is CMOS input.
This pin is shared with read strobe output.
It is CMOS input.
9
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 1 Overview of MB91191/MB91192 Series
Table 1.5-1 Pin Function List
Pin No. (LQFP)
Pin name
Form
Function
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
P20/P20/D16:A00
P21/P21/D17:A01
P22/P22/D18:A02
P23/P23/D19:A03
P24/P24/D20:A04
P25/P25/D21:A05
P26/P26/D22:A06
P27/P27/D23:A07
VDD
It is general-purpose I/O port.
It is CMOS input.
C
-
It is power supply pin.
P30/D24:A00/D24:A08
P31/D25:A01/D25:A09
P32/D26:A02/D26:A10
P33/D27:A03/D27:A11
P34/D28:A04/D28:A12
P35/D29:A05/D29:A13
P36/D30:A06/D30:A14
P37/D31:A07/D31:A15
Vss
It is high-current I/O port and shared with external bus pins.
It is CMOS input.
C
-
It is Vss pin.
P50/A08/P50
P51/A09/P51
P52/A10/P52
P53/A11/P53
It is high-current I/O port and shared with external bus pins.
It is CMOS input.
C
P54/A12/P54
P55/A13/P55
P56/A14/P56
P57/A15/P57
10
Download from Www.Somanuals.com. All Manuals Search And Download.
Table 1.5-1 Pin Function List
Pin No. (LQFP)
Pin name
Form
Function
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
P47
It is general-purpose I/O port. It is CMOS input.
P46/PPG18
P45/PPG17
P44/PPG16
P43/PPG15
P42/PPG14
P41/PPG13
P40/PPG12
P87/PPG11
P86/PPG10
P85/PPG09
P84/PPG08
P83/PPG07
P82/PPG06
P81/PPG05
P80/PPG04
P94/PPG03
P93/PPG02
P92/PPG01
P91/PPG00
P90/PO
C
This pin is shared with PPG output.
It is CMOS input.
This pin is shared with PPG output.
It is CMOS input.
C
This pin is shared with PPG output.
It is CMOS input.
C
C
This pin is shared with PPG output.
It is CMOS input.
This pin is shared with general-purpose prescaler output. It is
CMOS input.
63
VDD
64
65
66
67
68
69
70
71
-
A
-
It is power supply pin.
OSCO (O)
OSCI/PCK(I)
Vss
It is crystal oscillation pin for dedicated general-purpose
prescaler.
It is Vss terminal.
PC7/PWM0
PC6/PWM1
PC5/PWM2
PC4/PWM3
This pin is shared with PWM output.
It is CMOS input.
C
11
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 1 Overview of MB91191/MB91192 Series
Table 1.5-1 Pin Function List
Pin No. (LQFP)
Pin name
Form
Function
PC3/PWM4/SCS2
This pin is shared with PWM output and serial 2 chip select. It
is CMOS schmitt input.
72
PC2/PWM5/SCS1
PC1/SCK0
PC0/SO0
This pin is shared with PWM output and serial 1 chip select. It
is CMOS schmitt input.
73
74
75
76
77
78
79
80
81
82
83
F
This pin is shared with serial 0 shift clock.
It is CMOS schmitt input.
This pin is shared with serial 0 serial output.
It is CMOS input.
C
F
PD7/SI0
This pin is shared with serial 0 serial input.
It is CMOS schmitt input.
PD6/SCS0
PD5/SCK1
PD4/SO1
This pin is shared with serial 0 chip select input.
It is CMOS schmitt input.
This pin is shared with serial 1 shift clock.
It is CMOS schmitt input.
This pin is shared with serial 1 serial input.
It is CMOS input.
C
F
PD3/SI1/INT2
PD2/SCK2
PD1/SO2
This pin is shared with serial 1 serial input and external
interrupt 2. It is CMOS schmitt input.
This pin is shared with serial 2 shift clock.
It is CMOS schmitt input.
This pin is shared with serial 2 serial output.
It is CMOS input.
C
F
PD0/SI2
This pin is shared with serial 2 serial input.
It is CMOS schmitt input.
84
85
86
87
88
89
90
91
PA7/AN-F/KEY7
PA6/AN-E/KEY6
PA5/AN-D/KEY5
PA4/AN-C/KEY4
PA3/AN-B/KEY3
PA2/AN-A/KEY2
PA1/AN-9/KEY1
PA0/AN-8/KEY0
This pin is shared with analog input and key input.
It is CMOS schmitt input.
E
12
Download from Www.Somanuals.com. All Manuals Search And Download.
Table 1.5-1 Pin Function List
Pin No. (LQFP)
Pin name
Form
Function
92
93
PB7/AN-7
PB6/AN-6
PB5/AN-5
PB4/AN-4
PB3/AN-3
PB2/AN-2
PB1/AN-1
PB0/AN-0
AV DD
94
95
This pin is shared with analog input.
It is CMOS schmitt input.
D
96
97
98
99
100
101
102
103
104
105
106
107
108
-
-
-
-
It is A/D converter power supply pin.
It is A/D converter reference power supply pin.
It is Vss pin of A/D converter.
It is Vss pin.
AVRH
AVss
Vss
P17/RTO4
P16/RTO3
P15/RTO2
P14/RTO1
P13/RTO0
P12/EC5/INT1
This pin is shared with RTG output.
It is CMOS input.
C
This pin is shared with timer 5 clock input and external
interrupt input. It is CMOS schmitt input.
109
110
111
P11/EC4/INT0
P10/PMSK
This pin is shared with timer 4 clock input and external
interrupt input. It is CMOS schmitt input.
F
This pin is shared with PWC mask input.
It is CMOS schmitt input.
13
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 1 Overview of MB91191/MB91192 Series
Table 1.5-1 Pin Function List
Pin No. (LQFP)
Pin name
Form
Function
P07/EXI2/PMI
This pin is shared with external capture input and PWC input.
It is CMOS schmitt input.
112
113
114
P06/EXI1
P05/EXI0
P04/CFG
This pin is shared with external capture input.
It is CMOS schmitt input.
This pin is shared with capstan FG input.
It is CMOS schmitt input.
115
116
117
F
P03/DFG
P02/DPG
This pin is shared with drum FG input.
It is CMOS schmitt input.
This pin is shared with drum pulse input.
It is CMOS schmitt input.
118
119
120
P01/RFG0
P00/RFG1
VDD
This pin is shared with reel FG input.
It is CMOS schmitt input.
-
It is power supply pin.
14
Download from Www.Somanuals.com. All Manuals Search And Download.
1.6
I/O Circuit Type
Table 1.6-1 shows the I/O circuit type.
■ I/O Circuit Type
Table 1.6-1 I/O circuit types
Classifi-
Circuit Type
cation
Remark
•
•
Oscillation return resistance about
1MΩ
X0,OSCI
Clock input
A
Standby control
X1,OSCO
CMOS schmitt input
B
Input
•
•
CMOS level output
Output data
DC test
CMOS input without standby
control
DC test
C
Direction CTL
Input
Standby control = 1 fix
15
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 1 Overview of MB91191/MB91192 Series
Table 1.6-1 I/O circuit types
Classifi-
Circuit Type
cation
Remark
•
•
•
CMOS level output
CMOS input with input control
Analog input
Output data
DC test
DC test
Direction CTL
D
Analog input
CH selection
Digital input
Input control
•
•
CMOS level output
Output data
DC test
CMOS schmitt input with input
control
•
Analog input
DC test
Direction CTL
E
Analog input
CH selection
Digital input
Input control
•
•
CMOS level output
Output data
DC test
CMOS schmitt input without
standby control
DC test
F
Direction CTL
Input
Standby control = 1 fix
16
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 2 Handling Devices
2.1
Precautions When Handling Devices
The semiconductor device breaks down at a certain probability. Moreover, the failure of
the semiconductor device is greatly controlled by the condition (circuit condition and
environmental condition, etc.) used.
To have the high use, the semiconductor device is explained about reliability about the
matter which should be noted and considered as follows.
■ Precautions when Designing
Here, the matter which should be noted when an electronic equipment is designed with a semiconductor
device is described.
● Observance of absolute maximum rating
When an excessive stress (voltage, current, and temperature, etc.) adds, the semiconductor device has the
possibility to destroy. The value that this threshold was provided is an absolute maximum rating. Therefore,
care must be taken not to exceed the rating even for one item.
● Observance of recommended operation condition
The recommended operation condition is a condition to guarantee normal movement of the semiconductor
device. All standard values for electric features are assured within this condition range. Always use under
the recommended operation condition. When this condition is exceeded and used, the adverse effect is
occasionally caused for reliability.
Use by the item, the condition, and the logical combination not described to this material is not guaranteed.
Please consult with the section in charge of sales of our company about use by conditions other than being
described for the idea beforehand.
● Processing and protection of terminal
In the semiconductor device, there are a power supply and various input/output terminals. The following
attention is necessary for these.
•
Prevention of over-voltage/over-current
Deterioration is caused in the device when the voltage/current which exceeds the maximum rating is
applied to each terminal, and when it is remarkable, it becomes destruction. Please prevent such an over-
voltage/over-current occurring when you design the equipment.
•
Protection of output terminal
If the output terminal is short circuited with the power terminal or other output terminal, or when large
capacity load is connected, a large electrical current may result. If this condition is prolonged, the device
will be damaged, so this kind of connection should not be made.
•
Processing of unused input terminal
If the input terminal with very high impedance is used while opened, the operation might become unstable.
Ensure connections to the power terminal and ground terminal have the appropriate resistance.
18
Download from Www.Somanuals.com. All Manuals Search And Download.
● Latch up
The semiconductor device is composed by the formation of the region of the P-type and the N-type on the
substrate. Internal parasitism PN junction (thyristor structure) might keep doing on-line when the voltage of
an external abnormal voltage is added, and the heavy-current which exceeds hundreds of mA flow to the
power supply terminal. This is called a latch up. The reliability of the device is not only damaged when this
phenomenon occurs but also there is dreading the arrival heat generation, smoking, and the ignition to
destruction. Please note the following points to prevent this.
•
There must not be what the voltage more than the maximum rating adds the terminal. Please note
abnormal noise and surge etc.
•
An abnormal current must not flow in consideration of the power supply turning on sequence.
● Restriction of safety etc. and observance of standard
All over the world, various restrictions and standards of safety and the EMI, etc. have been installed. Please
suit these restriction and standard when the customer designs the equipment.
● Fail safe design
The semiconductor device breaks down at a certain probability. The customer safely designs such as the
device redundancy, fire spreading prevention, exceeding current prevention, and prevention of malfunction
not to occur the injury accident, fire accident, and social damage consequently when the semiconductor
device is broken.
● Attention concerning usage
The our company semiconductor device is intended to be used for a standard usage (associated equipment
for office appliances such as computers/OA and industries/communications/the measurements and
personal/home equipment etc.). The customer concerns the usage of threatening the life by the breakdown
and malfunction, dreading the damage to the human body, or the special application which the extreme
high reliability is requested (fro aviation/space, atomic control, device for relayed the bottom of the sea,
running control, the medical device to keep the life, etc.), be sure to consult with the sales division of our
company. When you use without the consultation and acknowledge that the responsibility cannot be
assumed about the occurring damage etc.
■ Precautions when Mounting Package
In the package, there are a lead insertion type and a surface mounting type. In both cases, quality assurance
for heat resistance at the soldering stage only applies to the mounting under conditions recommended by us.
Please inquire the section in charge of sales of our company about details of the mounting condition.
● Lead insertion type
There are two ways to mount the lead insertion type package onto the printing board-the first is to directly
solder it onto the printing board, and the second is to mount it on the printing board using the socket.
When soldering it directly to the printing board, the flow soldering method (wave soldering method)
whereby the solder is melted after inserting the lead through the hole in the printing board is generally used.
In this case, heat stress in excess of the usual maximum rating preservation temperature is added to the lead
part at the soldering stage. Please mount under the mounting recommendation condition of our company.
When the mounting method using the socket is used, if surface processing of the socket contact point and
surface processing of the IC lead are different, contact failure may be generated after a prolonged period.
Therefore, checking the surface processing of the socket contact and surface processing of the IC lead is
recommended before mounting.
19
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 2 Handling Devices
● Surface mounting type
The lead used in the surface mounting type package is thinner than that for the insertion type, so its shape is
easily changed. In line with the increased number of pins in the package, the lead pitch is also narrow, and
opening defects due to the lead change and short circuits due to the solder bridge can easily be caused, so
an appropriate mounting technique is required. We recommend the solder re-flow method, and implement
rank classification of the mounting conditions per product. Please mount according to the rank
classification of the our company recommendation.
● About keeping the semiconductor device
The plastic package is made of resin, so moisture is absorbed if left in a natural environment. When the
heat when mounting on the moisture absorption package joins, the decrease and the package crack of the
wet-proofing by the interfacial flaking off generation might be generated. Please note the following points.
•
•
•
The be dewy of moisture happens to the product in the place with a rapid temperature change. Store it in
a place with minimum temperature fluctuations that avoid such an environment.
The depository of the product recommends the use of a dry box. Please keep under the relative humidity
to 70% RH and the temperature to 5 to 30 °C.
Silica-gel is used as a dry medicine in our company with a damp-proof and high as packing material of
the semiconductor device if necessary an aluminum laminate bag. Put the semiconductor device in the
laminated aluminum bag and close it tightly for storage.
•
Please avoid the place where a lot of places and dust where the corrosively gas is generated.
● About the baking
The moisture absorption package can be dehumidified by executing the baking (heating dryness). Please
execute the baking by the condition which our company recommends.
● Static electricity
Please note the following points so that the semiconductor device may cause destruction by static electricity
easily.
•
Please adjust the relative humidity of the working environment to 40% to 70% RH. Please examine the
use of TEL device (apparatus for generating ion) etc. if necessary.
•
•
Earth the conveyer, soldering tank and iron, and peripheral incidental equipment to be used.
In order to prevent electrocution of human body, try to earth through a ring or armlet with high
resistance (about 1MΩ), wear conductive clothing and shoes, and place a conductive mat on the floor to
minimize static build-up.
•
•
Please execute the earth or the electrification prevention to the treatment device and meters.
Avoid using materials that are easily charged, such as polystyrene foam, to store the assembled board.
20
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Precautions
The reliability of the semiconductor is affected by the peripheral temperature as mentioned before, and
other environmental conditions. Please note the following points.
● Humidity
As for environment long-term use under the high humidity environment, something wrong with the leak
character might occur in not only the device but also printed wiring board, etc. Please consider the damp-
proof processing such as giving when the high humidity is assumed.
● Static electricity discharge
The semiconductor device might cause the malfunction by being generate the electrical discharge in Kon
when electrified thing exists in high voltage near the device. For this case, please treat the prevention of
electrification or the prevention of the electrical discharge.
● Corrosively gas, dust, and oil
If the device is used within a corrosive gas environment or where dust and oil, etc. may become attached,
the effect may be detrimental due to chemical reactions. Protective measures should be considered when
used under such an environment.
● Radiation and cosmic ray
A general device does not assume the environment exposed to the radiation and the cosmic ray in the
design. Therefore, use this to shield.
● Smoking and ignition
The device of the resin molding type is not nonflammability. Do not use the device near any ignitable
substance. In the event of smoke or fire may be generated toxic gases.
Additionally, please consult the section in charge of sales of our company about use under a special
environment for the idea.
21
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 2 Handling Devices
2.2
Others
The others are explained
■ External Reset Input
When "L" level is input to the RST pin, to ensure the inside achieves reset status, "L" level input to the
RST pin is required for at least five machine cycles.
■ Note on Using External Clock
When using the external clock, drive the X0. Figure 2.2-1 shows the example of using an external clock.
Figure 2.2-1 Example of using an external clock
X0
X1
OPEN
MB91191/MB91192 series
*:Be sure to make X1 pin open.
■ Power Supply Pin
If there are multiple VDD and VSS pins, from the point of view of device design, pins to be of the same
potential are connected the inside of the device to prevent such malfunctioning as latch up. To reduce
unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and
observe the standard for total output current, be sure to connect the VDD and VSS pins to the power supply
and ground externally.
Also try to ensure that connection to the VDD, Vss on this device is at the lowest impedance possible from
the power supply source. In addition, We will recommend the ceramic capacitor of about 0.1 µF to be
connected as bypass capacitor between VDD and VSS near this device.
■ Crystal Oscillation Circuit
The noise near X0 and the X1 terminal becomes original of the malfunction of this device. The printing
board should be designed so that the X0, X1, crystal oscillator (or ceramic oscillator), and bypass capacitor
to the ground are arranged as close as possible.
Printing board artwork around the X0 and X1 terminals to the ground is strongly recommended, as steady
operation can be expected.
■ Handling NC Pin
Use the Non Connect (N.C.) terminal while open.
■ Mode (MD0 to MD2) Pin
Please tie directly to VDD or VSS and use these terminals.
In order to prevent erroneous entry to test mode due to noise, the pattern length between each mode
terminal and VDD or VSS on the printing board should be as short as possible, and they should be connected
at low impedance.
■ At Power On
When the power is turned on, the RST pin must be started from "L" level status, and changed to "H" level
after at least five cycles of the internal operation clock have passed, after the power source reaches the VDD
level.
22
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
3.1
Memory Space
32
The logical address space of the FR20 series is 4 Gbytes (2 addresses), and the CPU
performs linear access.
■ Direct Addressing Area
The under-mentioned area of the address space is used for I/O. This area is called the "direct addressing
area" and operand addresses can be specified directly within the command. A direct area is different as
follows depending on the size of the accessed data.
•
Byte data access:0-0FFH
Half word data access:0-1FFH
Word data access:0-3FFH
•
•
■ Memory Map
Figure 3.1-1 shows the memory map of the MB91191/MB91192.
24
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure 3.1-1 MB91191/MB91192 Memory Map
00000000H
00000000H
I/O area
I/O area
000001FFH
00000200H
000001FFH
00000200H
PPG0 Data RAM area 256byte
SIO0 Data RAM area 128byte
PPG1 Data RAM area 64byte
I/O area
PPG0 Data RAM area 256byte
SIO0 Data RAM area 128byte
PPG1 Data RAM area 64byte
I/O area
000002FFH
00000300H
000002FFH
00000300H
Direct
Access
Area
0000037FH
00000380H
0000037FH
00000380H
000003BFH
000003C0H
000003BFH
000003C0H
000003FFH
00000400H
000003FFH
00000400H
I/O area
I/O area
000007FFH
00000800H
000007FFH
00000800H
Access interdiction
Access interdiction
00000FFFH
00001000H
00000FFFH
00001000H
SIO1 Data RAM area 128byte
SIO2 Data RAM area 128byte
SIO1 Data RAM area 128byte
SIO2 Data RAM area 128byte
Access interdiction
0000107FH
00001080H
0000107FH
00001080H
000010FFH
00001100H
000010FFH
00001100H
Access interdiction
0000DFFFH
0000E000H
0000E7FFH
0000E800H
Internal RAM area 8Kbyte
Internal RAM area 6Kbyte
0000FFFFH
00010000H
0000FFFFH
00010000H
Access interdiction
0007FFFFH
00080000H
Internal RAM area 2Kbyte
000807FFH
00080800H
Access interdiction
Access interdiction
0009FFFFH
000A0000H
000BFFFFH
000C0000H
Internal RAM area 2Kbyte
Internal ROM area (384kByte)
000C07FFH
000C0800H
Internal ROM area (254kByte)
Reset vector
000FFFFBH
000FFFFCH
000FFFFBH
000FFFFCH
1KB
Initial vector area
Reset vector
00100000H
00100000H
External expansion area
External expansion area
FFFFFFFFH
FFFFFFFFH
MB91191R
MB91192
Note:
Under single-chip mode, access to the external extension area is impossible.
Select internal ROM external bus mode using the mode register to access the external extension
area.
25
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
3.2
CPU Architecture
The FR20 CPU is a high performance core that adopts highly functional commands for
the embedded application as well as RISC architecture.
■ Feature of CPU Architecture
● Adoption of RISC architecture
•
Basic instruction: one instruction one cycle
● 32 bit architecture
•
General-purpose register 32 bits × 16
● Linear memory space of 4 GB
● Installing of multipliers
•
•
32 bits x multiplication 32 bits: 5 cycles
16 bits x multiplication 16 bits: 3 cycles
● Reinforcement of interruption processing function
•
•
•
High-speed response speed (6 cycles)
Support for multiple interrupts
Level mask function (16 levels)
● Reinforcement of instruction for I/O operation
•
•
Memory memory transfer operation
Bit processing instruction
● High code efficiency
•
16 bits in basic instruction word length
● Low power consumption
•
Sleep mode, stop mode
■ Construction of Internal Architecture
The FR20 CPU adopts the Harvard architecture structure whereby the command bus and data bus are
independent.
The on chip command cache is connected to the command bus (T-bus). A 32-bit <--> 16-bit bus converter
is connected to the data bus (D-bus), and performed interfaces between the CPU and peripheral resources.
A Harvard <--> Princeton bus converter is connected to both the I-bus and D-bus, performed and interfaces
between the CPU and bus controller.
26
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure 3.2-1 shows the construction of internal architecture.
Figure 3.2-1 Construction of Internal architecture
FR20 CPU
D-BUS
I-BUS
Instruction
Cache
Harvard
Princeton
32bit
Bus converter
16bit
Bus converter
R-bus
C-bus
Bus controller
Resource
● CPU
The FR20's 32-bit RISC architecture is compactly implemented on the CPU. A five-level command
pipeline method is adopted to execute one command per cycle. The pipeline is composed of the following
stages.
•
•
•
•
•
Instruction fetch (IF): The instruction address is output, and the instruction is fetched.
Instruction decode (ID): The decode does the fetched instruction. The register is read.
Execution (EX): The operation is executed.
Memory access (MA): Loading into the memory or the store is accessed.
Write-back (WB): Writes the operation results (or loaded memory data) to the register.
Figure 3.2-2 shows the instruction pipeline.
Figure 3.2-2 Instruction pipeline
CLK
Instruction 1
Instruction 2
Instruction 3
Instruction 4
WB
MA
EX
ID
WB
MA
EX
ID
WB
MA
EX
ID
WB
MA
EX
Instruction 5
Instruction 6
IF
WB
MA
IF
WB
The instruction is never in any order executed. Accordingly, if command A enters the pipeline before
command B, command A always reaches write backstage before command B.
As a rule, the instruction is executed at the speed of one instruction per cycle. However, a number of cycles
27
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
are required to execute commands for the load/store command to which memory wait is attached, branch
commands that do not have delay slots, and multi-cycle commands. Also, when the supplied instruction is
slow, the execution speed of the instruction decrease.
● 32-bit ↔ 16-bit bus converter
Interfaces between the D-BUS that quickly accesses at 32-bit width and the R-BUS that accesses at 16-bit
width, and realizes data access from the CPU to built-in peripheral circuit.
When 32-bit width access is performed from the CPU, this bus converter accesses the R-BUS by
converting it to 16-bit width access twice. Some of built-in peripheral circuits have access width-related
restrictions.
● Harvard ↔ Princeton bus converter
Coordinates between the CPU command access and data access, and realizes smooth interface with the
external bus.
In CPU, the instruction bus and the data bus are the independent Harvard architecture structures. On the
other hand, the bus controller that controls the external bus has a Princeton architectural structure with a
single bus. This bus converter ranks the priority order for command access and data access of the CPU, and
controls access to the bus controller. This operation always optimizes the external bus access ranking.
It also has a two-word write buffer to eliminate CPU bus waiting time and a one-word pre-fetch buffer to
fetch commands.
28
Download from Www.Somanuals.com. All Manuals Search And Download.
3.3
Dedicated Registers
Use the dedicated registers for specified purposes. Program counter (PC), program
status (PS), table base register (TBR), return pointer (RP), system stack pointer (SSP),
user stack pointer (USP), and multiplication/division results registers (MDH/MDL) are
prepared.
■ Dedicated Registers List
Figure 3.3-1 shows the dedicated register list.
Figure 3.3-1 Dedicated registers list
Program counter (PC)
ILM
SCR CCR Program status (PS)
Table base register (TBR)
Return pointer (RP)
System stack pointer (SSP)
User stack pointer (USP)
(MDH)
(MDL)
Multiplication and division result register
■ Program Counter (PC)
Function of program counter (PC: Program Counter) is described.
The program counter (PC) consists of 32-bit.
Figure 3.3-2 shows the bit configuration of the program counter (PC).
Figure 3.3-2 Program counter (PC)
bit
31
0 Initial value
XXXXXXXXH
The address of the executed instruction is shown with the program counter.
If the PC is updated when an instruction is executed, Bit 0 is set to "0". Bit 0 may be "1" only when an odd
address is specified as the branch destination address.
Even in that case, bit 0 is invalid, and the command must be placed in the address of the multiple of two.
The initial value by reset is irregular.
■ Program Status Register (PS)
This register retains the program status, and is separated into three parts, namely, ILM, SCR, and CCR.
The undefined bits are all reserved bits. When the register is read, "0" is always read. Writing is invalid.
29
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
■ Table Base Register (TBR)
Function of table base register (TBR: Table Base Register) is described.
The table base register (TBR) consists of 32-bit.
Figure 3.3-3 shows the bit configuration of the table base register (TBR).
Figure 3.3-3 Table base register (TBR)
bit
31
0 Initial value
000FFC00H
The table base register retains the starting address of the vector table used for EIT processing.
The initial value by reset is 000FFC00H.
■ Return Pointer (RP)
Function of Return Pointer (RP: Return Pointer) is described.
The return pointer (RP) consists of 32-bit.
Figure 3.3-4 shows the bit configuration of the return pointer (RP).
Figure 3.3-4 Return pointer (RP)
bit
31
0 Initial value
XXXXXXXXH
The address which returns from the sub routine is maintained at the return pointer.
The value of PC is forwarded to this RP at CALL instruction execution time.
The content of RP is forwarded to PC at RET instruction execution time.
The initial value by reset is irregular.
■ System Stack Pointer (SSP)
Function of system stack pointer (SSP: System Stack Pointer) is described.
The system stack pointer (SSP) consists of 32-bit.
Figure 3.3-5 shows the bit configuration of the system stack pointer (SSP).
Figure 3.3-5 System stack pointer (SSP)
bit
31
0 Initial value
00000000H
SSP is the system stack pointer.
When the S flag is "0", the SSP functions as R15. The SSP can be specified explicitly.
Also used as the stack pointer specifying the stack that saves the PS and PC when EIT occurs.
The initial value by reset is 00000000H.
30
Download from Www.Somanuals.com. All Manuals Search And Download.
■ User Stack Pointer (USP)
Function of user stack pointer (USP: User Stack Pointer) is described.
The user stack pointer (USP) consists of 32-bit.
Figure 3.3-6 shows the bit configuration of the user stack pointer (USP).
Figure 3.3-6 User stack pointer (USP)
bit
31
0 Initial value
XXXXXXXXH
USP is the user stack pointer.
When the S flag is "1", the USP functions as R15. The USP can be specified explicitly. The initial value by
reset is irregular.
The USP cannot be used for the RETI instruction.
■ Multiplication and Division Result Register (MDH/MDL)
Function of multiplication and division result register (MDH/MDL: Multiply & Divide register) is
described.
The multiplication and division result register (MDH/MDL) consists of 32-bit.
Figure 3.3-7 shows the bit configuration of the multiplication and division result register (MDH/MDL).
Figure 3.3-7 Multiplication and division result storage register (MDH/MDL)
Initial value
bit
31
0
XXXXXXXXH
MDH
MDL
XXXXXXXXH
MDH and MDL are the multiplication and division register. Each register is 32-bit long.
The initial value by reset is irregular.
● Functions when multiplication is executed
In the case of 32-bit x 32-bit multiplication, the 64-bit long operation results are stored in the
multiplication/division results register in the following format.
•
•
MDH: Higher 32-bit
MDL: Lower 32-bit
In the case of 16-bit x 16-bit multiplication, the results are stored in the multiplication/division results
register as follows.
•
•
MDH: Indeterminate
MDL: 32-bit
● Functions when division is executed
When beginning to calculate, the dividend is stored in MDL.
When division is calculated using the DIV0S/DIV0U, DIV1, DIV2, DIV3, or DIV4S commands, the
results are stored in the MDL and MDH as follows.
•
•
MDH: surplus
MDL: commerce
31
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
3.3.1
Program Status Register (PS)
The register retains the program status, and is separated into three parts, ILM, SCR, and
CCR.
A bit undefined in figure is reservation all bit. When the register is read, "0" is always
read. Writing is invalid.
■ Program Status Register (PS)
Figure 3.3-8 shows the configuration of the program status register (PS).
Figure 3.3-8 Program status register (PS)
bit
31
20
16
10 8 7
0
SCR
ILM
CCR
● Condition code register (CCR)
Figure 3.3-9 shows the configuration of the condition code register (CCR).
Figure 3.3-9 Condition code register (CCR)
7
6
5
4
I
3
2
Z
1
0
Initial value
--00XXXXH
bit
S
N
V
C
The function of each bit is explained as follow.
[bit5] S: Stack flag
This bit specifies the stack pointer to be used as R15.
Value
Function
The system stack pointer (SSP) is used as R15. When the EIT occurs, this bit is
automatically set to "0". (Note that a value saved on the stack is the value before it is
cleared)
0
1
The user stack pointer (USP) is used as R15.
This bit is cleared to "0" by a reset.
Select the SSP when the RETI instruction is executed.
32
Download from Www.Somanuals.com. All Manuals Search And Download.
[bit4] I: Interrupt enable flag
Permission and the interdiction of the user interruption demand are controlled.
Value
Function
User interruption interdiction.
0
When the INT instruction is executed, this bit is cleared to "0".
(Note that a value saved on the stack is the value before it is cleared)
User interruption permission.
Mask processing of user interrupt requests is controlled by the value retained by ILM.
1
This bit is cleared to "0" by a reset.
[bit3] N: Negative flag
This bit indicates the code when the operation results are defined as integers expressed as complements
of 2.
Value
Function
0
1
It is indicated that operation result was a positive value.
It is indicated that operation result was a negative value.
Initial state by reset is irregular.
[bit2] Z: Zero flag
This bit indicates whether or not the operation result is 0.
Value
Function
0
1
It is indicated that operation result was the values other than 0.
It is shown that operation result was 0.
Initial state by reset is irregular.
[bit1] V: Overflow flag
This bit is considered to be the integer expressing the operand used for operations as complements of 2,
and indicates whether or not an overflow was generated as the result of such operation.
Value
Function
0
1
It is indicated that no overflow has occurred as a result of the operation.
It is indicated that an overflow has occurred as a result of the operation.
Initial state by reset is irregular.
33
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
[bit0] C: carrying flag
This bit indicates whether or not carry or borrow was generated from the highest bit through the
operation.
Value
Function
0
1
It is indicated that no carry or borrow has occurred.
It is indicated that a carry or borrow has occurred.
Initial state by reset is irregular.
● System Condition code Register (SCR)
Figure 3.3-10 shows the configuration of the system condition code register (SCR: System Condition Code
Register).
Figure 3.3-10 System condition code register (SCR)
10
9
8
T
Initial value
XX0H
bit
D1
D0
Each bit function of the system condition code register (SCR) is explained as follows.
[bit10, 9] D1, D0: Flag for step division
The middle data of step division execution time is maintained. Do not change while executing the
division processing.
Restart of the step division is guaranteed by saving/returning the PS register value when other processes
are carried out during the step division. Initial state by reset is irregular.
When the DIV0S instruction is executed, the divided and the divisor are referenced and set.
When the DIV0U instruction is executed, the bits clear forcibly.
[bit8] T: step trace trap flag
It is a flag which specifies whether to make the step trace trap effective.
Value
Function
0
Step trace trap invalidity
Step trace trap effective
1
In this case, all NMIs for user and user interrupts will be interrupt disabled.
This bit is initialized to "0" by a reset.
The emulator uses the function of the step trace trap. When the emulator is used, it cannot be used in user
program.
34
Download from Www.Somanuals.com. All Manuals Search And Download.
● Interrupt level mask register (ILM)
Figure 3.3-11 shows the configuration of the interrupt level mask register (ILM).
Figure 3.3-11 Interrupt level register (ILM)
bit
20
19
18
17
16
Initial value
01111H
ILM4 ILM3 ILM2 ILM1 ILM0
The interrupt level mask register (ILM) retains the interrupt level mask value, and values retained by this
ILM are used as the level mask.
Interrupt requests are received only when the supported interrupt level is higher than the level indicated by
this ILM out of the interrupt requests to be input to the CPU.
As for the level value, 0(00000B) is the strongest, and 31(11111B) is weakest.
There is a limitation in the value which can be set from the program.
If the original value is between 16 to 31, the new value must be between 16 to 31. When the command
setting 0 to 15 is executed, the value (specified value + 16) is transferred.
If the original value is between 0 to 15, an arbitrary value between 0 to 31 can be set.
This register is initialized to 15 (01111B) by a reset.
35
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
3.4
General-purpose Register
Register R0 to R15 is a general-purpose register. These registers are used as the
pointer for memory access and accumulator for various operations.
■ General-purpose Register
Figure 3.4-1 shows the configuration of the general-purpose register.
Figure 3.4-1 Configuration of general-purpose register
32bit
[Initial value]
R0
R1
XXXX XXXXH
XXXX XXXXH
XXXX XXXXH
XXXX XXXXH
XXXX XXXXH
0000 0000H
R12
R13
R14
R15
AC
FP
SP
Register R0-R15 is a general register. These registers are used as the pointer for memory access and
accumulator for various operations. The following of the 16 registers are expected to have special uses, so
some commands are emphasized.
•
•
•
R13: Virtual accumulator (AC)
R14: Frame pointer (FP)
R15: Stack pointers (SP)
R0 to R14 of the initial value by reset is irregular. R15 becomes 00000000H (value of SSP).
36
Download from Www.Somanuals.com. All Manuals Search And Download.
3.5
Data Construction
The data allocation of the FR20 series uses as follow.
• Bit ordering: Little endian
• Byte ordering: Big endian
■ Bit Ordering
In the FR20 series, the little endian has been adopted as a bit ordering.
Figure 3.5-1 shows the data allocation of the bit ordering.
Figure 3.5-1 Data allocation of bit ordering
bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB
LSB
■ Byte Ordering
Big endian is adopted as the byte ordering for the FR family.
Figure 3.5-2 shows the data allocation of the byte ordering.
Figure 3.5-2 Data allocation of byte ordering
MSB
Memory bitNo.31
LSB
0
23
15
7
10101010 11001100 11111111 00010001
bit
7
0
n address 10101010
(n+1) address 11001100
(n+2) address 11111111
(n+3) address 00010001
37
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
3.6
Word Alignment
As commands and data are accessed per byte, addresses to be allocated differ
depending on the command length and data width.
■ Program Access
It is necessary to arrange the program of the FR20 series in the address of the multiple of two. Bit 0 of the
program counter (PC) is set to "0" when updating the PC in line with execution of the command. It may be
"1" only when an odd address is specified as the branch destination address. Even in that case, bit 0 is
invalid, and the command must be placed in the address of the multiple of two.
There is no odd number address exception.
■ Data Access
In the FR20 series, when data is accessed, forced alignment is applied to the address depending on its width
as follows.
•
•
•
Word Access:
Half-word access: An address must be a multiple of 2. (The lowest bit is forcibly "0".)
Byte Access:
An address must be a multiple of 4. (The lowest 2-bit is forcibly "00".)
-
When word or half-word data is accessed, "0" is forcibly set to some bits, which are the calculation results
of the effective address. For example, in the @(R13,Ri) addressing mode, the register before addition is
used for calculations as it is (even though the lowest bit is 1), and the lower bits of the addition results will
be masked. A register before calculation is not masked.
(example) LD @(R13,R2),R0
R13 00002222H
R2 00000003H
Addition result 00002225H
Lower 2-bit forcibly mask
Address pin 00002224H
38
Download from Www.Somanuals.com. All Manuals Search And Download.
3.7
Memory Map
The memory map for the FR20 series is shown.
■ Memory Map
The address space of the memory is 32 bit linear.
Figure 3.7-1 shows the memory map.
Figure 3.7-1 Memory map
0000 0000
0000 0100
H
H
Byte data
Direct addressing region
Halfword data
Word data
0000 0200
0000 0400
H
H
000F FC00
000F FFFF
H
H
Vector table
initial region
FFFF FFFF
H
● Direct addressing
The under-mentioned region of the address space is a region for I/O. In this area, the operand address can
be specified directly within the command through direct addressing.
The size of the address area which an address can be directly specified is different in each data length.
•
•
•
Byte data: (8 bits): 0 to 0FFH
Half-word data: (16 bits): 0 to 1FFH
Word data: (32 bits): 0 to 3FFH
● Vector table initial region
The region of 000FFC00H - 000FFFFFH is EITT vector table initial area.
The vector table used for EIT processing can be allocated to an arbitrary address by rewriting the TBR, but
it is allocated to this address on initialization through reset.
39
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
3.8
Overview of Instructions
The FR20 series supports logical operation and bit operations that are optimized for
embedded application, and direct addressing commands as well as a general RISC
command system. The set list shows the appendix. As each command is 16 bits length
(some commands are 32 or 48 bits), memory usage is more efficient.
■ Overview of Instructions
The instruction set can be divided into the following function groups.
•
•
•
•
•
•
Arithmetic operation
Load and store
Divergence
Logical operation and bit operation
Direct addressing
Others
● Arithmetic operation
It has standard arithmetic operation commands (addition, subtraction, comparison) and shift commands
(logic shift, arithmetic operation shift). Operations with carry that are used for multi-word length operations
and operations that do not change the flag value which are convenient for address calculations are enabled
for addition and subtraction.
Furthermore, it has 32-bit x 32-bit and 16-bit x 16-bit multiplication commands, and the 32-bit/32-bit step
division commands.
Also equipped with an immediate transfer command that sets immediate values to the register, and an inter-
register transfer command.
The arithmetic operation command executes all operations using a general-purpose register and
multiplication/division register within the CPU.
● Load and store
Load and store are the commands that read and write to external memories. They are also used to read and
write the peripheral circuits (I/O) within the chip.
Load and store have three types of access length, namely byte, half-word, and word. In addition to normal
indirect register memory addressing, memory addressing is also possible for certain commands such as
indirect displacement registers and indirect increment/decrement registers.
● Branch
In the FR20 series, whether the operations are with or without delay slots can be specified for the branch
command.
It is an instruction of the branch, the call, the interruption, and the return. There are two types of branch
command. One type has a delay slot and the other does not. They can be optimized to suit the purpose.
40
Download from Www.Somanuals.com. All Manuals Search And Download.
details of the branch commands.
● Logical operation and bit operation
Logic operation instruction can perform AND, OR, and EOR logic operations between general-purpose
registers, or between a general-purpose register and the memory (or I/O). Moreover, the bit operation
instruction can operate the content of the memory (And, I/O) directly. The register of the memory
addressing is generally indirect.
● Direct addressing
Direct addressing commands are used to access between I/O and general-purpose registers, or between I/O
and the memory. The I/O address can be accessed quickly and efficiently by direct specification within the
command instead of indirect register. Indirect memory addressing to the register with register increment/
decrement is also enabled for some commands.
● Others
This command executes flag set up within the PS register, stack operation, code/zero expansion, etc. Also
equipped with high-level language supported function entry/exit, and register multi-load/store commands.
41
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
3.8.1
Branch Command with Delay Slot
The operation with the delay slot branches prior to execute the command at the branch
destination after executing the command located immediately after the branch
command.
■ Branch Command with Delay Slot
The following commands execute the branch command with delay slot.
JMP:D @Ri
BRA:D label9
BC:D label9
BV:D label9
BLE:D label9
CALL:Dlabel12
BNO:D label9
BNC:D label9
BNV:D label9
BGT:D label9
CALL:D @Ri
BEQ:D label9
RET:D
BNE:D label9
BP:D label9
BGE:D label9
BHI:D label9
BN:D
label9
BLT:D label9
BLS:D label9
■ Operation of Branch Command with Delay Slot
Operations with delay slots branch out after executing the command placed just after the branch command
(called a "delay slot") prior to execute the branch destination command.
As the delay slot command is executed before the branch operation, the apparent execution speed is 1
cycle. The NOP command must be placed as an alternative if an effective command cannot be inserted in
the delay slot.
[example]
; Row of instruction
ADD
R1, R2
;
BRA:D LABEL
; Branch instructions
MOV
...
R2, R3
; Delay slot ......Executed before branch
LABEL:STR 3 and @R4 ; The divergence ahead
The command placed in the delay slot is executed whether the branch condition for the condition branch
command will be realized or not.
For delay branch commands, the execution order of the partial command seems to be reversed, but this
applies only to PC update operations, and other operations (i.e. update and refer to register) are absolutely
executed in the described order.
Concrete examples are shown below.
● The Ri to be referred to the JMP:D@Ri/CALL:D@Ri command will not be effected even if the command
within the delay slot updates the Ri.
[example]
LDI:32 #Label, R0
JMP:D @R0
; Branches out to Label
LDI:8
...
#0,
R0
; No effects on the branch destination address
42
Download from Www.Somanuals.com. All Manuals Search And Download.
● The RP to be referred by the RET:D command will not be effected even if the command within the delay
slot updates the RP.
[example]
RET:D
MOV
...
; Branch to address defined beforehand in RP
R8, RP; No effect on the return operation
● The flag referred by the Bcc: Drel command is not effected by the delay slot command either.
[example]
ADD
BC:D
#1,
R0 ; Flag change
Overflow ; Branch to execution result of above instruction
ANDCCR #0
...
; Do not refer to this flag update in the above-mentioned branch instruction.
● When RP is referred to for the command within the delay slot under the CALL:D command, the updated
contents will be read by the CALL:D command.
[example]
CALL:D Label
MOV RP and R0
..
; Update RP and branch
; RP of an execution above-mentioned CALL:D result is forwarded.
■ Limitations for Branch Command with Delay
● Instruction that can be placed in the delay slot
Only commands that satisfy the following conditions can be executed within the delay slot.
1 cycle instruction.
No branch instruction.
Instruction which does not influence operation even when order changes
•
•
•
The "1-cycle command" is a command in which "1", "a", "b", "c", or "d" is described in the cycle number
column within the commands list.
● Step trace trap
Step trace trap will not be generated between execution of the branch command with delay slot and the
delay slot.
● Interrupt/NMI
No interrupt/NUM is received between execution of the branch command with delay slot and the delay slot.
● Undefined instruction exception
If an undefined command exists with the delay slot, undefined command exception will not be generated.
At this time, undefined instruction operates as NOP instruction.
43
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
3.8.2
Branch Command without Delay Slot
Branch Command without Delay Slot is described.
■ Branch Command without Delay Slot
The following commands execute the branch command without delay slot.
JMP @Ri
CALL label12 CALL @Ri
RET
BEQ label9 BNE label9
BN label9 BP label9
BLT label9 BGE label9
BLS label9 BHI label9
BRA label9
BC label9
BV label9
BLE label9
BNO label9
BNC label9
BNV label9
BGT label9
■ Operation of Branch Command without Delay Slot
Operation of ones without delay slots are absolutely executed in command rank order. The instruction
provided immediately before the branch instruction is not executed after branching.
[example]
; Row of instruction
ADD
BRA
MOV
...
R1, R2
LABEL
R2, R3
;
; Branch instruction (delay slot none)
; Not executed
LABEL:STR 3 and @R4
; The branch ahead
Execution cycle number for branch commands without delay slots will be 2 cycles branched, or 1 cycle
non-branched. As the appropriate command cannot be inserted into the delay slot, the command code
efficiency is better than the branch command with the delay slot described the NOP instruction. A balance
between execution speed and code efficiency can be struck by selecting either the operation with the delay
slot when effective commands can be set in the delay slot, or the operation without the delay slot when
effective commands cannot be set.
44
Download from Www.Somanuals.com. All Manuals Search And Download.
3.9
EIT (Exception, Interruption, and Trap)
EIT indicates suspension of program execution due to generation of an event while
executing the current and other programs. It is a general term for Exception, Interrupt,
and Trap.
■ EIT (Exception, Interruption, and Trap)
The exception is an incident which occurs in relation to the context under execution. Execution restarts
from the instruction that caused the exception.
The interruption is an incident which occurs without any relation to the context under execution. The event
factor is hardware.
The trap is an incident which occurs in relation to the context under execution. There is something directed
by the program like the system call. Execution restarts from the instruction following the one that caused
the trap.
■ EIT Factor
The EIT factors are as follow.
•
•
•
•
•
•
•
•
•
•
Reset
User interruption (internal resource and external interruption)
NMI
Delayed interrupt
Undefined instruction exception
Trap instruction (INT)
Trap instruction (INTE)
Step trace trap
Coprocessor absent trap
Coprocessor error trap
■ Return from EIT
Use the RETI instruction to return from EIT.
45
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
3.9.1
Interrupt Level of EIT
Interrupt levels is controlled by 0 to 31 by five bits.
■ Interrupt level of EIT
The allocation of each level is as follow.
Table 3.9-1 Interrupt level
Interrupt level
Factor
Remark
2 decimal
number
10 decimal
number
00000
00001
00010
00011
00100
0
1
2
3
4
(System reservation)
When the original value of the ILM is 16 to 31,
values within this range cannot be set as the ILM
by the program.
INTE instruction, step trace trap
00101 to
01110
5 to 14
15
(System reservation)
01111
NMI (for user)
10000 to
11110
When ILM is set, it is a user interruption
interdiction.
16 to 30
31
Interrupt
-
11111
When ICR is set, it is an interruption interdiction.
It is a level of 16 to 31 that the operation is possible.
Undefined command exception, coprocessor absence trap, coprocessor error trap and INT instruction are
unaffected by the interrupt level. Moreover, ILM is occasionally changed.
■ Level Mask to Interruption/NMI
When NMI and interrupt requests are generated, the interrupt level held by the interrupt factor is compared
with the level mask value held by the ILM. And, when the following condition consists, the mask is done,
and the demand is not accepted.
Interrupt level held by factor ≥ Level mask value
46
Download from Www.Somanuals.com. All Manuals Search And Download.
3.9.2
Interrupt Stack Operation
The value of PC and PS is saved and revived in the area shown by SSP. After an
interrupt, PC is stored in the address indicated by the SSP, and PS is stored in the
address (SSP+4).
■ Interrupt Stack
Figure 3.9-1 shows the example of the interrupt stack.
Figure 3.9-1 Interrupt stack operation diagram
[Example]
SSP
[Befor interrupt]
[After interrupt]
80000000
SSP
7FFFFFF8
H
H
Memory
80000000
80000000
H
H
7FFFFFFC
7FFFFFFC
7FFFFFF8
H
PS
PC
H
H
7FFFFFF8
H
47
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
3.9.3
EIT Vector Table
From address which TBR shows to vector region for EIT region of 1KB
■ EIT Vector Table
Each vector is 4 bytes, and the relationship between the vector number and vector address is expressed
below.
vctadr = TBR + vctofs = TBR +(03FCH - 4 × vct)
vctadr: Vector Address
vctofs: Vector offset
vct:
Vector number
The lowest 2-bit of the addition result are always handled as "00".
The area of 000FFC00H to 000FFFFFH is an initial area of the vector table by reset. A special function is
allocated partially of the vector. The vector table on the architecture is shown in Table 3.9-2 .
Table 3.9-2 Vector table
Vector number
Vector Address
Description
0
1
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
000FFFFCH
TBR + 03F8H
TBR + 03F4H
TBR + 03F0H
TBR + 03ECH
TBR + 03E8H
TBR + 03E4H
TBR + 03E0H
TBR + 03DCH
TBR + 03D8H
TBR + 03D4H
TBR + 03D0H
TBR + 03CCH
TBR + 03C8H
TBR + 03C4H
TBR + 03C0H
TBR + 03BCH
Reset
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
2
3
4
5
6
7
Coprocessor absent trap
Coprocessor error trap
INTE Instruction
8
9
10
11
12
13
14
15
16
Instruction break exception
Operand break trap
Step trace trap
System reservation
Undefined instruction exception
NMI (for user)
Mask enable interrupt factor #0 (IRQ0)
17 to
63
11H to
3FH
TBR + 03B8H to
TBR + 0300H
Mask enable interrupt factor #1 (IRQ2) to
Mask enable interrupt factor #47 (IRQ47)
64
65
40H
41H
TBR + 02FCH
TBR + 02F8H
System reservation (used for REALOS)
System reservation (used for REALOS)
66 to
255
42H to
FFH
TBR + 02F4H to
TBR + 0000H
INT Instruction
48
Download from Www.Somanuals.com. All Manuals Search And Download.
3.9.4
Multiple EIT Processing
When a number of EIT factors are generated simultaneously, one of the EIT factors is
selected and accepted in the CPU, and after the EIT sequence is executed, such EIT
factors are detected again. This operation is repeated as necessary.
When EIT factors are detected, if there are no more EIT factors that can be accepted, the
handler command for the last EIT factor accepted will be executed.
Therefore, the handler order for each factor when a number of EIT factors are generated
simultaneously is determined by the following two elements.
• Priority level of EIT factor acceptance
• How to mask the other factor at receiving
■ Priority Level of EIT Factor Acceptance
Priority for acceptance of the EIT factors indicates the order when selecting the factors executing the EIT
sequence that saves PS and PC, updates the PC (on demand) and performs mask processing of other
factors. The handler of the factor previously accepted is not always executed first.
Table 3.9-3 shows the priority level of the EIT factor acceptance.
Table 3.9-3 Priority level of EIT factor acceptance and masking other factor
Priority order
of acceptance
Factor
Masking of other factor
1
2
Reset
Undefined instruction exception
INT Instruction
Other factors are abandoned.
Cancellation
I Flag=0
3
Coprocessor absent trap
Coprocessor error trap
User Interrupt
None
4
5
7
8
ILM = Level of accepted factor
NMI (for user)
ILM=15
ILM=4
ILM=4
INTE Instruction
Step trace trap
A tinge of mask processing onto other factors after accepting the EIT factors is added, and each handling
procedure for the generated EIT factors are also mentioned in Table 3.9-4 .
49
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
Table 3.9-4 Execution sequence of EIT handler
Execution sequence of handler
Factor
Reset *1
1
2
3
Undefined instruction exception
Step trace trap *2
INTE instruction *2
NMI (for user)
4
5
6
7
INT instruction
User interrupt
Coprocessor absent trap
Coprocessor error trap
8
*1: Other factors are abandoned.
*2: If the INTE instruction is executed in steps, only EIT of the step trace trap generates
INTE instruction.
The factor by INTE is disregarded.
Figure 3.9-2 shows the example of multiple EIT processing.
Figure 3.9-2 Example of multiple EIT processing
[Example]
Main routine
NMI handler
INT instruction handler
Priority level
First execute
(High) NMI generation
(Low) INT instruction execute
Next execute
50
Download from Www.Somanuals.com. All Manuals Search And Download.
3.9.5
Operation of EIT
This section explains operation of EIT
■ Operation of EIT
As per the following explanation, the "PC" at the transfer origin indicates the address of the command that
detected each EIT factor.
The "following command address" means that the command that detected EIT is as follows.
•
•
•
If LDI is 32: PC+6
If LDI: 20 and COPOP, COPLD, COPST and used: PC+4
Other instructions: PC+2
● Operation of user interruption/NMI
When a user interrupt or interrupt request of NMI for user is generated, the request is accepted or not is
determined in the following order.
● Right or wrong judgment of interruption demand acceptance
1. The interruption levels of requests that are generated simultaneously are compared, and the one with the
highest level (the smallest numeric value) will be selected. In terms of the levels used for comparisons,
the value retained by the supported ICR is used for mask enable interrupts, and a predetermined constant
is used for NMI.
2. When a number of interrupt requests of the same level are generated, the one with the youngest interrupt
number is selected.
3. Compares the interrupt level with the selected interrupt request with the level mask value determined by
ILM.
When the interrupt level is greater than or equal to the level mask value, the interrupt request is masked
and not accepted.
To (4) at interrupt levels < level mask value.
4. When the selected interruption request is an interruption that can be masked, the interruption request
will be masked and will not be accepted when the I flag is 0. If the I flag is 1, go to 5). When the
selected interrupt request is NMI, go to 5) regardless of the I-flag value.
5. When the above condition occurs, the interrupt request is accepted at the command-processing gap.
When an EIT request is detected, if the user interrupt/NMI request is accepted, the CPU operates as follows
using the interrupt number supporting the accepted interrupt request. ( ) in the [operation] shows the
address which the register indicates.
51
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
[Operation]
1. SSP-4
2. PS
→ SSP
→ (SSP)
→ SSP
3. SSP-4
4. Address of the following instruction→(SSP)
5. Interrupt level of accepted request→ ILM
6. "0"
→ S Flag
7. (TBR + Vector offset of accepted interrupt request)→ PC
Prior to execute the front command of the handler after the interrupt sequence ends, a new EIT is detected.
At this stage, if an acceptable EIT is generated, the CPU transits to the EIT processing sequence.
■ Operation of INT Instruction
The INT #u8 instruction operates as follow.
Branch to the interrupt handler for the vector indicated by u8.
[Operation]
1. SSP-4
2. PS
→ SSP
→ (SSP)
→ SSP
3. SSP-4
4. PC+2
5. "0"
→ (SSP)
→ I Flag
→ S Flag
6. "0"
7. (TBR+3FCH - 4 × u8)→ PC
■ Operation of INT Instruction
The INT instruction operates as follow.
Branch to the interrupt handler for the vector indicated by vector number #9.
[Operation]
1. SSP-4
2. PS
→ SSP
→ (SSP)
→ SSP
3. SSP-4
4. PC+2
→ (SSP)
5. "00100" → ILM
6. "0" → S Flag
7. (TBR+3D8H)→ PC
Do not use the INTE instruction during the INTE instruction and step trace trap processing routine.
Moreover, EIT is not generated while executing the step by INTE.
52
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Operation of Step Trace Trap
When the T flag of the SCR within the PS is set, and the step trace function is set to Enabled, a trap is
generated per command execution and creates a break.
● Condition of step trace trap detection
•
•
•
T Flag = 1
There is no delayed branch instruction.
While executing other than the INTE command and step trace trap processing routine.
When the above condition occurs, breaks at the command operation gap.
[Operation]
1. SSP-4
2. PS
→ SSP
→ (SSP)
→ SSP
3. SSP-4
4. Address of the following instruction→(SSP)
5. "00100" → ILM
6. "0"
→ S Flag
7. (TBR+3CCH)→ PC
When step trace traps are enabled by setting the T flag, NMI for users and user interruption are disabled.
Moreover, EIT by the INTE instruction is not generated.
■ Operation of Undefined Instruction Exception
If an undefined instruction is detected when decoding the command, an undefined instruction exception is
generated.
● Detection condition of undefined instruction exception
•
•
1) It is detected that it is undefined instruction at the decoding of the instruction.
2) Placed outside the delay slot (not immediately after the delay branch command).
When the above condition occurs, an undefined instruction exception is generated, and a break is created.
[Operation]
1. SSP-4
2. PS
→ SSP
→ (SSP)
→ SSP
3. SSP-4
4. PC
→ (SSP)
→ S Flag
5. "0"
6. (TBR+3C4H)→ PC
The address of the actual command that detected the undefined instruction exception is saved as the PC.
53
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
■ Coprocessor Absent Trap
When a coprocessor command using an unmounted coprocessor is executed, a coprocessor absence trap is
generated.
[Operation]
1. SSP-4
2. PS
→ SSP
→ (SSP)
→ SSP
3. SSP-4
4. Address of the following instruction→(SSP)
5. "0" → S Flag
6. (TBR+3E0H)→ PC
■ Coprocessor Error Trap
If an error occurs while using a coprocessor, when the coprocessor command that operates the coprocessor
is executed next, a coprocessor error trap is generated.
[Operation]
1. SSP-4
2. PS
→ SSP
→ (SSP)
→ SSP
3. SSP-4
4. Address of the following instruction→(SSP)
5. "0" → S Flag
6. (TBR+3DCH)→ PC
Note:
This product does not contain the coprocessor.
■ Operation of RETI Instruction
The RETI instruction is an instruction which returns from EIT processing routine.
[Operation]
1. (R15)
→ PC
→ R15
→ PS
2. R15+4
3. (R15)
4. R15+4
→ R15
Care must be taken that the stack pointer to be referred to returning of the PS and PC is selected in
accordance with the S flag contents. When the command that operates R15 (stack pointer) within the
interrupt handler is executed, set the S flag to "1" and use the USP as R15. The S flag must be returned to
"0" before the RETI command.
■ Delay Slot
In the delay slot of the branch instruction, there is a restriction concerning EIT.
54
Download from Www.Somanuals.com. All Manuals Search And Download.
3.10
Reset Sequence
This section explains the reset when the CPU is the operation state.
■ Reset Factor
The reset factor is as follow.
•
•
•
•
Input from external reset pin
Software reset by the SRST bit operation of the standby control register (STCR)
Count up of watchdog timer
Power on reset
■ Initialization by Reset
The reset factor is generated, the CPU is initialized.
● Releasing from the external reset pin or software reset
•
•
The pin is set to the predetermined state.
Each resource in the device is put in the reset state. The control register is initialized to the
predetermined value.
•
The lowest gear is selected for the clock.
■ Reset Sequence
When a reset factor is released, the CPU executes the following reset sequence.
•
(000FFFFCH) → PC
Note:
After reset, operation mode needs to be set by the mode register setting.
55
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
3.11
Memory Access Mode
In the FR20 series, operation mode is controlled by the mode pins (MD2, 1, 0) and the
mode register (MODR).
■ Operation Mode
In the operation mode, there are a bus mode and an access mode.
Bus mode
Single-chip
Access mode
Internal ROM
32 - bit bus widht
16 - bit bus widht
8 - bit bus widht
external bus
External ROM
external bus
● Bus Mode
The bus mode controls the internal ROM operation and external access function operation, and is specified
by the mode set up pins (MD2, 1, 0) and M1, M0 bit of the mode register (MODR).
● Access mode
The access mode controls the external data bus width, and is specified by the mode set up pins (MD2, 1, 0)
and BW1, 0 bits within the AMD0/AMD1/AMD32/AMD4 and AMD5 (address mode registers).
■ Mode Pin
Operation is specified by three pins (MD2, 1, 0) as per Table 3.11-1 .
Table 3.11-1 Mode Pin and setting mode
Mode pin
Reset vector
External data bus
width
Mode name
Remark
access area
External
External
External
Internal
-
MD2 MD1 MD0
External
vector mode 0
0
0
0
0
1
0
0
1
1
-
0
1
0
1
-
8 bits
16 bit
External
vector mode 1
The use of the terminal
is prohibited.
External
vector mode 2
32 bit
Internalvector
mode
(Mode register)
-
Single-chip mode
The use of the terminal
is prohibited.
-
56
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Mode Data
Data that the CPU writes at "0000 07FFH" after reset is called mode data.
The mode register (MODR) exists in "0000 07FFH" and after setting to this register, operation is carried out
under the set up mode of this register. The mode register can be written only once after resetting.
The set value of this register is valid immediately after writing.
■ Mode Register (MODR)
Figure 3.11-1 Mode register (MODR)
7
M1
W
6
M0
W
5
4
3
2
1
0
bit
Address: 0000 07FFH
Access
Initial value
XXXXXXXXB
Bus mode setting mode
[bit7, 6]: M1, M0
There are bus mode setting bits. These bits specify the bus mode after writing the mode register.
Table 3.11-2 Bus mode setting bits and function
M1
M0
Function
Remark
0
0
1
1
0
1
0
1
Single-chip mode
Internal ROM external bus mode
External ROM external bus mode
-
Setting disabled
Setting disabled
Note:
Only set the "00" and "01" for this product above.
[bit5-0]:-
System Reserved bit
Always write "0" to these bits.
57
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
■ Notes on Writing to Mode Register (MODR)
Before writing to the MODR, AMD0 to AMD5 must be set, and the bus width in each chip select (CS) area
must be decided.
The MODR has no bits used to set the bus width.
For the bus width, before writing to the MODR, the mode pins (MD2 to 0) are valid. After MODR writing,
set values (BW1, BW0) of the AMD0 to AMD5 will be valid.
For example, the external reset vector performs in the normal area 0 (the area in which the CSOX is active),
but in this case, the bus width is decided by the MD2 to MD0 pins. The bus width at that time is set to 32 or
16 bits by MD2 to MD0, and if MODR is written while nothing is set to AMD0, the initial value of the
AMD0 bus width has been set to 8 bits. So bus operation will be performed by transiting the area 0 to 8 bit
bus mode after writing the MODR, and erroneous operation will result.
AMD0 to AMD5 must be set before writing the MODR to prevent this kind of problem.
Figure 3.11-2 Notes on writing to mode register (MODR)
MODR programming
RST (Reset)
Bus width setting: MD2, 1, 0
BW1, 0 of MD0-5A
58
Download from Www.Somanuals.com. All Manuals Search And Download.
3.12
Clock Generation Section (Low Power Consumption
Mechanism)
The clock generation section is the modules that have the following functions:
• CPU clock generation (including the gear function)
• Peripheral clock generation (including the gear function)
• Reset generation and cause retention
• Standby function
• Built-in PLL (duty correction circuit)
■ Register in Clock Generation Section
Figure 3.12-1 Register in Clock Generation Section
7
1
bit
RSRR/WTCR
STCR
Reset Factor/Watchdog Cycle Control Register
Standby Control Register
Address: 000480H
000481H
000482H
000483H
000484H
000485H
Reserve
CTBR
(Access interdiction)
Timebase Timer Clear Register
Gear Control Register
GCR
WPR
Watchdog Reset Generation Dalayed Register
59
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
■ Block Diagram of Clock Generation Section
Figure 3.12-2 Block Diagram of Clock Generation Section
[Gear control unit]
R-bus
GCR register
CPU gear
Peripheral
gear
Osci-
llation
circuit
X0
X1
1/ 2
PLL
CPU clock
Internal bus clock
Internal
clock
generation
circuit
M
P
X
Internal peripheral clock
[Stop/Sleep control unit]
STCR regiter
Internal interrupt
Internal reset
STOP state
State
SLEEP state
CPU hold request
transition
control
circuit
Reset
generation
F/F
Internal reset
[Reset factor circuit]
RSRR register
Power-on detection
RST pin
[Watchdog control unit]
WPR register
Count
clok
Watchdog F/F
CTBR register
Timebase timer
60
Download from Www.Somanuals.com. All Manuals Search And Download.
3.12.1
Reset Factor Register (RSRR) and Watchdog Timer Cycle
Control Register (WTCR)
The reset factor register (RSRR) retains reset types generated, and the watchdog timer
cycle control register (WTCR) specifies the cycle for the watchdog timer.
■ Reset Factor Register (RSRR) and Watchdog Timer Cycle Control Register (WTCR)
Figure 3.12-3 Reset factor register (RSRR) and watchdog timer cycle control register (WTCR)
Initial value after
Power ON
bit
7
6
5
4
3
2
1
0
Address: 000480H
PONR
WDOG ERST SRST
WT1
WT0
1XXX XXXXB
Access
R
R
R
R
W
W
[bit7]: PONR
When this bit is "1", it indicates that the previously generated reset was a power-on reset. When this bit
is "1", contents other than this bit of this register are invalid.
[bit6]: (Reserved)
It is reserved bit. The reading value is undefined.
[bit5]: WDOG
When this bit is "1", it indicates that the previously generated reset was a watchdog reset.
[bit4]: ERST
When this bit is "1", it indicates that the previously generated reset was caused by the external reset pin.
[bit3]: SRST
When this bit is "1", it indicates that the previously generated reset was caused by the software reset
request.
[bit2]: (Reserved)
It is reserved bit. The reading value is undefined.
[bit1, 0]: WT1, 0
These bits specify the cycle of the watchdog timer. The bits and the selected cycle have the following
relationship. These bits are initialized when the entire reset is generated.
61
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
Table 3.12-1 Watchdog timer cycle specified by WT1 and WT0
Timer from last 5AH write to WPR to
occurrence of watchdog resetting
Writing spacing to at least necessary for
control generation of watchdog reset WPR
WT1
WT0
φ × 2 15 (Initial value)
φ × 2 17
φ × 2 15 to φ × 2 16
φ × 2 17 to φ × 2 18
φ × 2 19 to φ × 2 20
φ × 2 21 to φ × 2 22
0
0
1
1
0
1
0
1
φ × 2 19
φ × 2 21
Note: φ is twice as large as X0 when GCR CHC is 1, and is one time as large as X0 when GCR CHC is 0.
62
Download from Www.Somanuals.com. All Manuals Search And Download.
3.12.2
Standby Control Register (STCR)
This register controls standby operations and specifies the oscillation stabilization wait
time.
■ Standby Control Register (STCR)
Figure 3.12-4 Standby control register (STCR)
bit
7
6
5
4
3
2
1
0
Initial value
000111--B
Address: 00000481H
STOP SLEEP
R/W R/W
SRST OSC1 OSC0
R/W R/W R/W
Access
[bit7]:STOP
When "1" is written to this bit, the status will be stop that stops the internal peripheral clock, the internal
CPU clock, and oscillation.
[bit6]:SLEP
When "1" is written to this bit, the status will be standby that stops the internal CPU clock. If "1" is
written to both the STOP bit and this bit, the STOP bit is handled as the priority, so the status will be
stop.
[bit5]:(Reserved)
[bit4]:SRST
When "0" is written to this bit, a software reset request is generated.
[bit3, 2]:OSC1, 0
These bits specify the oscillation stabilization wait time. These bits and selected cycle have the
following relationship. This bit is initialized by a power-on reset, and is unaffected by any other reset
factors.
Table 3.12-2 Oscillation stabilization wait time specified by OSC1 and OSC0
OSC1
OSC0
Oscillation Stabilization Wait Time
φ × 2 15
φ × 2 17
0
0
1
1
0
1
0
1
φ × 2 19
φ × 2 21 (Initial value)
Note: φ is twice as large as X0 when GCR CHC is 1, and is one time as large as X0 when GCR CHC is 0.
[bit1, 0]:(Reserved)
There are reserved bits. The reading value is undefined.
63
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
3.12.3
Timebase Timer Clear Register (CTBR)
This register initializes the timebase timer contents to 0.
■ Timebase Timer Clear Register (CTBR)
Figure 3.12-5 Timebase timer clear register (CTBR)
Initial value
bit
Address: 000483H
Access
7
6
5
4
3
2
1
0
D7
W
D6
W
D5
W
D4
W
D3
W
D2
W
D1
W
D0
W
XXXX XXXXB
[bit7 to 0]
Writing A5H, 5AH continuously to this register clears the timebase timer to 0 immediately after 5AH.
The reading value of this register is irregular. There is no restriction on the time interval between A5H
and 5AH writing.
Note:
Clearing the timebase timer using this register temporarily fluctuates oscillation stability wait interval,
watchdog cycle, and peripheral cycles that use the timebase.
64
Download from Www.Somanuals.com. All Manuals Search And Download.
3.12.4
Gear Control Register (GCR)
The gear control register controls the gear functions of the CPU and peripheral clocks.
■ Gear Control Register (GCR)
Figure 3.12-6 Gear Control Register (GCR)
7
6
5
4
3
2
1
0
bit
Address: 000484H
Access
Initial value
11--11-1B
CCK1 CCK0
PCK1
PCK0
CHC
R/W R/W
R/W
R/W
R/W
[bit7, 6]:CCK1, 0
These bits specify the CPU gear cycle. The bits and selected cycles have the following relationship.
These bits are initialized by a reset.
Table 3.12-3 CPU machine clock
CPU machine clock
(source oscillation: input frequency from X0)
CCK1 CCK0
CHC
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
Source oscillation × 1
Source oscillation × 1/2
Source oscillation × 1/4
Source oscillation × 1/8
Source oscillation × 1/2
Source oscillation × 1/2 × 1/2
Source oscillation × 1/2 × 1/4
Source oscillation × 1/2 × 1/8 (Initial value)
65
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
[bit3, 2]:PCK1, 0
These bits specify the peripheral gear cycle. The bits and the selected cycles have the following
relationship. These bits are initialized by a reset.
Table 3.12-4 Peripheral machine clock
Peripheral machine clock
(source oscillation: input frequency from X0)
PCK1
PCK0 CHC
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
Source oscillation × 1
Source oscillation × 1/2
Source oscillation × 1/4
Source oscillation × 1/8
Source oscillation × 1/2
Source oscillation × 1/2 × 1/2
Source oscillation × 1/2 × 1/4
Source oscillation × 1/2 × 1/8 (Initial value)
[bit0]:CHC
This bit selects whether 1/2 division cycle or PLL/DCC cycle of the oscillation circuit is used as the
basic clock. The setting "1" is the 1/2 division cycle and the setting "0" is the PLL/DCC cycle.
66
Download from Www.Somanuals.com. All Manuals Search And Download.
3.12.5
Watchdog Reset Generation Delay Register (WPR)
This register clears the flip-flop for the watchdog timer. Using this register postpones
generation of the watchdog reset.
■ Watchdog Reset Generation Delay Register (WPR)
Figure 3.12-7 Watchdog reset generation delay register (WPR)
Initial value
bit
Address: 000485H
Access
7
6
4
5
4
3
2
1
0
D7
D6
D5
W
D4
W
D3
W
D2
W
D1
D0
XXXX XXXXB
W
W
W
W
[bit7 to 0]
Writing A5H, 5AH continuously to this register clears the flip-flop for the watchdog timer to "0"
immediately after 5AH, and postpones generation of the watchdog reset.
The reading value of this register is irregular. There is no time limit between A5H and 5AH, but if
writing both data is not finished within the period as per the following table, a watchdog reset is
generated. However, clearing is automatically carried out under stop/sleep mode, so when these
conditions are generated, the watchdog reset is automatically postponed.
Table 3.12-5 Watchdog timer cycle specified by WT1 and WT2
Writing spacing to at least
necessary for control generation of
watchdog reset WPR
Time from 5AH final writing in WPR to
generation of watchdog reset
WT1
WT0
φ × 2 15
φ × 2 17
φ × 2 19
φ × 2 21
φ × 2 15 to φ × 2 16
φ × 2 17 to φ × 2 18
φ × 2 19 to φ × 2 20
φ × 2 21 to φ × 2 22
0
0
1
1
0
1
0
1
Note: φ is twice as large as X0 when GCR CHC is 1, and is one time as large as X0 when GCR CHC is 0.
67
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
3.12.6
Reset Factor Retention
The reset factor retention holds the factor of previous generation. All flag is cleared to
"0" by reading.
Once a factor flag is set, it is not cleared unless the factor is read.
■ Block Diagram of Reset Factor Retention Circuit
Figure 3.12-8 Reset factor circuit Block Diagram
Power-on
detection
PONR
PONR
watch-dog Timer
reset detect Circuit
WDOG
ERST
SRST
WDOG
ERST
SRST
RST pin
Reset input circuit
SRST
decoder
.o r.
■ Setting of Reset Factor Retention
No special settings are required to use the rest factor function. Commands for reading the reset factor
register and branching to the appropriate program shall be placed near the front of the program to be set in
the reset entry address.
[example]
RESET-ENTRY
LDI:32 #RSRR,R10
LDI:8 #10000000B,R2
LDUB @R10,R1
MOV R1,R10
AND R2,R10
BNE PONR-RESET
LSR #1,R2
; GET RSRR VALUE INTO R1
; R10 USED AS A TEMPORARY REGISTER
; WAS PONR RESET?
; POINT NEXT BIT
MOV R1,R10
AND R2,R10
BNE WDOG-RESET
...
; R10 USED AS A TEMPORARY REGISTER
; WAS WATCH DOG RESET?
68
Download from Www.Somanuals.com. All Manuals Search And Download.
Notes:
•
•
When the PONR bit is 1, contents of bits other than that should be handled as indeterminate. Thus, if a
reset factor needs to be checked, the command for checking the power-on reset must be placed at the
front.
Checking reset factors other than power-on reset can be done in any position. Priorities are determined
in the order of checking.
69
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
3.12.7
Stop Status
Stop status indicates the status that stops all internal clocks and oscillation circuit
operation. It can be minimized the power consumption.
■ Overview of Stop Status
Stop status indicates the status that stops all internal clocks and oscillation circuit operation. It can be
minimized the power consumption.
Transition to the stop status is performed as follow.
•
Writing in standby control register (STCR) using the instruction
Returning from the stop status is performed one of the following.
•
•
Interrupt request (only applies to peripherals where interrupt request can be generated even under stop
status)
Applying the L level to the RST pin
Under stop status, all internal clocks are stopped, so built-in peripherals other than those that can generate
interrupts for returning will be stopped.
■ Block Diagram of Stop Control Section
Figure 3.12-9 shows the block diagram of stop control section.
Figure 3.12-9 Block diagram of stop control section
STOP state transition request signal
Stop signal
STCR
Internal bus
STOP
CPU clock
Clock
generation
Clear
Internal
Internal Interrupt
Internal bus clock
bus clock
Internal reset
generation
CPU Hold Enable
CPU Hold Request
Internal
peripheral
clock
Internal peripheral clock
generation
STOP state display singal
Clok stop
Clok cancel
request singal request singal
70
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Transition to Stop Status
● Transition to the stop state using an instruction
Write "1" to bit 7 of the STCR register to enter stop status.
After a stop request is issued, the status is changed such that the CPU does not use the internal bus, and
then the clocks are stopped in the following order.
CPU clock →internal bus clock → internal peripheral clock
The oscillation circuit stops when the internal peripheral clock stops.
Notes:
The following routine must be used to change the status to stop using a command.
•
•
•
Before writing to the STCR, set the same value to the CCK1, 0 and PCK1, 0 bit lots of the GCR, and the
gear ratios between the CPU system clock and peripheral system clock should be the same.
Do not provide the stop state when the CHC bit of GCR is "0". To enter stop status, "1" must be set to
the CHC bit of the GCR, and 1/2 division system clock must be selected.
At least five consecutive NOP instructions must be provided immediately after writing to the STCR.
[Setting]
DI:8 #00000001b,R1 ; CPU=Peripheral gear ratio, CHC=1
LDI:32 #GCR,R2
STB R1,@R2
LDI:8 #10010000b,R1 ; STOP=1
LDI:32 #STCR,R2
STB R1,@R2
NOP
;
;
;
;
;
NOP
NOP
NOP
NOP
■ Return by Stop Status
Returning from stop status can be performed by generating an interrupt or reset.
● Return by interrupt
If the interrupt-enabled bit attached to the peripheral function is valid, returns from the stop status by
generating a peripheral interrupt.
Returning from the stop status to the normal operation status is carried out in the following procedure.
Generates interrupt -> Restarts oscillation circuit operation -> Waits for oscillation stabilization -> After
stabilization, restarts supply of internal peripheral clock -> Restarts supply of internal bus clock -> Restarts
supply of internal CPU clock
The program execution after oscillation stabilization waiting time is as follows.
•
When the level of the interrupt is enabled by the I flag of CPU ILM
71
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
- After saving the register, fetches in the interrupt vector and executes from the processing routine.
When the level of the interrupt is disabled by the I flag of CPU ILM
•
- Executes the instruction the following instruction that changed to the stop status.
● Return by RST pin
Returning from stop status to normal operating status is as per the following procedure.
L level application to the RST pin -> Generates an internal reset -> Restarts oscillation circuit operation ->
Waits for oscillation stabilization -> After stabilization, restarts supply of internal peripheral clock ->
Restarts supply of internal bus clock -> Restarts supply of internal CPU clock -> Fetches in the reset vector
-> Restarts the command execution from the reset entry address
Notes:
•
•
If an interrupt request has already been generated from a peripheral, status is not changed to stop, and
writing is ignored.
No internal clocks are supplied while waiting for oscillation stabilization except for power-on reset. For
power-on reset, the internal status needs to be initialized, so all internal clocks are supplied.
72
Download from Www.Somanuals.com. All Manuals Search And Download.
3.12.8
Sleep Status
Sleep status indicates that the CPU clock and internal bus clock are stopped.
Power consumption under the status where CPU operation is not required can be
reduced in some extent.
■ Overview of Sleep Status
Sleep status indicates that the CPU clock and internal bus clock are stopped.
Power consumption under the status where CPU operation is not required can be reduced in some extent.
The transition to the sleep status is performed as follow.
•
Writing in standby control register (STCR) using the instruction
Returning from the sleep status is performed one of the following.
•
•
Interrupt request
Reset factor generation
Under sleep status, the peripheral clock operates, so reset is possible by interrupt of built-in peripheral.
■ Block Diagram of Sleep Control Section
Figure 3.12-10 shows the block diagram of the sleep control section.
Figure 3.12-10 Block diagram of sleep control section
Sleep state transition request signal
Stop signal
STCR
Internal bus
CPU clock
SLEP
Clock
generation
Clear
Internal
bus clock
generation
Internal Interrupt
Internal reset
Internal bus clock
Internal
peripheral
clock
Internal peripheral clock
generation
STOP state display singal
Clok stop
Clok cancel
request singal request singal
73
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
■ Transition to Sleep Status
To enter sleep status, write "0" to bit 7 of the STCR register and "1" to bit 6.
Issues the sleep request, and then stops clocks in the following order once the status of the CPU is changed
so that the internal bus is not used.
CPU clock → Internal bus clock
Notes:
The following routine must be used to change to sleep status.
•
Before writing the STCR, set the same value to the CCK1, 0 and PCK1, 0 bit lots of the GCR, and the
gear ratio between the CPU system clock and peripheral system clock should be the same.
•
•
The CHC bit of GCR is can be any value.
At least five consecutive NOP instructions must be provided immediately after writing to the STCR.
[Setting]
LDI:8 #11001100b,R1 ; CPU=Peripheral gear ratio (left example: oscillation x 1/8), CHC is option.
LDI:32 #GCR,R2
STB R1,@R2
LDI:8 #01010000b,R1 ; SLEP=1
LDI:32 #STCR,R2
STB R1,@R2
NOP
NOP
NOP
NOP
NOP
;
;
;
;
;
■ Return by Sleep Status
Returning from sleep status can be done by generating an interrupt or reset.
● Return by interrupt
If the interrupt-enabled bit attached to the peripheral function is valid, returns from sleep status by
generating a peripheral interrupt.
Returning from sleep status to normal operating status is as per the following procedure.
Generates interrupt -> Restarts supply of internal bus clock -> Restarts supply of internal CPU clock
The program execution after clock supply is as follow.
•
When the level of the interrupt is enabled by the I flag of CPU ILM
- After saving the register, fetches in the interrupt vector and executes from the processing routine.
When the level of the interrupt is disabled by the I flag of CPU ILM
•
- Executes the instruction of the following instruction that changed to the stop status.
74
Download from Www.Somanuals.com. All Manuals Search And Download.
● Return by Reset request
Returning from sleep status to normal operating status is as per the following procedure.
Generates an internal reset -> Restarts supply of internal bus clock -> Restarts supply of internal CPU clock
-> Fetches in the reset vector -> Restarts the command execution from the reset entry address
Notes:
•
•
Execution of the numeric command following the command that writes the STCR may be complete.
Therefore, if a cancel or branch command for the interrupt request is placed immediately after, it may
seem as though a different operation from that expected is carried out.
If an interrupt request has already been generated from a peripheral, the status will not be sleep.
75
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
3.12.9
State Transition in Standby Mode
Figure 3.12-11 shows the state transition in standby mode.
■ State Transition in Standby Mode
Figure 3.12-11 State transition in standby mode
Oscillation Stabilization
Wait Reset State
Power ON
Oscillation Stabilization
Reset State
Wait Time
STOP State
RUN State
SLEEP State
(1) Oscillation Stabilization Wait Time end
(2) Reset cancellation
(3) Reset input
(4) STCR register SLEP=1
(5) Interrupt input or NMI input
(6) STCR register STOP=1
76
Download from Www.Somanuals.com. All Manuals Search And Download.
3.12.10 Gear Function
The gear function supplies to thin out the clock. There are two types of independent
circuits (for the CPU and for peripherals), and data can be transmitted and received
between the CPU and peripherals even with different gear ratios. Furthermore, whether
to use a clock with the same cycle as the clock from the oscillation circuit or a clock via
the 1/2 division circuit can be specified as the original clock selection.
■ Block Diagram of Gear Control Section
Figure 3.12-12 Block diagram of gear control section
Gear interval indication
signal for CPU
Gear interval
generation circuit
for CPU clock
CCK
PCK
CHC
CPU clock
Internal bus
Internal bus
clock
Gear interval
generation circuit
for peripheral clock
X0
X1
1/ 2
Internal peripheral
clock
PLL
(1 multiplication)
Gear interval indication
signal for peripheral
■ Setting of Gear Function
The requested gear ratio can be set by setting the CCK1, 0 bit of the gear control register (GCR) to the
requested value under the CPU clock control, or by setting the PCK1, 0 bit of the same register to the
requested value under the peripheral clock control.
[example]
LDI:32 #GCR,R2
LDI:8 #11111100b,R1
STB R1,@R2
; CCK=11, PCK=11, CHC=0
; CPU clock=1/8f, Peripheral clock=1/8f, f=direct
; CCK=01, PCK=10, CHC=0
LDI:8 #01111000b,R1
STB R1,@R2
; CPU clock=1/2f, Peripheral clock=1/4f, f=direct
; CCK=00, PCK=10, CHC=0
LDI:8 #00111000b,R1
STB R1,@R2
; CPU clock=f, Peripheral clock=1/4f, f=direct
77
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
LDI:8 #00110000b,R1
STB R1,@R2
; CCK=00, PCK=00, CHC=0
; CPU clock=f, Peripheral clock=f, f=direct
; CCK=10, PCK=00, CHC=0
LDI:8 #10110000b,R1
STB R1,@R2
; CPU clock=1/4f, Peripheral clock=f, f=direct
Setting "1" to the CHC bit of the gear control register selects the 1/2 division circuit output as the source
clock, and uses "0" and the clock whose cycle is the same as the clock from the oscillation circuit as they
are. The CPU system and peripheral system are simultaneously changed to switch the source clock.
[example]
LDI:8 #01110001b,R1
LDI:32 #GCR,R2
; CCK=01, PCK=00, CHC=1
STB R1,@R2
; CPU clock=1/2f, Peripheral clock=f, f=1/2xtal
; CCK=00, PCK=00, CHC=1
LDI:8 #00110001b,R1
STB R1,@R2
; CPU clock=f, Peripheral clock=f, f=1/2xtal
; CCK=00, PCK=00, CHC=0
LDI:8 #00110000b,R1
STB R1,@R2
; CPU clock=f, Peripheral clock=f, f=direct
Figure 3.12-13 shows the timing.
Figure 3.12-13 Diagram of gear switching timing
Source clock
CPU clock (a)
CPU clock (b)
Peripheral clock (a)
Peripheral clock (b)
CHC
CCK value
0 0
PCK value
■ Restrictions of Gear Function
Table 3.12-6 shows the combination of the gear that can be used in MB91191/MB91192 series.
Table 3.12-6 Restrictions of gear function
CCK
For CHC=0
0, 0
0, 1
1, 0
1, 1
0, 0
0, 1
1, 0
1, 1
×
×
×
PCK
×
×
×
×: Selection disabled
: The resource of the SIO and PPG is disabled the operation.
78
Download from Www.Somanuals.com. All Manuals Search And Download.
Note:
When the CHC is 1, the peripheral resource of SIO and PPG does not operate correctly.
79
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
3.12.11 Clock Series Diagram
Figure 3.12-14 shows the clock series diagram.
■ Clock Series Diagram
Figure 3.12-14 Clock series diagram
XO
PLL
1/2
Clock
generation
unit
φ
θ
CPU
C bus
convert
I/D
ROM
RAM
Custom
External bus control
R bus
convert
D
Interrupt control
A/DC
RAM
RAM
SIO to 2
FRC
PPG0 to 1
RTG0 to 2
PWM0x to 1x
PWC
FG input unit
Ext-INT
CFG,DFG,FRG0-1
Sync with X0
PCK
General - purpose
Prescaler
Timer 0 to 4
Timer 5
EC4
EC5
General - purpose
port C to D
Sync with φ
General - purpose
port 0 to 7
80
Download from Www.Somanuals.com. All Manuals Search And Download.
3.12.12 Clock Series of Peripheral Resource
Table 3.12-7 shows the table for the clock series list of peripheral resource.
■ Table for Clock Series List of Peripheral Resource
Table 3.12-7 Table for clock series list of peripheral resource
Division clock
supply destination
Division clock generation
destination
Peripheral resource
Capstan
Clock
Remark
Each input is synchronized
with X0
Servo
Drum
Reel
X0(fch)
-
FRC
FRC, Capture
X0(fch)
PPG
-
RTG
Servo
General-purpose
prescaler
Timer 0-5
PWC
PPG
RTG
PPG0
FRC
φ
-
FRC
Clock generation block
PPG1
RTG0
RTG1
RTG2
FRC
-
FRC
A/D converter
φ
-
-
Clock generation block
General-purpose
prescaler
FRC
OSC
FRC
OSCI(PCK)
SIO
SIO0
SIO1
SIO2
TIM0
TIM1
TIM2
TIM3
TIM4
φ
-
Clock generation block
Each input is
synchronized with φ
Timer
FRC
-
FRC
Operation by FRC Clock
FRC, EC
φ(FRC, EC)
X0(fch)
FRC
Operation by FRC, external
clock
TIM5
-
-
FRC
FRC and external clock is
synchronized with φ
Clock generation block
PWM
PWC
PWM0x
PWM1x
-
FRC
-
FRC
Operation by FRC Clock
81
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
3.12.13 Watchdog Function
The watchdog function detects any uncontrolled programs. If writing A5 and 5A to
H
H
the watchdog reset postpone register is not performed within the predetermined period
due to an uncontrolled program or suchlike, a watchdog reset request is generated by
the watchdog timer.
■ Block Diagram of Watchdog Control Section
Figure 3.12-15 Block Diagram of Watchdog control section
M
P
X
Edge
Detect
Timebase
timer
Rese
generation F/F
Internal reset
Latch
State decoder
Reset state transition
request signal
clr
State transition
control circuit
CTBR
WTx
WPR
A5&5A
RSRR
WDOG
Internal bus
■ Activating Watchdog Timer
The watchdog timer starts operation by writing to the watchdog control register (WTCR). In this case, the
interval time for the watchdog timer is set by the WT1 and WT0 bits. In terms of interval time setup, only
the time set by the first writing is valid, and subsequent settings will be ignored.
[example]
LDI:8 #10000000b,R1 ; WT1, 0=10
LDI:32 #WTCR,R2
STB R1,@R2
; Watchdog timer activation
82
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Reset Generation Delay
Once the watchdog timer is initiated, A5H and 5AH must be regularly written to the watchdog reset
postpone register (WPR) by the program.
The flip-flop for watchdog reset memorizes the falling edge of the tap selected by the timebase timer if this
flip-flop is not cleared by the 2nd falling edge, a reset is generated.
Figure 3.12-16 shows the operations of the watchdog timer.
Figure 3.12-16 Operations of watchdog timer
Timebase timer Overflow
Watchdog flip-flop
WTE write
Watchdog start
Watchdog clear
Watchdog reset generation
Notes:
•
•
The time interval between the first 5AH and the next 5AH is not specified. Postponement of the
watchdog can be performed only when the interval for 5AH writing is within the period specified by the
WT bit twice, and A5H writing is performed once between them.
After the first A5H if writing other than 5AH is performed, the first A5H writing will be invalid.
Therefore, A5H must be written again.
■ Timebase Timer
Figure 3.12-17 Configuration of Timebase Timer
φ
1/21
1/22
1/23
1/ 218
1/219
1/220
1/221
The timerbase timer is used as the timer for the clock supplying to the watchdog timer and timer for the
oscillation stabilization wait time. The operation clock φ is twice as large as X0 when GCR CHC is 1, and
is one time as large as X0 when GCR CHC is 0.
83
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3 CPU
84
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 4
External Bus Interface
This chapter describes an outline of the external bus
interface, the register configuration/functions, the bus
operation, and the bus timing, and program examples
for the bus operation are explained.
85
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 4 External Bus Interface
4.1
Overview of External Bus Interface
The external bus interface controls the external memory and interface with the external
I/O.
■ Feature of External Bus Interface
•
16-bit (64KB) address output
•
Only 1 bank can be set by the chip select function
- Capable of setting by the 64KB in the arbitrary position on the logical address space
Capable of setting a 16-/8-bit bus width
•
•
•
•
Insertion of the programmable auto memory wait (maximum for 7 cycles)
Support for the time division I/O interface of address and data
Support of little endian mode
86
Download from Www.Somanuals.com. All Manuals Search And Download.
4.2
Block Diagram
Figure 4.2-1 shows the block diagram of the external bus interface.
■ Block Diagram of External Bus Interface
Figure 4.2-1 Block diagram of external bus interface
A-Out
M
U
X
External DATA Bus
write
buffer
switch
switch
read
buffer
DATA BLOCK
ADDRESS BLOCK
+1or +2
inpage
address
buffer
External
shifter
Address Bus
CS0X-CS5X
comparator
ASR
AMR
CS1X (Read/Write Control)
RD
Internal pin control unit
WR0, WR1
All Block Control
registers
&
ALE
Control
87
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 4 External Bus Interface
4.3
Area of Bus Interface
A total of six types of chip select areas are prepared as bus interfaces.
■ Area of Bus Interface
Each area position can be arbitrarily allocated in units of at least 64 KB in the 4 GB space by the area select
registers (ASR1 to 5) and area mask registers (AMR1 to 5).
Within the area specified by these registers, when the external bus access is performed to area 1 (CS1X),
the supported read/write signal (RD, WR0, and WR1) will be active "L".
Note:
The area 0 is allocated to space other than the area specified by ASR1 to ASR5.
At a reset, the external area other than 00010000H to 0005FFFFH becomes area 0.
0014FFFFH. In the same way, examples in which area 1 is allocated per 512 KB from 00000000H to
Figure 4.3-1 Setting example of chip select area
00000000H
00080000H
00000000H
00080000H
CS1X (512K)
CS0X (512K)
000FFFFFH
CS0X (1M byte)
CS2X (1M byte)
CS3X (1M byte)
CS4X (1M byte)
CS5X (1M byte)
000FFFFFH
0010FFFFH
0011FFFFH
0012FFFFH
0013FFFFH
0014FFFFH
001FFFFFH
002FFFFFH
003FFFFFH
004FFFFFH
CS1X (64k byte)
CS2X (64k byte)
CS3X (64k byte)
CS4X (64k byte)
CS5X (64k byte)
CS0X
CS0X
Region disposition example 1
Region disposition example 2
88
Download from Www.Somanuals.com. All Manuals Search And Download.
4.4
Bus Interface
The bus interface has an follow:
• Normal bus interface
• Time division I/O interface of address and data
• DRAM control interface
These interfaces can only be used in predetermined areas.
■ Bus Interface
Table 4.4-1 shows the correspondence between each chip select area and the usable interface function. The
area mode register (AMD) is specifies which interface is used.
Table 4.4-1 Each area and usable interface mode
Selectable bus interface
Area
Remark
Normal Bus Time division
DRAM
0
1
-
-
-
-
The use of the terminal is prohibited.
-
-
2 to 5
-
-
The use of the terminal is prohibited.
● Specifying time division I/O
In area 1, the address and data are time division input/output on the bus with the width set by AMD1.
The latch pulse of address is output to the ALE pin.
● Specifying bus size
A bus width can be specified the area 1 by the register setting.
89
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 4 External Bus Interface
4.5
Register of External bus Interface
This section lists the register of external bus interface.
■ Register List of External Bus Interface
Figure 4.5-1 Register list of external bus interface
15
8
7
0
bit
ASR 1
AMR1
ASR 2
AMR2
ASR 3
AMR3
ASR 4
AMR4
ASR 5
AMR5
Area Select Register 1
Area Mask Register 1
Area Select Register 2
Area Mask Register 2
Area Select Register 3
Area Mask Register 3
Area Select Register 4
Area Mask Register 4
Address:
00060CH
00060EH
000610H
000612H
000614H
000616H
000618H
00061AH
00061CH
00061EH
Area Select Register 5
Area Mask Register 5
AMD0
AMD32
AMD5
AMD1
AMD4
Area Mode Register 0 / Area Mode register 1
Area Mode Register 32 / Area Mode register 4
Area Mode Register 5
000620H
000622H
000624H
000626H
RFCR
ReFresh Control Register
DMCR4
DMCR5
DRAM Control Register 4
DRAM Control Register 4
00062CH
00062EH
LER
MODR*
Little Endian Register / MODe Register
0007FEH
*: For detail of MODR register, see "3.11 Memory Access Mode".
Note:
Function pins for parts are not prepared under this product, so do not access these registers.
90
Download from Www.Somanuals.com. All Manuals Search And Download.
4.5.1
Area Selection Register (ASR) and Area Mask Register
(AMR)
Area selection registers (ASR1 to ASR5) and area mask registers (AMR1 to ACR5)
specify the address space of the chip select areas 1 to 5.
■ Area Selection Register (ASR) and Area Mask Register (AMR)
Figure 4.5-2 Area selection register (ASR1 to 5)
bit
Initial value
0001H
ASR1
15
14
13
12
12
12
12
12
2
1
0
Address 0000 060CH
A31 A30 A29
A18 A17
A16
W
15
W
14
W
13
W
2
W
1
W
0
bit
ASR2
Address 0000 0610H
A30 A29
A18 A17 A16
A31
0002H
0003H
0004H
0005H
W
15
W
14
W
13
W
2
W
1
W
0
bit
ASR3
A30 A29
A18 A17 A16
Address 0000 0614H
A31
W
15
W
14
W
13
W
2
W
1
W
0
ASR4 bit
Address 0000 0618H
A30 A29
A18 A17 A16
A31
W
15
W
14
W
13
W
2
W
1
W
0
bit
ASR5
Address 0000 061CH
A31 A30 A29
A18 A17 A16
W
W
W
W
W
W
Figure 4.5-3 Area Mask register (AMR1 to 5)
bit
Initial valaue
0000H
AMR1
15
14
13
12
12
12
12
12
2
1
0
Address 0000 060EH
A31 A30 A29
A18 A17
A16
Access
W
15
W
14
W
13
W
2
W
1
W
0
bit
AMR2
Address 0000 0612H
A30 A29
A18 A17 A16
A31
0000H
0000H
0000H
0000H
Access
W
15
W
14
W
13
W
2
W
1
W
0
bit
AMR3
A30 A29
A18 A17 A16
Address 0000 0616H
A31
Access
AMR4 bit
W
15
W
14
W
13
W
2
W
1
W
0
Address 0000 061AH
A30 A29
A18 A17 A16
A31
Access
W
15
W
14
W
13
W
2
W
1
W
0
bit
AMR5
Address 0000 061EH
Access
A31 A30 A29
A18 A17 A16
W
W
W
W
W
W
Area selection registers (ASR1 to ASR5) and area mask registers (AMR1 to ANR5) specify the address
space of the chip select areas 1 to 5.
Area selection registers (ASR1 to ASR5) specify the upper 16 bits (A31 to A16) of the address, and mask
the address bit supported by the area mask registers (AMR1 to AMR 5). Each bit of area mask register
91
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 4 External Bus Interface
(AMR1 to AMR5) assumes "care" by "0" and "don't care" by "1".
"care" indicates the address space while setting "0" when the ASR set value is "0" or setting "1" when it is
"1". "don't care" indicates the address space for both "0" and "1" cases regardless of the ASR set value.
Examples for each chip select area specification by combining the area selection register and area mask
register are shown below.
[example 1]
ASR1 = 00000000 000000 11B
AMR1 = 00000000 000000 00B
When the above is set, the AMR1 bit supporting the bit where "1" is set to ASR1 is "0", so the address
space of area 1 will be 64 KB as per the following.
00000000 00000011 00000000 00000000B (00030000H)
to
00000000 00000011 11111111 11111111B (0003FFFFH)
[example 2]
ASR2 = 00001111 11111111B
AMR2 = 00000000 000000 11B
When the above is set, "1" and "0" are left as "care" for the ASR2 set value supporting the bit where "0" is
set as AMR2, and the ASR2 bit supporting the bit where "1" is set as AMR2 will be "don't care" for "0" or
"1", so the address space of area 2 will be 256 KB as per the following.
00001111 11111100 00000000 00000000B (0FFC0000H)
to
00001111 11111111 11111111 11111111B (0FFFFFFFH)
The address space of each area 1 to 5 can be arbitrarily allocated in units of at least 64 KB in the 4 GB
space by ASR1 to ASR5 and AMR1 to AMR5. Within the area specified by these registers, when bus
access is performed on area 1, the supported read/write pin (RD, WR0, and WR1) will be "L" output.
As area 0, space other than the area set by ASR1 to ASR5 and AMR 1 to AMR5 is allocated, the area other
than 0001000H to 0005FFFFH is allocated by the initial values of ASR1 to ASR5 and AMR1 to AMR5 at a
reset.
Note:
Set the chip select area so that mutual overlapping is avoided.
Figure 4.5-4 shows a map set in the units of 64KB by the initial value at a reset and a map of area set in the
example 1 and 2 above.
92
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure 4.5-4 Sample maps specified by chip select area
Initial value
00000000H
Setting value in Example1 and 2
00000000H
Region 0
00010000H
00020000H
00030000H
00040000H
00050000H
00060000H
FFFFFFFFH
Region 0
Region 1
Region 2
Region 3
Region 4
Region 5
Region 0
64KB
64KB
64KB
64KB
64KB
00030000H
00040000H
0FFC0000H
Region 1
Region 0
64KB
Region 2
Region 0
256KB
10000000H
FFFFFFFFH
93
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 4 External Bus Interface
4.5.2
Area Mode Register 1 (AMD1)
The area mode register 1 (AMD1) specifies the memory access operation mode for each
chip select area.
■ Area Mode Register 1 (AMD1)
Figure 4.5-5 Area mode register 1 (AMD1)
bit
7
6
5
4
3
2
1
0
Initial value
BW1 BW0 WTC2 WTC1 WTC0 0--00000B
Address: 0000 0621H
Access
MPX
R/W
R/W R/W R/W R/W R/W
The area mode register 1 (AMD1) specifies the operation mode for the chip select area 1 (the area specified
by ASR1 and AMR1). In area 1, the time division input/output interface can be specified for the address/
data input/output.
The time division input/output interface outputs addresses to the data bus and inputs/outputs data, and
supports 8-bit and 16-bit bus widths only as follows.
•
•
8-bit bus width: A7 to A0 multiplexes to D31 to D24.
16-bit bus width: A15 to A0 multiplexes to D31 to D16.
[bit7] :MPX (MultiPleX bit)
The MPX controls the time division input/output interface for the address and data input/output.
0
Specification prohibited
1
Time division input/output interface
When the external bus mode is used for this product, the time division input/output interface must be
specified.
[bit4, 3] :BW1, 0 (Bus Width bit)
The BW1 and 0 specifies the bus width of area 1.
BW1
BW0
Bus width
0
0
1
1
0
1
0
1
8 bits
16 bits
reserved
reserved
[bit2 to 0] :WTC2 to 0(Wait Cycle bit)
The WTC specifies the auto insert wait cycle number for normal bus interface and time division input/
output interface operation. Operation is the same as WTC2 to WTC0 of the AMD0, but is initialized to
"000" by reset, and the insert wait cycle number will be "0".
94
Download from Www.Somanuals.com. All Manuals Search And Download.
Note:
Be sure to set the BW1 and BW0 of AMD1 before writing to the MODR.
After setting the mode register (MODR), the bus width set by the AMD is valid for external area 1.
Do not change the BW1 and BW0 after writing the MODR. It causes the malfunction.
MODR write
RST (Reset)
The contents of AMD1 register is enabled.
95
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 4 External Bus Interface
4.5.3
Little Endian Register (LER)
Bus access of the MB91191/MB91192 series is usually big endian for all areas, but
setting the LER enables one of the areas from 1 to 5 to be handled as a little endian
area.
However, area 0 is not for little endian.
■ Little Endian Register (LER)
Figure 4.5-6 Little endian register (LER)
bit
7
6
5
4
3
2
1
0
Initial value
-----000B
Address: 0000 07FEH
Access
LE2
W
LE1
W
LE0
W
Table 4.5-1 Mode setting using combination of bits (LE2, LE1 and LE0)
LE2
LE1
LE0
Mode
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Initial value after reset. No little endian area exists.
Area 1 is handled as little endian. Area 0, 2 to 5 are handled as big endian.
Area 2 is handled as little endian. Area 0 to 1 and 3 to 5 are handled as big endian.
Area 3 is handled as little endian. Area 0 to 2 and 4 to 5 are handled as big endian.
Area 4 is handled as little endian. Area 0 to 3 and 5 are handled as big endian.
Area 5 is handled as little endian. Area 0 to 4 are handled as big endian.
96
Download from Www.Somanuals.com. All Manuals Search And Download.
4.6
Bus Operation
The basic item of the bus operation is explained as follow.
• The relationship between the data bus width and control signal
• Bus access of big endian
• Bus access of little endian
• Comparison of external access between big endian and little endian
■ Relationship between Data Bus Width and Control Signal
The relationship between the data bus width and control signal for the next bus interface is described.
•
The time division input/output bus interface
■ Bus Access of Big Endian
The external access is described as follow.
Data format
Data bus width
•
•
•
•
External bus access
Connection example with external device
■ Bus Access of Little Endian
The external access is described as follow.
•
•
•
•
Difference between little endian and big endian
Data format
Data bus width
Connection example with external device
■ Comparison of External Access between Big Endian and Little Endian
As a comparison of the external access between big endian and little endian, word access, half-word access,
and byte access to the bus width are described.
97
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 4 External Bus Interface
4.6.1
Relationship between Data Bus Width and Control Signal
The control signal of WR0 to WR1 always supports the byte position of the data bus 1:1
regardless of big endian/little endian is used, or the data bus width.
■ The Relationship between the Data Bus Width and Control Signal
In this section, the byte position of the data bus for this product used by the data bus width that has been
set, and control signals that support it are summarized.
● The time division input/output bus interface
Figure 4.6-1 Data bus width and control signals under the time division input/output bus interface
a) 16 bit bus width
Data bus Output address Control siganal
b) 8 bit bus width
Data bus Output address Control siganal
D31
A15 to 8
A7 to 0
WR0
WR1
A7 to 0
WR0
D16
(D15 to 0: unused)
(D23 to 0: unused)
98
Download from Www.Somanuals.com. All Manuals Search And Download.
4.6.2
Bus Access of Big Endian
The data format in the FR20 series is normally big endian. Thus, external bus access is
big endian for areas in which little endian (LER) is not set.
■ Data Format
The relationship between the internal register and external data bus is indicated per data format.
● Half-word access (LDUH, STH instruction execution)
Figure 4.6-2 Relationship between the internal register and external data bus of half-word access
a) Output address Lower"00"
b) Output address Lower"10"
External bus
Internal register
D31
Internal register External bus
D31
AA
D23
BB
D31
D23
D31
D23
D23
D15
D15
AA
D7
BB
D0
D15
D7
D15
D7
AA
BB
AA
BB
D7
D0
D0
D0
● Byte access (LDUH, STH instruction execution)
Figure 4.6-3 Relationship between internal register and external data bus of byte access
a) Output address Lower"00" b) Output address Lower"01" c) Output address Lower"10" d) Output address Lower"11"
Internal register
Internal register
Internal register
Internal register
External bus
External bus
External bus
External bus
D31
D31
D31
D31D31
D31
D31
D31
AA
D23
D23
D23
D23
D15
D23
D23
D15
D23
D15
D23
D15
D7
AA
D15
D15
D15D15
D7
AA
D7
D7
D0
D7
AA
D0
D7
D0 D0
D7
AA
D0
D7
AA
D0
AA
AA
D0
D0
■ Data Bus Width
The relationship between the internal register and external data bus is indicated per data bus width.
99
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 4 External Bus Interface
● 16-bit bus width
Figure 4.6-4 Relationship between internal register and external data bus of 16-bit bus width
Internal register
Output addres lower
External bus
"00"
"10"
D31
D23
D15
D07
D31
D23
read/write
AA
BB
CC
DD
AA
BB
CC
DD
● 8-bit bus width
Figure 4.6-5 Relationship between internal register and external data bus of 8-bit bus width
Internal register
Output addres lower
External bus
"00" "01" "10" "11"
read/write
D31
D23
D15
D07
D31
AA BB CC
DD
AA
BB
CC
DD
■ External Bus Access
External bus access (16-bit/8-bit bus width) is shown per word, half-word, and byte access in Figure 4.6-6
•
•
•
Access byte position
Program address and output address
Bus access count
: Specified address lower 2-bit by program
: Output address lower 2-bit
: Output address start byte position
: Access data byte position
PA1/PA0
Output A1/A0
: Bus access count
The MB91191/MB91192 series do not detect the misalignment.
According to the word access, even if the address lower 2-bit specified by the program is "00", "01", "10",
or "11", the address lower 2-bit to be output will be all "00". In case of half-word access, when the lower
address is "00" or "01", "00" will be set, and when it is "10" or "11", "10" will be set.
100
Download from Www.Somanuals.com. All Manuals Search And Download.
● Width of bus of 16 bits
Figure 4.6-6 External bus access on 16-bit bus width
(A) Word access
(a) PA1/PA0='00'
(b) PA1/PA0='01'
1) Output A1/A0='00'
(b) PA1/PA0='10'
1) Output A1/A0='00'
(b) PA1/PA0='11'
1) Output A1/A0='00'
1) Output A1/A0='00'
2) Output A1/A0='10'
MSB LSB
2) Output A1/A0='10'
2) Output A1/A0='10'
2) Output A1/A0='10'
00 01
00 01
10 11
00 01
10 11
00 01
10 11
10 11
16bit
(B) Halfword access
(a) PA1/PA0='00'
(b) PA1/PA0='01'
(d) PA1/PA0='11'
(c) PA1/PA0='10'
1) Output A1/A0='00'
MSB LSB
1) Output A1/A0='10'
1) Output A1/A0='00'
1) Output A1/A0='10'
00 01
10 11
00 01
10 11
00 01
10 11
00 01
10 11
(B) Byte access
(a) PA1/PA0='00'
1) Output A1/A0='00'
(b) PA1/PA0='01'
(b) PA1/PA0='10'
(d) PA1/PA0='11'
1) Output A1/A0='10'
1) Output A1/A0='01'
1) Output A1/A0='11'
MSB LSB
00 01
10 11
00 01
10 11
00 01
10 11
00 01
10 11
101
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 4 External Bus Interface
● Width of bus of 8 bits
Figure 4.6-7 External bus access on 8-bit bus width
(A) Word access
(a) PA1/PA0="00"
(b) PA1/PA0="01"
Output A1/A0="00"
(c) PA1/PA0="10"
(d) PA1/PA0="11"
Output A1/A0="00"
Output A1/A0="00"
Output A1/A0="00"
Output A1/A0="01"
Output A1/A0="10"
Output A1/A0="11"
Output A1/A0="01"
Output A1/A0="10"
Output A1/A0="11"
Output A1/A0="01"
Output A1/A0="10"
Output A1/A0="11"
Output A1/A0="01"
Output A1/A0="10"
Output A1/A0="11"
MSB LSB
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
8bit
(B) Halfword access
(a) PA1/PA0="00"
(b) PA1/PA0="01"
(c) PA1/PA0="10"
(d) PA1/PA0="11"
Output A1/A0="00"
Output A1/A0="01"
Output A1/A0="00"
Output A1/A0="01"
Output A1/A0="10"
Output A1/A0="11"
Output A1/A0="10"
Output A1/A0="11"
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
(C) Byte access
(a) PA1/PA0="00"
Output A1/A0="00"
(b) PA1/PA0="01"
(c) PA1/PA0="10"
(d) PA1/PA0="11"
Output A1/A0="01"
Output A1/A0="10"
Output A1/A0="11"
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
102
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Connection Example with External Device
Figure 4.6-8 Connection example with external device
MB91191/MB91192
D31
D23
D24 WR0 D16 WR1
0
1
X
D15 D08 D07 D00
16-bit device
D07 D00
8-bit device
("0"/"1" Address lower 1-bit)
103
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 4 External Bus Interface
4.6.3
Bus Access of Little Endian
For areas in which little endian (LER) is set, external bus access is little endian.
Bus access of the MB91191/MB91192 series is realized by swapping the byte position of
the data bus in accordance with the bus width while the big endian output address
order and control signal output are basically the same, using the bus access operation
for big endian.
When connected, the big endian and little endian areas must be physically separated,
so special care must be taken.
■ Differences between Little Endian and Big Endian
Differences between little endian and big endian are mentioned as follows.
The order of addresses to be output is the same for big endian and little endian.
Data bus control signal to be used for the 32-, 16-, and 8-bit bus width is the same for big endian and little
endian.
● Word access
The byte data at the MSB side supporting the big endian address "00" is the little endian byte data at the
LSB side. In the case of word access, all of the four-byte positions within the word will be reversed.
"00" → "11", "01" → "10", "10" → "01", "11" → "00"
● Half-word access
The byte data at the MSB side supporting the big endian address "0" is the little endian byte data at the LSB
side. In the case of half-word access, the two-byte positions within the half-word will be reversed.
"0" → "1", "1" → "0"
● Byte access
Both big endian and little endian are the same.
■ Data Format
The relationships between the internal register and external data bus is shown per data format.
● Half word access (LDUB, STB instruction execution)
Figure 4.6-9 Relationship between internal register and external data bus of half-word access
a) Output address Lower "00"
b) Output address Lower "10"
External bus
Internal register
D31
Internal register External bus
D31
D31
D23
D31
D23
BB
AA
D23
D23
D15
D7
D15
AA
D7
BB
D0
D15
D7
D15
D7
AA
BB
BB
AA
D0
D0
D0
104
Download from Www.Somanuals.com. All Manuals Search And Download.
● Byte access (LDUB, STB instruction execution)
Figure 4.6-10 Relationship between internal register and external data bus of byte access
a) Output address Lower "00" b) Output address Lower "01" c) Output address Lower "10"
d) Output address Lower "11"
Internal register External bus Internal register External bus Internal register External bus Internal register External bus
D31
D23
D31
D23
D31
D23
D31
D23
D31
D23
D31
D23
D31
D23
D31
D23
AA
AA
D15
D7
D15
D7
D15
D7
D15
D7
D15
D7
D15 D15
D15
D7
AA
D7
D0
D7
D0
AA
AA
AA
AA
AA
D0
D0
D0
D0
D0
D0
■ Data Bus Width
● 32-bit bus width
Figure 4.6-11 Relationship between internal register and external data bus of 32-bit bus width
Internal register
External bus
D31
D31
read/write
AA
BB
CC
DD
DD
CC
BB
AA
D23
D15
D07
D23
D15
D07
● 16-bit bus width
Figure 4.6-12 Relationship between internal register and external data bus of 16-bit bus width
Internal register
Output address lower
External bus
"00" "10"
D31
D23
D15
D07
D31
D23
read/write
AA
BB
CC
DD
DD BB
CC AA
105
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 4 External Bus Interface
● 8-bit bus width
Figure 4.6-13 Relationship between internal register and external data bus of 8-bit bus width
Internal register
Output address lower
External bus
"00" "01" "10" "11"
D31
D23
D15
D07
D31
read/write
AA
BB
CC
DD
DD CC BB
AA
■ Connection Example with External Device
● 16-bit bus width
Figure 4.6-14 Connection example with MB91191/MB91192 series and external device
(16-bit bus width)
MB91191/MB91192
D31
|
D23
|
D24
D16
WR0
WR1
WR0
WR1
D31-24 D23-16
MSB
LSB
D07 D00 D15 D08
106
Download from Www.Somanuals.com. All Manuals Search And Download.
● 8-bit bus width
Figure 4.6-15 Connection example with MB91191/MB91192 series and external device
(8-bit bus width)
MB91191/MB91192
series
D31
|
D24
WR0
D07 D00
Big endian region
107
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 4 External Bus Interface
4.6.4
Comparison between Big Endian and Little Endian for
External Access
Comparison between big endian and little endian of external access for word access,
half-word access, and byte access to the bus width is described.
■ Word Access
Big endian mode
Little endian mode
Internal Reg External pin
16-bit bus
width
Internal Reg External pin
address: "0" "1"
Control pin
Control pin
address:
D31
"0" "1"
D31
D31
D31
WR0
WR1
AA
BB
CC
DD
AA CC
BB DD
WR0
WR1
AA
DD BB
CC AA
BB
DD1166
CC
D16
DD
D00
D00
8-bit bus
width
Internal Reg External pin
Control pin
WR0
Internal Reg External pin
Control pin
WR0
address:
D31
"0" "1" "2" "3"
address:
D31
"0" "1" "2" "3"
D31
D31
AA
DD CC BB AA
AA
AA BB CC DD
DD2244
DD2244
BB
CC
DD
BB
CC
DD
D00
D00
108
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Half-word Access
Big endian mode
Little endian mode
Internal Reg External pin
16-bit bus
width
Internal Reg External pin
Control pin
Control pin
address:
D31
"0"
AA
BB
address: "0"
D31
D00
D31
D31
BB
WR0
WR1
WR0
WR1
AA
D16
AA
D16
AA
BB
BB
D00
Internal Reg External pin
Control pin
Internal Reg External pin
address: "2"
Control pin
"2"
address:
D31
D31
D31
D31
WR0
WR1
DD
CC
CC
DD
WR0
WR1
D16
CC
D16
CC
DD
DD
D00
D00
8-bit bus
width
Internal Reg External pin
Control pin
WR0
Internal Reg External pin
address: "0" "1"
Control pin
WR0
"0" "1"
address:
D31
D31
D31
D31
AA BB
BB AA
DD224
D24
D24
AA
AA
BB
BB
D00
D00
D00
D00
Internal Reg External pin
address: "2" "3"
Control pin
WR0
Internal Reg External pin
address: "2" "3"
Control pin
WR0
D31
D31
D31
D31
CC DD
DD CC
DD2244
DD2244
CC
DD
CC
DD
D00
D00
D00
D00
109
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 4 External Bus Interface
■ Byte Access
Big endian mode
Little endian mode
16-bit bus
width
Internal Reg External pin
Control pin
WR0
Internal Reg External pin
Control pin
WR0
address:
D31
"0"
address:
D31
"0"
D31
D31
D00
AA
AA
DD1166
AA
D16
AA
D00
Internal Reg External pin
Control pin
WR1
Internal Reg External pin
Control pin
WR1
address:
D31
"1"
"1"
address:
D31
D31
D31
BB
BB
D16
D16
D16
D16
D16
D16
BB
BB
D00
D00
Internal Reg External pin
Control pin
WR0
Internal Reg External pin
Control pin
WR0
address:
D31
"2"
address:
D31
"2"
D31
D31
CC
CC
D16
D16
CC
CC
D00
D00
Internal Reg External pin
Control pin
Internal Reg External pin
Control pin
WR1
address:
"3"
address:
"3"
D31
D31
D31
D31
DD
DD
WR1
D16
D16
DD
DD
D00
D00
110
Download from Www.Somanuals.com. All Manuals Search And Download.
Big endian mode
Little endian mode
8-bit
Bus width
Internal Reg External pin
Control pin
WR0
Internal Reg External pin
Control pin
WR0
address:
D31
address:
D31
"0"
"0"
D31
D31
AA
AA
D24
D24
AA
AA
D00
D00
Internal Reg External pin
Control pin
WR0
Internal Reg External pin
Control pin
WR0
address:
D31
"1"
address:
D31
"1"
D31
D31
BB
BB
D24
D24
BB
BB
D00
D00
Internal Reg External pin
Control pin
WR0
Internal Reg External pin
Control pin
WR0
address:
"2"
address:
"2"
D31
D31
D31
D31
CC
CC
D24
D24
CC
CC
D00
D00
Internal Reg External pin
address: "3"
Control pin
WR0
Internal Reg External pin
address: "3"
Control pin
WR0
D31
D31
D31
D31
DD
DD
D24
D24
DD
DD
D00
D00
111
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 4 External Bus Interface
4.7
Bus Timing
The detailed bus access operation in each mode is shown.
■ Time Division I/O Interface
In area 1, time division input/output interface for addresses/data is supported. The time division I/O is
performed the bus width specified by the BW1 and BW0.
For the time division input/output interface, a total of four clocks cycle, namely address output cycle (2
clocks) + data access cycle (2 clocks) comprises the basic bus cycle, and for the address output cycle, the
ALE pin is asserted as the output address latch signal.
Furthermore, the addresses (A15-A08) indicate the start byte for access to the address pins (A15-A08) in
the same way as normal during the time-shared bus cycle.
● 8 bits bus width read
Figure 4.7-1 8 bits bus width read
CASE
AAMD1: MPX=1, BW=00B, WTC=000B, EPCR0:ALEE=1
access --- 8 bit data read
MA1
MA2
BA1
BA2
CLK
ACLK
ALE
A15-08
D31-24
: Read data
Fetch timing
ddr15-08
ddr07-00
ddr15-08
ddr07-00
#0
External RD
At 8-bit bus width, A07 to A00 addresses output to D31 to D24.
● Automatic wait operation at the time division mode (16-bit bus width write)
Figure 4.7-2 Automatic wait operation at the time division mode (16-bit bus width write)
CASE
AMD1: MPX=1, BW=01B, WTC=001B, EPCR0:ALEE=1
aaccess --- 16 bit data write
MA1
MA2
BA1
BA1
BA2
CLK
ACLK
ALE
ddr15-08
ddr15-00
ddr15-08
ddr15-00
A15-08
D31-16
#0:1
External WR0, WR1
Note:
112
To access the external extend area, execute dummy read on built-in ROM area prior to access.
Download from Www.Somanuals.com. All Manuals Search And Download.
4.8
Program Example of External Bus Operation
A simple program example for operating the external bus is described.
■ Program Specification Example of External Bus Operation
The setting of register is shown as follow.
● Area
•
•
•
•
•
•
Area 0 (AMD0) : 32-bit, usual bus, automatic wait 0
Area 1 (AMD1) : 16-bit, time division I/O, automatic wait 2
Area 2 (AMD32) : 32-bit, usual bus, automatic wait 1
Area 3 (AMD32) : 32-bit, usual bus, automatic wait 1
Area 4 (AMD4) :16-bit, DRAM, page size 256, 1CAS/2WE, with wait, CBR refresh
Area 5 (AMD5) :16-bit, DRAM, page size 512, 2CAS/1WE, without wait, CBR refresh
● The others
•
•
•
•
Refresh (RFCR): without wait, 1/8 setting
External pin (EPCR0): external RDY reception, arbitration of BRQ, BGRNTX
External pin (DSCR) :DRAM pin setting
Little endian (LER) : area 2
Note the following about the others.
•
•
•
MD2, 1, and 0 are "010", and external vector is 32-bit mode.
Before setting the mode register (MODR), set area 0 to the same bus width.
Set the area 1 to 5 not to overlap.
■ Program Example of External Bus Operation
Under this program, bytes are used to write the byte register, and half-words are used for the half-word
register for explanatory purposes.
***** Example program
//Each register setting
init_gcr ldi:8 #0x00,r0
*****
// gcr register X1 clock mode
ldi:20
#0x484,r1
// gcr register address setting
// gcr register write
#0xffff,r0 // External pin setting
// External RDY wait, bus arbitration by BRQ, BGRNTX
stb
r0,@r1
init_epcr ldi:20
ldi:20
sth
#0x628,r1
r0,@r1
// epcr0 register address setting
// epcr0 register write
init_dscr ldi:8
#0xff,r0
// DRAM pin setting
// RAS, CAS, WE
ldi:20
#0x625,r1
// dscr register address setting
113
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 4 External Bus Interface
stb
r0,@r1
// dscr register write
#0x10,r0 // 32-bit bus, 0-wait
// amd0 register address setting
// amd0 register write
#0x8a,r0 // time division, 16-bit bus, 2-wait
// amd1 register address setting
// amd1 register write
#0x89,r0 // Normal, 32-bit bus, 1-wait
// amd32 register address setting
// amd32 register write
#0x88,r0 // DRAM, 16-bit bus
// amd4 register address setting
// amd4 register write
#0x88,r0 // DRAM, 16-bit bus
// amd5 register address setting
// amd5 register write
#0x0c90,r0 // page size=256, Q1/Q4-wait, Page
// 1CAS-2WE, CBR, No parity
init_amd0 ldi:8
ldi:20
stb
#0x620,r1
r0,@r1
init_amd1 ldi:8
ldi:20
stb
#0x621,r1
r0,@r1
init_amd32 ldi:8
ldi:20
stb
#0x622,r1
r0,@r1
init_amd4 ldi:8
ldi:20
stb
#0x623,r1
r0,@r1
init_amd5 ldi:8
ldi:20
stb
#0x624,r1
r0,@r1
init_dmcr4 ldi:20
ldi:20
sth
#0x62c,r1
r0,@r1
// dmcr4 register address setting
// dmcr4 register write
init_dmcr5 ldi:20
// 2CAS-1WE, CBR, No parity
#0x10c0,r0
// page size=512, Q1/Q4-wait none, Page
ldi:20
sth
#0x62e,r1
r0,@r1
// dmcr5 register address setting
// dmcr5 register write
init_rfcr ldi:20
#0x0205,r0
// REL=2, R1W/R3W-wait none, refresh, 1/8
ldi:20
sth
#0x626,r1
r0,@r1
// rfcr register address setting
// rfcr register write
init_asr ldi:32
#0x0013001,r0 // asr1,amr1 register setting value
ldi:32
ldi:32
ldi:32
ldi:32
ldi:20
ldi:20
ldi:20
ldi:20
ldi:20
st
#0x0015001,r1 // asr2,amr2 register setting value
#0x0017001,r2 // asr3,amr3 register setting value
#0x0019001,r3 // asr4,amr4 register setting value
#0x001b001,r4 // asr5,amr5 register setting value
#0x60c,r5
#0x610,r6
#0x614,r7
#0x618,r8
#0x61C,r9
r0,@r5
// asr1,amr1 register address setting
// asr2,amr2 register address setting
// asr3,amr3 register address setting
// asr4,amr4 register address setting
// asr5,amr5 register address setting
// asr1,amr1 register write
st
r1,@r6
// asr2,amr2 register write
114
Download from Www.Somanuals.com. All Manuals Search And Download.
st
st
st
r2,@r7
r3,@r8
r4,@r9
// asr3,amr3 register write
// asr4,amr4 register write
// asr5,amr5 register write
init_ler ldi:8
#0x02,r0
// CH2 little endian
ldi:20
stb
#0x7fe,r1
r0,@r1
// ler register address setting
// ler register write
init_modr ldi:8
#0x80,r0
// modr register address setting
// modr register write
// External ROM external bus
ldi:20
stb
#0x7ff,r1
r0,@r1
// external bus access
adr_set ldi:32
#0x00136da0, r0 // ch1 address
ldi:32
ldi:32
ldi:32
ldi:32
ldi:32
ldi:32
ldi:32
#0x00151300, r1 // ch2 address
#0x00196434, r2 // ch4 address (within the page)
#0x0019657c, r3 // ch4 address (within the page)
#0x00196600, r4 // ch4 address (outside of the page)
#0x001a6818, r5 // ch5 address (within the page)
#0x001a6b8c, r6 // ch5 address (within the page)
#0x001a6c00, r7 // ch5 address (outside of the page)
bus_acc ld
@r0,r8
// ch1 data word load
lduh
ld
@r1,r9
// ch2 data half word load
// ch4 data word load
// ch4 data byte load
@r2,r10
@r3,r11
r8,@r4
ldub
st
// ch4 data word store
// ch5 data half word store
// ch5 data word store
// ch5 data byte store
sth
st
r9,@r5
r10,@r6
r11,@r7
stb
115
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 4 External Bus Interface
116
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 5 I/O Port
5.1
Overview of I/O Port
The MB91191/MB91192 series have the 102 output ports. In terms of ports, there are
ports 2, 3, 5, and 6 that are also used for external bus functions, and ports 0, 1, 4, and 7
to D that are also used for peripheral functions. Ports other than ports 0, 2, and 3 have a
function selection bit per bit, and a port function, peripheral function, or external bus
function can be selected.
■ Register List of I/O Port
Figure 5.1-1 Register list of I/O Port
bit
7
0
Port 3 data register
Port 2 data register
Port 1 data register
Port 0 data register
Port 7 data register
Port 6 data register
Port 5 data register
Port 4 data register
Port B data register
Port A data register
Port 9 data register
Port 8 data register
PDR3
PDR2
PDR1
Address: 000000H
000001H
000002H
000003H
000004H
000005H
000006H
000007H
000010H
000011H
000012H
000013H
000016H
PDR0
PDR7
PDR6
PDR5
PDR4
PDRB
PDRA
PDR9
PDR8
PDRD
PDRC
Port D data register
Port C data register
000017H
Port 3 Direction register
Port 2 Direction register
Port 1 Direction register
Port 0 Direction register
Port 7 Direction register
Port 6 Direction register
Port 5 Direction register
Port 4 Direction register
Port B Direction register
Port A Direction register
Port 9 Direction register
Port 8 Direction register
DDR3
DDR2
DDR1
DDR0
DDR7
000008H
000009H
00000AH
00000BH
00000CH
00000DH
00000EH
00000FH
000018H
DDR6
DDR5
DDR4
DDRB
DDRA
DDR9
000019H
00001AH
00001BH
00001EH
DDR8
DDRD
Port D Direction register
Port C Direction register
DDRC
00001FH
PFS1
000602H
Port 1 function selection register
Port 7 function selection register
Port 6 function selection register
Port 5 function selection register
Port 4 function selection register
PFS7
PFS6
PFS5
000604H
000605H
000606H
PFS4
PIEB
PIEA
PFS9
000607H
000020H
000021H
000022H
000023H
Port B input enable register
Port A input enable register
Port 9 function selection register
Port 8 function selection register
PFS8
PFSD
PFSC
000026H
000027H
Port D function selection register
Port C function selection register
118
Download from Www.Somanuals.com. All Manuals Search And Download.
5.2
Port 0
Port 0 is the input/output port, and is also used for servo input, capture input, and PWC
input.
■ Functions of I/O Port 0
Each port has two registers per bit, namely the data direction register (DDR) and port data register (PDR),
and input/output can be set independently per bit. Pins whose DDR is "1" are set to Output, whereas Pins
whose DDR is "0" are set to Input. The PDR is undefined by a reset, and the DDR is cleared to "0" and set
to Input. The value written to the PDR is output to the pin at the time of output setup by specifying the
DDR per bit.
At this time, the contents of the PDR are read from the read value of the PDR.
At the time of the input setup, the pin will have high impedance status.
At this time, the pin level is read from the read value of the PDR.
■ Block Diagram of Port 0
Figure 5.2-1 Block Diagram of Port 0
PDR
DDR
Pin
P07 to P00
Periphreral input
Data register read
119
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 5 I/O Port
■ Registers for Port 0
● Port 0 data register (PDR0)
Figure 5.2-2 Port 0 data register (PDR0)
bit
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
PD07
R/W
PD06
R/W
PD05
R/W
PD04
R/W
PD03
R/W
PD02
R/W
PD01
R/W
PD00
R/W
Address: 000003H
Access
● Port 0 direction register (DDR0)
Figure 5.2-3 Port 0 direction register (DDR0)
bit
7
6
5
4
3
2
1
0
Initial value
Address: 00000BH
0000 0000B
DR07
DR06
DR05
DR04
DR03
DR02
DR01
DR00
Access
W
W
W
W
W
W
W
W
120
Download from Www.Somanuals.com. All Manuals Search And Download.
5.3
Port 1
Port 1 is an input/output port, and is also used for RTG output, timer clock/external
interrupt input, and PWC input.
■ Functions of I/O Port 1
The port has three registers per bit, namely DDR, PDR, and PFS (port function select register), and the port
input/output setup and function selection can be executed independently per bit. The peripheral function is
selected for pins whose PFS is "1", whereas the port function is selected for those whose PFS is "0". Pins
whose DDR is "1" are set to Output, whereas pins whose DDR is "0" are set to Input.
The PFS is initialized by a reset and the port function is selected. Also, the PDR is undefined, and the DDR
is cleared to "0" and the port is specified to Input.
The value written to the PDR is output to the pin at the time of output setup by specifying the DDR per bit.
At this time, the contents of the PDR are read from the read value of the PDR.
At the time of the input setup, the pin will have high impedance status. At this time, the pin level is read
from the read value of the PDR.
■ Block Diagram of Port 1
Figure 5.3-1 Block Diagram of Port 1
Peripheral output
Pin
PDR
P17 to P10
PFS
DDR
Peripheral input
Data register read
121
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 5 I/O Port
■ Registers for Port 1
● Port 1 data register (PDR1)
Figure 5.3-2 Port 1 data register (PDR1)
bit
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
PD17
R/W
PD16
R/W
PD15
R/W
PD14
R/W
PD13
R/W
PD12
R/W
PD11
R/W
PD10
R/W
Address: 000002H
Access
● Port 1 direction register (DDR1)
Figure 5.3-3 Port 1 direction register (DDR1)
bit
7
6
5
4
3
2
1
0
Initial value
Address: 00000AH
0000 0000B
DR17
DR16
DR15
DR14
DR13
DR12
DR11
DR10
Access
W
W
W
W
W
W
W
W
● Port 1 function selection register (PFS1)
Figure 5.3-4 Port 1 function selection register (PFS1)
bit
Address: 000602H
Access
7
6
5
4
3
2
1
0
Initial value
0000 0000B
RT4E
RT3E
RT2E
RT1E
RT0E
W
W
W
W
W
W
W
W
Table 5.3-1 Operation of function selection bits
Register setting value
Function selection bits
0
1
[bit7]: RT4E
[bit6]: RT3E
[bit5]: RT2E
[bit4]: RT1E
[bit3]: RT0E
[bit2]:
General-purpose port
RTG output 4
General-purpose port
RTG output 3
RTG output 2
RTG output1
RTG output0
General-purpose port
General-purpose port
General-purpose port
General-purpose port/EC5, INT1 input
General-purpose port/EC5, INT1 input
General-purpose port/PMSK input
Specification prohibited
Specification prohibited
Specification prohibited
[bit1]:
[bit0]:
122
Download from Www.Somanuals.com. All Manuals Search And Download.
5.4
Port 2, 3
Ports 2 and 3 function as input/output ports under single-chip mode, and function as
the address/data bus under external bus mode.
■ Functions of I/O Port 2, 3
Each port has two registers per bit, namely DDR and PDR, and input/output can be set independently per
bit. Pins whose DDR is "1" are set to Output, whereas pins whose DDR is "0" are set to Input.
The PDR is undefined by a reset the DDR is cleared to "0" and set to Input.
In terms of the DDR specification per bit, for output setup, the value written to the PDR is output to the pin,
and the PDR contents are read as the read value of the PDR in this case.
At the time of the input setup, the pin will have high impedance status. At this time, the pin level is read
from the read value of the PDR.
■ Block Diagram of Port 2, 3
Figure 5.4-1 Block Diagram of Port 2, 3
Bus signal
Bus control
Pin
PDR
P27 to P20
P37 to P30
DDR
Data register read
123
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 5 I/O Port
■ Registers for Port 2, 3
● Port 2, 3 data register (PDR2, 3)
Figure 5.4-2 Port 2 data register (PDR2)
bit
7
6
5
4
3
2
1
0
Initial value
PD27
R/W
PD26
R/W
PD25
R/W
PD24
R/W
PD23
R/W
PD22
R/W
PD21
R/W
PD20
R/W
XXXX XXXXB
Address: 000001H
Access
Figure 5.4-3 Port 3 data register (PDR3)
bit
Address: 000000H
Access
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
PD37
R/W
PD36
R/W
PD35
R/W
PD34
R/W
PD33
R/W
PD32
R/W
PD31
R/W
PD30
R/W
● Port 2, 3 direction register (DDR2, 3)
Figure 5.4-4 Port 2 direction register (DDR2)
bit
Address: 000009H
Access
7
6
5
DR25
W
4
DR24
W
3
DR23
W
2
1
0
Initial value
0000 0000B
DR27
W
DR26
W
DR22
W
DR21
W
DR20
W
Figure 5.4-5 Port 3 direction register (DDR3)
bit
7
6
DR36
W
5
DR35
W
4
DR34
W
3
DR33
W
2
DR32
W
1
DR31
W
0
DR30
W
Initial value
Address: 000008H
Access
0000 0000B
DR37
W
124
Download from Www.Somanuals.com. All Manuals Search And Download.
5.5
Port 5
Port 5 is the input/output port and is also used for the external bus function.
■ Functions of Port 5
The port has three registers per bit, namely DDR, PDR, and PFS, and the port input/output setup and
function selection can be executed independently per bit. The external bus function is selected for pins
whose PFS is "1", whereas the port function is selected for those whose PFS is "0". Pins whose DDR is "1"
are set to Output, whereas pins whose DDR is "0" are set to Input.
The PFS is initialized by a reset and the port function is selected. Also, the PDR is undefined and the DDR
is cleared to "0" and the port is specified to Input.
In terms of the DDR specification per bit, for output setup, the value written to the PDR is output to the pin,
and the PDR contents are read as the read value of the PDR in this case.
At the time of the input setup, the pin will have high impedance status. At this time, the pin level is read
from the read value of the PDR.
■ Block Diagram of Port 5
Figure 5.5-1 Block Diagram of Port 5
Peripheral output
Bus control
Pin
PDR
P57 to P50
PFS
DDR
Data register read
125
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 5 I/O Port
■ Registers for Port 5
● Port 5 data register (PDR5)
Figure 5.5-2 Port 5 data register (PDR5)
bit
7
6
5
4
3
2
1
0
Initial value
Address: 000006H
Access
PD57
R/W
PD56
R/W
PD55
R/W
PD54
R/W
PD53
R/W
PD52
R/W
PD51
R/W
PD50
R/W
XXXX XXXXB
● Port 5 direction register (DDR5)
Figure 5.5-3 Port 5 direction register (DDR5)
bit
7
6
5
4
3
2
1
0
Initial value
0000 0000B
Address: 00000EH
Access
DR57
DR56
DR55
DR54
DR53
DR52
DR51
DR50
W
W
W
W
W
W
W
W
● Port 5 function selection register (PFS5)
Figure 5.5-4 Port 5 function selection register (PFS5)
bit
7
6
5
4
3
2
1
0
Initial value
A15E
A14E
A13E
A12E
A11E
A10E
A09E
A08E
Address: 000606H
Access
1111 1111B
W
W
W
W
W
W
W
W
Table 5.5-1 Operation of function selection bits
Register setting value
Function selection bit
0
1
Address (A15) output *
Address (A14) output *
Address (A13) output *
Address (A12) output *
Address (A11) output *
Address (A10) output *
Address (A09) output *
Address (A08) output *
[bit7]: A15E
[bit6]: A14E
[bit5]: A13E
[bit4]: A12E
[bit3]: A11E
[bit2]: A10E
[bit1]: A09E
[bit0]: A08E
General-purpose port
General-purpose port
General-purpose port
General-purpose port
General-purpose port
General-purpose port
General-purpose port
General-purpose port
Note:
The * setting is only valid when the external bus mode is specified. The general-purpose port
function is always selected for single-chip mode.
126
Download from Www.Somanuals.com. All Manuals Search And Download.
5.6
Port 6, 7
Ports 6 and 7 are input/output ports, and are also used for the external bus function and
timer output function.
■ Port 6, 7
The port has three register per bit, namely DDR, PDR and PFS, and port input/output setup and function
selection can be executed independently per bit.
The external bus function or peripheral function is selected for pins whose PFS is "1", whereas the port
function is selected for those whose PFS is "0". Pins whose DDR is "1" are set to Output, whereas pins
whose DDR is "0" are set to Input.
The PFS is initialized by a reset and the port function is selected. Also, the PDR is undefined and the DDR
is cleared to "0" and the port is specified to input.
In terms of the DDR specification per bit, for output setup, the value written to the PDR is output to the pin,
and the PDR contents are read as the read value of the PDR in this case.
At the time of input setup, the pin will have high impedance status. At this time, the pin level is read from
the read value of the PDR.
127
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 5 I/O Port
■ Block Diagram of Port 6, 7
Figure 5.6-1 Block Diagram of Port 6, 7
Peripheral output
bus control
Pin
PDR
P63 to P60
PFS
DDR
Data register read
Peripheral output
PDR
Pin
P67 to P64
PFS
DDR
Data register read
X0
PCK
frequency division
1/ 2
PFS
CSEL
Pin
PDR
PFS
P70
XOUTE
DDR
Data register read
128
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Registers for Port 6, 7
● Port 6, 7 data register (PDR6, 7)
Figure 5.6-2 Port 6 data register (PDR6)
bit
7
6
5
4
3
2
1
0
Initial value
Address: 000005H
Access
XXXX XXXXB
PD76
R/W
PD66
R/W
PD65
R/W
PD64
R/W
PD63
R/W
PD62
R/W
PD61
R/W
PD60
R/W
Figure 5.6-3 Port 7 data register (PDR7)
bit
7
6
5
4
3
2
1
0
Initial value
---- ---XB
Address: 000004H
Access
PD70
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
● Port 6, 7 direction register (DDR6, 7)
Figure 5.6-4 Port 6 direction register (DDR6)
bit
7
6
5
DR65
W
4
DR64
W
3
DR63
W
2
DR62
W
1
DR61
W
0
DR60
W
Initial value
Address: 00000DH
Access
0000 0000B
DR67
W
DR66
W
Figure 5.6-5 Port 7 direction register (DDR7)
bit
Address: 00000CH
Access
7
6
5
4
3
2
1
0
Initial value
---- ---0B
DR70
W
W
W
W
W
W
W
W
● Port 6, 7 function selection register (PFS6, 7)
Figure 5.6-6 Port 6 function selection register (PFS6)
bit
7
6
5
4
3
2
1
0
Initial value
T4OE
T5O1E
ALEE
WR1XE WR0XE
RDXE 0000 1111B
W
Address: 000605H
Access
W
W
W
W
W
W
W
Table 5.6-1 Operation of function selection bits
Register setting value
Function selection bits
0
1
[bit7]: T4OE
[bit6]: T5O1E
[bit5]:
General-purpose port
General-purpose port
General-purpose port
General-purpose port
General-purpose port
T4O output
T5O output
Setting disabled
[bit4]:
Setting disabled
ALE output *
WR1 output *
WR0 output *
RD output *
[bit3]: ALEE
[bit2]: WR1XE
[bit1]: WR0XE
[bit0]: RDXE
General-purpose port
General-purpose port
General-purpose port
129
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 5 I/O Port
Note:
The * setting is only valid when the external bus mode is specified. The general-purpose port
function is always selected for single-chip mode.
Figure 5.6-7 Port 7 function selection register (PFS7)
bit
7
6
5
4
3
2
1
0
Initial value
---- --00B
Address: 000604H
Access
XOUTE
CSEL
W
W
Table 5.6-2 Operation of function selection bits
Register setting value
Function selection bits
0
1
[bit7]:
[bit6]:
[bit5]:
[bit4]:
[bit3]:
[bit2]:
[bit1]: CSEL
fch/2 output (X0)
PCK/2 output (OSCI)
Clock output enabled
[bit0]: XOUTE
General-purpose port
130
Download from Www.Somanuals.com. All Manuals Search And Download.
5.7
Port 4, 8, 9
Ports 4, 8 and 9 are input/output ports, and are also used for PPG output and general-
purpose prescaler output.
■ Functions of Port 4, 8, 9
The port has three registers per bit, namely DDR, PDR, and PFS, and port input/output setup and function
selection can be executed independently per bit. The peripheral function is selected for pins whose PFS is
"1", whereas the port function is selected for those whose PFS is "0". Pins whose DDR is "1" are set to
Output, whereas pins whose DDR is "0" are se to Input.
The PFS is cleared to "0" by reset, and the port function is selected, the PDR is undefined, and the DDR is
cleared to "0" and set to Input.
In terms of the DDR specification per bit, for output setup, the value written to the PDR is output to the pin,
and the PDR contents are read as the read value of the PDR in this case.
At the time of input setup, the pin will have high impedance status. At this time, the pin level is read from
the read value of the PDR.
■ Block Diagram of Port 4, 8, 9
Figure 5.7-1 Block Diagram of Port 4, 8, 9
Peripheral output
Pin
PDR
P46 to P40
P87 to P80
P94 to P91
PFS
DDR
Peripheral input
Data register read
Peripheral output
Pin
P90
PDR
PFS
DDR
Data register read
131
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 5 I/O Port
■ Registers for Port 4, 8, 9
● Port 4, 8, 9 data register (PDR4, 8, 9)
Figure 5.7-2 Port 4 data register (PDR4)
bit
7
6
5
4
3
2
1
0
Initial value
Address: 000007H
Access
PD47
R/W
PD46
R/W
PD45
R/W
PD44
R/W
PD43
R/W
PD42
R/W
PD41
R/W
PD40
R/W
XXXX XXXXB
Figure 5.7-3 Port 8 data register (PDR8)
bit
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
Address: 000013H
Access
PD87
R/W
PD86
R/W
PD85
R/W
PD84
R/W
PD83
R/W
PD82
R/W
PD81
R/W
PD80
R/W
Figure 5.7-4 Port 9 data register (PDR9)
bit
7
6
5
4
3
2
1
0
Initial value
---X XXXXB
Address: 000012H
Access
PD94
R/W
PD93
R/W
PD92
R/W
PD91
R/W
PD90
R/W
R/W
R/W
R/W
● Port 4, 8, 9 direction register (DDR4, 8, 9)
Figure 5.7-5 Port 4 direction register (DDR4)
bit
Address: 00000FH
Access
7
6
5
4
3
2
1
0
Initial value
DR47
DR46
DR45
DR44
DR43
DR42
DR41
DR40 0000 0000B
W
W
W
W
W
W
W
W
Figure 5.7-6 Port 8 direction register (DDR8)
bit
7
6
5
4
DR84
W
3
2
DR82
W
1
DR81
W
0
Initial value
Address: 00001BH
Access
0000 0000B
DR87
W
DR86
W
DR85
W
DR83
W
DR80
W
Figure 5.7-7 Port 9 direction register (DDR9)
bit
7
6
5
4
3
2
1
0
Initial value
Address: 00001AH
Access
---0 0000B
DR94
DR93
DR92
DR91
DR90
W
W
W
W
W
W
W
W
● Port 4, 8, 9 function selection register (PFS4, 8, 9)
Figure 5.7-8 Port 4 function selection register (PFS4)
bit
7
6
5
4
3
2
1
0
Initial value
PG18E PG17E PG16E PG15E PG14E
PG13E PG12E 0000 0000B
Address: 000607H
Access
W
W
W
W
W
W
W
W
132
Download from Www.Somanuals.com. All Manuals Search And Download.
Table 5.7-1 Operation of function selection bits
Register setting value
Function selection bits
0
1
[bit7]:
General-purpose port
General-purpose port
General-purpose port
General-purpose port
General-purpose port
General-purpose port
General-purpose port
General-purpose port
Setting disabled
[bit6]: PG18E
[bit5]: PG17E
[bit4]: PG16E
[bit3]: PG15E
[bit2]: PG14E
[bit1]: PG13E
[bit0]: PG12E
PPG output 18
PPG output 17
PPG output 16
PPG output 15
PPG output 14
PPG output 13
PPG output 12
Figure 5.7-9 Port 8 function selection register (PFS8)
bit
7
6
5
4
3
2
1
0
Initial value
0000 0000B
Address: 000023H
Access
PG11E PG10E
PG09E PG08E PG07E
PG06E PG05E
PG04E
W
W
W
W
W
W
W
W
Table 5.7-2 Operation of function selection bits
Register setting value
Function selection bits
0
1
[bit7]: PG11E
[bit6]: PG10E
[bit5]: PG09E
[bit4]: PG08E
[bit3]: PG07E
[bit2]: PG06E
[bit1]: PG05E
[bit0]: PG04E
General-purpose port
General-purpose port
General-purpose port
General-purpose port
General-purpose port
General-purpose port
General-purpose port
General-purpose port
PPG output 11
PPG output 10
PPG output 09
PPG output 08
PPG output 07
PPG output 06
PPG output 05
PPG output 04
Figure 5.7-10 Port 9 function selection register (PFS9)
bit
7
6
5
4
3
2
1
0
Initial value
---0 0000B
PG03E PG02E
PG01E PG00E
POE
Address: 000022H
Access
W
W
W
W
W
133
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 5 I/O Port
Table 5.7-3 Operation of function selection bits
Register setting value
Function selection bits
0
1
[bit7]:
[bit6]:
[bit5]:
[bit4]: PG03E
[bit3]: PG02E
[bit2]: PG01E
[bit1]: PG00E
[bit0]: POE
General-purpose port
General-purpose port
General-purpose port
General-purpose port
General-purpose port
PPG output 03
PPG output 02
PPG output 01
PPG output 00
General-purpose prescaler output
134
Download from Www.Somanuals.com. All Manuals Search And Download.
5.8
Port A, B
Ports A and B are the input/output ports, and analog input and key input (for port A
only) are shared.
■ Functions of Port A, B
The port has three registers per bit, namely, DDR, PDR, and PIE (port input enable register), and input/
output can be selected independently per bit. In terms of port input/output, pins whose DDR is "1" are set to
Output, whereas pins whose DDR is "0" are set to Input. To be used as a general-purpose port, port input is
enabled by setting "1" to the PIE.
The PIE is cleared to "0" by reset, and the port function is disabled. The PDR is undefined, and the DDR is
cleared to "0" and set to Input.
In terms of the DDR specification per bit, for output setup, the value written to the PDR is output to the pin,
and the PDR contents are read as the read value of the PDR in this case.
At the time of input setup, the pin will have high impedance status. At this time, the pin level is read from
the read value of the PDR.
■ Block Diagram of Port A, B
Figure 5.8-1 Block Diagram of Port A, B
PDR
Pin
PA7 to PA0
PB7 to PB0
PIE
DDR
Key input (only Port A)
Data register read
Analog input
135
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 5 I/O Port
■ Registers for Port A, B
● Port A, B data register (PDRA, B)
Figure 5.8-2 Port A data register (PDRA)
bit
Address: 000011H
Access
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
PDA7
R/W
PDA6
R/W
PDA5
R/W
PDA4
R/W
PDA3
R/W
PDA2
R/W
PDA1
R/W
PDA0
R/W
Figure 5.8-3 Port B data register (PDRB)
bit
Address: 000010H
Access
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
PDB7
R/W
PDB6
R/W
PDB5
R/W
PDB4
R/W
PDB3
R/W
PDB2
R/W
PDB1
R/W
PDB0
R/W
● Port A, B direction register (DDRA, B)
Figure 5.8-4 Port A direction register (DDRA)
bit
7
6
5
4
3
2
1
0
Initial value
Address: 000019H
Access
0000 0000B
DRA7
DRA6
DRA5
DRA4
DRA3
DRA2
DRA1
DRA0
W
W
W
W
W
W
W
W
Figure 5.8-5 Port B direction register (DDRB)
bit
7
6
5
4
3
2
1
0
Initial value
Address: 000018H
Access
0000 0000B
DRB7
DRB6
DRB5
DRB4
DRB3
DRB2
DRB1
DRB0
W
W
W
W
W
W
W
W
● Port A, B input enable register (PIEA, B)
Figure 5.8-6 Port A input enable register (PIEA)
bit
Address: 000021H
Access
7
PIA7
W
6
5
4
3
2
PIA2
W
1
0
Initial value
0000 0000B
PIA6
W
PIA5
W
PIA4
W
PIA3
W
PIA1
W
PIA0
W
Figure 5.8-7 Port B input enable register (PIEB)
bit
7
6
5
4
3
2
1
0
Initial value
Address: 000020H
Access
0000 0000B
PIB7
PIB6
PIB5
PIB4
PIB3
PIB2
PIB1
PIB0
W
W
W
W
W
W
W
W
When the port is used for input functions, input is enabled by setting "1" to the supported bit.
Set "0" for the port is to be used as the analog input.
136
Download from Www.Somanuals.com. All Manuals Search And Download.
5.9
Port C, D
Ports C and D are input/output ports, and are also used as the PWM output, serial I/O,
and external interrupt.
■ Functions of Port C, D
The port has three registers per bit, namely, DDR, PDR, and PFS and input/output, setup and function
selection can be executed independently per bit. The peripheral function is selected for pin whose PFS is
"1", whereas the port function is selected for these whose PFS is "0".
The pins whose DDR is "1" are set to Output, whereas pins whose DDR is "0" are set to Input. The PFS is
cleared to "0" by reset, and the port function is selected. The PDR is undefined, and the DDR is cleared to
"0" and set to Input.
In terms of the DDR specification per bit, for output setup, the value written to the PDR is output to the pin,
and the PDR contents are read as the read value of the PDR in this case.
At the time of input setup, the pin will have high impedance status. At this time, the pin level is read from
the read value of the PDR.
■ Block Diagram of Port C, D
Figure 5.9-1 Block Diagram of Port C, D
Peripheral signal
I/O control
Pin
PDR
PC1, PC0
PD5, PD4
PD2, PD1
PFS
DDR
Peripheral input
Data register read
Peripheral output
Pin
PDR
PFS
PC7 to PC2
PD7, PD3
PD0
DDR
Peripheral input
Data register read
137
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 5 I/O Port
■ Registers for Port C, D
● Port C, D data register (PDRC, D)
Figure 5.9-2 Port C data register (PDRC)
bit
7
6
5
4
3
2
1
0
Initial value
Address: 000017H
Access
XXXX XXXX
PDC7
R/W
PDC6
R/W
PDC5
R/W
PDC4
R/W
PDC3
R/W
PDC2
R/W
PDC1
R/W
PDC0
R/W
Figure 5.9-3 Port D data register (PDRD)
bit
7
6
5
4
3
2
1
0
Initial value
Address: 000016H
Access
XXXX XXXXB
PDD7
R/W
PDD6
R/W
PDD5
R/W
PDD4
R/W
PDD3
R/W
PDD2
R/W
PDD1
R/W
PDD0
R/W
● Port C, D direction register (DDRC, D)
Figure 5.9-4 Port C direction register (DDRC)
bit
7
6
5
4
3
2
1
0
Initial value
Address: 00001FH
Access
DRC7
DRC6
DRC5
DRC4
DRC3
DRC2
DRC1
DRC0 0000 0000B
W
W
W
W
W
W
W
W
Figure 5.9-5 Port D direction register (DDRD)
bit
7
6
5
4
3
2
1
0
Initial value
DRD7
DRD6
DRD5
DRD4
DRD3
DRD2
DRD1
DRD0
0000 0000B
Address: 00001EH
Access
W
W
W
W
W
W
W
W
● Port C, D function selection register (PFSC, D)
Figure 5.9-6 Port C input enable register (PFSC)
bit
7
6
5
4
3
2
1
0
S00E
W
Initial value
0000 0000B
Address: 000027H
Access
SCK0E
W
PWM00E PWM01E PWM02E PWM10E PWM11E PWM12E
W
W
W
W
W
W
138
Download from Www.Somanuals.com. All Manuals Search And Download.
Table 5.9-1 Operation of function selection bits
Register setting value
Function selection bits
0
1
[bit7]: PWM00E
[bit6]: PWM01E
[bit5]: PWM02E
[bit4]: PWM10E
[bit3]: PWM11E
[bit2]: PWM12E
[bit1]: SCK0E
General-purpose port
PWM00 output
General-purpose port
PWM01 output
PWM02 output
PWM10 output
PWM11 output
PWM12 output
General-purpose port
General-purpose port
General-purpose port/SCS2 input
General-purpose port/SCS1 input
General-purpose port
SCK0 input/output
SO0 output
[bit0]: SO0E
General-purpose port
Figure 5.9-7 Port D function selection register (PFSD)
bit
7
6
5
4
3
2
SCK2E
W
1
SO2E
W
0
Initial value
Address: 000026H
Access
0000 0000B
SCK1E
W
SO1E
W
W
W
W
W
Table 5.9-2 Operation of function selection bits
Register setting value
Function selection bits
0
1
[bit7]:
General-purpose port/SI0 input
Setting prohibited
[bit6]:
General-purpose port/SCS0 input
General-purpose port
Setting prohibited
SCK1 input/output
SO1 output
[bit5]: SCK1E
[bit4]: SO1E
[bit3]:
General-purpose port
General-purpose port/SI1, INT2 Setting prohibited
input
[bit2]: SCK2E
[bit1]: SO2E
[bit0]:
General-purpose port
SCK2 input/output
SO2 output
General-purpose port
General-purpose port/SI2 input
Setting prohibited
139
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 5 I/O Port
140
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 6 FG Input
6.1
Overview of FG Input
The Frequency Generate (FG) input section comprises of the capstan input, drum input,
and reel input sections. Each input section performs division of the input FG signal,
generation of signals to be input to the FRC capture section and masking of the
predetermined period.
■ Capstan Input
The capstan input consists of the following 6 items.
•
Capstan control register
Capstan input control register
Capstan mask timer control register
Multiplying circuit
•
•
•
•
8 -bit programmable divider
Mask timer
•
■ Drum Input
The drum input consists of the following 5 items.
•
•
•
•
•
Drum control register
Drum input control register
Drum mask timer control register
4-bit programmable divider
Mask timer
■ Reel Input
The reel input consists of the following 7 items.
•
Reel control register
•
•
•
•
•
•
Reel 0 input control register
Reel 0 mask timer control register
Reel 1 input control register
Reel 1 mask timer control register
8-bit programmable divider
Mask timer
142
Download from Www.Somanuals.com. All Manuals Search And Download.
6.2
Capstan Input
The capstan input section is comprised of a multiplying circuit, 8-bit programmable
divider, and mask timer. This section explains the operation of each section and control
register.
■ Block Diagram of Capstan Input
Figure 6.2-1 Block Diagram of Capstan Input
Write ST
CAPDVC
Load (Sync)
8bit
00
Programmable devider
2 multipli-
cation
CFG
M
P
X
DVCFG
(to FRC)
RS-FF
QS
START (Mask Enable)
R1
R2
(from FRC
FRC9, 13)
10
2 /fch
M
P
X
Mask End
14
Mask Timer
2 /fch
00
DVCFG Free
(Mask Disable)
Load (Sync)
R
S
CAPC
DUB MTCS CMTS FCLR CFGD
CAPMTC
Internal Bus
■ Register List of Capstan Input
Figure 6.2-2 Register list of Capstan Input
bit
7
0
Capstan input control register
Capstan timer control register
Capstan control register
000050H
000051H
000052H
Address:
CAPDVC
CAPMTC
CAPC
143
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 6 FG Input
■ Capstan Control Register (CAPC)
Figure 6.2-3 Capstan Control Register (CAPC)
bit
7
CFGD
R
6
FCLR
W
5
CMTS
R
4
3
2
1
0
Initial value
Address: 000052H
Access
X1X0 ---0B
MTCS
R/W
DUB
[bit7]:CFGD
This is the capstan edge detection flag during capstan masking.
0
1
Without edge detection
With edge detection
[bit6]:FCLR
This is the capstan input edge detection flag clear bit.
0
1
Clear the CFGD flag.
None
The read value of this bit is always "1".
[bit5]:CMTS
This is the capstan mask timer status flag.
0
1
Mask released
Masking
[bit4]:MTCS
This is clock source selection bit of mask timer.
Selection Clock
in fch:@20MHz
51.2 µs
2 10/fch (FRC9)
2 14/fch (FRC13)
0
1
819.2 µs
[bit3 to 1]:
It is an unused bit.
[bit0]:DUB
This is the CFG input multiplication selection bit.
0
1
None
2 multiplication
144
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Capstan Input Control Register (CAPDVC)
Figure 6.2-4 Capstan Input Control Register (CAPDVC)
bit
7
6
5
4
3
2
1
0
Initial value
Address: 000050H
Access
XXXX XXXXB
DIV7
R/W
DIV6
R/W
DIV5
R/W
DIV4
R/W
DIV3
R/W
DIV2
R/W
DIV1
R/W
DIV0
R/W
[bit7 to 0]:DIV7 to 0
Executes division control of the capstan input and edge detection control depending on the set value.
Set value
00H
Division control
Edge detection
None
Both edge detection
01H
1-frequency division
2-frequency division
3-frequency division to
to
02H
03H
to
Rising edge detection
FDH
253-frequency division
254-frequency division
255-frequency division
FEH
FFH
■ Capstan Mask Timer Control Register (CAPMTC)
Figure 6.2-5 Capstan mask timer control register (CAPMTC)
bit
7
6
5
4
3
2
1
0
Initial value
Address: 000051H
Access
XXXX XXXXB
D7
D6
R/W
D5
D4
D3
D2
R/W
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
[bit7 to 0]:D7 to 0
Executes masking period control for the capstan input depending on the set value. When ΦMT is
specified as the clock cycle time selected by the mask timer clock select (CS) bit of the capstan control
register, and N is specified as the set value, the capstan input masking period TM is as follow.
TM= ΦMT × N ΦMT/2
However, N is set to 0, the mask processing does not perform.
145
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 6 FG Input
■ Operation of Capstan Input
● Operation of Multiplying circuit
The capstan FG (CFG) input is input to the 8-bit programmable divider via "Slew" or double circuit by
setting the multiplication select (DUB) bit of the capstan control register (CAPC). The input CFG signal is
edge detected after division that was set by the capstan control register (CAPDVC) is performed, and then
passes through the capstan mask timer, and is connected to the FRC capture unit as the DVCFG signal.
Figure 6.2-6 CFG output by multiplication selection
Input CFG
Delay CFG1
Delay CFG2
CFG output
Through
(DUB=0)
2 multiplication
(DUB=1)
● Operation of 8-bit Programmable divider
The programmable divider can be divided within the range between 1 to 255 by the value set to the capstan
input control register (CAPDVC).
When the value set to CAPDVC is "00H", division is not executed, and both edges of the CFG input are
directly output as the DVCFG signal. When values other than "00H" are set to CAPDVC, the output
divided by the rising edge of the CFG input is output as the DVCFG signal.
When the value set to CAPDVC is updated during division, the counter value is updated immediately after
the update. In this case, the DVCFG output is masked if the counter is updated simultaneously with the
DVCFG output (reload operation).
Figure 6.2-7 shows the sequence of the programmable divider.
Figure 6.2-7 Operation timing diagram of programmable divider
CFG input
DVCFG output
2
1
3
2
1
3
2
1
0
0
0
0 8
7
6
5
4
3 5
4
3
2
Counter value
Reload timing
Write timing
CAPDVC value
3
3
0
8
5
● Operation of Mask Timer
The mask timer loads the CAPMTC value and starts counting, and also masks the DVCFG output after
detecting the CFG division output edge. When the DVCFG output is detected during the masking period,
the CFGD flag is set. Even if the CAPMTC value is updated during the masking period, load operation to
the mask timer will not be executed. This updated value will be valid from the next masking period.
146
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure 6.2-8 Operation timing diagram of Mask Timer
CFG
frequency division
Output edge
Mask period
DVCFG output
CFGD bit
Wclr
Wclr
M.T Load
CAPMTC
● Limitation on using
When double mode is specified for the capstan input, do not set "00H" to the capstan input control register.
It may cause the malfunction.
147
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 6 FG Input
6.3
Drum Input
The drum input section comprises of the 4-bit programmable divider and mask timer.
This section explains the operation of each section and control register.
■ Block Diagram of Drum Input
Figure 6.3-1 Block diagram of Drum Input
0
2
DPGE DPCLR DPGD
R
Write ST
S
R Q D Q
S
DRMDVC
Load (Sync)
4bit
00
DPG
DFG
Programmable devider
DVDFG
(to FRC)
RS-FF
QS
START (Mask Enable)
(from FRC
R1
R2
FRC9,13)
10
2 /fch
M
P
X
Mask End
14
Mask Timer
2 /fch
00
DVCFG Free
(Mask Disable)
Load (Sync)
R
S
CAPC
DINV MTCS DMTS DFCLR DFGD
DRMMTC
3
7
Internal bus
■ Register List of Drum Input
Figure 6.3-2 Register list of Drum Input
bit
7
0
000053H
000054H
000055H
DRMC
Drum control register
Address:
Drum input control register
DRMDVC
DRMMTC
Drum mask timer control register
148
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Drum Control Register (DRMC)
Figure 6.3-3 Drum Control Register (DRMC)
bit
7
DFCG
R
6
5
4
3
2
DPGD
R
1
0
Initial value
Address: 000053H
Access
X1X0 0X10B
DFCLR DMTS
MTCS
R/W
DINV
R/W
DPCLR
W
DPGE
R/W
W
R
[bit7]:DFGD
This is the division FG edge detection flag during drum masking.
0
1
Without edge detection
With edge detection
[bit6]:DFCLR
This is the edge detection flag clear bit during drum masking.
0
1
Clear the DFGD flag.
None
The read value of this bit is always "1".
[bit5]:DMTS
This is the drum mask timer status flag.
0
1
Mask released
Masking
[bit4]:MTCS
This is clock source selection bit of mask timer.
Selection Clock
in fch:@20MHz
51.2 µs
210/fch (FRC9)
0
1
2 14/fch (FRC13)
819.2 µs
[bit3]:DINV
This is the polarity control bit of the DFG input signal.
0
1
Input through
Input inversion
149
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 6 FG Input
[bit2]:DPGD
It is DPG input edge detection flag.
0
1
DPG Input None
DPG input
[bit1]:DPCLR
This is the clear bit of DPG input edge detection flag.
0
1
Clear the DPGD flag.
None
The read value of this bit is always "1".
[bit0]:DPGE
This is the initialization control bit for the programmable divider using DPG input.
0
1
Not initialize by DPG input
Initialize by DPG input
■ Drum Input Control Register (DRMDVC)
Figure 6.3-4 Drum Input Control Register (DRMDVC)
bit
7
6
5
4
3
2
1
0
Initial value
---- XXXXB
Address: 000054H
Access
DIV3
DIV2
R/W
DIV1
R/W
DIV0
R/W
[bit7 to 4]:
It is an unused bit.
[bit3 to 0]:DIV3 to 0
Division control of the drum input and edge detection control are performed by the set value.
Set value
00H
Division control
Edge detection
None
Both edge detection
01H
1-frequency division
2-frequency division
3-frequency division
to
02H
03H
to
Rising edge detection
0DH
13-frequency division
14-frequency division
15-frequency division
0EH
0FH
150
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Drum Mask Timer Control Register (DRMMTC)
Figure 6.3-5 Drum mask timer control register (DRMMTC)
bit
7
6
5
4
3
2
1
0
Initial value
Address: 000055H
Access
XXXX XXXXB
D7
D6
R/W
D5
D4
D3
D2
R/W
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
[bit7 to 0]:D7 to 0
The masking period control of the drum input is performed by the set value.
When Φ is specified as the clock cycle time selected by the mask timer clock select (CS) bit of the drum
control register, and N is specified as the set value, the drum input masking period TM is as follow.
TM= ΦMT × N ΦMT/2. However, N is set to 0, the mask processing does not perform.
■ Operation of Drum Input
● 4-bit Programmable divider
The programmable divider can perform division within the range 1 to 15 using the value set to the drum
input control register (DRMDVC).
Refer to the capstan input section for operation of the programmable divider.
Rewriting the DINV bit affects the programmable divider operation. Prior to perform rewriting, some kind
of action should be performed, such as masking the capture input.
● Initialization of programmable divider by DPG input
The programmable divider is initialized by the rising edge of the DPG input if DPG input is enabled.
Figure 6.3-6 shows the initialization operation by DPG input and the set timing of DPG detection flag.
Figure 6.3-6 Timing diagram of initialization operation by DPG input
DPG input
DFG input
DPG Edge
Case1 (INV=0)
Load timing
Counter value
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
DVDFG output
DPG Flag
Wclr
Wclr
Case2 (INV=1)
Load timing
Counter value
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
DVDFG output
DPG Flag
Wclr
Wclr
151
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 6 FG Input
6.4
Reel Input
The reel input section comprises of the 8-bit programmable divider and mask timer.
This section explains the register which controls the operation of each section.
■ Block Diagram of Reel Input
Figure 6.4-1 Block Diagram of Reel Input
Write ST
RLxDVC
Load (Sync)
8bi t
00
Programmable devider
DVRFGx
(to FRC)
RFGx
RS-FF
QS
START (Mask Enable)
(from FRC
R1
R2
FRC9, 13)
210/fch
214/fch
M
P
X
Mask End
Mask Timer
00
DVCFG Free
(Mask Disable
Load (Sync)
R
S
RLC RxMTCS RxMTS RxFCLR RLxD
RLxMTC
Internal bus
■ Register List of Reel Input
Figure 6.4-2 Register list of Reel Input
bit
Address: 000057H
000058H
7
0
RLC
Reel control register
RL0DVC
RL0MTC
Reel 0 input control register
000059H
Reel 0 mask timer control register
Reel 1 input control register
00005AH
RL1DVC
RL1MTC
00005BH
Reel 1 mask timer control register
152
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Reel Control Register (RLC)
Figure 6.4-3 Reel Control Register (RLC)
bit
7
RL1D
R
6
5
4
3
2
1
0
Initial value
X1X0 X1X0B
Address: 000057H
Access
R1FCLR R1MTS R1MTCS RL0D
R/W
R0FCLR R0MTS R0MTCS
R/W
W
R
R
W
R
[bit7]:RL1D
This is the division FG edge detection flag during reel 1 masking.
0
1
Without edge detection
With edge detection
[bit6]:R1FCLR
This is the edge detection flag clear bit during the reel 1 masking.
0
1
Clear RL1D flag.
None
The read value of this bit is always "1".
[bit5]:R1MTS
This is the reel 1 mask timer status flag.
0
1
Mask released
Masking
[bit4]:R1MTCS
This is clock source selection bit of reel 1 mask timer.
Selection Clock
in fch:@20MHz
51.2 µs
2 10/fch (FRC9)
2 14/fch (FRC13)
0
1
819.2 µs
[bit3]:RL0D
This is the division FG edge detection flag during the reel 0 masking.
0
1
Without edge detection
With edge detection
153
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 6 FG Input
[bit2]:R0FCLR
This is the edge detection flag clear bit during the reel 0 masking.
0
1
Clear RL0D flag
None
The read value of this bit is always "1".
[bit1]:R0MTS
This is the reel 0 mask timer status flag.
0
1
Mask released
Masking
[bit0]:R0MTCS
This is clock source selection bit of reel 0 mask timer.
Selection Clock
in fch:@20MHz
51.2 µs
2 10/fch (FRC9)
14/fch (FRC13)
0
1
819.2 µs
2
■ Reel Input Control Register (RLxDVC)
Figure 6.4-4 Reel input control register (RLxDVC)
bit
Access
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
DIV7
R/W
DIV6
R/W
DIV5
R/W
DIV4
R/W
DIV3
R/W
DIV2
R/W
DIV1
R/W
DIV0
R/W
[bit7 to 0]:DIV7 to 0
Division control of the drum input and edge detection control are performed by the set value.
Set value
00H
Division control
Edge detection
None
Both edge detection
01H
1-frequency division
2-frequency division
3-frequency division
to
02H
03H
to
Rising edge detection
FDH
253-frequency division
254-frequency division
255-frequency division
FEH
FFH
154
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Reel Mask Timer Control Register (RLxMTC)
Figure 6.4-5 Reel mask timer control register (RLxMTC)
bit
Access
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
D7
D6
R/W
D5
D4
D3
D2
R/W
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
[bit7 to 0]:D7 to 0
The masking period control of the reel input is performed by the set value. When ΦMT is specified as
the clock cycle time selected by the mask timer clock select (CS) bit of the reel control register, and N
is specified as the set value, the drum input masking period TM is as follow.
TM = ΦMT × N ΦMT/2. However, N is set to 0, the mask processing does not perform.
■ Operation of Reel Input
155
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 6 FG Input
156
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 7 FRC Capture
7.1
Overview of FRC Capture
The FRC capture section has built-in 24-bit free-run counter and uses FIFO format.
■ Feature of FRC Capture
•
Built-in 24-bit free-run counter (Minimum resolution 50 ns:@20 MHz)
•
Built-in FIFO (Data 21-bit x 8, factor 8-bit x 8)
■ Register List of FRC Capture
Figure 7.1-1 Register list of FRC capture
bit
7
0
Address:
000060H
000061H
000062H
000063H
000064H
000065H
000066H
000067H
000068H
000069H
00006AH
00006BH
FRCD2
FRCD1
FRCD0
CIC1
FRC count data register
Capture input control register
CIC0
CAPC
Capture control register
Capture source register
CAPS
CAPD2
CAPD1
CAPD0
Capture data register
158
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Block Diagram of FRC Capture
Figure 7.1-2 Block diagram of FRC capture
159
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 7 FRC Capture
7.2
Register of FRC Capture
This section shows the register configuration/functions of the FRC capture.
■ Capture Input Control Register (CIC1, CIC0)
● Capture input control register (CIC1)
Figure 7.2-1 Capture input control register (CIC1)
bit
Address: 000064H
Access
7
FCIF
R
6
5
4
3
2
1
0
Initial value
FCLR
W
FCIE
R/W
ICR2
R/W
ICR1
R/W
ICR0
R/W
X10- -000B
[bit7]:FCIF
It is capture request detection and interrupt request flag.
0
1
No capture request
Detect capture request
[bit6]:FCLR
It is capture request detection flag clear bit.
0
1
Clear CIF flag.
None
The read value of this bit is always "1".
[bit5]:FCIE
It is interrupt request enable bit.
0
1
Interdiction
Permission
[bit4, 3]:
It is an unused bit.
[bit2]:EIV2
It is EXI2 input edge detection polarity selection bit.
0
1
Falling edge detection
Rising edge detection
160
Download from Www.Somanuals.com. All Manuals Search And Download.
[bit1]:EIV1
[bit0]:EIV0
It is EXI1 input edge detection polarity selection bit.
0
1
Falling edge detection
Rising edge detection
It is EXI0 input edge detection polarity selection bit.
0
1
Falling edge detection
Rising edge detection
● Capture input control register (CIC0)
Figure 7.2-2 Capture input control register (CIC0)
bit
7
6
5
4
3
2
1
0
Initial value
RF1E
R/W
RF0E
R/W
CFGE
R/W
DFGE
R/W
EI2E
R/W
EI1E
R/W
EI0E
R/W
S0FT
W
0000 0000B
Address: 000065H
Access
Note:
Do not use the read modify write command on this register.
[bit7]:RF1E
It is DVRFG1 input control bit.
0
1
Input interdiction
Input permission
[bit6]:RF0E
It is DVRFG0 input control bit.
0
1
Input interdiction
Input permission
[bit5]:CFGE
It is DVCFG input control bit.
0
1
Input interdiction
Input permission
161
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 7 FRC Capture
[bit4]:DFGE
It is DVDFG input control bit.
0
1
Input interdiction
Input permission
[bit3]:EI2E
It is EXI2 input control bit.
0
1
Input interdiction
Input permission.
It is automatically to "0" by acceptance of capture request.
[bit2]:EI1E
It is EXI1 input control bit.
0
1
Input interdiction
Input permission.
It is automatically to "0" by acceptance of capture request.
[bit1]:EI0E
It is EXI0 input control bit.
0
1
Input interdiction
Input permission.
It is automatically to "0" by acceptance of capture request.
[bit0]:SOFT
It is software trigger generation bit.
0
1
None
Generate capture request.
The read value of this bit is always "0".
162
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Capture Control Register (CAPC)
Figure 7.2-3 Capture control register (CAPC)
bit
Address: 000067H
Access
7
6
5
4
3
2
1
0
INC
W
Initial value
FUL
R
EMP
R
CLR
W
---- 0100B
[bit7, 6, 5, 4]:
It is an unused bit.
[bit3]:FUL
It is FIFO full flag.
0
1
Status which affords to input the data to FIFO
Status of FIFO full
[bit2]:EMP
It is FIFO empty flag.
0
1
Status which data is remained in FIFO
Status of FIFO empty
[bit1]:CLR
It is FIFO clear control bit.
0
1
None
Clear FIFO.
The read value of this bit is always "0".
[bit0]:INC
It is FIFO output control bit.
0
1
None
Output next data on FIFO.
The read value of this bit is always "0".
163
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 7 FRC Capture
■ Capture Source Register (CAPS)
Figure 7.2-4 Capture source register (CAPS)
bit
7
6
5
4
3
2
1
0
Initial value
RFG1
RFG0
CFG
DFG
EXI2
EXI1
EXI0
S0FT
Address: 000068H
Access
XXXX XXXXB
R
R
R
R
R
R
R
R
These bits indicate the capture factors of the captured data.
When each bit is "1", it has a capture request.
When it is "0", it does not have a capture request.
■ Capture Data Registers (CAPD2 to 0)
Figure 7.2-5 Capture data register (CAPD2)
bit
7
6
5
4
3
2
1
0
Initial value
Address: 000069H
Access
XXXX XXXXB
CNT23
CNT22
CNT21 CNT20
CNT19
CNT18
CNT17 CNT16
R
R
R
R
R
R
R
R
Figure 7.2-6 Capture data register (CAPD1)
bit
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
Address: 00006AH
Access
CNT15
CNT14
CNT13 CNT12
CNT11 CNT10
CNT9
CNT8
R
R
R
R
R
R
R
R
Figure 7.2-7 Capture data register (CAPD0)
bit
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
CNT7
CNT6
CNT5
CNT4
CNT3
CNT2
CNT0
CNT0
Address: 00006BH
Access
R
R
R
R
R
R
R
R
These indicate the time that the capture request is generated.
■ FRC Count Data Register (FRCD2 to 0)
Figure 7.2-8 FRC count data register (FRCD2)
bit
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
CNT23
CNT22
CNT21 CNT20
CNT19 CNT18
CNT17
CNT16
Address: 000061H
Access
R
R
R
R
R
R
R
R
Figure 7.2-9 FRC count data register (FRCD1)
bit
7
6
5
4
3
2
1
0
Initial value
Address: 000062H
Access
XXXX XXXX
CNT15
CNT14 CNT13
CNT12
CNT11 CNT10
CNT9
CNT8
R
R
R
R
R
R
R
R
Figure 7.2-10 FRC count data register (FRCD0)
bit
Address: 000063H
Access
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
CNT7
CNT6
CNT5
CNT4
CNT3
CNT2
CNT0
CNT0
R
R
R
R
R
R
R
R
Reading this register enables the free run counter value (time) to be known.
164
Download from Www.Somanuals.com. All Manuals Search And Download.
7.3
Operation of FRC Capture
Up to eight capture data can be fetched in FIFO. If a new capture request is generated
while data is full, the former data will be updated with the new data.
If a capture request is generated while the FIFO storage is empty, overhead for a
maximum of "fch x 18 cycles" (10 cycles from the CIF set) will be generated until data
setup (readable status).
■ Controlling Method of FIFO
Latching the data in FIFO is performed the following procedure.
1. When EMP bit is "0", read the data.
2. Writes the INC bit to "1". Therefore, next data in FIFO is ready. (Maximum of fch x 5 cycles)
3. Checks the EMP bit and EMP=0: Returns to 2) to extract the following data. EMP=1: Completes all
data reading.
To initialize FIFO and dispose of data within FIFO storage, writing "1" to the FIFO clear bit initializes the
FIFO.
Figure 7.3-1 Operation timing diagram of FIFO
8 fch
Captuer request
Captuer Timing
CIF_bit
EMP_bit
Fifo Data
INC_bit Write
FCLR_bit Write
8 fch+
3 fch+
3 fch+
■ Capture Data
The lowest 3 bits of the capture data will be valid only when the DFG bit of the capture source register is
"1". When the DFG bit is "0", masks the lowest 3 bits after reading the capture data.
■ Reading of FRC Count Data
Use the word access command to read the counter data. When the half-word access command is read, after
reading the counter data subordinate, read the superior data.
Correct values cannot be read using byte access commands. The top byte read by the word access
command is invalid data, so execute mask processing.
165
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 7 FRC Capture
166
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 8 Programmable Pulse Generator (PPG0, 1)
8.1
Overview of Programmable Pulse Generator (PPG0, 1)
The programmable pulse generators (PPG0, 1) have built-in buffer RAM (PPG0: 256
bytes, PPG1: 64 bytes) and A/DC hard start function.
■ Feature of Programmable Pulse Generator (PPG0, 1)
•
•
•
Built-in buffer RAM (PPG0: 256 bytes, PPG1: 64 bytes)
Output timing precision 800 ns(@20 MHz)
Built-in A/D converter hard start function
■ Block Diagram of Programmable Pulse Generator (PPG0, 1)
Figure 8.1-1 Block diagram of programmable pulse generator (PPG0, 1)
from FRC
FRC3-19
PPG0 control unit
IRQ06 (to I-Unit)
PO19-23
PO0-18
to Internal logic unit
Data RAM 256 byte
PO15
to General - purpose Prescaler
P0-18O
to Port output unit
PO0-9
Data RAM 64 byte
PO10-15
to Internal logic
IRQ07 (to I-Unit)
PPG1 control unit
168
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure 8.1-2 Block diagram of programmable pulse generator (PPG0, 1)
Internal bus (Address-Bus)
Internal bus (R-Bus)
Internal bus (D-Bus)
PPGxTH, L
PPGxS A
Timing data register
Address setting
DataR AM
Load
EQ
Comparator
Address counter
FRC4-19
FRC3
Output timing latch
Comparator
Output data latch
Output data latch
Timing
control
Output pattern data latch
EQ.STB
R
PPG
output
Relativity counter
PO??
OVF
Q
R1
R2
S
IRQx
(to I-unit)
SQ
R
ST
IE
FCLR
IF
PPGxC
Internal bus (AD-Bus)
169
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 8 Programmable Pulse Generator (PPG0, 1)
■ Register List of Programmable Pulse Generator (PPG0, 1)
Figure 8.1-3 Register list of programmable pulse generator (PPG0, 1)
bit
7
0
Address:
00006CH
00006DH
00006EH
00006FH
PPG0TH
PPG0TL
PPG1TH
PPG1TH
PPG0 Timing data register
PPG1 Timing data register
000200H
0002FFH
RAM
PPG0 Data RAM
PPG1 Data RAM
256byte
000380H
RAM
64byte
0003BFH
0003C0H
0003C1H
0003C2H
0003C3H
0003C4H
0003C5H
0003C6H
0003C7H
PPG0C
PPG0 Control register
PPG0SA
PPG0 Start address setting register
PPG1C
PPG1 Control register
PPG1SA
PPG1 Start address setting register
170
Download from Www.Somanuals.com. All Manuals Search And Download.
8.2
Register of Programmable Pulse Generator (PPG0, 1)
The register configuration/functions of the programmable pulse generator (PPG0, 1) are
described.
■ PPGx Control Register (PPGxC)
Figure 8.2-1 PPGx control register (PPGxC)
bit
Address: 0003C0H (PPG0C)
0003C4H (PPG1C)
Access
7
6
5
4
3
2
1
0
Initial value
0000 X100B
Test
Test
Test
Test
IF
FCLR
IE
ST
R/W
R/W
R/W
R/W
R
W
R/W
R/W
[bit7 to 4]:Test
Please set "0".
[bit3]:IF
It is output timing data match interrupt request flag.
0
1
Not match
Match
[bit2]:FCLR
It is interrupt request flag clear bit.
0
1
Clear IF.
None
The read value of this bit is always "1".
[bit1]:IE
It is interrupt enable bit.
0
1
Interrupt interdiction
Interrupt permission
[bit0]:ST
It is PPG start bit.
0
1
PPG stop
PPG start
171
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 8 Programmable Pulse Generator (PPG0, 1)
■ Timing Data Register (PPGxT)
Figure 8.2-2 Timing data register (PPGxTH)
bit
Address: 00006CH (PPG0TH)
00006EH (PPG1TH)
Access
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
D15
D14
D13
D12
D11
D10
D09
D08
W
W
W
W
W
W
W
W
Figure 8.2-3 Timing data register (PPGxTL)
bit
Address: 00006DH (PPG0TL)
00006FH (PPG1TL)
Access
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
D07
D06
D05
D04
D03
D02
D01
D00
W
W
W
W
W
W
W
W
When the timing data register is updated continuously, write new data after 18/fch or more has passed after
writing.
Do not use the byte access command to access the register.
■ Start Address Setting Register (PPGxSA)
Figure 8.2-4 Start address setting register (PPGxSA)
bit
Address: 0003C1H (PPG0SA)
0003C5H (PPG1SA)
Access
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
A7/SA7
A6/SA6
A3/SA3
A2/SA2
A5/SA5 A4/SA4
R/W R/W
A1/SA1 A0/SA0
R/W R/W
R/W
R/W
R/W
R/W
[bit7 to 0]:A7 to 0
The set address will be the PPG output starting frame data address, and the read value will be the frame
data address to be output next.
Table 8.2-1 Relationship between start address and data RAM
Data RAM Address
Set value
PPG0
PPG1
00H
02H
04H
000200H
000202H
000204H
000380H
000382H
000384H
to
to
3CH
00023CH
0003BCH
3EH
40H
42H
44H
00023EH
000240H
000242H
000244H
0003BEH
-
-
to
to
-
-
FCH
0002FCH
FEH
0002FEH
172
Download from Www.Somanuals.com. All Manuals Search And Download.
8.3
PPG Data RAM
This section shows the relationship between the PPG data RAM and frame.
■ Relationship between PPG Data RAM and Frame
Figure 8.3-1 Relationship between PPG data RAM and frame
MSB
LSB
RAM Address PPGxSA
200H /380H
202H /382H
000H
002H
PPG1
PPG0
n+0H
n+2H
n+4H
n+6H
n+8H
n+AH
n+CH
Output timing data
Output puttern data 0
Output puttern data 1
Frame 1
Frame 1
Frame 2
Frame 3
Frame 2
2FFH /---
H
173
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 8 Programmable Pulse Generator (PPG0, 1)
8.4
Configuration of Frame Data
Each frame is made up of 2-byte length output timing data (OTD) that specifies the
output time and n x 2-byte length output pattern data (OPDx) that specifies the output
value.
In terms of the PPG0 frame configuration, 4 bytes (32 bits) of output pattern data exist,
which is a 6 bytes per frame configuration; and for PPG1, 2 bytes (16 bits) of output
pattern data exist, which is a 4 bytes per frame configuration.
■ PPG0 Frame Data
Figure 8.4-1 PPG0 Frame data
7
6
5
4
3
2
1
0
TD15 TD14 TD13 TD12
TD07 TD06 TD05 TD04
TD11 TD10
TD03 TD02
TD09 TD08
TD01 TD00
OD31 OD30 OD29 OD28 OD27 OD26 OD25 OD24
OD23 OD22 OD21 OD20 OD19 OD18 OD17 OD16
OD15 OD14 OD13 OD12 OD11 OD10 OD09 OD08
OD07 OD06 OD05 OD04 OD03 OD02 OD01 OD00
[OD31-29]: Unused
[OD 28 ]: PPG0 interrupt control
[OD 27 ]: A/DC Start control (ADST0)
[OD26-24]: A/DC Channel control
[OD23-19]: Unused
[OD18-16]: PO018-016 Output data
[OD 15 ]: PO015, Update timing output data of General - purpose prescaler
[OD14-00]: PO014-000 Output data
[TD15-0]: Output timing data
■ PPG1 Frame Data
Figure 8.4-2 PPG1 Frame data
7
6
5
4
3
2
1
0
TD15 TD14 TD13 TD12
TD07 TD06 TD05 TD04
TD11 TD10
TD03 TD02
TD09 TD08
TD01 TD00
OD15 OD14 OD13 OD12 OD11 OD10 OD09 OD08
OD07 OD06 OD05 OD04 OD03 OD02 OD01 OD00
[OD 15 ]: Unused
[OD 14 ]: PPG1 Interrupt control
[OD 13 ]: A/DC Start control (ADST1)
[OD12-10]: Unused
[OD09-00]:PO109-100 Output data
[TD15-0]: Output timing data
174
Download from Www.Somanuals.com. All Manuals Search And Download.
8.5
Operation of PPG
The operation of PPG has output and start operation.
■ Output Operation of PPG
Clears the relative counter when the values set to the timing data register (PPGxTH, PPGxTL) and the FRC
value match, and after loading the value of the address set register to the memory address counter, retains
the 1st field data of data RAM (output timing data, output data) in the output timing data latch and output
data latch.
The retained output data is transferred to the output latch by the rising edge of the relative counter clock
under the cycle whose relative counter and output timing data match, and the 2nd field data is newly
retained in each latch.
Figure 8.5-1 Output operation of PPG
Data RAM
(OTD)
Output timing data latch
Comparator
Output data latch (ODLH)
Output data latch (ODLL)
Relativity counter
FRC3
Output latch (OUTH)
Output latch (OUTL)
FRC.EQ.TD
PPG Output
Figure 8.5-2 PPG output detail timing
(FRC3=24/fch, 0.8us:fch=@20MHz)
FRC3
FRC. EQ. TD
0
1
2
3
4
5
6
7
8
9
RAM Relativity addr
Relativity counter
CNT. EQ. OTD
X
XXXX
0000
0001
0002
OTD
TX (XXXX)
T0 (0000)
Tn (nnnn)
ODLH
ODLL
OUTL
ODL (TX)
ODL (T0)
ODH (T0)
ODL (Tn)
ODH (Tn)
ODH (TX)
OUT (TX-1)
OUT (T0)
175
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 8 Programmable Pulse Generator (PPG0, 1)
Figure 8.5-3 Operation timing of PPG
FRC3
FC4-19R
FRC. EQ. TD
Relativity
counter value
XX
XX
00
01
02
03
04
05
06
07
00
01
02
03
CNT. EQ. OTD
PPG.OUT
PPG.IEN
IRQ.STB
IFlag
F1
F2
FX
F1
Wclr
■ Start Operation of PPG
The PPG starts operation by setting "1" to the start bit. The initial operation is performed as follow.
•
•
•
Clears the relative counter and loads the initial address in synchronization with the falling edge of the
FRC clock after starting.
Reads the frame data indicated by the initial address, sets data to each latch of OTD and ODL, and the
status will be compare match wait for the OTD value and relative counter value.
When compare match is detected, transfers the ODL value to the output latch (OUTL) in
synchronization with rising edge of the FRC clock, reads the next frame data, then updates each latch
value of OTD and ODL, while the status is compare match wait. (This operation is performed
repeatedly.)
■ Update Timing Data Register
When timing data is updated during PPG operation, the next data should be written after FRC3 x 2 or
longer has passed after writing the register.
■ Precaution when Clear IF Flag
Do not perform clearing of IF flag and interrupt enable (IE=1) concurrently. Enables interrupts after
clearing the IF flag.
176
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 9 Real Timing Generator (RTG)
9.1
Overview of Real Timing Generator (RTG)
The real timing generator (RTG) has 3 built-in circuits, namely real timing generators 0
to 2 (RTG0 to 2).
■ Feature of Real Timing Generator (RTG)
•
•
•
Contain 3 RTG circuit
Output timing accuracy selectable 400 ns/800 ns
5 timing outputs
■ Block Diagram of Real Timing Generator (RTG)
Figure 9.1-1 Block diagram of real timing generator (RTG)
IRQ08 (toI-Unit)
RTG0
RTG0
RTG0
RTO04-00
RTO14-10
RTO24-20
ADST
ADST
(to A/DC)
ADST
RTG Output
(to Port unit)
RTO4-0
IRQ09 (toI-Unit)
ADST
IRQ10 (toI-Unit)
FRC2-19
178
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure 9.1-2 Block diagram of real timing generator (RTG)
Internal bus
EMP
FUL
CLR
TSEL
OUTE
IE
FCLR
IF
RTGxC
R Q
IRQx
(to I-unit)
S
Output Disable
FRC2-19
RTG2,3 Timing Select
MPX
Comparator
EQ
ADSTx
RTOx4
Fi fo-o ut
RTG0x4-0
Output
R
(to MPX)
16bit
5bit
Fifo
Control
Fifo-in
Write STB
Internal bus
179
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 9 Real Timing Generator (RTG)
■ Register List of Real Timing Generator (RTG)
Figure 9.1-3 Register list of Real Timing Generator (RTG)
bit
7
0
Address:
000034H
000035H
000036H
000037H
RTG0 Control register
RTG0C
RTG0D
RTG0TH
RTG0TL
RTG0 Output data register
RTG0 Timing data register
000038H
000039H
00003AH
00003BH
RTG1C
RTG1D
RTG1TH
RTG1TL
RTG1 Control registe
RTG1 Output data register
RTG1 Timing data register
RTG2 Control registe
00003CH
00003DH
00003EH
00003FH
RTG2C
RTG2D
RTG2TH
RTG2TL
RTG2 Output data register
RTG2 Timing data register
180
Download from Www.Somanuals.com. All Manuals Search And Download.
9.2
Register of Real Timing Generator (RTG)
The register configuration/functions of the real timing generator (RTG) are described.
■ RTGx Control Register (RTGxC)
Figure 9.2-1 RTGx Control Register (RTGxC)
bit
Address: 000034H (RTG0C)
000038H (RTG1C)
00003CH (RTG2C)
Access
7
6
5
4
3
2
1
0
Initial value
X100 0001B
IF
FCLR
IE
OUTE
TSEL
CLR
FUL
EMP
R
W
R/W
R/W
R/W
W
R
R
[bit7]:IF
It is output timing data match interrupt request flag.
0
1
Not match
Match
[bit6]:FCLR
It is interrupt request flag clear bit.
0
1
Clear IF.
None
The read value of this bit is always "1".
[bit5]:IE
It is interrupt enable bit.
0
1
Interrupt interdiction
Interrupt permission
[bit4]:OUTE
It is output enable bit.
0
1
RTG output interdiction (Low output fixed)
RTG output enable
[bit3]:TSEL
It is timing accuracy selection bit of RTG section (RTG0 to 2).
0
1
400 ns accuracy (in fch=@20 MHz)
800 ns accuracy (in fch=@20 MHz)
181
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 9 Real Timing Generator (RTG)
This bit exists with the RTG0 only, and it affects the timing accuracy of all RTGs.
[bit2]:CLR
It is FIFO initialization bit.
0
1
None
Clear FIFO.
The read value of this bit is always "0".
[bit1]:FUL
It is FIFO full flag.
0
1
FIFO empty status
FIFO full status
[bit0]:EMP
It is FIFO empty flag.
0
1
Data is remained in FIFO
FIFO empty status
■ Output Data Register (RTGxD)
Figure 9.2-2 Output data register (RTGxD)
bit
Address: 000035H (RTG0D)
000039H (RTG1D)
00003DH (RTG2D)
Access
7
6
5
4
3
2
1
0
Initial value
OD4
OD3
OD2
OD1
OD0
---X XXXXB
R/W
R/W
R/W
R/W
R/W
Data written to this register will be the RTG output data. Reading value is read that the RTG is current
output data. In terms of the RTG output, the value logically added (OR) per bit of each channel is output.
■ Timing Data Register (RTGxT)
Figure 9.2-3 Timing data register (RTGxT)
bit
Address: 000036H (RTG0TH)
00003AH (RTG1TH)
00003EH (RTG2TH)
Access
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
D15
D14
D13
D12
D11
D10
D09
D08
W
W
W
W
W
W
W
W
bit
Address: 000037H (RTG0TL)
00003BH (RTG1TL)
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
D07
D06
D05
D04
D03
D02
D01
D00
00003FH (RTG2TL)
Access
W
W
W
W
W
W
W
W
It is a register to set the output time of the RTG output. Writing this register sets the value set by the output
data register in FIFO format.
182
Download from Www.Somanuals.com. All Manuals Search And Download.
9.3
Operation of Real Timing Generator (RTG)
Initiation procedure of the real timing generator (RTG) and RTG output timing are
described.
■ Initiation Procedure of Real Timing Generator (RTG)
1. Performs the initialization of control register.
2. Set the output data to RTGxD. In this case, do not use the command with RMW.
3. Set the output time to RTGxTH, L. In this case, the output data set by 2) is transferred to FIFO and EMP
flag becomes 0. 3 machine cycles are required for the EMP flag to be determined after setting the output
time. So if the flag is to be checked immediately after setting the output time, test should be carried out
after executing dummy read, etc.
Notes:
•
•
•
Do not use word access commands to set the output data and output time.
Use half-word access commands to set the output time.
Prior to setting up the output time, set up the output data.
Figure 9.3-1 Operation timing of FIFO
RTGxT write
Out Data
Fifo 1st
XXXX
XXXX
XXXX
T0001
T0001
T0001
T0002
T0002
T0001
T0003
T0003
Fifo 2nd
T0003
T0001
EMP flag
FUL flag
RTG Output
XXXX
3 Machine cycle (3 x φ)
■ RTG Output Timing
Figure 9.3-2 Output timing of RTG
FRC2/3
FRC value
CMP latch
FFFF
0000
0000
0000
0003
nnnn
0003
nnnn
FRC. EQ. TD
Output timing
RTG Output
OUT(T0)
183
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 9 Real Timing Generator (RTG)
184
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 10 Timer
10.1
Overview of Timer
The timer section comprises of a 16-bit timer and 8-/16-bit timer/counter.
■ Feature of Timer
•
•
•
16-bit x 4ch
16-bit timer/counter x 1ch (with square wave output)
8-/16-bit timer/counter x 1ch (with square wave output)
■ Configuration of Timer
Figure 10.1-1 Block diagram of Timer
16bit Timer
FRC
from FRC
Timer 0
IRQ15
IRQ16
IRQ17
IRQ18
16bit Timer
Timer 1
16bit Timer
Timer 2
16bit Timer
Timer 3
16bit Timer
EC4
EC5
T4O
IRQ14
Timer 4
8/16bit Timer/Counter
8bit Timer0
8bit Timer1
T5O1
IRQ13
Timer 5
IRQ12
186
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Register List of Timer
Figure 10.1-2 Register list of Timer
bit
15
87
0
Address: 000070H
000072H
000074H
000076H
000078H
00007AH
00007CH
00007EH
000080H
000082H
000084H
000086H
000088H
00008AH
00008CH
00008EH
000090H
000092H
T0CD
T0DR
T0CR
T1CR
T1CD
T1DR
T2CD
T2DR
T2CR
T3CR
T3CD
T3DR
T4CD
T4DR
T4CR
Timer 0 (16 bit Timer)
Timer 1 (16 bit Timer)
Timer 2 (16 bit Timer)
Timer 3 (16 bit Timer)
Timer 4 (16 bit Timer)
Timer 5 (16 bit Timer)
T5CR1
T5DR1
T5CD1
T5CR0
T5DR0
T5CD0
187
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 10 Timer
10.2
Overview of 16-bit Timer (Timer 0 to 4)
16-bit timer (timer 0 to 4) can be select from 4 clocks.
■ Block Diagram of 16-bit Timer (Timer 0 to 4)
Figure 10.2-1 Block diagram of 16-bit timer (Timer 0 to 4)
Internal Bus
TxCRL
TSTR
TC0
TC1
LFLG LREQ
Q
S
R
DQ
TxO
QX
TSTR
TxDRL
TxDRH
Data Register
TxCRH
TIE
FCLR IFLG
Load
Compare Data Lach
Comparater
IRQx
R
S
Q
EQ
TxCDL
TxCDH
CLR
CK0
CK3
16bit Counter
M
P
X
CK
188
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Register List of 16-bit Timer (Timer 0 to 4)
Figure 10.2-2 Register list of 16-bit timer (timer 0 to 4)
15 87
bit
0
T0CDH
T0DRH
T0CRH
T1CRH
T1CDH
T1DRH
T2CDH
T2DRH
T2CRH
T3CRH
T3CDH
T3DRH
T4CDH
T4DRH
T4CRH
T0CDL
T0DRL
T0CRL
T1CRL
T1CDL
T1DRL
T2CDL
T2DRL
T2CRL
T3CRL
T3CDL
T3DRL
T4CDL
T4DRL
T4CRL
Timer 0 Count Data Register
Timer 0 Data Register
Address
000070H
000072H
000074H
000076H
000078H
00007AH
00007CH
00007EH
000080H
000082H
000084H
000086H
000088H
00008AH
00008CH
Timer 0 Control Register
Timer 1 Control Register
Timer 1 Count Data Register
Timer 1 Data Register
Timer 2 Count Data Register
Timer 2 Data Register
Timer 2 Control Register
Timer 3 Control Register
Timer 3 Count Data Register
Timer 3 Data Register
Timer 4 Count Data Register
Timer 4 Data Register
Timer 4 Control Register
189
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 10 Timer
10.3
Register of 16-bit Timer (Timer 0 to 4)
Register configuration/functions of 16-bit timer (timer 0 to 4) is shown.
■ Timer Control Register L (TxCRL)
Figure 10.3-1 Timer control register L (TxCRL)
bit
7
6
5
4
3
LFLG
R
2
1
0
Initial value
---0 0000B
LREQ
R/W
TC1
R/W
TC0
R/W
TSTR
R/W
Access
[bit7 to 5]:
It is an unused bit.
[bit4]:LREQ
It is timer data load request bit.
0
1
None
Load request is performed timer data to compare latch and output
compare data to output latch.
Always read "0" at reading.
[bit3]:LFLG
It is timer data load complete flag bit.
0
1
Timer data load complete.
Timer data load does not complete.
[bit2]:TC1
[bit1]:TC0
There are clock source selection bit. Timer 0 to 4 is as follow.
Table 10.3-1 Timer 0 to 3
Clock cycle time
(fch:@20MHz)
TC1
TC0
Selection Clock
24/fch (FRC3)
0
0
1
1
0
1
0
1
0.8 µs
26/fch (FRC5)
28/fch (FRC7)
210/fch (FRC9)
3.2 µs
Internal clock
12.8 µs
51.2 µs
190
Download from Www.Somanuals.com. All Manuals Search And Download.
Table 10.3-2 Timer 4
Clock cycle time
(fch:@20 MHz)
TC1
TC0
Selection Clock
24/fch (FRC3)
0
0
1
1
0
1
0
1
0.8 µs
3.2 µs
26/fch (FRC5)
Internal clock
28/fch (FRC7)
EC4
12.8 µs
External clock
Min ***** µs
*:fch: source oscillation frequency
[bit0]:TSTR
Table 10.3-3 Timer operation enable bit
0
1
Timer operation stop
Enabling timer Operation
■ Timer Control Register H (TxCRH)
Figure 10.3-2 Timer control register H (TxCRH)
bit
7
6
5
4
3
2
1
IFLG
R
0
Initial value
0--- -1X0B
Test
R/W
FCLR
R/W
TIE
R/W
Access
[bit7]:Test
It is for a test.
Always write "0" to this bit.
[bit6-3]:
It is an unused bit.
[bit2]:FCLR
It is match detection flag clear bit.
0
1
Clear match detection flag.
None
Always read "1" at reading.
191
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 10 Timer
[bit1]:IFLG
It is match detection flag.
0
1
No match detection
Match detection
[bit0]:TIE
It is interrupt enable bit.
0
1
Interrupt interdiction
Interrupt permission
■ Timer Data Register H, L (TxDRH, TxDRL)
Figure 10.3-3 Timer data register H, L (TxDRH, TxDRL)
bit
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The counter is cleared by the register that sets the value to be compared with the counter value when
matched with the counter value.
■ Timer Count Register H, L (TxCDH, TxCDL)
Figure 10.3-4 Timer count register H, L (TxCDH, TxCDL)
bit
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
Access
R
R
R
R
R
R
R
R
bit
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
Access
R
R
R
R
R
R
R
R
192
Download from Www.Somanuals.com. All Manuals Search And Download.
10.4
Operation of 16-bit Timer (Timer 0 to 4)
In terms of the 16-bit timer, the internal clock can be selected from four types by setting
the clock source selection bit (TC1, TC0) of the timer control register (TxCRL). The timer
data register (TxDRH, TxDRL) will be the one used for setting the interval time, and
reading the timer count data register (TxCDH, TxCDL) enables the timer count value to
be known.
■ Operation of 16-bit Timer (Timer 0 to 4)
When the timer starts up, counting begins after the counter is cleared to "0000H" by writing "1" to the timer
start bit (TSTR) of the timer control register "L" after setting the interval time to the timer data register. The
compare latch of the timer data register is loaded immediately after writing if the timer is suspended.
Matching the counter value with the set value of the compare latch sets the match detection flag (IFLG) to
"1". In this case, the counter is cleared to "0000H" if the load request flag is set, the data register value is
loaded to the compare latch, and counting continues. In terms of the interval time "T", when "n" is selected
as the data register set value, and "φ" is selected as the selection clock, the interval time "T" becomes
below.
T= Φ × (n+1)
The toggle output frequency fTO is as follow.
fTO=1/{Φ × (n+1) × 2}
Figure 10.4-1 Operation of 16-bit timer
EQ
EQ
EQ
Counter clear
data setting value
Compare latch
Count value
0000H
TSTR
LFLG
LREQ=1(W)
LREQ=1(W)
FCLR=0(W)
IFLG
TxO
FCLR=0(W)
FCLR=0(W)
193
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 10 Timer
■ External Clock Mode (Only Timer 4)
The external clock input is selected as the external clock mode by the clock source selection bit (TC1, TC0)
of the timer control register (T4CR).
In order to start up the timer, writing "1" to the T4CR timer start bit (TSTR) clears the counter, and then
counting starts. The number of events can be found by reading the count data register (T4CD).
Figure 10.4-2 External Clock Mode operation
EC4
TSTR=1
TADR
7FH
7FH
FFH
55H
Compare latch
Counter clear
FFH
00H
Indeter-
01H
00
00H
01H
02H
03H
7EH
7FH
minate
Count value
IFLG
FCLR=0(W)
194
Download from Www.Somanuals.com. All Manuals Search And Download.
10.5
Overview of 8-/16-bit Timer/Counter
3 internal and 1 external clock input can be selected.
■ Feature of 8-/16-bit Timer/Counter
•
•
•
•
3 internal and 1 external clock input can be selected.
Usable as an 8-bit timer/counter and 8-bit timer under 8-bit 2ch mode.
Usable as 16-bit timer/counter under 16-bit mode.
Square wave output function
■ Block Diagram of 8-/16-bit Timer/Counter
Figure 10.5-1 Block diagram of 8-/16-bit Timer/Counter
TxCR0 TSTR0 TCS00 TCS01 TCS02 CINV TIE0 TFCR0 TIF0
R
S
IRQxx
I-unit
(from FRC)
CK00
DQ
TxO0
Unused
QX
M
P
X
CK
CLR
8bit Counter Low
Comparator Low
TSTR0
CK02
EC5
EQ
LOAD Comparate data latch
Data Register Low
TxDR0
Count Data Reg Low
TxCD0
TxDR1
TxCD1
Data Register Hi
Count Data Reg Hi
LOAD Comparate data latch
EQ
Comparator Hi
(from FRC)
CK10
CLR
CK
8bit Counter Hi
M
P
X
TxO1
(T5O1)
DQ
QX
CK12
8bit Mode
TSTR0
/TSTR1
IRQxx
(I-unit)
R
S
TxCR1 TSTR1 TCS10 TCS11 TCS12
TIE1 TFCR1 TIF1
195
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 10 Timer
■ Register List of 8-/16-bit Timer/Counter
Figure 10.5-2 Register list of 8-/16-bit Timer/Counter
15 87
bit
0
Address:
00008EH
000090H
000092H
TxCR1
TxDR1
TxCD1
TxCR0
TxDR0
TxCD0
Timer Control Register 1,0
Timer Data Register 1,0
Count Data Register 1,0
196
Download from Www.Somanuals.com. All Manuals Search And Download.
10.6
Register of 8-/16-bit Timer/Counter
Register configuration/functions of 8-/16-bit timer/counter is shown.
■ Timer Control Register 1 (TxCR1)
Figure 10.6-1 Timer control register 1(TxCR1)
bit
7
6
5
4
3
2
1
0
Initial value
010- 0000B
TIF1
TFCR1
TIE1
TCS12
TCS11 TCS10
R/W R/W
TSTR1
Access
R
W
R/W
R/W
R/W
[bit7]:TIF1
It is compare match detection flag bit.
0
1
Compare match does not generate.
Compare match generates.
[bit6]:TFCR1
It is compare match detection flag clear bit.
0
1
Clear compare match detection flag.
None
The read value of this bit is always "1".
[bit5]:TIE1
It is interrupt enable bit of timer 1.
0
1
Interdiction
Permission
[bit4]:
It is an unused bit.
[bit3]:TCS12
[bit2]:TCS11
197
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 10 Timer
[bit1]:TCS10
It is clock source selection bit of timer.
TCS12
TCS11
TCS10
Selection Clock
source
in fch = @20 MHz
2 4/fch (FRC3)
2 6/fch (FRC5)
2 8/fch (FRC7)
0
0
0
0
0
1
0
1
0
0.8 µs
3.2 µs
12.8 µs
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Setting disabled
16-bit mode
-
[bit0]:TSTR1
It is timer start bit.
0
1
Operation stop
Clear counter and start operation.
■ Timer Control Register 0 (TxCR0)
Figure 10.6-2 Timer control register 0 (TxCR0)
bit
7
6
5
4
3
2
1
0
Initial value
CINV
0100 0000B
TIF0
TFCR0
TIE0
TCS02
TCS01 TCS00
TSTR0
Access
R
W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7]:TIF0
It is compare match detection flag bit.
0
1
Compare match does not generate.
Compare match generates.
[bit6]:TFCR0
It is compare match detection flag clear bit.
0
1
Clear compare match detection flag.
None
The read value of this bit is always "1".
198
Download from Www.Somanuals.com. All Manuals Search And Download.
[bit5]:TIE0
It is interrupt enable bit of timer 0.
0
1
Interdiction
Permission
[bit4]:CINV
It is count clock reverse bit.
0
Count up by falling of selection clock source.
Count up rising of selection clock source.
1
[bit3]:TCS02
[bit2]:TCS01
[bit0]:TCS00
It is clock source selection bit.
TCS02
TCS01
TCS00
Selection Clock
source
in fch = @20 MHz
2 4/fch (FRC3)
2 6/fch (FRC5)
2 8/fch (FRC7)
0
0
0
0
0
1
0
1
0
0.8 µs
3.2 µs
12.8 µs
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Setting disabled
External Clock Mode
-
[bit0]:TSTR0
It is timer start bit.
0
1
Operation stop
Clear counter and start operation.
199
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 10 Timer
■ Timer Data Register 1, 0 (TxDR1, TxDR0)
Figure 10.6-3 Timer data register 1, 0 (TxDR1, TxDR0)
bit
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The timer data register value is loaded to the compare latch, and used as data compared to the counter
value. Use the setting of the interval time under the timer mode. Also used to set the number of events to be
detected under the external clock mode.
■ Count Data Register (TxCD1, TxCD0)
Figure 10.6-4 Count data register (TxCD1, TxCD0)
bit
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
Access
R
R
R
R
R
R
R
R
bit
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
Access
R
R
R
R
R
R
R
R
Read operation under the timer/counter mode reads the counter value.
200
Download from Www.Somanuals.com. All Manuals Search And Download.
10.7
Operation of 8-/16-bit Timer/Counter
In terms of 8-/16-bit timer/counter operations, there are controls for the 8-bit internal
clock mode, 8-bit external clock mode (event counter), and 16-bit mode.
■ Operation in 8-bit Internal Clock Mode
In terms of the 8-bit internal clock mode, the internal clock can be selected from seven types by setting the
clock source selection bit (TCS02, TCS01, TCS00) (TCS12, TCS11, TCS10) of the timer control register
0, 1 (TxCR0, TxCR1). The timer data register 0, 1 (TxDR0, TxDR1) will be the register for setting the
interval time.
When the timer starts up, writing "1" to the timer start bit (TSTR0, TSTR1) of the timer control register
after setting the interval time to the data register clears the counter to "00H", and loads the data register
value to the compare latch. Then counting starts.
When the counter value matches the compare latch value, "1" is set as the compare match detection flag
(TIF0, TIF1). In this case, the counter is cleared to "00H", and the data register value is reloaded to the
compare latch, and counting continues. Also, the toggle output (TxOx) reverses the output per compare
match.
When "n" is selected as the data register set value, and "Φ" is selected as the selection clock, the interval
time "T" becomes below.
T = Φ × (n+1)
The toggle output frequency fTO is as follow.
fTO=1/{Φ × (n+1) × 2}
Figure 10.7-1 Operation of Internal clock mode
EQ
EQ
EQ
Counter clear
Data setting value
Compare latch
Count value
0000H
TSTRx
TIFx
TFCRx=0(W)
TFCRx=0(W)
TFCRx=0(W)
TxOx
■ Operation of 8-bit External Clock Mode (Event Counter)
The external clock mode is used to select the external clock input using the clock source selection bit
(TCS02, TCS01, TCS00) of the timer control register 0 (TxCR0).
In order to start up the timer, writing "1" to the TxCR0 timer start bit (TSTR0) clears the counter, and then
counting starts. The number of events can be found by reading the count data register (TxCDL).
201
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 10 Timer
Figure 10.7-2 Operation of external Clock Mode
ECx
TSTR0=1
TxDR0
7F
7F
H
H
FF
H
55
H
Compare latch
Counter clear
FF
H
Indeter-
00H
01H
00
00
H
01
H
02
H
03
H
7E
H
7F
H
minate
Count value
TIF0
TFCR0=0(W)
■ Control in 16-bit Mode
The 16-bit mode can be used as the 16-bit timer/counter in the same way as the 8-bit mode by setting each
Figure 10.7-3 Control in 16-bit mode
bit
7
6
5
4
3
2
1
0
TxCR1
TIF1
TFCLR1
TIE1
TCS12
TCS11 TCS10
TSTR1
No relation
Set ot 0
5
Set to 111
Set ot 0
0
bit
7
6
4
3
2
1
TxCR0
TIF0
TFCLR0
TIE0
CINV
TCS02
TCS01
TCS00
TSTR0
Flag
Clock polling
Clock select
Start/Stop
In terms of the 16-bit mode setting, set "111" to the TCS12, TCS11, and TCS10 bits of timer control
register 1 (TxCR1).
In the 16-bit mode, timers are controlled by the timer control register 0 (TxCR0). As regards the data
register in this case, TxDR1 is the superior byte and TxDR0 is the subordinate byte. For the count data
register, TxCD1 is the superior byte and TxCD0 is the subordinate byte.
The selection of the clock source is performed in the TCS02, TCS01, and TCS00 bits of TxCR0. In order to
start the timer, writing "1" to the TSTR0 bit of TxCR0 clears the counter, and counting starts.
When the counter value matches the compare latch value, the TIF0 bit of TxCR0 is set to "1". As above,
under 16-bit mode, the timer 0 side function can be used as it is in the extended 16-bit format.
Refer to the "■Operation in 8-bit Internal Clock Mode, Operation of 8-bit external clock mode (Event
counter)" for operations under 16-bit mode.
202
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 11 12-bit PWM
11.1
Overview of 12-bit PWM
The 12-bit PWM has a 12-bit resolution using the duty control and added pulse based
on the selectable basic frequency.
■ Feature of 12-bit PWM
•
12-bit resolution (rate, multi-type)
•
The conversion cycle can be selected: 0.2 ms/basic frequency 78.1 kHz (in fch:@20 MHz) and 0.4 ms/
basic frequency 39.0 kHz (in fch:@20 MHz).
■ Block Diagram of 12-bit PWM
Figure 11.1-1 Block Diagram of 12-bit PWM
M
P
X
1/fch
2/fch
8bit Counter
4bit Counter
OVF
EQ
8bit Comp
8bit Latch
4bit Comp
4bit Latch
M
P
X
PWMx0
Output
R Q
S
DQ
PWMx0L
PWMx0H
Data Reg Low
Data Reg Hi
PWMx1
Output
PWMx2
Output
Q R
Load
S
Test
STR
CKS LFLG LREQ PWMxC
Internal Bus
204
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Register list of 12-bit PWM
Figure 11.1-2 Register list of 12-bit PWM
15 87
bit
0
PWM0C
PWM00L
PWM01L
PWM02L
PWM1C
PWM10L
PWM11L
PWM12L
PWM0 Control Register
PWM00 Data Register
PWM01 Data Register
PWM02 Data Register
PWM1 Control Register
PWM10 Data Register
PWM11 Data Register
PWM12 Data Register
Address:
000040H
000042H
000044H
000046H
000048H
00004AH
00004CH
00004EH
PWM00H
PWM01H
PWM02H
PWM10H
PWM11H
PWM12H
205
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 11 12-bit PWM
11.2
Register of 12-bit PWM
Register configuration/functions of 12-bit PWM is shown.
■ PWMx Control Register (PWMxC)
Figure 11.2-1 PWMx Control Register (PWMxC)
bit
7
6
5
4
3
2
1
LFLG
R
0
Initial value
0--- 00X0B
Test
R/W
STR
R/W
CKS
R/W
LREQ
W
Access
[bit7]:Test
Please set "0".
[bit6 to 4]:
It is an unused bit.
[bit3]:STR
It is PWM operation enable bit.
0
1
Operation disabled
Operation enabled
[bit2]:CKS
It is clock select bit.
0
1
1/fch (fch: 50 ns in @20 MHz)
2/fch (fch: 100 ns in @20 MHz)
[bit1]:LFLG
It is load request flag to compare latch.
0
1
No load request and complete load.
Load request
[bit0]:LREQ
It is load request bit.
0
1
None
Load data register value to compare latch.
The read value of this bit is always "0".
206
Download from Www.Somanuals.com. All Manuals Search And Download.
■ PWMx0 to 2 Data Register (PWMDxx)
Figure 11.2-2 PWMx0 to 2 Data Register (PWMDxx)
bit
7
6
5
4
3
2
1
0
Initial value
---- XXXXB
D11
W
D10
W
D9
W
D8
W
Access
bit
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
D7
W
D6
W
D5
W
D4
W
D3
W
D2
W
D1
W
D0
W
Access
[bit11 to 4]:D11 to 4
It is duty control bit.
Control duty of basic frequency.
[bit3 to 0]:D3 to 0
It is added pulse control bit.
Control position of added pulse.
Use the half-word access command to write to this register.
(Byte access command cannot be write.)
207
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 11 12-bit PWM
11.3
Operation of 12-bit PWM
The 12-bit PWM acquires a 12-bit resolution by inserting added pulse to the output
waveform using the 8-bit and 4-bit counters.
■ Operation of 12-bit PWM
The 12-bit PWM is operated by the 8-bit and 4-bit counters. The 8-bit counter will be the basic frequency
at the time of PWM conversion, and output waveform duty is specified by the duty control-bit of the data
register. In terms of the conversion operation, this is repeated 16 times, and 12-bit resolution is acquired by
inserting an added pulse to the specific position during repeated operation. Insertion position of the added
pulse is specified by the added pulse control bit.
The PWM output waveform will be as Figure 11.3-1 .
Figure 11.3-1 PWM operation waveform
1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16
Convert cycle
Add Pulse
Basic frequency
fch/28 or fch/29
A pulse is added when "1" is specified in accordance with the added pulse control bit value.
Table 11.3-1 Pulse Insert Position
DATA
0000B
0001B
0010B
0011B
0100B
0101B
0110B
0111B
1000B
1001B
1010B
1011B
1100B
1101B
1110B
1111B
Insertion position of added pulse
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
-
-
-
1
1
-
-
-
-
-
-
-
1
1
-
-
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
1
1
1
1
-
-
-
1
1
1
1
-
-
-
1
1
1
1
-
-
-
1
1
1
1
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
1
1
-
-
-
-
-
1
1
-
-
-
-
-
-
-
1
-
-
-
-
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
-
-
1
-
-
-
-
1
-
-
-
-
1
1
-
-
1
-
-
1
-
-
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
1
-
-
1
1
1
1
1
208
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Update procedure of PWM data
1. Waits for load completion when the load request flag (LFLG) is set.
2. Sets the set value to each data register and writes "1" to the load request bit (LREQ). →The load request
flag (LFLG) is set. Do not update the data when LFLG is 1. It may cause the malfunction.
3. When the load is completed, and the LFLG is cleared. (The load operation generates 1/interval period of
basic frequency.)
209
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 11 12-bit PWM
210
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 12 8-bit Pulse Width Counter
12.1
Overview of 8-bit Pulse Width Counter
The 8-bit pulse width counter measures the pulse width by 400 ns accuracy.
■ Feature of 8-bit Pulse Width Counter
•
Pulse width measurement accuracy 400 ns (in fch = @20 MHz)
•
Mask input function
■ Block Diagram of 8-bit Pulse Width Counter
Figure 12.1-1 Block Diagram of 8-bit pulse width counter
23/fch
FFH
8bit Counter
R
PMI
PMSK
Captuer Register
PWCD
Q S1
S2
R
ST MSKE CAPF CAPE PWCC
Internal Bus
■ Register List of 8-bit Pulse Width Counter
Figure 12.1-2 Register list of 8-bit pulse width counter
bit
Address: 000094H
000095H
7
0
PWC Control Register
PWC Data Register
PWCC
PWCD
212
Download from Www.Somanuals.com. All Manuals Search And Download.
12.2
Register of 8-bit Pulse Width Counter
The register configuration/functions of the 8-bit pulse width counter are mentioned.
■ PWC Control Register (PWCC)
Figure 12.2-1 PWC Control Register (PWCC)
bit
Address: 000094H
Access
7
6
5
4
3
2
1
0
Initial value
0--- 0X00B
Test
CAPE
CAPF
MSKE
ST
R/W
W
R
R/W
R/W
[bit7]:Test
It is test bit.
Please set "0".
[bit6 to 4]:
It is an unused bit.
[bit3]:CAPE
It is capture enable bit.
0
1
None
Clear CAPF bit and become capture enable status.
The read value of this bit is always "0".
[bit2]:CAPF
It is capture flag.
0
1
No capture data. Capture enable status
Capture data. Capture disable status
[bit1]:MSKE
It is mask (PMSK) input enable bit.
0
1
PMSK input interdiction
PMSK input permission
213
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 12 8-bit Pulse Width Counter
[bit0]:ST
It is PWC start bit.
0
1
PWC stop. CAPF is fixed "1".
PWC Operation
■ PWC Data Register (PWCD)
Figure 12.2-2 PWC data register (PWCD)
bit
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
Address: 000095H
Access
R
R
R
R
R
R
R
R
It is a register to store the measurement value of the pulse width.
214
Download from Www.Somanuals.com. All Manuals Search And Download.
12.3
Operation of 8-bit Pulse Width Counter
The pulse width counting operation of the 8-bit pulse width counter is described.
■ Pulse Input Mask Function
Pulse input (PMI) can be directly masked by the pulse mask input signal (PMSK).
In order to control PMI input by PMSK input, set "1" to the mask input enabled (MSKE) bit of the PWC
control register (PWCC) for PMSK input enabled status. Therefore, the PMI input can be controlled by the
PMSK input signal.
■ Pulse Width Count Operation
The PWC clears the counter value capture and counter at the rising edge of the PMI signal. The cleared
counter continues the counting operation as it is, and when the counter value becomes "FFH", counting
stops, and retains that status until detecting the rising edge of the next PMI input.
In terms of the capture operation, when the capture flag (CAPF) is "0" (enabled status), capture is executed,
whereas when CAPF is "1" (disabled status), capture is not executed. These operation shows in Figure
Figure 12.3-1 PWC operation
PMI Input
Edge
FFH
Count value
00H
xxH
nnH
FFH
PWCD
CAP.Disable
CAP.Enable
CAPF
CAPE Write
■ CAPF Bit
The PWC initializes the CAPF bit to "1", when the ST bit is "0". In this case, do not clear the CAPF bit
during the operation is stopped.
Clearing the CAPF bit must be executed after enabling the PWC operation.
215
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 12 8-bit Pulse Width Counter
216
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 13
External Interrupt
External interrupt comprises of the key input interrupt
and external interrupt sections. This chapter describes
an outline of the external interrupt 1 (key input circuit)
and external interrupt (INT0 to 2), and the register
configuration/functions, and their operation.
217
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 13 External Interrupt
13.1
Overview of External Interrupt
External interrupt comprises of the key input interrupt and external interrupt sections,
and a total of 11 factors can be received.
■ Feature of External Interrupt
External interrupts comprise of the key input interrupt and external interrupt sections.
•
•
External interrupt3 input
Key input interrupt 8 input
218
Download from Www.Somanuals.com. All Manuals Search And Download.
13.2
External Interrupt 1 (Key Input Circuit)
The external interrupt 1 (key input circuit) has 8 inputs.
■ Block Diagram of External Interrupt 1 (Key Input Circuit)
Figure 13.2-1 Block Diagram of Key input circuit
IRQ23
SR
KEY7
R
Read-STB
KEY6
KEY5
KEY4
KEY3
KEY2
KEY1
KEY0
KIS7 KIS6 KIS5 KIS4 KIS3 KIS2 KIS1 KIS0
KEYS
KIE7 KIE6 KIE5 KIE4 KIE3 KIE2 KIE1 KIE0
KEYC
Internal Bus
■ Register List of External Interrupt 1 (Key Input Circuit)
Figure 13.2-2 Register list of External interrupt 1 (Key input circuit)
bit
7
0
Key Input Control Register
Key Input Status Register
KEYC
KEYS
Address: 000096H
000097H
219
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 13 External Interrupt
■ Key Input Control Register (KEYC)
Figure 13.2-3 Key input control register (KEYC)
bit
7
6
5
4
3
2
1
0
Initial value
0000 0000B
KIE7
R/W
KIE6
R/W
KIE5
R/W
KIE4
R/W
KIE3
R/W
KIE2
R/W
KIE1
R/W
KIE0
R/W
Address: 000096H
Access
[bit7 to 0]:KIE7 to 0
There are input enable bit of KEY7 to 0.
0
1
KEY input interdiction
KEY input permission
■ Key Input Status Register (KEYS)
Figure 13.2-4 Key input status register (KEYS)
bit
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
KIS7
KIS6
KIS5
KIS4
KIS3
KIS2
KIS1
KIS0
R
Address: 000097H
Access
R
R
R
R
R
R
R
[bit7 to 0]:KIS7 to 0
There are edge detection flag of KEY7 to 0.
0
1
None
Falling edge detection
These flags are cleared by the read operation.
■ Operation of External Interrupt 1 (Key Input Circuit)
In order to use the key input, Port A input must be enabled. If Port A input is disabled while key input is
enabled, a key input edge detection interrupt may be generated.
The key input sets the flip-flop when the input signal falling edge is detected. In this case, if the supported
key input is enabled, an interrupt request is generated. The generated interrupt request can be also used to
return from standby status, etc.
Do not use the bit operation command to read the key input status register.
220
Download from Www.Somanuals.com. All Manuals Search And Download.
13.3
External Interrupt (INT0 to 2)
The external interrupt (INT0 to 2) has 3 inputs.
■ Feature of External Interrupt (INT0 to 2)
•
Each interrupt is independent vector.
•
Usable for returning from standby.
■ Block Diagram of External Interrupt (INT0 to 2)
Figure 13.3-1 Block diagram of external interrupt (INT0 to 2)
SR
R
INT2
IRQ04
clr
enable
INT1
INT0
IRQ03
IRQ02
IF3
IF2
IF1
Test
EIF
INT2E INT1E INT0E Test I2CLR I1CLR I0CLR Test
EIE
Internal Bus
■ Register List of External Interrupt (INT0 to 2)
Figure 13.3-2 Register list of external interrupt (INT0 to 2)
bit
7
0
External Interupt Enable R
External Interupt Request
Address: 000098H
000099H
EIE
EIF
221
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 13 External Interrupt
■ External Interrupt Enable Register (EIE)
Figure 13.3-3 External interrupt enable register (EIE)
bit
7
6
5
4
3
2
1
0
Initial value
0000 111-B
INT2E
R/W
INT1E
R/W
INT0E
R/W
Test
R/W
I2CLR
W
I1CLR
W
I0CLR
W
Address: 000098H
Access
W
[bit7 to 5]:INT2E to 0E
There are interrupt enable bits of INT2 to 0.
0
1
Interrupt interdiction
Interruption permission
[bit4]:Test
It is test control bit.
Please set "0".
[bit3 to 1]:I2CLR to I0CLR
There are interrupt flag clear bits of INT2 to 0.
0
1
The flag is clear.
None
The read value of this bit is always "1".
[bit0]:
It is an unused bit.
■ External Interrupt Request Flag (EIF)
Figure 13.3-4 External interrupt request flag (EIF)
bit
7
6
5
4
3
IF2
R
2
IF1
R
1
IF0
R
0
Test
R
Initial value
---- XXXXB
Address: 000099H
Access
[bit7 to 4]:
It is an unused bit.
[bit3 to 1]:IF2 to 0
There are input edge detection flag of INT2 to 0.
0
1
None
Falling edge detection
[bit0]:Test
It is test bit.
222
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Operation of External Interrupt (INT0 to 2)
The external interrupt sets the interrupt request flag (IF2 to 0) when the falling edge of the input signal is
detected. In this case, if the supported interrupt is enabled (INTxE=1), an interrupt request is generated to
the interrupt controller, whereas if it is disabled, no interrupt request is generated.
The external interrupt can be used for returning the standby status.
Before enabling interrupts, clear the interrupt request flag.
223
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 13 External Interrupt
224
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 14 Delayed Interrupt Module
14.1
Overview of Delayed Interrupt Module
The delay interrupt module is used to generate interrupts for switching tasks.
Using this module enables interrupt requests to the CPU to be generated or cancelled
by the software.
■ Block Diagram of Delayed Interrupt Module
Figure 14.1-1 Block diagram of delayed interrupt module
INT*(C-unit)
Priority judgement
OR
LEVEL4 to 0
LEVEL judgement
ICR00
RI00
(to CPU)
LEVEL,
VECTOR
judgement
VECTOR
Generation
VCT5 to 0
ICR47
RI47
DLYIR Q
DLYI
R-Bus
■ Register List of Delayed Interrupt Module
Figure 14.1-2 Register list of Delayed Interrupt Module
bit
7
0
Delayed Interrupt Control R
Address: 000430H
DICR
226
Download from Www.Somanuals.com. All Manuals Search And Download.
14.2
Delayed Interrupt Control Register (DICR)
The delay interrupt control register (DICR) controls delay interrupts.
■ Delayed Interrupt Control Register (DICR)
Figure 14.2-1 Delayed interrupt control register (DICR)
bit
7
6
5
4
3
2
1
0
Initial value
---- ---0B
DLYI
R/W
Address: 00430H
Access
[bit7 to 1]:
It is an unused bit.
[bit0]:DLYI
It is EINT input edge detection flag.
Table 14.2-1
0
Delayed interrupt factor cancellation and no request
Delayed interrupt factor generation
1
This bit is controlled the generation or cancellation of the corresponding interrupt factor.
227
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 14 Delayed Interrupt Module
14.3
Operation of Delayed Interrupt Module
Delay interrupts are used to generate interrupts for switching tasks. Using this function
enables interrupt requests to the CPU to be generated or cancelled by the software.
■ Interrupt Number
The delay interrupt is allocated to the interrupt factor supporting the largest interrupt number. It will be the
interrupt factor that supports the interrupt number 63 (3FH) for this product comprising of 48 factors.
■ DLYI Bit of DICR
Writing "1" to this bit generates a delay interrupt factor. Also, writing "0" cancels a delay interrupt factor.
This bit is the same as the interrupt factor flag under general interrupts. Clear this bit within the interrupt
routine, and simultaneously switch the task.
228
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 15 Interrupt Controller
15.1
Overview of Interrupt Controller
The interrupt controller comprises of the interrupt control register, interrupt priority
decision circuit, interrupt level, and interrupt number generation sections, and controls
interrupt reception and adjustment.
■ Block Diagram of Interrupt Controller
Figure 15.1-1 Block Diagram of Interrupt controller
INT*(C-unit)
Priority judgement
OR
LEVEL4 to 0
LEVEL judgement
ICR00
RI00
(to CPU)
LEVEL,
VECTOR
Generation
VECTOR
judgement
VCT5 to 0
ICR47
RI47
DLYIR Q
DLYI
R-Bus
Notes:
•
•
INT* is the wake-up signal to the clock control sections during sleep/stop status.
230
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Register List of Interrupt Controller
Figure 15.1-2 Register list of interrupt controller
bit
7
0
Interrupt Control Register 00
Interrupt Control Register 01
Interrupt Control Register 02
Interrupt Control Register 03
Interrupt Control Register 04
Address:
ICR00
ICR01
ICR02
ICR03
ICR04
000400H
000401H
000402H
000403H
000404H
00042BH
00042CH
00042DH
00042EH
00042FH
ICR43
ICR44
ICR45
ICR46
ICR47
Interrupt Control Register 43
Interrupt Control Register 44
Interrupt Control Register 45
Interrupt Control Register 46
Interrupt Control Register 47
231
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 15 Interrupt Controller
15.2
Interrupt Control Register (ICRxx)
This is interrupt control register. One is set per interrupt input, and sets the interrupt
level for the interrupt request to be supported.
■ Interrupt Control Register (ICRxx)
Figure 15.2-1 Interrupt control register (ICRxx)
bit
7
6
5
4
ICR4
R
3
2
1
0
Initial value
---1 1111B
ICR3
R/W
ICR2
R/W
ICR1
R/W
ICR0
R/W
Access
[bit4 to 0] ICR4 to 0
The interrupt level of the interrupt request to be supported is specified by the interrupt level setting bit.
When the interrupt level set to this register is the level mask value that has been set to the ILM register
of the CPU or higher, the interrupt request is masked by the CPU side.
Initialized to 11111B by reset.
Table 15.2-1 is shown the interrupt-level setting bits that can be set and the corresponding interrupt
levels.
Table 15.2-1 Level setting and corresponding interrupt levels
ICR4
ICR3
ICR2
ICR1
ICR0
Interrupt level
System reservation
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Highest level that can be set
(High)
(low)
Disables the interrupt.
*: ICR4 is fixed "1" and cannot be "0".
232
Download from Www.Somanuals.com. All Manuals Search And Download.
15.3
Operation of Interrupt Controller
The interrupt request generated at the resource is controlled by the interrupt-enabled
bit that has been set per resource. If an interrupt is enabled at each resource, the
generated interrupt request generates an interrupt request signal to the interrupt
controller.
■ Priority Order Evaluation
The interrupt controller selects the highest priority factor from those that have been generated
simultaneously, and outputs the factor's interrupt level and interrupt number to the CPU.
The criteria for evaluating the priority order of the interrupt causes are shown below.
● The interrupt cause meets the following conditions:
•
•
•
The interrupt cause has an interrupt level other than 31 (A value of 31 represents interrupt disable.)
The interrupt cause has the lowest interrupt level
The interrupt cause has the smallest interrupt number
Table 15.3-1 shows the relationship between interrupt causes, interrupt numbers, and interrupt levels.
Figure 15.3-1 Flowchart of interrupt cause
Interrupt Controler
CPU
Resource request 01
Resource request 02
Resource request xx
Resource request yy
ICR01
ICR02
CMP
IL
ICRxx
CMP
ILM
ICRyy
233
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 15 Interrupt Controller
Table 15.3-1 Relationship between interrupt causes, interrupt numbers, and interrupt levels
Interrupt number
Interrupt
level
TBR default
address
Interrupt cause
Offset
03BC
10 decimal
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
16 decimal
IRQ0
Reserved
10
11
12
13
14
15
16
17
18
19
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
ICR16
ICR17
ICR18
ICR19
ICR20
ICR21
ICR22
ICR23
ICR24
ICR25
ICR26
ICR27
ICR28
ICR29
ICR30
ICR31
ICR32
ICR33
ICR34
ICR35
ICR36
ICR37
ICR38
ICR39
ICR40
ICR41
ICR42
ICR43
ICR44
ICR45
ICR46
ICR47
000FFFBC
H
H
H
H
H
H
H
H
H
H
H
H
IRQ1
Reserved
03B8
03B4
03B0
000FFFB8
000FFFB4
000FFFB0
H
H
IRQ2
External Interrupt 0 (INT0)
External Interrupt 1 (INT1)
External Interrupt 2 (INT2)
24-bit Free Run Counter/Capture
Programmable Pulse Generator ch0
Programmable Pulse Generator ch1
Real timing Generator ch0
Real timing Generator ch1
Real timing Generator ch2
10-bit A/D Converter (Hard)
8-/16-bit Timer/Counter(Timer5 to 0)
8-/16-bit Timer/Counter(Timer5 to 1)
16-bit Timer/Counter (Timer4)
16-bit Timer (Timer0)
16-bit Timer (Timer1)
16-bit Timer (Timer2)
16-bit Timer (Timer3)
Serial I/O ch0 (SIO0)
Serial I/O ch1 (SIO1)
Serial I/O ch2 (SIO2)
10-bit A/D Converter (Soft)
Key-Input Interrupt
Reserved
H
H
H
H
IRQ3
IRQ4
03AC
000FFFAC
H
H
H
H
H
H
H
H
H
H
IRQ5
03A8
03A4
03A0
000FFFA8
000FFFA4
000FFFA0
000FFF9C
IRQ6
IRQ7
IRQ8
039C
IRQ9
0398
0394
0390
000FFF98
000FFF94
000FFF90
H
H
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ16
IRQ17
IRQ18
IRQ19
IRQ20
IRQ21
IRQ22
IRQ23
IRQ24
IRQ25
IRQ26
IRQ27
IRQ28
IRQ29
IRQ30
IRQ31
IRQ32
IRQ33
IRQ34
IRQ35
IRQ36
IRQ37
IRQ38
IRQ39
IRQ40
IRQ41
IRQ42
IRQ43
IRQ44
IRQ45
IRQ46
IRQ47
1A
1B
1C
1D
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
038C
000FFF8C
H
H
0388
0384
0380
000FFF88
000FFF84
000FFF80
H
H
1E
H
H
H
H
1F
20
21
22
23
24
25
26
27
28
29
037C
000FFF7C
H
H
0378
0374
0370
000FFF78
000FFF74
000FFF70
H
H
H
H
H
H
036C
000FFF6C
H
H
0368
0364
0360
000FFF68
000FFF64
000FFF60
H
H
H
H
H
H
035C
000FFF5C
H
H
Reserved
0358
0354
0350
000FFF58
000FFF54
000FFF50
H
H
Reserved
2A
2B
2C
2D
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Reserved
Reserved
034C
000FFF4C
H
H
Reserved
0348
0344
0340
000FFF48
000FFF44
000FFF40
H
H
Reserved
2E
H
H
H
H
Reserved
2F
30
31
32
33
34
35
36
37
38
39
Reserved
033C
000FFF3C
H
H
Reserved
0338
0334
0330
000FFF38
000FFF34
000FFF30
H
H
Reserved
H
H
H
H
Reserved
Reserved
032C
000FFF2C
H
H
Reserved
0328
0324
0320
000FFF28
000FFF24
000FFF20
H
H
Reserved
H
H
H
H
Reserved
Reserved
031C
000FFF1C
H
H
Reserved
0318
0314
0310
000FFF18
000FFF14
000FFF10
H
H
Reserved
3A
3B
3C
3D
H
H
H
H
H
H
H
H
H
H
Reserved
Reserved
030C
000FFF0C
H
H
Reserved
0308
0304
0300
000FFF08
000FFF04
000FFF00
H
H
Flash
3E
3F
H
H
H
H
Delayed Interrupt (REALOS)
234
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Return by Standby Mode (Stop/Sleep)
The function returned from the stop mode is realized in the interrupt controller by generating an interrupt
request.
Even if an interrupt request is generated from a peripheral, a return request is generated from the standby
mode to the clock control section.
Operation of the priority decision section restarts after the clock is supplied upon returning from the stop
status. The CPU continues executing commands until the result is output from the priority decision section.
The same operation is performed when returning from the sleep status.
Note:
Interrupt request output should be disabled from the stop and sleep mode by the supported
peripheral control register in order that the interrupt factors are not return factors. As the return
request signal from the standby mode is just a logical sum output of all interrupt factor, the contents
of the interrupt level that has been set to the ICR are not taken into account.
■ Cancellation of Interrupt Cause
There is a limit between the command for releasing the interrupt factor and the RETI command under the
235
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 15 Interrupt Controller
236
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 16 10-bit A/D Converter
16.1
Overview of 10-bit A/D Converter
The 10-bit successive approximation type A/D converter retains the conversion
initiation modes using software and hardware.
■ Feature of 10-bit A/D Converter
•
•
•
•
Conversion time 8.4 µs (sampling 6.3 µs, conversion 2.2 µs) in fch:@20 MHz
Corporate 6 stages of FIFO soft conversion result (4-bit + 10-bit)
Corporate 6 stages of FIFO hard conversion result (4-bit + 10-bit)
Channel scan function
■ Block Diagram of 10-bit A/D Converter
Figure 16.1-1 Block Diagram of 10-bit A/D Converter
(Soft) Fifo 6 steps
(Hard) Fifo 6 steps
Buf
AN-F
AN-E
AN-D
AN-C
AN-B
AN-A
AN-9
AN-8
AN-7
AN-6
AN-5
AN-4
AN-3
AN-2
AN-1
AN-0
D/A Convertor
Comparator
Control Logic
A/D
M
P
X
S/H
ch& Status
Control Logic
from RTG (RTO4)
from PPG1(OD13)
from PPG0(OD27)
ADST1
IRQ22(Soft)
IRQ11(Hard)
ADST0
ch_Sel
from PPG0(OD26-24)
■ Register List of 10-bit A/D Converter
Figure 16.1-2 Register list of 10-bit A/D Converter
15
0
bit
87
Address:
A/DC Control Register
0000A0H
0000A2H
0000A4H
0000A6H
0000A8H
0000AAH
ADCH
ADCL
SCSR
HCSR
Soft Conversion Analog Input Selection Register
Soft Conversion Status Register
SCIS
Soft Conversion FIFO Data Register
Hard Conversion Status Register
SCFD
HCFD
Hard Conversion FIFO Data Register
238
Download from Www.Somanuals.com. All Manuals Search And Download.
16.2
Register of 10-bit A/D Converter
The register configuration/functions of the 10-bit A/D converter is shown.
■ A/D Converter Control Register (ADCH, ADCL)
● ADCH
Figure 16.2-1 A/D converter control register (ADCH)
bit
Address: 0000A0H
Access
7
Test
R
6
Test
R
5
Test
R
4
3
2
HCS
1
SCS
0
Initial value
ADMV
HCNS
SSTR
XXX0 0000B
R
R
R
R
R
[bit7 to 5]:Test
It is test bit.
[bit4]:ADMV
It is flag to indicate under A/D conversion.
0
1
Not Under the conversion
Under the conversion
[bit3]:HCNS
It is hard start hold flag.
0
1
No conversion hold by hard start (without nest)
Conversion hold by hard start (with nest)
[bit2]:HCS
It is hard conversion status flag.
0
1
Conversion complete by hard start
Under the conversion by hard start
[bit1]:SCS
It is soft conversion status flag.
0
1
Conversion complete by soft start
Under the conversion by soft start
[bit0]:SSTR
It is soft conversion start bit.
0
1
None
Start/restart soft conversion (writing under conversion)
When this bit is read, "0" is always read.
239
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 16 10-bit A/D Converter
● ADCL
Figure 16.2-2 A/D converter control register (ADCL)
bit
Address: 0000A1H
Access
7
6
5
4
3
2
Hi2
1
Hi1
0
Hi0
Initial value
Test
Test
Test
000- -XXXB
R/W
R/W
R
R/W
R/W
R/W
[bit7 to 6]:Test
Please set "0".
[bit5]:Test
It is test bit.
[bit4, 3]:
There are unused bit.
[bit2 to 0]:Hi2 to 0
There are analog input selection bits for hard conversion.
Hi2
Hi1
Hi0
Selection analog input
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AN-0
AN-1
AN-2
AN-3
AN-4
AN-5
AN-6
AN-7
■ Soft Conversion Analog Input Selection Register (SCIS)
Figure 16.2-3 Soft conversion analog input selection register (SCIS)
15 14 13 12 11 10
iF iE iD iC iB iA
9
8
7
6
5
4
3
2
1
0
bit
Initial value
Address: 0000A2H
i9 i8
i7
i6
i5
i4 i3 i2
i1
i0
0000 0000H
Access
R/W
[bit15 to 0]:iF to 0
There are analog input selection bits for soft conversion.
0
1
Input non-selection
Input selection
When a number of inputs are selected, all selected inputs are converted sequentially.
240
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Soft Conversion Status Register (SCSR)
Figure 16.2-4 Soft conversion status register (SCSR)
bit
Address: 0000A5H
Access
7
6
5
4
3
2
1
0
Initial value
SFCR
SFUL
SEMP
SCEF
SECR
SCIE
X10- -001B
R
W
R/W
W
R
R
[bit7]:SCEF
It is soft conversion end flag.
0
1
None or Under the conversion
Conversion complete
[bit6]:SECR
It is SCEF clear bit.
0
1
Clear soft conversion end flag.
None
The read value of this bit is always "1".
[bit5]:SCIE
It is soft conversion interrupt enable bit.
0
1
Interrupt interdiction
Interruption permission
The interrupt request is generated when SCEF=1 is SCIE=1.
[bit4, 3]:
It is an unused bit.
[bit2]:SFCR
It is soft conversion FIFO clear bit.
0
1
None
Clear FIFO.
The read value of this bit is always "0".
[bit1]:SFUL
It is soft conversion FIFO full bit.
0
1
Status that data can input to FIFO
FIFO full
[bit0]:SEMP
It is soft conversion FIFO empty bit.
0
1
Status that data is retained in FIFO
FIFO empty
241
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 16 10-bit A/D Converter
■ Soft Conversion FIFO Data Register (SCFD)
Figure 16.2-5 Soft conversion FIFO data register (SCFD)
15 14 13 12 11 10
C3 C2 C1 C0
9
8
7
6
5
4
3
2
1
0
bit
Address: 0000A6H
Access
Initial value
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
XXXX --XXH
XXXX XXXXH
R
It is conversion result register for soft start. Reading this register enables data to be fetched sequentially.
[bit11, 10]:
It is an unused bit.
[bit15 to 12]:C3 to 0
It is input channel of conversion result.
C3
C2
C1
C0
Channel supported by
conversion result
0
0
0
0
0
0
0
1
AN-0
AN-1
0 to 1
1
0 to 1
1
1 to 1
1
0 to 0
1
AN-2 to AN-E
AN-F
[bit9 to 0]:D9 to 0
It is soft conversion data.
■ Hard Conversion Status Register (HCSR)
Figure 16.2-6 Hard Conversion Status Register (HCSR)
bit
Address: 0000A9H
Access
7
6
5
4
3
2
1
0
Initial value
HFCR
HFUL
HEMP
HCEF
HECR
HCIE
X10- -001B
R
W
R/W
W
R
R
[bit7]:HCEF
It is hard conversion end flag.
0
1
None or Under the conversion
Conversion complete
[bit6]:HECR
It is HCEF clear bit.
0
1
Clear hard conversion end flag.
None
The read value of this bit is always "1".
242
Download from Www.Somanuals.com. All Manuals Search And Download.
[bit5]:HCIE
It is hard conversion interrupt enable bit.
0
Interruption interdiction
Interruption permission
1
The interrupt request is generated when HCEF=1 is HCIE=1.
[bit2]:HFCR
It is hard conversion FIFO clear bit.
0
1
None
Clear FIFO.
The read value of this bit is always "0".
[bit1]:HFUL
It is hard conversion FIFO full bit.
0
1
Status that data can input to FIFO
Status of FIFO full
[bit0]:HEMP
It is hard conversion FIFO empty bit.
0
1
Status that data is retained in FIFO
Status of FIFO empty
■ Hard Conversion FIFO Data Register (HCFD)
Figure 16.2-7 Hard conversion FIFO data register (HCFD)
15 14 13 12 11 10
RS C2 C1 C0
9
8
7
6
5
4
3
2
1
0
bit
Initial value
Address: 0000AAH
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
XXXX --XXH
XXXX XXXXH
Access
R
It is conversion result register for hard start. Reading this register enables data to be fetched sequentially.
[bit15]:RS
It is hard conversion request status.
0
1
ADST0 (PPG0)
ADST1 (PPG1, RTG)
243
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 16 10-bit A/D Converter
[bit14 to 12]:C2 to 0
It is input channel of hard conversion result.
C2
C1
C0
Channel supported by
conversion result
0
0
0
0
0
1
AN-0
AN-1
0 to 1
1
1 to 1
1
0 to 0
1
AN-2 to AN-6
AN-7
[bit9 to 0]:D9 to 0
There are hard conversion data.
244
Download from Www.Somanuals.com. All Manuals Search And Download.
16.3
Operation of 10-bit A/D Converter
In terms of 10-bit A/D converter operations, A/D operation is possible using both
software and hardware conversions.
■ A/D Operation by Soft Conversion
In order to carry out A/D conversion using software conversion, first select the required channel from the
16 analog input pins AN0 to ANF. Enabled by writing "1" to the bit supported by the SCIS register.
● For one channel
When only one channel is selected as the analog input pin for software conversion: Writing "1" to the
SSTR bit of the ADCH register starts the software conversion, and the SCS bit of the ADCH register will
be set to "1".
Writing "1" to the SSTR bit again during conversion initializes the conversion operation, and conversion
restarts.
When A/D conversion ends, the SCS bit of the ADCH register is reset to "0", and the SCEF bit of the
SCSR register is set to "1". Reading these status bits enables the end of the conversion to be determined. If
the interrupt for conversion completion needs to be generated, the SCIS bit of the SCSR register shall be set
to "1".
● For multiple channel
When a number of channels are selected as the analog input pin for software conversion, automatically
checks whether or not each channel is selectable, then switches channels sequentially, starts up A/D
conversion, and stores the conversion results on a FIFO basis.
For the channel to be converted, writing "1" to the bit supported by the SCIS register and writing "1" to the
SSTR bit of the ADCH register starts software conversion, and the SCS bit of the ADCH register will be
set to "1". The conversion channel is selected from 0 to 15 sequentially, any channels that are not selected
by the SCIS register are not converted, and the next selected channel will be converted.
Writing "1" to the SSTR bit during conversion initializes the conversion operation, and conversion restarts
from channel 0.
When A/D conversion of all selected channels ends, the SCS bit of the ADCH register is reset to "0", and
the SCEF bit of the SCSR register is set to "1". If an interrupt for conversion completion needs to be
generated, the SCIS bit of the SCSR register shall be set to "1".
The A/D converted results can be stored FIFO up to six times, and they are automatically input on FIFO
basis at the end of A/D conversion. FIFO data can be retrieved by reading the SCFD register, then after
reading is automatically incremented in FIFO format, and the next data is output.
However, when the SCFD register is read through byte access, it is not incremented in FIFO format. When
the next conversion is carried out while FIFO basis is full (SCSR:SFUL_bit=1), the conversion results will
be overwritten at the sixth FIFO column.
245
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 16 10-bit A/D Converter
■ A/D Operation by Hard Conversion
A/D conversion using hardware conversion can be operated by the ADST0 (PPG0) or ADST1 (PPG1,
RTG) factors, and operation starts when the ADST0 or ADST1 rising edge is detected. Both ADST0 and
ADST1 can select eight analog input pins (AN0 to AN7), with ADST0 being selected by the OD26 to 24
signals from the PPG0, and ADST1 being selected by the ADCL register Hi2 to 0.
When the A/D conversion is performed, the HCS bit of the ADCH register is set to "1". When conversion
ends, the HCS bit of the ADCH register is reset to "0", and the HCEF bit of the HCSR register is set to "1".
If the conversion completion interrupt needs to be generated, the HCIS bit of the HCSR register shall be set
to "1".
The A/D converted results can be stored FIFO up to six times, and they are automatically input on FIFO
basis at the end of A/D conversion. FIFO data can be retrieved by reading the HCFD register, then after
reading is automatically incremented in FIFO format, and the next data is output.
However, when the HCFD register is read through byte access, it is not incremented in FIFO format.
● Generation condition of hard start request signal
When OD027(PPG0) & EQ(PPG0)=1, the ADST0 signal generates.
When OD113 & EQ(PPG1)=1, the ADST1 signal generates.
When RTO04 & EQ0(RTG0)=1, the ADST1 signal generates.
When RTO14 & EQ1(RTG1)=1, the ADST1 signal generates.
When RTO24 & EQ2(RTG2)=1, the ADST1 signal generates.
■ Priority Order of A/D Conversion
In terms of the A/D conversion initiation factors, three types of initiation can be executed, namely initiation
by software, and initiation by two types of hardware (ADST0 & ADST1), and their priority ranking is as
follows.
Priority order
High
ADST0 initiation by hardware
to
ADST1 initiation by hardware
Initiation by software
Low
● When initiation by hardware enters at software operation
Suspend the operation by software and perform the operation by hardware. When hardware operation ends,
software operation automatically restarts.
● When ADST0 initiation enters at operation by ADST1 initiation
Hold the operation by ADST1 initiation and perform the operation by ADST0 initiation. When the
operation initiated by the ADST0 ends, ADST1 automatically restarts.
Note:
Conversion initiation requests with the same factor are masked during conversion by hardware.
246
Download from Www.Somanuals.com. All Manuals Search And Download.
16.4
State Transition of 10-bit A/D Converter
Figure 16.4-1 shows the state transition of 10-bit A/D converter.
■ State Transition of 10-bit A/D Converter
Figure 16.4-1 State transition of 10-bit A/D converter
000
A/D Conversion wait
Soft Conversion request
001
Hard Conversion request
010
Soft Conversion end Hard Conversion end
Soft Converting
Hard Converting
Soft Conversion request
Hard Conversion request
011
Hard Conversion end
Hard Converting
With Soft Converting
reservation
Hard Conversion end
Hard Conversion request
110
Hard Converting
Hard Conversion end
Hard Conversion request
With ADST1 Converting
reservation
111
Soft Conversion request
Hard Converting
With ADST1 Converting reservation
With Soft Converting reservation
The operation state can be known by the SCS, HCS, and HCNS bit of the ADCH register.
HCNS
HCS
SCS
Status Description
0
0
0
0
0
1
0
1
0
Analog to digital conversion wait
Analog to digital conversion by soft start
Analog to digital conversion by hard start (0 and 1)
Analog to digital conversion by hard start (0 and 1)
Retention of soft start
0
1
1
1
1
1
1
0
1
Analog to digital conversion by hard start 0
Retention of soft start 1
Analog to digital conversion by hard start 0
Retention of soft start and hard start 1
247
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 16 10-bit A/D Converter
248
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 17 Serial I/O
17.1
Overview of Serial I/O
The serial I/O can automatically transfer 8-bit serial data and can select external
initiation, multiple shift clock, and transfer interval time.
■ Feature of Serial I/O
•
•
•
•
•
8-bit serial data can be transferred using clock synchronization.
Automatic transfer of up to 128 bytes
External initiation by ship select input (XCS)
4-type shift clock (inner: 3, outer: 1) can be selected
Enable/disable of transition interval time can be selected
■ Block Diagram of Serial I/O
Figure 17.1-1 Block diagram of serial I/O
Internal Bus
IRQx
Port
CTL
R
SIF ICLR SIE CSAF ACLR DIR
CSE ST
IC1
IC0
Control Unit
SC2
SC1
SC0
Transfer Byte Count Register
BM
XCS
SCK
Compare
23/fch
M
P
X
Clock
Control
Unit
SHIFT-CLOCK
24/fch
25/fch
Transfer Byte Count Register
Address offset
External
SO
SI
Shift Register
BMOD
RAM
250
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Register List of Serial I/O
Figure 17.1-2 Register list of Serial I/O
7
0
Address:
000300H
00037FH
SIO0 DATA RAM
Serial 0 Data Buffer RAM
128byte
0003C8H
0003C9H
0003CAH
0003CBH
0003CCH
0003CDH
0003CEH
0003CFH
0003D0H
0003D1H
0003D2H
0003D3H
S0CR
S0MR
S0AO
S0BR
S1CR
S1MR
S1AO
S1BR
S2CR
S2MR
S2AO
S2BR
Serial Control Register
Clock Mode Setting Register
Address Offset Register
Transfer Byte Count Setting Register
Serial Control Register
Clock Mode Setting Register
Address Offset Register
Transfer Byte Count Setting Register
Serial Control Register
Clock Mode Setting Register
Address Offset Register
Serial 0
Serial 1
Serial 2
Transfer Byte Count Setting Register
001000H
SIO1 DATA RAM
128byte
Serial 1 Data Buffer RAM
Serial 2 Data Buffer RAM
00107FH
001080H
SIO2 DATA RAM
128byte
0010FFH
251
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 17 Serial I/O
17.2
Register of Serial I/O
The register configuration/functions of the serial I/O is shown.
■ Serial Control Register (SxCR)
Figure 17.2-1 Serial control register (SxCR)
bit
7
6
5
4
3
2
1
0
Initial value
SIF
ICLR
SIE
CSAF
ACLR
CSE
DIR
ST
0100 1000B
Access
R
W
R/W
R
W
R/W
R/W
R/W
[bit7]:SIF
It is serial I/O transfer completion flag.
0
1
Serial data transfer does not complete.
Serial data transfer completes.
[bit6]:ICLR
It is transfer completion flag clear bit.
0
1
Clear transfer completion flag
None
The read value of this bit is always "1".
[bit5]:SIE
It is interrupt enable bit.
0
1
Interruption is disabled.
Interruption is enabled.
[bit4]:CSAF
It is forced end flag at chip select transfer.
0
1
Automatic transfer normally ends by chip select.
Forcibly ends by chip select under transfer.
[bit3]:ACLR
It is forced end flag clear bit.
0
1
Clear transfer completion flag.
None
252
Download from Www.Somanuals.com. All Manuals Search And Download.
The read value of this bit is always "1".
[bit2]:CSE
It is the chip select auto-transfer enable bit.
0
1
Automatic transfer is disabled.
Automatic transfer is enabled.
[bit1]:DIR
It is transfer direction control bit.
Transfer reception data to RAM per transmitting RAM data
(transmission/reception mode)
0
1
Transmit RAM data (Transmission mode)
[bit0]:ST
It is serial transfer start bit.
0
1
Transfer Stop
Transfer start
This bit will be cleared to "0" when serial data transfer ends.
■ Clock Mode Setting Register (SxMR)
Figure 17.2-2 Clock mode setting register (SxMR)
bit
7
6
5
4
3
2
1
0
Initial value
IC1
IC0
SC2
SC1
SC0
--0X XXXXB
Access
R/W
R/W
R/W
R/W
R/W
R/W
[bit7, 6]:
There are unused bits.
[bit5]:
It is undefined bit. (Reserved)
[bit4]:IC1
253
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 17 Serial I/O
[bit3]:IC0
It is selection bit of interval. Setting the interval is as follows.
IC1
IC0
Interval: T int
0
0
1
1
0
1
0
1
Tclk × 16 µs
Tclk × 32 µs
Tclk × 64 µs
No interval time (selection is disabled at external clock)
*:Tclk= Shift clock cycle time
[bit2]:SC2
[bit1]:SC1
[bit0]:SC0
It is selection bit of shift clock.
Cycle time
(fch=@20MHz)
SC2 SC1 SC0
Selection clock
Shift clock cycle time: Tclk
-
Specification
prohibited
0
0
0
-
3
0
0
0
0
1
1
1
0
1
0.4 µs (1:1)
0.8 µs (1:1)
1.6 µs (1:1)
2 × φ
4
2 × φ
Internal clock
5
2 × φ
Specification
prohibited
1
0
0
-
-
1
1
1
0
1
1
1
0
1
External clock
Min 8 x φ (duty 50%)
0.4 µs (φ:50 ns)
-
-
-
-
Specification
prohibited
φ: Defined by peripheral clock gear (PCK1 and 0)
fch: Source oscillation frequency
Table 17.2-1 Shift clock cycle and interval at 20 MHz operation
Tint
SC2
SC1
SC0
Tclk
IC1, IC0=(0, 0)
IC1, IC0=(0, 1)
IC1, IC0=(1, 0)
0
0
0
0
1
1
1
0
1
0.4 µs
0.8 µs
1.6 µs
6.4 µs
12.8 µs
25.6 µs
12.8 µs
25.6 µs
51.2 µs
51.2 µs
102.4 µs
204.8 µs
254
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Address Offset Register (SxAO)
Figure 17.2-3 Address offset register (SxAO)
bit
7
6
5
4
3
2
A2
W
1
A1
W
0
Initial value
-000 0000B
A6
A5
W
A4
W
A3
W
A0
W
Access
Sets the start address offset of the serial data RAM.
■ Transfer Byte Number Setting Register (SxBR)
Figure 17.2-4 Transfer byte number setting register (SxBR)
bit
7
6
5
4
3
2
1
0
Initial value
BM0D
BC6
BC5
BC4
BC3
BC2
BC1
BC0
0XXX XXXXB
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7]:BMOD
It is serial buffer mode control bit.
0
Buffer overwrite mode
Transmission/reception data buffer independent mode
1
[bit6 to 0]:BC6 to 0
It is transfer byte number setting bit. The transfer byte number becomes the set value +1. Up to 128
bytes can be transferred. However, when transmission/reception data buffer independent mode is
specified by the BMOD bit, specification of BC6 will be invalid, and a maximum of 64 bytes will be
transferred.
255
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 17 Serial I/O
17.3
Serial Data RAM
The serial data RAM has 128 bytes per channel. In this section, explanations are given
based on serial 0.
■ Serial Data RAM
For serial 0 of this RAM, the byte number set by the transfer byte number setting register from the address
"300H" is used as the serial data buffer.
When BMOD=0, the transfer address is 1st byte: "300H"; 2nd byte: "301H". When BMOD=1, the transfer
address is 1st byte: transmission data "300H", reception data "340H"; 2nd byte: transmission data "301H",
reception data "341H". In both cases, any area exceeding the byte number that has been set can be used as
data RAM. If other than 00H is set as the offset address, the value whereby the set value is added to the
address of 300H will be the 1st byte address.
Figure 17.3-1 Data RAM and transfer order (BMOD=0)
Address
Transmission/Reception Buffer
offset + 00300H
offset + 00301H
offset + 00302H
offset + 00303H
1 Byte
2 Byte
3 Byte
4 Byte
offset + 0037DH
offset + 0037EH
offset + 0037FH
126 Byte
127 Byte
128 Byte
(When exceeding 00037FH by setting
the offset address)
Figure 17.3-2 Data RAM and transfer order (BMOD=1)
Transmission Buffer
1 Byte
Reception Buffer
offset + 00300H
offset + 00301H
offset + 00340H
offset + 00341H
1 Byte
2 Byte
2 Byte
offset + 0033FH
64 Byte
offset + 0037FH
64 Byte
(When exceeding 0033F )
(When exceeding 0037F )
H
H
256
Download from Www.Somanuals.com. All Manuals Search And Download.
17.4
Operation of Serial I/O
The serial I/O has two modes, namely, transmission mode and transmission/reception
mode.
■ Operation of Serial I/O
The serial I/O has two modes, namely, transmission mode and transmission/reception mode. In the case of
transmission mode (DIR=1), contents transferred to the P.S conversion buffer from the data RAM area are
synchronized to the falling of the external clock or serial shift clock (SCK) generated internally and output
to the serial output pin (SO) bit serially. In the case of transmission reception mode (DIR=0), contents
transferred to the P.S conversion buffer from the data RAM area are synchronized to the falling of the
external clock or serial shift clock (SCK) generated internally, output to the serial output pin (SO) bit
serially, also retrieved into the P.S conversion buffer at the rising of the serial shift clock (SCK) bit serially
from the serial input pin (SI), and transferred to the data RAM when 8-bit transfer ends.
● Transmission/reception mode
Figure 17.4-1 Serial transfer mode at transmission/reception mode
Data RAM region
#0
#1
#2
#5
#6
#7
SCK
#7 #6 #5 #4 #3 #2 #1 #0
SI
SO
SCK
SI
C K
SI
P
S Convert
O
SO
● Transmission mode
Figure 17.4-2 Serial transfer mode at transmission mode
Data RAM region
#0
#1
#2
#5
#6
#7
SCK
SO
#7 #6 #5 #4 #3 #2 #1 #0
SCK
C K
P
S Convert
O
SO
257
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 17 Serial I/O
■ Operation Mode of Serial I/O
In terms of the serial I/O operation mode, there are two types, namely, internal shift clock mode and
external shift clock mode depending on the shift clock type, and these are specified by the SCMR. Mode
switching and clock selection should be executed while the serial I/O is stopped (ST bit of SCR = 0).
● Internal shift clock mode
Operated by the internal clock, and outputs the shift clock with 50% duty from the SCK pin as the
synchronous timing output. In terms of data, 1-bit transfers are carried out per clock, and data for the
number of bytes that have been set for the SCBR is transferred sequentially at set intervals.
Figure 17.4-3 Interval mode
#0
#1
#2
#3
#4
#5
#6
#7
#0
#1
#2
SCK
SI
SO
Tclk
Tclk: Clock cycle
Tint: Interval
Tint
Figure 17.4-4 No interval mode
#3 #4 #5 #6 #7
#0
#1
#2
#0
#1
#7
SCK
SI
SO
Tclk
[Automatic transfer mode by chip select]
Setting "1" to chip select enable (CSE) bit enables control for the starting and stopping of transfers by
the chip select input (XCS) pin. When serial transfer starts at the falling of the XCS pin, and the XCS
pin rises before transfer for the number of bytes set has ended, serial transfer will be forcibly
terminated. When the XCS pin is "H" level, both the SCK and SO pins will have high impedance.
Figure 17.4-5 Chip select transfer mode
#0
#1
#2
#3
#4
#5
#6
#7
#0
#1
SCK
SO
start
stop
XCS
● External shift clock mode
Transfers 1-bit data per clock in synchrony with the external shift clock input from the SCK pin. Select
other than No Interval (IC1, 0=1, 1) as the interval specification in this case. When No Interval is selected,
communication cannot be carried out correctly.
Note:
258
Do not write SCR, SCMR, or SCBR during serial I/O operation under either mode.
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Interrupt Function
The serial I/O is set by the transfer end flag (SIF) bit when data transfer ends. In this case, the interrupt
request is generated. When termination (suspension) is executed by inputting chip select, the chip select
termination flag (CSAF) bit is set and an interrupt request is generated.
Figure 17.4-6 Interrupt generation timing
Internal Clock Mode 1 byte Transmission
#0 #1 #2 #3 #4 #5 #6 #7
SCK
SO
Transfer End Interruption
STB
(INT-REQ)SIF
External Clock Mode 1 byte Transmission
#0 #1 #2 #3 #4 #5 #6 #7
Transfer End Interruption
SCK
SO
(INT-REQ)SIF
Internal Clock Mode 1 byte Transmission
#0 #1 #2 #3 #4
SCK
SO
Forced End Interruption of XCS
XCS
CSAF
INT-REQ
■ Start/Stop Timing of Shift Operation
Writing "1" to the ST bit of the SCR initiates transfer, whereas writing "0" stops transfer. (When XCS input
is enabled, transfer does not start until the falling of the XCS pin is detected after writing "1" to the ST bit.)
When data transfer ends, clears the ST bit automatically to "0" and stops operation.
● Internal shift clock mode
Figure 17.4-7 Shift operation start/stop timing
At 1 byte Transmission end
#0 #1 #2 #3 #4 #5 #6 #7
SCK
SO
SIF
ST
At 1 byte Transmission suspend
#0 #1 #2 #3 #4 #5
SCK
SO
SIF
ST
259
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 17 Serial I/O
Figure 17.4-8 Shift operation start/stop timing by chip select
At 1 byte Transmission end
#0 #1 #2 #3 #4 #5 #6 #7
SCK
SO
XCS
SIF
CSAF
ST
At 1 byte Transmission suspend
#0 #1 #2 #3 #4
SCK
SO
XCS
SIF
CSAF
ST
● External shift clock mode
Figure 17.4-9 Shift operation start/stop timing by external clock
At 1 byte Transmission end
#0 #1 #2 #3 #4 #5 #6 #7
SCK
SO
SIF
ST
At 1 byte Transmission suspend
#0 #1 #2 #3 #4 #5
SCK
SO
SIF
ST
260
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 18 10-bit General-purpose Prescaler
18.1
Overview of 10-bit General-purpose Prescaler
The 10-bit general-purpose prescaler has built-in dedicated oscillation circuit and a load
function using the PPG output.
■ Feature of 10-bit General-purpose Prescaler
•
•
•
10-bit prescaler x 1ch (with square wave and pulse output)
Dedicated internal oscillation circuit
Includes load function driven by PPG output
■ Block Diagram of 10-bit General-purpose Prescaler
Figure 18.1-1 Block Diagram of 10-bit General-purpose Prescaler
(from FRC) 21/fch
23/fch
M
P
X
D
10bit Reload
Down Counter
26/fch
Q
M
P
X
PO Output
Osci-
PCK/OSCI
OSCO
llation
Circuit
GPRD
PPG-015
M
P
X
Synchronous
Reload Data Latch
Load
GPRD Reload Data Register
Write STB
INV
OM LDM PCS1 PCS0 ST GPRC
Internal Bus
■ Register List of 10-bit General-purpose Prescaler
Figure 18.1-2 Register list of 10-bit General-purpose Prescaler
15
8
7
0
bit
000030H
000032H
Address:
Prescaler Control Register
Data Register
GPRC
GPRDH
GPRDL
262
Download from Www.Somanuals.com. All Manuals Search And Download.
18.2
Register of 10-bit General-purpose Prescaler
The register configuration/functions of 10-bit general-purpose prescaler is shown.
■ Prescaler Control Register (GPRC)
Figure 18.2-1 Prescaler control register (GPRC)
bit
7
6
5
4
3
2
1
0
Initial value
--XX 0XX0B
INV
R/W
OM
R/W
LDM
R/W
PCS1
R/W
PCS0
R/W
ST
Address: 000031H
Access
R/W
[bit7, 6]:
There are unused bits.
[bit5]:INV
It is external clock input polarity selection bit.
Input through
0
1
Input inversion
[bit4]:OM
It is output mode selection bit.
Output reload pulse
0
1
Two-division output of reload pulse
[bit3]:LDM
It is update mode selection bit of reload data.
Update by writing data register
Update by both edges of PPG0 output (PO015)
0
1
[bit2, 1]:PCS1, 0
There are input clock select bits.
PCS1
PCS0
Selection Clock
Cycle (fch:@20MHz)
2 1/fch (FRC0)
2 3/fch (FRC2)
0
0
1
1
0
1
0
1
100 ns
400 ns
3.2 us
-
2 6/fch (FRC5)
External clock (PCK/OSCI)
263
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 18 10-bit General-purpose Prescaler
[bit0]:ST
It is operation enable bit.
Operation stop
0
1
Enabling operations
■ Data Register (GPRD)
Figure 18.2-2 Data Register (GPRDH)
bit
7
6
5
4
3
2
1
0
Initial value
Address: 000032H
Access
---- --XXB
D8
W
D9
W
Figure 18.2-3 Data Register (GPRDL)
bit
7
6
5
4
3
2
1
0
Initial value
XXXX XXXXB
Address: 000033H
Access
D7
W
D6
W
D5
W
D4
W
D3
W
D2
W
D1
W
D0
W
The division operation set to this register is performed. When "N" is set, the clock output frequency "fn" is
below.
fn =1/{Φ × (N+1)}
Use half-word access commands to write to this register. (Byte access command cannot be written.)
264
Download from Www.Somanuals.com. All Manuals Search And Download.
18.3
Operation of 10-bit General-purpose Prescaler
Division operation of the 10-bit general-purpose prescaler and updating operation of the
reload data latch are described.
■ Division Operation and PO Output
Figure 18.3-1 shows the operation of general-purpose prescaler.
Figure 18.3-1 Operation of general-purpose prescaler
Reload Data Latch
Count value
0000H
ST
PO output (Pulse)
PO output (1/2)
Figure 18.3-2 PO output timing
CLK
Count value
002
001
000
XXX
XXX-1
001
000
000
XXX
PO output (Pulse)
PO output (1/2)
■ Update Operation of Reload Data Latch
For updating operation of the reload data latch, there are two operation modes, namely updating by
rewriting the data register and updating at both edges of the PPG output. Switch operation mode can be
selected by the LDM bit of the GPRC.
● Update mode operation by rewriting data register
Under this mode, writing data register executes loading to the reload data latch. Newly loaded data
(division value) is changed to operation with new division value as soon as the division operation using the
previous value ends.
Update of the data register under this mode must be executed at an interval of "2 cycles of the clock
selected by the clock selection bit + 1 machine cycle" or more.
265
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 18 10-bit General-purpose Prescaler
Figure 18.3-3 Update timing of reload data latch
CLK
Data Register Value
Write STB
xx
nn
yy
Load Request
Load Timing
xx
nn
yy
Load Data Latch
Data update
disable period
● Update mode operation by both edges of PPG output
Under this mode, exactly the same operation as the update mode by rewriting the data register is carried out
except for detecting both edges of the PPG output and executing load requests per edge. When this mode is
selected, no load request is generated by rewriting the data register.
266
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 19 Bit Search Module
19.1
Overview of Bit Search Module
The bit search module detects 0, 1, or point of change for data written to the input
register, and returns the detected bit position.
■ Feature of Bit Search Module
•
Search for the bit position that first changes between 1 and 0 beginning from MSB or a word in one
cycle.
■ Block Diagram of Bit Search Module
Figure 19.1-1 Block Diagram of Bit search module
Input latch
Address
Decoder
Detection
mode
1 detection data
Bit search circuit
Detection result
■ Register List of Bit Search Module
Figure 19.1-2 Register list of Bit search module
31 16
bit
Address:
000003F0H
000003F4H
BSD0
BSD1
0 Detection Data Register
1 Detection Data Register
Change Point Detection Data Register
Detection Result Register
000003F8H
000003FCH
BSDC
BSRR
Note:
268
REALOS related hardware is used by the real time OS. Therefore, when REALOS is used, it cannot
be used under the user program.
Download from Www.Somanuals.com. All Manuals Search And Download.
19.2
Register of Bit Search Module
The register configuration/functions of bit search module is shown.
■ 0 Detection Data Register (BSD0)
Figure 19.2-1 0 detection data register (BSD0)
bit
31
16 15
0
Initial value
XXXX XXXXB
Address: 000003F0H
Access
W
•
•
•
•
The module detects 0 for the value written to this register.
The initial value by reset is irregular.
The read value is indeterminate.
Use 32-bit length data transfer command for data transfer (do not use 8-bit and 16-bit length data
transfer commands).
■ 1 Detection Data Register (BSD1)
Figure 19.2-2 1 detection data register (BSD1)
bit
31
16 15
0
Initial value
XXXX XXXXB
Address: 000003F4H
Access
R/W
•
•
Use 32-bit length data transfer command for data transfer (do not use 8-bit and 16-bit length data
transfer commands).
Write
The module detects 1 for the value written to this register.
•
Read
Saved data in the internal status of the bit search module is read. If the bit search module is used by the
interrupt handler, etc., it is used when the original status is saved/returned. In case of 0 detection, change
point detection, or even when data is written to the data register, save/return is possible by operating
only data register for 1 detection.
•
The initial value by reset is irregular.
■ Change Point Detection Data Register (BSDC)
Figure 19.2-3 Change point detection data register (BSDC)
bit
31
16 15
0
Initial value
XXXX XXXXB
Address: 000003F8H
Access
W
•
•
•
•
The module detects a change point for the value written to this register.
The initial value by reset is irregular.
The read value is indeterminate.
Use 32-bit length data transfer command for data transfer (do not use 8-bit and 16-bit length data
transfer commands).
269
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 19 Bit Search Module
■ Detection Result Register (BSRR)
Figure 19.2-4 Detection result register (BSRR)
bit
31
16 15
0
value
XXXX XXXXB
Address: 000003FCH
Access
W
•
•
The result of 0 detection, 1 detection or change detection is read from this register.
Which detection results are to be read is decided by the data register that was written last.
270
Download from Www.Somanuals.com. All Manuals Search And Download.
19.3
Operation of Bit Search Module
0 detection and 1 detection by the bit search module, and detection operation are
described.
■ 0 Detection
Scans data that was written to the data register for 0 detection from the MSB to LSB, and returns the
position where the first "0" was detected.
The detection result can be obtained by reading the detection result register.
Relationship between the detected position and numeric value to be returned is as per Table 19.3-1 .
When "0" does not exist (in other words, when the numeric value is FFFFFFFFH), a value of 32 is returned
as the search result.
[Execution example]
Figure 19.3-1 Execution example of 0 detection
Program data
Read data (decimal)
11111111111111111111000000000000B
11111000010010011110000010101010B
10000000000000101010101010101010B
11111111111111111111111111111111B
(FFFFF000H
(F849E0AAH
(8002AAAAH
(FFFFFFFFH
)
)
)
)
2 0
5
1
3 2
■ 1 Detection
Scans data that was written to the data register for 1 detection from the MSB to LSB, and returns the
position where the first "1" was detected.
The detection result can be obtained by reading the detection result register.
Relationship between the detected position and value to be returned is as per Table 19.3-1 .
When "1" does not exist (in other words, when the numeric value is 00000000H), a value of 32 is returned
as the search result.
[Execution example]
Figure 19.3-2 Execution example of 1 detection
Program data
Read data (decimal)
00100000000000000000000000000000B
00000001001000110100010101100111B
00000000000000111111111111111111B
00000000000000000000000000000001B
00000000000000000000000000000000B
(20000000H
(01234567H
(0003FFFFH
)
)
)
2
7
1 4
3 1
3 2
(00000001H
)
(00000000H
)
271
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 19 Bit Search Module
■ Change Point Detection
Scans data that was written to the data register for detecting the point of change from bit 30 to LSB, and
compares it with the MSB value. Returns the position where the value different from the MSB was first
detected.
The detection result can be obtained by reading the detection result register.
The detected position and value to be returned are as per Table 19.3-1 .
When the change point does not exist, value of 32 is returned.
In the change point detection, 0 is not returned as the detection result.
[Execution example]
Figure 19.3-3 Execution example of change point detection
Program data
Read data (decimal)
2
00100000000000000000000000000000H
00000001001000110100010101100111H
00000000000000111111111111111111H
00000000000000000000000000000001H
00000000000000000000000000000000H
11111111111111111111000000000000H
11111000010010011110000010101010H
10000000000000101010101010101010H
11111111111111111111111111111111H
(20000000B)
(01234567B)
(0003FFFFB)
(00000001B)
(00000000B)
(FFFFF000B)
(F849E0AAB)
(8002AAAAB)
(FFFFFFFFB)
7
1 4
3 1
3 2
2 0
5
1
3 2
Table 19.3-1 Bit position and value to be returned (decimal)
Detected bit Returned Detected bit Returned
Detected bit
position
Returned Detected bit
Returned
value
position
value
position
value
value
position
31
30
29
28
27
26
25
24
0
1
2
3
4
5
6
7
23
22
21
20
19
18
17
16
8
15
14
13
12
11
10
9
16
17
18
19
20
21
22
23
7
24
25
26
27
28
29
30
31
32
9
6
10
11
12
13
14
15
5
4
3
2
1
0
8
-
not exist
272
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Save/Return Processes
When the internal status of the bit search module needs to be saved/returned, for example using the bit
search module during interrupt handling, follow the procedure below.
1. Read the 1 detection data register and store the read data (Save).
2. Use the bit search module.
3. Write the data saved in step 1) to the 1 detection data register (Return).
As per the above operation, the value acquired when reading the detection result register for the next time is
in accordance with the contents written to the bit search module before 1). Even if the data register that was
written last is for 0 detection or change point detection, correctly returns by following the above procedure.
273
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 19 Bit Search Module
274
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 20 Wait Controller
20.1
Outline of Wait Control Section
The wait control section sets the access speed (wait number) for built-in memory.
■ Internal Memory Area
The internal memory area is as follows.
•
•
MB91191 series: address:0xC0000 to 0xfffff
MB91192 series: address:0x80000 to 0xfffff (However, access is disabled 0x80800 to 0x9ffff.)
■ Register List of Wait Controller
Figure 20.1-1 Register list of Wait controller
bit
7
0
Wait Control Register
WAITC
Address: 0007C4H
276
Download from Www.Somanuals.com. All Manuals Search And Download.
20.2
Wait Control Register (WAITC)
The configuration/functions of the wait control register are shown.
■ Wait Control Register (WAITC)
Figure 20.2-1 Wait Control Register (WAITC)
bit
7
6
5
4
3
2
1
0
Initial value
---- -000B
Address: 0007C4H
Access
WTC1
R/W
WTC0
R/W
W
[bit7 to 3]:
There are unused bits.
[bit2]:
Be sure to write "0".
[bit1, 0]:WTC1, 0
There are specification bits of wait count.
WTC1
WTC0
Wait count
at φ=fch/2
at φ=fch
0
0
1
1
0
1
0
1
0Wait(2cycle)
1Wait(3cycle)
Reserved
200 ns
Combination setting disable
300 ns
150 ns
-
-
-
-
Reserved
277
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 20 Wait Controller
278
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 21 Flash Memory
21.1
Overview of Flash Memory
The MB91F191A and MB91F192 devices have built-in flash memory that can erase all
sectors in a block and erase per sector using a single +3V power source, and write per
*1
half-word (16-bit) using a FR-CPU with 254-Kbyte (2-Mbit) / 384-Kbyte (3-Mbit)
capacities respectively.
■ Overview of Flash Memory
The function of this flash memory is the same as our 2Mbit (256K × 8 / 128K × 16) flash memory
MBM29LV200T (excluding some sector configuration), and writing from outside the device using a*2,
ROM writer is also possible.
In addition to the MBM29LV200T equivalent function, if it is used as built-in ROM of the FR-CPU,
command/data reading per word (32-bit) is possible, and high-speed operation can be realized.
*1
It is built-in flash memory of 3V operation 254 KByte
(MB91F191A)/384 KByte (MB91F192).
Combining a flash memory macro and FR-CPU interface circuit realizes the following functions.
•
•
CPU program/data storage memory function
- When this flash memory is used as ROM, 32-bit bus width access is enabled.
- Enables reading, writing, and erasing (auto program algorithm*3) using the CPU
Functions equivalent to those of the MB29LV200T (a flash memory product)
- Enables reading, writing, and erasing (auto program algorithm*3) using the ROM writer
This chapter describes use of this flash memory from the FR-CPU. Refer to the separate manual for the
ROM writer User’s Guide for details when using this flash memory from the ROM writer.
*1: The MBM29LV200T has 256 Kbytes, but a 2-Kbyte area overlaps with built-in RAM for the
MB91F191A, so use is impossible.
*2: The memory capacity of the MB91F192 is 384 Kbytes, but it is extended to be based on the
MBM29LV200T (256 Kbytes), so the function is the same.
*3: Automatic program algorithm=Embedded Algorithm TM
Embedded Algorithm TM is a registered trademark of Advanced Micro Devices, Inc.
280
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Block Diagram of Flash Memory
Figure 21.1-1 Block Diagram of Flash memory
Rasing edge
detection
RDY/BUSYX
RESETX
BYTEX
OEX
Flash Memory
Control signal
generation
WEX
CEX
FA18 to 0
DI15 to 0 DO 31 to 0
Address buffer
CA18 to 0
Data buffer
INTE
RDYINT
RDY
WE
CD31 to 0
FR-C Bus (Instruction/Data)
■ Register List of Flash Memory
Figure 21.1-2 Register list of Flash memory
bit
7
0
Flash Memory Status Register
(4bit)
FSTR
Address: 0007C0H
281
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 21 Flash Memory
■ Memory Map and Sector Construction
Address mapping of the flash memory differs when accessed from the FR-CPU and by the ROM writer*1.
This shows the mapping at accessing from the CPU.
Figure 21.1-3 Memory map and sector construction (MB91F191A)
31 MSB side 16bit16
LSB side 16bit 0
15
000FFFFE-FH
000FFFFC-DH
FFFFFFFFH
SA4(16Kbyte)
SA9(16Kbyte)
000F8002-3H
000F4002-3H
000F0002-3H
000F8000-1H
000F4000-1H
000F0000-1H
SA3(8Kbyte)
SA2(8Kbyte)
SA8(8Kbyte)
SA7(8Kbyte)
SA1(32Kbyte)
SA6(32Kbyte)
000E0002-3H
000E0000-1H
000FFFFFH
Flash memory region
Internal RAM region
000C0800H
000C0000H
SA0(63Kbyte)
SA5(63Kbyte)
Status register
Memory map
000007C0H
00000000H
000C0802-3H
000C0800-1H
Sector construction (SA=Sector address)
Table 21.1-1 Sector address table (MB91F191A)
Corresponding
bit position
Sector address
Address range
Sector capacity
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
000A0000-1h to 000BFFFC-Dh (MSB side 16-bit)
000C0000-1h to 000DFFFC-Dh (MSB side 16-bit)
000E0000-1h to 000EFFFC-Dh (MSB side 16-bit)
000F0000-1h to 000F3FFC-Dh (MSB side 16-bit)
000F4000-1h to 000F7FFC-Dh (MSB side 16-bit)
000F8000-1h to 000FFFFC-Dh (MSB side 16-bit)
000A0002-3h to 000BFFFE-Fh (LSB side 16-bit)
000C0002-3h to 000DFFFE-Fh (LSB side 16-bit)
000E0002-3h to 000EFFFE-Fh (LSB side 16-bit)
000F0002-3h to 000F3FFE-Fh (LSB side 16-bit)
Bit31 to 16
Bit31 to 16
Bit31 to 16
Bit31 to 16
Bit31 to 16
Bit31 to 16
Bit15 to 00
Bit15 to 00
Bit15 to 00
Bit15 to 00
64 Kbytes
64 Kbytes
32 Kbytes
8 Kbytes
8 Kbytes
16 Kbytes
64 Kbytes
64 Kbytes
32 Kbytes
8 Kbytes
282
Download from Www.Somanuals.com. All Manuals Search And Download.
Figure 21.1-4 Memory Map and Sector construction (MB91F192)
31 MSB side 16bit16
LSB side 16bit 0
15
000FFFFE-FH
000FFFFC-DH
FFFFFFFFH
SA5(16Kbyte)
SA11(16Kbyte)
000F8002-3H
000F4002-3H
000F0002-3H
000F8000-1H
000F4000-1H
000F0000-1H
SA4(8Kbyte)
SA3(8Kbyte)
SA10(8Kbyte)
SA9(8Kbyte)
SA2(32Kbyte)
SA8(32Kbyte)
000E0000-1H
000C0000-1H
000E0002-3H
000C0002-3H
000FFFFFH
SA1(64Kbyte)
SA7(64Kbyte)
Flash memory region
Internal RAM region
000A0000H
00080800H
00080000H
SA0(64Kbyte)
SA6(64Kbyte)
Status register
Memory map
000007C0H
00000000H
000A0002-3H
000A0000-1H
Sector construction (SA=Sector address)
Table 21.1-2 Sector address table (MB91F192)
Corresponding
bit position
Sector address
Address range
Sector capacity
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
000A0000-1h to 000BFFFC-Dh (MSB side 16-bit)
000C0000-1h to 000DFFFC-Dh (MSB side 16-bit)
000E0000-1h to 000EFFFC-Dh (MSB side 16-bit)
000F0000-1h to 000F3FFC-Dh (MSB side 16-bit)
000F4000-1h to 000F7FFC-Dh (MSB side 16-bit)
000F8000-1h to 000FFFFC-Dh (MSB side 16-bit)
000A0002-3h to 000BFFFE-Fh (LSB side 16-bit)
000C0002-3h to 000DFFFE-Fh (LSB side 16-bit)
000E0002-3h to 000EFFFE-Fh (LSB side 16-bit)
000F0002-3h to 000F3FFE-Fh (LSB side 16-bit)
000F4002-3h to 000F7FFE-Fh (LSB side 16-bit)
000F8002-3h to 000FFFFE-Fh (LSB side 16-bit)
Bit31 to 16
Bit31 to 16
Bit31 to 16
Bit31 to 16
Bit31 to 16
Bit31 to 16
Bit15 to 00
Bit15 to 00
Bit15 to 00
Bit15 to 00
Bit15 to 00
Bit15 to 00
64 Kbytes
64 Kbytes
32 Kbytes
8 Kbytes
8 Kbytes
16 Kbytes
64 Kbytes
64 Kbytes
32 Kbytes
8 Kbytes
8 Kbytes
16 Kbytes
*1: The mounted flash memory is little endian, but it is converted to big endian by the FR-CPU interface circuit. This
conversion function does not work during access by the ROM writer, so mapping is different from CPU mode.
283
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 21 Flash Memory
21.2
Flash Memory Status Register (FSTR)
The flash memory status register (FSTR) indicates the flash memory operation status.
■ Flash Memory Status Register (FSTR)
Figure 21.2-1 Flash memory status register (FSTR)
bit
7
6
5
4
RDY
R
3
2
1
0
Initial value
000- ---0B
INTE
R/W
RDYINT
R/W
WE
R/W
Address: 007C0H
Access
R/W
It is a register that indicates the operation status of flash memory.
Controls interrupts to the CPU and writing to the flash memory.
It can be accessed only by CPU. It cannot be accessed at mounting the writer.
Do not use the read modify write command to access this register.
[bit 7]: INTE
Controls generation of interrupts when auto algorithm (write, erase, etc.) of the flash memory ends.
0
1
Disables auto algorithm termination interrupt output. (Initial value)
Enables auto algorithm termination interrupt output.
Be initialized to "0" when resetting.
This bit can be read and written.
[bit 6]: RDYINT
It will be "1" when the auto algorithm (write, erase, etc.) of the flash memory ends.
The auto algorithm termination interrupt request is generated if this bit becomes "1" when interrupt
generation is enabled by specifying bit7:INTE= "1".
Be initialized to "0" when resetting.
This bit can be read and written. However, "0" only is possible for writing, and even if "1" is written,
the bit value will not be changed.
[bit 5]: WE
Controls the writing data and command to the flash memory under the CPU mode.
While this bit is "0", writing data and command to the flash memory will be invalid. Reading data from
the flash memory will be 32-bit access.
While this bit is "1", writing data and command to the flash memory will be valid, and initiation of the
auto algorithm is enabled. However, reading data from the flash memory will be 16-bit access, and 32-
bit access is impossible. So during this period, it cannot be used as the program memory.
This bit must be re-written after confirming the auto algorithm (write/erase) is stopped by the RDY bit.
While the RDY bit is "0", the value of this bit cannot be re-written.
284
Download from Www.Somanuals.com. All Manuals Search And Download.
0
1
Disables writing to the flash memory and enables 32-bit reading [Initial
value]
Enables writing to the flash memory and disables 32-bit reading
(programming mode)
Be initialized to "0" when resetting.
This bit can be read and written.
[bit 4]:RDY
This bit indicates the operation status of the auto algorithm (write/erase).
While this bit is "0", writing or erasing is carried out by the auto algorithm, and new write or erase
commands cannot be received. Data cannot be read from the flash memory address. The read data
indicates the flash memory status.
0
1
During writing/erasing, commands that read, write, and erase data
cannot be received.
Commands that read, write, and erase data can be received.
This bit is not initialized at reset. (It conforms the status of flash memory at that time.)
Read is only possible. Writing does not affect the value of this bit.
[bit 3 to 1]:(reserved bit)
There are reserved bit. The read value is irregular, and write operation does not affect.
[bit 0]:(reserved bit)
It is reserved bit. These bits indicate "0" when read. Always write "0" to this bit. Writing "1" does not
guarantee.
Be initialized to "0" when resetting.
Always write "0". These bits indicate "0" when read.
285
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 21 Flash Memory
21.3
Operation of Flash Memory
When accessed by the FR-CPU, the following two types of access mode exist.
• ROM mode: Word (32-bit) length data can be read in blocks, but not written.
• Programming mode: Word (32-bit) length access is disabled, but writing in half-word
(16-bit) lengths is enabled.
■ FR-CPU ROM Mode (32-bit, Read Only)
This mode functions as the internal ROM of FR-CPU. Enables word (32-bit) length data to be read in
blocks, but cannot write to the flash memory or initiate auto algorithm.
● Mode specification method
•
•
•
This mode is on when the "WE" bit of the flash memory status register is "0".
When the CPU is in operation, it always enters this mode after the reset has been released.
When the CPU is not in operation, it cannot enter this mode.
● Operation content
•
•
When reading the flash memory area, word (32-bit) length data is read from the memory in blocks.
The number of cycles required to read data is 2 cycles per word (1 wait). Using this enables commands
to be supplied to the FR-CPU without waiting.
● Restrictions
•
•
•
The address allocation method and endian type differ from writing the ROM writer.
Under this mode, neither command nor data can be written to the flash memory.
When setting the gear cycle of the CPU system to source oscillation x1, 1 Wait must be specified by the
Wait control section before setting.
■ FR-CPU Programming Mode (16-bit, Read/Write)
This mode is enabled erasing/writing data. Access of word (32-bit) length data in blocks is impossible, so
while operation is carried out under this mode, program execution on the flash memory is impossible.
● Mode specification method
•
•
This mode is on when the "WE" bit of the flash memory status register is "1".
When the CPU is in operation, the "WE" bit becomes "0" after the reset has been released. Write "1" to
use this mode. Returns to ROM mode when the "WE" bit becomes "0" by rewriting "0" or generating a
reset.
•
The "WE" bit cannot be rewritten while the "RDY" bit of the flash memory status register is "0".
Rewrite the "WE" bit after confirming that the "RDY" bit has changed to "1".
● Operation content
When reading the flash memory area, half-word (16-bit) length data is read from the memory in blocks.
•
286
Download from Www.Somanuals.com. All Manuals Search And Download.
The number of cycles taken for reading is 2 cycles per half-word (1 wait).
•
Writing command to the flash memory enables the auto algorithm to be initiated. Initiating auto
Algorithm (Embedded Algorithm TM)" for details of the auto algorithm.
● Restrictions
•
•
•
The address allocation method and endian type differ from writing the ROM writer.
Under this mode, reading data of word (32-bit) length is disabled.
When setting the gear cycle of the CPU system to source oscillation x 1, 1 Wait must be specified by the
Wait control area before setting.
■ Auto Algorithm Execute State
When auto algorithm is initiated under CPU programming mode, the auto algorithm operation status can be
identified by the internal ready/busy signal (RDY/BUSYX). This ready/busy signal level can be read as the
"RDY" bit of the flash memory status register.
While the "RDY" bit is "0", writing or erasing is carried out by the auto algorithm, and no new write or
erase commands can be received. Also, data cannot be read form the flash memory address.
The data read while the "RDY" bit is "0" is the hardware sequence flag indicating the flash memory status.
■ Interrupt Control
Interrupt request can be generated to the CPU by the exit sequence of the auto algorithm. By doing this, the
end of prolonged auto algorithm sequences can be known immediately.
Auto algorithm exit interrupt is controlled by the "RDYINT" and "INTE" bit of the flash memory status
register.
"RDYINT" bit is the auto algorithm termination interrupt flag. When detecting the rising edge of "0" from
"1" of the internal ready/busy signal (RDY/BUSYX), sets to "1". When the "INTE" bit is "1", if the
"RDYINT" bit is set, an interrupt request is output to the CPU.
Write "0" to the "RDYINT" bit or "INTE" bit to cancel the interrupt request.
287
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 21 Flash Memory
21.4
Flash Memory Auto Algorithm (Embedded Algorithm TM)
Writing or erasing of the flash memory cell is carried out by initiating the auto algorithm
stored by the flash memory itself.
■ Command Operation
In order to initiate the auto algorithm, execute continuous writing of half-word (16-bit) data for 1 to 6 times
to the flash memory. This is called a command.
If an invalid address or data is written, or the address and data are written in the wrong order, the flash
memory is reset to read mode.
Table 21.4-1 lists the command.
Table 21.4-1 Command sequence table
1 Writing Cycle
2 Writing Cycle
Address Data
3 Writing Cycle
Address Data
4 Writing Cycle
5 Writing Cycle
Address Data
6 Writing Cycle
Address Data
Command
sequence
Access numbers
Address
Data
Address
Data
XXXXXXXXH F0F0H
Read/Reset
Read/Reset
Program
1
4
4
6
6
-
-
-
-
-
-
-
000F5556H
000F5556H
000F5556H
000F5556H
AAAAH 000EAAAAH 5555H 000F5556H F0F0H
AAAAH 000EAAAAH 5555H 000F5556H A0A0H
RA
PA
RD
PD
000EAAAAH 5555H
1010H
3030H
000E5556H
AAAAH 000EAAAAH 5555H 000F5556H 8080H 000F5556H AAAAH 000EAAAAH 5555H
Chip Erasing
Sector Erasing
SA
AAAAH 000EAAAAH 5555H 000F5556H 8080H 000F5556H AAAAH
-
-
-
-
-
-
XXXXXXXXH B0B0H
XXXXXXXXH 3030H
Sector Erasing being Suspended
Sector Erasing being Restarted
-
-
-
-
-
-
*: Commands must be issued by writing half-words under the FR-CPU programming mode.
RA: Read address /RD: Read data
PA: Write address/PD: Write data
SA: Sector address (specification of any address in the sector. Refer to Table 21.1-1 and Table 21.1-2 )
Erase suspension command (B0H) and erase restart command (30H) are only valid while erasing the sector.
Two types of reset command can reset the flash memory to read mode.
288
Download from Www.Somanuals.com. All Manuals Search And Download.
● Read (Read)/Reset command
In order to return from timing limit excess to read mode, issue the read/reset command sequence. Reads
data from the flash memory with the read cycle. The flash memory retains the read status until another
command is input.
The flash memory is automatically read/reset when the power is turned on. In this case, the data read
command in unnecessary.
● Program (Write)
Under CPU programming mode, writing is basically carried out per half-word. Writing requires four bus
cycles. There are two "unlock" cycles for the command sequence, and the writing set up command and
writing data cycle continue. Starts writing to the memory at the last writing cycle.
After executing the auto writing algorithm command sequence, the flash memory no longer requires
external control. The flash memory generates the appropriate write pulse automatically created within it,
and verifies the margin of the written cell. The auto writing operation ends when the bit 7 data matches the
data written to this bit by the data polling function (refer to "21.5 Auto Algorithm Execute State -
Hardware sequence flag"), takes this opportunity to return to read mode, and will not receive writing
addresses any longer. As a result, the flash memory requests the next valid address at this stage. In this
manner, data polling indicates that the memory is being written.
During writing, all commands written to the flash memory are ignored. If address data exists while
hardware reset is initiated at writing, such data cannot be guaranteed.
Writing is enabled in any address order or even if the sector boundary is exceeded. Data "0" cannot be
returned to data "1" by writing. If data "1" is written to data "0", the element is determined as defective by
the data polling algorithm, or it appears to be written as data "1". However, when data is read under the
reset/read mode, the data remains as "0". Data 0 can be changed to data 1 at the erase operation only.
● Chip Erasing
Chip erase (erasing all sectors in blocks) is carried out by accessing for six times. Firstly, two "unlock"
cycles exist, and continuously, the "set up" command is written. Until the chip erase command, two more
"unlock" cycles continue.
During a chip erase operation, the user does not need to write data to the flash memory prior to erasing.
While executing the auto erase algorithm, the flash memory automatically writes "0" patterns and verifies
before erasing all cells (pre-programmed). During this operation, the flash memory does not require
external control.
Auto erase starts by writing within the command sequence, ends when bit 7 becomes "1", and the flash
memory returns to read mode at this stage. The chip erasure time will be [time for sector erase x total
number of sectors + time for writing chip (preprogrammed)].
289
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 21 Flash Memory
● Sector Erasing
Sector erase requires six access cycles. Two "unlock" cycles exist, and the "set up" command is written
continuously, then two more "unlock" cycles follow, and erasure of the sector starts by inputting the sector
erase command at the sixth cycle. The next sector erase command can be received during the 50µs time-out
from writing the last sector erase command.
Multiple sector erase can be simultaneously received by writing six bus cycles as mentioned before. This
sequence is carried out by continuously writing the sector erase command (30H) at the sector address to be
erased simultaneously. Erasing the sector starts on exiting the 50 µs time-out period from writing the last
sector erase command. In other words, when a number of sectors are erased simultaneously, the next sector
to be erased must be input within 50 µs. If it is input after that, the command may not be received. Whether
or not the sector erase command followed is valid can be monitored by bit 3. (Refer to "21.5 Auto
Algorithm Execute State - Hardware sequence flag" for details). Resets the sector erase command during
the time-out or any command other than erase suspension to read, and ignores the previous command
sequence. In this case, erasure is completed by re-erasing the sector. The sector address can be input to the
sector erase buffer from any combination and number (0 to 6).
For sector erasure, the user does not need to write to the flash memory before erasing. The flash memory
writes to all cells within the sector to be erased automatically (preprogrammed). Other sectors not to be
erased are unaffected while erasing the sector. During these operations, the flash memory does not require
external control.
Auto sector erase starts after the 50µs time-out period from writing the last sector erase command. When
the bit 7 data becomes "1" (refer to "21.5 Auto Algorithm Execute State - Hardware sequence flag" for
details), it ends and the flash memory returns to read mode. Other commands are ignored. Data polling is
activated at any address within the erased sector. Time for erasing multiple sectors will be [(time for
erasing the sector + time for writing the sector (preprogrammed)) x number of sectors to be erased].
290
Download from Www.Somanuals.com. All Manuals Search And Download.
● Temporary deletion suspension
The erase suspension command suspends the auto algorithm of the flash memory while erasing the sector
by user, and enables data from sectors not being erased to be read/written. This command is only valid
while erasing sectors, and is ignored while erasing and writing chips. The erase suspension commands
(BOH) are only valid while erasing sectors that include sector erase time-out periods after sector erase
commands (30H). When this command is input during the time-out period, time-out ends immediately, and
the erasure operation is suspended. When the erase restart command is written, erasure operation restarts.
Any address is acceptable when inputting the command that suspends erase and the command that restarts
erase.
If the erase suspension command is input while erasing the sector, it takes a maximum of 20 µs for the flash
memory to stop the erasure operation. When the flash memory enters erase suspension mode, the ready/
busy output and bit 7 output are "1", and bit 6 stops toggling. Whether the erasure operation has stopped or
not can be checked by inputting the address of the sector that is being erased and monitoring values read by
bits 6 and 7. Writing of the erase suspension command is also ignored.
Once the erasure operation stops, the flash memory enters erase suspension/read mode. Under this mode,
reading data is valid for sectors in which data erasure is not suspended, but it is same as standard reading
for others. During reading erase suspension, bit 2 toggles to continuous reading from the sector whose
details).
After entering erase suspension reading mode, the user can write to the flash memory by writing a write
command sequence. This writing mode becomes the erase suspension writing mode. Writing under this
mode is validated for sectors in which data erasure is not suspended, but for others, it is the same as writing
normal bytes. Under erase suspension writing mode, bit 2 toggles for continuous reading from the sector
whose erasure was suspended. The erase suspension bit can be used to detect this operation. Notes on use,
bit 6 can read any address, but bit 7 must read the written address.
In order to restart the sector erase operation, the restart command (30H) must be input. In this case,
inputting of the restart command is ignored. On the other hand, the erase suspension command can be input
after the flash memory restarts erasing.
291
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 21 Flash Memory
21.5
Auto Algorithm Execute State
This flash memory has hardware that notifies the internal flash memory operation
status and operation completion for outside of the flash memory to execute the write/
erase flow by auto algorithm. One is a hardware sequence flag, and the other is the
ready/busy signal.
■ Ready/Busy Signal (RDY/BUSYX)
The flash memory has a ready/busy signal as well as a hardware sequence flag as a means to notify whether
the internal auto algorithm is being executed or has finished. This ready/busy signal is connected to the
flash memory interface circuit, and can be read as the "RDY" bit of the flash memory status register.
Interrupt requests can be also generated to the CPU by the rising of the ready/busy signal. (Refer to "21.2
Flash Memory Status Register (FSTR)" for details).
When the read value of the "RDY" bit is "0", the flash memory is being written on or erased. In this case,
neither write nor erase commands will be accepted. When the read value of the "RDY" bit is "1", the flash
memory is on wait state to be read/written on or erased.
■ Hardware Sequence Flag
Figure 21.5-1 Hardware sequence flag
bit
15
8 7
0
0
(Indeterminate)
Hardware sequence flag
Hardware sequence flag
At read Halfword
bit
7
At read Byte (Only odd number address)
*: Word reading is disabled. (Only to be used under FR-CPU programming mode.)
The hardware sequence flag can be acquired as data by reading any address (odd addresses in the case of
byte access) of the flash memory while executing auto algorithm. There are 5 valid bits of data, each of
them expresses the auto algorithm status.
Figure 21.5-2 Hardware sequence flag (At Half word, Byte access)
bit
7
6
5
4
3
2
1
0
Indeterminate
Indeterminate Indeterminate
DPOLL TOGGLE TLOVER
SETIMR TOGGL2
These flags are meaningless in FR-CPU ROM mode. Half-word or byte reading must be carried out under
FR-CPU programming mode only.
292
Download from Www.Somanuals.com. All Manuals Search And Download.
Table 21.5-1 State list of hardware sequence flag
State
DPOLL
TOGGLE TLOVER SETIMR TOGGL2
Automatic Writing operation
Automatic Erasing operation
Erase suspension read (sectors in
Reverse Data
0
Toggle
Toggle
0
0
0
1
1
Toggle
Toggle *1
Data
1
1
0
Data
0
0
Data
0
erase suspension)
Executing
Erase
Erase suspension read (sectors not
in erase suspension)
mode
suspension
Data
Data
Erase suspension write (sectors
not in erase suspension)
Toggle *2
1 *3
Reverse Data
Automatic Writing operation
Reverse Data
Toggle
Toggle
Toggle
1
1
1
0
1
1
1
Time limit
Automatic Erasing operation
exceeded
0
0
Undefined
Undefined
Write operation at erase suspension
*1: Bit 2 toggles when reading continuously from the erase suspension sector.
*2: Bit 6 toggles even when reading continuously from any address.
*3: During writing erasure suspension, bit 2 will be "1" when reading the address that is being written.
However, bit 2 toggles when reading continuously from sectors in which erasure is suspended.
[bit 7]:DPOLL=Data polling
[bit 6]:TOGGLE=Toggle bit
[bit 5]:TLOVER=Time limit exceeded
[bit 3]:SETIMR=Sector erasing timer
[bit 2]:TOGGL2=Toggle bit 2
Each bit is briefly described below:
[bit 7]:DPOLL (Data polling)
293
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 21 Flash Memory
● Automatic Writing operation
When reading is carried out while executing the auto write algorithm, the flash memory outputs the
reversed data of the data that was last written to bit 7. When read access is carried out once the auto write
algorithm is completes, the flash memory outputs bit 7 of the read data at the address indicated by the
address signal.
● Automatic Erasing operation
While executing the auto erase algorithm, if reading is carried out, the flash memory outputs "0" regardless
of the address indicated by the address signal. In the same way, "1" is output when it ends.
● Sector erasing being suspended
When reading is carried out while sector deletion is suspended. The flash memory outputs "1" if the address
indicated by the address signal belongs to the sector during deletion. If it does not belong to the sector
during deletion, the read value "bit 7" of the address indicated by the address signal is output. Whether the
sector status is erase suspended or not, and which sector is being erased, can be determined by referring to
the toggle bit of bit 6 mentioned later.
Note:
When the auto algorithm operation approaches the end, bit 7 (data polling) will be changed
asynchronously during reading. This indicates that the flash memory sends information about its
operating status to bit 7, and sends the defined data to the next one. Even when the flash memory
finishes the auto algorithm, and bit 7 outputs the defined data, other bits are not defined yet. Defined
data of other bits are read continuously.
[bit 6]:TOGGLE (Toggle bit)
● Auto writing or erasing operation
While executing the auto writing or erase algorithm, if reading continuously, the flash memory outputs the
results while setting "1" and "0" as toggles to bit 6. When the auto writing or erase algorithm ends, toggling
of bit 6 is stopped for continuous reading, and valid data is output. Toggle bit is validated after the last
writing cycle of each command sequence is executed.
If writing is attempted, but the sector to be written on is protected from being overwritten, after toggling for
about 2 µs, toggling ends without rewriting the data. In terms of erasing, if all selected sectors are protected
from being overwritten, the toggle bit toggles for about 100 µs, and then returns to read mode without
rewriting any data.
● Sector erasing being suspended
When reading is carried out while sector deletion is suspended, the flash memory outputs "1" if the address
indicated by the address signal belongs to the sector during deletion. Outputs bit 6 of the read value of the
address indicated by the address signal, if it does not belong to the sector being erased.
[bit 5]:TLOVER (Time limit exceeded)
294
Download from Www.Somanuals.com. All Manuals Search And Download.
● Auto writing or erasing operation
Bit 5 indicates that execution of the auto algorithm is exceeded the time prescribed within the flash memory
(number of internal pulse times). Bit 5 outputs "1" under this status. In other words, when this flag outputs
"1" while the auto algorithm is operating, it indicates that writing or deletion has failed.
Attempts to write bit 5 to non-blank areas without prior erasure may cause failure. In this case, defined data
cannot be read from bit7 (data polling), and bit6 (toggle bit) will continuously toggle. Under this status, if
the time limit is exceeded, "1" will be output to bit 5. Please note that this indicates that the flash memory
was not used correctly rather than any defect with the flash memory. If this event occurs, the reset
command should be executed.
[bit 3]:SETIMR (Sector erasing timer)
● Sector erase operation
After the first sector deletion command sequence is executed, the waiting period for sector deletion is
indicated. Bit 3 outputs "0" during this period, and "1" if the sector erase wait period is exceeded. The data
polling and toggle bits are validated after executing the first sector deletion command sequence.
When "1" is set in this flag while the data polling or toggle bit function indicates that the erase algorithm is
being executed, an internally controlled erase operation has started. Writing of continuous command is
ignored until the data polling or toggle bit indicates the erase termination. (Input of deletion suspension
code only is accepted.)
If this flag is "0", the flash memory accepts the additional sector deletion code to be written. For
confirmation, using software to check this flag status prior to writing the sector erase code is recommended.
If "1" is shown at the 2nd status check, the additional sector deletion code may not have been accepted.
When reading is carried out while sector deletion is suspended. The flash memory outputs "1" if the address
indicated by the address signal belongs to the sector during deletion. If it does not belong to the sector
during deletion, the read value "bit 3" of the address indicated by the address signal is output.
[bit 2]:TOGGL2 (toggle bit 2)
● Sector erase operation
This toggle bit is used to detect whether the flash memory is in auto deletion or suspension of deletion
status in addition to the toggle bit of bit 6. Bit 2 operates the toggle when continuously reading from the
sectors that have been deleted during auto deletion. If the flash memory is under deletion suspension
reading mode, bit 2 operates the toggle by continuously reading from the sector in which deletion is
suspended.
If the flash memory is under deletion suspension reading mode, "1" is read by bit 2 by continuously reading
from the sector in which deletion is not suspended. In contrast to bit 2, bit 6 toggles only during normal
writing, erasing, or erase suspension writing.
For example, bits 2 and 6 are used together to detect the erase suspension reading mode. (Bit 2 toggles,
whereas bit 6 does not.)
Bit 2 is also used to detect the deleted sectors. When the flash memory is being deleted, bit 2 operates the
toggle if reading from the deleted sector.
295
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 21 Flash Memory
296
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix
Details that could not be described within the body text,
such as I/O map, interrupt vector, peripheral circuit
measurement speed, restrictions and commands list for
use of the MB91191/MB91192 series are described in the
appendix.
297
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix A I/O Map
Appendix A I/O Map
built into the MB91191/MB91192 series.
■ I/O Map
Table A-1 I/O Map
Address
00000H
Register Name
Port 3 data register
Access
R/W
Register
PDR3
Initial value
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
---- ---XB
00001H
00002H
00003H
00004H
00005H
00006H
00007H
00008H
00009H
0000AH
0000BH
0000CH
0000DH
0000EH
0000FH
00010H
00011H
00012H
00013H
00014H
00015H
00016H
00017H
00018H
00019H
0001AH
0001BH
0001CH
0001DH
0001EH
0001FH
Port 2 data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
PDR2
PDR1
PDR0
PDR7
PDR6
PDR5
PDR4
DDR3
DDR2
DDR1
DDR0
DDR7
DDR6
DDR5
DDR4
PDRB
PDRA
PDR9
PDR8
Port 1 data register
Port 0 data register
Port 7 data register
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
0000 0000B
Port 6 data register
Port5 data register
Port 4 data register
Port 3 data direction register
Port 2 data direction register
Port 1 data direction register
Port 0 data direction register
Port 7 data direction register
Port 6 data direction register
Port 5 data direction register
Port 4 data direction register
Port B data register
0000 0000B
W
0000 0000B
W
0000 0000B
W
---- ---0B
W
0000 0000B
W
0000 0000B
W
0000 0000B
W
XXXX XXXXB
XXXX XXXXB
---X XXXXB
XXXX XXXXB
R/W
R/W
R/W
R/W
Port A data register
Port 9 data register
Port 8 data register
Reserved
XXXX XXXXB
XXXX XXXXB
0000 0000B
Port D data register
R/W
R/W
W
PDRD
PDRC
DDRB
DDRA
DDR9
DDR8
Port C data register
Port B data direction register
Port A data direction register
Port 9 data direction register
Port 8 data direction register
0000 0000B
W
---0 0000B
W
0000 0000B
W
0000 0000B
0000 0000B
Port D data direction register
Port C data direction register
W
W
DDRD
DDRC
298
Download from Www.Somanuals.com. All Manuals Search And Download.
Table A-1 I/O Map
Address
Register Name
Port B input enable register
Access
Register
PIEB
Initial value
0000 0000B
0000 0000B
---0 0000B
00020H
00021H
00022H
00023H
00024H
00025H
00026H
00027H
W
Port A input enable register
W
W
W
PIEA
PFS9
PFS8
Port 9 function selection register
Port 8 function selection register
0000 0000B
Reserved
0000 0000B
0000 0000B
Port D function selection register
Port C function selection register
W
W
PFSD
PFSC
00028H to
0002FH
Reserved
00030H
00031H
00032H
00033H
00034H
00035H
00036H
00037H
00038H
00039H
0003AH
0003BH
0003CH
0003DH
0003EH
0003FH
00040H
00041H
00042H
00043H
00044H
00045H
00046H
00047H
00048H
00049H
0004AH
0004BH
0004CH
0004DH
Reserved
--XX 0XX0B
---- --XXB
10 bit General-purpose prescaler control register
R/W
W
GPRC
GPRD
10 bit General-purpose prescaler data register
XXXX XXXXB
X100 0001B
RTG0 Control Register
R/W
R/W
RTG0C
RTG0D
---X XXXXB
XXXX XXXXB
XXXX XXXXB
X100 0001B
RTG0 Output data register
RTG0 Timing data register
W
RTG0T
RTG1 Control Register
R/W
R/W
RTG1C
RTG1D
---X XXXXB
XXXX XXXXB
XXXX XXXXB
X100 0001B
RTG1 Output data register
RTG1 Timing data register
W
RTG1T
RTG2 Control Register
R/W
R/W
RTG2C
RTG2D
---X XXXXB
XXXX XXXXB
XXXX XXXXB
RTG2 Output data register
RTG2 Timing data register
W
RTG2T
Reserved
0--- 00X0B
PWM0 Control Register
R/W
W
PWM0C
---- XXXXB
PWM00 Data Register
PWM01 Data Register
PWM02 Data Register
PWMD00
XXXX XXXXB
---- XXXXB
W
W
PWMD01
PWMD02
XXXX XXXXB
---- XXXXB
XXXX XXXXB
Reserved
0--- 00X0B
PWM1 Control Register
R/W
W
PWM1C
---- XXXXB
PWM10 Data Register
PWM11 Data Register
PWMD10
XXXX XXXXB
---- XXXXB
W
PWMD11
XXXX XXXXB
299
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix A I/O Map
Table A-1 I/O Map
Address
Register Name
Access
Register
Initial value
---- XXXXB
0004EH
PWM12 Data Register
W
PWMD12
0004FH
00050H
00051H
00052H
00053H
00054H
00055H
00056H
00057H
00058H
00059H
0005AH
0005BH
0005CH
0005DH
0005EH
0005FH
00060H
00061H
00062H
00063H
00064H
00065H
00066H
00067H
00068H
00069H
0006AH
0006BH
0006CH
0006DH
0006EH
0006FH
00070H
00071H
00072H
00073H
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
X1X0 ---0B
Capstan input control register
Capstan mask timer control register
Capstan control register
R/W
R/W
R/W
R/W
R/W
R/W
CAPDVC
CAPMTC
CAPC
X1X0 0X10B
---- XXXXB
Dram control register
DRMC
Dram input control register
Dram mask timer control register
Reserved
DRMDVC
DRMMTC
XXXX XXXXB
X1X0 X1X0B
Reel control register
R/W
R/W
R/W
R/W
R/W
RLC
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
Reel 0 input control register
Reel 0 mask timer control register
Reel 1 input control register
Reel 1 mask timer control register
RL0DVC
RL0MTC
RL1DVC
RL1MTC
Reserved
Reserved
XXXX XXXXB
XXXX XXXXB
XXXX X000B
X10- -000B
R
FRCD2
FRCD1
FRCD0
CIC1
FRC count data register
R
R
R/W
R/W
Capture input control register
0000 0000B
CIC0
Reserved
---- 0100B
Capture control register
Capture source register
R/W
R
CAPC
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
CAPS
CAPD2
CAPD1
CAPD0
Capture data register
R
PPG0 Timing data register
PPG1 Timing data register
16 bit Timer 0 count data register
16 bit Timer 0 data register
W
PPG0T
PPG1T
T0CD
T0DR
W
R
R/W
300
Download from Www.Somanuals.com. All Manuals Search And Download.
Table A-1 I/O Map
Address
Register Name
Access
R/W
Register
T0CR
Initial value
0--- -1X0B
00074H
16 bit Timer 0 Control Register
16 bit Timer 1 Control Register
16 bit Timer 1 count data register
16 bit Timer 1 data register
00075H
00076H
00077H
00078H
00079H
0007AH
0007BH
0007CH
0007DH
0007EH
0007FH
00080H
00081H
00082H
00083H
00084H
00085H
00086H
00087H
00088H
00089H
0008AH
0008BH
0008CH
0008DH
0008EH
0008FH
00090H
00091H
00092H
00093H
00094H
00095H
00096H
00097H
00098H
00099H
---0 0000B
0--- -1X0B
R/W
R
T1CR
T1CD
T1DR
T2CD
T2DR
T2CR
T3CR
T3CD
T3DR
T4CD
T4DR
T4CR
---0 0000B
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
0--- -1X0B
R/W
R
16 bit Timer 2 count data register
16 bit Timer 2 data register
R/W
R/W
R/W
R
16 bit Timer 2 Control Register
16 bit Timer 3 Control Register
16 bit Timer 3 count data register
16 bit Timer 3 data register
---0 0000B
0--- -1X0B
---0 0000B
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
0--- -1X0B
R/W
R
16 bit Timer 4 count data register
16 bit Timer 4 data register
R/W
R/W
R/W
R/W
R
16 bit Timer 4 Control Register
8/16 bit Timer / Counter control register
8/16 bit Timer / Counter data register
8/16 bit Timer / Counter count data register
---0 0000B
010- 0000B
T5CR1
T5CR0
T5DR1
T5DR0
T5CD1
T5CD0
PWCC
PWCD
KEYC
KEYS
EIE
0100 0000B
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
0--- 0X00B
8 bit PWC control register
8 bit PWC Data Register
R/W
R
XXXX XXXXB
0000 0000B
Key input Control Register
Key input Status Register
External interrupt enable register
External Interrupt request flag
R/W
R
XXXX XXXXB
0000 111-B
R/W
R
---- XXXXB
EIF
301
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix A I/O Map
Table A-1 I/O Map
Address
0009AH
Register Name
Access
Register
Initial value
0009BH
0009CH
Reserved
0009DH
0009EH
0009FH
000A0H
000A1H
000A2H
000A3H
000A4H
000A5H
000A6H
000A7H
000A8H
000A9H
000AAH
000ABH
000ACH
000ADH
000AEH
000AFH
XXX0 0000B
000- -XXXB
0000 0000B
0000 0000B
R
R
ADCH
A/DC Control Register
ADCL
R/W
R/W
A/DC Soft conversion analog input selection
register
SCIS
Reserved
X10- -001B
Soft conversion Status Register
R/W
R
SCSR
SCFD
XXXX --XXB
XXXX XXXXB
A/DC Soft conversion FIFO data register
Reserved
X10- -001B
A/DC Hard conversion Status Register
R/W
R
HCSR
HCFD
XXXX --XXB
XXXX XXXXB
A/DC Hard conversion FIFO data register
Reserved
000B0H to
001FFH
00200H to
002FFH
XXXX XXXXB
XXXX XXXXB
XXXX XXXXB
PPG0 Data RAM
R/W
R/W
R/W
-
-
-
00300H to
0037FH
Serial 0 Data buffer RAM
PPG1 Data RAM
00380H to
003BFH
003C0H
003C1H
003C2H
003C3H
003C4H
003C5H
003C6H
003C7H
003C8H
003C9H
0000 X100B
PPG0 Control Register
R/W
R/W
PPG0C
XXXX XXXXB
PPG0 start address setting register
PPG0SA
Reserved
0000 X100B
PPG1 Control Register
R/W
R/W
PPG1C
XXXX XXXXB
PPG1 start address setting register
PPG1SA
Reserved
0100 1000B
Serial control register
R/W
R/W
S0CR
S0MR
--0X XXXXB
Clock Mode setting register
302
Download from Www.Somanuals.com. All Manuals Search And Download.
Table A-1 I/O Map
Address
Register Name
Address offset register
Access
Register
S0AO
Initial value
-000 0000B
003CAH
003CBH
003CCH
003CDH
003CEH
003CFH
003D0H
003D1H
003D2H
003D3H
W
0XXX XXXXB
0100 1000B
Transfer byte count setting register
Serial control register
R/W
S1CR
S1MR
W
S0BR
R/W
--0X XXXXB
-000 0000B
Clock Mode setting register
Address offset register
R/W
S1AO
R/W
0XXX XXXXB
0100 1000B
Transfer byte count setting register
Serial control register
S1BR
S2CR
S2MR
W
R/W
--0X XXXXB
-000 0000B
Clock Mode setting register
Address offset register
R/W
S2AO
S2BR
0XXX XXXXB
Transfer byte count setting register
R/W
003D4H to
003EFH
Reserved
003F0H
003F1H
003F2H
003F3H
003F4H
003F5H
003F6H
003F7H
003F8H
003F9H
003FAH
003FBH
003FCH
003FDH
003FEH
003FFH
00400H
00401H
00402H
00403H
XXX XXXXB
XXX XXXXB
XXX XXXXB
XXX XXXXB
XXX XXXXB
XXX XXXXB
XXX XXXXB
XXX XXXXB
XXX XXXXB
XXX XXXXB
XXX XXXXB
XXX XXXXB
XXX XXXXB
XXX XXXXB
XXX XXXXB
XXX XXXXB
---1 1111B
0 detection data register
W
BSD0
BSD1
BSDC
BSRR
1 detection data register
R/W
W
Change point detection data register
Detection result register
R
Interrupt control register 0
Interrupt control register 1
Interrupt control register 2
Interrupt control register 3
R/W
R/W
R/W
R/W
ICR00
ICR01
ICR02
ICR03
---1 1111B
---1 1111B
---1 1111B
00404H to
0042FH
---1 1111B to
---1 1111B
Interrupt control register 4 to
Interrupt control register 47
R/W to
R/W
ICR04 to
ICR47
00430H
00431H
00432H
00433H
---- ---0B
Delayed interrupt Control Register
Reserved
R/W
DICR
Reserved
Reserved
00434H to
0047FH
303
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix A I/O Map
Table A-1 I/O Map
Address
Register Name
Access
R/W
Register
RSRR/WTCR
STCR
Initial value
1XXX XXXXB
0001 11--B
Reset factor register / Watchdog cycle control
register
00480H
00481H
00482H
00483H
00484H
00485H
00486H
00487H
Standby control register
Reserved
R/W
XXXX XXXXB
11-- 11-1B
Timebase timer clear register
Gear Control Register
W
CTBR
GCR
R/W
W
XXXX XXXXB
Watchdog reset generation delayed register
WPR
Reserved
Reserved
Reserved
00488H to
005FFH
00600H
00601H
00602H
00603H
00604H
00605H
00606H
00607H
00608H
00609H
0060AH
0060BH
0060CH
0060DH
0060EH
0060FH
00610H
00611H
00612H
00613H
00614H
00615H
00616H
00617H
00618H
00619H
0061AH
0061BH
0000 0000B
Port 1 function selection register
Reserved
W
PFS1
---- --00B
Port 7 function selection register
Port 6 function selection register
Port 5 function selection register
Port 4 function selection register
W
W
W
W
PFS7
PFS6
PFS5
PFS4
0000 1111B
1111 1111B
0000 0000B
Reserved
0000 0000B
0000 0001B
0000 0000B
0000 0000B
0000 0000B
0000 0002B
0000 0000B
0000 0000B
0000 0000B
0000 0003B
0000 0000B
0000 0000B
0000 0000B
0000 0004B
0000 0000B
0000 0000B
Area selection Register 1
Area mask Register 1
Area selection Register 2
Area mask Register 2
Area selection Register 3
Area mask Register 3
Area selection Register 4
Area mask Register 4
W
W
W
W
W
W
W
W
ASR1
AMR1
ASR2
AMR2
ASR3
AMR3
ASR4
AMR4
304
Download from Www.Somanuals.com. All Manuals Search And Download.
Table A-1 I/O Map
Address
Register Name
Area selection Register 5
Access
Register
ASR5
Initial value
0000 0000B
0000 0005B
0000 0000B
0000 0000B
0061CH
W
0061DH
0061EH
0061FH
00620H
00621H
00622H
00623H
Area mask Register 5
W
AMR5
AMD1
Reserved
0--0 0000B
Area mode Register
Reserved
R/W
Reserved
00624H to
0062FH
Reserved
Reserved
Reserved
Reserved
00630H to
0077FH
00780H to
007AFH
007B0H to
007BFH
Flash memory control register (MB91F191A/
MB91F192)
007C0H
000- ---0B
---- -000B
R/W
R/W
FSTR
007C1H
007C2H
007C3H
007C4H
007C5H
007C6H
007C7H
Reserved
Wait Control Register
Reserved
WAITC
007C8H to
007FBH
Reserved
Reserved
007FCH
007FDH
007FEH
007FFH
---- -000B
Little endian register
Mode register
W
W
LER
XXXX XXXXB
MODR
Note:
Do not execute RMW commands to registers that have a write-only bit.
RMW system instruction (RMW: Read-modify-write)
AND
Rj,@Ri
OR
Rj,@Ri
Rj,@Ri
Rj,@Ri
#u4,@Ri
EOR
Rj,@Ri
ANDH Rj,@Ri
ANDB Rj,@Ri
BANDL #u4,@Ri
ORH
ORB
BORL
EORH Rj,@Ri
EORB Rj,@Ri
BEORL #u4,@Ri
305
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix B Interrupt vector
Appendix B Interrupt vector
The interrupt factor of the MB91191/MB91192 series and allocation of the interrupt
vector/interrupt control register are described in the interrupt vector table.
■ Interrupt Vector
Table B-1 Interrupt vector table (Continued)
Interrupt Vector number
Interru
pt level
TBR default
Interrupt cause
Offset
address
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
000FFFE4H
000FFFE0H
10 decimal
16 decimal
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
Reset
0
-
03FCH
03F8H
03F4H
03F0H
03ECH
03E8H
03E4H
03E0H
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
System reservation
1
-
2
-
3
-
4
-
5
-
6
-
7
-
8
-
03DCH 000FFFDCH
9
04H
-
03D8H
03D4H
03D0H
000FFFD8H
000FFFD4H
000FFFD0H
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
-
04H
-
03CCH 000FFFCCH
03C8H
03C4H
03C0H
000FFFC8H
000FFFC4H
000FFFC0H
Undefined instruction exception
-
System reservation
0FH
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
NMI
System reservation
03BCH 000FFFBCH
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
System reservation
03B8H
03B4H
03B0H
000FFFB8H
000FFFB4H
000FFFB0H
External interrupt 0 (INT0)
External interrupt 1 (INT1)
External interrupt 2 (INT2)
03ACH 000FFFACH
24 bit FRC capture
03A8H
03A4H
03A0H
039CH
0398H
0394H
0390H
038CH
0388H
0384H
000FFFA8H
000FFFA4H
000FFFA0H
000FFF9CH
000FFF98H
000FFF94H
000FFF90H
000FFF8CH
000FFF88H
000FFF84H
Programmable Pulse Generator ch0(PPG0)
Programmable Pulse Generator ch1(PPG1)
Real timing generator ch0(RTG0)
Real timing generator ch1(RTG1)
Real timing generator ch2(RTG2)
10 bit A/D converter (HARD)
8/16 bit Timer / Counter (Timer 5-0)
8/16 bit Timer / Counter (Timer5-1)
16 bit Timer / Counter (Timer4)
306
Download from Www.Somanuals.com. All Manuals Search And Download.
Table B-1 Interrupt vector table (Continued)
Interrupt Vector number
Interru
pt level
TBR default
address
Interrupt cause
Offset
10 decimal
16 decimal
1FH
20H
16 bit Timer (Timer0)
16 bit Timer (Timer 1)
16 bit Timer (Timer2)
16 bit Timer (Timer3)
Serial ch0(SIO0)
31
32
33
34
35
36
37
38
39
40
ICR15
ICR16
ICR17
ICR18
ICR19
ICR20
ICR21
ICR22
ICR23
ICR24
0380H
037CH
0378H
0374H
0370H
036CH
0368H
0364H
0360H
035CH
0358H
000FFF80H
000FFF7CH
000FFF78H
000FFF74H
000FFF70H
000FFF6CH
000FFF68H
000FFF64H
000FFF60H
000FFF5CH
000FFF58H
IRQ15
IRQ16
IRQ17
IRQ18
IRQ19
IRQ20
IRQ21
IRQ22
IRQ23
21H
22H
23H
Serial ch1(SIO1)
24H
Serial ch2(SIO2)
25H
10 bit A/D converter (SOFT)
Key input Interrupt
System reservation
26H
27H
28H
IRQ24
41
to
61
29H
ICR25
to
ICR45
IRQ25
to
IRQ45
System reservation
to
3DH
to
0308H
to
000FFF08H
62
63
64
65
3EH
3FH
40H
41H
42H
ICR46
0304H
0300H
02FCH
02F8H
02F4H
000FFF04H
000FFF00H
000FFEFCH
000FFEF8H
000FFEF4H
IRQ46
IRQ47
FLASH
ICR47
Delayed Interrupt Factor bit
System reservation (using for REALOS*)
System reservation (using for REALOS*)
-
-
66
to
255
System reservation
to
FFH
-
to
0000H
to
000FFD00H
*: Use 0x40, 0x41 for the system code when using REALOS/FR.
ICR: This is the register set within the interrupt controller, and it sets the interrupt levels for each interrupt
request. ICR is prepared corresponding to each of the interruption demand.
TBR: It is a register which shows the first address of the vector table for EIT.
The address to which the offset value determined per TBR and EIT factor is added will be the vector
address.
Note:
From address which TBR shows to vector region for EIT region of 1KB
The size per vector is 4 bytes, and the relationship between the vector number and vector address is
expressed as below.
vctadr = TBR + vctofs
= TBR +(3FCH - 4 × vct)
vctadr: Vector Address
vctofs: Vector offset
vct:
Vector number
307
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix C Measurement accuracy of peripheral circuit
Appendix C Measurement accuracy of peripheral circuit
the output timing accuracy.
■ Measurement Accuracy of Peripheral Circuit Relative to FRC and Output Timing
Accuracy
Figure C-1 Measurement accuracy of peripheral circuit relative to FRC and output timing accuracy
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24bit FRC
Measurement
50ns
3bit
21bit
21bit
21bit
21bit
21bit
DFG
CFG
RFG
accuracy
Measurement
accuracy
400ns
400ns
400ns
400ns
Measurement
accuracy
EXI0-2 Measurement
accuracy
Soft
Measurement
accuracy
Output accuracy
16bit
PPG0-1
Output accuracy
Output accuracy
16bit
16bit
RTG0-2
RTG0-2
400ns (TSEL=0)
800ns (TSEL=1)
Measurement
accuracy
8bit
PWC
40ns
308
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix D Restrictions for Using MB91191/MB91192 series
This section shows the restrictions for using MB91191/MB91192 series.
■ Restrictions for Using MB91191/MB91192 Series
● Restrictions of using gear function
There is a limit to the gear combination of the CPU system and peripheral system for the MB91191/
MB91192 series in order to ensure correct operation of the peripheral function.
Table D-1 At CHC=0
Peripheral
φ
θ
1/1
1/2
1/4
×
1/8
×
1/1
1/2
×
: Selectable. But need to set 1wait.
: Selectable.
×
×
CPU
: Selectable. However, there is the restrictions of
peripheral.
system
1/4
1/8
×
×: Not selectable
Table D-2 At CHC=1
Peripheral
φ
θ
1/1
1/2
1/4
×
1/8
×
1/1
×
1/2
×
×
CPU
system
1/4
×
1/8
309
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix E Instruction List
Appendix E Instruction List
Instruction list of FR series is shown. Beforehand, the following matters are explained
for better understanding of the command list.
• How to Read the Instruction List
• Symbol of addressing mode
• Instruction format
■ How to Read the Instruction List
Instruction operand is XXX scr, dest (src--> dest).
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remark
ADD
*ADD
Rj,
#s5,
,
,
Rj
Rj
A
C
,
AG
A4
,
,
1
1
,
CCCC
CCCC
Ri+Rj
Ri+s5
→Rj
→Ri
,
,
,
,
,
,
↓
↓
↓
↓
↓
↓
↓
↓
1)
2)
3)
4)
5)
6)
6)
7)
1. The instruction name is shown.
*: The indication is the extend command whose command was extended or added by the assembler regardless of
the CPU specifications.
2. A specifiable Addressing mode is shown in the operand by the sign.
- Refer to the "Addressing mode symbols" for the symbol meanings.
3. The instruction format is shown.
4. The hexadecimal number is displayed to the instruction code.
5. The number of machine cycles is shown.
- a: It is a memory access cycle, and there is a possibility to postpone by the Ready function.
- b: It is a memory access cycle, and there is a possibility to postpone by the Ready function. If the
register that is targeted for LD operation is referred to by the command that immediately follows
it, an interlock is activated, and the execution cycle number will be increased by 1.
- c: When the command immediately following is one that reads or writes R15, SSP, or USP, an
interlock is activated, and the execution cycle number will be increased by 1, thus becoming 2.
- d: When the command immediately following refers to the MDH/MDL, an interlock is activated,
and the execution cycle number will be increased by 1, thus becoming 2.
- a, b, c, d, and the minimum are one cycle.
310
Download from Www.Somanuals.com. All Manuals Search And Download.
6. The flag change is shown.
Flag change
Meaning of flag
C: change
-: No change
0: Clear
N: Negative flag
Z: Zero flag
V: Over flag
1: Set
C: Carrying flag
7. The instruction operation is written.
311
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix E Instruction List
■ Symbol of Addressing Mode
Table E-1 Description of symbol of addressing mode
Symbol
Explanation
Ri
Register direct (R0 to R15, AC, FP, SP)
Register direct (R0 to R15, AC, FP, SP)
Register direct (R13, AC)
Rj
R13
Ps
Register direct (direct program status register)
Register direct (TBR, RP, SSP, USP, MDH, MDL)
Register direct (CR0 to CR15)
Rs
CRi
CRj
#i8
Register direct (CR0 to CR15)
Unsigned 8 bit value immediately (-128 to 255)
Note: -128 to -1 are used as 128 to 255.
#i20
#i32
Unsigned 20 bit value immediately (-0X80000 to 0XFFFFF)
Note: -0X7FFFF to -1 are used as 0X7FFFF to 0XFFFFF.
Unsigned 32 bit value immediately (-0X80000000 to 0XFFFFFFFF)
Note: -0X80000000 to -1 are used as 0X80000000 to 0XFFFFFFFF.
#s5
Signed 5 bit value immediately (-16 to 15)
#s10
Signed 10 bit value immediately (Only the multiple of -512 to 5084)
Unsigned 20 bit value immediately (0 to 15)
#u4
#u5
Unsigned 5 bit value immediately (0 to 31)
#u8
Unsigned 8 bit value immediately (0 to 255)
#u10
Unsigned 10 bit value immediately (Only the multiple of 0 - 10204:)
Unsigned 8 bit direct address (0 to 0XFF)
@dir8
@dir9
@dir10
label9
label12
label20
label32
@Ri
Unsigned 9 bit direct address (Only the multiple of 0 to 0X1FE2)
Unsigned 10 bit direct address (Only the multiple of 0 to 0X3FC4).
Divergence address of signed 9 bits (Only the multiple of -0X100 to 0XFC2)
Divergence address of signed 12 bits (Only the multiple of -0X800 to 0X7FC2)
Divergence address of signed 20 bits (-0X80000 to 0X7FFFF)
Divergence address of signed 32 bits (-0X80000000 to 0X7FFFFFFF)
Register indirect (R0 to R15, AC, FP, SP)
@Rj
Register indirect (R0 to R15, AC, FP, SP)
@(R13,Rj)
Relativity is register indirect (Rj:R0 to R15, AC, FP, SP)
@(R14,disp10) Relative indirectly register (Only the multiple of disp10:-0X200 to 0X1FC4)
@(R14,disp9)
@(R14,disp8)
Relative indirectly register (Only the multiple of disp9:-0X100 to 0XFE2)
Relativity is register indirect (disp8:-0X80 to 0X7F)
@(R15,udisp6) Relative indirectly register (Only the multiple of udisp6:0 to 604)
@Ri+
Register indirectly with post increment (R0 to R15, AC, FP, SP)
Register indirectly with post increment (R13, AC)
Register list
@R13+
(reglist)
312
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Instruction Format
Table E-2 Instruction format
Type
Instruction format
A
MSB
LSB
16bit
OP
8
Rj
4
Ri
4
B
OP
i8/o8
8
Ri
4
4
C
OP
8
u4/m4
4
Ri
4
C’
Only ADD, ADDN, CMP, LSL, LSR, ASR instructions
OP
7
s5/u5
5
Ri
4
D
u8/rel8/dir/
reglist
OP
8
8
E
F
OP
8
SUB-OP
Ri
4
4
rel11
11
OP
5
313
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix E Instruction List
E.1 Instruction list of FR series
Instruction list of FR series is described in order to following instruction.
■ Instruction List of FR Series
314
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Addition and Subtraction Instruction
Table E-3 Addition and subtraction instruction
Mnemonic
ADD Rj, Ri
Type
OP
CYCLE
NZVC
Operation
Remark
A
C'
A6
A4
1
1
CCCC
CCCC
Ri+Rj →Ri
Ri+s5 →Ri
*ADD #s5, Ri
Upper in assembler
1 bit is regarded as a sign.
0 expansions
ADD #u4, Ri
ADD2 #u4, Ri
C
C
A4
A5
1
1
CCCC
CCCC
Ri+extu(i4) →Ri
Ri+extu(i4) →Ri
Minus expansion
ADDC Rj, Ri
A
A7
1
CCCC
Ri+Rj +c→Ri
Addition with carry
ADDN Rj, Ri
*ADDN #s5, Ri
A
C'
A2
A0
1
1
----
----
Ri+Rj →Ri
Ri+s5 →Ri
Upper in assembler
1 bit is regarded as a sign.
0 expansions
ADDN #u4, Ri
ADDN2 #u4, Ri
C
C
A0
A1
1
1
----
----
Ri+extu(i4) →Ri
Ri+extu(i4) →Ri
Minus expansion
SUB Rj, Ri
SUBC Rj, Ri
SUBN Rj, Ri
A
A
A
AC
AD
AE
1
1
1
CCCC
CCCC
----
RiRj →Ri
RiRj c→Ri
Ri-Rj →Ri
Reduction with carry
■ Comparison Operation Instruction
Table E-4 Comparison operation instruction
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remark
CMP Rj, Ri
*CMP #s5, Ri
A
C'
AA
A8
1
1
CCCC
CCCC
Ri-Rj
Ri-s5
Upper in assembler
1 bit is regarded as a sign.
0 expansions
CMP #u4, Ri
CMP2 #u4, Ri
C
C
A8
A9
1
1
CCCC
CCCC
Ri-extu(i4)
Ri-extu(i4)
Minus expansion
■ Logical Operation Instruction
Table E-5 Logical operation instruction
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remark
AND Rj, Ri
A
A
A
A
82
84
85
86
1
CC--
CC--
CC--
CC--
Ri &=Rj
(Ri) &=Rj
(Ri) &=Rj
(Ri) &=Rj
Word
Word
Half word
Byte
AND Rj, @Ri
ANDH Rj, @Ri
ANDB Rj, @Ri
1+2a
1+2a
1+2a
OR Rj, Ri
A
A
A
A
92
94
95
96
1
CC--
CC--
CC--
CC--
Ri | =Rj
Word
Word
Half word
Byte
OR Rj, @Ri
ORH Rj, @Ri
ORB Rj, @Ri
1+2a
1+2a
1+2a
(Ri) | =Rj
(Ri) | =Rj
(Ri) | =Rj
EOR Rj, Ri
A
A
A
A
9A
9C
9D
9E
1
CC--
CC--
CC--
CC--
Ri ^ =Rj
Word
Word
Half word
Byte
EOR Rj, @Ri
EORH Rj, @Ri
EORB Rj, @Ri
1+2a
1+2a
1+2a
(Ri) ^ =Rj
(Ri) ^ =Rj
(Ri) ^ =Rj
315
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix E Instruction List
■ Bit Manipulation Instructions
Table E-6 Bit manipulation instructions
Mnemonic
Type
OP
CYCLE NZVC
Operation
Remark
BANDL #u4, @Ri
BANDH #u4, @Ri
*BAND #u8, @Ri
C
C
80
81
1+2a
1+2a
----
----
----
(Ri) &=(0xF0+u4)
(Ri) &=((u4 < <4)+0x0F)
(Ri) &=u8
The subordinate position four bits are
operated.
The high rank four bits are operated.
*1
BORL #u4, @Ri
BORH #u4, @Ri
*BOR #u8, @Ri
C
C
90
91
1+2a
1+2a
----
----
----
(Ri) | =u4
(Ri) | =(u4 < <4)
(Ri) | =u8
The subordinate position four bits are
operated.
The high rank four bits are operated.
*2
BEORL #u4, @Ri
BEORH #u4, @Ri
*BEOR #u8, @Ri
C
C
98
99
1+2a
1+2a
----
----
----
(Ri) ^ =u4
(Ri) ^ =(u4 < <4)
(Ri) ^ =u8
The subordinate position four bits are
operated.
The high rank four bits are operated.
*3
BTSTL #u4, @Ri
BTSTH #u4, @Ri
C
C
88
89
2+a
2+a
0C--
CC--
(Ri) &u4
(Ri) &(u4 < <4)
Lower 4 bit test
Upper 4 bit test
*1: The assembler generates BANDL when the u8&0x0F bit is raised, or generates BANDH when the u8&0xF0 bit is raised. There is a
case generating both BANDL and BANDH.
*2: The assembler generates BORL when the u8&0x0F bit is raised, or generates BORH when the u8&0xF0 bit is raised. There is a case
generating both BORL and BODH.
*3: The assembler generates BEORL when the u8&0x0F bit is raised, or generates BEORH when the u8&0xF0 bit is raised. There is a
case generating both BEORL and BEORH.
■ Multiplication and Division Instructions
Table E-7 Multiplication and division instructions
Mnemonic
MUL Rj,Ri
MULU Rj,Ri
MULH Rj,Ri
MULUH Rj,Ri
Type
OP
CYCLE
NZVC
Operation
Remark
A
A
A
A
AF
AB
BF
BB
5
5
3
3
CCC-
CCC-
CC--
CC--
Ri*Rj→MDH,MDL
Ri*Rj→MDH,MDL
Ri*Rj→MDL
32bit*32bit=64bit
None
16bit*16bit=32bit
None
Ri*Rj→MDL
DIV0S Ri
DIV0U Ri
DIV1 Ri
DIV2 Ri
DIV3
E
E
E
E
E
E
97-4
97-5
97-6
97-7
9F-6
9F-7
1
1
d
1
1
----
----
-C-C
-C-C
----
Step operation
32bit/32bit=32bit
DIV4S
*DIV Ri
1
36
----
-C-C
*1
MDL/Ri→MDL,
MDL%Ri→MDH
MDL/Ri→MDL,
MDL%Ri→MDH
*2
*DIVU Ri
33
-C-C
*1:Generates DIV0S, DIV1 × 32, DIV2, DIV3, DIV4S. Instruction code length is 72 bytes.
*2:Generates DIV0U, DIV1 × 32. Instruction code length is 66 bytes.
316
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Shift Instruction
Table E-8 Shift instruction
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remark
LSL Rj, Ri
*LSL #u5, Ri(u5:0 to 31)
LSL #u4, Ri
A
C'
C
B6
B4
B4
B5
1
1
1
1
CC-C
CC-C
CC-C
CC-C
Ri < <Rj→Ri
Logical shift
Ri < <u5→Ri
Ri < <u4→Ri
Ri < <(u4+16)→Ri
LSL2 #u4, Ri
C
LSR Rj, Ri
*LSR #u5, Ri(u5:0 to 31)
LSR #u4, Ri
A
C'
C
B2
B0
B0
B1
1
1
1
1
CC-C
CC-C
CC-C
CC-C
Ri > >Rj→Ri
Logical shift
Ri > >u5→Ri
Ri > >u4→Ri
Ri > >(u4+16)→Ri
LSR2 #u4, Ri
C
ASR Rj, Ri
*ASR #u5, Ri(u5:0 to 31)
ASR #u4, Ri
A
C'
C
BA
B8
B8
B9
1
1
1
1
CC-C
CC-C
CC-C
CC-C
Ri > >Rj→Ri
Arithmetic shift
Ri > >u5→Ri
Ri > >u4→Ri
Ri > >(u4+16)→Ri
ASR2 #u4, Ri
C
■ Value Move Operation of Value Sets/16 Bits/32 Bits Immediately
Table E-9 Value move operation of value sets/16 bits/32 bits immediately
Mnemonic
LDI:32 #i32,Ri
LDI:20 #i20,Ri
LDI:8 #i8,Ri
Type
OP CYCLE NZVC
Operation
Remark
E
C
B
9F-8
9B
3
2
1
----
----
----
i32→Ri
i20→Ri
i8→Ri
0 expansions of high rank 12bit.
0 expansions of high rank 24 bit.
C0
*
*LDI# {i8 | i20 | i32}, Ri
{i8 | i20 | i32} →Ri
*: When the immediate value is an absolute value, i8, i20, or i32 is automatically selected by the assembler.
When the immediate value is a relative value, or includes an external reference symbol, i32 is automatically selected.
317
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix E Instruction List
■ Memory Loading Instruction
Table E-10 Memory loading instruction
Mnemonic
LD @Rj,Ri
LD @(R13,Rj),Ri
LD @(R14,disp10),Ri
LD @(R15,udisp6),Ri
LD @R15+,Ri
Type
OP
CYCLE
NZVC
Operation
Remark
A
A
B
C
E
E
E
04
00
20
b
b
b
b
b
b
----
----
----
----
----
----
(Rj) → Ri
(R13+Rj) → Ri
(R14+disp10) → Ri
(R15+udisp6) → Ri
(R15) → Ri,R15+=4
(R15) → Rs,R15+=4
03
07-0
07-8
07-9
*
LD @R15+,Rs
LD @R15+,PS
Rs: special register
1+a+b
CCCC (R15) → PS,R15+=4
LDUH @Rj,Ri
LDUH @(R13,Rj),Ri
LDUH @(R14,disp9),Ri
A
A
B
05
01
40
b
b
b
----
----
----
(Rj) →Ri
(R13+Rj) →Ri
(R14+disp9) →Ri
0 expansions
0 expansions
0 expansions
LDUB @Rj,Ri
LDUB @(R13,Rj),Ri
LDUB @(R14,disp8),Ri
A
A
B
06
02
60
b
b
b
----
----
----
(Rj) → Ri
(R13+Rj) → Ri
(R14+disp8) → Ri
0 expansions
0 expansions
0 expansions
*:Special register Rs: TBR, RP, USP, SSP, MDH, MDL
Note:
The assembler calculates and sets values as follows in the 08 and 04 fields for hardware specifications.
disp10/4→o8, disp9/2→o8, disp8→o8, disp10, disp9, disp8 are with sign.
udisp6/4→o4udisp6 is without sign.
■ Memory Store Instruction
Table E-11 Memory store instruction
Mnemonic
ST Ri,@Rj
ST Ri,@(R13,Rj)
ST Ri,@(R14,disp10)
ST Ri,@(R15,udisp6)
ST Ri,@-R15
Type
OP
CYCLE
NZVC
Operation
Remark
A
A
B
C
E
E
E
14
10
30
a
a
a
a
a
a
a
----
----
----
----
----
----
----
Ri→(Rj)
Ri→(R13+Rj)
Ri→(R14+disp10)
Ri→(R15+udisp6)
R15-=4,Ri→(R15)
R15-=4,Rs→(R15)
R15-=4,PS→(R15)
Word
Word
Word
13
17-0
17-8
17-9
*
ST Rs,@-R15
ST PS,@-R15
Rs: special register
STH Ri,@Rj
STH Ri,@(R13,Rj)
STH Ri,@(R14,disp9)
A
A
B
15
11
50
a
a
a
----
----
----
Ri→(Rj)
Ri→(R13+Rj)
Ri→(R14+disp9)
Half word
Half word
Half word
STB Ri,@Rj
STB Ri,@(R13,Rj)
STB Ri,@(R14,disp8)
A
A
B
16
12
70
a
a
a
----
----
----
Ri→(Rj)
Ri→(R13+Rj)
Ri→(R14+disp8)
Byte
Byte
Byte
*:Special register Rs: TBR, RP, USP, SSP, MDH, MDL
Note:
The assembler calculates and sets values as follows in the 08 and 04 fields for hardware specifications.
disp10/4→o8, disp9/2→o8, disp8→o8, disp10, disp9, disp8 are with sign.
udisp6/4→o4udisp6 is without sign.
318
Download from Www.Somanuals.com. All Manuals Search And Download.
■ Transfer Instruction between Registers
Table E-12 Transfer instruction between registers
Mnemonic
MOV Rj,Ri
MOV Rs,Ri
MOV Ri,Rs
MOV PS,Ri
MOV Ri,PS
Type
OP
CYCLE
NZVC
Operation
Rj→Ri
Rs→Ri
Ri→Rs
PS→Ri
Ri→PS
Remark
A
A
A
E
8B
B7
B3
17-1
07-1
1
1
1
1
c
----
----
----
----
CCCC
Transfer between general purpose register
*
Rs: special register
Rs: special register
*
E
*: Special register Rs: TBR, RP, USP, SSP, MDH, MDL
■ Normal Divergence (There is no delay) Instruction
Table E-13 Normal divergence (There is no delay) instruction
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remark
JMP @Ri
E
F
97-0
D0
2
2
----
----
Ri→PC
CALL label12
PC+2→RP,
PC+2+(label12-PC-2)→PC
PC+2→RP,Ri→PC
CALL @Ri
RET
E
E
D
97-1
97-2
1F
2
2
----
----
----
RP→PC
Return
INT #u8
3+3a
SSP-=4,PS→(SSP),
SSP-=4,PC+2→(SSP),
0: I flag, 0: S flag
(TBR+0x3FC-u8 × 4) →PC
SSP-=4,PS→(SSP),
SSP-=4,PC+2→(SSP),
0→S Flag,
INTE
E
9F-3
3+3a
----
for emulator
(TBR+0x3D8) →PC
RETI
E
97-3
2+2a
CCCC
(R15) →PC,R15-=4,
(R15) →PS,R15-=4
BRA label9
BNO label9
BEQ label9
D
D
D
E0
E1
E2
2
1
2/1
----
----
----
PC+2+(label9-PC-2) →PC
not diverge
if(Z==1)then
PC+2+(label9-PC-2) →PC
↑ s/Z==0
BNE label9
BC label9
BNC label9
BN label9
BP label9
BV label9
BNV label9
BLT label9
BGE label9
BLE label9
BGT label9
BLS label9
BHI label9
D
D
D
D
D
D
D
D
D
D
D
D
D
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
----
----
----
----
----
----
----
----
----
----
----
----
----
↑ s/C==1
↑ s/C==0
↑ s/N==1
↑ s/N==0
↑ s/V==1
↑ s/V==0
↑ s/VxorN==1
↑ s/VxorN==0
↑ s/(VxorN)orZ==1
↑ s/(VxorN)orZ==0
↑ s/CorZ==1
↑ s/CorZ==0
319
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix E Instruction List
Note:
•
"2/1" of CYCLE number is following;
2: branching
1: not branching
•
•
The assembler calculates and sets values as follows in the rel11 and rel8 fields for hardware specifications.
(label12-PC-2)/2→rel11, (label9-PC-2)/2→rel8, label12, label9 are with sign.
When executing RETI instruction, S flag is required to be "0".
■ Delay Divergence Instruction
Table E-14 Delay divergence Instruction
Mnemonic
JMP:D @Ri
Type
OP
CYCLE
NZVC
Operation
Remark
E
F
9F-0
D8
1
1
----
----
Ri→PC
CALL:D label12
PC+4→RP,
PC+2+(label12-PC-2)→PC
PC+4→RP,Ri→PC
CALL:D @Ri
RET:D
E
E
9F-1
9F-2
1
1
----
----
RP→PC
Return
BRA:D label9
BNO:D label9
BEQ:D label9
D
D
D
F0
F1
F2
1
1
1
----
----
----
PC+2+(label9-PC-2) →PC
not diverge
if(Z==1)then
PC+2+(label9-PC-2) →PC
↑ s/Z==0
BNE:D label9
BC:D label9
BNC:D label9
BN:D label9
BP:D label9
BV:D label9
BNV:D label9
BLT:D label9
BGE:D label9
BLE:D label9
BGT:D label9
BLS:D label9
BHI:D label9
D
D
D
D
D
D
D
D
D
D
D
D
D
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
1
1
1
1
1
1
1
1
1
1
1
1
1
----
----
----
----
----
----
----
----
----
----
----
----
----
↑ s/C==1
↑ s/C==0
↑ s/N==1
↑ s/N==0
↑ s/V==1
↑ s/V==0
↑ s/VxorN==1
↑ s/VxorN==0
↑ s/(VxorN)orZ==1
↑ s/(VxorN)orZ==0
↑ s/CorZ==1
↑ s/CorZ==0
Note:
•
The assembler calculates and sets values as follows in the rel11 and rel8 fields for hardware specifications.
(label12-PC-2)/2->rel11, (label9-PC-2)/2→rel8, label12, label9 are with sign.
•
•
In terms of delayed branches, branching must be implemented after executing the next command (delay slot).
Commands that can be placed at the delay slot are all 1 cycle, a, b, c, and d cycle commands.
Two or more-cycle instruction cannot be put.
320
Download from Www.Somanuals.com. All Manuals Search And Download.
■ The Other Instruction
Table E-15 The other Instruction
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remark
NOP
E
9F-A
1
----
Anything does not change
either.
ANDCCR #u8
ORCCR #u8
D
D
83
93
c
c
CCCC
CCCC
CCR and u8 →CCR
CCR or u8 →CCR
STILM #u8
D
87
1
----
i8→ILM
Value set of ILM
immediately
*1
ADDSP #s10
D
A3
1
----
R15+=s10
ADDSP Instruction
EXTSB Ri
EXTUB Ri
EXTSH Ri
EXTUH Ri
E
E
E
E
97-8
97-9
97-A
97-B
1
1
1
1
----
----
----
----
sign extension 8→32bit
0 expansions 8→32bit
sign extension16→32bit
0 expansions16→32bit
LDM0 (reglist)
LDM1 (reglist)
*LDM (reglist)
D
D
8C
8D
----
----
----
(R15) →reglist, R15 increment loading multi R0 - R7
(R15) →reglist, R15 increment loading multi R8 - R15
(R15) →reglist, R15 increment loading multi R0 - R15
*2
*3
STM0 (reglist)
STM1 (reglist)
*STM (reglist)
D
D
8E
8F
----
----
----
R15 decrement, reglist→(R15)
R15 decrement, reglist→(R15)
R15 decrement, reglist→(R15)
store multi R0 - R7
store multi R8 - R15
store multi - R0 - R15
*4
ENTER #u10
D
0F
1+a
----
R14→(R15-4), R15-4→R14,
R15-u10→R15
Entrance processing of
function
LEAVE
E
9F-9
8A
b
----
----
R14+4→R15, (R15-4)→R14
Exit processing of function
XCHB @Rj,Ri
A
2a
Ri→TEMP
(Rj)→Ri
TEMP→(Rj)
For semaphore control
Byte Data
*1: s10 is set by that assembler calculates s10/4 to s8. s10 has the sign.
*2: Under the reglist, if one of R0-R7 is specified, LDM0 is generated, whereas if one of R8-R15 is specified, LDM1 is generated. In
other case, both LDM0 and LDM1 may be able to be generated.
*3: Under the reglist, if one of R0-R7 is specified, STM0 is generated, whereas if one of R8-R15 is specified, STM1 is generated. There
is a case generating both STM1 and STM0.
*4: u10 is set by that assembler calculates u10/4 to u8. u10 does not have the sign.
321
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix E Instruction List
■ 20-bit Normal Divergence Macro Instruction
Table E-16 20-bit Normal divergence macro instruction
Mnemonic
Operation
Remark
*CALL20 label20,Ri
Address of the following instruction-->RP,
Ri: Temporary register (Refer to reference 1.)
label20→PC
*BRA20 label20,Ri
*BEQ20 label20,Ri
*BNE20 label20,Ri
*BC20 label20,Ri
*BNC20 label20,Ri
*BN20 label20,Ri
*BP20 label20,Ri
*BV20 label20,Ri
*BNV20 label20,Ri
*BLT20 label20,Ri
*BGE20 label20,Ri
*BLE20 label20,Ri
*BGT20 label20,Ri
*BLS20 label20,Ri
*BHI20 label20,Ri
label20→PC
if(Z==1)thenlabel20→PC
↑ s/Z==0
Ri: Temporary register (Refer to reference 2.)
Ri: Temporary register (Refer to reference 3.)
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑ s/C==1
↑ s/C==0
↑ s/N==1
↑ s/N==0
↑ s/V==1
↑ s/V==0
↑ s/VxorN==1
↑ s/VxorN==0
↑ s/(VxorN)orZ==1
↑ s/(VxorN)orZ==0
↑ s/CorZ==1
↑ s/CorZ==0
Reference 1: CALL20
1) When label20-PC-2 is - 0x100 - + 0xfe, the instruction is generated as follows.
CALL label12
2) When label20-PC-2 is outside the area as per 1) and includes an external reference symbol, the command is generated as
follows.
LDI:20 #label20,Ri
CALL @Ri
Reference 2: BRA20
1) When label20-PC-2 is - 0x100 - + 0xfe, the instruction is generated as follows.
BRA label9
2) When label20-PC-2 is outside the area as per 1) and includes an external reference symbol, the command is generated as
follows.
LDI:20 #label20,Ri
JMP @Ri
Reference 3: Bcc20
1) When label20-PC-2 is - 0x100 - + 0xfe, the instruction is generated as follows.
Bcc label9
2) When label20-PC-2 is outside the area as per 1) and includes an external reference symbol, the command is generated as
follows.
Bxcc false xcc is a contradiction condition of cc.
LDI:20 #label20,Ri
JMP @Ri
false:
322
Download from Www.Somanuals.com. All Manuals Search And Download.
■ 20-bit Delayed Divergence Macro Instruction
Table E-17 20-bit Delayed divergence macro instruction
Mnemonic
Operation
Remark
*CALL20:D label20,Ri
Address of the following instruction +2→RP,
label20→PC
Ri: Temporary register (Refer to reference 1.)
*BRA20:D label20,Ri
*BEQ20:D label20,Ri
*BNE20:D label20,Ri
*BC20:D label20,Ri
*BNC20:D label20,Ri
*BN20:D label20,Ri
*BP20:D label20,Ri
*BV20:D label20,Ri
*BNV20:D label20,Ri
*BLT20:D label20,Ri
*BGE20:D label20,Ri
*BLE20:D label20,Ri
*BGT20:D label20,Ri
*BLS20:D label20,Ri
*BHI20:D label20,Ri
label20→PC
if(Z==1)thenlabel20→PC
↑ s/Z==0
Ri: Temporary register (Refer to reference 2.)
Ri: Temporary register (Refer to reference 3.)
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑ s/C==1
↑ s/C==0
↑ s/N==1
↑ s/N==0
↑ s/V==1
↑ s/V==0
↑ s/VxorN==1
↑ s/VxorN==0
↑ s/(VxorN)orZ==1
↑ s/(VxorN)orZ==0
↑ s/CorZ==1
↑ s/CorZ==0
Reference1: CALL20:D
1) When label20-PC-2 is - 0x100 - + 0xfe, the instruction is generated as follows.
CALL:D label12
2) When label20-PC-2 is outside the area as per 1) and includes an external reference symbol, the command is generated as
follows.
LDI:20 #label20,Ri
CALL:D @Ri
Reference 2: BRA20:D
1) When label20-PC-2 is - 0x100 - + 0xfe, the instruction is generated as follows. x
BRA:D label9
2) When label20-PC-2 is outside the area as per 1) and includes an external reference symbol, the command is generated as
follows.
LDI:20 #label20,Ri
JMP:D @Ri
Reference 3: Bcc20:D
1) When label20-PC-2 is - 0x100 - + 0xfe, the instruction is generated as follows.
Bcc:D label9
2) When label20-PC-2 is outside the area as per 1) and includes an external reference symbol, the command is generated as
follows.
Bxcc false xcc is a contradiction condition of cc.
LDI:20 #label20,Ri
JMP:D @Ri
false:
323
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix E Instruction List
■ 32-bit Normal Divergence Macro Instruction
Table E-18 32-bit Normal divergence macro instruction
Mnemonic
Operation
Remark
*CALL32 label32,Ri
Address of the following instruction→RP,
label32→PC
Ri: Temporary register (Refer to reference 1.)
*BRA32 label32,Ri
*BEQ32 label32,Ri
*BNE32 label32,Ri
*BC32 label32,Ri
*BNC32 label32,Ri
*BN32 label32,Ri
*BP32 label32,Ri
*BV32 label32,Ri
*BNV32 label32,Ri
*BLT32 label32,Ri
*BGE32 label32,Ri
*BLE32 label32,Ri
*BGT32 label32,Ri
*BLS32 label32,Ri
*BHI32 label32,Ri
label32→PC
if(Z==1)thenlabel32→PC
↑ s/Z==0
Ri: Temporary register (Refer to reference 2.)
Ri: Temporary register (Refer to reference 3.)
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑ s/C==1
↑ s/C==0
↑ s/N==1
↑ s/N==0
↑ s/V==1
↑ s/V==0
↑ s/VxorN==1
↑ s/VxorN==0
↑ s/(VxorN)orZ==1
↑ s/(VxorN)orZ==0
↑ s/CorZ==1
↑ s/CorZ==0
Reference 1: CALL32
1) When label20-PC-2 is - 0x100 - + 0xfe, the instruction is generated as follows.
CALL label12
2) When label32-PC-2 is outside the area as per 1) and includes an external reference symbol, the command is generated as
follows.
LDI:32 #label32,Ri
CALL @Ri
Reference 2: BRA32
1) When label32-PC-2 is - 0x100 - + 0xfe, the instruction is generated as follows.
BRA label9
2) When label32-PC-2 is outside the area as per 1) and includes an external reference symbol, the command is generated as
follows.
LDI:32 #label32,Ri
JMP @Ri
Reference 3: Bcc32
1) When label32-PC-2 is - 0x100 - + 0xfe, the instruction is generated as follows. x
Bcc label9
2) When label32-PC-2 is outside the area as per 1) and includes an external reference symbol, the command is generated as
follows.
Bxcc false xcc is a contradiction condition of cc.
LDI:32 #label32,Ri
JMP @Ri
false:
324
Download from Www.Somanuals.com. All Manuals Search And Download.
■ 32-bit Delayed Divergence Macro Instruction
Table E-19 32-bit Delayed divergence macro instruction
Mnemonic
Operation
Remark
*CALL32:D label32,Ri
Address of the following instruction Ri: Temporary register (Refer to reference 1.)
+2→RP, label32→PC
*BRA32:D label32,Ri
*BEQ32:D label32,Ri
*BNE32:D label32,Ri
*BC32:D label32,Ri
*BNC32:D label32,Ri
*BN32:D label32,Ri
*BP32:D label32,Ri
*BV32:D label32,Ri
*BNV32:D label32,Ri
*BLT32:D label32,Ri
*BGE32:D label32,Ri
*BLE32:D label32,Ri
*BGT32:D label32,Ri
*BLS32:D label32,Ri
*BHI32:D label32,Ri
label32→PC
if(Z==1)thenlabel32→PC
↑ s/Z==0
Ri: Temporary register (Refer to reference 2.)
Ri: Temporary register (Refer to reference 3.)
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑ s/C==1
↑ s/C==0
↑ s/N==1
↑ s/N==0
↑ s/V==1
↑ s/V==0
↑ s/VxorN==1
↑ s/VxorN==0
↑ s/(VxorN)orZ==1
↑ s/(VxorN)orZ==0
↑ s/CorZ==1
↑ s/CorZ==0
Reference 1: CALL32:D
1) When label32-PC-2 is -0x800 - +0x7fe, the instruction is generated as follows.
CALL:D label12
2) When label32-PC-2 is outside the area as per 1) and includes an external reference symbol, the command is generated as
follows.
LDI:32 #label32,Ri
CALL:D @Ri
Reference 2: BRA32:D
1) When label32-PC-2 is - 0x100 - + 0xfe, the instruction is generated as follows.
BRA:D label9
2) When label32-PC-2 is outside the area as per 1) and includes an external reference symbol, the command is generated as
follows.
LDI:32 #label32,Ri
JMP:D @Ri
Reference 3: Bcc32:D
1) When label32-PC-2 is - 0x100 - + 0xfe, the instruction is generated as follows.
Bcc:D label9
2) When label32-PC-2 is outside the area as per 1) and includes an external reference symbol, the command is generated as
follows.
Bxcc false xcc is a contradiction condition of cc.
LDI:32 #label32,Ri
JMP:D @Ri
false:
325
Download from Www.Somanuals.com. All Manuals Search And Download.
Appendix E Instruction List
■ Direct Addressing Instruction
Table E-20 Direct addressing instruction
Mnemonic
Type
OP
CYCLE NZVC
Operation
Remark
DMOV @dir10, R13
DMOV R13, @dir10
DMOV @dir10, @R13+
DMOV @R13+, @dir10
DMOV @dir10, @-R15
DMOV @R15+, @dir10
D
D
D
D
D
D
08
18
0C
1C
0B
1B
b
a
2a
2a
2a
2a
----
----
----
----
----
----
(dir10) →R13
Word
Word
Word
Word
Word
Word
R13→(dir10)
(dir10) →(R13),R13+=4
(R13) →(dir10),R13+=4
R15-=4, (R15) →(dir10)
(R15) →(dir10),R15+=4
*
DMOVH @dir9, R13
DMOVH R13, @dir9
DMOVH @dir9, @R13+
DMOVH @R13+, @dir9
D
D
D
D
09
19
0D
1D
b
a
2a
2a
----
----
----
----
(dir9) →R13
Half word
Half word
Half word
Half word
R13→(dir9)
(dir9) →(R13),R13+=2
(R13) →(dir9),R13+=2
*
*
DMOVB @dir8, R13
DMOVB R13, @dir8
DMOVB @dir8, @R13+
DMOVB @R13+, @dir8
D
D
D
D
0A
1A
0E
1E
b
a
2a
2a
----
----
----
----
(dir8) →R13
R13→(dir8)
(dir8) →(R13),R13++
(R13) →(dir8),R13++
Byte
Byte
Byte
Byte
Note:
The assembler calculates and sets values as follows in the dir8, dir9, and dir10 fields.
Dir8→dir, dir9/2→dir, dir10/4→dirdir8, dir9, dir10 are without sign.
■ Resource Instruction
Table E-21 resource instruction
Mnemonic
Type
C
OP
BC
BD
CYCLE
NZVC
----
Operation
Remark
LDRES @Ri+, #u4
STRES #u4, @Ri+
a
a
(Ri) → Resource of u4
Ri+=4
(Ri) → Resource of u4
Ri+=4
u4: Channel number
u4: Channel number
C
----
■ Coprocessor Control Instruction
Table E-22 Coprocessor control instruction
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remark
COPOP #u4, #u8, CRj, CRi
COPLD #u4, #u8, Rj, CRi
COPST #u4, #u8, CRj, Ri
COPSV #u4, #u8, CRj, Ri
E
E
E
E
9F-C
9F-D
9F-E
9F-F
2+a
----
----
----
----
Operation instruction
1+2a
1+2a
1+2a
Rj→CRi
CRj→Ri
CRj→Ri
Error trap none
Note:
•
{CRi | CRj}:=CR0 | CR1 | CR2 | CR3 | CR4 | CR5 | CR6 | CR7 | CR8 | CR9 | CR10 | CR11 | CR12 | CR13 | CR14 | CR15
u4:= channel specification
u8:= command specification
326
Download from Www.Somanuals.com. All Manuals Search And Download.
INDEX
Numerics
Block Diagram of Flash Memory ..........................281
Block Diagram of FRC Capture............................159
Block Diagram of Gear Control Section..................77
Block Diagram of Interrupt Controller ...................230
Block Diagram of Port 0........................................119
Block Diagram of Port 1........................................121
Block Diagram of Port 2, 3....................................123
Block Diagram of Port 4, 8, 9................................131
Block Diagram of Port 5........................................125
Block Diagram of Port 6, 7....................................128
Block Diagram of Port A, B...................................135
Block Diagram of Port C, D ..................................137
0 Detection........................................................... 271
0 Detection Data Register (BSD0)....................... 269
1 Detection........................................................... 271
1 Detection Data Register (BSD1)....................... 269
20-bit Delayed Divergence Macro Instruction...... 323
20-bit Normal Divergence Macro Instruction........ 322
32-bit Delayed Divergence Macro Instruction...... 325
32-bit Normal Divergence Macro Instruction........ 324
A
A/D Converter Control Register (ADCH, ADCL).. 239
A/D Operation by Hard Conversion ..................... 246
A/D Operation by Soft Conversion....................... 245
Activating Watchdog Timer.................................... 82
Addition and Subtraction Instruction .................... 315
Address Offset Register (SxAO).......................... 255
Area Mode Register 1 (AMD1)............................... 94
Area of Bus Interface ............................................. 88
Block Diagram of Programmable Pulse Generator
(PPG0, 1) ...................................................168
Block Diagram of Real Timing Generator (RTG)..178
Block Diagram of Reel Input.................................152
Block Diagram of Reset Factor Retention Circuit...68
Block Diagram of Serial I/O ..................................250
Block Diagram of Sleep Control Section ................73
Block Diagram of Stop Control Section ..................70
Block Diagram of Watchdog Control Section .........82
Branch Command with Delay Slot..........................42
Branch Command without Delay Slot.....................44
Bus Access of Big Endian ......................................97
Bus Access of Little Endian....................................97
Bus Interface ..........................................................89
Byte Access..........................................................110
Byte Ordering .........................................................37
Area Selection Register (ASR) and Area Mask
Register (AMR)............................................ 91
At Power On........................................................... 22
Auto Algorithm Execute State.............................. 287
B
Bit Manipulation Instructions................................ 316
Bit Ordering............................................................ 37
Block Diagram of 10-bit A/D Converter................ 238
Block Diagram of 10-bit General-purpose Prescaler
................................................................... 262
C
Cancellation of Interrupt Cause............................235
CAPF Bit...............................................................215
Capstan Control Register (CAPC)........................144
Capstan Input .......................................................142
Capstan Input Control Register (CAPDVC)..........145
Block Diagram of 12-bit PWM.............................. 204
Block Diagram of 16-bit Timer (Timer 0 to 4)....... 188
Block Diagram of 8-/16-bit Timer/Counter ........... 195
Block Diagram of 8-bit Pulse Width Counter........ 212
Block Diagram of All MB91191/MB91192 Series..... 4
Block Diagram of Bit Search Module ................... 268
Block Diagram of Capstan Input .......................... 143
Block Diagram of Clock Generation Section.......... 60
Block Diagram of Delayed Interrupt Module ........ 226
Block Diagram of Drum Input............................... 148
Block Diagram of External Bus Interface ............... 87
Block Diagram of External Interrupt (INT0 to 2)... 221
Capstan Mask Timer Control Register (CAPMTC)
...................................................................145
Capture Control Register (CAPC) ........................163
Capture Data ........................................................165
Capture Data Registers (CAPD2 to 0)..................164
Capture Input Control Register (CIC1, CIC0).......160
Capture Source Register (CAPS).........................164
Change Point Detection........................................272
Change Point Detection Data Register (BSDC) ...269
Block Diagram of External Interrupt 1 (Key Input
Circuit) ....................................................... 219
327
Download from Www.Somanuals.com. All Manuals Search And Download.
Clock Mode Setting Register (SxMR)...................253
Clock Series Diagram.............................................80
Command Operation............................................288
F
Feature of 10-bit A/D Converter........................... 238
Feature of 10-bit General-purpose Prescaler ...... 262
Feature of 12-bit PWM......................................... 204
Feature of 8-/16-bit Timer/Counter ...................... 195
Feature of 8-bit Pulse Width Counter................... 212
Feature of Bit Search Module .............................. 268
Feature of CPU Architecture.................................. 26
Feature of External Bus Interface .......................... 86
Feature of External Interrupt................................ 218
Feature of External Interrupt (INT0 to 2).............. 221
Feature of FRC Capture ...................................... 158
Feature of MB91191/MB91192 Series..................... 2
Comparison of External Access between Big Endian
and Little Endian ..........................................97
Comparison Operation Instruction........................315
Configuration of Timer..........................................186
Connection Example with External Device...103, 106
Construction of Internal Architecture......................26
Control in 16-bit Mode..........................................202
Controlling Method of FIFO..................................165
Coprocessor Absent Trap ......................................54
Coprocessor Control Instruction...........................326
Coprocessor Error Trap..........................................54
Count Data Register (TxCD1, TxCD0).................200
Crystal Oscillation Circuit .......................................22
Feature of Programmable Pulse Generator (PPG0, 1)
................................................................... 168
Feature of Real Timing Generator (RTG) ............ 178
Feature of Serial I/O............................................. 250
Feature of Timer .................................................. 186
Flash Memory Status Register (FSTR)................ 284
FRC Count Data Register (FRCD2 to 0).............. 164
D
Data Access...........................................................38
Data Bus Width ..............................................99, 105
Data Format ...................................................99, 104
Data Register (GPRD)..........................................264
Dedicated Registers List ........................................29
Delay Divergence Instruction ...............................320
Delay Slot...............................................................54
Delayed Interrupt Control Register (DICR)...........227
Detection Result Register (BSRR).......................270
FR-CPU Programming Mode (16-bit, Read/Write)
................................................................... 286
FR-CPU ROM Mode (32-bit, Read Only)............. 286
Functions of I/O Port 0......................................... 119
Functions of I/O Port 1......................................... 121
Functions of I/O Port 2, 3..................................... 123
Functions of Port 4, 8, 9....................................... 131
Functions of Port 5............................................... 125
Functions of Port A, B.......................................... 135
Functions of Port C, D.......................................... 137
Differences between Little Endian and Big Endian
...................................................................104
Direct Addressing Area ..........................................24
Direct Addressing Instruction ...............................326
Division Operation and PO Output.......................265
DLYI Bit of DICR ..................................................228
Drum Control Register (DRMC) ...........................149
Drum Input ...........................................................142
Drum Input Control Register (DRMDVC) .............150
Drum Mask Timer Control Register (DRMMTC) ..151
G
Gear Control Register (GCR)................................. 65
General-purpose Register...................................... 36
H
Half-word Access................................................. 109
Handling NC Pin .................................................... 22
Hard Conversion FIFO Data Register (HCFD) .... 243
Hard Conversion Status Register (HCSR)........... 242
Hardware Sequence Flag.................................... 292
How to Read the Instruction List.......................... 310
E
EIT (Exception, Interruption, and Trap)..................45
EIT Factor ..............................................................45
EIT Vector Table ....................................................48
External Bus Access ............................................100
External Clock Mode (Only Timer 4)....................194
External Interrupt Enable Register (EIE)..............222
External Interrupt Request Flag (EIF) ..................222
External Reset Input...............................................22
I
I/O Circuit Type...................................................... 15
I/O Map ................................................................ 298
Initialization by Reset............................................. 55
328
Download from Www.Somanuals.com. All Manuals Search And Download.
Initiation Procedure of Real Timing Generator (RTG)
................................................................... 183
Operation of 12-bit PWM......................................208
Operation of 16-bit Timer (Timer 0 to 4)...............193
Instruction Format................................................ 313
Instruction List of FR Series................................. 314
Internal Memory Area .......................................... 276
Interrupt Control................................................... 287
Interrupt Control Register (ICRxx) ....................... 232
Interrupt Function................................................. 259
Interrupt level of EIT............................................... 46
Interrupt Number.................................................. 228
Interrupt Stack........................................................ 47
Interrupt Vector .................................................... 306
Operation of 8-bit External Clock Mode (Event
Counter) .....................................................201
Operation of Branch Command with Delay Slot.....42
Operation of Branch Command without Delay Slot44
Operation of Capstan Input ..................................146
Operation of Drum Input.......................................151
Operation of EIT .....................................................51
Operation of External Interrupt (INT0 to 2)...........223
Operation of External Interrupt 1 (Key Input Circuit)
...................................................................220
Operation of INT Instruction ...................................52
Operation of Reel Input ........................................155
Operation of RETI Instruction.................................54
Operation of Serial I/O..........................................257
Operation of Step Trace Trap.................................53
Operation of Undefined Instruction Exception........53
Output Data Register (RTGxD) ............................182
Output Operation of PPG .....................................175
Overview of Flash Memory...................................280
Overview of Instructions .........................................40
Overview of Sleep Status .......................................73
Overview of Stop Status.........................................70
K
Key Input Control Register (KEYC)...................... 220
Key Input Status Register (KEYS) ....................... 220
L
Level Mask to Interruption/NMI.............................. 46
Limitations for Branch Command with Delay......... 43
Little Endian Register (LER) .................................. 96
Logical Operation Instruction ............................... 315
M
Measurement Accuracy of Peripheral Circuit Relative
to FRC and Output Timing Accuracy......... 308
P
Package Dimension (FLGA-144)..............................6
Package Dimension (LQFP-120)..............................5
Pin ............................................................................9
Pin Assignment (FLGA-144).....................................8
Pin Assignment (LQFP-120).....................................7
Pin Function List.......................................................9
Port 6, 7................................................................127
Power Supply Pin ...................................................22
PPG0 Frame Data................................................174
PPG1 Frame Data................................................174
PPGx Control Register (PPGxC)..........................171
Precaution when Clear IF Flag.............................176
Precautions.............................................................21
Precautions when Designing..................................18
Precautions when Mounting Package ....................19
Prescaler Control Register (GPRC)......................263
Priority Level of EIT Factor Acceptance .................49
Priority Order Evaluation ......................................233
Priority Order of A/D Conversion..........................246
Program Access .....................................................38
Program Counter (PC)............................................29
Program Example of External Bus Operation.......113
Memory Loading Instruction................................. 318
Memory Map.................................................... 24, 39
Memory Map and Sector Construction ................ 282
Memory Store Instruction..................................... 318
Mode (MD0 to MD2) Pin ........................................ 22
Mode Data ............................................................. 57
Mode Pin................................................................ 56
Mode Register (MODR) ......................................... 57
Multiplication and Division Instructions ................ 316
Multiplication and Division Result Register (MDH/
MDL)............................................................ 31
N
Normal Divergence (There is no delay) Instruction
................................................................... 319
Note on Using External Clock................................ 22
Notes on Writing to Mode Register (MODR).......... 58
O
Operation ............................................................. 151
Operation in 8-bit Internal Clock Mode ................ 201
Operation Mode ..................................................... 56
Operation Mode of Serial I/O ............................... 258
329
Download from Www.Somanuals.com. All Manuals Search And Download.
Program Specification Example of External Bus
Operation ...................................................113
Registers for Port A, B......................................... 136
Registers for Port C, D......................................... 138
Program Status Register (PS)..........................29, 32
Pulse Input Mask Function...................................215
Pulse Width Count Operation...............................215
PWC Control Register (PWCC)............................213
PWC Data Register (PWCD)................................214
PWMx Control Register (PWMxC).......................206
PWMx0 to 2 Data Register (PWMDxx) ................207
Relationship between Data Bus Width and Control
Signal........................................................... 97
Relationship between PPG Data RAM and Frame
................................................................... 173
Reset Factor .......................................................... 55
Reset Factor Register (RSRR) and Watchdog Timer
Cycle Control Register (WTCR)................... 61
Reset Generation Delay......................................... 83
Reset Sequence .................................................... 55
Resource Instruction............................................ 326
Restrictions for Using MB91191/MB91192 Series309
Restrictions of Gear Function ................................ 78
Return by Sleep Status.......................................... 74
Return by Standby Mode (Stop/Sleep) ................ 235
Return by Stop Status............................................ 71
Return from EIT ..................................................... 45
Return Pointer (RP) ............................................... 30
RTG Output Timing.............................................. 183
RTGx Control Register (RTGxC) ......................... 181
R
Reading of FRC Count Data ................................165
Ready/Busy Signal (RDY/BUSYX).......................292
Reel Control Register (RLC) ................................153
Reel Input.............................................................142
Reel Input Control Register (RLxDVC).................154
Reel Mask Timer Control Register (RLxMTC)......155
Register in Clock Generation Section ....................59
Register List of 10-bit A/D Converter....................238
Register List of 10-bit General-purpose Prescaler262
Register list of 12-bit PWM...................................205
Register List of 16-bit Timer (Timer 0 to 4)...........189
Register List of 8-/16-bit Timer/Counter...............196
Register List of 8-bit Pulse Width Counter ...........212
Register List of Bit Search Module.......................268
Register List of Capstan Input..............................143
Register List of Delayed Interrupt Module............226
Register List of Drum Input ..................................148
Register List of External Bus Interface...................90
Register List of External Interrupt (INT0 to 2).......221
S
Save/Return Processes....................................... 273
Serial Control Register (SxCR)............................ 252
Serial Data RAM .................................................. 256
Setting of Gear Function........................................ 77
Setting of Reset Factor Retention.......................... 68
Shift Instruction .................................................... 317
Soft Conversion Analog Input Selection Register
(SCIS)........................................................ 240
Register List of External Interrupt 1 (Key Input Circuit)
...................................................................219
Soft Conversion FIFO Data Register (SCFD)...... 242
Soft Conversion Status Register (SCSR) ............ 241
Standby Control Register (STCR).......................... 63
Start Address Setting Register (PPGxSA)........... 172
Start Operation of PPG........................................ 176
Start/Stop Timing of Shift Operation .................... 259
State Transition in Standby Mode.......................... 76
State Transition of 10-bit A/D Converter.............. 247
Symbol of Addressing Mode................................ 312
System Stack Pointer (SSP).................................. 30
Register List of Flash Memory..............................281
Register List of FRC Capture ...............................158
Register List of I/O Port........................................118
Register List of Interrupt Controller ......................231
Register List of Programmable Pulse Generator
(PPG0, 1) ...................................................170
Register List of Real Timing Generator (RTG).....180
Register List of Reel Input....................................152
Register List of Serial I/O .....................................251
Register List of Timer...........................................187
Register List of Wait Controller.............................276
Registers for Port 0 ..............................................120
Registers for Port 1 ..............................................122
Registers for Port 2, 3 ..........................................124
Registers for Port 4, 8, 9 ......................................132
Registers for Port 5 ..............................................126
Registers for Port 6, 7 ..........................................129
T
Table Base Register (TBR).................................... 30
Table for Clock Series List of Peripheral Resource81
The Other Instruction........................................... 321
The Relationship between the Data Bus Width and
Control Signal .............................................. 98
Time Division I/O Interface................................... 112
330
Download from Www.Somanuals.com. All Manuals Search And Download.
Timebase Timer..................................................... 83
Timebase Timer Clear Register (CTBR)................ 64
Timer Control Register 0 (TxCR0) ....................... 198
Timer Control Register 1 (TxCR1) ....................... 197
Timer Control Register H (TxCRH)...................... 191
Timer Control Register L (TxCRL) ....................... 190
Timer Count Register H, L (TxCDH, TxCDL)....... 192
Timer Data Register 1, 0 (TxDR1, TxDR0).......... 200
Timer Data Register H, L (TxDRH, TxDRL)......... 192
Timing Data Register (PPGxT) ............................ 172
Timing Data Register (RTGxT) ............................ 182
Transfer Byte Number Setting Register (SxBR) .. 255
Transfer Instruction between Registers ............... 319
Transition to Sleep Status...................................... 74
Transition to Stop Status........................................ 71
U
Update Operation of Reload Data Latch ..............265
Update procedure of PWM data...........................209
Update Timing Data Register ...............................176
User Stack Pointer (USP).......................................31
V
Value Move Operation of Value Sets/16 Bits/32 Bits
Immediately................................................317
W
Wait Control Register (WAITC) ............................277
Watchdog Reset Generation Delay Register (WPR)
.....................................................................67
Word Access ........................................................108
331
Download from Www.Somanuals.com. All Manuals Search And Download.
332
Download from Www.Somanuals.com. All Manuals Search And Download.
CM71-10113-1E
FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL
FR20
32 BIT MICRO CONTROLLER
MB91191/MB91192 SERIES
HARDWARE MANUAL
March 2004 the first edition
Published FUJITSU LIMITED Electronic Devices
Edited
Business Promotion Dept.
Download from Www.Somanuals.com. All Manuals Search And Download.
334
Download from Www.Somanuals.com. All Manuals Search And Download.
|