Cypress Computer Hardware STK11C68 User Manual

STK11C68  
64 Kbit (8K x 8) SoftStore nvSRAM  
Features  
Functional Description  
25 ns, 35 ns, and 45 ns access times  
Pin compatible with industry standard SRAMs  
Software initiated nonvolatile STORE  
Unlimited Read and Write endurance  
Automatic RECALL to SRAM on power up  
Unlimited RECALL cycles  
The Cypress STK11C68 is a 64Kb fast static RAM with a nonvol-  
atile element in each memory cell. The embedded nonvolatile  
elements incorporate QuantumTrap technology producing the  
world’s most reliable nonvolatile memory. The SRAM provides  
unlimited read and write cycles, while independent nonvolatile  
data resides in the highly reliable QuantumTrap cell. Data  
transfers under software control from SRAM to the nonvolatile  
elements (the STORE operation). On power up, data is automat-  
ically restored to the SRAM (the RECALL operation) from the  
nonvolatile memory. RECALL operations are also available  
under software control.  
1,000,000 STORE cycles  
100 year data retention  
Single 5V+10% operation  
Commercial and industrial temperature  
28-pin (330 mil) SOIC package  
28-pin (300 mil) CDIP and 28-pad (350 mil) LCC packages  
RoHS compliance  
Logic Block Diagram  
V
CC  
V
CAP  
Quantum Trap  
128 X 512  
A5  
POWER  
STORE  
CONTROL  
A6  
A7  
A8  
RECALL  
STORE/  
RECALL  
CONTROL  
STATIC RAM  
ARRAY  
128 X 512  
HSB  
A9  
A11  
A12  
SOFTWARE  
DETECT  
A0  
-
A12  
DQ0  
COLUMN I/O  
DQ1  
DQ2  
DQ3  
COLUMN DEC  
DQ4  
DQ5  
DQ6  
DQ7  
A0  
A4  
A10  
A1  
A3  
A2  
OE  
CE  
WE  
Cypress Semiconductor Corporation  
Document Number: 001-50638 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 30, 2009  
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STK11C68  
not necessary that OE is LOW for a valid sequence. After the  
tSTORE cycle time is fulfilled, the SRAM is again activated for  
Read and Write operation.  
Device Operation  
The STK11C68 is a versatile memory chip that provides several  
modes of operation. The STK16C88 can operate as a standard  
8K x 8 SRAM. A 8K x 8 array of nonvolatile storage elements  
shadow the SRAM. SRAM data can be copied nonvolatile  
memory or nonvolatile data can be recalled to the SRAM.  
Software RECALL  
Data is transferred from the nonvolatile memory to the SRAM by  
a software address sequence. A software RECALL cycle is  
initiated with a sequence of Read operations in a manner similar  
to the software STORE initiation. To initiate the RECALL cycle,  
the following sequence of CE controlled Read operations is  
performed:  
SRAM Read  
The STK11C68 performs a Read cycle whenever CE and OE are  
LOW while WE is HIGH. The address specified on pins A0–12  
determines the 8,192 data bytes accessed. When the Read is  
initiated by an address transition, the outputs are valid after a  
delay of tAA (Read cycle 1). If the Read is initiated by CE or OE,  
the outputs are valid at tACE or at tDOE, whichever is later (Read  
cycle 2). The data outputs repeatedly respond to address  
changes within the tAA access time without the need for transi-  
tions on any control input pins, and remains valid until another  
address change or until CE or OE is brought HIGH, or WE  
brought LOW.  
1. Read address 0x0000, Valid READ  
2. Read address 0x1555, Valid READ  
3. Read address 0x0AAA, Valid READ  
4. Read address 0x1FFF, Valid READ  
5. Read address 0x10F0, Valid READ  
6. Read address 0x0F0E, Initiate RECALL cycle  
Internally, RECALL is a two step procedure. First, the SRAM data  
is cleared; then, the nonvolatile information is transferred into the  
SRAM cells. After the tRECALL cycle time, the SRAM is again  
ready for Read and Write operations. The RECALL operation  
does not alter the data in the nonvolatile elements. The nonvol-  
atile data can be recalled an unlimited number of times.  
SRAM Write  
A Write cycle is performed whenever CE and WE are LOW. The  
address inputs must be stable prior to entering the Write cycle  
and must remain stable until either CE or WE goes HIGH at the  
end of the cycle. The data on the common IO pins DQ0–7 are  
written into the memory if it has valid tSD, before the end of a WE  
controlled Write or before the end of an CE controlled Write.  
Keep OE HIGH during the entire Write cycle to avoid data bus  
contention on common IO lines. If OE is left LOW, internal  
circuitry turns off the output buffers tHZWE after WE goes LOW.  
Hardware RECALL (Power Up)  
During power up or after any low power condition (VCC  
<
V
RESET), an internal RECALL request is latched. When VCC  
once again exceeds the sense voltage of VSWITCH, a RECALL  
cycle is automatically initiated and takes tHRECALL to complete.  
If the STK11C68 is in a Write state at the end of power up  
RECALL, the SRAM data is corrupted. To help avoid this  
situation, a 10 Kohm resistor is connected either between WE  
Software STORE  
Data is transferred from the SRAM to the nonvolatile memory by  
a software address sequence. The STK11C68 software STORE  
cycle is initiated by executing sequential CE controlled Read  
cycles from six specific address locations in exact order. During  
the STORE cycle, an erase of the previous nonvolatile data is  
first performed followed by a program of the nonvolatile  
elements. When a STORE cycle is initiated, input and output are  
disabled until the cycle is completed.  
and system VCC or between CE and system VCC  
.
Hardware Protect  
The STK11C68 offers hardware protection against inadvertent  
STORE operation and SRAM Writes during low voltage condi-  
tions. When VCAP<VSWITCH, all externally initiated STORE  
operations and SRAM Writes are inhibited.  
Because a sequence of Reads from specific addresses is used  
for STORE initiation, it is important that no other Read or Write  
accesses intervene in the sequence. If they intervene, the  
sequence is aborted and no STORE or RECALL takes place.  
Noise Considerations  
The STK11C68 is a high speed memory. It must have a high  
frequency bypass capacitor of approximately 0.1 µF connected  
between VCC and VSS, using leads and traces that are as short  
as possible. As with all high speed CMOS ICs, careful routing of  
power, ground, and signals reduce circuit noise.  
To initiate the software STORE cycle, the following Read  
sequence is performed:  
1. Read address 0x0000, Valid READ  
2. Read address 0x1555, Valid READ  
3. Read address 0x0AAA, Valid READ  
4. Read address 0x1FFF, Valid READ  
5. Read address 0x10F0, Valid READ  
6. Read address 0x0F0F, Initiate STORE cycle  
Low Average Active Power  
CMOS technology provides the STK11C68 the benefit of  
drawing significantly less current when it is cycled at times longer  
than 50 ns. Figure 2 shows the relationship between ICC and  
Read or Write cycle time. Worst case current consumption is  
shown for both CMOS and TTL input levels (commercial temper-  
ature range, VCC = 5.5V, 100% duty cycle on chip enable). Only  
standby current is drawn when the chip is disabled. The overall  
The software sequence is clocked with CE controlled Reads.  
When the sixth address in the sequence is entered, the STORE  
cycle commences and the chip is disabled. It is important that  
Read cycles and not Write cycles are used in the sequence. It is  
Document Number: 001-50638 Rev. **  
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STK11C68  
average current drawn by the STK11C68 depends on the  
following items:  
Best Practices  
nvSRAM products have been used effectively for over 15 years.  
While ease of use is one of the product’s main system values,  
experience gained working with hundreds of applications has  
resulted in the following suggestions as best practices:  
The duty cycle of chip enable  
The overall cycle rate for accesses  
The ratio of Reads to Writes  
CMOS versus TTL input levels  
The operating temperature  
The VCC level  
The nonvolatile cells in an nvSRAM are programmed on the  
test floor during final test and quality assurance. Incoming  
inspection routines at customer or contract manufacturer’s  
sites sometimes reprograms these values. Final NV patterns  
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.  
Theendproduct’sfirmwareshouldnotassumethatanNVarray  
is in a set programmed state. Routines that check memory  
content values to determine first time system configuration,  
IO loading  
Figure 2. Current Versus Cycle Time (Read)  
cold or warm boot status, and so on must always program a  
unique NV pattern (for example, complex 4-byte pattern of 46  
E6 49 53 hex or more random bytes) as part of the final system  
manufacturing test to ensure these system routines work  
consistently.  
Power up boot firmware routines should rewrite the nvSRAM  
into the desired state. While the nvSRAM is shipped in a preset  
state, best practice is to again rewrite the nvSRAM into the  
desired state as a safeguard against events that might flip the  
bit inadvertently (program bugs, incoming inspection routines,  
and so on).  
Figure 3. Current Versus Cycle Time (Write)  
Table 1. Hardware Mode Selection  
CE  
WE  
A12–A0  
Mode  
IO  
Notes  
[1]  
L
H
0x0000  
0x1555  
0x0AAA  
0x1FFF  
0x10F0  
0x0F0F  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
Nonvolatile STORE  
[1]  
L
H
0x0000  
0x1555  
0x0AAA  
0x1FFF  
0x10F0  
0x0F0E  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
Nonvolatile RECALL  
Note  
1. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.  
Document Number: 001-50638 Rev. **  
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STK11C68  
Power Dissipation ......................................................... 1.0W  
DC Output Current (1 output at a time, 1s duration).... 15 mA  
Maximum Ratings  
Exceeding maximum ratings may shorten the useful life of the  
device. These user guidelines are not tested.  
Operating Range  
Storage Temperature ................................. –65°C to +150°C  
Temperature under bias.............................. –55°C to +125°C  
Supply Voltage on VCC Relative to GND ..........–0.5V to 7.0V  
Voltage on Input Relative to Vss............0.6V to VCC + 0.5V  
Voltage on DQ0-7 ...................................–0.5V to Vcc + 0.5V  
Ambient  
Range  
VCC  
Temperature  
0°C to +70°C  
-40°C to +85°C  
Commercial  
Industrial  
4.5V to 5.5V  
4.5V to 5.5V  
DC Electrical Characteristics  
Over the operating range (VCC = 4.5V to 5.5V)  
Parameter  
ICC1  
Description  
Test Conditions  
Min  
Max  
Unit  
Average VCC Current tRC = 25 ns  
Commercial  
90  
75  
65  
mA  
mA  
mA  
t
t
RC = 35 ns  
RC = 45 ns  
Dependent on output loading and cycle rate.  
Values obtained without output loads.  
Industrial  
90  
75  
65  
mA  
mA  
mA  
IOUT = 0 mA.  
ICC2  
ICC3  
Average VCC Current All Inputs Do Not Care, VCC = Max  
during STORE Average current for duration tSTORE  
3
mA  
Average VCC Current at WE > (VCC – 0.2V). All other inputs cycling.  
tRC= 200 ns, 5V, 25°C Dependent on output loading and cycle rate. Values obtained  
10  
mA  
Typical  
without output loads.  
[2]  
ISB1  
VCC Standby Current  
(Standby, Cycling TTL tRC = 35 ns, CE > VIH  
Input Levels)  
tRC = 25 ns, CE > VIH  
Commercial  
Industrial  
27  
23  
20  
mA  
mA  
mA  
tRC = 45 ns, CE > VIH  
28  
24  
21  
mA  
mA  
mA  
[2]  
ISB2  
VCC Standby Current  
CE > (VCC – 0.2V). All others VIN < 0.2V or > Commercial  
(VCC – 0.2V). Standby current level after  
750  
μA  
nonvolatile cycle is complete.  
Inputs are static. f = 0 MHz.  
Industrial  
1500  
μA  
IIX  
Input Leakage Current VCC = Max, VSS < VIN < VCC  
-1  
-5  
+1  
+5  
μA  
μA  
IOZ  
Off State Output  
Leakage Current  
VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL  
VIH  
Input HIGH Voltage  
2.2  
VCC  
0.5  
+
V
VIL  
Input LOW Voltage  
VSS – 0.5  
2.4  
0.8  
V
V
V
VOH  
VOL  
Output HIGH Voltage IOUT = –4 mA  
Output LOW Voltage  
IOUT = 8 mA  
0.4  
Data Retention and Endurance  
Parameter  
Description  
Min  
100  
Unit  
DATAR  
NVC  
Data Retention  
Years  
K
Nonvolatile STORE Operations  
1,000  
Note  
2. CE > V does not produce standby current levels until any nonvolatile cycle in progress has timed out.  
IH  
Document Number: 001-50638 Rev. **  
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STK11C68  
Capacitance  
In the following table, the capacitance parameters are listed.[3]  
Parameter  
CIN  
COUT  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
Max  
8
Unit  
pF  
TA = 25°C, f = 1 MHz,  
CC = 0 to 3.0V  
V
7
pF  
Thermal Resistance  
In the following table, the thermal resistance parameters are listed.[3]  
Parameter  
Description  
Test Conditions  
28-SOIC 28-CDIP 28-LCC Unit  
ΘJA  
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard test methods  
and procedures for measuring thermal  
impedance, per EIA / JESD51.  
TBD  
TBD  
TBD  
°C/W  
ΘJC  
Thermal Resistance  
(Junction to Case)  
TBD  
TBD  
TBD  
°C/W  
Figure 4. AC Test Loads  
R1 480Ω  
5.0V  
Output  
R2  
30 pF  
255Ω  
AC Test Conditions  
Input Pulse Levels....................................................0V to 3V  
Input Rise and Fall Times (10% to 90%)...................... <5 ns  
Input and Output Timing Reference Levels.................... 1.5V  
Note  
3. These parameters are guaranteed by design and are not tested.  
Document Number: 001-50638 Rev. **  
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STK11C68  
AC Switching Characteristics  
SRAM Read Cycle  
Parameter  
25 ns  
35 ns  
45 ns  
Unit  
Description  
Cypress  
Alt  
Min  
Max  
Min  
Max  
Min  
Max  
Parameter  
tACE  
tELQV  
tAVAV, ELEH  
tAVQV  
Chip Enable Access Time  
Read Cycle Time  
25  
35  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tRC  
t
25  
35  
45  
[5]  
tAA  
tDOE  
Address Access Time  
25  
10  
35  
15  
45  
20  
tGLQV  
Output Enable to Data Valid  
Output Hold After Address Change  
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
[5]  
tOHA  
tAXQX  
5
5
5
5
5
5
[6]  
[6]  
[6]  
[6]  
tLZCE  
tHZCE  
tLZOE  
tHZOE  
tELQX  
tEHQZ  
10  
10  
25  
13  
13  
35  
15  
15  
45  
tGLQX  
0
0
0
0
0
0
tGHQZ  
[3]  
tPU  
tELICCH  
tEHICCL  
[3]  
tPD  
Switching Waveforms  
Figure 5. SRAM Read Cycle 1: Address Controlled [4, 5]  
W5&  
$''5(66  
W$$  
W2+$  
'4ꢌꢊ'$7$ꢌ287ꢋ  
'$7$ꢌ9$/,'  
Figure 6. SRAM Read Cycle 2: CE and OE Controlled [4]  
W5&  
$''5(66  
&(  
W$&(  
W3'  
W+=&(  
W/=&(  
2(  
W+=2(  
W'2(  
W/=2(  
'4ꢌꢊ'$7$ꢌ287ꢋ  
'$7$ꢌ9$/,'  
$&7,9(  
W38  
67$1'%<  
,&&  
Notes  
4. WE must be High during SRAM Read cycles.  
5. I/O state assumes CE and OE < V and WE > V ; device is continuously selected.  
IL  
IH  
6. Measured ±200 mV from steady state output voltage.  
Document Number: 001-50638 Rev. **  
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STK11C68  
SRAM Write Cycle  
Parameter  
25 ns  
35 ns  
45 ns  
Unit  
Description  
Write Cycle Time  
Cypress  
Parameter  
Alt  
Min  
Max  
Min  
Max  
Min  
Max  
tWC  
tAVAV  
tWLWH, WLEH  
tELWH, ELEH  
tDVWH, DVEH  
tWHDX, EHDX  
tAVWH, AVEH  
tAVWL, AVEL  
tWHAX, EHAX  
tWLQZ  
tWHQX  
25  
20  
20  
10  
0
35  
25  
25  
12  
0
45  
30  
30  
15  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tPWE  
tSCE  
tSD  
t
Write Pulse Width  
t
Chip Enable To End of Write  
Data Setup to End of Write  
Data Hold After End of Write  
Address Setup to End of Write  
Address Setup to Start of Write  
Address Hold After End of Write  
Write Enable to Output Disable  
Output Active After End of Write  
t
tHD  
t
tAW  
t
20  
0
25  
0
30  
0
tSA  
t
tHA  
t
0
0
0
[6,7]  
tHZWE  
tLZWE  
10  
13  
15  
5
5
5
Switching Waveforms  
Figure 7. SRAM Write Cycle 1: WE Controlled [7, 8]  
tWC  
ADDRESS  
CE  
tHA  
tSCE  
tAW  
tSA  
tPWE  
WE  
tHD  
tSD  
DATA VALID  
DATA IN  
tHZWE  
tLZWE  
HIGH IMPEDANCE  
PREVIOUS DATA  
DATA OUT  
Figure 8. SRAM Write Cycle 2: CE and OE Controlled [7, 8]  
tWC  
ADDRESS  
tHA  
tSCE  
tSA  
CE  
WE  
tAW  
tPWE  
tSD  
tHD  
DATA IN  
DATA VALID  
HIGH IMPEDANCE  
DATA OUT  
Notes  
7. If WE is Low when CE goes Low, the outputs remain in the high impedance state.  
8.  
CE or WE must be greater than V during address transitions.  
IH  
Document Number: 001-50638 Rev. **  
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STK11C68  
AutoStore INHIBIT or Power Up RECALL  
STK11C68  
Max  
Parameter  
Alt  
Description  
Unit  
Min  
[9]  
tHRECALL  
tRESTORE  
tHLHZ  
Power up RECALL Duration  
STORE Cycle Duration  
550  
10  
μs  
ms  
V
tSTORE  
VSWITCH  
VRESET  
Low Voltage Trigger Level  
Low Voltage Reset Level  
4.0  
4.5  
3.6  
V
Switching Waveform  
Figure 9. AutoStore INHIBIT/Power Up RECALL  
VCC  
5V  
VSWITCH  
VRESET  
STORE INHIBIT  
POWER-UP RECALL  
t
HRECALL  
DQ (DATA OUT)  
POWER-UP  
RECALL  
BROWN OUT  
STORE INHIBIT  
BROWN OUT  
STORE INHIBIT  
BROWN OUT  
STORE INHIBIT  
NO RECALL  
NO RECALL  
RECALL WHEN  
(V DID NOT GO  
(V DID NOT GO  
V
RETURNS  
CC  
CC  
CC  
BELOW V  
)
BELOW V  
)
ABOVE V  
RESET  
RESET  
SWITCH  
Note  
9.  
t
starts from the time V rises above V  
.
SWITCH  
HRECALL  
CC  
Document Number: 001-50638 Rev. **  
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STK11C68  
Software Controlled STORE/RECALL Cycle  
The software controlled STORE/RECALL cycle follows. [10, 11]  
25 ns  
35 ns  
45 ns  
Unit  
Parameter  
tRC  
Alt  
Description  
Min  
Max  
Min  
Max  
Min  
Max  
tAVAV  
tAVEL  
tELEH  
tELAX  
STORE/RECALL Initiation Cycle Time  
Address Setup Time  
25  
0
35  
0
45  
0
ns  
ns  
ns  
ns  
μs  
tSA  
tCW  
Clock Pulse Width  
20  
20  
25  
20  
30  
20  
tHACE  
Address Hold Time  
tRECALL  
RECALL Duration  
20  
20  
20  
Switching Waveform  
Figure 10. CE Controlled Software STORE/RECALL Cycle [11]  
tRC  
tRC  
ADDRESS # 1  
ADDRESS # 6  
ADDRESS  
tSA  
tSCE  
CE  
tHACE  
OE  
t
STORE / tRECALL  
HIGH IMPEDANCE  
DATA VALID  
DATA VALID  
DQ (DATA)  
Notes  
10. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).  
11. The six consecutive addresses must be read in the order listed in Table 1 on page 4. WE must be HIGH during all six consecutive cycles.  
Document Number: 001-50638 Rev. **  
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STK11C68  
Part Numbering Nomenclature  
STK11C68 - S F 45 I TR  
Packaging Option:  
TR = Tape and Reel  
Blank = Tube  
Temperature Range:  
Blank - Commercial (0 to 70°C)  
I - Industrial (-40 to 85°C)  
Speed:  
25 - 25 ns  
35 - 35 ns  
45 - 45 ns  
Lead Finish  
F = 100% Sn (Matte Tin)  
Package:  
S = Plastic 28-pin 330 mil SOIC  
C = Ceramic 28-pin 300 mil DIP  
L = Ceramic 28-pin 350 mil LLC  
Ordering Information  
Speed (ns)  
Ordering Code  
STK11C68-SF25TR  
STK11C68-SF25  
STK11C68-SF25ITR  
STK11C68-SF25I  
STK11C68-SF35TR  
STK11C68-SF35  
STK11C68-C35  
Package Diagram  
001-85058  
001-85058  
001-85058  
001-85058  
001-85058  
001-85058  
001-51695  
001-51696  
001-85058  
001-85058  
001-51695  
001-51696  
Package Type  
28-Pin SOIC (330 mil)  
28-Pin SOIC (330 mil)  
28-Pin SOIC (330 mil)  
28-Pin SOIC (330 mil)  
28-Pin SOIC (330 mil)  
28-Pin SOIC (330 mil)  
28-Pin CDIP (300 mil)  
28-Pin LCC (350 mil)  
28-Pin SOIC (330 mil)  
28-Pin SOIC (330 mil)  
28-Pin CDIP (300 mil)  
28-Pin LCC (350 mil)  
Operating Range  
25  
Commercial  
Industrial  
35  
Commercial  
STK11C68-L35  
STK11C68-SF35ITR  
STK11C68-SF35I  
STK11C68-C35I  
Industrial  
STK11C68-L35I  
Document Number: 001-50638 Rev. **  
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STK11C68  
Ordering Information (continued)  
Speed (ns)  
Ordering Code  
STK11C68-SF45TR  
STK11C68-SF45  
STK11C68-C45  
Package Diagram  
001-85058  
001-85058  
001-51695  
001-51696  
001-85058  
001-85058  
001-51695  
001-51696  
Package Type  
28-Pin SOIC (330 mil)  
28-Pin SOIC (330 mil)  
28-Pin CDIP (300 mil)  
28-Pin LCC (350 mil)  
28-Pin SOIC (330 mil)  
28-Pin SOIC (330 mil)  
28-Pin CDIP (300 mil)  
28-Pin LCC (350 mil)  
Operating Range  
Commercial  
45  
STK11C68-L45  
STK11C68-SF45ITR  
STK11C68-SF45I  
STK11C68-C45I  
STK11C68-L45I  
Industrial  
All parts are Pb-free. The above table contains Final information. Contact your local Cypress sales representative for availability of these parts  
Document Number: 001-50638 Rev. **  
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STK11C68  
Package Diagrams  
Figure 11. 28-Pin (330 Mil) SOIC (51-85058)  
51-85058 *A  
Document Number: 001-50638 Rev. **  
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STK11C68  
Package Diagrams (continued)  
Figure 12. 28-Pin (300 Mil) Side Braze DIL (001-51695)  
001-51695 **  
Document Number: 001-50638 Rev. **  
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STK11C68  
Package Diagrams (continued)  
Figure 13. 28-Pad (350 Mil) LCC (001-51696)  
1. ALL DIMENSION ARE IN INCHES AND MILLIMETERS [MIN/MAX]  
2. JEDEC 95 OUTLINE# MO-041  
001-51696 **  
3. PACKAGE WEIGHT : TBD  
Document Number: 001-50638 Rev. **  
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STK11C68  
Document History Page  
Document Title: STK11C68 64 Kbit (8K x 8) SoftStore nvSRAM  
Document Number: 001-50638  
Orig. of  
Change  
Submission  
Date  
Rev.  
ECN No.  
Description of Change  
**  
2625084  
GVCH/PYRS  
01/30/09  
New data sheet  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any  
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,  
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical  
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-50638 Rev. **  
Revised January 30, 2009  
Page 16 of 16  
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective  
holders.  
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