Cypress Computer Hardware CY7C68003 User Manual

DATA BRIEF

CY7C68003

MoBL-USB™ TX2UL USB 2.0

ULPI Transceiver

■ UART Pass Through Mode

■ ESD Compliance:

❐ JESD22-A114D 8 kV Contact Human Body Model (HBM) for

DP, DM, and VSS Pins

❐ IEC61000-4-2 8 kV Contact Discharge

❐ IEC61000-4-2 15 kV Air Discharge

Features

™

The Cypress MoBL-USB TX2UL is a low voltage high speed

(HS) USB 2.0 ULPI Transceiver.

The TX2UL is specifically designed for mobile handset

applications by offering tiny package options and low power

consumption.

■ Support for Industrial Temperature Range (-40°C to 85°C)

■ USB 2.0 Full Speed and High Speed Compliant Transceiver

■ Multi-Range (1.8V to 3.3V) IO Voltages

■ Fully Compliant ULPI Link Interface

■ 8-bit SDR ULPI Data Path

■ Low Power Consumption for Mobile Applications:

❐ 5 uA Nominal Sleep Mode

❐ 30 mA Nominal Active HS Transfer

■ Small Package for Mobile Applications:

❐ 2.14 x 1.76 mm 20-pin WLCSP 0.4 mm Pitch

❐ 4 x 4 mm 24-pin QFN

■ UTMI+ Level 0 Support

■ Integrated Oscillator

Applications

■ Integrated PLL (13, 19.2, 24, or 26 MHz Reference)

■ Integrated USB Pull Up and Termination Resistors

■ 3.0V to 5.775V VBATT Input

■ Mobile Phones

■ PDAs

■ Portable Media Players (PMPs)

■ DTV Applications

■ Portable GPS Units

■ Chip Select Pin

■ Single Ended Device RESET Input

TX2UL Block Diagram

TX2UL

ULPI Block

CLOCK

Control/

Data

Operational

mode

tracking

interrupt

DATA[7:0]

Tx/Rx

Core

DIR

USB

Logic

UTMI+

FS/HS

Level0

PHY

STP

Registers

Block

NXT

ULPI Wrapper

RXD

TXD

Global Control Block

Reset / Clock / Power /

Misc. Control

RESET_N

CS_N

3.3V Regulator

Block

VBATT

(3.0 –

5.775V)

VCC

(1.8V)

POR

1.8V

Bandgap

PLL

13/19.2/

24/26 MHz

XOSC

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 1, 2009

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CY7C68003

Clocking

TX2UL supports external crystal and clock inputs at the 13, 19.2,

24, and 26 MHz frequencies. The internal PLL applies the proper

clock multiply option depending on the input frequency. For appli-

cations that use an external clock source to drive XI, the XO pin

(in 24-pin QFN package) is left floating. TX2UL has an on-chip

oscillator circuit that uses an external 13, 19.2, 24, or 26 MHz

(±100 ppm) crystal with the following characteristics:

The selection between input clock source and frequency on the

XI pin is determined by the Chip Configuration register loaded

through the RESET_N during Configuration Mode. The external

clock source requirements are shown in Figure 3 on page 4.

Figure 2. Crystal Configuration

■ Parallel Resonant

TX2UL

■ Fundamental Mode

XTAL

■ 750 mW Drive Level

PLL

■ 12 pF (5 percent tolerance) Load Capacitors

■ 150 ppm

12 pf

TX2UL operates on one of two primary clock sources:

■ LVCMOS square wave clock input driven on the XI pin

■ Crystal generated sine wave clock on the XI and XO pins

* 12 pF capacitor values assumes a trace capacitance of

3 pF per side on a four layer FR4 PCA

Table 3. External Clock Requirements

Specification

Unit

Parameter

Description

Min

Max

Supply Voltage Noise at frequencies < 50 MHz

Input Phase Noise at 100 Hz

mV p-p

dBc/Hz

PN_100

PN_1k

–75

Input Phase Noise at 1 kHz offset

Input Phase Noise at 10 kHz offset

Input Phase Noise at 100 kHz offset

Input Phase Noise at 1 MHz offset

Duty Cycle

–104

–120

–128

–130

PN_10k

PN_100k

PN_1M

Maximum Frequency Deviation

150

ppm

VBATT

Power Domains

This is the battery input supply that powers the 3.3V Regulator

block. It can range anywhere from 3.0 to 5.775V during actual

operation.

The TX2UL has three power supply domains:

■ VCC

■ VIO

Voltage Regulator

■ VBATT

The internal 3.3V regulator block regulates the VBATT supply to

the internal 3.3V supply for the USBIO and XOSC blocks. If the

supply voltage at VBATT is below 3.3V, the regulator block

switches the VBATT supply directly for the USBIO and XOSC

blocks.

TX2UL has two grounds:

■ VSS

■ VSSBATT

Power Supply Sequence

VCC

TX2UL does not require power supply sequence. All power

supplies are independently sequenced without damaging the

part. All supplies are up and stable for the device to function

properly. The analog block contains circuitry that senses the

power supply to determine when all supplies are valid.

This is the core 1.8V power supply for the TX2UL. It can range

anywhere from 1.7V to 1.9V during actual operation.

VIO

This is the 1.8V to 3.3V multi range supply to the I/O ring. It can

range anywhere from 1.7V to 3.6V during actual operation.

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CY7C68003

Normal operation mode first, and then changes to Sleep mode.

The Mode Change State diagram in Figure 3 shows the mode

change path of TX2UL. The entries of the six operations modes

(20-pin CSP package has 5 operation modes) are listed in

T a ble 4 and T a ble 5. There are three mode change transactions

that require the RESET_N assert or deassert with tSTATE (see

Table 21 on page 19 for tSTATE). These three mode change

transactions are:

Operation Modes

There are six operation modes available in TX2UL. They are:

■ Normal Operation Mode

■ Configuration Mode

■ ULPI Low Power Mode

■ Sleep Mode

■ Change from Normal Operation Mode to Configuration Mode

– RESET_N is required to assert with tSTATE

■ Carkit UART Pass Through Mode

■ Tri-state ULPI Interface Output Mode (only available in 24-pin

QFN package)

■ Change from Configuration Mode to Normal Operation Mode

– RESET_N is required to de-assert with tSTATE

When changing the operation modes, if the current and changing

modes are not the Normal Operation Mode, TX2UL first changes

to the Normal Operation Mode. For example, to change from

ULPI Low power mode to Sleep mode, TX2UL changes to

■ Change from Normal Operation Mode to Sleep Mode –

RESET_N is required to assert with tSTATE

Figure 3. Mode Change State Diagram

Carkit UART Pass Through

Mode

Tri-State ULPI Interface

Output Mode (available in 24-

pin QFN package only)

Sleep Mode

Normal Operation Mode

Configuration Mode

ULPI Low Power Mode

Table 4. TX2UL 20-Pin CPS Package Operation Modes

Table 5. TX2UL 24-Pin QFN Package Operation Modes

RESET_N

Mode

CS_N

0 (Low)

RESET_N

Mode

0 (Low) Sleep Mode

0 (Low)

Sleep Mode

1 (High) Normal Operation Mode

1 (High) Enter into ULPI Low Power Mode by setting Sus-

pendM register bit (in Function Control Register) to

0 during the Normal Operation Mode.

1 (High) Enter into ULPI Low Power Mode

bysettingSuspendMregisterbit(in

Function Control Register) to 0 dur-

ing the Normal Operation Mode.

1 (High) Enter into Carkit UART Pass Through Mode by set-

ting Carkit Mode register bit (in Interface Control

0 (Low)

1 (High) Enter into Carkit UART Pass

Through Mode by setting Carkit

Mode register bit (in Interface Con-

trol Register) to 1 during the Nor-

mal Operation Mode.

0 (Low)

when

Power On

(VCC On)

Enter into Configuration Mode

1 (High)

0 (Low)

Configuration Mode

1 (High) Tri-state ULPI Interface output pins

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CY7C68003

The operation and configuration modes are described in

Operation Modes on page 4 and Configuration Mode on page 14

respectively. The ULPI Low power mode and Sleep mode are

described in the following sections:

Sleep Mode

Sleep mode is entered by asserting RESET_N during the Normal

Operation Mode. When RESET_N is driven low for tSTATE (see

Table 21 on page 19 for tSTATE requirement) while CS_N is low,

TX2UL enters into Sleep Mode. VCC must remain supplied (ON)

during the sleep mode. This mode powers down all internal

circuitry except the RESET_N pin and the chip_config register.

The ULPI interface bus is tri-stated.

ULPI Low Power Mode

In this mode, the link optionally places the TX2UL in low power

mode when the USB is suspended. TX2UL powers down all the

circuitry except for the interface pins and full speed receiver. To

enter low power mode, the link must set SuspendM in the

Function Control register to 0b. The TX2UL clock is stopped for

a minimum of five cycles after TX2UL accepts the register write.

To exit the low power mode, the link signals TX2UL to exit the

mode by asynchronously asserting a signal, STP. The TX2UL

wakes up its internal circuitry and when it meets the ULPI timing

requirements it deasserts DIR. The SuspendM register is set to

1b.

During the Sleep Mode ensure that:

■ TheULPIinterfaceIOsiseitherfloatingordrivenhighbythelink

■ DP and DM are either floating or pull to 0V

■ Deassert RESET_N to exit the Sleep Mode.

VID and PID

The VID and PID are hard coded into Product ID and Vendor ID registers (read only) as shown in T a ble 6.

Table 6. Immediate Register Values for VID and PID

Address (6 bits)

Field Name

Size (bit)

Value

00h

01h

02h

03h

Set

Clr

Vendor ID (VID) Low

B4h

04h

03h

68h

Vendor ID (VID) High

Product ID (PID) Low

Product ID (PID) High

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Revised April 1, 2009

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