Cypress Computer Hardware CY62147EV30 User Manual

CY62147EV30 MoBL®  
4-Mbit (256K x 16) Static RAM  
ideal for providing More Battery Life™ (MoBL®) in portable appli-  
cations such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption when addresses are not toggling. Placing the  
device into standby mode reduces power consumption by more  
than 99% when deselected (CE HIGH or both BLE and BHE are  
HIGH). The input and output pins (IO0 through IO15) are placed  
in a high impedance state when:  
Features  
Very high speed: 45 ns  
Temperature ranges  
Industrial: –40°C to +85°C  
Automotive-A: –40°C to +85°C  
Automotive-E: –40°C to +125°C  
Wide voltage range: 2.20V to 3.60V  
Pin compatible with CY62147DV30  
Ultra low standby power  
Deselected (CE HIGH)  
Outputs are disabled (OE HIGH)  
Both Byte High Enable and Byte Low Enable are disabled  
(BHE, BLE HIGH)  
Typical standby current: 1 μA  
Maximum standby current: 7 μA (Industrial)  
Write operation is active (CE LOW and WE LOW)  
Ultra low active power  
Typical active current: 2 mA at f = 1 MHz  
Easy memory expansion with CE [1] and OE features  
Automatic power down when deselected  
CMOS for optimum speed and power  
To write to the device, take Chip Enable (CE) and Write Enable  
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data  
from IO pins (IO0 through IO7) is written into the location  
specified on the address pins (A0 through A17). If Byte High  
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15  
)
is written into the location specified on the address pins (A0  
through A17).  
AvailableinPb-free48-ballVFBGA(single/dualCEoption)and  
44-pin TSOPII packages  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If  
Byte Low Enable (BLE) is LOW, then data from the memory  
location specified by the address pins appear on IO0 to IO7. If  
Byte High Enable (BHE) is LOW, then data from memory  
appears on IO8 to IO15. See the Truth Table on page 9 for a  
complete description of read and write modes.  
Byte power down feature  
Functional Description  
The CY62147EV30 is a high performance CMOS static RAM  
organized as 256K words by 16 bits. This device features  
advanced circuit design to provide ultra low active current. It is  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
Logic Block Diagram  
DATA IN DRIVERS  
A
10  
9
A
A
8
A
7
6
5
4
3
A
A
A
256K x 16  
IO –IO  
0
7
RAM Array  
A
IO –IO  
8
15  
A
2
1
0
A
A
COLUMN DECODER  
BHE  
WE  
CE  
POWER DOWN  
CIRCUIT  
BHE  
BLE  
[1]  
CE  
OE  
BLE  
Note  
1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE and  
1
CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH.  
2
1
2
Cypress Semiconductor Corporation  
Document #: 38-05440 Rev. *G  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 31, 2009  
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CY62147EV30 MoBL®  
DC Input Voltage [5, 6]............ –0.3V to 3.9V (VCCmax + 0.3V)  
Output Current into Outputs (LOW) ............................ 20 mA  
Maximum Ratings  
Exceeding the maximum ratings may impair the useful life of the  
device. User guidelines are not tested.  
Static Discharge Voltage .......................................... >2001V  
(MIL-STD-883, Method 3015)  
Storage Temperature ................................ –65°C to + 150°C  
Latch Up Current .....................................................>200 mA  
Ambient Temperature with  
Power Applied .......................................... –55°C to + 125°C  
Operating Range  
Supply Voltage to Ground  
Potential .............................0.3V to + 3.9V (VCCmax + 0.3V)  
Ambient  
[7]  
Device  
Range  
VCC  
Temperature  
DC Voltage Applied to Outputs  
CY62147EV30LL Ind’l/Auto-A –40°C to +85°C  
2.2V to  
3.6V  
in High-Z State [5, 6] ...............0.3V to 3.9V (VCCmax + 0.3V)  
Auto-E  
–40°C to +125°C  
Electrical Characteristics  
Over the Operating Range  
45 ns (Ind’l/Auto-A)  
55 ns (Auto-E)  
Parameter  
Description  
Test Conditions  
IOH = –0.1 mA  
Unit  
Min  
2.0  
2.4  
Typ [2]  
Max  
Min  
Typ [2]  
Max  
VOH  
Output HIGH  
Voltage  
2.0  
2.4  
V
V
IOH = –1.0 mA, VCC > 2.70V  
IOL = 0.1 mA  
VOL  
VIH  
VIL  
Output LOW  
Voltage  
0.4  
0.4  
0.4  
0.4  
V
I
OL = 2.1 mA, VCC = 2.70V  
VCC = 2.2V to 2.7V  
CC= 2.7V to 3.6V  
V
Input HIGH  
Voltage  
1.8  
2.2  
VCC + 0.3 1.8  
VCC + 0.3 2.2  
VCC + 0.3  
VCC + 0.3  
0.6  
V
V
V
Input LOW  
Voltage  
VCC = 2.2V to 2.7V  
VCC= 2.7V to 3.6V  
GND < VI < VCC  
–0.3  
–0.3  
–1  
0.6  
0.8  
+1  
–0.3  
–0.3  
–4  
V
0.8  
V
IIX  
Input Leakage  
Current  
+4  
μA  
IOZ  
ICC  
Output Leakage GND < VO < VCC, Output Disabled  
Current  
–1  
+1  
–4  
+4  
μA  
VCC Operating  
Supply Current  
f = fmax = 1/tRC VCC = VCC(max)  
15  
2
20  
15  
2
25  
3
mA  
IOUT = 0 mA  
f = 1 MHz  
2.5  
CMOS levels  
ISB1  
Automatic CE  
Power Down  
Current —  
CE > VCC – 0.2V  
1
7
1
20  
μA  
μA  
VIN > VCC – 0.2V, VIN < 0.2V  
f = fmax (Address and Data Only),  
f = 0 (OE, BHE, BLE and WE),  
VCC = 3.60V  
CMOS Inputs  
[8]  
ISB2  
Automatic CE  
Power Down  
Current —  
1
7
1
20  
CE > VCC – 0.2V  
V
IN > VCC – 0.2V or VIN < 0.2V,  
f = 0, VCC = 3.60V  
CMOS Inputs  
Capacitance  
For all packages.[9]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
TA = 25°C, f = 1 MHz,  
CC = VCC(typ)  
Max  
Unit  
CIN  
10  
10  
pF  
pF  
V
COUT  
Notes  
5.  
6.  
V
= –2.0V for pulse durations less than 20 ns.  
IL(min)  
V
= V + 0.75V for pulse durations less than 20 ns.  
IH(max)  
CC  
7. Full device AC operation assumes a minimum of 100 μs ramp time from 0 to V (min) and 200 μs wait time after V stabilization.  
CC  
CC  
8. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I  
/ I  
spec. Other inputs can be left floating.  
SB2 CCDR  
9. Tested initially and after any design or process changes that may affect these parameters.  
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CY62147EV30 MoBL®  
Thermal Resistance[9]  
VFBGA  
Package  
TSOP II  
Package  
Parameter  
Description  
Test Conditions  
Unit  
ΘJA  
Thermal Resistance  
(Junction to Ambient)  
Still Air, soldered on a 3 × 4.5 inch, two-layer  
printed circuit board  
75  
77  
13  
°C/W  
ΘJC  
Thermal Resistance  
(Junction to Case)  
10  
°C/W  
Figure 4. AC Test Load and Waveforms  
R1  
ALL INPUT PULSES  
VCC  
OUTPUT  
VCC  
90%  
90%  
10%  
10%  
GND  
Rise Time = 1 V/ns  
R2  
30 pF  
Fall Time = 1 V/ns  
INCLUDING  
JIG AND  
SCOPE  
Equivalent to: THEVENIN EQUIVALENT  
RTH  
OUTPUT  
V
Parameters  
2.50V  
16667  
15385  
8000  
3.0V  
1103  
1554  
645  
Unit  
Ω
R1  
R2  
Ω
RTH  
VTH  
Ω
1.20  
1.75  
V
Data Retention Characteristics  
Over the Operating Range  
Parameter  
Description  
VCC for Data Retention  
Data Retention Current  
Conditions  
Min Typ [2] Max Unit  
VDR  
1.5  
V
[8]  
ICCDR  
VCC= 1.5V, CE > VCC – 0.2V,  
IN > VCC – 0.2V or VIN < 0.2V  
Ind’l/Auto-A  
Auto-E  
0.8  
7
μA  
V
12  
[9]  
tCDR  
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
ns  
ns  
[10]  
tR  
tRC  
Figure 5. Data Retention Waveform[ , 11]  
DATA RETENTION MODE  
VCC(min)  
VCC(min)  
V
DR  
> 1.5V  
VCC  
t
t
R
CDR  
CE or  
BHE.BLE  
Notes  
10. Full device operation requires linear V ramp from V to V  
11. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.  
> 100 μs or stable at V > 100 μs.  
CC(min)  
CC  
DR  
CC(min)  
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CY62147EV30 MoBL®  
Switching Characteristics  
Over the Operating Range [12, 13]  
45 ns (Ind’l/Auto-A)  
55 ns (Auto-E)  
Unit  
Parameter  
Description  
Min  
Max  
Min  
Max  
Read Cycle  
tRC  
Read Cycle Time  
45  
55  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
45  
55  
tOHA  
tACE  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tPU  
Data Hold from Address Change  
CE LOW to Data Valid  
10  
10  
45  
22  
55  
25  
OE LOW to Data Valid  
OE LOW to LOW Z[14]  
5
10  
0
5
10  
0
OE HIGH to High Z[14, 15]  
CE LOW to Low Z[14]  
18  
18  
20  
20  
CE HIGH to High Z[14, 15]  
CE LOW to Power Up  
tPD  
CE HIGH to Power Down  
BLE/BHE LOW to Data Valid  
BLE/BHE LOW to Low Z[14]  
BLE/BHE HIGH to HIGH Z[14, 15]  
45  
45  
55  
55  
tDBE  
tLZBE  
tHZBE  
Write Cycle[16]  
tWC  
10  
10  
18  
20  
Write Cycle Time  
45  
35  
35  
0
55  
40  
40  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSCE  
tAW  
CE LOW to Write End  
Address Setup to Write End  
Address Hold from Write End  
Address Setup to Write Start  
WE Pulse Width  
tHA  
tSA  
0
0
tPWE  
tBW  
35  
35  
25  
0
40  
40  
25  
0
BLE/BHE LOW to Write End  
Data Setup to Write End  
Data Hold from Write End  
WE LOW to High-Z[14, 15]  
WE HIGH to Low-Z[14]  
tSD  
tHD  
tHZWE  
tLZWE  
18  
20  
10  
10  
Notes  
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V  
/2, input pulse  
CC(typ)  
levels of 0 to V  
, and output loading of the specified I /I as shown in the AC Test Load and Waveforms on page 4.  
CC(typ)  
OL OH  
13. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.  
14. At any temperature and voltage condition, t is less than t , t is less than t , t is less than t , and t is less than t for any device.  
HZCE  
LZCE HZBE  
LZBE HZOE  
LZOE  
HZWE  
LZWE  
15. t  
, t  
, t  
, and t  
transitions are measured when the outputs enter a high impedance state.  
HZOE HZCE HZBE  
HZWE  
16. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE, or both = V . All signals must be active to initiate a write and any of these  
IL  
IL  
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.  
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CY62147EV30 MoBL®  
Switching Waveforms  
Figure 6. Read Cycle No. 1 (Address Transition Controlled)[17, 18]  
tRC  
ADDRESS  
tAA  
tOHA  
PREVIOUS DATA VALID  
DATA VALID  
DATA OUT  
Figure 7. Read Cycle No. 2 (OE Controlled)[1, 18, 19]  
ADDRESS  
CE  
t
RC  
t
PD  
HZCE  
t
t
ACE  
OE  
t
HZOE  
t
DOE  
t
LZOE  
BHE/BLE  
t
HZBE  
t
DBE  
t
LZBE  
HIGH  
IMPEDANCE  
HIGHIMPEDANCE  
DATA VALID  
DATA OUT  
t
LZCE  
t
PU  
V
50%  
50%  
CC  
I
SUPPLY  
SB  
CURRENT  
Notes  
17. The device is continuously selected. OE, CE = V , BHE, BLE, or both = V  
.
IL  
IL  
18. WE is HIGH for read cycle.  
19. Address valid before or similar to CE and BHE, BLE transition LOW.  
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CY62147EV30 MoBL®  
Switching Waveforms (continued)  
Figure 8. Write Cycle No. 1 (WE Controlled)[1, 16, 20, 21]  
t
WC  
ADDRESS  
CE  
tSCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
BW  
BHE/BLE  
OE  
t
HD  
t
SD  
NOTE 22  
DATAIN  
DATA IO  
t
HZOE  
Figure 9. Write Cycle No. 2 (CE Controlled)[1, 16, 20, 21]  
t
WC  
ADDRESS  
CE  
t
SCE  
tSA  
t
t
HA  
AW  
tPWE  
WE  
t
BW  
BHE/BLE  
OE  
t
t
SD  
HD  
DATAIN  
DATA IO  
t
HZOE  
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CY62147EV30 MoBL®  
Switching Waveforms (continued)  
Figure 10. Write Cycle No. 3 (WE Controlled, OE LOW)[1, 21]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
BW  
BHE/BLE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
HD  
t
SD  
DATA IO  
DATAIN  
t
LZWE  
t
HZWE  
Figure 11. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[1, 21]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
tBW  
BHE/BLE  
WE  
t
SA  
tPWE  
tHZWE  
t
HD  
t
SD  
DATAIN  
DATA IO  
tLZWE  
Notes  
20. Data I/O is high impedance if OE = V  
.
IH  
21. If CE goes HIGH simultaneously with WE = V , the output remains in a high impedance state.  
IH  
22. During this period, the IOs are in output state. Do not apply input signals.  
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CY62147EV30 MoBL®  
Truth Table  
CE[ ]  
WE  
X
OE  
X
BHE  
X
BLE  
X
IOs  
Mode  
Deselect/Power Down  
Deselect/Power Down  
Read  
Power  
H
L
L
L
High Z  
High Z  
Standby (ISB  
Standby (ISB  
)
)
X
X
H
H
H
L
L
L
Data Out (IO0–IO15  
)
Active (ICC  
Active (ICC  
)
)
H
L
H
L
Data Out (IO0–IO7);  
IO8–IO15 in High Z  
Read  
L
H
L
L
H
Data Out (IO8–IO15);  
IO0–IO7 in High Z  
Read  
Active (ICC  
)
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z  
High Z  
High Z  
Output Disabled  
Output Disabled  
Output Disabled  
Write  
Active (ICC  
Active (ICC  
Active (ICC  
Active (ICC  
Active (ICC  
)
)
)
)
)
L
Data In (IO0–IO15)  
L
H
Data In (IO0–IO7);  
IO8–IO15 in High Z  
Write  
L
L
X
L
H
Data In (IO8–IO15);  
IO0–IO7 in High Z  
Write  
Active (ICC  
)
Ordering Information  
Speed  
Package  
Diagram  
Operating  
Range  
Ordering Code  
(ns)  
Package Type  
45  
CY62147EV30LL-45BVI  
CY62147EV30LL-45BVXI  
CY62147EV30LL-45B2XI  
CY62147EV30LL-45ZSXI  
CY62147EV30LL-45BVXA  
CY62147EV30LL-45ZSXA  
CY62147EV30LL-55ZSXE  
51-85150 48-Ball Very Fine Pitch Ball Grid Array [23]  
Industrial  
51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-Free) [23]  
51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-Free) [24]  
51-85087 44-Pin Thin Small Outline Package II (Pb-Free)  
51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-Free) [23]  
51-85087 44-Pin Thin Small Outline Package II (Pb-Free)  
51-85087 44-Pin Thin Small Outline Package II (Pb-Free)  
Automotive-A  
Automotive-E  
55  
Contact your local Cypress sales representative for availability of these parts.  
Notes  
23. This BGA package is offered with single chip enable.  
24. This BGA package is offered with dual chip enable.  
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CY62147EV30 MoBL®  
Package Diagrams  
Figure 12. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150  
BOTTOM VIEW  
A1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
Ø0.30 0.05(48X)  
A1 CORNER  
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875  
A
A
0.75  
B
6.00 0.10  
3.75  
B
6.00 0.10  
0.15(4X)  
SEATING PLANE  
C
51-85150-*D  
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CY62147EV30 MoBL®  
Package Diagrams (continued)  
Figure 13. 44-Pin TSOP II, 51-85087  
51-85087-*A  
Document #: 38-05440 Rev. *G  
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CY62147EV30 MoBL®  
Document History Page  
Document Title: CY62147EV30 MoBL® 4-Mbit (256K x 16) Static RAM  
Document Number: 38-05440  
Orig. of  
Change  
Submission  
Date  
Rev.  
ECN No.  
Description of Change  
**  
201861  
247009  
AJU  
SYT  
01/13/04  
See ECN  
New Data Sheet  
*A  
Changed from Advanced Information to Preliminary  
Moved Product Portfolio to Page 2  
Changed Vcc stabilization time in footnote #8 from 100 μs to 200 μs  
Removed Footnote #15(tLZBE) from Previous Revision  
Changed ICCDR from 2.0 μA to 2.5 μA  
Changed typo in Data Retention Characteristics(tR) from 100 μs to tRC ns  
Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin  
Changed tHZOE, tHZBE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to  
18 ns for 45 ns Speed Bin  
Changed tSCE and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns  
for 45 ns Speed Bin  
Changed tHZCE from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns  
Speed Bin  
Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for  
45 ns Speed Bin  
Changed tDOE from 15 to 18 ns for 35 ns Speed Bin  
Changed Ordering Information to include Pb-Free Packages  
*B  
414807  
ZSD  
See ECN  
Changed from Preliminary information to Final  
Changed the address of Cypress Semiconductor Corporation on Page #1 from  
“3901 North First Street” to “198 Champion Court”  
Removed 35ns Speed Bin  
Removed “L” version of CY62147EV30  
Changed ball E3 from DNU to NC.  
Removed redundant foot note on DNU.  
Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from  
1.5 mA to 2 mA at f=1 MHz  
Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax  
Changed ISB1 and ISB2 Typ values from 0.7 μA to 1 μA and Max values from  
2.5 μA to 7 μA.  
Changed ICCDR from 2.5 μA to 7 μA.  
Added ICCDR typical value.  
Changed AC test load capacitance from 50 pF to 30 pF on Page #4.  
Changed tLZOE from 3 ns to 5 ns  
Changed tLZCE, tLZBE and tLZWE from 6 ns to 10 ns  
Changed tHZCE from 22 ns to 18 ns  
Changed tPWE from 30 ns to 35 ns.  
Changed tSD from 22 ns to 25 ns.  
Updated the package diagram 48-pin VFBGA from *B to *D  
Updated the ordering information tableandreplacedthePackageNamecolumn  
with Package Diagram.  
*C  
*D  
464503  
925501  
NXR  
VKN  
See ECN  
See ECN  
Included Automotive Range in product offering  
Updated the Ordering Information  
Added Preliminary Automotive-A information  
Added footnote #9 related to ISB2 and ICCDR  
Added footnote #14 related AC timing parameters  
*E  
*F  
*G  
1045701  
VKN  
See ECN  
10/03/08  
04/01/09  
Converted Automotive-A and Automotive -E specs from preliminary to final  
Added -45B2XI part (Dual CE option)  
2577505 VKN/PYRS  
2681901 VKN/PYRS  
Added CY62147EV30LL-45ZSXA in the ordering information table  
Document #: 38-05440 Rev. *G  
Page 12 of 13  
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CY62147EV30 MoBL®  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document #: 38-05440 Rev. *G  
Revised March 31, 2009  
Page 13 of 13  
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the  
trademarks of their respective holders.  
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