Cypress Computer Hardware CY62128EV30 User Manual

CY62128EV30  
MoBL® 1 Mbit (128K x 8) Static RAM  
Features  
Functional Description  
Very high speed: 45 ns  
The CY62128EV30 is a high performance CMOS static RAM  
module organized as 128K words by 8 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life™ (MoBL ) in portable  
applications such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption when addresses are not toggling. Placing the  
device into standby mode reduces power consumption by more  
Temperature ranges:  
• Industrial: –40°C to +85°C  
• Automotive-A: –40°C to +85°C  
• Automotive-E: –40°C to +125°C  
®
Wide voltage range: 2.20V – 3.60V  
Pin compatible with CY62128DV30  
than 99% when deselected (CE HIGH or CE LOW). The eight  
1
2
input and output pins (IO through IO ) are placed in a high  
0
7
Ultra low standby power  
Typical standby current: 1 μA  
Maximum standby current: 4 μA  
impedance state when the device is deselected (CE HIGH or  
1
CE LOW), the outputs are disabled (OE HIGH), or a write  
2
operation is in progress (CE LOW and CE HIGH and WE  
1
2
LOW).  
Ultra low active power  
To write to the device, take Chip Enable (CE LOW and CE  
Typical active current: 1.3 mA @ f = 1 MHz  
1
2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight IO  
pins is then written into the location specified on the Address pin  
(A through A ).  
Easy memory expansion with CE , CE and OE features  
1
2
Automatic power down when deselected  
CMOS for optimum speed and power  
0
16  
To read from the device, take Chip Enable (CE LOW and CE  
1
2
HIGH) and Output Enable (OE) LOW while forcing Write Enable  
(WE) HIGH. Under these conditions, the contents of the memory  
location specified by the address pins appear on the IO pins.  
Offered in Pb-free 32-pin SOIC, 32-pin TSOP I, and 32-pin  
STSOP packages  
Logic Block Diagram  
IO  
0
INPUT BUFFER  
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
IO  
1
IO  
2
128K x 8  
ARRAY  
IO  
3
IO  
IO  
IO  
IO  
4
5
6
7
A
A
A
9
10  
11  
CE  
CE  
1
2
POWER  
DOWN  
COLUMN DECODER  
WE  
OE  
Note  
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05579 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 28, 2008  
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CY62128EV30  
Output Current into Outputs (LOW)............................. 20 mA  
Maximum Ratings  
Static Discharge Voltage.......................................... > 2001V  
(MIL-STD-883, Method 3015)  
Exceeding maximum ratings may impair the useful life of the  
device. These user guidelines are not tested.  
Latch up Current.....................................................> 200 mA  
Storage Temperature.................................. –65°C to +150°C  
Ambient Temperature with  
Power Applied ............................................ –55°C to +125°C  
Operating Range  
Ambient  
Device  
Range  
V
CC  
Supply Voltage to Ground  
Potential..........................................–0.3V to V  
Temperature  
+ 0.3V  
CC(max)  
CY62128EV30LL Ind’l/Auto-A  
Auto-E  
–40°C to +85°C 2.2V to  
DC Voltage Applied to Outputs  
3.6V  
–40°C to +125°C  
in High-Z State  
.........................–0.3V to V  
+ 0.3V  
+ 0.3V  
CC(max)  
.......................–0.3V to V  
CC(max)  
DC Input Voltage  
Electrical Characteristics  
(Over the Operating Range)  
45 ns (Ind’l/Auto-A)  
55 ns (Auto-E)  
Parameter  
Description  
Test Conditions  
= –0.1 mA  
Unit  
Min Typ  
2.0  
Max  
Min Typ  
2.0  
Max  
V
Output HIGH Voltage  
I
I
V
V
OH  
OH  
= –1.0 mA, V > 2.70V  
2.4  
2.4  
OH  
CC  
V
V
Output LOW Voltage  
Input HIGH Voltage  
I
I
= 0.1 mA  
0.4  
0.4  
0.4  
0.4  
V
V
V
OL  
OL  
OL  
= 2.1 mA, V > 2.70V  
CC  
V
= 2.2V to 2.7V  
1.8  
2.2  
V
+
1.8  
2.2  
V
+
IH  
CC  
CC  
CC  
0.3V  
0.3V  
V
= 2.7V to 3.6V  
V
+
V
+
V
CC  
CC  
CC  
0.3V  
0.3V  
V
I
Input LOW Voltage  
V
V
= 2.2V to 2.7V  
= 2.7V to 3.6V  
–0.3  
–0.3  
–1  
0.6  
0.8  
+1  
–0.3  
–0.3  
–4  
0.6  
0.8  
+4  
V
IL  
CC  
V
CC  
Input Leakage Current  
GND < V < V  
CC  
μA  
μA  
mA  
mA  
IX  
I
I
I
Output Leakage Current GND < V < V , Output Disabled  
–1  
+1  
–4  
+4  
OZ  
O
CC  
V
Operating Supply  
f = f  
= 1/t  
V
= V  
CCmax  
= 0 mA  
11  
16  
11  
35  
CC  
CC  
max  
RC  
CC  
Current  
I
OUT  
f = 1 MHz  
1.3  
2.0  
1.3  
4.0  
CMOS levels  
I
Automatic CE  
Power down  
CE > V 0.2V, CE < 0.2V  
1
4
1
35  
μA  
SB1  
1
CC  
2
V
> V –0.2V, V < 0.2V)  
IN  
CC IN  
Current — CMOS Inputs f = f  
(Address and Data Only),  
max  
f = 0 (OE and WE), V = 3.60V  
CC  
I
Automatic CE  
Power down  
CE > V – 0.2V, CE < 0.2V  
1
4
1
30  
μA  
SB2  
1
CC  
2
V
> V – 0.2V or V < 0.2V,  
IN  
CC IN  
Current — CMOS Inputs f = 0, V = 3.60V  
CC  
Notes  
4.  
5.  
V
V
= –2.0V for pulse durations less than 20 ns.  
IL(min)  
= V +0.75V for pulse durations less than 20 ns.  
IH(max)  
CC  
6. Full device AC operation assumes a 100 μs ramp time from 0 to V (min) and 200 μs wait time after V stabilization.  
CC  
CC  
7. Only chip enables (CE and CE ) must be at CMOS level to meet the I / I spec. Other inputs can be left floating.  
1
2
SB2 CCDR  
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CY62128EV30  
Capacitance  
(For all packages)  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max  
10  
Unit  
pF  
C
C
IN  
A
V
= V  
CC  
CC(typ)  
10  
pF  
OUT  
Thermal Resistance  
Parameter  
Description  
Test Conditions  
TSOP I  
SOIC  
STSOP  
Unit  
Θ
Thermal Resistance  
(Junction to Ambient)  
Still Air, soldered on a 3 x 4.5 inch,  
two-layer printed circuit board  
33.01  
48.67  
32.56  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
3.42  
25.86  
3.59  
°C/W  
JC  
Figure 1. AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
V
CC  
V
OUTPUT  
CC  
90%  
10%  
90%  
10%  
R2  
GND  
Rise Time = 1 V/ns  
30 pF  
Fall Time = 1 V/ns  
INCLUDING  
JIG AND  
SCOPE  
Equivalent to:  
THEVENIN EQUIVALENT  
R
TH  
OUTPUT  
V
Parameters  
2.50V  
16667  
15385  
8000  
3.0V  
1103  
1554  
645  
Unit  
Ω
R1  
R2  
Ω
R
Ω
TH  
TH  
V
1.20  
1.75  
V
Data Retention Characteristics  
(Over the Operating Range)  
Parameter  
Description  
Conditions  
Min  
Typ  
Max Unit  
V
V
for Data Retention  
1.5  
V
DR  
CC  
[7]  
I
Data Retention Current  
V
= 1.5V,  
CC  
Ind’l/Auto-A  
Auto-E  
3
μA  
μA  
CCDR  
CE > V 0.2V or CE < 0.2V,  
V
1
CC  
2
30  
> V 0.2V or V < 0.2V  
IN  
CC IN  
t
t
Chip Deselect to Data Retention  
Time  
0
ns  
ns  
CDR  
R
Operation Recovery Time  
t
RC  
Note  
8. Tested initially and after any design or process changes that may affect these parameters.  
9. Full device AC operation requires linear V ramp from V to V > 100 μs or stable at V > 100 μs.  
CC(min)  
CC  
DR  
CC(min)  
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CY62128EV30  
Data Retention Waveform [10]  
DATA RETENTION MODE  
> 1.5V  
V
V
CC(min)  
V
CC(min)  
VCC  
DR  
t
t
R
CDR  
CE  
Switching Characteristics  
(Over the Operating Range)  
45 ns (Ind’l/Auto-A)  
55 ns (Auto-E)  
Min Max  
Parameter  
Read Cycle  
Description  
Unit  
Min  
Max  
t
t
t
t
t
t
t
Read Cycle Time  
45  
55  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
45  
55  
AA  
Data Hold from Address Change  
CE LOW to Data Valid  
10  
OHA  
ACE  
DOE  
LZOE  
HZOE  
45  
22  
55  
25  
OE LOW to Data Valid  
OE LOW to Low Z  
5
10  
0
5
10  
0
[12,13]  
OE HIGH to High Z  
18  
18  
45  
20  
20  
55  
CE LOW to Low Z  
t
t
ns  
ns  
LZCE  
CE HIGH to High Z  
HZCE  
CE LOW to Power Up  
CE HIGH to Power Up  
t
t
ns  
ns  
PU  
PD  
Write Cycle  
t
t
t
t
t
Write Cycle Time  
45  
35  
35  
0
55  
40  
40  
0
ns  
ns  
ns  
ns  
ns  
WC  
SCE  
AW  
HA  
CE LOW to Write End  
Address Setup to Write End  
Address Hold from Write End  
Address Setup to Write Start  
WE Pulse Width  
0
0
SA  
t
t
t
t
t
35  
25  
0
40  
25  
0
ns  
ns  
ns  
ns  
ns  
PWE  
Data Setup to Write End  
Data Hold from Write End  
SD  
HD  
WE LOW to High Z  
18  
20  
HZWE  
LZWE  
WE HIGH to Low Z  
10  
10  
Notes  
10. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.  
1
2
1
2
1
2
11. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V  
/2, input  
CC(typ)  
pulse levels of 0 to V  
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” on page 4.  
CC(typ)  
OL OH  
12. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
for any given device.  
LZWE  
HZCE  
LZCE HZOE  
LZOE  
HZWE  
13. t  
, t  
, and t  
transitions are measured when the output enter a high impedance state.  
HZOE HZCE  
HZWE  
14. The internal write time of the memory is defined by the overlap of WE, CE = V . All signals must be ACTIVE to initiate a write and any of these signals can  
IL  
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.  
Document #: 38-05579 Rev. *D  
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CY62128EV30  
Switching Waveforms  
Figure 2. Read Cycle 1 (Address transition controlled)  
tRC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Figure 3. Read Cycle No. 2 (OE controlled)  
ADDRESS  
CE  
t
RC  
t
ACE  
OE  
t
HZOE  
t
DOE  
t
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
LZCE  
t
PD  
ICC  
t
V
CC  
PU  
50%  
SUPPLY  
CURRENT  
50%  
ISB  
Figure 4. Write Cycle No. 1 (WE controlled)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
OE  
t
t
SD  
HD  
DATA IO  
NOTE  
DATA VALID  
t
HZOE  
Notes  
15. The device is continuously selected. OE, CE = V , CE = V .  
IH  
1
IL  
2
16. WE is HIGH for read cycle.  
17. Address valid before or similar to CE transition LOW and CE transition HIGH.  
1
2
18. Data IO is high impedance if OE = V  
.
IH  
19. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high impedance state.  
1
2
20. During this period, the IOs are in output state. Do not apply input signals.  
Document #: 38-05579 Rev. *D  
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CY62128EV30  
Switching Waveforms (continued)  
Figure 5. Write Cycle No. 2 (CE1 or CE2 controlled)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
t
AW  
HA  
t
PWE  
WE  
t
t
HD  
SD  
DATA IO  
DATA VALID  
Figure 6. Write Cycle No. 3 (WE controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
NOTE  
DATA VALID  
DATA IO  
t
t
LZWE  
HZWE  
Table 2. Truth Table for CY62128EV30  
CE  
H
X
CE  
X
WE  
X
OE  
X
Inputs/Outputs  
Mode  
Power  
1
2
High Z  
High Z  
Deselect/Power Down  
Deselect/Power Down  
Read  
Standby (I  
Standby (I  
)
SB  
SB  
L
X
X
)
L
H
H
L
Data Out  
High Z  
Active (I  
Active (I  
Active (I  
)
)
)
CC  
CC  
CC  
L
H
H
H
X
Output Disabled  
Write  
L
H
L
Data in  
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CY62128EV30  
Ordering Information  
Speed  
(ns)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
45  
CY62128EV30LL-45SXI  
CY62128EV30LL-45ZXI  
51-85081 32-pin 450-Mil SOIC (Pb-free)  
51-85056 32-pin TSOP Type I (Pb-free)  
Industrial  
CY62128EV30LL-45ZAXI 51-85094 32-pin STSOP (Pb-free)  
45  
55  
CY62128EV30LL-45ZXA  
CY62128EV30LL-55ZXE  
51-85056 32-pin TSOP Type I (Pb-free)  
51-85056 32-pin TSOP Type I (Pb-free)  
Automotive-A  
Automotive-E  
Contact your local Cypress sales representative for availability of these parts.  
Package Diagrams  
Figure 7. 32-Pin (450 Mil) Molded SOIC, 51-85081  
16  
1
0.546[13.868]  
0.566[14.376]  
0.440[11.176]  
0.450[11.430]  
17  
32  
0.793[20.142]  
0.817[20.751]  
0.006[0.152]  
0.012[0.304]  
0.101[2.565]  
0.111[2.819]  
0.118[2.997]  
MAX.  
0.004[0.102]  
0.047[1.193]  
0.063[1.600]  
0.004[0.102]  
0.050[1.270]  
BSC.  
0.023[0.584]  
0.039[0.990]  
MIN.  
0.014[0.355]  
0.020[0.508]  
51-85081-*B  
SEATING PLANE  
Document #: 38-05579 Rev. *D  
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CY62128EV30  
Package Diagrams (continued)  
Figure 8. 32-Pin Thin Small Outline Package Type I (8 x 20 mm), 51-85056  
51-85056-*D  
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CY62128EV30  
Package Diagrams (continued)  
Figure 9. 32-Pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094  
51-85094-*D  
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CY62128EV30  
Document History Page  
Document Title: CY62128EV30 MoBL® 1 Mbit (128K x 8) Static RAM  
Document Number: 38-05579  
REV.  
ECN NO. Issue Date Orig. of  
Change  
Description of Change  
**  
285473  
461631  
See ECN  
See ECN  
PCI  
New Data Sheet  
*A  
NXR Converted from Preliminary to Final  
Removed 35 ns Speed Bin  
Removed “L” version of CY62128EV30  
Removed Reverse TSOP I package from Product offering.  
Changed I  
Changed I  
Changed I  
Changed I  
Changed I  
from 8 mA to 11 mA and I  
from 12 mA to 16 mA for f = f  
CC (Typ)  
CC (Max) max  
from 1.5 mA to 2.0 mA for f = 1 MHz  
from 1 μA to 4 μA  
CC (max)  
SB2 (max)  
SB2 (Typ)  
from 0.5 μA to 1 μA  
from 1 μA to 3 μA  
CCDR (max)  
Changed the AC Test load Capacitance value from 50 pF to 30 pF  
Changed t  
Changed t  
Changed t  
Changed t  
from 3 to 5 ns  
from 6 to 10 ns  
from 22 to 18 ns  
from 30 to 35 ns  
LZOE  
LZCE  
HZCE  
PWE  
Changed t from 22 to 25 ns  
SD  
Changed t  
from 6 to 10 ns  
LZWE  
Updated the Ordering Information table.  
*B  
*C  
464721  
See ECN  
NXR Updated the Block Diagram on page # 1  
1024520 See ECN  
VKN Added final Automotive-A and Automotive-E information  
Added footnote #9 related to I  
and I  
SB2  
CCDR  
Updated Ordering Information table  
*D  
2257446 See ECN  
NXR Changed the Maximum rating of Ambient Temperature with Power Applied from  
55°C to +125°C to –55°C to +125°C.  
© Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document #: 38-05579 Rev. *D  
Revised March 28, 2008  
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MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All other trademarks or registered trademarks referenced herein are property of the respective  
corporations. All products and company names mentioned in this document may be the trademarks of their respective holders.  
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