CY14B101L
1 Mbit (128K x 8) nvSRAM
Features
Functional Description
■
■
■
25 ns, 35 ns, and 45 ns access times
Pin compatible with STK14CA8
The Cypress CY14B101L is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
Hands off automatic STORE on power down with only a small
capacitor
■
STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power down
■
■
■
■
■
■
■
■
RECALL to SRAM initiated by software or power up
Unlimited READ, WRITE, and RECALL cycles
200,000 STORE cycles to QuantumTrap
20 year data retention at 55°C
Single 3V +20%, –10% operation
Commercial and industrial temperature
32-pin (300 mil) SOIC and 48-pin (300 mil) SSOP packages
RoHS compliance
Logic Block Diagram
V
CC
V
CAP
QuantumTrap
1024 x 1024
A5
POWER
STORE
RECALL
CONTROL
A6
A7
A8
STORE/
RECALL
CONTROL
STATIC RAM
ARRAY
1024 X 1024
A9
HSB
A12
A13
A14
A15
A16
SOFTWARE
DETECT
A15
-
A0
DQ0
COLUMN IO
DQ1
DQ2
DQ3
COLUMN DEC
DQ4
DQ5
DQ6
DQ7
A0
A4
A11
A10
A1
A3
A2
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-06400 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 30, 2009
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CY14B101L
Figure 2 shows the proper connection of the storage capacitor
A pull up is placed on WE to hold it inactive during power up.
Device Operation
The CY14B101L nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM READ and WRITE operations are inhibited.
The CY14B101L supports unlimited reads and writes similar to
a typical SRAM. In addition, it provides unlimited RECALL opera-
tions from the nonvolatile cells and up to one million STORE
operations.
Figure 2. AutoStore Mode
VCC
VCC
VCAP
WE
SRAM Read
The CY14B101L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A0–16 determines the 131,072 data bytes accessed.
When the READ is initiated by an address transition, the outputs
are valid after a delay of tAA (READ cycle 1). If the READ is
initiated by CE or OE, the outputs are valid at tACE or at tDOE
,
whichever is later (READ cycle 2). The data outputs repeatedly
respond to address changes within the tAA access time without
the need for transitions on any control input pins, and remains
valid until another address change or until CE or OE is brought
HIGH, or WE or HSB is brought LOW.
SRAM Write
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull-up resistor is shown connected to HSB.
The HSB signal is monitored by the system to detect if an
AutoStore cycle is in progress.
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the WRITE cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle.
The data on the common IO pins DQ0–7 are written into the
memory if it has valid tSD, before the end of a WE controlled
WRITE or before the end of an CE controlled WRITE. Keep OE
HIGH during the entire WRITE cycle to avoid data bus contention
on common IO lines. If OE is left LOW, internal circuitry turns off
the output buffers tHZWE after WE goes LOW.
Hardware STORE (HSB) Operation
The CY14B101L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B101L conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle only begins if a WRITE to
the SRAM takes place since the last STORE or RECALL cycle.
The HSB pin also acts as an open drain driver that is internally
driven LOW to indicate a busy condition, while the STORE
(initiated by any means) is in progress. This pin should be exter-
nally pulled up if it is used to drive other inputs.
AutoStore Operation
The CY14B101L stores data to nvSRAM using one of three
storage operations:
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B101L.
SRAM READ and WRITE operations, that are in progress when
HSB is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the CY14B101L continues SRAM operations for tDELAY. During
tDELAY, multiple SRAM READ operations take place. If a WRITE
is in progress when HSB is pulled LOW, it allows a time, tDELAY
to complete. However, any SRAM WRITE cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
If HSB is not used, it is left unconnected.
Document Number: 001-06400 Rev. *I
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CY14B101L
Hardware RECALL (Power Up)
Data Protection
During power up or after any low power condition (VCC
<
The CY14B101L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
VSWITCH), an internal RECALL request is latched. When VCC
once again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
when VCC is less than VSWITCH
.
If the CY14B101L is in a WRITE mode (both CE and WE are low)
at power up after a RECALL or after a STORE, the WRITE is
inhibited until a negative transition on CE or WE is detected. This
protects against inadvertent writes during power up or brown out
conditions.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B101L software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Noise Considerations
The CY14B101L is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and VSS, using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
Low Average Active Power
To initiate the software STORE cycle, the following READ
sequence is performed:
CMOS technology provides the CY14B101L the benefit of
drawing significantly less current when it is cycled at times longer
shown for both CMOS and TTL input levels (commercial temper-
ature range, VCC = 3.6V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the CY14B101L depends on the
following items:
1. Read address 0x4E38, Valid READ
2. Read address 0xB1C7, Valid READ
3. Read address 0x83E0, Valid READ
4. Read address 0x7C1F, Valid READ
5. Read address 0x703F, Valid READ
6. Read address 0x8FC0, Initiate STORE cycle
■
■
■
■
■
■
■
The duty cycle of chip enable
The overall cycle rate for accesses
The ratio of READs to WRITEs
CMOS versus TTL input levels
The operating temperature
The VCC level
The software sequence is clocked with CE controlled READs or
OE controlled READs. When the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. It is important that READ cycles and not WRITE cycles
are used in the sequence. It is not necessary that OE is LOW for
a valid sequence. After the tSTORE cycle time is fulfilled, the
SRAM is again activated for READ and WRITE operation.
Software RECALL
IO loading
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations is
performed:
Figure 3. Current Versus Cycle Time
1. Read address 0x4E38, Valid READ
2. Read address 0xB1C7, Valid READ
3. Read address 0x83E0, Valid READ
4. Read address 0x7C1F, Valid READ
5. Read address 0x703F, Valid READ
6. Read address 0x4C63, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the tRECALL cycle time, the SRAM is once
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
Document Number: 001-06400 Rev. *I
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CY14B101L
Preventing Store
Best Practices
Disable the AutoStore function by initiating an AutoStore Disable
sequence. A sequence of READ operations is performed in a
manner similar to the software STORE initiation. To initiate the
AutoStore Disable sequence, perform the following sequence of
CE controlled READ operations:
nvSRAM products have been used effectively for over 15 years.
While ease of use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sitessometimesreprogramthesevalues. FinalNVpatternsare
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on must always program a unique
NV pattern (for example, complex 4-byte pattern of 46 E6 49
53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8B45 AutoStore Disable
Re-enable the AutoStore by initiating an AutoStore Enable
sequence. A sequence of READ operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore Enable sequence, perform the following sequence of
CE controlled READ operations:
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a preset
state, the best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs, incoming inspection routines,
and so on).
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4B46 AutoStore Enable
■
■
If autostore is firmware disabled, it does not reset to “autostore
enabled”oneverypowerdowneventcapturedbythenvSRAM.
The application firmware should re-enable or re-disable
autostore on each reset sequence based on the behavior
desired.
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) is issued to save the
AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
TheVCAP valuespecifiedinthisdatasheetincludesaminimum
and a maximum value size. Best practice is to meet this
requirementandnotexceedthemaximumVCAP valuebecause
higher inrush currents may reduce the reliability of the internal
pass transistor. Customers that wantto use a larger VCAP value
to make sure there is extra store charge should discuss their
V
CAP size selection with Cypress to understand any impact on
the Vcap voltage level at the end of a tRECALL period.
Document Number: 001-06400 Rev. *I
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CY14B101L
.
Table 1. Hardware Mode Selection
A15 – A0
Mode
IO
Power
Standby
Active[3]
Active
CE
WE
OE
H
X
X
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
L
L
L
H
L
L
X
L
H
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
AutoStore Disable
L
L
L
H
H
H
L
L
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
AutoStore Enable
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active ICC2
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Nonvolatile Recall
Notes
1. The six consecutive address locations are in the order listed. WE is HIGH during all six cycles to enable a nonvolatile cycle.
2. While there are 17 address lines on the CY14B101L, only the lower 16 lines are used to control software modes.
3. IO state depends on the state of OE. The IO table shown is based on OE Low.
Document Number: 001-06400 Rev. *I
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CY14B101L
Package Power Dissipation
Capability (TA = 25°C) ................................................... 1.0W
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Surface Mount Lead Soldering
Temperature (3 Seconds).......................................... +260°C
Storage Temperature ................................. –65°C to +150°C
DC output Current (1 output at a time, 1s duration) .... 15 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Supply Voltage on VCC Relative to GND ..........–0.5V to 4.1V
Latch Up Current ................................................... > 200 mA
Voltage Applied to Outputs
in High Z State.......................................–0.5V to VCC + 0.5V
Operating Range
Input Voltage...........................................–0.5V to Vcc + 0.5V
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
Transient Voltage (<20 ns) on
Any Pin to Ground Potential ..................–2.0V to VCC + 2.0V
2.7V to 3.6V
2.7V to 3.6V
-40°C to +85°C
DC Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
ICC1
Average VCC Current tRC = 25 ns
Commercial
Industrial
65
55
50
mA
mA
tRC = 35 ns
tRC = 45 ns
Dependent on output loading and cycle rate.
Values obtained without output loads.
70
60
55
mA
mA
mA
IOUT = 0 mA.
ICC2
ICC3
Average VCC Current All Inputs Do Not Care, VCC = Max
during STORE Average current for duration tSTORE
6
mA
mA
Average VCC Current at WE > (VCC – 0.2V). All other inputs cycling.
RC= 200 ns, 5V, 25°C Dependent on output loading and cycle rate. Values obtained
Typical without output loads.
10
t
ICC4
ISB
Average VCAP Current All Inputs Do Not Care, VCC = Max
during AutoStore Cycle Average current for duration tSTORE
3
3
mA
mA
VCC Standby Current
CE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
IIX
Input Leakage Current VCC = Max, VSS < VIN < VCC
-1
-1
+1
+1
μA
μA
IOZ
Off State Output
Leakage Current
VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL
VIH
Input HIGH Voltage
2.0
VCC
0.5
+
V
VIL
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Storage Capacitor
VSS – 0.5
2.4
0.8
V
V
VOH
VOL
VCAP
IOUT = –2 mA
IOUT = 4 mA
0.4
V
Between VCAP pin and Vss, 6V rated.
17
120
uF
Notes
4. The HSB pin has I
= –10 μA for V of 2.4 V. This parameter is characterized but not tested.
OUT
OH
5.
V
changes by 100 mV when V > 3.5V.
IH CC
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CY14B101L
Data Retention and Endurance
Parameter
Description
Min
20
Unit
Years
K
DATAR
NVC
Data Retention at 55°C
Nonvolatile STORE Operations
200
Capacitance
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 0 to 3.0V
Max
7
Unit
pF
V
7
pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.[6]
Parameter
Description
Test Conditions
32-SOIC
48-SSOP
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA / JESD51.
33.64
32.9
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
13.6
16.35
°C/W
Figure 4. AC Test Loads
For Tri-state Specs
R1 577Ω
R1 577Ω
3.0V
3.0V
Output
Output
R2
R2
789
30 pF
5 pF
789Ω
Ω
AC Test Conditions
Input Pulse Levels....................................................0V to 3V
Input Rise and Fall Times (10% to 90%)...................... <5 ns
Input and Output Timing Reference Levels.................... 1.5V
Note
6. These parameters are guaranteed by design and are not tested.
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CY14B101L
AC Switching Characteristics
SRAM Read Cycle
Parameter
25 ns
35 ns
45 ns
Unit
Description
Cypress
Alt
Min
Max
Min
Max
Min
Max
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ACE
ELQV
t
25
35
45
RC
AA
AVAV, ELEH
[8]
Address Access Time
25
12
35
15
45
20
AVQV
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
DOE
OHA
GLQV
[8]
3
3
3
3
3
3
AXQX
[9]
[9]
[9]
[9]
LZCE
HZCE
LZOE
HZOE
ELQX
10
10
25
13
13
35
15
15
45
EHQZ
0
0
0
0
0
0
GLQX
GHQZ
[6]
PU
ELICCH
EHICCL
[6]
PD
Switching Waveforms
W5&
$''5(66
W$$
W2+$
'4ꢀꢁ'$7$ꢀ287ꢂ
'$7$ꢀ9$/,'
W5&
$''5(66
&(
W$&(
W3'
W+=&(
W/=&(
2(
W+=2(
W'2(
W/=2(
'4ꢀꢁ'$7$ꢀ287ꢂ
'$7$ꢀ9$/,'
$&7,9(
W38
67$1'%<
,&&
Notes
7. WE and HSB must be HIGH during SRAM READ cycles.
8. Device is continuously selected with CE and OE both Low.
9. Measured ±200 mV from steady state output voltage.
10. HSB must remain high during READ and WRITE cycles.
Document Number: 001-06400 Rev. *I
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CY14B101L
SRAM Write Cycle
Parameter
25 ns
35 ns
45 ns
Unit
Description
Write Cycle Time
Cypress
Parameter
Alt
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
25
20
20
10
0
35
25
25
12
0
45
30
30
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
AVAV
WLWH, WLEH
t
Write Pulse Width
PWE
SCE
SD
t
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
ELWH, ELEH
t
DVWH, DVEH
t
HD
WHDX, EHDX
t
20
0
25
0
30
0
AW
AVWH, AVEH
t
SA
AVWL, AVEL
t
0
0
0
HA
WHAX, EHAX
10
13
15
HZWE
LZWE
WLQZ
WHQX
3
3
3
Switching Waveforms
tWC
ADDRESS
CE
tHA
tSCE
tAW
tSA
tPWE
WE
tHD
tSD
DATA VALID
DATA IN
tHZWE
tLZWE
HIGH IMPEDANCE
PREVIOUS DATA
DATA OUT
tWC
ADDRESS
tHA
tSCE
tSA
CE
WE
tAW
tPWE
tSD
tHD
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
Notes
11. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
12.
CE or WE must be greater than V during address transitions.
IH
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CY14B101L
AutoStore or Power Up RECALL
CY14B101L
Parameter
Alt
Description
Unit
Min
Max
[13]
t
t
t
t
Power up RECALL Duration
STORE Cycle Duration
20
ms
ms
V
HRECALL
RESTORE
HLHZ
12.5
2.65
STORE
V
t
Low Voltage Trigger Level
SWITCH
V
Rise Time
150
μs
VCCRISE
CC
Switching Waveforms
Figure 9. AutoStore/Power Up RECALL
No STORE occurs
without atleast one
SRAM write
STORE occurs only
if a SRAM write
has happened
V
CC
V
SWITCH
tVCCRISE
AutoStore
tSTORE
tSTORE
POWER-UP RECALL
Read & Write Inhibited
tHRECALL
tHRECALL
Note Read and Write cycles are ignored during STORE, RECALL, and while Vcc is below V
SWITCH
Notes
13. t
starts from the time V rises above V .
SWITCH
HRECALL
CC
14. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place.
15. Industrial Grade devices requires 15 ms max.
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CY14B101L
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows.
25 ns
35 ns
45 ns
Unit
Parameter
Alt
Description
Min
Max
Min
Max
Min
Max
RC
t
t
t
t
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
Address Setup Time
25
0
35
0
45
0
ns
ns
ns
ns
AVAV
AVEL
ELEH
SA
Clock Pulse Width
20
1
25
1
30
1
CW
t
Address Hold Time
HA
GHAX, ELAX
RECALL Duration
120
120
120
μs
RECALL
Switching Waveforms
tRC
tRC
ADDRESS # 1
ADDRESS # 6
ADDRESS
CE
tSA
tSCE
tHA
OE
t
STORE / tRECALL
HIGH IMPEDANCE
DATA VALID
DATA VALID
DQ (DATA)
tRC
tRC
ADDRESS # 1
ADDRESS # 6
ADDRESS
CE
OE
tSA
tSCE
t
tHA
STORE / tRECALL
HIGH IMPEDANCE
DATA VALID
DQ (DATA)
DATA VALID
Notes
16. The software sequence is clocked on the falling edge of CE controlled READs or OE controlled READs.
17. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
Document Number: 001-06400 Rev. *I
Page 12 of 18
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CY14B101L
Hardware STORE Cycle
CY14B101L
Parameter
Alt
Description
Hardware STORE Pulse Width
Unit
Min
15
1
Max
t
t
t
t
t
ns
PHSB
HLHX
t
Time Allowed to Complete SRAM Cycle
Soft Sequence Processing Time
70
70
μs
DELAY
HLQZ , BLQZ
us
ss
Switching Waveforms
Figure 12. Hardware STORE Cycle
3+6%
W66
W66
6RIWꢀ6HTXHQFH
&RPPDQG
6RIWꢀ6HTXHQFH
&RPPDQG
$GGUHVV
$GGUHVVꢀꢃꢄ
W6$
$GGUHVVꢀꢃꢅ
W&:
$GGUHVVꢀꢃꢄ
$GGUHVVꢀꢃꢅ
W&:
&(
9&&
Notes
18. On a hardware STORE initiation, SRAM operation continues to be enabled for time t
to allow read and write cycles to complete.
DELAY
19. This is the amount of time to take action on a soft sequence command. Vcc power must remain high to effectively register command.
20. Commands such as Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
Document Number: 001-06400 Rev. *I
Page 13 of 18
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CY14B101L
Part Numbering Nomenclature
CY 14 B 101 L - SZ 25 X C T
Option
T - Tape and Reel
Blank - Std.
Temperature
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Pb-Free
Speed
25 - 25 ns
35 - 35 ns
45 - 45 ns
Package
SZ - 32 SOIC
SP - 48 SSOP
Data Bus
L - x8
Density
101 - 1 Mb
Voltage
B - 3.0V
NVSRAM
14 - AutoStore + Software Store + Hardware Store
Cypress
Ordering Information
Speed
Operating
Range
Ordering Code
Package Diagram
Package Type
32-pin SOIC
(ns)
25
CY14B101L-SZ25XCT
CY14B101L-SZ25XC
CY14B101L-SP25XCT
CY14B101L-SP25XC
CY14B101L-SZ25XIT
CY14B101L-SZ25XI
CY14B101L-SP25XIT
CY14B101L-SP25XI
CY14B101L-SZ35XCT
CY14B101L-SZ35XC
CY14B101L-SP35XCT
CY14B101L-SP35XC
CY14B101L-SZ35XIT
CY14B101L-SZ35XI
CY14B101L-SP35XIT
CY14B101L-SP35XI
51-85127
51-85127
51-85061
51-85061
51-85127
51-85127
51-85061
51-85061
51-85127
51-85127
51-85061
51-85061
51-85127
51-85127
51-85061
51-85061
Commercial
32-pin SOIC
48-pin SSOP
48-pin SSOP
32-pin SOIC
32-pin SOIC
48-pin SSOP
48-pin SSOP
32-pin SOIC
32-pin SOIC
48-pin SSOP
48-pin SSOP
32-pin SOIC
32-pin SOIC
48-pin SSOP
48-pin SSOP
Industrial
35
Commercial
Industrial
Document Number: 001-06400 Rev. *I
Page 14 of 18
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CY14B101L
Ordering Information
Speed
Operating
Range
Ordering Code
Package Diagram
Package Type
32-pin SOIC
(ns)
45
CY14B101L-SZ45XCT
CY14B101L-SZ45XC
CY14B101L-SP45XCT
CY14B101L-SP45XC
CY14B101L-SZ45XIT
CY14B101L-SZ45XI
CY14B101L-SP45XIT
CY14B101L-SP45XI
51-85127
51-85127
51-85061
51-85061
51-85127
51-85127
51-85061
51-85061
Commercial
32-pin SOIC
48-pin SSOP
48-pin SSOP
32-pin SOIC
32-pin SOIC
48-pin SSOP
48-pin SSOP
Industrial
All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts
Package Diagrams
Figure 14. 32-Pin (300 Mil) SOIC (51-85127)
PIN 1 ID
16
1
MIN.
MAX.
DIMENSIONS IN INCHES[MM]
REFERENCE JEDEC MO-119
0.292[7.416]
0.299[7.594]
0.405[10.287]
0.419[10.642]
PART #
17
32
S32.3 STANDARD PKG.
SZ32.3 LEAD FREE PKG.
SEATING PLANE
0.810[20.574]
0.822[20.878]
0.090[2.286]
0.100[2.540]
0.004[0.101]
0.050[1.270]
TYP.
0.006[0.152]
0.012[0.304]
0.041[1.041]
0.026[0.660]
0.032[0.812]
0.021[0.533]
0.004[0.101]
0.0100[0.254]
0.014[0.355]
0.020[0.508]
51-85127-*A
Document Number: 001-06400 Rev. *I
Page 15 of 18
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CY14B101L
Package Diagrams (continued)
Figure 15. 48-Pin Shrunk Small Outline Package (51-85061)
51-85061-*C
Document Number: 001-06400 Rev. *I
Page 16 of 18
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CY14B101L
Document History Page
Document Title: CY14B101L 1 Mbit (128K x 8) nvSRAM
Document Number: 001-06400
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
*A
*B
425138
437321
471966
TUP
TUP
TUP
New data sheet
Show data sheet on External Web
Changed I from 5 mA to 10 mA
CC3
Changed ISB from 2 mA to 3 mA
Changed V
Changed t
from 2.2V to 2.0V
IH(min)
from 40
μs to 50
μs
RECALL
Changed Endurance from 1 million Cycles to 500K Cycles
Changed Data Retention from 100 years to 20 years
Added Soft Sequence Processing Time Waveform
Updated Part Numbering Nomenclature and Ordering Information
*C
503272
PCI
Changed from Advance to Preliminary
Changed the term “Unlimited” to “Infinite”
Changed Endurance from 500K Cycles to 200K Cycles
Added temperature specification to Data Retention - 20 years at 55
°C
Removed Icc values from the DC table for 25 ns and 35 ns industrial grade
1
Changed Icc value from 3 mA to 6 mA in the DC table
2
Added a footnote on V
IH
Changed V
from 2.55V to 2.45V
SWITCH(min)
Added footnote 17 related to using the software command
Updated Part Nomenclature Table and Ordering Information Table
*D
597002
TUP
Removed V
table
specification from the AutoStore/Power Up RECALL
SWITCH(min)
Changed t
specification from 20 ns to 1 ns
GLAX
Added t
specification of 70
μs in the hardware STORE cycle table
DELAY(max)
Removed t
specification
HLBL
Changed t specification from 70
μ
s (min) to 70 s (max)
μ
SS
Changed V
from 57
μF to 120
μF
CAP(max)
*E
*F
688776
1349963
2427986
VKN
UHA/SFV
GVCH
Added footnote related to HSB
Changed t to t
GLAX
GHAX
Changed from Preliminary to Final
Updated Ordering Information table
*G
*H
Move to external web
2546756 GVCH/AESA 08/01/2008 Aligned part number nomenclature
Corrected typo in ordering information
Changed pin definition of NC pin
Updated data sheet template
*I
2625139 GVCH/PYRS
01/30/09
Updated “features”
o
Added data retention at 55 C
Updated WE pin description
Added best practices
Added I
spec for 25ns and 35ns access speed for industrial temperate
CC1
Updated V from Vcc+0.3 to Vcc+0.5
IH
Removed footnote 4 and 5
Added Data retention and Endurance Table
Added Thermal resistance values
Changed parameter t to t
AS
SA
Changed t
Renamed t
from 50us to 120us (Including t of 70us)
RECALL
ss
to t
GLAX
HA
Updated figure 11 and 12
Renamed t to t
HLHX
PHSB
Updated Figure 13
Document Number: 001-06400 Rev. *I
Page 17 of 18
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CY14B101L
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales
Products
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Clocks & Buffers
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Memories
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USB
© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-06400 Rev. *I
Revised January 30, 2009
Page 18 of 18
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective
holders.
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