Quadrature Encoder Counter Board
Models: 2IQEC2 2IQEC4
Documentation Number 2IQEC2/43798
This product
Designed and Manufactured
In Ottawa, Illinois
USA
of domestic and imported parts by
B&B Electronics Mfg. Co. Inc.
707 Dayton Rd. P.O. Box 1040 -- Ottawa, IL 61350
PH (815) 433-5100 -- FAX (815) 433-5105
Internet:
1998 B&B Electronics -- September 1998
2IQEC2/43798 Manual
Cover Page
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PH (815) 433-5100 -- FAX (815) 433-5105
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Chapter 1: Introduction
The 2IQEC2/4 is a 2/4 channel quadrature encoder 24 bit
counter card used to track the position of up to 4 separate
encoders. This card is an ISA card that can be used in either an 8
or 16 bit slot. This card allows the computer to keep track of
position without a lot of CPU overhead, freeing it up for more
important tasks.
The 2IQEC2/4 offers a huge amount of flexibility. Upon a
borrow or carry the card can be configured to reset, load a preset,
cause an interrupt request or simply send out a TTL signal to
indicate the carry or borrow. The card contains two inputs that can
be configured to clear the counter or load the preset into the
counter. The index lines may also be used to clear the counter,
load the preset or cause an interrupt. The four channels use IRQ
sharing to prevent all the computer's resources from being taken up
by this card. The interrupt service routine can poll the card to find
out which channel caused the interrupt request.
Packing List
Examine the shipping carton and contents for physical damage.
The following items should be in the shipping carton:
1.
2.
3.
2IQEC2 or 2IQEC4
2IQEC2/4 3.5" disk
This instruction manual
If any of these items are damaged or missing contact B&B
Electronics immediately.
Address Switch Setup
The 2IQEC2/4 cards use a 7-position DIP switch to program
the binary I/O address of each port on the card. The 2IQEC2/4
cards are factory configured for address 0x300 with no IRQ. If you
plan on installing the 2IQEC2/4 with these settings, check the switch
settings to ensure that they did not get inadvertently changed during
shipping.
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Specifications
ꢀ
Bus: IBM PC ISA Bus
ꢀ
Slot: Requires 1 full length slot for complete IRQ selectability.
When installed in a short slot, IRQs 10-15 will not be available.
The four channel card requires an additional space to mount the
connectors in the back panel. This space does not need a slot
on the motherboard.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Dimensions: 8.75" x 4.4"
I/O connection: 15-pin female D-sub connectors
Interrupt: IRQ 2-7, 10-12, 14, or 15.
Address: Switch programmable, 0 to hex 7F0
RS-422 Differential inputs
Differential input high-threshold voltage 0.2V maximum
Differential input low threshold voltage -0.2V maximum
Input differential voltage range 1.5 to 6 volts
TTL inputs
Input high threshold 2 V Maximum
Input low threshold 0.7 V Maximum
Input voltage range -0.2 to 5.5 volts
TTL outputs
ꢀ
ꢀ
1 mA source @ 4.375 V
5 mA sink @ 0.5 V
ꢀ
ꢀ
12 MHz count rate in quadrature 4X mode.
24-bit counters for up to four axes on 2IQEC4
(two axes on 2IQEC2)
ꢀ
ꢀ
Digital filtering of the quadrature clocks
Power Consumption
+5 VDC @ 250 mA
(See additional specifications in Appendix B.)
2
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Chapter 2: Installation
Software Installation
The 2IQEC2/4 comes with a useful example program. This
example program may be used royalty free when used with the B&B
Electronics 2IQEC2/4. Any other use is strictly prohibited. To install
this example file on your hard drive:
1. Place the disk in drive A:
2. Type A: and press the <ENTER> key.
3. Type Install and press the <ENTER> key.
4. Follow the instructions given by the program.
Installing the Card
1. Turn the power to your computer off.
2. Remove the cover of the computer. Be sure to use proper
grounding techniques.
3. Pick any full length (16-bit) unused slot. Although the 2IQEC2/4
cards will work in a short (8-bit) slot, IRQ's 10-15 will not be
available.
4. Remove the expansion slot cover. Save the screw for
installation of the 2IQEC2/4 card.
5. Set the address, IRQ, and other jumper settings. See Card
Settings in the next section for instructions on setting the
address and IRQ.
6. Install the 2IQEC2/4 card into the unused slot. Be certain that
the card is inserted completely into the slot.
7. Secure the card with the mounting screw.
Card Settings
Address
Switch S1 configures the address of the card. Switches
represent a 0 in the ON position, 1 when OFF. The address lines
are labeled on the card. SA10 is the MSB and SA4 is the LSB.
Table 1 shows the numerical weight and electrical connection of
each switch position.
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Table 1. Address Switches
1st Digit
6
2nd Digit
Switch
7
5
4
3
2
1
Position
Bus
Connection
Decimal
Weight
SA10
SA9
512
200
SA8
SA7
SA6
SA5
SA4
1024
400
256
100
128
80
64
40
32
20
16
10
Hex Weight
To set the address of the 2IQEC2/4 card at some common
locations, follow the switch settings shown in Table 2.
Table 2. Frequently Unused Port Addresses
Base
Binary
Switch
I/O Space
Hex
Address
Equivalent
Settings
Description
MSB
LSB
7654321
0100000
0110000
0110001
0111000
0111010
200
300
310
380
3A0
1000000000
1100000000
1100010000
1110000000
1110100000
game port
prototype
prototype
SDLC
bisync com
To install at another address, follow the procedure below.
1.
Select the address. Using an I/O port usage table (one is
included in Appendix A) select an unused hex address
space. Note that the card occupies 16 bytes of I/O space.
Use caution when selecting a port address. It is very
important that nothing else is installed at the selected
address.
2.
3.
4.
Convert the hex address to its binary equivalent.
Throw away the 4 least significant bits.
The remaining 7 digits represent the switch address. 1's
represent an OFF switch. 0's represent an ON switch.
4
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IRQ
The 2IQEC2/4 card allows the use of interrupts (IRQ) 2-7,
10-12, 14, and 15. This interrupt is shared with all the channels. To
determine the channel that caused the interrupt, the interrupt
service routine must read the address located at the base address
plus 8. The lower nibble will indicate which channel caused the
interrupt. Where bit 0 is the X-Axis, bit 1 is the Y-Axis, bit 2 is the Z-
Axis, and bit 3 is the W-Axis. The upper nibble is not used. To
clear the interrupt, the interrupt service routine must read or write to
the address located at base address plus 12 (0xC). The IRQ is set
by placing a jumper on JP1. Only one jumper should be placed on
JP1 at any one time. Check Table 3 for common interrupt uses.
Table 3. Hardware Interrupts
IRQ AT machines
XT machines
2
routed to IRQ controller 2 Reserved
3
4
5
serial port COM2,4
serial port COM1,3
LPT2
Serial port COM2,4
Serial port COM1,3
hard disk
6
floppy disk
Floppy disk
7
8
9
10
11
12
13
14
15
LPT1
parallel printer port 1 (LPT1)
not available
not available
not available
not available
not available
not available
not available
not available
real-time clock
re-directed to IRQ2
Unassigned
Unassigned
Unassigned
Coprocessor
hard disk
Unassigned
The conditions required to generate an interrupt can be
selected by the use of jumpers. Each axis is independently
configured. Note that more than one condition can be configured to
generate the interrupt. Note that the use of an interrupt is not
required.
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Configuring the jumpers
The jumpers located on the left side of the card make it
easy to configure the card to your individual needs. The jumpers
are grouped by axis and function. The top group of jumpers is for
the X axis. Then next groups going down are for the Y-axis, Z-axis,
and W-axis respectfully. There are three signals that can be routed
via these jumpers. They are the FLG1 and FLG2 outputs from the
counter chips, and the index from the encoder. The FLG1 and
FLG2 outputs are software configurable. The FLG1 can be
configured to act as a carry (pulse on counter overflow), compare
(pulse when counter equals the preset register), index, or carry and
borrow (pulse on either an overflow or an underflow of the counter).
The FLG2 can be configured to act as a borrow, up-down indicator,
or an error flag. These outputs are brought to the user connectors.
The first jumpers labeled JP4, JP8, JP12 and JP16 allow
you to select what conditions cause the counter to be loaded with
the preset value in the preset register. The middle jumpers labeled
JP3, JP7, JP11, and JP15 allow you to select what conditions cause
the counter to be reset or the counter to be enabled depending on
the software configuration of the input. The last jumpers labeled
JP2, JP6, JP10, and JP14 are used to define what conditions cause
an interrupt (IRQ).
JP5 selects the type of input encoder signals for the X and
Y axes not including the index. Set jumper JP5 for RS-422
differential mode and remove the jumper for TTL level encoder
input. When in differential mode the TTL output of the differential
receivers is present at the TTL pins. Leave these pins unconnected
in differential mode.
JP13 selects the type of input encoder signals for the Z and
W axis not including the index. Set jumper JP13 for RS-422
differential mode and remove the jumper for TTL level encoder
input. When in differential mode the TTL output of the differential
receivers is present at the TTL pins. Leave these pins unconnected
in differential mode.
JP9 selects the type of input from the index pins. This
jumper affects all the axes' index inputs. Set jumper JP9 for RS-422
differential mode and remove the jumper for TTL level encoder
input. When in differential mode the TTL output of the index
receivers is present at the TTL pins. Leave these pins unconnected
in differential mode.
6
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Location of Jumpers
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Software Registers
Flag Register (Read Data Address)
The FLAG register is a read-only register that holds the
status information of the counters and can be read out on the data
bus. To read the FLAG byte for any axis, read the control address
of that axis.
FLAG Byte Defined
7 6 5 4 3 2 1 0
BT: Borrow toggle flip-flop.
Toggles every time CNTR underflows
CT: Carry toggle flip-flop.
Toggles every time CNTR overflows
CPT: Compare toggle flip-flop.
Toggles every time PR equals CNTR.
S: Sign flag. Set to 1 when CNTR underflows.
Reset to 0 when CNTR overflows
E: Error flag. Set to 1 when excessive noise is present at
the count inputs in quadrature mode. Irrelevant in non-
quadrature mode.
U/D': Up/Down flag. Set to 1 when counting up
And reset to 0 when counting down
IDX: Index. Set to 1 when selected index input is at active
level.
0: Not used. Always reset to 0.
Reset and Load Signal Decoders (Write to Control Address)
The following functions can be performed by writing to the
control address for that axis. Note that bits 5 and 6 define the
register and should always be zero when writing to the RLD register.
RLD Byte Defined
7 6 5 4 3 2 1 0
X
X
0
0
0
0
X
X
X
X
X
X
X
X
0
1
NOP
Reset BP
X
X
X
X
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
0
0
1
1
0
1
0
1
X
X
X
X
NOP
Reset CNTR
Reset BT, CT, CPT, S
Reset E
X
X
X
X
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
NOP
Transfer PR to CNTR
Transfer CNTR to OL
Transfer PR0 to PSC
0
1
0
0
0
0
X
X
X
X
X
X
X
X
X
X
Select the RLD addressed by X'/Y input
Select both XRLD and YRLD or ZRLD and WRLD together
8
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Filter Clock Prescalers
Each PSC is an 8-bit programmable modulo-N down
counter, driven by the FCK clock. The factor N is downloaded into a
PSC from the associated PR low byte register PR0. The PSCs
provide the ability to generate independent filter clock frequencies
for each channel.
Final filter clock frequency
FFCKn=fFCK/(n+1), where n=PSC=0 to 255
Counter Mode Registers (Write to Control Address)
The counter’s operational mode is programmed by writing a
byte into the counter mode registers (CMRs).
CMR Byte Defined
7 6 5 4 3 2 1 0
X
X
0
0
1
1
X
X
X
X
X
X
X
X
0
1
Binary Count
Binary Coded Decimal Count
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
0
0
1
1
0
1
0
1
X
X
X
X
Normal Count
Range Limit
Non-Recycle Count
Modulo-N
X
X
X
X
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
Non-quadrature
Quadrature 1X
Quadrature 2X
Quadrature 4X
0
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
Select the CMR addressed by X'/Y input
Select both XCMR and YCMR or ZCMR and WCMR
together
Definitions of count modes
Range Limit. In range limit count mode, an upper and a
lower limit is set, mimicking limit switches in the mechanical
counterpart. The upper limit is set by the contents of the PR and the
lower limit is set to be 0. The CNTR freezes at CNTR=PR when
counting up and at CNTR=0 when counting down. At either of these
limits, the counting is resumed only when the count direction is
reversed.
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Non-Recycle. In non-recycle count mode, the CNTR is disabled,
whenever a count overflow or underflow takes place. The end of
cycle is marked by the generation of a Carry (in Up Count) or a
Borrow (in Down Count). The CNTR is re-enabled when a reset or
load operation is performed on the CNTR.
Modulo-N. In modulo-N count mode, a count boundary is set
between 0 and the content of PR. When counting up at CNTR=PR,
the CNTR is reset to 0 and the up count is continued from that point.
When counting down, at CNTR=0, the CNTR is loaded with the
content of PR and down count is continued from that point.
The modulo-N is true bidirectional in that the divide-by-N
output frequency is generated in both up and down direction of
counting for same N and does not require the complement of N in
the UP instance. In frequency divider application, the modulo-N
output frequency can be obtained at either the Compare(FLG1) or
the Borrow(FLG2) output. Modulo-N output frequency, fN=fI/(N+1)
where fI is the input count frequency and N=PR.
Input/Output Control Register (Write to Control Address)
The functional modes of the programmable input and output
pins are written into the IORs.
IOR Byte Defined
7 6 5 4 3 2 1 0
X
X
1
1
0
0
X
X
X
X
X
X
X
X
0
1
Disable inputs A and B
Enable inputs A and B
X
X
1
1
0
0
X
X
X
X
X
X
0
1
X
X
LCNTR'/LOL' pin is Load CNTR input
LCNTR'/LOL' pin is Load OL input
X
X
1
1
0
0
X
X
X
X
1
0
X
X
X
X
RCNTR'/ABG pin is Reset CNTR input
RCNTR'/ABG pin is A and B Enable gate
X
X
X
X
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
FLG1 pin is Carry' output, FLG2 pin is Borrow' output
FLG1 pin is Compare' output, FLG2 pin is Borrow' output
FLG1 pin is Carry'/Borrow' output, FLG2 pin is U/D'
FLG1 pin is IDX, FLG2 is E
0
1
1
1
0
0
X
X
X
X
X
X
X
X
X
X
Select the IOR addressed by X'/Y input
Select both XIOR and YIOR or ZIOR and WIOR together
10
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Index Control Registers (Write to Control Address)
Either the LCNTR'/LOL' or the RCNTR'/ABG inputs can be
initialized to operate as an index input. When initialized as such,
the index signal from the encoder, applied to one of these inputs
performs either the Reset CNTR or the Load CNTR or the Load OL
operation synchronously with the quadrature clocks. Note that only
one of these inputs can be selected as the Index input at a time and
hence only one type on indexing function can be performed in any
given set-up. The index function must be disabled in non-
quadrature count mode.
IDR Byte Defined
7 6 5 4 3 2 1 0
X
X
1
1
1
1
X
X
X
X
X
X
X
X
0
1
Disable Index
Enable Index
X
X
1
1
1
1
X
X
X
X
X
X
0
1
X
X
Negative Index Polarity
Positive Index Polarity
X
X
1
1
1
1
X
X
X
X
1
0
X
X
X
X
LCNTR'/LOL' pin is indexed
RCNTR'/ABG pin is indexed
0
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
Select the IDR addressed by X'/Y input
Select both XCIDR and YIDR or ZIDR and WIDR together
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Chapter 3: TROUBLESHOOTING
If you are unable to communicate with the card from your software:
1.
3.
4.
5.
Double check that the address is properly set.
Check your pinouts.
Try the demo software that comes with the card.
Call B&B Electronics' Technical Support. Technicians are
available at (815) 433-5100 to answer your questions from 8
am - 5:00 pm weekdays (Central Time).
12
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Appendix A: Hardware I/O Map
I/O Map of XT Class Machines
Hex Address Address Function in XT Class Machines
000-00F
020-021
040-043
060-063
080-083
0A0-0AF
200-20F
210-217
2E8-2EF
2F8-2FF
300-31F
320-32F
378-37F
380-38F
3B0-3BF
3D0-3D7
3E8-3EF
3F0-3F7
3F8-3FF
DMA controller (8237A)
interrupt controller (8259A)
timer (8253)
PPI (8255A)
DMA page register (74LS612)
NMI - non maskable interrupt
game port joystick controller
expansion unit
COM4 serial port
COM2 serial port
prototype card
hard disk
parallel printer
SDLC
MDA - monochrome adapter and printer
CGA - color graphics adapter
COM3 serial port
floppy diskette controller
COM1 serial port
2IQEC2/43798 Manual
Appendix A: Hardware I/O Maps
A-1
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Hardware I/O Map of AT Class Machines
Hex Address Address Function in AT Class Machines
000-01F
020-03F
040-05F
060-06F
070-07F
080-09F
0A0-0BF
0C0-0DF
0F0-0FF
1F0-1F8
200-20F
258-25F
278-27F
2E8-2EF
2F8-2FF
300-31F
378-37F
380-38F
3A0-3AF
3B0-3BF
3BC-3BE
3C0-3CF
3D0-3D7
3E8-3EF
3F0-3F7
3F8-3FF
DMA controller #1 (8237A-5)
interrupt controller #1 (8259A)
timer (8254)
keyboard (8042)
NMI - non maskable interrupt & CMOS RAM
DMA page register (74LS612)
interrupt controller #2 (8259A)
DMA controller #2 (8237A)
80287 math coprocessor
hard disk
game port joystick controller
Intel Above Board
parallel printer port 2
COM4 serial port
COM2 serial port
prototype card
parallel printer 1
SDLC or bisynch com 2
bisynch com 1
MDA - monochrome adapter
parallel printer on monochrome adapter
EGA - reserved
CGA - color graphics adapter
COM 3 serial port
floppy diskette controller
COM1 serial port
Any sixteen byte space not listed above and not used
by any other equipment in your system may be used for the
serial port.
A-2 Appendix A: Hardware I/O Maps
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Appendix B: Specifications/Timing Diagrams
Pin Description
1.
A+
2.
A-
3.
A (TTL)
4.
B+
5.
B-
6.
B (TTL)
7.
I+
8.
I-
9.
I (TTL)
10.
11.
12.
13.
14.
15.
FLG 2 (Programmed output)
FLG 1 (Programmed output)
Load Counter (Input)
Reset Counter (Input)
+5VDC
Ground
Addresses
Base ............................. X Axis Data
Base+1 ......................... X Axis Control
Base+2 ......................... Y Axis Data
Base+3 ......................... Y Axis Control
Base+4 ......................... Z Axis Data
Base+5 ......................... Z Axis Control
Base+6 ......................... W Axis Data
Base+7 ......................... W Axis Control
Base+8 ......................... IRQ Register
Base+9 ......................... Do not use
Base+10 ....................... Do not use
Base+11 ....................... Do not use
Base+12 ....................... Clear IRQ
Base+13 ....................... Do not use
Base+14 ....................... Do not use
Base+15 ....................... Do not use
2IQEC2/43798 Manual
Appendix B: Specifications
B-1
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Transient Characteristics
Quadrature Mode
Parameter
Symbol
Min.Value Max. Value Unit Remarks
FCK High Pulse Width
FCK Low Pulse Width
FCK Frequency
t1
t2
fFCK
t 3
21
21
-
-
-
24
-
ns
ns
MHz
ns
-
-
-
Mod-n Filter Clock(FCKn)Period
42
t3= (n+1) (t1+t2),
where
N=PSC=0 to FFH
-
t4≥2t3
t5≥4t3
FCKn Frequency
Quadrature Separation
Quadrature ClockPulse Width
Quadrature ClockFrequency
Quadrature Clockto Count Delay
X1/X2/X4 Count ClockPulse Width t Q2
Index Input Pulse Width
Index Skew from A
Carry/Borrow/Compare Output Width
fFCKn
t4
t 5
f QA, fQB
t Q1
-
24
-
-
3
6t3
-
-
42
-
MHz
ns
ns
83
167
-
5t3
42
125
-
MHz fQA=fQB=1/8t3
-
-
ns
ns
ns
ns
tQ2=t3
tidx≥3t3
tAi≤t3
tQ3=t3
tidx
tAi
tQ3
42
Non-Quadrature Mode
Parameter
Symbol
Min.Value Max. Value Unit Remarks
ClockA – High Pulse Width
ClockA – Low Pulse Width
Direction Input B Set-up Time
Direction Input B Hold Time
Gate Input (ABG) Set-up Time
Gate Input (ABG) Hold Time
ClockFrequency (non-Mod-N)
ClockFrequency (Mod-N)
t 6
t 7
t8S
t8H
tGS
tGH
f A
f AN
16
16
20
20
20
20
-
-
-
16
-
-
-
-
-
-
30
25
30
-
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
MHz fA=(1/ (t6+t7))
MHz
ns
-
-
Clockto Carry or Borrow Out Delay t 9
Carry or Borrow Out Pulse Width
Load CNTR, Reset CNTR and
Load OL Pulse Width
t10
ns
t10=t7
t11
t 12
20
50
-
-
ns
ns
-
-
Clockto Compare Out Delay
B-2
Appendix B: Specifications
2IQEC2/43798 Manual
B&B Electronics -- PO Box 1040 -- Ottawa, IL 61350
PH (815) 433-5100 -- FAX (815) 433-5105
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Filter Clock (modulo-1 shown)
Quadrature Clock and Index (Positive index shown)
2IQEC2/43798 Manual
Appendix B: Specifications
B-3
B&B Electronics -- PO Box 1040 -- Ottawa, IL 61350
PH (815) 433-5100 -- FAX (815) 433-5105
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Carry, Borrow, Compare, Carry Toggle, Borrow Toggle and
Compare Toggle
(4X Quadrature, Normal, Binary Count, and PR=1)
Non Quadrature mode (A=Count B=Direction)
B-4
Appendix B: Specifications
2IQEC2/43798 Manual
B&B Electronics -- PO Box 1040 -- Ottawa, IL 61350
PH (815) 433-5100 -- FAX (815) 433-5105
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Non-Recycle, Non-Quadrature, BCD Mode
Modulo-N, Non-Quadrature (Modulo-3 shown)
Range Limit, Non-Quadrature (PR=4)
2IQEC2/43798 Manual
Appendix B: Specifications
B-5
B&B Electronics -- PO Box 1040 -- Ottawa, IL 61350
PH (815) 433-5100 -- FAX (815) 433-5105
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Appendix C: Typical Set-up Examples
2IQEC2/43798 Manual Appendix C: Typical Set-up Examples C-1
B&B Electronics -- PO Box 1040 -- Ottawa, IL 61350
PH (815) 433-5100 -- FAX (815) 433-5105
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