AT91SAM9XE-EK Evaluation Board
....................................................................................................................
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Table of Contents (Continued)
4.3 Microcontroller Clock ......................................................................................................... 4-2
4.4 Memory Configuration........................................................................................................ 4-2
4.5 Ethernet ............................................................................................................................. 4-3
4.6 Miscellaneous .................................................................................................................... 4-3
Schematics.................................................................................................................5-1
5.1 Schematics ........................................................................................................................ 5-1
Revision History .........................................................................................................6-1
6.1 Revision History................................................................................................................. 6-1
ii
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Section 1
Overview
1.1
1.2
Scope
The AT91SAM9XE-EK evaluation kit enables the evaluation of and code development for applications
running on an AT91SAM9XE device.
This guide focuses on the AT91SAM9XE-EK board as an evaluation platform.
The board supports the AT91SAM9XE in an LFBGA217 package as well as in a PQFP208 package.
Deliverables
The AT91SAM9XE-EK package contains the following items:
„ an AT91SAM9XE-EK board
„ universal input AC/DC power supply with US, UK and Europe plug adapter
„ one A/B-type USB cable
„ one serial RS232 cable
„ one RJ45 crossed Ethernet cable
„ one CD-ROM that allows the user to begin evaluating the AT91 ARM® Thumb® 32-bit microcontroller
quickly.
1.3
AT91SAM9XE-EK Evaluation Board
The board is equipped with an AT91SAM9XE (217-ball LFBGA package) together with the following:
„ 64 Mbytes of SDRAM memory
„ 256 Mbytes of NANDFlash memory
„ one Atmel serial DataFlash®
„ one Atmel TWI serial EEPROM
„ one USB device port interface
„ two USB Host port interfaces
„ one DBGU serial communication port
„ one complete MODEM serial communication port
„ one additional serial communication port with RTS/CTS handshake control
„ JTAG/ICE debug interface
„ one PHY Ethernet 100-base TX with three status LEDs
„ one Atmel AT73C213 Audio DAC
„ one Power LED and one general-purpose LED
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„ two user input push buttons
„ one Wakeup input push button
„ one reset push button
„ one DataFlash, SD/MMC card slot
„ four expansion connectors (PIOA, PIOB, PIOC, IMAGE SENSOR)
„ one BGA-like EBI expansion footprint connector
„ one Lithium Coin Cell Battery Retainer for 12 mm cell size
1-2
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Section 2
Setting Up the AT91SAM9XE-EK Board
2.1
2.2
Electrostatic Warning
The AT91SAM9XE-EK evaluation board is shipped in protective anti-static packaging. The board must
not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be
worn when handling the board. Avoid touching the component pins or any other metallic element.
Requirements
In order to set up the AT91SAM9XE-EK evaluation board, the following items are needed:
„ the AT91SAM9XE-EK evaluation board itself.
„ AC/DC power adapter (5V at 2A), 2.1 mm by 5.5 mm
2.3
Layout
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Figure 2-1. AT91SAM9XE-EK Layout-Top View
2-2
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Figure 2-2. AT91SAM9XE-EK Layout - Bottom View
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2.4
2.5
Powering Up the Board
The AT91SAM9XE-EK requires 5V DC ( 5%). DC power is supplied to the board via the 2.1 mm by 5.5
mm socket J1. Coaxial plug center positive standard.
Backup Power Supply
The user has the possibility to plug a battery (3V Lithium Battery CR1225 or equivalent) in order to per-
manently power the backup part of the device. In this case, J10 configuration must be set in position 1, 2.
2.6
Getting Started
The AT91SAM9XE-EK evaluation board is delivered with a CD-ROM containing all necessary informa-
tion and step-by-step procedures for working with the most common development toolchains. Please
date information on getting started with the AT91SAM9XE-EK.
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Section 3
Board Description
3.1
AT91SAM9XE 512/256/128 Microcontroller
• Incorporates the ARM926EJ-S™ ARM® Thumb® Processor
– DSP instruction Extensions, ARM Jazelle® Technology for Java® Acceleration
– 8 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer
– 200 MIPS at 180 MHz
– Memory Management Unit
– EmbeddedICE™, Debug Communication Channel Support
• Additional Embedded Memories
– One 32 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed
– One 32 Kbyte (for AT91SAM9XE256 and AT91SAM9XE512) or 16 Kbyte (for AT91SAM9XE128) Internal SRAM, Single-cycle
Access at Maximum Matrix Speed
– 128, 256 or 512 Kbytes of Internal High-speed Flash for AT91SAM9XE128, AT91SAM9XE256 or AT91SAM9XE512
Respectively. Organized in 256, 512 or 1024 Pages of 512 Bytes Respectively.
• 128-bit Wide Access
• Fast Read Time: 60 ns
• Page Programming Time: 4 ms, Including Page Auto-erase,
Full Erase Time: 10 ms
• 10,000 Write Cycles, 10 Years Data Retention, Page Lock Capabilities, Flash Security Bit
• Enhanced Embedded Flash Controller (EEFC)
– Interface of the Flash Block with the 32-bit Internal Bus
– Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory Interface
• External Bus Interface (EBI)
– Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash™
• USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, 2,688-byte Configurable Integrated DPRAM
• USB 2.0 Full Speed (12 Mbits per second) Host Single Port in the 208-pin PQFP Device and Double Port in 217-ball LFBGA
Device
– Single or Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
• Ethernet MAC 10/100 Base-T
– Media Independent Interface or Reduced Media Independent Interface
– 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
• Image Sensor Interface
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
• Bus Matrix
– Six 32-bit-layer Matrix
– Remap Command
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• Fully-featured System Controller, including
– Reset Controller, Shutdown Controller
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer
• Reset Controller (RSTC)
– Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control
• Clock Generator (CKGR)
– Selectable 32,768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power Supply,
Providing a Permanent Slow Clock
– 3 to 20 MHz On-chip Oscillator, One Up to 240 MHz PLL and One Up to 100 MHz PLL
• Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
– Two Programmable External Clock Signals
• Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
• Debug Unit (DBGU)
– 2-wire UART and support for Debug Communication Channel, Programmable ICE Access Prevention
• Periodic Interval Timer (PIT)
– 20-bit Interval Timer Plus 12-bit Interval Counter
• Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
• Real-Time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
• One 4-channel 10-bit Analog to Digital Converter
• Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC,)
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
• Peripheral DMA Controller Channels (PDC)
• Two-slot Multimedia Card Interface (MCI)
– SDCard/SDIO and MultiMediaCard™ Compliant
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
• One Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
– Full Modem Signal Control on USART0
• One 2-wire UART
• Two Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– Synchronous Communications
• Two Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
– High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2
3-2
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• Two Two-wire Interfaces (TWI)
– Master, Multi-master and Slave Mode Operation
– General Call Supported in Slave Mode
– Connection to PDC Channel to Optimize Data Transfers in Master Mode Only
• IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
• Required Power Supplies:
– 1.65V to 1.95V for VDDBU, VDDCORE and VDDPLL
– 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os)
– 3.0V to 3.6V for VDDIOP0 and VDDANA (Analog-to-digital Converter)
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os)
• Available in a 208-pin PQFP Green and a 217-ball LFBGA Green Package
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3.3
3.4
Microcontroller
„ One LFBGA 217-ball device fitted on board
„ One LQFP 208-lead device footprint
To use the microcontroller in the LQFP package, the user has to unsolder MN4 and solder the PQFP208
microcontroller on the MN6 footprint.
Memory
„ 32 Kbytes of Internal ROM
„ 32 Kbyte of Internal SRAM
„ 512 Kbytes of Internal High-speed Flash
„ Atmel serial DataFlash
„ 64 Mbytes of SDRAM memory (32-bit bus width)
„ 256 Mbytes of NANDFlash memory (8-bit bus width)
„ TWI serial EEPROM
3.5
Clock Circuitry
„ 18.432 MHz standard crystal for the embedded oscillator
„ Selectable 32768Hz Low-power external standard crystal Oscillator or Internal Low Power RC
Oscillator
3.6
3.7
3.8
3.9
Reset Circuitry
„ Internal reset controller with bi-directional reset pin
„ External reset pushbutton
Shutdown Controller
„ Programmable shutdown and Wake-Up
„ Wake-up push button
Power Supply Circuitry
„ On-board 1.8V High Efficiency step-down charge pump regulator with shutdown control
„ On-board 3.3V linear regulator with shutdown control
Remote Communication
„ One serial interface (DBGU COM Port) via RS-232 DB9 male socket
„ One complete modem serial interface (COM Port 0) via RS-232 DB9 male socket
„ One additional serial interface (COM Port 1) with RTS/CTS handshake control via RS-232 DB9 male
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socket
„ USB V2.0 full-speed compliant, 12 Mbits per second (UDP)
„ One Ethernet 100-base TX with three status LEDs
3.10
3.11
Audio Stereo Interface
„ One Atmel stereo audio DAC (AT73C213)
„ One 32 Ohm/20 mW Stereo Headset output (J4) with master volume and mute controls
User Interface
„ One user green LED
„ One yellow power LED (can be also software controlled)
3.12
3.13
Debug Interface
„ 20-pin JTAG/ICE interface connector
„ DBGU COM port
Expansion Slot
„ One DataFlash, SD/MMC card slot
„ All I/Os of the AT91SAM9XE are routed to peripheral extension connectors
„ All I/Os of the AT91SAM9XE Image Sensor Interface are routed to peripheral extension connectors
„ All EBI Signals of the AT91SAM9XE are routed to extension footprint connectors (J25)
This allows the developer to check the integrity of the components and to extend the features of the
board by adding external hardware components or boards.
Notes: 1. Only one available with the 208-lead PQFP package.
2. Not available with the 208-lead PQFP package.
3-6
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3.14
PIO Usage
Table 3-1. PIO Controller A
I/O Line
PA0
Peripheral A
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS0
RTS2
Peripheral B
MCDB0
Comments
Function
SPI DATAFLASH, SPI/MCI SD/MMC/DATAFLASH Slot
(PA0..PA5)
PA1
MCCDB
PA2
PA3
MCDB3
MCDB2
MCDB1
PA4
PA5
CTS2
PA6
MCDA0
MCCDA
MCCK
User LED
ETHERNET DM9161A MII/RMII (IRQ)
MCI SD/MMC/DATAFLASH Slot
Power LED
PA7
PA8
PA9
MCDA1
MCDA2
MCDA3
ETX0
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
ETX2
ETX3
ETHERNET DM9161A MII Interface (PA10..PA11)
ETHERNET DM9161A RMII Interface (PA12..PA19)
ETX1
ERX0
ERX1
ETXEN
ERXDV
ERXER
ETXCK
EMDC
ETHERNET DM9161A MII/RMII Interface (PA20..PA21)
EMDIO
ADTRG
TWD
ETXER
ETX2
ETHERNET DM9161A MII Interface
SERIAL EEPROM (SDA)
TWCK
ETX3
SERIAL EEPROM (SCL)
TCLK0
TIOA0
ERX2
ERX3
ERXCK
ECRS
ECOL
RXD4
TXD4
ETHERNET DM9161A MII Interface (PA25..PA29)
High-Drive
High-Drive
High-Drive
TIOA1
TIOA2
SCK1
SCK2
(BP3) User's interface Push Button
(BP4) User's interface Push Button
SCK0
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Table 3-2. PIO Controller B
I/O Line
PB0
Peripheral A
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
SPI1_NPCS0
TXD0
Peripheral B
TIOA3
Comments
Function
Audio DAC AT73C213 (MISO)
Audio DAC AT73C213 (MOSI)
Audio DAC AT73C213 (SPCK)
Audio DAC AT73C213 (Chip Select)
COM PORT 0 (TXD)
PB1
TIOB3
PB2
TIOA4
PB3
TIOA5
PB4
PB5
RXD0
TXD1
COM PORT 0 (RXD)
PB6
TCLK1
TCLK2
COM PORT 1 (TXD)
PB7
RXD1
TXD2
COM PORT 1 (RXD)
PB8
PB9
RXD2
TXD3
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
ISI_D8
ISI_D9
(J28) IMAGE SENSOR CONNECTOR (PB10..PB13)
RXD3
TXD5
ISI_D10
ISI_D11
RXD5
DRXD
DTXD
TK0
SERIAL DEBUG PORT(RXD)
SERIAL DEBUG PORT(TXD)
TCLK3
TCLk4
Audio DAC AT73C213 (BCLK)
TF0
Audio DAC AT73C213 (LRFS)
TD0
TIOB4
Audio DAC AT73C213 (SDIN)
RD0
TIOB5
(J28) IMAGE SENSOR CONNECTOR (CTRL2)
(J28) IMAGE SENSOR CONNECTOR (PB20..PB31)
RK0
ISI_D0
RF0
ISI_D1
DSR0
DCD0
DTR0
ISI_D2
Warning: Shared with COM PORT 0 (PB22..PB27)
ISI_D3
ISI_D4
RI0
ISI_D5
RTS0
ISI_D6
CTS0
ISI_D7
RTS1
ISI_PCK
ISI_VSYNC
ISI_HSYNC
ISI_MCK
Warning: Shared with COM PORT 1 (PB28..PB29)
CTS1
PCK0
PCK1
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Table 3-3. PIO Controller C
I/O Line
PC0
Peripheral A
Peripheral B
SCK3
Comments
Function
AD0
AD1
PC1
PCK0
Audio DAC AT73C213 (MCLK)
PC2
AD2
PCK1
PC3
AD3
SPI1_NPCS3
SPI1_NPCS2
SPI1_NPCS1
CFCE1
PC4
A23
(J28) IMAGE SENSOR CONNECTOR (CTRL1)
USB_CNX (VBUS DETECT)
PC5
A24
PC6
TIOB2
TIOB1
NCS4/CFCS0
NCS5/CFCS1
A25/CFRNW
NCS2
IRQ0
PC7
CFCE2
PC8
RTS3
PC9
TIOB0
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
CTS3
SPI0_NPCS1
NCS7
SPI DATAFLASH memory (Chip Select)
FIQ
NCS6
NandFlash (RDYBSY)
NandFlash (NANDCS)
NCS3/NANDCS
NWAIT
D16
IRQ2
IRQ1
SPI0_NPCS2
SPI0_NPCS3
SPI1_NPCS1
SPI1_NPCS2
SPI1_NPCS3
EF100
EBI Data Bus (PC16..PC31)
D17
D18
D19
D20
D21
D22
TCLK5
D23
D24
D25
D26
D27
D28
D29
D30
D31
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Section 4
Configuration
4.1
Jumpers
Table 4-1. Jumpers Configuration
Designation
Default Setting
Feature
J2
Closed
3.3V Jumper(1)
Forces power on.
J3
J6
J7
Closed
Closed
2-3
To use the software shutdown control, J3 must be opened. 3V
battery backup must be present.
VDDPLL Jumper(1)
Erase/Normal operation mode
1-2: Erase entire flash chip
2-3 or open: Normal operating mode
Slow Clock OSCSEL
J9
2 - 3
1-2: Internal RC Oscillator
2-3: External Crystal Oscillator
J10
J12
J15
J32
J33
Closed
Closed
Closed
Closed
Closed
VDDBU Jumper(1)
VDDCORE Jumper(1)
Enables Ethernet Auto MDIX control
Enables the use of the embedded NANDFLASH device (MN6xx)
Enables the use of the embedded DATAFLASH device (MN9)
Notes: 1. These jumpers are provided for power consumption measurement. By default, they are
closed. To use this feature, the user has to open the strap and insert an ammeter.
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4.2
JTAG/ICE
Table 4-2. JTAG/ICE Configuration
Designation
Default Setting
Opened
Feature
S1
S2
Disables the ICE NTRST input
Selects ICE mode or JTAG mode
Opened
Disables TCK <-> RTCK local loop. If S3 is closed, R13 must be
unsoldered.
S3
Opened
R13
R14
Soldered
Soldered
Enables the ICE RTCK return. S3 must be opened
Enables the ICE NRST input
4.3
Microcontroller Clock
Table 4-3. Microcontroller Clock Configuration
Designation
Default Setting
Soldered
Feature
R18/R20
S4
Enables the use of 18.432MHz crystal. If an external clock is used,
R18/R20 must be unsoldered and S4 closed.
Opened
J9
4.4
Memory Configuration
Table 4-4. Memory Configuration
Designation
SDRAM
Default Setting
Feature
R31
R32
Soldered
Soldered
Enables MN7 Chip select access
Enables MN8 Chip select access
NAND Flash (MN6x)
R34
S6
Soldered
Opened
Enables the use of Ready Busy signal
Disables write protection.
SERIAL DATAFLASH (MN9)
S5
Opened
Disables the write protection.
TWI SERIAL EEPROM (MN10)
R46
R47
Soldered
Soldered
Enables SCL access
Enables SDA access
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4.5
4.6
Ethernet
RMII is the factory default mode.
To evaluate the MII mode, the user has to unsolder R49, R50, R127, close S7, S8 and populate R119 to
R126, C88, C89, Y4.
Miscellaneous
Refer to the TOP level schematic for the PIO usage.
Table 4-5. Miscellaneous
Designation
R82
Default Setting
Soldered
Feature
USB DEVICE: Enables the use of the USBCNX signal
R72
Soldered
DBGU COM Port: Enables the use of DTXD output signal.
Enables the use of DRXD input.
R73
Soldered
Soldered
RS232 COM Port 0: Enable the use of output signals.
R94
R95
R96
RTS0
TXD0
DTR0
RS232 COM Port 0: Enable the use of input signals.
R98
DCD0
R101
R103
R104
R105
R106
DSR0
RXD0
Soldered
CTS0
RI0
Enables all MAX3241E outputs buffer
RS232 COM Port 1: Enables the use of output signals.
R83
R85
TXD1
RTS1
Soldered
Soldered
RS232 COM Port 1: Enables the use of input signals.
R86
R88
RXD1
CTS1
TP1
TP2
TP3
TP4
TP5
TP6
N.A
N.A
N.A
N.A
N.A
N.A
GND Test point
GND Test point.
GND Test point.
GND Test point.
Reserved: do not use
Reserved: do not use
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Section 5
Schematics
5.1
Schematics
This section contains the following schematics:
„ Board Diagram - Schematic Top Level
„ Power supply and audio
„ 217-ball BGA AT91SAM9XE Microcontroller
„ 208-pin LQFP AT91SAM9XE Microcontroller
„ Memory
„ Ethernet
„ Serial Interface
„ Expansion and User Interface
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Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Atmel Asia
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