Motorola MPC8260 User Manual
MPC8260UM/D  
4/1999  
Rev. 0  
MPC8260 PowerQUICC IIª  
UserÕs Manual  
ª
Overview  
PowerPC Processor Core  
Memory Map  
1
2
3
System Interface Unit (SIU)  
4
Reset  
External Signals  
5
6
60x Signals  
The 60x Bus  
7
8
Clocks and Power Control  
Memory Controller  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
Secondary (L2) Cache Support  
IEEE 1149.1 Test Access Port  
Communications Processor Module Overview  
Serial Interface with Time-Slot Assigner  
CPM Multiplexing  
Baud-Rate Generators (BRGs)  
Timers  
SDMA Channels and IDMA Emulation  
Serial Communications Controllers (SCCs)  
SCC UART Mode  
SCC HDLC Mode  
SCC BISYNC Mode  
SCC Transparent Mode  
SCC Ethernet Mode  
SCC AppleTalk Mode  
Serial Management Controllers (SMCs)  
Multi-Channel Controllers (MCCs)  
Fast Communications Controllers  
ATM Controller  
Fast Ethernet Controller  
FCC HDLC Controller  
FCC Transparent Controller  
Serial Peripheral Interface (SPI)  
2
I C Controller  
Parallel I/O Ports  
Register Quick Reference Guide  
A
Glossary  
Index  
GLO  
IND  
1
Overview  
PowerPC Processor Core  
Memory Map  
System Interface Unit (SIU)  
2
3
4
Reset  
External Signals  
5
6
60x Signals  
The 60x Bus  
7
8
Clocks and Power Control  
Memory Controller  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
Secondary (L2) Cache Support  
IEEE 1149.1 Test Access Port  
Communications Processor Module Overview  
Serial Interface with Time-Slot Assigner  
CPM Multiplexing  
Baud-Rate Generators (BRGs)  
Timers  
SDMA Channels and IDMA Emulation  
Serial Communications Controllers (SCCs)  
SCC UART Mode  
SCC HDLC Mode  
SCC BISYNC Mode  
SCC Transparent Mode  
SCC Ethernet Mode  
SCC AppleTalk Mode  
Serial Management Controllers (SMCs)  
Multi-Channel Controllers (MCCs)  
Fast Communications Controllers  
ATM Controller  
Fast Ethernet Controller  
FCC HDLC Controller  
FCC Transparent Controller  
Serial Peripheral Interface (SPI)  
2
I C Controller  
Parallel I/O Ports  
Register Quick Reference Guide  
A
Glossary  
Index  
GLO  
IND  
CONTENTS  
Paragraph  
Number  
Page  
Number  
Title  
About This Book  
Before Using this ManualÑImportant Note.......................................................... lv  
Audience ................................................................................................................ lv  
Organization.......................................................................................................... lvi  
Suggested Reading................................................................................................ lix  
MPC8xx Documentation .............................................................................. lix  
PowerPC Documentation ............................................................................. lix  
Conventions ........................................................................................................... lx  
Acronyms and Abbreviations ............................................................................... lxi  
PowerPC Architecture Terminology Conventions ............................................. lxiv  
Chapter 1  
Overview  
1.1  
1.2  
1.2.1  
1.2.2  
1.2.3  
1.3  
1.3.1  
1.4  
1.5  
1.6  
1.6.1  
1.6.2  
1.7  
1.7.1  
1.7.1.1  
1.7.1.2  
1.7.1.3  
1.7.1.4  
1.7.1.5  
1.7.1.6  
Features................................................................................................................ 1-1  
MPC8260Õs Architecture Overview .................................................................... 1-4  
MPC603e Core ................................................................................................ 1-5  
System Interface Unit (SIU) ............................................................................ 1-6  
Communications Processor Module (CPM).................................................... 1-6  
Software Compatibility Issues............................................................................. 1-7  
Signals.............................................................................................................. 1-7  
Differences between MPC860 and MPC8260..................................................... 1-9  
Serial Protocol Table............................................................................................ 1-9  
MPC8260 Configurations.................................................................................. 1-10  
Pin Configurations......................................................................................... 1-10  
Serial Performance......................................................................................... 1-10  
MPC8260 Application Examples ...................................................................... 1-11  
Examples of Communication Systems .......................................................... 1-11  
Remote Access Server ............................................................................... 1-11  
Regional Office Router.............................................................................. 1-12  
LAN-to-WAN Bridge Router.................................................................... 1-13  
Cellular Base Station ................................................................................. 1-14  
Telecommunications Switch Controller .................................................... 1-14  
SONET Transmission Controller .............................................................. 1-15  
MOTOROLA  
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CONTENTS  
Paragraph  
Number  
Page  
Number  
Title  
1.7.2  
Bus Configurations.........................................................................................1-15  
Basic System ..............................................................................................1-15  
High-Performance Communication ...........................................................1-16  
High-Performance System Microprocessor ...............................................1-17  
1.7.2.1  
1.7.2.2  
1.7.2.3  
Chapter 2  
PowerPC Processor Core  
2.1  
2.2  
2.2.1  
2.2.2  
2.2.3  
2.2.4  
2.2.4.1  
2.2.4.2  
2.2.4.3  
2.2.5  
Overview ..............................................................................................................2-1  
PowerPC Processor Core Features ......................................................................2-3  
Instruction Unit.................................................................................................2-5  
Instruction Queue and Dispatch Unit ...............................................................2-5  
Branch Processing Unit (BPU).........................................................................2-6  
Independent Execution Units ...........................................................................2-6  
Integer Unit (IU)...........................................................................................2-6  
Load/Store Unit (LSU).................................................................................2-7  
System Register Unit (SRU) ........................................................................2-7  
Completion Unit...............................................................................................2-7  
Memory Subsystem Support ............................................................................2-8  
Memory Management Units (MMUs) .........................................................2-8  
Cache Units ..................................................................................................2-8  
Programming Model.............................................................................................2-8  
Register Set.......................................................................................................2-8  
PowerPC Register Set ..................................................................................2-9  
MPC8260-Specific Registers .....................................................................2-11  
Hardware Implementation-Dependent Register 0 (HID0).....................2-11  
Hardware Implementation-Dependent Register 1 (HID1).....................2-14  
Hardware Implementation-Dependent Register 2 (HID2).....................2-15  
Processor Version Register (PVR).........................................................2-16  
PowerPC Instruction Set and Addressing Modes...........................................2-16  
Calculating Effective Addresses ................................................................2-16  
PowerPC Instruction Set ............................................................................2-16  
MPC8260 Implementation-Specific Instruction Set ..................................2-18  
Cache Implementation........................................................................................2-18  
PowerPC Cache Model...................................................................................2-18  
MPC8260 Implementation-Specific Cache Implementation..........................2-19  
Data Cache .................................................................................................2-19  
Instruction Cache........................................................................................2-21  
Cache Locking............................................................................................2-21  
Entire Cache Locking.............................................................................2-21  
Way Locking..........................................................................................2-21  
Exception Model.................................................................................................2-22  
2.2.6  
2.2.6.1  
2.2.6.2  
2.3  
2.3.1  
2.3.1.1  
2.3.1.2  
2.3.1.2.1  
2.3.1.2.2  
2.3.1.2.3  
2.3.1.2.4  
2.3.2  
2.3.2.1  
2.3.2.2  
2.3.2.3  
2.4  
2.4.1  
2.4.2  
2.4.2.1  
2.4.2.2  
2.4.2.3  
2.4.2.3.1  
2.4.2.3.2  
2.5  
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MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
CONTENTS  
Paragraph  
Number  
Page  
Number  
Title  
2.5.1  
2.5.2  
2.5.3  
2.6  
2.6.1  
2.6.2  
2.7  
PowerPC Exception Model............................................................................2-22  
MPC8260 Implementation-Specific Exception Model..................................2-23  
Exception Priorities........................................................................................2-26  
Memory Management ........................................................................................2-26  
PowerPC MMU Model ..................................................................................2-27  
MPC8260 Implementation-Specific MMU Features.....................................2-28  
Instruction Timing..............................................................................................2-29  
Differences between the MPC8260Õs Core and the PowerPC 603e  
2.8  
Microprocessor...............................................................................................2-30  
Chapter 3  
Memory Map  
Chapter 4  
System Interface Unit (SIU)  
4.1  
4.1.1  
4.1.2  
4.1.3  
4.1.4  
4.1.5  
4.2  
4.2.1  
System Configuration and Protection ..................................................................4-2  
Bus Monitor .....................................................................................................4-3  
Timers Clock....................................................................................................4-4  
Time Counter (TMCNT)..................................................................................4-4  
Periodic Interrupt Timer (PIT).........................................................................4-5  
Software Watchdog Timer ...............................................................................4-6  
Interrupt Controller ..............................................................................................4-7  
Interrupt Configuration ....................................................................................4-8  
Interrupt Source Priorities................................................................................4-9  
SCC, FCC, and MCC Relative Priority .....................................................4-12  
PIT, TMCNT, and IRQ Relative Priority ..................................................4-12  
Highest Priority Interrupt...........................................................................4-13  
Masking Interrupt Sources .............................................................................4-13  
Interrupt Vector Generation and Calculation.................................................4-14  
Port C External Interrupts ..........................................................................4-16  
Programming Model ..........................................................................................4-17  
Interrupt Controller Registers ........................................................................4-17  
SIU Interrupt Configuration Register (SICR)............................................4-17  
SIU Interrupt Priority Register (SIPRR)....................................................4-18  
CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L) .................4-19  
SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L).....................4-21  
SIU Interrupt Mask Registers (SIMR_H and SIMR_L) ............................4-22  
SIU Interrupt Vector Register (SIVEC).....................................................4-23  
SIU External Interrupt Control Register (SIEXR).....................................4-24  
System Configuration and Protection Registers ............................................4-25  
Bus Configuration Register (BCR) ...........................................................4-25  
4.2.2  
4.2.2.1  
4.2.2.2  
4.2.2.3  
4.2.3  
4.2.4  
4.2.4.1  
4.3  
4.3.1  
4.3.1.1  
4.3.1.2  
4.3.1.3  
4.3.1.4  
4.3.1.5  
4.3.1.6  
4.3.1.7  
4.3.2  
4.3.2.1  
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CONTENTS  
Paragraph  
Number  
Page  
Number  
Title  
4.3.2.2  
4.3.2.3  
4.3.2.4  
4.3.2.5  
4.3.2.6  
4.3.2.7  
4.3.2.8  
4.3.2.9  
4.3.2.10  
4.3.2.11  
4.3.2.12  
4.3.2.13  
4.3.2.14  
4.3.2.15  
4.3.2.16  
4.3.3  
60x Bus Arbiter Configuration Register (PPC_ACR) ...............................4-28  
60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL) .............4-28  
Local Bus Arbiter Configuration Register (LCL_ACR)............................4-29  
Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL)...4-30  
SIU Module Configuration Register (SIUMCR) .......................................4-31  
Internal Memory Map Register (IMMR) ...................................................4-34  
System Protection Control Register (SYPCR)...........................................4-35  
Software Service Register (SWSR)............................................................4-36  
60x Bus Transfer Error Status and Control Register 1 (TESCR1).............4-36  
60x Bus Transfer Error Status and Control Register 2 (TESCR2).............4-37  
Local Bus Transfer Error Status and Control Register 1 (L_TESCR1).....4-38  
Local Bus Transfer Error Status and Control Register 2 (L_TESCR2).....4-39  
Time Counter Status and Control Register (TMCNTSC)..........................4-40  
Time Counter Register (TMCNT)..............................................................4-41  
Time Counter Alarm Register (TMCNTAL) .............................................4-41  
Periodic Interrupt Registers............................................................................4-42  
Periodic Interrupt Status and Control Register (PISCR)............................4-42  
Periodic Interrupt Timer Count Register (PITC) .......................................4-43  
Periodic Interrupt Timer Register (PITR) ..................................................4-44  
SIU Pin Multiplexing..........................................................................................4-44  
4.3.3.1  
4.3.3.2  
4.3.3.3  
4.4  
Chapter 5  
Reset  
5.1  
Reset Causes.........................................................................................................5-1  
Reset Actions....................................................................................................5-2  
Power-On Reset Flow.......................................................................................5-2  
HRESET Flow .................................................................................................5-3  
SRESET Flow...................................................................................................5-3  
Reset Status Register (RSR).................................................................................5-4  
Reset Mode Register (RMR)................................................................................5-5  
Reset Configuration..............................................................................................5-6  
Hard Reset Configuration Word.......................................................................5-8  
Hard Reset Configuration Examples................................................................5-9  
Single MPC8260 with Default Configuration..............................................5-9  
Single MPC8260 Configured from Boot EPROM.....................................5-10  
Multiple MPC8260s Configured from Boot EPROM................................5-10  
Multiple MPC8260s in a System with No EPROM...................................5-12  
5.1.1  
5.1.2  
5.1.3  
5.1.4  
5.2  
5.3  
5.4  
5.4.1  
5.4.2  
5.4.2.1  
5.4.2.2  
5.4.2.3  
5.4.2.4  
Chapter 6  
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MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
CONTENTS  
Title  
Paragraph  
Number  
Page  
Number  
External Signals  
6.1  
6.2  
Functional Pinout .................................................................................................6-1  
Signal Descriptions ..............................................................................................6-2  
Chapter 7  
60x Signals  
7.1  
7.2  
7.2.1  
Signal Configuration ............................................................................................7-2  
Signal Descriptions ..............................................................................................7-3  
Address Bus Arbitration Signals......................................................................7-3  
Bus Request (BR)ÑOutput .........................................................................7-3  
Address Bus Request (BR)ÑOutput .......................................................7-3  
Address Bus Request (BR)ÑInput..........................................................7-4  
Bus Grant (BG) ............................................................................................7-4  
Bus Grant (BG)ÑInput............................................................................7-4  
Bus Grant (BG)ÑOutput.........................................................................7-5  
Address Bus Busy (ABB) ............................................................................7-5  
Address Bus Busy (ABB)ÑOutput.........................................................7-5  
Address Bus Busy (ABB)ÑInput............................................................7-6  
Address Transfer Start Signal ..........................................................................7-6  
Transfer Start (TS) .......................................................................................7-6  
Transfer Start (TS)ÑOutput....................................................................7-6  
Transfer Start (TS)ÑInput...........................................................................7-6  
Address Transfer Signals .................................................................................7-7  
Address Bus (A[0Ð31]) ................................................................................7-7  
Address Bus (A[0Ð31])ÑOutput.............................................................7-7  
Address Bus (A[0Ð31])ÑInput................................................................7-7  
Address Transfer Attribute Signals..................................................................7-7  
Transfer Type (TT[0Ð4])..............................................................................7-8  
Transfer Type (TT[0Ð4])ÑOutput...........................................................7-8  
Transfer Type (TT[0Ð4])ÑInput .............................................................7-8  
Transfer Size (TSIZ[0Ð3]) ...........................................................................7-8  
Transfer Burst (TBST).................................................................................7-8  
Global (GBL) ...............................................................................................7-9  
Global (GBL)ÑOutput............................................................................7-9  
Global (GBL)ÑInput...............................................................................7-9  
Caching-Inhibited (CI)ÑOutput..................................................................7-9  
Write-Through (WT)ÑOutput ....................................................................7-9  
Address Transfer Termination Signals...........................................................7-10  
Address Acknowledge (AACK) ................................................................7-10  
Address Acknowledge (AACK)ÑOutput .............................................7-10  
Address Acknowledge (AACK)ÑInput................................................7-10  
7.2.1.1  
7.2.1.1.1  
7.2.1.1.2  
7.2.1.2  
7.2.1.2.1  
7.2.1.2.2  
7.2.1.3  
7.2.1.3.1  
7.2.1.3.2  
7.2.2  
7.2.2.1  
7.2.2.1.1  
7.2.2.2  
7.2.3  
7.2.3.1  
7.2.3.1.1  
7.2.3.1.2  
7.2.4  
7.2.4.1  
7.2.4.1.1  
7.2.4.1.2  
7.2.4.2  
7.2.4.3  
7.2.4.4  
7.2.4.4.1  
7.2.4.4.2  
7.2.4.5  
7.2.4.6  
7.2.5  
7.2.5.1  
7.2.5.1.1  
7.2.5.1.2  
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CONTENTS  
Paragraph  
Number  
Page  
Number  
Title  
7.2.5.2  
Address Retry (ARTRY)............................................................................7-11  
Address Retry (ARTRY)ÑOutput.........................................................7-11  
Address Retry (ARTRY)ÑInput ...........................................................7-11  
Data Bus Arbitration Signals..........................................................................7-12  
Data Bus Grant (DBG)...............................................................................7-12  
Data Bus Grant (DBG)ÑInput ..............................................................7-12  
Data Bus Grant (DBG)ÑOutput............................................................7-12  
Data Bus Busy (DBB) ................................................................................7-13  
Data Bus Busy (DBB)ÑOutput.............................................................7-13  
Data Bus Busy (DBB)ÑInput................................................................7-13  
Data Transfer Signals .....................................................................................7-13  
Data Bus (D[0Ð63])....................................................................................7-13  
Data Bus (D[0Ð63])ÑOutput.................................................................7-14  
Data Bus (D[0Ð63])ÑInput ...................................................................7-14  
Data Bus Parity (DP[0Ð7]) .........................................................................7-14  
Data Bus Parity (DP[0Ð7])ÑOutput......................................................7-14  
Data Bus Parity (DP[0Ð7])ÑInput.........................................................7-15  
Data Transfer Termination Signals ................................................................7-15  
Transfer Acknowledge (TA) ......................................................................7-15  
Transfer Acknowledge (TA)ÑInput......................................................7-15  
Transfer Acknowledge (TA)ÑOutput...................................................7-16  
Transfer Error Acknowledge (TEA) ..........................................................7-16  
Transfer Error Acknowledge (TEA)ÑInput..........................................7-16  
Transfer Error Acknowledge (TEA)ÑOutput .......................................7-17  
Partial Data Valid Indication (PSDVAL)...................................................7-17  
Partial Data Valid (PSDVAL)ÑInput ...................................................7-17  
Partial Data Valid (PSDVAL)ÑOutput.................................................7-18  
7.2.5.2.1  
7.2.5.2.2  
7.2.6  
7.2.6.1  
7.2.6.1.1  
7.2.6.1.2  
7.2.6.2  
7.2.6.2.1  
7.2.6.2.2  
7.2.7  
7.2.7.1  
7.2.7.1.1  
7.2.7.1.2  
7.2.7.2  
7.2.7.2.1  
7.2.7.2.2  
7.2.8  
7.2.8.1  
7.2.8.1.1  
7.2.8.1.2  
7.2.8.2  
7.2.8.2.1  
7.2.8.2.2  
7.2.8.3  
7.2.8.3.1  
7.2.8.3.2  
Chapter 8  
The 60x Bus  
8.1  
8.2  
8.2.1  
8.2.2  
8.3  
8.3.1  
8.3.2  
8.4  
8.4.1  
8.4.2  
8.4.3  
Terminology .........................................................................................................8-1  
Bus Configuration.................................................................................................8-2  
Single MPC8260 Bus Mode.............................................................................8-2  
60x-Compatible Bus Mode...............................................................................8-3  
60x Bus Protocol Overview..................................................................................8-4  
Arbitration Phase..............................................................................................8-5  
Address Pipelining and Split-Bus Transactions ...............................................8-7  
Address Tenure Operations ..................................................................................8-7  
Address Arbitration ..........................................................................................8-7  
Address Pipelining............................................................................................8-9  
Address Transfer Attribute Signals ................................................................8-10  
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CONTENTS  
Paragraph  
Number  
Page  
Number  
Title  
8.4.3.1  
8.4.3.2  
8.4.3.3  
8.4.3.4  
8.4.3.5  
8.4.3.6  
8.4.3.7  
8.4.3.8  
8.4.4  
8.4.4.1  
8.4.4.2  
8.4.5  
8.5  
8.5.1  
8.5.2  
8.5.3  
8.5.4  
8.5.5  
8.5.6  
8.6  
Transfer Type Signal (TT[0Ð4]) Encoding ................................................8-10  
Transfer Code Signals TC[0Ð2] .................................................................8-13  
TBST and TSIZ[0Ð3] Signals and Size of Transfer...................................8-13  
Burst Ordering During Data Transfers.......................................................8-14  
Effect of Alignment on Data Transfers......................................................8-14  
Effect of Port Size on Data Transfers ........................................................8-16  
60x-Compatible Bus ModeÑSize Calculation..........................................8-19  
Extended Transfer Mode............................................................................8-20  
Address Transfer Termination .......................................................................8-23  
Address Retried with ARTRY ...................................................................8-23  
Address Tenure Timing Configuration......................................................8-25  
Pipeline Control .............................................................................................8-26  
Data Tenure Operations .....................................................................................8-26  
Data Bus Arbitration ......................................................................................8-26  
Data Streaming Mode ....................................................................................8-27  
Data Bus Transfers and Normal Termination ................................................8-27  
Effect of ARTRY Assertion on Data Transfer and Arbitration .....................8-28  
Port Size Data Bus Transfers and PSDVAL Termination .............................8-28  
Data Bus Termination by Assertion of TEA..................................................8-30  
Memory CoherencyÑMEI Protocol..................................................................8-31  
Processor State Signals.......................................................................................8-32  
Support for the lwarx/stwcx. Instruction Pair ................................................8-33  
TLBISYNC Input...........................................................................................8-33  
Little-Endian Mode ............................................................................................8-33  
8.7  
8.7.1  
8.7.2  
8.8  
Chapter 9  
Clocks and Power Control  
9.1  
9.2  
9.3  
9.4  
9.4.1  
9.4.2  
9.5  
9.6  
9.6.1  
9.7  
Clock Unit ............................................................................................................9-1  
Clock Configuration.............................................................................................9-2  
External Clock Inputs...........................................................................................9-5  
Main PLL .............................................................................................................9-5  
PLL Block Diagram.........................................................................................9-5  
Skew Elimination.............................................................................................9-6  
Clock Dividers......................................................................................................9-6  
The MPC8260Õs Internal Clock Signals...............................................................9-6  
General System Clocks ....................................................................................9-7  
PLL Pins...............................................................................................................9-7  
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Paragraph  
Number  
Page  
Number  
Title  
9.8  
9.9  
9.10  
System Clock Control Register (SCCR) ..............................................................9-8  
System Clock Mode Register (SCMR) ................................................................9-9  
Basic Power Structure ........................................................................................9-10  
Chapter 10  
Memory Controller  
10.1  
10.2  
Features...............................................................................................................10-3  
Basic Architecture ..............................................................................................10-5  
Address and Address Space Checking ...........................................................10-8  
Page Hit Checking..........................................................................................10-9  
Error Checking and Correction (ECC)...........................................................10-9  
Parity Generation and Checking.....................................................................10-9  
Transfer Error Acknowledge (TEA) Generation............................................10-9  
Machine Check Interrupt (MCP) Generation.................................................10-9  
Data Buffer Controls (BCTLx) ....................................................................10-10  
Atomic Bus Operation..................................................................................10-10  
Data Pipelining ............................................................................................10-10  
External Memory Controller Support...........................................................10-11  
External Address Latch Enable Signal (ALE)..............................................10-11  
ECC/Parity Byte Select (PBSE)...................................................................10-11  
Partial Data Valid Indication (PSDVAL).....................................................10-12  
Register Descriptions........................................................................................10-13  
Base Registers (BRx) ...................................................................................10-14  
Option Registers (ORx)................................................................................10-16  
60x SDRAM Mode Register (PSDMR).......................................................10-21  
Local Bus SDRAM Mode Register (LSDMR) ............................................10-24  
Machine A/B/C Mode Registers (MxMR)...................................................10-26  
Memory Data Register (MDR).....................................................................10-28  
Memory Address Register (MAR) ...............................................................10-29  
60x Bus-Assigned UPM Refresh Timer (PURT).........................................10-30  
Local Bus-Assigned UPM Refresh Timer (LURT)......................................10-30  
60x Bus-Assigned SDRAM Refresh Timer (PSRT)....................................10-31  
Local Bus-Assigned SDRAM Refresh Timer (LSRT).................................10-32  
Memory Refresh Timer Prescaler Register (MPTPR) .................................10-32  
60x Bus Error Status and Control Registers (TESCRx)...............................10-33  
Local Bus Error Status and Control Registers (L_TESCRx) .......................10-33  
SDRAM Machine.............................................................................................10-33  
Supported SDRAM Configurations .............................................................10-35  
SDRAM Power-On Initialization.................................................................10-35  
JEDEC-Standard SDRAM Interface Commands.........................................10-35  
Page-Mode Support and Pipeline Accesses .................................................10-36  
10.2.1  
10.2.2  
10.2.3  
10.2.4  
10.2.5  
10.2.6  
10.2.7  
10.2.8  
10.2.9  
10.2.10  
10.2.11  
10.2.12  
10.2.13  
10.3  
10.3.1  
10.3.2  
10.3.3  
10.3.4  
10.3.5  
10.3.6  
10.3.7  
10.3.8  
10.3.9  
10.3.10  
10.3.11  
10.3.12  
10.3.13  
10.3.14  
10.4  
10.4.1  
10.4.2  
10.4.3  
10.4.4  
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Paragraph  
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Title  
10.4.5  
10.4.5.1  
10.4.6  
Bank Interleaving ........................................................................................10-36  
SDRAM Address Multiplexing (SDAM and BSMA) .............................10-37  
SDRAM Device-Specific Parameters..........................................................10-38  
Precharge-to-Activate Interval.................................................................10-38  
Activate to Read/Write Interval ...............................................................10-39  
Column Address to First Data OutÑCAS Latency.................................10-40  
Last Data Out to Precharge ......................................................................10-40  
Last Data In to PrechargeÑWrite Recovery ...........................................10-41  
Refresh Recovery Interval (RFRC)..........................................................10-41  
External Address Multiplexing Signal.....................................................10-41  
External Address and Command Buffers (BUFCMD)............................10-42  
SDRAM Interface Timing............................................................................10-42  
SDRAM Read/Write Transactions...............................................................10-46  
SDRAM Mode-Set Command Timing ........................................................10-46  
SDRAM Refresh..........................................................................................10-47  
SDRAM Refresh Timing .............................................................................10-47  
SDRAM Configuration Examples ...............................................................10-48  
SDRAM Configuration Example (Page-Based Interleaving)..................10-48  
SDRAM Configuration Example (Bank-Based Interleaving) .....................10-50  
General-Purpose Chip-Select Machine (GPCM).............................................10-51  
Timing Configuration...................................................................................10-52  
Chip-Select Assertion Timing..................................................................10-53  
Chip-Select and Write Enable Deassertion Timing .................................10-54  
Relaxed Timing........................................................................................10-55  
Output Enable (OE) Timing.....................................................................10-57  
Programmable Wait State Configuration.................................................10-57  
Extended Hold Time on Read Accesses ..................................................10-57  
External Access Termination .......................................................................10-60  
Boot Chip-Select Operation.........................................................................10-61  
Differences between MPC8xxÕs GPCM and MPC8260Õs GPCM...............10-62  
User-Programmable Machines (UPMs)...........................................................10-62  
Requests .......................................................................................................10-64  
Memory Access Requests ........................................................................10-65  
UPM Refresh Timer Requests .................................................................10-65  
Software RequestsÑrun Command.........................................................10-66  
Exception Requests..................................................................................10-66  
Programming the UPMs...............................................................................10-66  
Clock Timing ...............................................................................................10-67  
The RAM Array...........................................................................................10-69  
RAM Words.............................................................................................10-70  
Chip-Select Signals (CxTx) .................................................................10-74  
Byte-Select Signals (BxTx) .................................................................10-75  
General-Purpose Signals (GxTx, GOx) ...............................................10-76  
10.4.6.1  
10.4.6.2  
10.4.6.3  
10.4.6.4  
10.4.6.5  
10.4.6.6  
10.4.6.7  
10.4.6.8  
10.4.7  
10.4.8  
10.4.9  
10.4.10  
10.4.11  
10.4.12  
10.4.12.1  
10.4.13  
10.5  
10.5.1  
10.5.1.1  
10.5.1.2  
10.5.1.3  
10.5.1.4  
10.5.1.5  
10.5.1.6  
10.5.2  
10.5.3  
10.5.4  
10.6  
10.6.1  
10.6.1.1  
10.6.1.2  
10.6.1.3  
10.6.1.4  
10.6.2  
10.6.3  
10.6.4  
10.6.4.1  
10.6.4.1.1  
10.6.4.1.2  
10.6.4.1.3  
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CONTENTS  
Paragraph  
Number  
Page  
Number  
Title  
10.6.4.1.4  
10.6.4.1.5  
10.6.4.2  
10.6.4.3  
10.6.4.4  
10.6.4.5  
10.6.4.6  
10.6.5  
10.6.6  
10.7  
10.7.0.1  
10.8  
10.8.1  
10.8.2  
10.9  
10.9.1  
10.9.2  
Loop Control ........................................................................................10-76  
Repeat Execution of Current RAM Word (REDO) ............................10-76  
Address Multiplexing...............................................................................10-77  
Data Valid and Data Sample Control.......................................................10-77  
Signals Negation.......................................................................................10-78  
The Wait Mechanism ...............................................................................10-78  
Extended Hold Time on Read Accesses ..................................................10-79  
UPM DRAM Configuration Example..........................................................10-79  
Differences between MPC8xx UPM and MPC8260 UPM ..........................10-80  
Memory System Interface Example Using UPM.............................................10-81  
EDO Interface Example ...........................................................................10-92  
Handling Devices with Slow or Variable Access Times................................10-100  
Hierarchical Bus Interface Example...........................................................10-100  
Slow Devices Example...............................................................................10-100  
External Master Support (60x-Compatible Mode).........................................10-101  
60x-Compatible External Masters..............................................................10-101  
MPC8260-Type External Masters..............................................................10-101  
Extended Controls in 60x-Compatible Mode.............................................10-101  
Using BNKSEL SIgnals in Single-MPC8260 Bus Mode ..........................10-102  
Address Incrementing for External Bursting Masters................................10-102  
External Masters Timing............................................................................10-102  
Example of External Master Using the SDRAM Machine ....................10-104  
10.9.3  
10.9.4  
10.9.5  
10.9.6  
10.9.6.1  
Chapter 11  
Secondary (L2) Cache Support  
11.1  
L2 Cache Configurations....................................................................................11-1  
Copy-Back Mode............................................................................................11-1  
Write-Through Mode......................................................................................11-2  
ECC/Parity Mode ...........................................................................................11-4  
L2 Cache Interface Parameters...........................................................................11-7  
System Requirements When Using the L2 Cache Interface...............................11-7  
L2 Cache Operation............................................................................................11-7  
Timing Example .................................................................................................11-8  
11.1.1  
11.1.2  
11.1.3  
11.2  
11.3  
11.4  
11.5  
Chapter 12  
IEEE 1149.1 Test Access Port  
12.1  
12.2  
12.3  
12.4  
Overview ............................................................................................................12-1  
TAP Controller ...................................................................................................12-2  
Boundary Scan Register .....................................................................................12-3  
Instruction Register...........................................................................................12-28  
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Paragraph  
Number  
Page  
Number  
Title  
12.5  
12.6  
MPC8260 Restrictions .....................................................................................12-30  
Nonscan Chain Operation ................................................................................12-30  
Chapter 13  
Communications Processor Module Overview  
13.1  
13.2  
13.3  
Features ..............................................................................................................13-1  
MPC8260 Serial Configurations........................................................................13-3  
Communications Processor (CP) .......................................................................13-4  
Features ..........................................................................................................13-4  
CP Block Diagram .........................................................................................13-4  
PowerPC Core Interface.................................................................................13-6  
Peripheral Interface ........................................................................................13-6  
Execution from RAM.....................................................................................13-7  
RISC Controller Configuration Register (RCCR) .........................................13-7  
RISC Time-Stamp Control Register (RTSCR)..............................................13-9  
RISC Time-Stamp Register (RTSR)............................................................13-10  
RISC Microcode Revision Number .............................................................13-10  
Command Set...................................................................................................13-11  
CP Command Register (CPCR)...................................................................13-11  
CP Commands..........................................................................................13-13  
Command Register Example........................................................................13-15  
Command Execution Latency......................................................................13-15  
Dual-Port RAM................................................................................................13-15  
Buffer Descriptors (BDs) .............................................................................13-17  
Parameter RAM ...........................................................................................13-17  
RISC Timer Tables...........................................................................................13-18  
RISC Timer Table Parameter RAM.............................................................13-19  
RISC Timer Command Register (TM_CMD) .............................................13-20  
RISC Timer Table Entries............................................................................13-21  
RISC Timer Event Register (RTER)/Mask Register (RTMR) ....................13-21  
set timer Command ......................................................................................13-22  
RISC Timer Initialization Sequence ............................................................13-22  
RISC Timer Initialization Example .............................................................13-22  
RISC Timer Interrupt Handling ...................................................................13-23  
RISC Timer Table Scan Algorithm..............................................................13-23  
Using the RISC Timers to Track CP Loading .............................................13-24  
13.3.1  
13.3.2  
13.3.3  
13.3.4  
13.3.5  
13.3.6  
13.3.7  
13.3.8  
13.3.9  
13.4  
13.4.1  
13.4.1.1  
13.4.2  
13.4.3  
13.5  
13.5.1  
13.5.2  
13.6  
13.6.1  
13.6.2  
13.6.3  
13.6.4  
13.6.5  
13.6.6  
13.6.7  
13.6.8  
13.6.9  
13.6.10  
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Number  
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Number  
Title  
Chapter 14  
Serial Interface with Time-Slot Assigner  
14.1  
14.2  
14.3  
14.4  
Features...............................................................................................................14-3  
Overview ............................................................................................................14-4  
Enabling Connections to TSA............................................................................14-7  
Serial Interface RAM..........................................................................................14-8  
One Multiplexed Channel with Static Frames................................................14-9  
One Multiplexed Channel with Dynamic Frames..........................................14-9  
Programming SIx RAM Entries...................................................................14-10  
SIx RAM Programming Example ................................................................14-13  
Static and Dynamic Routing.........................................................................14-14  
Serial Interface Registers..................................................................................14-17  
SI Global Mode Registers (SIxGMR) ..........................................................14-17  
SI Mode Registers (SIxMR).........................................................................14-17  
SIx RAM Shadow Address Registers (SIxRSR)..........................................14-23  
SI Command Register (SIxCMDR)..............................................................14-24  
SI Status Registers (SIxSTR) .......................................................................14-25  
Serial Interface IDL Interface Support .............................................................14-25  
IDL Interface Example.................................................................................14-26  
IDL Interface Programming .........................................................................14-29  
Serial Interface GCI Support............................................................................14-31  
SI GCI Activation/Deactivation Procedure..................................................14-33  
Serial Interface GCI Programming...............................................................14-33  
Normal Mode GCI Programming.............................................................14-33  
SCIT Programming ..................................................................................14-33  
14.4.1  
14.4.2  
14.4.3  
14.4.4  
14.4.5  
14.5  
14.5.1  
14.5.2  
14.5.3  
14.5.4  
14.5.5  
14.6  
14.6.1  
14.6.2  
14.7  
14.7.1  
14.7.2  
14.7.2.1  
14.7.2.2  
Chapter 15  
CPM Multiplexing  
15.1  
15.2  
15.3  
15.4  
15.4.1  
15.4.2  
15.4.3  
15.4.4  
15.4.5  
15.4.6  
Features...............................................................................................................15-2  
Enabling Connections to TSA or NMSI.............................................................15-3  
NMSI Configuration...........................................................................................15-4  
CMX Registers ...................................................................................................15-6  
CMX UTOPIA Address Register (CMXUAR)..............................................15-7  
CMX SI1 Clock Route Register (CMXSI1CR) ...........................................15-10  
CMX SI2 Clock Route Register (CMXSI2CR) ...........................................15-11  
CMX FCC Clock Route Register (CMXFCR).............................................15-12  
CMX SCC Clock Route Register (CMXSCR).............................................15-14  
CMX SMC Clock Route Register (CMXSMR)...........................................15-17  
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Paragraph  
Number  
Page  
Number  
Title  
Chapter 16  
Baud-Rate Generators (BRGs)  
16.1  
16.2  
16.3  
BRG Configuration Registers 1Ð8 (BRGCx).....................................................16-2  
Autobaud Operation on a UART .......................................................................16-4  
UART Baud Rate Examples ..............................................................................16-5  
Chapter 17  
Timers  
17.1  
17.2  
Features ..............................................................................................................17-2  
General-Purpose Timer Units.............................................................................17-2  
Cascaded Mode..............................................................................................17-3  
Timer Global Configuration Registers (TGCR1 and TGCR2)......................17-4  
Timer Mode Registers (TMR1ÐTMR4).........................................................17-6  
Timer Reference Registers (TRR1ÐTRR4)....................................................17-7  
Timer Capture Registers (TCR1ÐTCR4) .......................................................17-8  
Timer Counters (TCN1ÐTCN4).....................................................................17-8  
Timer Event Registers (TER1ÐTER4)...........................................................17-8  
17.2.1  
17.2.2  
17.2.3  
17.2.4  
17.2.5  
17.2.6  
17.2.7  
Chapter 18  
SDMA Channels and IDMA Emulation  
18.1  
18.2  
18.2.1  
18.2.2  
18.2.3  
18.2.4  
18.3  
18.4  
18.5  
SDMA Bus Arbitration and Bus Transfers ........................................................18-2  
SDMA Registers ................................................................................................18-3  
SDMA Status Register (SDSR) .....................................................................18-3  
SDMA Mask Register (SDMR).....................................................................18-4  
SDMA Transfer Error Address Registers (PDTEA and LDTEA).................18-4  
SDMA Transfer Error MSNUM Registers (PDTEM and LDTEM) .............18-4  
IDMA Emulation................................................................................................18-5  
IDMA Features...................................................................................................18-5  
IDMA Transfers.................................................................................................18-6  
Memory-to-Memory Transfers ......................................................................18-6  
External Request Mode..............................................................................18-8  
Normal Mode .............................................................................................18-9  
Memory to/from Peripheral Transfers ...........................................................18-9  
Dual-Address Transfers ...........................................................................18-10  
Peripheral to Memory ..........................................................................18-10  
Memory to Peripheral ..........................................................................18-10  
Single Address (Fly-By) Transfers ..........................................................18-11  
Peripheral-to-Memory Fly-By Transfers .............................................18-11  
Memory-to-Peripheral Fly-By Transfers .............................................18-11  
18.5.1  
18.5.1.1  
18.5.1.2  
18.5.2  
18.5.2.1  
18.5.2.1.1  
18.5.2.1.2  
18.5.2.2  
18.5.2.2.1  
18.5.2.2.2  
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Number  
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Number  
Title  
18.5.3  
18.6  
18.7  
18.7.1  
18.7.1.1  
18.7.1.2  
18.7.2  
18.8  
18.8.1  
18.8.2  
18.8.2.1  
18.8.2.2  
18.8.2.3  
18.8.3  
18.8.4  
18.8.5  
18.9  
Controlling 60x Bus Bandwidth...................................................................18-12  
IDMA Priorities................................................................................................18-12  
IDMA Interface Signals....................................................................................18-12  
DREQx and DACKx....................................................................................18-13  
Level-Sensitive Mode...............................................................................18-13  
Edge-Sensitive Mode ...............................................................................18-13  
DONEx.........................................................................................................18-14  
IDMA Operation...............................................................................................18-14  
Auto Buffer and Buffer Chaining.................................................................18-15  
IDMAx Parameter RAM ..............................................................................18-16  
DMA Channel Mode (DCM) ...................................................................18-18  
Data Transfer Types as Programmed in DCM.........................................18-20  
Programming DTS and STS.....................................................................18-20  
IDMA Performance......................................................................................18-22  
IDMA Event Register (IDSR) and Mask Register (IDMR).........................18-22  
IDMA BDs ...................................................................................................18-23  
IDMA Commands ............................................................................................18-26  
start_idma Command....................................................................................18-26  
stop_idma Command....................................................................................18-26  
IDMA Bus Exceptions......................................................................................18-27  
Externally Recognizing IDMA Operand Transfers......................................18-27  
Programming the Parallel I/O Registers...........................................................18-28  
IDMA Programming Examples........................................................................18-29  
Peripheral-to-Memory Mode (60x Bus to Local Bus)ÑIDMA2.................18-29  
Memory-to-Peripheral Fly-By Mode (Both on 60x Bus)ÑIDMA3 ............18-30  
18.9.1  
18.9.2  
18.10  
18.10.1  
18.11  
18.12  
18.12.1  
18.12.2  
Chapter 19  
Serial Communications Controllers (SCCs)  
19.1  
Features...............................................................................................................19-2  
The General SCC Mode Registers (GSMR1ÐGSMR4) .................................19-3  
Protocol-Specific Mode Register (PSMR) .....................................................19-9  
Data Synchronization Register (DSR)............................................................19-9  
Transmit-on-Demand Register (TODR).........................................................19-9  
SCC Buffer Descriptors (BDs).........................................................................19-10  
SCC Parameter RAM .......................................................................................19-13  
SCC Base Addresses ....................................................................................19-15  
Function Code Registers (RFCR and TFCR)...............................................19-15  
Handling SCC Interrupts..............................................................................19-16  
Initializing the SCCs.....................................................................................19-17  
Controlling SCC Timing with RTS, CTS, and CD ......................................19-18  
Synchronous Protocols.............................................................................19-18  
19.1.1  
19.1.2  
19.1.3  
19.1.4  
19.2  
19.3  
19.3.1  
19.3.2  
19.3.3  
19.3.4  
19.3.5  
19.3.5.1  
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19.3.5.2  
19.3.6  
19.3.6.1  
19.3.7  
Asynchronous Protocols ..........................................................................19-21  
Digital Phase-Locked Loop (DPLL) Operation...........................................19-22  
Encoding Data with a DPLL....................................................................19-24  
Clock Glitch Detection.................................................................................19-26  
Reconfiguring the SCCs...............................................................................19-26  
General Reconfiguration Sequence for an SCC Transmitter...................19-26  
Reset Sequence for an SCC Transmitter..................................................19-27  
General Reconfiguration Sequence for an SCC Receiver .......................19-27  
Reset Sequence for an SCC Receiver ......................................................19-27  
Switching Protocols .................................................................................19-27  
Saving Power ...............................................................................................19-27  
19.3.8  
19.3.8.1  
19.3.8.2  
19.3.8.3  
19.3.8.4  
19.3.8.5  
19.3.9  
Chapter 20  
SCC UART Mode  
20.1  
20.2  
20.3  
20.4  
20.5  
20.6  
20.7  
20.8  
Features ..............................................................................................................20-2  
Normal Asynchronous Mode .............................................................................20-3  
Synchronous Mode.............................................................................................20-3  
SCC UART Parameter RAM.............................................................................20-4  
Data-Handling Methods: Character- or Message-Based....................................20-5  
Error and Status Reporting.................................................................................20-6  
SCC UART Commands .....................................................................................20-6  
Multidrop Systems and Address Recognition....................................................20-7  
Receiving Control Characters ............................................................................20-8  
Hunt Mode (Receiver)......................................................................................20-10  
Inserting Control Characters into the Transmit Data Stream...........................20-10  
Sending a Break (Transmitter).........................................................................20-11  
Sending a Preamble (Transmitter)....................................................................20-11  
Fractional Stop Bits (Transmitter)....................................................................20-11  
Handling Errors in the SCC UART Controller................................................20-12  
UART Mode Register (PSMR)........................................................................20-13  
SCC UART Receive Buffer Descriptor (RxBD) .............................................20-15  
SCC UART Transmit Buffer Descriptor (TxBD)............................................20-18  
SCC UART Event Register (SCCE) and Mask Register (SCCM) ..................20-19  
SCC UART Status Register (SCCS)................................................................20-21  
SCC UART Programming Example ................................................................20-22  
S-Records Loader Application.........................................................................20-23  
20.9  
20.10  
20.11  
20.12  
20.13  
20.14  
20.15  
20.16  
20.17  
20.18  
20.19  
20.20  
20.21  
20.22  
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Number  
Page  
Number  
Title  
Chapter 21  
SCC HDLC Mode  
21.1  
21.2  
21.3  
21.4  
21.5  
21.6  
21.7  
21.8  
SCC HDLC Features ..........................................................................................21-2  
SCC HDLC Channel Frame Transmission.........................................................21-2  
SCC HDLC Channel Frame Reception..............................................................21-3  
SCC HDLC Parameter RAM .............................................................................21-3  
Programming the SCC in HDLC Mode .............................................................21-5  
SCC HDLC Commands .....................................................................................21-5  
Handling Errors in the SCC HDLC Controller ..................................................21-6  
HDLC Mode Register (PSMR) ..........................................................................21-7  
SCC HDLC Receive Buffer Descriptor (RxBD)................................................21-8  
SCC HDLC Transmit Buffer Descriptor (TxBD) ............................................21-11  
HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)......................21-12  
SCC HDLC Status Register (SCCS) ................................................................21-14  
SCC HDLC Programming Examples...............................................................21-14  
SCC HDLC Programming Example #1 .......................................................21-15  
SCC HDLC Programming Example #2 .......................................................21-16  
HDLC Bus Mode with Collision Detection .....................................................21-17  
HDLC Bus Features .....................................................................................21-19  
Accessing the HDLC Bus.............................................................................21-19  
Increasing Performance................................................................................21-20  
Delayed RTS Mode......................................................................................21-21  
Using the Time-Slot Assigner (TSA)...........................................................21-22  
HDLC Bus Protocol Programming ..............................................................21-23  
Programming GSMR and PSMR for the HDLC Bus Protocol................21-23  
HDLC Bus Controller Programming Example ........................................21-23  
21.9  
21.10  
21.11  
21.12  
21.13  
21.13.1  
21.13.2  
21.14  
21.14.1  
21.14.2  
21.14.3  
21.14.4  
21.14.5  
21.14.6  
21.14.6.1  
21.14.6.2  
Chapter 22  
SCC BISYNC Mode  
22.1  
22.2  
22.3  
22.4  
22.5  
22.6  
22.7  
22.8  
22.9  
22.10  
22.11  
Features...............................................................................................................22-2  
SCC BISYNC Channel Frame Transmission.....................................................22-2  
SCC BISYNC Channel Frame Reception ..........................................................22-3  
SCC BISYNC Parameter RAM..........................................................................22-3  
SCC BISYNC Commands..................................................................................22-5  
SCC BISYNC Control Character Recognition...................................................22-6  
BISYNC SYNC Register (BSYNC)...................................................................22-7  
SCC BISYNC DLE Register (BDLE)................................................................22-8  
Sending and Receiving the Synchronization Sequence......................................22-9  
Handling Errors in the SCC BISYNC................................................................22-9  
BISYNC Mode Register (PSMR).....................................................................22-10  
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Title  
22.12  
22.13  
22.14  
22.15  
22.16  
22.17  
SCC BISYNC Receive BD (RxBD) ................................................................22-12  
SCC BISYNC Transmit BD (TxBD)...............................................................22-14  
BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)..............22-15  
SCC Status Registers (SCCS) ..........................................................................22-16  
Programming the SCC BISYNC Controller ....................................................22-17  
SCC BISYNC Programming Example ............................................................22-18  
Chapter 23  
SCC Transparent Mode  
23.1  
23.2  
23.3  
23.4  
Features ..............................................................................................................23-1  
SCC Transparent Channel Frame Transmission Process...................................23-2  
SCC Transparent Channel Frame Reception Process ........................................23-2  
Achieving Synchronization in Transparent Mode .............................................23-3  
Synchronization in NMSI Mode ....................................................................23-3  
In-Line Synchronization Pattern ................................................................23-3  
External Synchronization Signals ..............................................................23-4  
External Synchronization Example........................................................23-4  
Transparent Mode without Explicit Synchronization ................................23-5  
Synchronization and the TSA ........................................................................23-5  
Inline Synchronization Pattern...................................................................23-6  
Inherent Synchronization ...........................................................................23-6  
End of Frame Detection .................................................................................23-6  
CRC Calculation in Transparent Mode..............................................................23-6  
SCC Transparent Parameter RAM.....................................................................23-6  
SCC Transparent Commands.............................................................................23-7  
Handling Errors in the Transparent Controller ..................................................23-8  
Transparent Mode and the PSMR......................................................................23-9  
SCC Transparent Receive Buffer Descriptor (RxBD).......................................23-9  
SCC Transparent Transmit Buffer Descriptor (TxBD)....................................23-10  
SCC Transparent Event Register (SCCE)/Mask Register (SCCM).................23-12  
SCC Status Register in Transparent Mode (SCCS) .........................................23-13  
SCC2 Transparent Programming Example......................................................23-13  
23.4.1  
23.4.1.1  
23.4.1.2  
23.4.1.2.1  
23.4.1.3  
23.4.2  
23.4.2.1  
23.4.2.2  
23.4.3  
23.5  
23.6  
23.7  
23.8  
23.9  
23.10  
23.11  
23.12  
23.13  
23.14  
Chapter 24  
SCC Ethernet Mode  
24.1  
24.2  
24.3  
24.4  
24.5  
Ethernet on the MPC8260..................................................................................24-2  
Features ..............................................................................................................24-3  
Connecting the MPC8260 to Ethernet ...............................................................24-4  
SCC Ethernet Channel Frame Transmission......................................................24-5  
SCC Ethernet Channel Frame Reception...........................................................24-6  
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Number  
Title  
24.6  
24.7  
24.8  
24.9  
The Content-Addressable Memory (CAM) Interface ........................................24-7  
SCC Ethernet Parameter RAM...........................................................................24-8  
Programming the Ethernet Controller ..............................................................24-10  
SCC Ethernet Commands.................................................................................24-10  
SCC Ethernet Address Recognition .................................................................24-11  
Hash Table Algorithm ......................................................................................24-13  
Interpacket Gap Time.......................................................................................24-13  
Handling Collisions..........................................................................................24-13  
Internal and External Loopback .......................................................................24-14  
Full-Duplex Ethernet Support ..........................................................................24-14  
Handling Errors in the Ethernet Controller ......................................................24-14  
Ethernet Mode Register (PSMR)......................................................................24-15  
SCC Ethernet Receive BD................................................................................24-17  
SCC Ethernet Transmit Buffer Descriptor .......................................................24-19  
SCC Ethernet Event Register (SCCE)/Mask Register (SCCM).......................24-21  
SCC Ethernet Programming Example..............................................................24-23  
24.10  
24.11  
24.12  
24.13  
24.14  
24.15  
24.16  
24.17  
24.18  
24.19  
24.20  
24.21  
Chapter 25  
SCC AppleTalk Mode  
25.1  
25.2  
25.3  
25.4  
25.4.1  
25.4.2  
25.4.3  
25.4.4  
Operating the LocalTalk Bus..............................................................................25-1  
Features...............................................................................................................25-2  
Connecting to AppleTalk....................................................................................25-3  
Programming the SCC in AppleTalk Mode .......................................................25-3  
Programming the GSMR................................................................................25-3  
Programming the PSMR.................................................................................25-4  
Programming the TODR ................................................................................25-4  
SCC AppleTalk Programming Example ........................................................25-4  
Chapter 26  
Serial Management Controllers (SMCs)  
26.1  
26.2  
Features...............................................................................................................26-2  
Common SMC Settings and Configurations ......................................................26-3  
SMC Mode Registers (SMCMR1/SMCMR2) ...............................................26-3  
SMC Buffer Descriptor Operation .................................................................26-5  
SMC Parameter RAM ....................................................................................26-6  
SMC Function Code Registers (RFCR/TFCR)..........................................26-8  
Disabling SMCs On-the-Fly...........................................................................26-9  
SMC Transmitter Full Sequence ................................................................26-9  
SMC Transmitter Shortcut Sequence.........................................................26-9  
SMC Receiver Full Sequence.....................................................................26-9  
26.2.1  
26.2.2  
26.2.3  
26.2.3.1  
26.2.4  
26.2.4.1  
26.2.4.2  
26.2.4.3  
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Paragraph  
Number  
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Number  
Title  
26.2.4.4  
26.2.4.5  
26.2.5  
26.2.6  
26.3  
SMC Receiver Shortcut Sequence ...........................................................26-10  
Switching Protocols .................................................................................26-10  
Saving Power ...............................................................................................26-10  
Handling Interrupts in the SMC...................................................................26-10  
SMC in UART Mode.......................................................................................26-10  
Features ........................................................................................................26-11  
SMC UART Channel Transmission Process ...............................................26-11  
SMC UART Channel Reception Process.....................................................26-12  
Programming the SMC UART Controller...................................................26-12  
SMC UART Transmit and Receive Commands..........................................26-12  
Sending a Break ...........................................................................................26-13  
Sending a Preamble......................................................................................26-13  
Handling Errors in the SMC UART Controller ...........................................26-13  
SMC UART RxBD ......................................................................................26-14  
SMC UART TxBD ......................................................................................26-16  
SMC UART Event Register (SMCE)/Mask Register (SMCM) ..................26-18  
SMC UART Controller Programming Example..........................................26-19  
SMC in Transparent Mode...............................................................................26-20  
Features ........................................................................................................26-21  
SMC Transparent Channel Transmission Process .......................................26-21  
SMC Transparent Channel Reception Process ............................................26-22  
Using SMSYN for Synchronization.............................................................26-22  
Using the Time-Slot Assigner (TSA) for Synchronization..........................26-23  
SMC Transparent Commands......................................................................26-25  
Handling Errors in the SMC Transparent Controller...................................26-25  
SMC Transparent RxBD..............................................................................26-26  
SMC Transparent TxBD ..............................................................................26-27  
SMC Transparent Event Register (SMCE)/Mask Register (SMCM)..........26-28  
SMC Transparent NMSI Programming Example........................................26-29  
The SMC in GCI Mode....................................................................................26-30  
SMC GCI Parameter RAM..........................................................................26-30  
Handling the GCI Monitor Channel.............................................................26-31  
SMC GCI Monitor Channel Transmission Process .................................26-31  
SMC GCI Monitor Channel Reception Process ......................................26-31  
Handling the GCI C/I Channel.....................................................................26-31  
SMC GCI C/I Channel Transmission Process .........................................26-31  
SMC GCI C/I Channel Reception Process ..............................................26-31  
SMC GCI Commands ..................................................................................26-32  
SMC GCI Monitor Channel RxBD..............................................................26-32  
SMC GCI Monitor Channel TxBD..............................................................26-32  
SMC GCI C/I Channel RxBD......................................................................26-33  
SMC GCI C/I Channel TxBD......................................................................26-33  
SMC GCI Event Register (SMCE)/Mask Register (SMCM) ......................26-34  
26.3.1  
26.3.2  
26.3.3  
26.3.4  
26.3.5  
26.3.6  
26.3.7  
26.3.8  
26.3.9  
26.3.10  
26.3.11  
26.3.12  
26.4  
26.4.1  
26.4.2  
26.4.3  
26.4.4  
26.4.5  
26.4.6  
26.4.7  
26.4.8  
26.4.9  
26.4.10  
26.4.11  
26.5  
26.5.1  
26.5.2  
26.5.2.1  
26.5.2.2  
26.5.3  
26.5.3.1  
26.5.3.2  
26.5.4  
26.5.5  
26.5.6  
26.5.7  
26.5.8  
26.5.9  
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Number  
Title  
Chapter 27  
Multi-Channel Controllers (MCCs)  
27.1  
27.2  
27.3  
27.4  
27.5  
27.6  
Features...............................................................................................................27-1  
MCC Data Structure Organization .....................................................................27-2  
Global MCC Parameters.....................................................................................27-3  
Channel Extra Parameters ..................................................................................27-5  
Super-Channel Table..........................................................................................27-5  
Channel-Specific HDLC Parameters..................................................................27-8  
Internal Transmitter State (TSTATE) ............................................................27-9  
Interrupt Mask (INTMSK) .............................................................................27-9  
Channel Mode Register (CHAMR)..............................................................27-10  
Internal Receiver State (RSTATE)...............................................................27-11  
Channel-Specific Transparent Parameters........................................................27-12  
Channel Mode Register (CHAMR)ÑTransparent Mode ............................27-13  
MCC Configuration Registers (MCCFx) .........................................................27-15  
MCC Commands..............................................................................................27-16  
MCC Exceptions...............................................................................................27-17  
MCC Event Register (MCCE)/Mask Register (MCCM) .............................27-18  
Interrupt Table Entry................................................................................27-19  
MCC Buffer Descriptors ..................................................................................27-21  
Receive Buffer Descriptor (RxBD)..............................................................27-21  
Transmit Buffer Descriptor (TxBD).............................................................27-23  
MCC Initialization and Start/Stop Sequence....................................................27-24  
Single-Channel Initialization........................................................................27-25  
Super Channel Initialization.........................................................................27-26  
MCC Latency and Performance .......................................................................27-26  
27.6.1  
27.6.2  
27.6.3  
27.6.4  
27.7  
27.7.1  
27.8  
27.9  
27.10  
27.10.1  
27.10.1.1  
27.11  
27.11.1  
27.11.2  
27.12  
27.12.1  
27.12.2  
27.13  
Chapter 28  
Fast Communications Controllers (FCCs)  
28.1  
28.2  
28.3  
28.4  
28.5  
28.6  
28.7  
28.7.1  
28.8  
Overview ............................................................................................................28-2  
General FCC Mode Registers (GFMRx)............................................................28-3  
FCC Protocol-Specific Mode Registers (FPSMRx)...........................................28-7  
FCC Data Synchronization Registers (FDSRx) .................................................28-7  
FCC Transmit-on-Demand Registers (FTODRx) ..............................................28-7  
FCC Buffer Descriptors......................................................................................28-8  
FCC Parameter RAM .......................................................................................28-10  
FCC Function Code Registers (FCRx).........................................................28-13  
Interrupts from the FCCs..................................................................................28-13  
FCC Event Registers (FCCEx).....................................................................28-14  
FCC Mask Registers (FCCMx)....................................................................28-14  
28.8.1  
28.8.2  
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28.8.3  
28.9  
28.10  
28.11  
28.12  
28.12.1  
28.12.2  
28.12.3  
28.12.4  
28.12.5  
28.13  
FCC Status Registers (FCCSx)....................................................................28-14  
FCC Initialization.............................................................................................28-14  
FCC Interrupt Handling ...................................................................................28-15  
FCC Timing Control ........................................................................................28-15  
Disabling the FCCs On-the-Fly........................................................................28-19  
FCC Transmitter Full Sequence...................................................................28-20  
FCC Transmitter Shortcut Sequence............................................................28-20  
FCC Receiver Full Sequence .......................................................................28-20  
FCC Receiver Shortcut Sequence ................................................................28-21  
Switching Protocols .....................................................................................28-21  
Saving Power....................................................................................................28-21  
Chapter 29  
ATM Controller  
29.1  
29.2  
29.2.1  
Features ..............................................................................................................29-2  
ATM Controller Overview.................................................................................29-4  
Transmitter Overview ....................................................................................29-5  
AAL5 Transmitter Overview.....................................................................29-5  
AAL1 Transmitter Overview.....................................................................29-5  
AAL0 Transmitter Overview.....................................................................29-6  
Transmit External Rate and Internal Rate Modes......................................29-6  
Receiver Overview.........................................................................................29-6  
AAL5 Receiver Overview .........................................................................29-7  
AAL1 Receiver Overview .........................................................................29-7  
AAL0 Receiver Overview .........................................................................29-8  
Performance Monitoring ................................................................................29-8  
ABR Flow Control.........................................................................................29-8  
ATM Pace Control (APC) Unit..........................................................................29-8  
APC Modes and ATM Service Types............................................................29-8  
APC Unit Scheduling Mechanism .................................................................29-9  
Determining the Scheduling Table Size.......................................................29-10  
Determining the Cells Per Slot (CPS) in a Scheduling Table..................29-10  
Determining the Number of Slots in a Scheduling Table ........................29-11  
Determining the Time-Slot Scheduling Rate of a Channel..........................29-11  
ATM Traffic Type........................................................................................29-11  
Peak Cell Rate Traffic Type.....................................................................29-11  
Determining the PCR Traffic Type Parameters.......................................29-11  
Peak and Sustain Traffic Type (VBR) .....................................................29-12  
Example for Using VBR Traffic Parameters.......................................29-12  
Handling the Cell Loss Priority (CLP)ÑVBR Type 1 and 2 ..............29-13  
Peak and Minimum Cell Rate Traffic Type (UBR+)...............................29-13  
29.2.1.1  
29.2.1.2  
29.2.1.3  
29.2.1.4  
29.2.2  
29.2.2.1  
29.2.2.2  
29.2.2.3  
29.2.3  
29.2.4  
29.3  
29.3.1  
29.3.2  
29.3.3  
29.3.3.1  
29.3.3.2  
29.3.4  
29.3.5  
29.3.5.1  
29.3.5.2  
29.3.5.3  
29.3.5.3.1  
29.3.5.3.2  
29.3.5.4  
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29.3.6  
29.4  
Determining the Priority of an ATM Channel .............................................29-13  
VCI/VPI Address Lookup Mechanism.............................................................29-14  
External CAM Lookup.................................................................................29-14  
Address Compression...................................................................................29-15  
VP-Level Address Compression Table (VPLT) ......................................29-17  
VC-Level Address Compression Tables (VCLTs) ..................................29-18  
Misinserted Cells..........................................................................................29-18  
Receive Raw Cell Queue..............................................................................29-19  
Available Bit Rate (ABR) Flow Control..........................................................29-20  
The ABR Model ...........................................................................................29-20  
ABR Flow Control Source End-System Behavior...................................29-21  
ABR Flow Control Destination End-System Behavior............................29-21  
ABR Flowcharts.......................................................................................29-22  
RM Cell Structure.........................................................................................29-25  
RM Cell Rate Representation...................................................................29-26  
ABR Flow Control Setup .............................................................................29-27  
OAM Support ...................................................................................................29-27  
ATM-Layer OAM Definitions .....................................................................29-27  
Virtual Path (F4) Flow Mechanism..............................................................29-28  
Virtual Channel (F5) Flow Mechanism........................................................29-28  
Receiving OAM F4 or F5 Cells....................................................................29-28  
Transmitting OAM F4 or F5 Cells...............................................................29-29  
Performance Monitoring ..............................................................................29-29  
Running a Performance Block Test..........................................................29-30  
PM Block Monitoring ..............................................................................29-30  
PM Block Generation...............................................................................29-31  
BRC Performance Calculations................................................................29-32  
User-Defined Cells (UDC)...............................................................................29-32  
UDC Extended Address Mode (UEAD) ......................................................29-33  
ATM Layer Statistics........................................................................................29-33  
ATM-to-TDM Interworking.............................................................................29-34  
Automatic Data Forwarding.........................................................................29-34  
Using Interrupts in Automatic Data Forwarding..........................................29-35  
Timing Issues................................................................................................29-36  
Clock Synchronization (SRTS and Adaptive FIFOs) ..................................29-36  
Mapping TDM Time Slots to VCs...............................................................29-36  
CAS Support.................................................................................................29-36  
Trunk Condition ...........................................................................................29-37  
ATM-to-ATM Data Forwarding ..................................................................29-37  
ATM Memory Structure...................................................................................29-37  
Parameter RAM............................................................................................29-37  
Determining UEAD_OFFSET (UEAD Mode Only) ...............................29-40  
VCI Filtering (VCIF)................................................................................29-40  
29.4.1  
29.4.2  
29.4.2.1  
29.4.2.2  
29.4.3  
29.4.4  
29.5  
29.5.1  
29.5.1.1  
29.5.1.2  
29.5.1.3  
29.5.2  
29.5.2.1  
29.5.3  
29.6  
29.6.1  
29.6.2  
29.6.3  
29.6.4  
29.6.5  
29.6.6  
29.6.6.1  
29.6.6.2  
29.6.6.3  
29.6.6.4  
29.7  
29.7.1  
29.8  
29.9  
29.9.1  
29.9.2  
29.9.3  
29.9.4  
29.9.5  
29.9.6  
29.9.7  
29.9.8  
29.10  
29.10.1  
29.10.1.1  
29.10.1.2  
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Title  
29.10.1.3  
29.10.2  
Global Mode Entry (GMODE) ................................................................29-41  
Connection Tables (RCT, TCT, and TCTE)................................................29-41  
ATM Channel Code.................................................................................29-42  
Receive Connection Table (RCT)............................................................29-43  
AAL5 Protocol-Specific RCT..............................................................29-46  
AAL5-ABR Protocol-Specific RCT....................................................29-47  
AAL1 Protocol-Specific RCT..............................................................29-48  
AAL0 Protocol-Specific RCT..............................................................29-50  
Transmit Connection Table (TCT) ..........................................................29-51  
AAL5 Protocol-Specific TCT..............................................................29-54  
AAL1 Protocol-Specific TCT..............................................................29-54  
AAL0 Protocol-Specific TCT..............................................................29-55  
VBR Protocol-Specific TCTE .............................................................29-56  
UBR+ Protocol-Specific TCTE ...........................................................29-57  
ABR Protocol-Specific TCTE .............................................................29-58  
OAM Performance Monitoring Tables ........................................................29-60  
APC Data Structure......................................................................................29-61  
APC Parameter Tables.............................................................................29-62  
APC Priority Table...................................................................................29-63  
APC Scheduling Tables ...........................................................................29-63  
ATM Controller Buffer Descriptors (BDs)..................................................29-64  
Transmit Buffer Operations .....................................................................29-64  
Receive Buffers Operation.......................................................................29-65  
Static Buffer Allocation .......................................................................29-65  
Global Buffer Allocation .....................................................................29-66  
Free Buffer Pools .................................................................................29-67  
Free Buffer Pool Parameter Tables......................................................29-68  
ATM Controller Buffers ..........................................................................29-69  
AAL5 RxBD ............................................................................................29-69  
AAL1 RxBD ............................................................................................29-71  
AAL0 RxBD ............................................................................................29-72  
AAL5, AAL1 User-Defined CellÑRxBD Extension..............................29-73  
AAL5 TxBDs...........................................................................................29-74  
AAL1 TxBDs...........................................................................................29-76  
AAL0 TxBDs...........................................................................................29-77  
AAL5, AAL1 User-Defined CellÑTxBD Extension..............................29-78  
AAL1 Sequence Number (SN) Protection Table (AAL1 Only)..................29-78  
UNI Statistics Table .....................................................................................29-78  
ATM Exceptions ..............................................................................................29-79  
Interrupt Queues...........................................................................................29-79  
Interrupt Queue Entry ..................................................................................29-80  
Interrupt Queue Parameter Tables ...............................................................29-81  
The UTOPIA Interface.....................................................................................29-82  
29.10.2.1  
29.10.2.2  
29.10.2.2.1  
29.10.2.2.2  
29.10.2.2.3  
29.10.2.2.4  
29.10.2.3  
29.10.2.3.1  
29.10.2.3.2  
29.10.2.3.3  
29.10.2.3.4  
29.10.2.3.5  
29.10.2.3.6  
29.10.3  
29.10.4  
29.10.4.1  
29.10.4.2  
29.10.4.3  
29.10.5  
29.10.5.1  
29.10.5.2  
29.10.5.2.1  
29.10.5.2.2  
29.10.5.2.3  
29.10.5.2.4  
29.10.5.3  
29.10.5.4  
29.10.5.5  
29.10.5.6  
29.10.5.7  
29.10.5.8  
29.10.5.9  
29.10.5.10  
29.10.5.11  
29.10.6  
29.10.7  
29.11  
29.11.1  
29.11.2  
29.11.3  
29.12  
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Paragraph  
Number  
Page  
Number  
Title  
29.12.1  
29.12.1.1  
29.12.2  
29.12.2.1  
29.12.2.2  
29.12.2.3  
29.13  
29.13.1  
29.13.2  
29.13.3  
29.13.4  
29.14  
29.15  
29.16  
29.16.1  
29.16.2  
29.16.3  
UTOPIA Interface Master Mode..................................................................29-82  
UTOPIA Master Multiple PHY Operation ..............................................29-83  
UTOPIA Interface Slave Mode....................................................................29-83  
UTOPIA Slave Multiple PHY Operation.................................................29-84  
UTOPIA Clocking Modes........................................................................29-84  
UTOPIA Loop-Back Modes ....................................................................29-85  
ATM Registers .................................................................................................29-85  
General FCC Mode Register (GFMR) .........................................................29-85  
FCC Protocol-Specific Mode Register (FPSMR) ........................................29-85  
ATM Event Register (FCCE)/Mask Register (FCCM)................................29-87  
FCC Transmit Internal Rate Registers (FTIRRx) ........................................29-88  
ATM Transmit Command ................................................................................29-90  
SRTS Generation and Clock Recovery Using External Logic.........................29-91  
Configuring the ATM Controller for Maximum CPM Performance ...............29-92  
Using Transmit Internal Rate Mode.............................................................29-92  
APC Configuration.......................................................................................29-93  
Buffer Configuration ....................................................................................29-93  
Chapter 30  
Fast Ethernet Controller  
30.1  
30.2  
30.3  
30.4  
30.5  
30.6  
30.7  
30.8  
Fast Ethernet on the MPC8260...........................................................................30-2  
Features...............................................................................................................30-3  
Connecting the MPC8260 to Fast Ethernet........................................................30-4  
Ethernet Channel Frame Transmission...............................................................30-5  
Ethernet Channel Frame Reception....................................................................30-7  
Flow Control.......................................................................................................30-8  
CAM Interface....................................................................................................30-8  
Ethernet Parameter RAM ...................................................................................30-9  
Programming Model.........................................................................................30-12  
Ethernet Command Set.....................................................................................30-12  
RMON Support.................................................................................................30-14  
Ethernet Address Recognition..........................................................................30-15  
Hash Table Algorithm ......................................................................................30-17  
Interpacket Gap Time.......................................................................................30-18  
Handling Collisions..........................................................................................30-18  
Internal and External Loopback .......................................................................30-18  
Ethernet Error-Handling Procedure..................................................................30-19  
Fast Ethernet Registers.....................................................................................30-19  
FCC Ethernet Mode Register (FPSMR).......................................................30-20  
Ethernet Event Register (FCCE)/Mask Register (FCCM) ...........................30-21  
30.9  
30.10  
30.11  
30.12  
30.13  
30.14  
30.15  
30.16  
30.17  
30.18  
30.18.1  
30.18.2  
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Paragraph  
Number  
Page  
Number  
Title  
30.19  
30.20  
Ethernet RxBDs................................................................................................30-23  
Ethernet TxBDs................................................................................................30-26  
Chapter 31  
FCC HDLC Controller  
31.1  
31.2  
31.3  
31.4  
31.5  
31.5.1  
31.5.2  
31.6  
31.7  
31.8  
31.9  
31.10  
Key Features.......................................................................................................31-2  
HDLC Channel Frame Transmission Processing...............................................31-2  
HDLC Channel Frame Reception Processing....................................................31-3  
HDLC Parameter RAM......................................................................................31-4  
Programming Model ..........................................................................................31-5  
HDLC Command Set.....................................................................................31-5  
HDLC Error Handling....................................................................................31-6  
HDLC Mode Register (FPSMR)........................................................................31-7  
HDLC Receive Buffer Descriptor (RxBD)........................................................31-9  
HDLC Transmit Buffer Descriptor (TxBD).....................................................31-12  
HDLC Event Register (FCCE)/Mask Register (FCCM)..................................31-14  
FCC Status Register (FCCS)............................................................................31-16  
Chapter 32  
FCC Transparent Controller  
32.1  
32.2  
32.3  
32.3.1  
32.3.2  
32.3.3  
Features ..............................................................................................................32-2  
Transparent Channel Operation .........................................................................32-2  
Achieving Synchronization in Transparent Mode .............................................32-2  
In-Line Synchronization Pattern ....................................................................32-3  
External Synchronization Signals ..................................................................32-3  
Transparent Synchronization Example ..........................................................32-4  
Chapter 33  
Serial Peripheral Interface (SPI)  
33.1  
33.2  
33.3  
33.3.1  
33.3.2  
33.3.3  
33.4  
33.4.1  
33.4.1.1  
33.4.2  
Features ..............................................................................................................33-2  
SPI Clocking and Signal Functions....................................................................33-2  
Configuring the SPI Controller ..........................................................................33-3  
The SPI as a Master Device ...........................................................................33-3  
The SPI as a Slave Device .............................................................................33-4  
The SPI in Multimaster Operation .................................................................33-4  
Programming the SPI Registers .........................................................................33-6  
SPI Mode Register (SPMODE) .....................................................................33-6  
SPI Examples with Different SPMODE[LEN] Values..............................33-8  
SPI Event/Mask Registers (SPIE/SPIM) .......................................................33-9  
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Number  
Title  
33.4.3  
33.5  
33.5.1  
33.6  
33.7  
33.7.1  
33.7.1.1  
33.7.1.2  
33.8  
33.9  
33.10  
SPI Command Register (SPCOM).................................................................33-9  
SPI Parameter RAM.........................................................................................33-10  
Receive/Transmit Function Code Registers (RFCR/TFCR) ........................33-12  
SPI Commands .................................................................................................33-12  
The SPI Buffer Descriptor (BD) Table.............................................................33-13  
SPI Buffer Descriptors (BDs).......................................................................33-13  
SPI Receive BD (RxBD)..........................................................................33-14  
SPI Transmit BD (TxBD).........................................................................33-15  
SPI Master Programming Example..................................................................33-16  
SPI Slave Programming Example ....................................................................33-17  
Handling Interrupts in the SPI..........................................................................33-18  
Chapter 34  
I C Controller  
2
34.1  
34.2  
34.3  
Features...............................................................................................................34-2  
I2C Controller Clocking and Signal Functions...................................................34-2  
I2C Controller Transfers.....................................................................................34-3  
I2C Master Write (Slave Read) ......................................................................34-4  
I2C Loopback Testing ....................................................................................34-4  
I2C Master Read (Slave Write) ......................................................................34-4  
I2C Multi-Master Considerations...................................................................34-5  
I2C Registers.......................................................................................................34-6  
I2C Mode Register (I2MOD) .........................................................................34-6  
I2C Address Register (I2ADD) ......................................................................34-7  
I2C Baud Rate Generator Register (I2BRG)..................................................34-7  
I2C Event/Mask Registers (I2CER/I2CMR)..................................................34-8  
I2C Command Register (I2COM) ..................................................................34-8  
I2C Parameter RAM...........................................................................................34-9  
I2C Commands .................................................................................................34-11  
The I2C Buffer Descriptor (BD) Table.............................................................34-12  
I2C Buffer Descriptors (BDs).......................................................................34-12  
I2C Receive Buffer Descriptor (RxBD) ...................................................34-13  
I2C Transmit Buffer Descriptor (TxBD)..................................................34-14  
34.3.1  
34.3.2  
34.3.3  
34.3.4  
34.4  
34.4.1  
34.4.2  
34.4.3  
34.4.4  
34.4.5  
34.5  
34.6  
34.7  
34.7.1  
34.7.1.1  
34.7.1.2  
Chapter 35  
Parallel I/O Ports  
35.1  
35.2  
35.2.1  
35.2.2  
Features...............................................................................................................35-1  
Port Registers......................................................................................................35-2  
Port Open-Drain Registers (PODRAÐPODRD).............................................35-2  
Port Data Registers (PDATAÐPDATD).........................................................35-2  
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Paragraph  
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Page  
Number  
Title  
35.2.3  
35.2.4  
35.2.5  
35.3  
Port Data Direction Registers (PDIRAÐPDIRD)...........................................35-3  
Port Pin Assignment Register (PPAR)...........................................................35-4  
Port Special Options Registers AÐD (PSORAÐPSORD)...............................35-4  
Port Block Diagram............................................................................................35-6  
Port Pins Functions ............................................................................................35-6  
General Purpose I/O Pins...............................................................................35-7  
Dedicated Pins................................................................................................35-7  
Ports Tables........................................................................................................35-7  
Interrupts from Port C ......................................................................................35-19  
35.4  
35.4.1  
35.4.2  
35.5  
35.6  
Appendix A  
Register Quick Reference Guide  
A.1  
A.2  
A.3  
PowerPC RegistersÑUser Registers ..................................................................A-1  
PowerPC RegistersÑSupervisor Registers.........................................................A-2  
MPC8260-Specific SPRs ....................................................................................A-3  
Glossary  
Index  
MOTOROLA  
Contents  
xxxi  
CONTENTS  
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Number  
Page  
Number  
Title  
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MPC8260 PowerQUICC II UserÕs Manual  
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Figure  
Number  
Page  
Number  
Title  
1-1  
1-2  
1-3  
1-4  
1-5  
1-6  
1-7  
1-8  
MPC8260 Block Diagram ......................................................................................... 1-5  
MPC8260 External Signals........................................................................................ 1-8  
Remote Access Server Configuration...................................................................... 1-11  
Regional Office Router Configuration .................................................................... 1-12  
LAN-to-WAN Bridge Router Configuration........................................................... 1-13  
Cellular Base Station Configuration........................................................................ 1-14  
Telecommunications Switch Controller Configuration........................................... 1-14  
SONET Transmission Controller Configuration..................................................... 1-15  
Basic System Configuration .................................................................................... 1-16  
High-Performance Communication......................................................................... 1-16  
High-Performance System Microprocessor Configuration ..................................... 1-17  
MPC8260 Integrated Processor Core Block Diagram............................................... 2-2  
MPC8260 Programming ModelÑRegisters............................................................ 2-10  
Hardware Implementation Register 0 (HID0) ......................................................... 2-11  
Hardware Implementation Register 1 (HID1) ......................................................... 2-15  
Hardware Implementation-Dependent Register 2 (HID2) ...................................... 2-15  
Data Cache Organization......................................................................................... 2-20  
.SIU Block Diagram .................................................................................................. 4-1  
System Configuration and Protection Logic.............................................................. 4-3  
Timers Clock Generation........................................................................................... 4-4  
TMCNT Block Diagram............................................................................................ 4-5  
PIT Block Diagram.................................................................................................... 4-5  
Software Watchdog Timer Service State Diagram.................................................... 4-6  
Software Watchdog Timer Block Diagram ............................................................... 4-7  
MPC8260 Interrupt Structure .................................................................................... 4-8  
Interrupt Request Masking ...................................................................................... 4-14  
SIU Interrupt Configuration Register (SICR).......................................................... 4-17  
SIU Interrupt Priority Register (SIPRR).................................................................. 4-18  
CPM High Interrupt Priority Register (SCPRR_H) ................................................ 4-19  
CPM Low Interrupt Priority Register (SCPRR_L) ................................................. 4-20  
SIPNR_H Fields ...................................................................................................... 4-21  
SIPNR_L Fields....................................................................................................... 4-21  
SIMR_H Register .................................................................................................... 4-22  
SIMR_L Register..................................................................................................... 4-23  
SIU Interrupt Vector Register (SIVEC) .................................................................. 4-23  
Interrupt Table Handling Example .......................................................................... 4-24  
1-9  
1-10  
1-11  
2-1  
2-2  
2-3  
2-4  
2-5  
2-6  
4-1  
4-2  
4-3  
4-4  
4-5  
4-6  
4-7  
4-8  
4-9  
4-10  
4-11  
4-12  
4-13  
4-14  
4-15  
4-16  
4-17  
4-18  
4-19  
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Figure  
Number  
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Number  
Title  
4-20  
4-21  
4-22  
4-23  
4-24  
4-25  
4-26  
4-27  
4-28  
4-29  
4-30  
4-31  
4-32  
4-33  
4-34  
4-35  
4-36  
4-37  
4-38  
4-39  
4-40  
5-1  
5-2  
5-3  
5-4  
5-5  
5-6  
6-1  
7-1  
8-1  
8-2  
8-3  
8-4  
8-5  
8-6  
8-7  
8-8  
8-9  
SIU External Interrupt Control Register (SIEXR)................................................... 4-25  
Bus Configuration Register (BCR).......................................................................... 4-26  
PPC_ACR................................................................................................................ 4-28  
PPC_ALRH ............................................................................................................. 4-29  
PPC_AALRL........................................................................................................... 4-29  
LCL_ACR................................................................................................................ 4-29  
LCL_ALRH............................................................................................................. 4-30  
LCL_ALRL ............................................................................................................. 4-31  
SIU Model Configuration Register (SIUMCR)....................................................... 4-31  
Internal Memory Map Register (IMMR)................................................................. 4-34  
System Protection Control Register (SYPCCR)...................................................... 4-35  
The 60x Bus Transfer Error Status and Control Register 1 (TESCR1)................... 4-36  
60x Bus Transfer Error Status and Control Register 2 (TESCR2).......................... 4-37  
Local Bus Transfer Error Status and Control Register 1 (L_TESCR1) .................. 4-38  
Local Bus Transfer Error Status and Control Register 2 (L_TESCR2) .................. 4-39  
Time Counter Status and Control Register (TMCNTSC) ....................................... 4-40  
Time Counter Register (TCMCNT) ........................................................................ 4-41  
Time Counter Alarm Register (TMCNTAL) .......................................................... 4-42  
Periodic Interrupt Status and Control Register (PISCR) ......................................... 4-42  
Periodic interrupt Timer Count Register (PITC)..................................................... 4-43  
Periodic Interrupt Timer Register (PITR)................................................................ 4-44  
Reset Status Register (RSR) ...................................................................................... 5-4  
Reset Mode Register (RMR) ..................................................................................... 5-5  
Hard Reset Configuration Word................................................................................ 5-8  
Single Chip with Default Configuration.................................................................. 5-10  
Configuring a Single Chip from EPROM ............................................................... 5-10  
Configuring Multiple Chips..................................................................................... 5-11  
MPC8260 External Signals........................................................................................ 6-2  
PowerPC Signal Groupings ....................................................................................... 7-2  
Single MPC8260 Bus Mode ...................................................................................... 8-3  
60x-Compatible Bus Mode........................................................................................ 8-4  
Basic Transfer Protocol ............................................................................................. 8-5  
Address Bus Arbitration with External Bus Master .................................................. 8-9  
Address Pipelining................................................................................................... 8-10  
Interface to Different Port Size Devices.................................................................. 8-17  
Retry Cycle .............................................................................................................. 8-24  
Single-Beat and Burst Data Transfers ..................................................................... 8-28  
128-Bit Extended Transfer to 32-Bit Port Size........................................................ 8-29  
Burst Transfer to 32-Bit Port Size ........................................................................... 8-30  
Data Tenure Terminated by Assertion of TEA........................................................ 8-31  
MEI Cache Coherency ProtocolÑState Diagram (WIM = 001)............................. 8-32  
System PLL Block Diagram...................................................................................... 9-5  
PLL Filtering Circuit ................................................................................................. 9-8  
8-10  
8-11  
8-12  
9-1  
9-2  
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Figure  
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9-3  
9-4  
9-5  
10-1  
10-2  
10-3  
10-4  
10-5  
10-6  
10-7  
10-8  
10-9  
System Clock Control Register (SCCR).................................................................... 9-8  
System Clock Mode Register (SCMR)...................................................................... 9-9  
Relationships of SCMR Parameters ........................................................................ 9-10  
Dual-Bus Architecture............................................................................................. 10-3  
Memory Controller Machine Selection ................................................................... 10-6  
Simple System Configuration.................................................................................. 10-7  
Basic Memory Controller Operation ....................................................................... 10-8  
Partial Data Valid for 32-Bit Port Size Memory, Double-Word Transfer ............ 10-13  
Base Registers (BRx) ............................................................................................ 10-14  
Option Registers (ORx)ÑSDRAM Mode ............................................................ 10-16  
ORx ÑGPCM Mode............................................................................................. 10-18  
ORxÑUPM Mode................................................................................................. 10-20  
60x/Local SDRAM Mode Register (PSDMR/LSDMR) ....................................... 10-21  
Machine x Mode Registers (MxMR)..................................................................... 10-26  
Memory Data Register (MDR).............................................................................. 10-29  
Memory Address Register (MAR) ........................................................................ 10-29  
60x Bus-Assigned UPM Refresh Timer (PURT) .................................................. 10-30  
Local Bus-Assigned UPM Refresh Timer (LURT)............................................... 10-30  
60x Bus-Assigned SDRAM Refresh Timer (PSRT) ............................................. 10-31  
Local Bus-Assigned SDRAM Refresh Timer (LSRT).......................................... 10-32  
Memory Refresh Timer Prescaler Register (MPTPR)........................................... 10-32  
128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown)............ 10-34  
PRETOACT = 2 (2 Clock Cycles) ........................................................................ 10-39  
ACTTORW = 2 (2 Clock Cycles) ......................................................................... 10-39  
CL = 2 (2 Clock Cycles)........................................................................................ 10-40  
LDOTOPRE = 2 (-2 Clock Cycles)....................................................................... 10-40  
WRC = 2 (2 Clock Cycles).................................................................................... 10-41  
RFRC = 4 (6 Clock Cycles)................................................................................... 10-41  
EAMUX = 1 .......................................................................................................... 10-42  
BUFCMD = 1 ........................................................................................................ 10-42  
SDRAM Single-Beat Read, Page Closed, CL = 3................................................. 10-43  
SDRAM Single-Beat Read, Page Hit, CL = 3....................................................... 10-43  
SDRAM Two-Beat Burst Read, Page Closed, CL = 3.......................................... 10-43  
SDRAM Four-Beat Burst Read, Page Miss, CL = 3............................................. 10-44  
SDRAM Single-Beat Write, Page Hit ................................................................... 10-44  
SDRAM Three-Beat Burst Write, Page Closed .................................................... 10-44  
SDRAM Read-after-Read Pipeline, Page Hit, CL = 3 .......................................... 10-45  
SDRAM Write-after-Write Pipelined, Page Hit.................................................... 10-45  
SDRAM Read-after-Write Pipelined, Page Hit..................................................... 10-45  
SDRAM Mode-Set Command Timing.................................................................. 10-46  
Mode Data Bit Settings.......................................................................................... 10-47  
SDRAM Bank-Staggered CBR Refresh Timing ................................................... 10-48  
GPCM-to-SRAM ConÞguration............................................................................ 10-52  
10-10  
10-11  
10-12  
10-13  
10-14  
10-15  
10-16  
10-17  
10-18  
10-19  
10-20  
10-21  
10-22  
10-23  
10-24  
10-25  
10-26  
10-27  
10-28  
10-29  
10-30  
10-31  
10-32  
10-33  
10-34  
10-35  
10-36  
10-37  
10-38  
10-39  
10-40  
MOTOROLA  
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xxxv  
ILLUSTRATIONS  
Figure  
Number  
Page  
Number  
Title  
10-41  
10-42  
10-43  
10-44  
10-45  
10-46  
10-47  
10-48  
10-49  
10-50  
10-51  
10-52  
10-53  
10-54  
10-55  
10-56  
10-57  
10-58  
10-59  
GPCM Peripheral Device Interface....................................................................... 10-53  
GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0) ................... 10-53  
GPCM Memory Device Interface.......................................................................... 10-54  
GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0) ......... 10-54  
GPCM Memory Device Basic Timing (ACS ¹ 00, CSNT = 1, TRLX = 0) ......... 10-55  
GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1)....... 10-55  
GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0,TRLX = 1)....... 10-56  
GPCM Relaxed-Timing Write (ACS = 10, SCY = 0, CSNT = 1, TRLX = 1)...... 10-56  
GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1)...... 10-57  
GPCM Read Followed by Read (ORx[29Ð30] = 0x, Fastest Timing) .................. 10-58  
GPCM Read Followed by Read (ORx[29Ð30] = 01) ............................................ 10-59  
GPCM Read Followed by Write (ORx[29Ð30] = 01) ........................................... 10-59  
GPCM Read Followed by Read (ORx[29Ð30] = 10) ............................................ 10-60  
External Termination of GPCM Access................................................................ 10-61  
User-Programmable Machine Block Diagram ...................................................... 10-63  
RAM Array Indexing............................................................................................. 10-64  
Memory Refresh Timer Request Block Diagram.................................................. 10-66  
Memory Controller UPM Clock Scheme for Integer Clock Ratios ...................... 10-67  
Memory Controller UPM Clock Scheme for Non-Integer (2.5:1/3.5:1)  
Clock Ratios ........................................................................................................ 10-68  
UPM Signals Timing Example.............................................................................. 10-69  
RAM Array and Signal Generation ....................................................................... 10-70  
The RAM Word..................................................................................................... 10-70  
CS Signal Selection ............................................................................................... 10-75  
BS Signal Selection ............................................................................................... 10-75  
UPM Read Access Data Sampling ........................................................................ 10-78  
Wait Mechanism Timing for Internal and External Synchronous Masters ........... 10-79  
DRAM Interface Connection to the 60x Bus (64-Bit Port Size)........................... 10-82  
Single-Beat Read Access to FPM DRAM............................................................. 10-83  
Single-Beat Write Access to FPM DRAM............................................................ 10-84  
Burst Read Access to FPM DRAM (No LOOP)................................................... 10-85  
Burst Read Access to FPM DRAM (LOOP)......................................................... 10-86  
Burst Write Access to FPM DRAM (No LOOP) .................................................. 10-87  
Refresh Cycle (CBR) to FPM DRAM................................................................... 10-88  
Exception Cycle..................................................................................................... 10-89  
FPM DRAM Burst Read Access (Data Sampling on Falling Edge of CLKIN) ... 10-91  
MPC8260/EDO Interface Connection to the 60x Bus........................................... 10-92  
Single-Beat Read Access to EDO DRAM............................................................. 10-93  
Single-Beat Write Access to EDO DRAM............................................................ 10-94  
Single-Beat Write Access to EDO DRAM Using REDO to Insert Three  
10-60  
10-61  
10-62  
10-63  
10-64  
10-65  
10-66  
10-67  
10-68  
10-69  
10-70  
10-71  
10-72  
10-73  
10-74  
10-75  
10-76  
10-77  
10-78  
10-79  
Wait States........................................................................................................... 10-95  
Burst Read Access to EDO DRAM....................................................................... 10-96  
Burst Write Access to EDO DRAM...................................................................... 10-97  
10-80  
10-81  
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Figure  
Number  
Page  
Number  
Title  
10-82  
10-83  
10-84  
10-85  
10-86  
11-1  
11-2  
11-3  
11-4  
12-1  
12-2  
12-3  
12-4  
12-5  
12-6  
13-1  
13-2  
13-3  
13-4  
13-5  
13-6  
13-7  
13-8  
13-9  
13-10  
13-11  
13-12  
14-1  
14-2  
14-3  
14-4  
14-5  
14-6  
14-7  
14-8  
14-9  
14-10  
14-11  
14-12  
14-13  
14-14  
14-15  
14-16  
Refresh Cycle (CBR) to EDO DRAM................................................................... 10-98  
Exception Cycle For EDO DRAM........................................................................ 10-99  
Pipelined Bus Operation and Memory Access in 60x-Compatible Mode........... 10-103  
External Master Access (GPCM) ........................................................................ 10-104  
External Master Configuration with SDRAM Device......................................... 10-105  
L2 Cache in Copy-Back Mode ................................................................................ 11-2  
External L2 Cache in Write-Through Mode............................................................ 11-4  
External L2 Cache in ECC/Parity Mode ................................................................. 11-6  
Read Access with L2 Cache .................................................................................... 11-9  
Test Logic Block Diagram....................................................................................... 12-2  
TAP Controller State Machine ................................................................................ 12-3  
Output Pin Cell (O.Pin) ........................................................................................... 12-4  
Observe-Only Input Pin Cell (I.Obs)....................................................................... 12-4  
Output Control Cell (IO.CTL)................................................................................. 12-5  
General Arrangement of Bidirectional Pin Cells..................................................... 12-5  
MPC8260 CPM Block Diagram.............................................................................. 13-3  
Communications Processor (CP) Block Diagram ................................................... 13-5  
RISC Controller Configuration Register (RCCR)................................................... 13-8  
RISC Time-Stamp Control Register (RTSCR)........................................................ 13-9  
RISC Time-Stamp Register (RTSR) ..................................................................... 13-10  
CP Command Register (CPCR)............................................................................. 13-11  
Dual-Port RAM Block Diagram............................................................................ 13-15  
Dual-Port RAM Memory Map .............................................................................. 13-16  
RISC Timer Table RAM Usage ............................................................................ 13-19  
RISC Timer Command Register (TM_CMD)....................................................... 13-20  
TM_CMD Field Descriptions................................................................................ 13-21  
RISC Timer Event Register (RTER)/Mask Register (RTMR).............................. 13-21  
SI Block Diagram .................................................................................................... 14-2  
Various Configurations of a Single TDM Channel ................................................. 14-5  
Dual TDM Channel Example .................................................................................. 14-6  
Enabling Connections to the TSA ........................................................................... 14-8  
One TDM Channel with Static Frames and Independent Rx and Tx Routes.......... 14-9  
One TDM Channel with Shadow RAM for Dynamic Route Change ................... 14-10  
SIx RAM Entry Fields........................................................................................... 14-10  
Using the SWTR Feature....................................................................................... 14-12  
Example: SIx RAM Dynamic Changes, TDMa and b, Same SIx RAM Size....... 14-16  
SI Global Mode Registers (SIxGMR) ................................................................... 14-17  
SI Mode Registers (SIxMR) .................................................................................. 14-18  
One-Clock Delay from Sync to Data (xFSD = 01)................................................ 14-20  
No Delay from Sync to Data (xFSD = 00) ............................................................ 14-20  
Falling Edge (FE) Effect When CE = 1 and xFSD = 01 ....................................... 14-21  
Falling Edge (FE) Effect When CE = 0 and xFSD = 01 ....................................... 14-21  
Falling Edge (FE) Effect When CE = 1 and xFSD = 00 ....................................... 14-22  
MOTOROLA  
Illustrations  
xxxvii  
ILLUSTRATIONS  
Figure  
Number  
Page  
Number  
Title  
14-17  
14-18  
14-19  
14-20  
14-21  
14-22  
14-23  
14-24  
15-1  
15-2  
15-3  
15-4  
15-5  
15-6  
15-7  
15-8  
15-9  
15-10  
15-11  
15-12  
16-1  
16-2  
17-1  
17-2  
17-3  
17-4  
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17-6  
17-7  
17-8  
17-9  
18-1  
18-2  
18-3  
18-4  
18-5  
18-6  
Falling Edge (FE) Effect When CE = 0 and xFSD = 00 ....................................... 14-23  
SIx RAM Shadow Address Registers (SIxRSR)................................................... 14-24  
SI Command Register (SIxCMDR)....................................................................... 14-24  
SI Status Registers (SIxSTR)................................................................................. 14-25  
Dual IDL Bus Application Example...................................................................... 14-26  
IDL Terminal Adaptor........................................................................................... 14-27  
IDL Bus Signals..................................................................................................... 14-28  
GCI Bus Signals .................................................................................................... 14-32  
CPM Multiplexing Logic (CMX) Block Diagram .................................................. 15-2  
Enabling Connections to the TSA ........................................................................... 15-4  
Bank of Clocks ........................................................................................................ 15-5  
CMX UTOPIA Address Register (CMXUAR)....................................................... 15-7  
Connection of the Master Address .......................................................................... 15-8  
Connection of the Slave Address............................................................................. 15-9  
Multi-PHY Receive Address Multiplexing ........................................................... 15-10  
CMX SI1 Clock Route Register (CMXSI1CR)..................................................... 15-11  
CMX SI2 Clock Route Register (CMXSI2CR)..................................................... 15-12  
CMX FCC Clock Route Register (CMXFCR)...................................................... 15-13  
CMX SCC Clock Route Register (CMXSCR)...................................................... 15-15  
CMX SMC Clock Route Register (CMXSMR) .................................................... 15-18  
Baud-Rate Generator (BRG) Block Diagram.......................................................... 16-1  
Baud-Rate Generator Configuration Registers (BRGCx) ....................................... 16-2  
Timer Block Diagram.............................................................................................. 17-1  
Timer Cascaded Mode Block Diagram ................................................................... 17-4  
Timer Global Configuration Register 1 (TGCR1)................................................... 17-4  
Timer Global Configuration Register 2 (TGCR2)................................................... 17-5  
Timer Mode Registers (TMR1ÐTMR4) .................................................................. 17-6  
Timer Reference Registers (TRR1ÐTRR4) ............................................................. 17-7  
Timer Capture Registers (TCR1ÐTCR4)................................................................. 17-8  
Timer Counter Registers (TCN1ÐTCN4) ................................................................ 17-8  
Timer Event Registers (TER1ÐTER4)..................................................................... 17-8  
SDMA Data Paths.................................................................................................... 18-1  
SDMA Bus Arbitration (Transaction Steal) ............................................................ 18-3  
SDMA Status Register (SDSR)............................................................................... 18-3  
SDMA Transfer Error MSNUM Registers (PDTEM/LDTEM).............................. 18-4  
IDMA Transfer Buffer in the Dual-Port RAM........................................................ 18-7  
Example IDMA Transfer Buffer States for a Memory-to-Memory Transfer  
(Size = 128 Bytes) ................................................................................................. 18-8  
IDMAx ChannelÕs BD Table................................................................................. 18-15  
DCM Parameters ................................................................................................... 18-18  
IDMA Event/Mask Registers (IDSR/IDMR) ........................................................ 18-23  
IDMA BD Structure .............................................................................................. 18-23  
SCC Block Diagram ................................................................................................ 19-2  
18-7  
18-8  
18-9  
18-10  
19-1  
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21-8  
21-9  
GSMR_HÑGeneral SCC Mode Register (High Order) ......................................... 19-3  
GSMR_LÑGeneral SCC Mode Register (Low Order) .......................................... 19-6  
Data Synchronization Register (DSR)..................................................................... 19-9  
Transmit-on-Demand Register (TODR).................................................................. 19-9  
SCC Buffer Descriptors (BDs) .............................................................................. 19-11  
SCC BD and Buffer Memory Structure................................................................. 19-12  
Function Code Registers (RFCR and TFCR) ........................................................ 19-15  
Output Delay from RTS Asserted for Synchronous Protocols.............................. 19-18  
Output Delay from CTS Asserted for Synchronous Protocols.............................. 19-19  
CTS Lost in Synchronous Protocols...................................................................... 19-20  
Using CD to Control Synchronous Protocol Reception ........................................ 19-21  
DPLL Receiver Block Diagram............................................................................. 19-22  
DPLL Transmitter Block Diagram ........................................................................ 19-23  
DPLL Encoding Examples .................................................................................... 19-25  
UART Character Format ......................................................................................... 20-1  
Two UART Multidrop Configurations.................................................................... 20-8  
Control Character Table .......................................................................................... 20-9  
Transmit Out-of-Sequence Register (TOSEQ)...................................................... 20-10  
Asynchronous UART Transmitter......................................................................... 20-11  
Protocol-Specific Mode Register for UART (PSMR)........................................... 20-14  
SCC UART Receiving using RxBDs .................................................................... 20-16  
SCC UART Receive Buffer Descriptor (RxBD)................................................... 20-17  
SCC UART Transmit Buffer Descriptor (TxBD) ................................................. 20-18  
SCC UART Interrupt Event Example ................................................................... 20-20  
SCC UART Event Register (SCCE) and Mask Register (SCCM)........................ 20-20  
SCC Status Register for UART Mode (SCCS) ..................................................... 20-21  
HDLC Framing Structure ........................................................................................ 21-2  
HDLC Address Recognition.................................................................................... 21-5  
HDLC Mode Register (PSMR) ............................................................................... 21-7  
SCC HDLC Receive Buffer Descriptor (RxBD)..................................................... 21-8  
SCC HDLC Receiving Using RxBDs ................................................................... 21-10  
SCC HDLC Transmit Buffer Descriptor (TxBD) ................................................. 21-11  
HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ........................... 21-12  
SCC HDLC Interrupt Event Example ................................................................... 21-13  
SCC HDLC Status Register (SCCS) ..................................................................... 21-14  
Typical HDLC Bus Multimaster Configuration.................................................... 21-18  
Typical HDLC Bus Single-Master Configuration................................................. 21-19  
Detecting an HDLC Bus Collision ........................................................................ 21-20  
Nonsymmetrical Tx Clock Duty Cycle for Increased Performance...................... 21-21  
HDLC Bus Transmission Line Configuration....................................................... 21-21  
Delayed RTS Mode ............................................................................................... 21-22  
HDLC Bus TDM Transmission Line Configuration............................................. 21-22  
Classes of BISYNC Frames..................................................................................... 22-1  
21-10  
21-11  
21-12  
21-13  
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21-15  
21-16  
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26-17  
26-18  
Control Character Table and RCCM ....................................................................... 22-6  
BISYNC SYNC (BSYNC)...................................................................................... 22-7  
BISYNC DLE (BDLE)............................................................................................ 22-8  
Protocol-Specific Mode Register for BISYNC (PSMR)....................................... 22-10  
SCC BISYNC RxBD............................................................................................. 22-12  
SCC BISYNC Transmit BD (TxBD) .................................................................... 22-14  
BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM).................... 22-15  
SCC Status Registers (SCCS)................................................................................ 22-16  
Sending Transparent Frames between MPC8260s.................................................. 23-5  
SCC Transparent Receive Buffer Descriptor (RxBD)............................................. 23-9  
SCC Transparent Transmit Buffer Descriptor (TxBD) ......................................... 23-11  
SCC Transparent Event Register (SCCE)/Mask Register (SCCM) ...................... 23-12  
SCC Status Register in Transparent Mode (SCCS)............................................... 23-13  
Ethernet Frame Structure......................................................................................... 24-1  
Ethernet Block Diagram .......................................................................................... 24-2  
Connecting the MPC8260 to Ethernet..................................................................... 24-5  
Ethernet Address Recognition Flowchart.............................................................. 24-12  
Ethernet Mode Register (PSMR)........................................................................... 24-15  
SCC Ethernet Receive RxBD ................................................................................ 24-17  
Ethernet Receiving using RxBDs .......................................................................... 24-19  
SCC Ethernet TxBD .............................................................................................. 24-20  
SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)............................ 24-21  
Ethernet Interrupt Events Example........................................................................ 24-22  
LocalTalk Frame Format ......................................................................................... 25-1  
Connecting the MPC8260 to LocalTalk.................................................................. 25-3  
SMC Block Diagram ............................................................................................... 26-2  
SMC Mode Registers (SMCMR1/SMCMR2)......................................................... 26-3  
SMC Memory Structure .......................................................................................... 26-5  
SMC Function Code Registers (RFCR/TFCR) ....................................................... 26-8  
SMC UART Frame Format ................................................................................... 26-11  
SMC UART RxBD................................................................................................ 26-14  
RxBD Example...................................................................................................... 26-16  
SMC UART TxBD................................................................................................ 26-17  
SMC UART Event Register (SMCE)/Mask Register (SMCM)............................ 26-18  
SMC UART Interrupts Example ........................................................................... 26-19  
Synchronization with SMSYNx.................................................................... 26-23  
Synchronization with the TSA............................................................................... 26-24  
SMC Transparent RxBD........................................................................................ 26-26  
SMC Transparent Event Register (SMCE)/Mask Register (SMCM).................... 26-28  
SMC Monitor Channel RxBD ............................................................................... 26-32  
SMC Monitor Channel TxBD ............................................................................... 26-32  
SMC C/I Channel RxBD ....................................................................................... 26-33  
SMC C/I Channel TxBD ....................................................................................... 26-33  
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26-19  
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27-2  
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27-8  
SMC GCI Event Register (SMCE)/Mask Register (SMCM)................................ 26-34  
BD Structure for One MCC..................................................................................... 27-3  
Super Channel Table Entry...................................................................................... 27-5  
Transmitter Super Channel Example....................................................................... 27-6  
Receiver Super Channel with Slot Synchronization Example ................................ 27-7  
Receiver Super Channel without Slot Synchronization Example ........................... 27-7  
TSTATE High Byte................................................................................................. 27-9  
INTMSK Mask Bits............................................................................................... 27-10  
Channel Mode Register (CHAMR)....................................................................... 27-10  
Rx Internal State (RSTATE) High Byte................................................................ 27-12  
Channel Mode Register (CHAMR)ÑTransparent Mode...................................... 27-14  
SI MCC Configuration Register (MCCF) ............................................................. 27-15  
Interrupt Circular Table ......................................................................................... 27-17  
MCC Event Register (MCCE)/Mask Register (MCCM) ...................................... 27-18  
Interrupt Circular Table Entry ............................................................................... 27-20  
MCC Receive Buffer Descriptor (RxBD) ............................................................. 27-21  
MCC Transmit Buffer Descriptor (TxBD)............................................................ 27-23  
FCC Block Diagram ................................................................................................ 28-3  
General FCC Mode Register (GFMR) .................................................................... 28-3  
FCC Memory Structure ........................................................................................... 28-9  
Buffer Descriptor Format ........................................................................................ 28-9  
Function Code Register (FCRx) ............................................................................ 28-13  
Output Delay from RTS Asserted.......................................................................... 28-16  
Output Delay from CTS Asserted.......................................................................... 28-17  
CTS Lost................................................................................................................ 28-18  
Using CD to Control Reception............................................................................. 28-19  
APC Scheduling Table Mechanism....................................................................... 29-10  
VBR Pacing Using the GCRA (Leaky Bucket Algorithm)................................... 29-12  
External CAM Data Input Fields........................................................................... 29-14  
External CAM Output Fields................................................................................. 29-14  
Address Compression Mechanism ........................................................................ 29-16  
General VCOFFSET Formula for Contiguous VCLTs......................................... 29-17  
VP Pointer Address Compression ......................................................................... 29-18  
VC Pointer Address Compression......................................................................... 29-18  
ATM Address Recognition Flowchart................................................................... 29-19  
MPC8260Õs ABR Basic Model ............................................................................. 29-20  
ABR Transmit Flow .............................................................................................. 29-22  
ABR Transmit Flow (Continued) .......................................................................... 29-23  
ABR Transmit Flow (Continued) .......................................................................... 29-24  
ABR Receive Flow................................................................................................ 29-25  
Rate Format for RM Cells ..................................................................................... 29-26  
Rate Formula for RM Cells ................................................................................... 29-26  
Performance Monitoring Cell Structure (FMCs and BRCs) ................................. 29-29  
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29-59  
29-60  
FMC, BRC Insertion.............................................................................................. 29-32  
Format of User-Defined Cells ............................................................................... 29-33  
External CAM Address in UDC Extended Address Mode ................................... 29-33  
ATM-to-TDM Interworking.................................................................................. 29-35  
VCI Filtering Enable Bits ...................................................................................... 29-40  
Global Mode Entry (GMODE).............................................................................. 29-41  
Example of a 1024-Entry Receive Connection Table ........................................... 29-43  
Receive Connection Table (RCT) Entry................................................................ 29-44  
AAL5 Protocol-Specific RCT ............................................................................... 29-46  
AAL5-ABR Protocol-Specific RCT...................................................................... 29-47  
AAL1 Protocol-Specific RCT ............................................................................... 29-48  
AAL0 Protocol-Specific RCT ............................................................................... 29-50  
Transmit Connection Table (TCT) Entry .............................................................. 29-51  
AAL5 Protocol-Specific TCT................................................................................ 29-54  
AAL1 Protocol-Specific TCT................................................................................ 29-54  
AAL0 Protocol-Specific TCT................................................................................ 29-55  
Transmit Connection Table Extension (TCTE)ÑVBR Protocol-Specific ........... 29-56  
UBR+ Protocol-Specific TCTE............................................................................. 29-57  
ABR Protocol-Specific TCTE ............................................................................... 29-58  
OAM Performance Monitoring Table ................................................................... 29-60  
ATM Pace Control Data Structure ........................................................................ 29-62  
The APC Scheduling Table Structure.................................................................... 29-63  
Control Slot............................................................................................................ 29-63  
Transmit Buffers and BD Table Example ............................................................. 29-65  
Receive Static Buffer Allocation Example............................................................ 29-66  
Receive Global Buffer Allocation Example.......................................................... 29-67  
Free Buffer Pool Structure..................................................................................... 29-67  
Free Buffer Pool Entry........................................................................................... 29-68  
AAL5 RxBD.......................................................................................................... 29-69  
AAL1 RxBD.......................................................................................................... 29-71  
AAL0 RxBD.......................................................................................................... 29-72  
User-Defined CellÑRxBD Extension................................................................... 29-74  
AAL5 TxBD .......................................................................................................... 29-74  
AAL1 TxBD .......................................................................................................... 29-76  
AAL0 TxBDs......................................................................................................... 29-77  
User-Defined CellÑTxBD Extension................................................................... 29-78  
AAL1 Sequence Number (SN) Protection Table .................................................. 29-78  
Interrupt Queue Structure ...................................................................................... 29-80  
Interrupt Queue Entry............................................................................................ 29-80  
UTOPIA Master Mode Signals ............................................................................. 29-82  
UTOPIA Slave Mode Signals................................................................................ 29-83  
FCC ATM Mode Register (FPSMR)..................................................................... 29-86  
ATM Event Register (FCCE)/FCC Mask Register (FCCM) ................................ 29-88  
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FCC Transmit Internal Rate Clocking................................................................... 29-89  
FCC Transmit Internal Rate Registers (FTIRRx).................................................. 29-89  
COMM_INFO Field .............................................................................................. 29-90  
AAL1 SRTS Generation Using External Logic .................................................... 29-91  
AAL1 SRTS Clock Recovery Using External Logic ............................................ 29-92  
Ethernet Frame Structure......................................................................................... 30-1  
Ethernet Block Diagram ......................................................................................... 30-3  
Connecting the MPC8260 to Ethernet..................................................................... 30-5  
Ethernet Address Recognition Flowchart.............................................................. 30-16  
FCC Ethernet Mode Registers (FPSMR) .............................................................. 30-20  
Ethernet Event Register (FCCE)/Mask Register (FCCM) .................................... 30-22  
Ethernet Interrupt Events Example........................................................................ 30-23  
Fast Ethernet Receive Buffer (RxBD)................................................................... 30-24  
Ethernet Receiving Using RxBDs ......................................................................... 30-26  
Fast Ethernet Transmit Buffer (TxBD).................................................................. 30-27  
HDLC Framing Structure ........................................................................................ 31-2  
HDLC Address Recognition Example..................................................................... 31-5  
HDLC Mode Register (FPSMR) ............................................................................. 31-8  
FCC HDLC Receiving Using RxBDs ................................................................... 31-10  
FCC HDLC Receive Buffer Descriptor (RxBD)................................................... 31-11  
FCC HDLC Transmit Buffer Descriptor (TxBD) ................................................. 31-12  
HDLC Event Register (FCCE)/Mask Register (FCCM)....................................... 31-14  
HDLC Interrupt Event Example............................................................................ 31-16  
FCC Status Register (FCCS) ................................................................................. 31-16  
In-Line Synchronization Pattern.............................................................................. 32-3  
Sending Transparent Frames between MPC8260s.................................................. 32-4  
SPI Block Diagram.................................................................................................. 33-1  
Single-Master/Multi-Slave Configuration............................................................... 33-3  
Multimaster Configuration ...................................................................................... 33-5  
SPMODEÑSPI Mode Register............................................................................... 33-6  
SPI Transfer Format with SPMODE[CP] = 0 ......................................................... 33-7  
SPI Transfer Format with SPMODE[CP] = 1 ......................................................... 33-7  
SPIE/SPIMÑSPI Event/Mask Registers................................................................. 33-9  
SPCOMÑSPI Command Register........................................................................ 33-10  
RFCR/TFCRÑFunction Code Registers .............................................................. 33-12  
SPI Memory Structure ........................................................................................... 33-13  
SPI RxBD .............................................................................................................. 33-14  
SPI TxBD............................................................................................................... 33-15  
I2C Controller Block Diagram................................................................................. 34-1  
I2C Master/Slave General Configuration ................................................................ 34-2  
I2C Transfer Timing ................................................................................................ 34-3  
I2C Master Write Timing......................................................................................... 34-4  
I2C Master Read Timing ......................................................................................... 34-5  
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35-7  
I2C Mode Register (I2MOD)................................................................................... 34-6  
I2C Address Register (I2ADD) ............................................................................... 34-7  
I2C Baud Rate Generator Register (I2BRG) ........................................................... 34-7  
I2C Event/Mask Registers (I2CER/I2CMR)........................................................... 34-8  
I2C Command Register (I2COM) ........................................................................... 34-9  
I2C Function Code Registers (RFCR/TFCR)........................................................ 34-11  
I2C Memory Structure ........................................................................................... 34-12  
I2C RxBD .............................................................................................................. 34-13  
I2C TxBD............................................................................................................... 34-14  
Port Open-Drain Registers (PODRAÐPODRD)...................................................... 35-2  
Port Data Registers (PDATAÐPDATD).................................................................. 35-3  
Port Data Direction Register (PDIR)....................................................................... 35-3  
Port Pin Assignment Register (PPARAÐPPARD) .................................................. 35-4  
Special Options Registers (PSORAÐPOSRD)......................................................... 35-5  
Port Functional Operation........................................................................................ 35-6  
Primary and Secondary Option Programming......................................................... 35-8  
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ii  
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1-1  
1-2  
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2-2  
2-3  
2-4  
2-5  
2-6  
2-7  
Acronyms and Abbreviated Terms............................................................................. lxi  
Terminology Conventions ....................................................................................... lxiv  
Instruction Field Conventions ................................................................................... lxv  
Acronyms and Abbreviated Terms...................................................................... I-lxviii  
MPC8260 Serial Protocols ........................................................................................ 1-9  
MPC8260 Serial Performance ................................................................................. 1-10  
HID0 Field Descriptions.......................................................................................... 2-12  
HID1 Field Descriptions.......................................................................................... 2-15  
HID2 Field Descriptions.......................................................................................... 2-15  
Exception Classifications for the Processor Core.................................................... 2-24  
Exceptions and Conditions ...................................................................................... 2-24  
Integer Divide Latency ............................................................................................ 2-30  
Major Differences between MPC8260Õs Core and the MPC603e UserÕs  
Manual.................................................................................................................. 2-30  
Internal Memory Map................................................................................................ 3-1  
Acronyms and Abbreviated Terms........................................................................... II-ii  
System Configuration and Protection Functions ....................................................... 4-2  
Interrupt Source Priority Levels ................................................................................ 4-9  
Encoding the Interrupt Vector ................................................................................. 4-14  
SICR Field Descriptions.......................................................................................... 4-18  
SIPRR Field Descriptions........................................................................................ 4-19  
SCPRR_H Field Descriptions.................................................................................. 4-20  
SCPRR_L Field Descriptions.................................................................................. 4-20  
SIEXR Field Descriptions ....................................................................................... 4-25  
BCR Field Descriptions........................................................................................... 4-26  
PPC_ACR Field Descriptions.................................................................................. 4-28  
LCL_ACR Field Descriptions ................................................................................. 4-30  
SIUMCR Register Field Descriptions ..................................................................... 4-32  
IMMR Field Descriptions........................................................................................ 4-34  
SYPCR Field Descriptions ...................................................................................... 4-35  
TESCR1 Field Descriptions .................................................................................... 4-36  
TESCR2 Field Descriptions .................................................................................... 4-38  
L_TESCR1 Field Descriptions................................................................................ 4-39  
L_TESCR2 Field Descriptions................................................................................ 4-40  
TMCNTSC Field Descriptions................................................................................ 4-40  
TMCNTAL Field Descriptions................................................................................ 4-42  
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PISCR Field Descriptions........................................................................................ 4-43  
PITC Field Descriptions .......................................................................................... 4-44  
PITR Field Descriptions .......................................................................................... 4-44  
SIU Pins Multiplexing Control................................................................................ 4-45  
Reset Causes .............................................................................................................. 5-1  
Reset Actions for Each Reset Source ........................................................................ 5-2  
RSR Field Descriptions ............................................................................................. 5-4  
RMR Field Descriptions............................................................................................ 5-5  
RSTCONF Connections in Multiple-MPC8260 Systems ......................................... 5-6  
Configuration EPROM Addresses............................................................................. 5-7  
Hard Reset Configuration Word Field Descriptions ................................................. 5-8  
Acronyms and Abbreviated Terms.........................................................................III-iii  
External Signals......................................................................................................... 6-3  
DP[0Ð7] Signal Assignments................................................................................... 7-15  
Terminology .............................................................................................................. 8-1  
Transfer Type Encoding .......................................................................................... 8-10  
Transfer Code Encoding.......................................................................................... 8-13  
Transfer Size Signal Encoding ................................................................................ 8-13  
Burst Ordering ......................................................................................................... 8-14  
Aligned Data Transfers............................................................................................ 8-15  
Unaligned Data Transfer Example (4-Byte Example)............................................. 8-16  
Data Bus Requirements For Read Cycle ................................................................. 8-18  
Data Bus Contents for Write Cycles........................................................................ 8-19  
Address and Size State Calculations........................................................................ 8-20  
Data Bus Contents for Extended Write Cycles........................................................ 8-21  
Data Bus Requirements for Extended Read Cycles ................................................ 8-21  
Address and Size State for Extended Transfers....................................................... 8-22  
Clock Default Modes................................................................................................. 9-2  
Clock Configuration Modes ...................................................................................... 9-2  
Dedicated PLL Pins ................................................................................................... 9-7  
SCCR Field Descriptions........................................................................................... 9-8  
SCMR Field Descriptions.......................................................................................... 9-9  
Number of PSDVAL Assertions Needed for TA Assertion.................................. 10-12  
60x Bus Memory Controller Registers.................................................................. 10-13  
BRx Field Descriptions.......................................................................................... 10-14  
ORx Field Descriptions (SDRAM Mode) ............................................................. 10-16  
ORxÑGPCM Mode Field Descriptions................................................................ 10-18  
Option Register (ORx)ÑUPM Mode.................................................................... 10-20  
PSDMR Field Descriptions ................................................................................... 10-21  
LSDMR Field Descriptions ................................................................................... 10-24  
Machine x Mode Registers (MxMR)..................................................................... 10-27  
MDR Field Descriptions........................................................................................ 10-29  
MAR Field Description ......................................................................................... 10-30  
10-1  
10-2  
10-3  
10-4  
10-5  
10-6  
10-7  
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10-10  
10-11  
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10-37  
10-38  
10-39  
10-40  
10-41  
10-42  
10-43  
12-1  
60x Bus-Assigned UPM Refresh Timer (PURT) .................................................. 10-30  
Local Bus-Assigned UPM Refresh Timer (LURT)............................................... 10-31  
60x Bus-Assigned SDRAM Refresh Timer (PSRT) ............................................. 10-31  
LSRT Field Descriptions ....................................................................................... 10-32  
MPTPR Field Descriptions.................................................................................... 10-32  
SDRAM Interface Signals ..................................................................................... 10-33  
SDRAM Interface Commands............................................................................... 10-35  
SDRAM Address Multiplexing (A0ÐA15)............................................................ 10-37  
SDRAM Address Multiplexing (A16ÐA31).......................................................... 10-38  
60x Address Bus Partition ..................................................................................... 10-48  
SDRAM Device Address Port during activate Command .................................... 10-49  
SDRAM Device Address Port during read/write Command................................. 10-49  
Register Settings (Page-Based Interleaving........................................................... 10-49  
60x Address Bus Partition ..................................................................................... 10-50  
SDRAM Device Address Port during activate Command .................................... 10-50  
SDRAM Device Address Port during read/write Command................................. 10-50  
Register Settings (Bank-Based Interleaving)......................................................... 10-51  
GPCM Interfaces Signals ...................................................................................... 10-51  
GPCM Strobe Signal Behavior.............................................................................. 10-52  
TRLX and EHTR Combinations ........................................................................... 10-58  
Boot Bank Field Values after Reset....................................................................... 10-62  
UPM Interfaces Signals ......................................................................................... 10-62  
UPM Routines Start Addresses ............................................................................. 10-65  
RAM Word Bit Settings ........................................................................................ 10-71  
MxMR Loop Field Usage...................................................................................... 10-76  
UPM Address Multiplexing................................................................................... 10-77  
60x Address Bus Partition ..................................................................................... 10-80  
DRAM Device Address Port during an activate command................................... 10-80  
Register Settings .................................................................................................... 10-80  
UPMs Attributes Example..................................................................................... 10-82  
UPMs Attributes Example..................................................................................... 10-90  
EDO Connection Field Value Example................................................................. 10-92  
TAP Signals............................................................................................................. 12-2  
Boundary Scan Bit Definition ................................................................................. 12-6  
Instruction Decoding ............................................................................................. 12-29  
Acronyms and Abbreviated Terms..........................................................................IV-v  
Possible MPC8260 Applications ............................................................................. 13-3  
Peripheral Prioritization........................................................................................... 13-6  
RISC Controller Configuration Register Field Descriptions................................... 13-8  
RTSCR Field Descriptions .................................................................................... 13-10  
RISC Microcode Revision Number....................................................................... 13-10  
CP Command Register Field Descriptions............................................................ 13-11  
CP Command Opcodes.......................................................................................... 13-13  
12-2  
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18-4  
18-5  
18-6  
18-7  
18-8  
18-9  
18-10  
18-11  
18-12  
18-13  
Command Descriptions ......................................................................................... 13-14  
Buffer Descriptor Format ...................................................................................... 13-17  
Parameter RAM..................................................................................................... 13-18  
RISC Timer Table Parameter RAM ...................................................................... 13-20  
SIx RAM Entry (MCC = 0)................................................................................... 14-11  
SIx RAM Entry (MCC = 1)................................................................................... 14-13  
SIx RAM Entry Descriptions................................................................................. 14-14  
SIxGMR Field Descriptions .................................................................................. 14-17  
SIxMR Field Descriptions ..................................................................................... 14-18  
SIxRSR Field Descriptions.................................................................................... 14-24  
SIxCMDR Field Description ................................................................................. 14-25  
SIxSTR Field Descriptions.................................................................................... 14-25  
IDL Signal Descriptions ........................................................................................ 14-27  
SIx RAM Entries for an IDL Interface.................................................................. 14-30  
GCI Signals............................................................................................................ 14-31  
SIx RAM Entries for a GCI Interface (SCIT Mode) ............................................. 14-34  
Clock Source Options.............................................................................................. 15-6  
CMXUAR Field Descriptions ................................................................................. 15-7  
CMXSI1CR Field Descriptions............................................................................. 15-11  
CMXSI2CR Field Descriptions............................................................................. 15-12  
CMXFCR Field Descriptions ................................................................................ 15-13  
CMXSCR Field Descriptions ................................................................................ 15-15  
CMXSMR Field Descriptions ............................................................................... 15-18  
BRGCx Field Descriptions...................................................................................... 16-3  
BRG External Clock Source Options ...................................................................... 16-4  
Typical Baud Rates for Asynchronous Communication ......................................... 16-5  
TGCR1 Field Descriptions ...................................................................................... 17-4  
TGCR2 Field Descriptions ...................................................................................... 17-5  
TMRIÐTMR4 Field Descriptions ............................................................................ 17-6  
TER Field Descriptions ........................................................................................... 17-9  
SDSR Field Descriptions......................................................................................... 18-3  
PDTEM and LDTEM Field Descriptions................................................................ 18-4  
IDMA Transfer Parameters ..................................................................................... 18-7  
IDMAx Parameter RAM ....................................................................................... 18-16  
DCM Field Descriptions........................................................................................ 18-18  
IDMA Channel Data Transfer Operation .............................................................. 18-20  
Valid Memory-to-Memory STS/DTS Values ....................................................... 18-21  
Valid STS/DTS Values for Peripherals ................................................................. 18-21  
IDSR/IDMR Field Descriptions ............................................................................ 18-23  
IDMA BD Field Descriptions................................................................................ 18-24  
IDMA Bus Exceptions........................................................................................... 18-27  
Parallel I/O Register ProgrammingÑPort C ......................................................... 18-28  
Parallel I/O Register ProgrammingÑPort A......................................................... 18-28  
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18-16  
19-1  
19-2  
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19-7  
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20-2  
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20-8  
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21-8  
21-9  
21-10  
22-1  
22-2  
22-3  
22-4  
22-5  
22-6  
22-7  
Parallel I/O Register ProgrammingÑPort D......................................................... 18-29  
Example: Peripheral-to-Memory ModeÑIDMA2................................................ 18-29  
Example: Memory-to-Peripheral Fly-By Mode (on 60x)ÐIDMA3....................... 18-30  
GSMR_H Field Descriptions................................................................................... 19-4  
GSMR_L Field Descriptions ................................................................................... 19-6  
TODR Field Descriptions...................................................................................... 19-10  
SCC Parameter RAM Map for All Protocols ........................................................ 19-13  
Parameter RAMÑSCC Base Addresses ............................................................... 19-15  
RFCRx /TFCRx Field Descriptions....................................................................... 19-16  
SCCx Event, Mask, and Status Registers ............................................................. 19-16  
Preamble Requirements......................................................................................... 19-24  
DPLL Codings....................................................................................................... 19-25  
UART-Specific SCC Parameter RAM Memory Map............................................. 20-4  
Transmit Commands................................................................................................ 20-6  
Receive Commands ................................................................................................. 20-7  
Control Character Table, RCCM, and RCCR Descriptions .................................... 20-9  
TOSEQ Field Descriptions.................................................................................... 20-10  
DSR Fields Descriptions........................................................................................ 20-12  
Transmission Errors............................................................................................... 20-12  
Reception Errors .................................................................................................... 20-13  
PSMR UART Field Descriptions .......................................................................... 20-14  
SCC UART RxBD Status and Control Field Descriptions ................................... 20-17  
SCC UART TxBD Status and Control Field Descriptions.................................... 20-18  
SCCE/SCCM Field Descriptions for UART Mode............................................... 20-21  
UART SCCS Field Descriptions ........................................................................... 20-22  
UART Control Characters for S-Records Example............................................... 20-24  
HDLC-Specific SCC Parameter RAM Memory Map............................................. 21-4  
Transmit Commands................................................................................................ 21-5  
Receive Commands ................................................................................................ 21-6  
Transmit Errors ...................................................................................................... 21-6  
Receive Errors ......................................................................................................... 21-6  
PSMR HDLC Field Descriptions ............................................................................ 21-7  
SCC HDLC RxBD Status and Control Field Descriptions ..................................... 21-9  
SCC HDLC TxBD Status and Control Field Descriptions.................................... 21-11  
SCCE/SCCM Field Descriptions........................................................................... 21-12  
HDLC SCCS Field Descriptions ........................................................................... 21-14  
SCC BISYNC Parameter RAM Memory Map........................................................ 22-4  
Transmit Commands................................................................................................ 22-5  
Receive Commands ................................................................................................. 22-5  
Control Character Table and RCCM Field Descriptions......................................... 22-7  
BSYNC Field Descriptions...................................................................................... 22-8  
BDLE Field Descriptions ........................................................................................ 22-9  
Receiver SYNC Pattern Lengths of the DSR .......................................................... 22-9  
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26-8  
26-9  
26-10  
26-11  
26-12  
26-13  
26-14  
26-15  
26-16  
Transmit Errors...................................................................................................... 22-10  
Receive Errors ....................................................................................................... 22-10  
PSMR Field Descriptions ...................................................................................... 22-11  
SCC BISYNC RxBD Status and Control Field Descriptions................................ 22-12  
SCC BISYNC TxBD Status and Control Field Descriptions................................ 22-14  
SCCE/SCCM Field Descriptions........................................................................... 22-16  
SCCS Field Descriptions ....................................................................................... 22-17  
Control Characters................................................................................................. 22-18  
Receiver SYNC Pattern Lengths of the DSR .......................................................... 23-3  
SCC Transparent Parameter RAM Memory Map ................................................... 23-7  
Transmit Commands................................................................................................ 23-7  
Receive Commands ................................................................................................. 23-8  
Transmit Errors........................................................................................................ 23-8  
Receive Errors ......................................................................................................... 23-8  
SCC Transparent RxBD Status and Control Field Descriptions ............................. 23-9  
SCC Transparent TxBD Status and Control Field Descriptions ........................... 23-11  
SCCE/SCCM Field Descriptions........................................................................... 23-12  
SCCS Field Descriptions ....................................................................................... 23-13  
SCC Ethernet Parameter RAM Memory Map......................................................... 24-8  
Transmit Commands.............................................................................................. 24-10  
Receive Commands ............................................................................................... 24-11  
Transmission Errors............................................................................................... 24-14  
Reception Errors .................................................................................................... 24-15  
PSMR Field Descriptions ...................................................................................... 24-16  
SCC Ethernet Receive RxBD Status and Control Field Descriptions................... 24-17  
SCC Ethernet Transmit TxBD Status and Control Field Descriptions.................. 24-20  
SCCE/SCCM Field Descriptions........................................................................... 24-21  
SMCMR1/SMCMR2 Field Descriptions ................................................................ 26-4  
SMC UART and Transparent Parameter RAM Memory Map................................ 26-6  
RFCR/TFCR Field Descriptions.............................................................................. 26-8  
Transmit Commands.............................................................................................. 26-12  
Receive Commands ............................................................................................... 26-13  
SMC UART Errors................................................................................................ 26-13  
SMC UART RxBD Field Descriptions ................................................................. 26-14  
SMC UART TxBD Field Descriptions.................................................................. 26-17  
SMCE/SMCM Field Descriptions......................................................................... 26-18  
SMC Transparent Transmit Commands ................................................................ 26-25  
SMC Transparent Receive Commands.................................................................. 26-25  
SMC Transparent Error Conditions....................................................................... 26-25  
SMC Transparent RxBD Field Descriptions ......................................................... 26-26  
SMC Transparent TxBD........................................................................................ 26-27  
SMC Transparent TxBD Field Descriptions ......................................................... 26-27  
SMCE/SMCM Field Descriptions......................................................................... 26-28  
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29-1  
29-2  
29-3  
29-4  
29-5  
29-6  
29-7  
29-8  
29-9  
SMC GCI Parameter RAM Memory Map............................................................. 26-30  
SMC GCI Commands............................................................................................ 26-32  
SMC Monitor Channel RxBD Field Descriptions................................................. 26-32  
SMC Monitor Channel TxBD Field Descriptions................................................. 26-33  
SMC C/I Channel RxBD Field Descriptions......................................................... 26-33  
SMC C/I Channel TxBD Field Descriptions......................................................... 26-34  
SMCE/SMCM Field Descriptions......................................................................... 26-34  
Global Multiple-Channel Parameters ...................................................................... 27-3  
Channel Extra Parameters........................................................................................ 27-5  
Channel-Specific Parameters for HDLC ................................................................. 27-8  
TSTATE High-Byte Field Descriptions .................................................................. 27-9  
CHAMR Field Descriptions .................................................................................. 27-10  
RSTATE High-Byte Field Descriptions................................................................ 27-12  
Channel-Specific Parameters for Transparent Operation...................................... 27-12  
CHAMR Field DescriptionsÑTransparent Mode................................................. 27-14  
MCCF Field Descriptions...................................................................................... 27-15  
Group Channel Assignments ................................................................................. 27-16  
Transmit Commands.............................................................................................. 27-16  
Receive Commands ............................................................................................... 27-17  
MCCE/MCCM Register Field Descriptions.......................................................... 27-19  
Interrupt Circular Table Entry Field Descriptions................................................. 27-20  
RxBD Field Descriptions....................................................................................... 27-21  
TxBD Field Descriptions....................................................................................... 27-23  
GFMR Register Field Descriptions ......................................................................... 28-4  
FCC Data Synchronization Register (FDSR).......................................................... 28-7  
FCC Transmit-on-Demand Register (TODR) ......................................................... 28-8  
TODR Field Descriptions........................................................................................ 28-8  
FCC Parameter RAM Common to All Protocols .................................................. 28-11  
FCRx Field Descriptions ....................................................................................... 28-13  
ATM Service Types................................................................................................. 29-9  
External CAM Input and Output Field Descriptions............................................. 29-15  
Field Descriptions for Address Compression........................................................ 29-16  
VCOFFSET Calculation Examples for Contiguous VCLTs................................. 29-17  
VP-Level Table Entry Address Calculation Example........................................... 29-17  
VC-Level Table Entry Address Calculation Example........................................... 29-18  
Fields and their Positions in RM Cells .................................................................. 29-26  
Pre-Assigned Header Values at the UNI ............................................................... 29-27  
Pre-Assigned Header Values at the NNI ............................................................... 29-28  
Performance Monitoring Cell Fields ..................................................................... 29-30  
ATM Parameter RAM Map................................................................................... 29-38  
UEAD_OFFSETs for Extended Addresses in the UDC Extra Header ................. 29-40  
VCI Filtering Enable Field Descriptions ............................................................... 29-40  
GMODE Field Descriptions .................................................................................. 29-41  
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29-50  
30-1  
Receive and Transmit Connection Table Sizes ..................................................... 29-42  
RCT Field Descriptions ......................................................................................... 29-45  
RCT Settings (AAL5 Protocol-Specific)............................................................... 29-47  
ABR Protocol-Specific RCT Field Descriptions................................................... 29-48  
AAL1 Protocol-Specific RCT Field Descriptions................................................. 29-49  
AAL0-Specific RCT Field Descriptions ............................................................... 29-50  
TCT Field Descriptions ......................................................................................... 29-52  
AAL5-Specific TCT Field Descriptions................................................................ 29-54  
AAL1-Specific TCT Field Descriptions................................................................ 29-55  
AAL0-Specific TCT Field Descriptions................................................................ 29-56  
VBR-Specific TCTE Field Descriptions ............................................................... 29-56  
UBR+ Protocol-Specific TCTE Field Descriptions .............................................. 29-57  
ABR-Specific TCTE Field Descriptions ............................................................... 29-58  
OAMÑPerformance Monitoring Table Field Descriptions.................................. 29-61  
APC Parameter Table ............................................................................................ 29-62  
APC Priority Table Entry ...................................................................................... 29-63  
Control Slot Field Description............................................................................... 29-64  
Free Buffer Pool Entry Field Descriptions ............................................................ 29-68  
Free Buffer Pool Parameter Table ......................................................................... 29-68  
Receive and Transmit Buffers ............................................................................... 29-69  
AAL5 RxBD Field Descriptions ........................................................................... 29-70  
AAL1 RxBD Field Descriptions ........................................................................... 29-72  
AAL0 RxBD Field Descriptions ........................................................................... 29-73  
AAL5 TxBD Field Descriptions............................................................................ 29-75  
AAL1 TxBD Field Descriptions............................................................................ 29-76  
AAL0 TxBD Field Descriptions............................................................................ 29-77  
UNI Statistics Table............................................................................................... 29-79  
Interrupt Queue Entry Field Description ............................................................... 29-81  
Interrupt Queue Parameter Table........................................................................... 29-81  
UTOPIA Master Mode Signal Descriptions.......................................................... 29-82  
UTOPIA Slave Mode Signals................................................................................ 29-84  
UTOPIA Loop-Back Modes.................................................................................. 29-85  
FCC ATM Mode Register (FPSMR)..................................................................... 29-86  
FCCE/FCCM Field Descriptions........................................................................... 29-88  
FTIRRx Field Descriptions.................................................................................... 29-89  
COMM_INFO Field Descriptions......................................................................... 29-90  
Flow Control Frame Structure................................................................................. 30-8  
Ethernet-Specific Parameter RAM.......................................................................... 30-9  
Transmit Commands.............................................................................................. 30-12  
Receive Commands ............................................................................................... 30-13  
RMON Statistics and Counters.............................................................................. 30-14  
Transmission Errors............................................................................................... 30-19  
Reception Errors .................................................................................................... 30-19  
30-2  
30-3  
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30-6  
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A-1  
FPSMR Ethernet Field Descriptions ..................................................................... 30-20  
FCCE/FCCM Field Descriptions........................................................................... 30-22  
RxBD Field Descriptions....................................................................................... 30-24  
Ethernet TxBD Field Definitions........................................................................... 30-27  
FCC HDLC-Specific Parameter RAM Memory Map............................................. 31-4  
Transmit Commands................................................................................................ 31-5  
Receive Commands ................................................................................................. 31-6  
HDLC Transmission Errors..................................................................................... 31-6  
HDLC Reception Errors ......................................................................................... 31-7  
FPSMR Field Descriptions...................................................................................... 31-8  
RxBD field Descriptions........................................................................................ 31-11  
HDLC TxBD Field Descriptions.......................................................................... 31-13  
FCCE/FCCM Field Descriptions........................................................................... 31-15  
FCCS Register Field Descriptions......................................................................... 31-17  
SPMODE Field Descriptions................................................................................... 33-6  
Example Conventions.............................................................................................. 33-8  
SPIE/SPIM Field Descriptions ................................................................................ 33-9  
SPCOM Field Descriptions ................................................................................... 33-10  
SPI Parameter RAM Memory Map ....................................................................... 33-10  
RFCR/TFCR Field Descriptions............................................................................ 33-12  
SPI Commands ...................................................................................................... 33-12  
SPI RxBD Status and Control Field Descriptions ................................................. 33-14  
SPI TxBD Status and Control Field Descriptions ................................................. 33-15  
I2MOD Field Descriptions ...................................................................................... 34-6  
I2ADD Field Descriptions....................................................................................... 34-7  
I2BRG Field Descriptions ....................................................................................... 34-8  
I2CER/I2CMR Field Descriptions .......................................................................... 34-8  
I2COM Field Descriptions ...................................................................................... 34-9  
I2C Parameter RAM Memory Map ......................................................................... 34-9  
RFCR/TFCR Field Descriptions............................................................................ 34-11  
I2C Transmit/Receive Commands......................................................................... 34-11  
I2C RxBD Status and Control Bits........................................................................ 34-13  
I2C TxBD Status and Control Bits ........................................................................ 34-14  
PODRx Field Descriptions ..................................................................................... 35-2  
PDIR Field Descriptions.......................................................................................... 35-3  
PPAR Field Descriptions......................................................................................... 35-4  
PSORx Field Descriptions....................................................................................... 35-5  
Port AÑDedicated Pin Assignment (PPARA = 1) ................................................. 35-8  
Port B Dedicated Pin Assignment (PPARB = 1)................................................... 35-12  
Port C Dedicated Pin Assignment (PPARC = 1)................................................... 35-14  
Port D Dedicated Pin Assignment (PPARD = 1) ................................................ 35-17  
User-Level PowerPC Registers (Non-SPRs)............................................................ A-1  
User-Level PowerPC SPRs....................................................................................... A-1  
A-2  
MOTOROLA  
Tables  
liii  
TABLES  
Table  
Number  
Page  
Number  
Title  
A-3  
A-4  
A-5  
Supervisor-Level PowerPC Registers (Non-SPR).................................................... A-2  
Supervisor-Level PowerPC SPRs............................................................................. A-2  
MPC8260-Specific Supervisor-Level SPRs............................................................. A-3  
liv  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
About This Book  
The primary objective of this manual is to help communications system designers build  
systems using the Motorola MPC8260 and to help software designers provide operating  
systems and user-level applications to take fullest advantage of the MPC8260.  
Although this book describes aspects regarding the PowerPCª architecture that are critical  
for understanding the MPC8260 core, it does not contain a complete description of the  
architecture. Where additional information might help the reader, references are made to  
The PowerPC Microprocessor Family: The Programming Environments. Ordering  
information for this book are provided in the section, ÒPowerPC Documentation.Ó  
The information in this book is subject to change without notice, as described in the  
disclaimers on the title page of this book. As with any technical documentation, it is the  
readersÕ responsibility to be sure they are using the most recent version of the  
documentation. For more information, contact your sales representative.  
Before Using this ManualÑImportant Note  
Before using this manual, determine whether it is the latest revision and if there are errata  
or addenda. To locate any published errata or updates for this document, refer to the world-  
wide web at http://www.motorola.com/netcomm.  
Audience  
This manual is intended for software and hardware developers and application  
programmers who want to develop products for the MPC8260. It is assumed that the reader  
has a basic understanding of computer networking, OSI layers, and RISC architecture. In  
addition, it is assumed that the reader has a basic understanding of the communications  
protocols described here. Where it is considered useful, additional sources are provided that  
provide in-depth discussions of such topics.  
MOTOROLA  
About This Book  
lv  
     
Organization  
Following is a summary and a brief description of the chapters of this manual:  
¥
Part I, ÒOverview,Ó provides a high-level description of the MPC8260, describing  
general operation and listing basic features.  
Ñ Chapter 1, ÒOverview,Ó provides a high-level description of MPC8260 functions  
and features. It roughly follows the structure of this book, summarizing the  
relevant features and providing references for the reader who needs additional  
information.  
Ñ Chapter 2, ÒPowerPC Processor Core,Ó provides an overview of the MPC8260  
core, summarizing topics described in further detail in subsequent chapters.  
Ñ Chapter 3, ÒMemory Map,Ó presents a table showing where MPC8260 registers  
are mapped in memory. It includes cross references that indicate where the  
registers are described in detail.  
¥
¥
Part II, ÒConÞguration and Reset,Ó describes start-up behavior of the MPC8260  
Ñ Chapter 4, ÒSystem Interface Unit (SIU),Ó describes the system conÞguration  
and protection functions which provide various monitors and timers, and the 60x  
bus conÞguration.  
Ñ Chapter 5, ÒReset,Ó describes the behavior of the MPC8260 at reset and start-up.  
Part III, ÒThe Hardware Interface,Ó describes external signals, clocking, memory  
control, and power management of the MPC8260.  
Ñ Chapter 6, ÒExternal Signals,Ó shows a functional pinout of the MPC8260 and  
describes the MPC8260 signals.  
Ñ Chapter 7, Ò60x Signals,Ó describes signals on the 60x bus.  
Ñ Chapter 8, ÒThe 60x Bus,Ó describes the operation of the bus used by PowerPC  
processors.  
Ñ Chapter 9, ÒClocks and Power Control,Ó describes the clocking architecture of  
the MPC8260.  
Ñ Chapter 10, ÒMemory Controller,Ó describes the memory controller, which  
controlling a maximum of eight memory banks shared between a general-  
purpose chip-select machine (GPCM) and three user-programmable machines  
(UPMs).  
Ñ Chapter 11, ÒSecondary (L2) Cache Support,Ó provides information about  
implementation and conÞguration of a level-2 cache.  
Ñ Chapter 12, ÒIEEE 1149.1 Test Access Port,Ó describes the dedicated user-  
accessible test access port (TAP), which is fully compatible with the IEEE  
1149.1 Standard Test Access Port and Boundary Scan Architecture.  
¥
Part IV, ÒCommunications Processor Module,Ó describes the conÞguration,  
clocking, and operation of the various communications protocols supported by the  
MPC8260.  
lvi  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Ñ Chapter 13, ÒCommunications Processor Module Overview,Ó provides a brief  
overview of the MPC8260 CPM.  
Ñ Chapter 14, ÒSerial Interface with Time-SlotAssigner,Ó describes the SIU, which  
controls system start-up, initialization and operation, protection, as well as the  
external system bus.  
Ñ Chapter 15, ÒCPM Multiplexing,Ó describes the CPM multiplexing logic (CMX)  
which connects the physical layerÑUTOPIA, MII, modem lines,  
Ñ Chapter 16, ÒBaud-Rate Generators (BRGs),Ó describes the eight independent,  
identical baud-rate generators (BRGs) that can be used with the FCCs, SCCs,  
and SMCs.  
Ñ Chapter 17, ÒTimers,Ó describes the MPC8260 timer implementation, which can  
be conÞgured as four identical 16-bit or two 32-bit general-purpose timers.  
Ñ Chapter 18, ÒSDMA Channels and IDMA Emulation,Ó describes the two  
physical serial DMA (SDMA) channels on the MPC8260.  
Ñ Chapter 19, ÒSerial Communications Controllers (SCCs),Ó describes the four  
serial communications controllers (SCC), which can be conÞgured  
independently to implement different protocols for bridging functions, routers,  
and gateways, and to interface with a wide variety of standard WANs, LANs, and  
proprietary networks.  
Ñ Chapter 20, ÒSCC UART Mode,Ó describes the MPC8260 implementation of  
universal asynchronous receiver transmitter (UART) protocol that is used for  
sending low-speed data between devices.  
Ñ Chapter 21, ÒSCC HDLC Mode,Ó describes the MPC8260 implementation of  
HDLC protocol.  
Ñ Chapter 22, ÒSCC BISYNC Mode,Ó describes the MPC8260 implementation of  
byte-oriented BISYNC protocol developed by IBM for use in networking  
products.  
Ñ Chapter 23, ÒSCC Transparent Mode,Ó describes the MPC8260 implementation  
of transparent mode (also called totally transparent mode), which provides a  
clear channel on which the SCC can send or receive serial data without bit-level  
manipulation.  
Ñ Chapter 24, ÒSCC Ethernet Mode,Ó describes the MPC8260 implementation of  
Ethernet protocol.  
Ñ Chapter 25, ÒSCCAppleTalk Mode,Ó describes the MPC8260 implementation of  
AppleTalk.  
Ñ Chapter 26, ÒSerial Management Controllers (SMCs),Ó describes two serial  
management controllers, full-duplex ports that can be conÞgured independently  
to support one of three protocolsÑUART, transparent, or general-circuit  
interface (GCI).  
MOTOROLA  
About This Book  
lvii  
Ñ Chapter 27, ÒMulti-Channel Controllers (MCCs),Ó describes the MPC8260Õs  
multi-channel controller (MCC), which handles up to 128 serial, full-duplex data  
channels.  
Ñ Chapter 28, ÒFast Communications Controllers (FCCs),Ó describes the  
MPC8260Õs fast communications controllers (FCCs), which are SCCs optimized  
for synchronous high-rate protocols.  
Ñ Chapter 29, ÒATM Controller,Ó describes the MPC8260 ATM controller, which  
provides the ATM and AAL layers of the ATM protocol. The ATM controller  
performs segmentation and reassembly (SAR) functions of AAL5, AAL1, and  
AAL0, and most of the common parts convergence sublayer (CP-CS) of these  
protocols.  
Ñ Chapter 30, ÒFast Ethernet Controller,Ó describes the MPC8260Õs  
implementation of the Ethernet IEEE 802.3 protocol.  
Ñ Chapter 31, ÒFCC HDLC Controller,Ó describes the FCC implementation of the  
HDLC protocol.  
Ñ Chapter 32, ÒFCC Transparent Controller,Ó describes the FCC implementation  
of the transparent protocol.  
Ñ Chapter 33, ÒSerial Peripheral Interface (SPI),Ó describes the serial peripheral  
interface, which allows the MPC8260 to exchange data between other MPC8260  
chips, the MC68360, the MC68302, the M68HC11, and M68HC05  
microcontroller families, and peripheral devices such as EEPROMs, real-time  
clocks, A/D converters, and ISDN devices.  
Ñ Chapter 34, ÒI2C Controller,Ó describes the MPC8260 implementation of the  
inter-integrated circuit (I2C¨) controller, which allows data to be exchanged with  
other I2C devices, such as microcontrollers, EEPROMs, real-time clock devices,  
and A/D converters.  
Ñ Chapter 35, ÒParallel I/O Ports,Ó describes the four general-purpose I/O  
ports AÐD. Each signal in the I/O ports can be conÞgured as a general-purpose  
I/O signal or as a signal dedicated to supporting communications devices, such  
as SMCs, SCCs. MCCs, and FCCs.  
¥
¥
Appendix A, ÒRegister Quick Reference Guide,Ó provides a quick reference to the  
registers incorporated in the PowerPC core.  
This book also includes an index and a glossary.  
lviii  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Suggested Reading  
This section lists additional reading that provides background for the information in this  
manual as well as general information about the PowerPC architecture.  
MPC8xx Documentation  
Supporting documentation for the MPC8260 can be accessed through the world-wide web  
at http://www.mot.com/netcomm. This documentation includes technical speciÞcations,  
reference materials, and detailed applications notes.  
PowerPC Documentation  
The PowerPC documentation is organized in the following types of documents:  
¥
UserÕs manualsÑThese books provide details about individual PowerPC  
implementations and are intended to be used in conjunction with The Programming  
Environments Manual. These include the following:  
Ñ PowerPC MPC603eª & EC603e RISC Microprocessor UserÕs Manual  
(Motorola order #: MPC603EUM/AD, Rev. 1)  
Ñ PowerPC 604ª RISC Microprocessor UserÕs Manual  
(Motorola order #: MPC604UM/AD)  
¥
Programming environments manualsÑThese books provide information about  
resources deÞned by the PowerPC architecture that are common to PowerPC  
processors. There are two versions, one that describes the functionality of the  
combined 32- and 64-bit architecture models and one that describes only the 32-bit  
model.  
Ñ PowerPC Microprocessor Family: The Programming Environments, Rev 1  
(Motorola order #: MPCFPE/AD)  
Ñ PowerPC Microprocessor Family: The Programming Environments for 32-Bit  
Microprocessors, Rev. 1 (Motorola order #: MPCFPE32B/AD)  
¥
PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors  
(Motorola order #: MPCBUSIF/AD) provides a detailed functional description of  
the 60x bus interface, as implemented on the PowerPC MPC601ª, MPC603e,  
MPC604, and MPC750 family of PowerPC microprocessors. This document is  
intended to help system and chip set developers by providing a centralized reference  
source to identify the bus interface presented by the 60x family of PowerPC  
microprocessors.  
¥
¥
PowerPC Microprocessor Family: The ProgrammerÕs Reference Guide  
(Motorola order #: MPCPRG/D) is a concise reference that includes the register  
summary, memory control model, exception vectors, and the PowerPC instruction  
set.  
PowerPC Microprocessor Family: The ProgrammerÕs Pocket Reference Guide  
(Motorola order #: MPCPRGREF/D). This feedlot card provides an overview of the  
PowerPC registers, instructions, and exceptions for 32-bit implementations.  
MOTOROLA  
About This Book  
lix  
     
¥
Application notesÑThese short documents contain useful information about  
speciÞc design issues useful to programmers and engineers working with PowerPC  
processors.  
For a current list of PowerPC documentation, refer to the world-wide web at  
http://www.mot.com/PowerPC.  
Conventions  
This document uses the following notational conventions:  
Bold entries in Þgures and tables showing registers and parameter  
RAM should be initialized by the user.  
Bold  
mnemonics  
Instruction mnemonics are shown in lowercase bold.  
italics  
Italics indicate variable command parameters, for example, bcctrx.  
Book titles in text are set in italics.  
0x0  
PreÞx to denote hexadecimal number  
0b0  
PreÞx to denote binary number  
rA, rB  
rD  
Instruction syntax used to identify a source GPR  
Instruction syntax used to identify a destination GPR  
REG[FIELD]  
Abbreviations or acronyms for registers or buffer descriptors are  
shown in uppercase text. SpeciÞc bits, Þelds, or numerical ranges  
appear in brackets. For example, MSR[LE] refers to the little-endian  
mode enable bit in the machine state register.  
x
In certain contexts, such as in a signal encoding or a bit Þeld,  
indicates a donÕt care.  
n
Â
&
|
Used to express an undeÞned numerical value  
NOT logical operator  
AND logical operator  
OR logical operator  
lx  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Acronyms and Abbreviations  
Table i contains acronyms and abbreviations used in this document. Note that the meanings  
for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an  
acronym stands may not be intuitively obvious.  
Table i. Acronyms and Abbreviated Terms  
Term  
A/D  
Meaning  
Analog-to-digital  
ALU  
ATM  
BD  
Arithmetic logic unit  
Asynchronous transfer mode  
Buffer descriptor  
BIST  
BPU  
BRI  
Built-in self test  
Branch processing unit  
Basic rate interface.  
Bus unit ID  
BUID  
CAM  
CEPT  
Content-addressable memory  
Conference des administrations Europeanes des Postes et Telecommunications (European  
Conference of Postal and Telecommunications Administrations).  
CMX  
CPM  
CR  
CPM multiplexing logic  
Communication processor module  
Condition register  
CRC  
Cyclic redundancy check  
CTR  
Count register  
DABR  
DAR  
Data address breakpoint register  
Data address register  
DEC  
Decrementer register  
DMA  
DPLL  
DRAM  
DSISR  
DTLB  
EA  
Direct memory access  
Digital phase-locked loop  
Dynamic random access memory  
Register used for determining the source of a DSI exception  
Data translation lookaside buffer  
Effective address  
EEST  
EPROM  
FPR  
Enhanced Ethernet serial transceiver  
Erasable programmable read-only memory  
Floating-point register  
FPSCR  
Floating-point status and control register  
MOTOROLA  
About This Book  
lxi  
     
Table i. Acronyms and Abbreviated Terms (Continued)  
Term  
FPU  
Meaning  
Floating-point unit  
GCI  
General circuit interface  
General-purpose chip-select machine  
General-purpose register  
Graphical user interface  
High-level data link control  
Inter-integrated circuit  
GPCM  
GPR  
GUI  
HDLC  
2
I C  
IDL  
Inter-chip digital link  
IEEE  
IrDA  
ISDN  
ITLB  
IU  
Institute of Electrical and Electronics Engineers  
Infrared Data Association  
Integrated services digital network  
Instruction translation lookaside buffer  
Integer unit  
JTAG  
LIFO  
LR  
Joint Test Action Group  
Last-in-Þrst-out  
Link register  
LRU  
LSB  
lsb  
Least recently used  
Least-signiÞcant byte  
Least-signiÞcant bit  
LSU  
MAC  
MESI  
MMU  
MSB  
msb  
MSR  
NaN  
NIA  
Load/store unit  
Multiply accumulate  
ModiÞed/exclusive/shared/invalidÑcache coherency protocol  
Memory management unit  
Most-signiÞcant byte  
Most-signiÞcant bit  
Machine state register  
Not a number  
Next instruction address  
Nonmultiplexed serial interface  
No operation  
NMSI  
No-op  
OEA  
OSI  
Operating environment architecture  
Open systems interconnection  
lxii  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Table i. Acronyms and Abbreviated Terms (Continued)  
Term  
PCI  
Meaning  
Peripheral component interconnect  
Personal Computer Memory Card International Association  
Processor identiÞcation register  
Primary rate interface  
PCMCIA  
PIR  
PRI  
PVR  
RISC  
RTOS  
RWITM  
Rx  
Processor version register  
Reduced instruction set computing  
Real-time operating system  
Read with intent to modify  
Receive  
SCC  
SCP  
SDLC  
SDMA  
SI  
Serial communication controller  
Serial control port  
Synchronous Data Link Control  
Serial DMA  
Serial interface  
SIMM  
SIU  
Signed immediate value  
System interface unit  
SMC  
SNA  
SPI  
Serial management controller  
Systems network architecture  
Serial peripheral interface  
Special-purpose register  
Registers available for general purposes  
Static random access memory  
Machine status save/restore register 0  
Machine status save/restore register 1  
Test access port  
SPR  
SPRGn  
SRAM  
SRR0  
SRR1  
TAP  
TB  
Time base register  
TDM  
TLB  
Time-division multiplexed  
Translation lookaside buffer  
Time-slot assigner  
TSA  
Tx  
Transmit  
UART  
UIMM  
Universal asynchronous receiver/transmitter  
Unsigned immediate value  
MOTOROLA  
About This Book  
lxiii  
Table i. Acronyms and Abbreviated Terms (Continued)  
Term  
UISA  
Meaning  
User instruction set architecture  
UPM  
USART  
USB  
VA  
User-programmable machine  
Universal synchronous/asynchronous receiver/transmitter  
Universal serial bus  
Virtual address  
VEA  
XER  
Virtual environment architecture  
Register used primarily for indicating conditions such as carries and overßows for integer operations  
PowerPC Architecture Terminology Conventions  
Table ii lists certain terms used in this manual that differ from the architecture terminology  
conventions.  
Table ii. Terminology Conventions  
The Architecture SpeciÞcation  
Data storage interrupt (DSI)  
This Manual  
DSI exception  
Extended mnemonics  
Instruction storage interrupt (ISI)  
Interrupt  
SimpliÞed mnemonics  
ISI exception  
Exception  
Privileged mode (or privileged state)  
Problem mode (or problem state)  
Real address  
Supervisor-level privilege  
User-level privilege  
Physical address  
Translation  
Relocation  
Storage (locations)  
Memory  
Storage (the act of)  
Access  
lxiv  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Table iii describes instruction Þeld notation conventions used in this manual.  
Table iii. Instruction Field Conventions  
The Architecture SpeciÞcation  
Equivalent to:  
BA, BB, BT  
BF, BFA  
D
crbA, crbB, crbD (respectively)  
crfD, crfS (respectively)  
d
DS  
ds  
FLM  
FM  
FXM  
CRM  
RA, RB, RT, RS  
rA, rB, rD, rS (respectively)  
SI  
SIMM  
U
IMM  
UI  
UIMM  
/, //, ///  
0...0 (shaded)  
MOTOROLA  
About This Book  
lxv  
   
lxvi  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part I  
Overview  
Intended Audience  
Part I is intended for readers who need a high-level understanding of the MPC8260.  
Contents  
Part I provides a high-level description of the MPC8260, describing general operation and  
listing basic features.  
¥
Chapter 1, ÒOverview,Ó provides a high-level description of MPC8260 functions  
and features. It roughly follows the structure of this book, summarizing the relevant  
features and providing references for the reader who needs additional information.  
¥
¥
Chapter 2, ÒPowerPC Processor Core,Ó provides an overview of the MPC8260 core.  
Chapter 3, ÒMemory Map,Ó presents a table showing where MPC8260 registers are  
mapped in memory. It includes cross references that indicate where the registers are  
described in detail.  
Conventions  
Part I uses the following notational conventions:  
mnemonics  
Instruction mnemonics are shown in lowercase bold.  
italics  
Italics indicate variable command parameters, for example, bcctrx.  
Book titles in text are set in italics.  
0x0  
PreÞx to denote hexadecimal number  
0b0  
PreÞx to denote binary number  
rA, rB  
rD  
Instruction syntax used to identify a source GPR  
Instruction syntax used to identify a destination GPR  
MOTOROLA  
Part I. Overview  
Part I-lxvii  
   
Part I. Overview  
REG[FIELD]  
Abbreviations or acronyms for registers or buffer descriptors are  
shown in uppercase text. SpeciÞc bits, Þelds, or numerical ranges  
appear in brackets. For example, MSR[LE] refers to the little-endian  
mode enable bit in the machine state register.  
x
In certain contexts, such as in a signal encoding or a bit Þeld,  
indicates a donÕt care.  
n
Indicates an undeÞned numerical value  
Acronyms and Abbreviations  
Table iv contains acronyms and abbreviations that are used in this document.  
Table iv. Acronyms and Abbreviated Terms  
Term  
ATM  
Meaning  
Asynchronous Mode  
BD  
Buffer descriptor  
BPU  
COP  
CP  
Branch processing unit  
Common on-chip processor  
Communications processor  
Communications processor module  
Cyclic redundancy check  
Count register  
CPM  
CRC  
CTR  
DABR  
DAR  
DEC  
DMA  
DPLL  
DRAM  
DTLB  
EA  
Data address breakpoint register  
Data address register  
Decrementer register  
Direct memory access  
Digital phase-locked loop  
Dynamic random access memory  
Data translation lookaside buffer  
Effective address  
FCCÔ  
FPR  
Fast communications controller  
Floating-point register  
GPCM  
GPR  
HDLC  
General-purpose chip-select machine  
General-purpose register  
High-level data link control  
Inter-integrated circuit  
2
I C  
IEEE  
Institute of Electrical and Electronics Engineers  
Part I-lxviii  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part I. Overview  
Table iv. Acronyms and Abbreviated Terms (Continued)  
Term  
ISDN  
Meaning  
Integrated services digital network  
Instruction translation lookaside buffer  
Integer unit  
ITLB  
IU  
JTAG  
LRU  
LSU  
MCC  
MII  
Joint Test Action Group  
Least recently used (cache replacement algorithm)  
Load/store unit  
Multi-channel controller  
Media-independent interface  
Memory management unit  
Machine state register  
MMU  
MSR  
NMSI  
OEA  
OSI  
Nonmultiplexed serial interface  
Operating environment architecture  
Open systems interconnection  
Peripheral component interconnect  
Reduced instruction set computing  
Real-time clock  
PCI  
RISC  
RTC  
RTOS  
Rx  
Real-time operating system  
Receive  
SCC  
SDLC  
SDMA  
SI  
Serial communications controller  
Synchronous data link control  
Serial DMA  
Serial interface  
SIU  
System interface unit  
SMC  
SPI  
Serial management controller  
Serial peripheral interface  
Special-purpose register  
Static random access memory  
Test access port  
SPR  
SRAM  
TAP  
TB  
Time base register  
TDM  
TLB  
TSA  
Time-division multiplexed  
Translation lookaside buffer  
Time-slot assigner  
MOTOROLA  
Part I. Overview  
Part I-lxix  
Part I. Overview  
Table iv. Acronyms and Abbreviated Terms (Continued)  
Term  
Meaning  
Tx  
Transmit  
UART  
UISA  
UPM  
VEA  
Universal asynchronous receiver/transmitter  
User instruction set architecture  
User-programmable machine  
Virtual environment architecture  
Part I-lxx  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Chapter 1  
Overview  
10  
10  
The MPC8260 PowerQUICC IIª is a versatile communications processor that integrates  
on one chip a high-performance PowerPCª RISC microprocessor, a very ßexible system  
integration unit, and many communications peripheral controllers that can be used in a  
variety of applications, particularly in communications and networking systems.  
The core is an embedded variant of the PowerPC MPC603eª microprocessor with 16  
Kbytes of instruction cache and 16 Kbytes of data cache and no ßoating-point unit (FPU).  
The system interface unit (SIU) consists of a ßexible memory controller that interfaces to  
almost any user-deÞned memory system, and many other peripherals making this device a  
complete system on a chip.  
The communications processor module (CPM) includes all the peripherals found in the  
MPC860, with the addition of three high-performance communication channels that  
support new emerging protocols (for example, 155-Mbps ATM and Fast Ethernet).  
MPC8260 has dedicated hardware that can handle up to 256 full-duplex, time-division-  
multiplexed logical channels  
This document describes the functional operation of MPC8260, with an emphasis on  
peripheral functions. Chapter 2, ÒPowerPC Processor Core,Ó is an overview of the PowerPC  
microprocessor core; detailed information about the core can be found in the MPC603e &  
EC603e RISC Microprocessors UserÕs Manual (order number: MPC603EUM/AD).  
1.1 Features  
The following is an overview of the MPC8260 feature set:  
¥
PowerPC dual-issue integer core  
Ñ A core version of the MPC603e microprocessor  
Ñ System core microprocessor supporting frequencies of 100Ð200 MHz  
Ñ Separate 16-Kbyte data and instruction caches:  
Ð Four-way set associative  
Ð Physically addressed  
Ð LRU replacement algorithm  
MOTOROLA  
Chapter 1. Overview  
1-1  
       
Part I. Overview  
Ñ PowerPC architecture-compliant memory management unit (MMU)  
Ñ Common on-chip processor (COP) test interface  
Ñ Supports bus snooping for cache coherency  
Ñ No ßoating-point unit (FPU). Floating-point arithmetic is not supported.  
Ñ Support for ßoating-point loads and stores.  
Ñ Support for cache locking.  
¥
Low-power (less than 2.5 W when fully operational at 133 MHz, 2-V internal and  
3.3-V I/O)  
¥
¥
Separate power supply for internal logic (2 V) and for I/O (3.3 V)  
Separate PLLs for PowerPC core and for the CPM  
Ñ PowerPC core and CPM can run at different frequencies for power/performance  
optimization  
Ñ Internal PowerPC core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1,  
3.5:1, 4:1, 5:1, 6:1 ratios  
Ñ Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1,  
6:1 ratios  
¥
64-bit data and 32-bit address 60x bus  
Ñ Bus supports multiple master designs  
Ñ Supports single transfers and burst transfers  
Ñ 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller  
Ñ Supports data parity or ECC and address parity  
32-bit data and 18-bit address local bus  
Ñ Single-master bus, supports external slaves  
Ñ Eight-beat burst transfers  
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¥
Ñ 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller  
System interface unit (SIU)  
Ñ Clock synthesizer  
Ñ Reset controller  
Ñ Real-time clock (RTC) register  
Ñ Periodic interrupt timer  
Ñ Hardware bus monitor and software watchdog timer  
Ñ IEEE 1149.1 JTAG test access port  
Twelve-bank memory controller  
¥
Ñ Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and  
other user-deÞnable peripherals  
1-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part I. Overview  
Ñ Byte write enables and selectable parity generation  
Ñ 32-bit address decodes with programmable bank size  
Ñ Three user programmable machines, general-purpose chip-select machine, and  
page mode pipeline SDRAM machine  
Ñ Byte selects for 64-bit bus width (60x) and for 32-bit bus width (local)  
Ñ Dedicated interface logic for SDRAM  
Disable CPU mode  
¥
¥
Communications processor module (CPM)  
Ñ Embedded 32-bit communications processor (CP) uses a RISC architecture for  
ßexible support for communications peripherals  
Ñ Interfaces to PowerPC core through on-chip 24-Kbyte dual-port RAM and DMA  
controller  
Ñ Serial DMA channels for receive and transmit on all serial channels  
Ñ Parallel I/O registers with open-drain and interrupt capability  
Ñ Virtual DMA functionality executing memory to memory and memory to I/O  
transfers  
Ñ Three fast communication controllers (FCCs) supporting the following protocols  
Ð 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media  
independent interface (MII)  
Ð ATMÑfull-duplex SAR at 155 Mbps, UTOPIA interface, AAL5, AAL1,  
AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR trafÞc types, up to 64 K  
external connections  
Ð Transparent  
Ð HDLCÑup to T3 rates (clear channel)  
Ñ Two multichannel controllers (MCCs)  
Ð Two 128 serial full-duplex data channels (for a total of 256 64 Kbps channels).  
Each MCC can be split into four subgroups of 32 channels each.  
Ð Almost any combination of subgroups can be multiplexed to single or  
multiple TDM interfaces  
Ñ Four serial communications controllers (SCCs) identical to those on the  
MPC860, supporting the digital portions of the following protocols:  
Ð Ethernet/IEEE 802.3 CDMA/CS  
Ð HDLC/SDLC and HDLC bus  
Ð Universal asynchronous receiver transmitter (UART)  
Ð Synchronous UART  
Ð Binary synchronous (BiSync) communications  
Ð Transparent  
MOTOROLA  
Chapter 1. Overview  
1-3  
Part I. Overview  
Ñ Two serial management controllers (SMCs), identical to those of the MPC860  
Ð Provide management for BRI devices as general-circuit interface (GCI)  
controllers in time- division-multiplexed (TDM) channels  
Ð Transparent  
Ð UART (low-speed operation)  
Ñ One serial peripheral interface identical to the MPC860 SPI  
2
2
Ñ One I C controller (identical to the MPC860 I C controller)  
Ð Microwire compatible  
Ð Multiple-master, single-master, and slave modes  
Ñ Up to eight TDM interfaces  
Ð Supports two groups of four TDM channels for a total of eight TDMs  
Ð 2,048 bytes of SI RAM  
Ð Bit or byte resolution  
Ð Independent transmit and receive routing, frame synchronization.  
Ð Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN  
basic rate, ISDN primary rate, Motorola interchip digital link (IDL), general  
circuit interface (GCI), and user-deÞned TDM serial interfaces  
Ñ Eight independent baud rate generators and 20 input clock pins for supplying  
clocks to FCC, SCC, and SMC serial channels  
Ñ Four independent 16-bit timers that can be interconnected as two 32-bit timers  
1.2 MPC8260Õs Architecture Overview  
The MPC8260 has two external buses to accommodate bandwidth requirements from the  
high-speed system core and the very fast communications channels. As shown in  
Figure 1-1, the MPC8260 has three major functional blocks:  
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¥
¥
A 64-bit PowerPC core derived from the MPC603e with MMUs and cache  
A system interface unit (SIU)  
A communications processor module (CPM)  
1-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part I. Overview  
16-Kbyte  
Instruction Cache  
60x Bus  
IMMU  
MPC603e  
PowerPC  
Core  
16-Kbyte  
Data Cache  
60x -to-Local Bus Bridge  
Memory Controller  
Bus Interface Unit  
Clock Counter  
DMMU  
Local  
Bus  
Timers  
Interrupt  
Controller  
24-Kbyte Dual  
Port RAM  
Serial DMAs  
Parallel I/O  
Baud Rate Gen.  
4 Virtual  
IDMAs  
32-Bit RISC Communications  
Processor (CP) and  
Program ROM  
System Functions  
2
MCC MCC FCC  
FCC  
FCC  
SCC SCC SCC SCC SMC SMC  
SPI  
I C  
Time Slot Assigner  
Serial Interface  
8 TDMs  
2 UTOPIA 3 MIIs  
Non-Multiplexed I/O  
Figure 1-1. MPC8260 Block Diagram  
Both the system core and the CPM have an internal PLL, which allows independent  
optimization of the frequencies at which they run. The system core and CPM are both  
connected to the 60x bus.  
1.2.1 MPC603e Core  
The MPC603e core is derived from the PowerPC MPC603e microprocessor without the  
ßoating-point unit and with power management modiÞcations. The core is a high-  
performance low-power implementation of the PowerPC family of reduced instruction set  
computer (RISC) microprocessors. The MPC603e core implements the 32-bit portion of  
the PowerPC architecture, which provides 32-bit effective addresses, integer data types of  
8, 16, and 32 bits. The MPC603e cache provides snooping to ensure data coherency with  
other masters. This helps ensure coherency between the CPM and system core.  
The core includes 16 Kbytes of instruction cache and 16 Kbytes of data cache. It has a 64-  
bit split-transaction external data bus, which is connected directly to the external MPC8260  
pins.  
MOTOROLA  
Chapter 1. Overview  
1-5  
   
Part I. Overview  
The MPC603e core has an internal common on-chip (COP) debug processor. This  
processor allows access to internal scan chains for debugging purposes. It is also used as a  
serial connection to the core for emulator support.  
The MPC603e core performance for the SPEC 95 benchmark for integer operations ranges  
between 4.4 and 5.1 at 200 MHz. In Dhrystone 2.1 MIPS, the MPC603e is 280 MIPS at  
200 MHz (compared to 86 MIPS of the MPC860 at 66 MHz).  
The MPC603e core can be disabled. In this mode, the MPC8260 functions as a slave  
peripheral to an external core or to another MPC8260 device with its core enabled.  
1.2.2 System Interface Unit (SIU)  
The SIU consists of the following:  
¥
A 60x-compatible parallel system bus conÞgurable to 64-bit data width. The  
MPC8260 supports 64-, 32-, 16-, and 8-bit port sizes. The MPC8260 internal arbiter  
arbitrates between internal components that can access the bus (system core, CPM,  
and one external master). This arbiter can be disabled, and an external arbiter can be  
used if necessary.  
¥
A local (32-bit data, 32-bit internal and 18-bit external address) bus. This bus is used  
to enhance the operation of the very high-speed communication controllers. Without  
requiring extensive manipulation by the core, the bus can be used to store connection  
tables for ATM or buffer descriptors (BDs) for the communication channels or raw  
data that is transmitted between channels. The local bus is synchronous to the 60x  
bus and runs at the same frequency.  
¥
Memory controller supporting 12 memory banks that can be allocated for either the  
system or the local bus. The memory controller is an enhanced version of the  
MPC860 memory controller. It supports three user-programmable machines.  
Besides all MPC860 features, the memory controller also supports SDRAM with  
page mode and address data pipeline.  
¥
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Supports JTAG controller IEEE 1149.1 test access port (TAP).  
A bus monitor that prevents 60x bus lock-ups, a real-time clock, a periodic interrupt  
timer, and other system functions useful in embedded applications.  
¥
Glueless interface to L2 cache (MPC2605) and 4-/16-K-entry CAM (MCM69C232/  
MCM69C432).  
1.2.3 Communications Processor Module (CPM)  
The CPM contains features that allow the MPC8260 to excel in a variety of applications  
targeted mainly for networking and telecommunication markets.  
The CPM is a superset of the MPC860 PowerQUICC CPM, with enhancements on the CP  
performance and additional hardware and microcode routines that support high bit rate  
protocols like ATM (up to 155 Mbps full-duplex) and Fast Ethernet (100-Mbps full-  
duplex).  
1-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part I. Overview  
The following list summarizes the major features of the CPM:  
¥
The CP is an embedded 32-bit RISC controller residing on a separate bus (CPM  
local bus) from the 60x bus (used by the system core). With this separate bus, the CP  
does not affect the performance of the PowerPC core. The CP handles the lower  
layer tasks and DMA control activities, leaving the PowerPC core free to handle  
higher layer activities. The CP has an instruction set optimized for communications,  
but can also be used for general-purpose applications, relieving the system core of  
small often repeated tasks.  
¥
¥
Two serial DMA (SDMA) that can do simultaneous transfers, optimized for burst  
transfers to the 60x bus and to the local bus.  
Three full-duplex, serial fast communications controllers (FCCs) supporting ATM  
(155 Mbps) protocol through UTOPIA2 interface (there are two UTOPIA interfaces  
on the MPC8260), IEEE 802.3 and Fast Ethernet protocols, HDLC up to E3 rates  
(45 Mbps) and totally transparent operation. Each FCC can be conÞgured to transmit  
fully transparent and receive HDLC or vice-versa.  
¥
Two multichannel controllers (MCCs) that can handle an aggregate of 256 X 64  
Kbps HDLC or transparent channels, multiplexed on up to eight TDM interfaces.  
The MCC also supports super-channels of rates higher than 64 Kbps and  
subchanneling of the 64-Kbps channels.  
¥
¥
Four full-duplex serial communications controllers (SCCs) supporting IEEE802.3/  
Ethernet, high- level synchronous data link control, HDLC, local talk, UART,  
synchronous UART, BISYNC, and transparent.  
Two full-duplex serial management controllers (SMC) supporting GCI, UART, and  
transparent operations  
2
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Serial peripheral interface (SPI) and I C bus controllers  
Time-slot assigner (TSA) that supports multiplexing of data from any of the four  
SCCs, three FCCs, and two SMCs.  
1.3 Software Compatibility Issues  
As much as possible, the MPC8260 CPM features were made similar to those of the  
previous devices (MPC860). The code ßow ports easily from previous devices to the  
MPC8260, except for new protocols supported by the MPC8260.  
Although many registers are new, most registers retain the old status and event bits, so an  
understanding of the programming models of the MC68360, MPC860, or MPC85015 is  
helpful. Note that the MPC8260 initialization code requires changes from the MPC860  
initialization code (Motorola provides reference code).  
1.3.1 Signals  
Figure 1-2 shows MPC8260 signals grouped by function. Note that many of these signals  
are multiplexed and this Þgure does not indicate how these signals are multiplexed.  
MOTOROLA  
Chapter 1. Overview  
1-7  
   
Part I. Overview  
NOTE  
A bar over a signal name indicates that the signal is active  
lowÑfor example, BB (bus busy). Active-low signals are  
referred to as asserted (active) when they are low and negated  
when they are high. Signals that are not active low, such as  
TSIZ[0Ð3] (transfer size signals) are referred to as asserted  
when they are high and negated when they are low.  
VCCSYN/GNDSYN/VCCSYN1//VDDH/VDD/  
¾¾¾>100  
32 <¾¾> A[0Ð31]  
VSS  
PAR/L_A14 <¾¾>  
SMI/FRAME/L_A15 <¾¾>  
1
1
1
1
1
1
1
1
5
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
<¾¾> TT[0Ð4]  
<¾¾> TSIZ[0Ð3]  
<¾¾> TBST  
TRDY/L_A16 <¾¾>  
CKSTOP_OUT/IRDY/L_A17 <¾¾>  
STOP/L_A18 <¾¾>  
<¾¾> GBL/IRQ1  
<¾¾> CI/BADDR29/IRQ2  
<¾¾> WT/BADDR30/IRQ3  
<¾¾¾ L2_HIT/IRQ4  
<¾¾> CPU_BG/BADDR31/IRQ5  
¾¾¾> CPU_DBG  
¾¾¾> CPU_BR  
<¾¾> BR  
DEVSEL/L_A19 <¾¾>  
IDSEL/L_A20 <¾¾>  
PERR/L_A21 <¾¾>  
L
O
C
A
L
SERR/L_A22 <¾¾>  
REQ0/L_A23 <¾¾>  
REQ1/L_A24 <¾¾>  
GNT0/L_A25 <¾¾>  
GNT1/L_A26 <¾¾¾  
CLK/L_A27 <¾¾>  
1
1
1
1
1
1
1
1
1
1
6
0
x
<¾¾> BG  
<¾¾> ABB/IRQ2  
<¾¾> TS  
<¾¾> AACK  
<¾¾> ARTRY  
<¾¾> DBG  
<¾¾> DBB/IRQ3  
P
O
W
E
R
Q
U
I
B
U
S
CORE_SRESET/RST/L_A28 <¾¾>  
INTA/L_A29 <¾¾>  
LOCK/L_A30 <¾¾>  
L_A31 <¾¾>  
AD[0–31]/LCL_D[0Ð31] <¾¾> 32  
B
U
S
64 <¾¾> D[0Ð63]  
1
1
1
1
1
1
1
1
1
1
1
1
1
<¾¾> NC/DP0/RSRV/EXT_BR2  
<¾¾> IRQ1/DP1/EXT_BG2  
<¾¾> IRQ2/DP2/TLBISYNC/EXT_DBG2  
<¾¾> IRQ3/DP3/CKSTP_OUT/EXT_BR3  
<¾¾> IRQ4/DP4/CORE_SRESET/EXT_BG3  
<¾¾> IRQ5/DP5/TBEN/EXT_DBG3  
<¾¾> IRQ6/DP6/CSE0  
<¾¾> IRQ7/DP7/CSE1  
<¾¾> PSDVAL  
<¾¾> TA  
<¾¾> TEA  
C/BE[0–3]/LCL_DP[0Ð3] <¾¾>  
LBS[0Ð3]/LSDDQM[0Ð3]/LWE[0Ð3] <¾¾¾  
4
4
LGPL0/LSDA10 <¾¾¾  
LGPL1/LSDWE <¾¾¾  
LGPL2/LSDRAS/LOE <¾¾¾  
LGPL3/LSDCAS <¾¾¾  
LPBS/LGPL4/LUPWAIT/LGTA <¾¾>  
LGPL5 <¾¾>  
1
1
1
1
1
1
1
M
E
M
C
LWR <¾¾>  
<¾¾> IRQ0/NMI_OUT  
<¾¾> IRQ7/INT_OUT/APE  
C
C
PA[0Ð31] <¾¾> 32  
PB[4Ð31] <¾¾> 28  
PC[0Ð31] <¾¾> 32  
PD[4Ð31] <¾¾> 28  
PORESET¾¾¾> 1  
RSTCONF¾¾¾> 1  
HRESET<¾¾>  
SRESET<¾¾>  
QREQ<¾¾¾ 1  
P
I
O
10 ¾¾¾> CS[0Ð9]  
1
1
2
1
1
8
1
1
1
1
1
1
1
1
1
1
1
<¾¾> CS[10]/BCTL1/DBG_DIS  
<¾¾> CS[11]/AP[0]  
¾¾¾> BADDR[27Ð28]  
¾¾¾> ALE  
M
E
M
C
1
1
¾¾¾> BCTL0  
II  
¾¾¾> PWE[0Ð7]/PSDDQM[0Ð7]/PBS[0Ð7]  
¾¾¾> PSDA10/PGPL0  
¾¾¾> PSDWE/PGPL1  
¾¾¾> POE/PSDRAS/PGPL2  
¾¾¾> PSDCAS/PGPL3  
<¾¾> PGTA/PUPMWAIT/PGPL4/PPBS  
¾¾¾> PSDAMUX/PGPL5  
<¾¾- TMS  
<¾¾¾TDI  
<¾¾- TCK  
<¾¾- TRST  
-¾¾> TDO  
R
S
T
XFC¾¾¾> 1  
CLKIN¾¾¾> 1  
TRIS¾¾¾> 1  
BNKSEL[0]/TC[0]/AP[1]/MODCK1<¾¾>  
BNKSEL[1]/TC[1]/AP[2]/MODCK2<¾¾>  
BNKSEL[2]/TC[2]/AP[3]/MODCK3<¾¾>  
C
L
K
1
1
1
J
T
A
G
TERM[0Ð1] ¾¾¾> 2  
NC ¾¾¾> 4  
Figure 1-2. MPC8260 External Signals  
1-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part I. Overview  
1.4 Differences between MPC860 and MPC8260  
The following MPC860 features are not included in the MPC8260.  
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¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
On-chip crystal oscillators (must use external oscillator)  
4-MHz oscillator (input clock must be at the bus speed)  
Low power (stand-by) modes  
Battery-backup real-time clock (must use external battery-backup clock)  
BDM (COP offers most of the same functionality)  
True little-endian mode  
PCMCIA interface  
Infrared (IR) port  
QMC protocol in SCC (256 HDLC channels are supported by the MCCs)  
Multiply and accumulate (MAC) block in the CPM  
Centronics port (PIP)  
Asynchronous HDLC protocol (optional RAM microcode)  
Pulse-width modulated outputs  
SCC Ethernet controller option to sample 1 byte from the parallel port when a  
receive frame is complete  
¥
Parallel CAM interface for SCC (Ethernet)  
1.5 Serial Protocol Table  
Table 1-1 summarizes available protocols for each serial port.  
Table 1-1. MPC8260 Serial Protocols  
Port  
Port  
FCC  
SCC  
MCC  
SMC  
ATM (Utopia)  
100BaseT  
10BaseT  
HDLC  
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
HDLC_BUS  
Transparent  
UART  
Ö
Ö
Ö
DPLL  
Multichannel  
Ö
MOTOROLA  
Chapter 1. Overview  
1-9  
     
Part I. Overview  
1.6 MPC8260 ConÞgurations  
The MPC8260 offers ßexibility in conÞguring the device for speciÞc applications. The  
functions mentioned in the above sections are all available in the device, but not all of them  
can be used at the same time. This does not imply that the device is not fully activated in  
any given implementation: The CPM architecture has the advantage of using common  
hardware resources for many different protocols, and applications. Two physical factors  
limit the functionality in any given systemÑpinout and performance.  
1.6.1 Pin ConÞgurations  
Some pins have multiple functions. Choosing one function may preclude the use of another.  
Information about multiplexing constraints can be found in Chapter 15, ÒCPM  
Multiplexing,Ó and Chapter 35, ÒParallel I/O Ports.Ó  
1.6.2 Serial Performance  
Serial performance depends on a number of factors:  
¥
¥
¥
¥
Serial rate versus CPM clock frequency for adequate sampling on serial channels  
Serial rate and protocol versus CPM clock frequency for CP protocol handling  
Serial rate and protocol versus bus bandwidth  
Serial rate and protocol versus system core clock for adequate protocol handling  
The second item above is addressed in this sectionÑthe CPÕs ability to handle high bit-rate  
protocols in parallel. Slow bit-rate protocols do not signiÞcantly affect those numbers.  
Table 1-2 describes a few options to conÞgure the fast communications channels on the  
MPC8260. The frequency speciÞed is the minimum CPM frequency necessary to run the  
mentioned protocols concurrently at full-duplex.  
Table 1-2. MPC8260 Serial Performance  
FCC1  
FCC2  
FCC3  
MCC  
CPM Clock  
60x Bus Clock  
155-Mbps ATM  
100 BaseT  
100 BaseT  
100 BaseT  
100 BaseT  
100 BaseT  
133 MHz  
133 MHz  
133 MHz  
133 MHz  
166 MHz  
133 MHz  
133 MHz  
166 MHz  
166 MHz  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
155-Mbps ATM  
100 BaseT  
128 * 64 Kbps channels  
128 * 64 Kbps channels  
256 * 64 Kbps channels  
256 * 64 Kbps channels  
256 * 64 Kbps  
100 BaseT  
155-Mbps ATM  
100 BaseT  
45-Mbps HDLC  
45-Mbps HDLC  
100 BaseT  
100 BaseT  
256 * 64 Kbps  
16 * 576 Kbps  
1-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part I. Overview  
FCCs can also be used to run slower HDLC or 10 BaseT, for example. The CPÕs RISC  
architecture has the advantage of using common hardware resources for all FCCs.  
1.7 MPC8260 Application Examples  
The MPC8260 can be conÞgured to meet many system application needs, as shown in the  
following sections.  
1.7.1 Examples of Communication Systems  
Communication examples:  
¥
¥
¥
¥
¥
¥
Remote access server  
Regional ofÞce router  
LAN-to-WAN bridge router  
Cellular base station  
Telecom switch controller  
SONET transmission controller  
1.7.1.1 Remote Access Server  
See Figure 1-3 for remote access server conÞguration.  
MPC8260  
SDRAM/DRAM/SRAM  
Quad  
T1  
TDM0  
TDM7  
60x Bus  
Channelized Data  
(up to 256 channels)  
Framer  
SDRAM/DRAM/SRAM  
155 Mbps  
ATM PHY  
UTOPIA Multi PHY  
10/100BaseT  
ATM  
Local Bus  
Connection Tables  
(optional)  
or  
or  
MII  
Transceiver  
DSP Bank  
E3 clear channel  
(takes one TDM)  
Framer  
Slaves  
on  
Slow  
Comm  
PHY  
2
Local  
Bus  
SMC/I C/SPI/SCC  
Figure 1-3. Remote Access Server Configuration  
MOTOROLA  
Chapter 1. Overview  
1-11  
       
Part I. Overview  
In this application, eight TDM ports are connected to external framers. In the MPC8260,  
each group of four ports support up to 128 channels. One TDM interface can support 32Ð  
128 channels. The MPC8260 receives and transmits data in transparent or HDLC mode,  
and stores or retrieves the channelized data from memory. The data can be stored either in  
memory residing on the 60x bus or in memory residing on the local bus.  
The main trunk can be conÞgured as 155 Mbps full-duplex ATM, using the UTOPIA  
interface, or as 10/100 BaseT Fast Ethernet with MII interface, or as a high-speed serial  
channel (up to 45 Mbps). In ATM mode, there may be a need to store connection tables in  
external memory on the local bus; for example, 128 active internal connections require 8  
Kbytes of dual-port RAM. The need for local bus depends on the total throughput of the  
system. The MPC8260 supports automatic (without software intervention) cross connect  
between ATM and MCC, routing ATM AAL1 frames to MCC slots.  
The local bus can be used as an interface to a bank of DSPs that can run code that performs  
analog modem signal modulation. Data to and from the DSPs can be transferred through  
the parallel bus with the internal virtual IDMA.  
The MPC8260 memory controller supports many types of memories, including EDO  
DRAM and page-mode, pipeline SDRAM for efÞcient burst transfers.  
1.7.1.2 Regional OfÞce Router  
Figure 1-4 shows a regional ofÞce router conÞguration.  
MPC8260  
TDM0  
Quad  
T1  
Framer  
TDM3  
SDRAM/DRAM/SRAM  
MII  
10/100BaseT  
10/100BaseT  
60x Bus  
Channelized Data  
Transceiver  
(up to 128 channels)  
Slow  
Comm  
PHY  
2
SMC/I C/SPI/SCC  
Figure 1-4. Regional Office Router Configuration  
1-12  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part I. Overview  
In this application, the MPC8260 is connected to four TDM interfaces channalizing up to  
128 channels. Each TDM port supports 32Ð128 channels. If 128 channels are needed, each  
TDM port can be conÞgured to support 32 channels. This example has two MII ports for  
10/100 BaseT LAN connections. In all the examples, the SCC ports can be used for  
management.  
1.7.1.3 LAN-to-WAN Bridge Router  
Figure 1-5 shows a LAN-to-WAN router conÞguration, which is similar to the previous  
example.  
MPC8260  
MII  
10/100BaseT  
Transceiver  
SDRAM/DRAM/SRAM  
155 Mbps  
UTOPIA Multi PHY  
ATM PHY  
60x Bus  
Data  
155 Mbps  
ATM PHY  
SDRAM/DRAM/SRAM  
UTOPIA Multi PHY  
10/100BaseT  
or  
Local Bus  
ATM Connection  
Tables (optional)  
MII  
Transceiver  
Slow  
Comm  
PHY  
2
SMC/I C/SPI/SCC  
Figure 1-5. LAN-to-WAN Bridge Router Configuration  
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Chapter 1. Overview  
1-13  
   
Part I. Overview  
1.7.1.4 Cellular Base Station  
Figure 1-6 shows a cellular base station conÞguration.  
MPC8260  
SDRAM/DRAM/SRAM  
TDM0  
Framer  
60x Bus  
Channelized Data  
(up to 256 channels)  
TDM1  
DSP Bank  
Local Bus  
Slow  
Slaves  
on  
Comm  
2
SMC/I C/SPI/SCC  
Local  
Bus  
PHY  
Figure 1-6. Cellular Base Station Configuration  
Here the MPC8260 channelizes two E1s (up to 256, 16-Kbps channels).  
The local bus can control a bank of DSPs. Data to and from the DSPs can be transferred  
through the parallel bus to the host port of the DSPs with the internal virtual IDMA.  
2
The slow communication ports (SCCs, SMCs, I C, SPI) can be used for management and  
debug functions.  
1.7.1.5 Telecommunications Switch Controller  
Figure 1-7 shows a telecommunications switch controller conÞguration.  
MPC8260  
155 Mbps  
UTOPIA Multi PHY  
ATM  
PHY  
SDRAM/DRAM/SRAM  
60x Bus  
10/100BaseT  
10/100BaseT  
MII  
Transceiver  
SDRAM/DRAM/SRAM  
ATM  
Connection  
Tables  
Local Bus  
Slow  
Comm  
PHY  
2
SMC/I C/SPI/SCC  
(10BaseT)  
Figure 1-7. Telecommunications Switch Controller Configuration  
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Part I. Overview  
The MPC8260 CPM supports a total aggregate throughput of 710 Mbps at 133 MHz. This  
includes two full-duplex 100 BaseT and one full-duplex 155 Mbps forATM. The MPC603e  
core can operate at a different (higher) speed, if the application requires it.  
1.7.1.6 SONET Transmission Controller  
Figure 1-8 shows a SONET transmission controller conÞguration.  
MPC8260  
TDM0  
TDM3  
576 Kbps  
SONET  
Transceivers  
SDRAM/DRAM/SRAM  
60x Bus  
Channelized Data  
(up to 16 channels)  
MII  
10/100BaseT  
Transceiver  
SDRAM/DRAM/SRAM  
ATM  
Connection  
Tables  
Local Bus  
Slow  
Comm  
PHY  
2
SMC/I C/SPI/SCC  
(10BaseT)  
Figure 1-8. SONET Transmission Controller ConÞguration  
In this application, the MPC8260 implements super channeling with the MCC. Nine 64-  
Kbps channels are combined to form a 576-Kbps channel. The MPC8260 at 133 MHz can  
support up to sixteen 576-Kbps superchannels. The MPC8260 also supports subchanneling  
(under 64 Kbps) with its MCC.  
1.7.2 Bus ConÞgurations  
The following sections describe the following possible bus conÞgurations:  
¥
¥
¥
Basic system  
High-performance communication system  
High-performance system core  
1.7.2.1 Basic System  
In the basic system conÞguration., shown in Figure 1-9, the MPC8260 core is enabled and  
uses the 64-bit 60x data bus. The 32-bit local bus data is needed to store connection tables  
for many active ATM connections. The local bus may also be used to store data that does  
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Chapter 1. Overview  
1-15  
       
Part I. Overview  
not need to be heavily processed by the core. The CP can store large data frames in the local  
memory without interfering with the operation of the system core.  
MPC8260  
SDRAM/SRAM/DRAM/Flash  
60x Bus  
PHY  
Communication  
Channels  
SDRAM/SRAM/DRAM  
155 Mbps  
Local Bus  
ATM  
UTOPIA  
ATM  
PHY  
Connection Tables  
Figure 1-9. Basic System Configuration  
1.7.2.2 High-Performance Communication  
Figure 1-10 shows a high-performance communication conÞguration.  
MPC8260 A  
SDRAM/SRAM/DRAM  
Local Bus  
ATM  
Communication  
Channels  
PHY  
Connection Tables  
SDRAM/SRAM/DRAM/Flash  
155 Mbps  
60x Bus  
UTOPIA  
ATM  
PHY  
MPC8260 B  
(master/slave)  
Communication  
Channels  
PHY  
SDRAM/SRAM/DRAM  
155 Mbps  
ATM  
Local Bus  
ATM  
UTOPIA  
PHY  
Connection Tables  
Figure 1-10. High-Performance Communication  
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Part I. Overview  
Serial throughput is enhanced by connecting one MPC8260 in master or slave mode (with  
system core enabled or disabled) to another MPC8260 in master mode with the core  
enabled. The core in MPC8260 A can access the memory on the local bus of MPC8260 B.  
1.7.2.3 High-Performance System Microprocessor  
Figure 1-11 shows a conÞguration with a high-performance system microprocessor  
(MPC750).  
MPC750  
32-Kbyte I cache  
32-Kbyte D cache  
Backside  
Cache  
MPC8260 (slave)  
SDRAM/SRAM/DRAM  
60x Bus  
Communication  
Channels  
PHY  
SDRAM/SRAM/DRAM  
155 Mbps  
Local Bus  
ATM  
Connection Tables  
UTOPIA  
ATM  
PHY  
Figure 1-11. High-Performance System Microprocessor Configuration  
In this system, the MPC603e core internal is disabled and an external high-performance  
microprocessor is connected to the 60x bus.  
MOTOROLA  
Chapter 1. Overview  
1-17  
   
Part I. Overview  
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MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Chapter 2  
PowerPC Processor Core  
20  
20  
The MPC8260 contains an embedded version of the PowerPC 603eª processor. This  
chapter provides an overview of the basic functionality of the processor core. For detailed  
information regarding the processor refer to the following:  
¥
MPC603e & EC603e UserÕs Manual (Those chapters that describe the  
programming model, cache model, memory management model, exception model,  
and instruction timing)  
¥
PowerPCª Microprocessor Family: The Programming Environments for 32-Bit  
Microprocessors  
This section describes the details of the processor core, provides a block diagram showing  
the major functional units, and describes brießy how those units interact.  
The signals associated with the processor core are described individually in Chapter 7, Ò60x  
Signals.Ó Chapter 8, ÒThe 60x Bus,Ó describes how those signals interact.  
2.1 Overview  
The processor core is a low-power implementation of the PowerPC microprocessor family  
of reduced instruction set computing (RISC) microprocessors. The processor core  
implements the 32-bit portion of the PowerPC architecture, which supports 32-bit effective  
addresses.  
Figure 2-1 is a block diagram of the processor core.  
MOTOROLA  
Chapter 2. PowerPC Processor Core  
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Part I. Overview  
64 Bit  
Branch  
Processing  
Unit  
64 Bit  
Sequential  
Fetcher  
64 Bit  
CTR  
CR  
LR  
Instruction  
Queue  
64 Bit  
Dispatch Unit  
64 Bit  
Instruction Unit  
32 Bit  
64 Bit  
Integer  
Unit  
Load/Store  
Unit  
System  
Register  
Unit  
GPR File  
FPR File  
/
+
*
GPR  
Rename  
Registers  
FPR  
Rename  
Registers  
+
+
XER  
32 Bit  
Completion  
Unit  
Data MMU  
Instruction MMU  
64 Bit  
SRs  
SRs  
DBAT  
Array  
IBAT  
Array  
ITLB  
DTLB  
Power  
Dissipation  
Control  
Time Base  
Counter/  
Decrementer  
16-Kbyte  
D Cache  
16-Kbyte  
Tags  
I Cache  
Tags  
JTAG/COP  
Interface  
Clock  
Multiplier  
Touch Load Buffer  
Copyback Buffer  
60x Bus  
Interface  
32-Bit Address Bus  
64-Bit Data Bus  
Figure 2-1. MPC8260 Integrated Processor Core Block Diagram  
The processor core is a superscalar processor that can issue and retire as many as three  
instructions per clock. Instructions can execute out of order for increased performance;  
however, the processor core makes completion appear sequential.  
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Part I. Overview  
The processor core integrates four execution unitsÑan integer unit (IU), a branch  
processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The  
ability to execute four instructions in parallel and the use of simple instructions with rapid  
execution times yield high efÞciency and throughput. Most integer instructions execute in  
one clock cycle.  
The processor core supports integer data types of 8, 16, and 32 bits, and ßoating-point data  
types of 32 and 64 bits. Note that although the MPC8260 does not implement a ßoating-  
point arithmetic unit, it does retain the 32 architecturally-deÞned ßoating point registers  
(FPRs), which can be used to hold 32, 64-bit operands that can in turn be transferred to and  
from the 32 general-purpose registers (GPRs), which can hold 32, 32-bit operands.  
The processor core provides separate on-chip, 16-Kbyte, four-way set-associative,  
physically addressed caches for instructions and data and on-chip instruction and data  
memory management units (MMUs). The MMUs contain 64-entry, two-way set-  
associative, data and instruction translation lookaside buffers (DTLB and ITLB) that  
provide support for demand-paged virtual memory address translation and variable-sized  
block translation. The TLBs and caches use a least recently used (LRU) replacement  
algorithm. The processor core also supports block address translation through the use of  
two independent instruction and data block address translation (IBAT and DBAT) arrays of  
four entries each. Effective addresses are compared simultaneously with all four entries in  
the BAT array during block translation. In accordance with the PowerPC architecture, if an  
effective address hits in both the TLB and BAT array, the BAT translation takes priority.  
As an added feature to the MPC603e core, the MPC8260 can lock the contents of 1Ð3 ways  
in the instruction and data cache (or an entire cache). For example, this allows embedded  
applications to lock interrupt routines or other important (time-sensitive) instruction  
sequences into the instruction cache. It allows data to be locked into the data cache, which  
may be important to code that must have deterministic execution.  
The processor core has a 60x bus that incorporates a 64-bit data bus and a 32-bit address  
bus. The processor core supports single-beat and burst data transfers for memory accesses  
and supports memory-mapped I/O operations.  
2.2 PowerPC Processor Core Features  
This section describes the major features of the processor core:  
¥
High-performance, superscalar microprocessor  
Ñ As many as three instructions issued and retired per clock cycle  
Ñ As many as four instructions in execution per clock cycle  
Ñ Single-cycle execution for most instructions  
MOTOROLA  
Chapter 2. PowerPC Processor Core  
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Part I. Overview  
¥
Four independent execution units and two register Þles  
Ñ BPU featuring static branch prediction  
Ñ A 32-bit IU  
Ñ LSU for data transfer between data cache and GPRs and FPRs  
Ñ SRU that executes condition register (CR), special-purpose register (SPR), and  
integer add/compare instructions  
Ñ Thirty-two GPRs for integer operands  
Ñ Thirty-two FPRs. These can be used for operands for ßoating-point load and  
store operands,  
¥
High instruction and data throughput  
Ñ Zero-cycle branch capability (branch folding)  
Ñ Programmable static branch prediction on unresolved conditional branches  
Ñ BPU that performs CR lookahead operations  
Ñ Instruction fetch unit capable of fetching two instructions per clock from the  
instruction cache  
Ñ A six-entry instruction queue that provides lookahead capability  
Ñ Independent pipelines with feed-forwarding that reduces data dependencies in  
hardware  
Ñ 16-Kbyte data cacheÑfour-way set-associative, physically addressed; LRU  
replacement algorithm  
Ñ 16-Kbyte instruction cacheÑfour-way set-associative, physically addressed;  
LRU replacement algorithm  
Ñ Cache write-back or write-through operation programmable on a per page or per  
block basis  
Ñ Address translation facilities for 4-Kbyte page size, variable block size, and  
256-Mbyte segment size  
Ñ A 64-entry, two-way set-associative ITLB  
Ñ A 64-entry, two-way set-associative DTLB  
Ñ Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte  
blocks  
Ñ Software table search operations and updates supported through fast trap  
mechanism  
Ñ 52-bit virtual address; 32-bit physical address  
Facilities for enhanced system performance  
¥
Ñ A 32- or 64-bit, split-transaction external data bus with burst transfers  
Ñ Support for one-level address pipelining and out-of-order bus transactions  
Ñ Hardware support for misaligned little-endian accesses  
Ñ Added bus multipliers of 4.5x, 5x, 5.5x, 6x, 6.5x 7x, 7.5x, 8x. See Figure 2-3.  
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Part I. Overview  
¥
¥
Integrated power management  
Ñ Three power-saving modes: doze, nap, and sleep  
Ñ Automatic dynamic power reduction when internal functional units are idle  
Deterministic behavior and debug features  
Ñ On-chip cache locking options for the instruction and data caches (1Ð3 ways or  
the entire cache contents can be locked)  
Ñ In-system testability and debugging features through JTAG and boundary-scan  
capability  
Figure 2-1 shows how the execution unitsÑIU, BPU, LSU, and SRUÑoperate  
independently and in parallel. Note that this is a conceptual diagram and does not attempt  
to show how these features are physically implemented on the chip.  
The processor core provides address translation and protection facilities, including an  
ITLB, DTLB, and instruction and data BAT arrays. Instruction fetching and issuing is  
handled in the instruction unit. The MMUs translate addresses for cache or external  
memory accesses.  
2.2.1 Instruction Unit  
As shown in Figure 2-1, the instruction unit, which contains a fetch unit, instruction queue,  
dispatch unit, and the BPU, provides centralized control of instruction ßow to the execution  
units. The instruction unit determines the address of the next instruction to be fetched based  
on information from the sequential fetcher and from the BPU.  
The instruction unit fetches the instructions from the instruction cache into the instruction  
queue. The BPU extracts branch instructions from the fetcher and uses static branch  
prediction on unresolved conditional branches to allow the instruction unit to fetch  
instructions from a predicted target instruction stream while a conditional branch is  
evaluated. The BPU folds out branch instructions for unconditional branches or conditional  
branches unaffected by instructions in progress in the execution pipeline.  
Instructions issued beyond a predicted branch do not complete execution until the branch  
is resolved, preserving the programming model of sequential execution. If any of these  
instructions are to be executed in the BPU, they are decoded but not issued. Instructions to  
be executed by the IU, LSU, and SRU are issued and allowed to complete up to the register  
write-back stage. Write-back is allowed when a correctly predicted branch is resolved, and  
instruction execution continues without interruption on the predicted path. If branch  
prediction is incorrect, the instruction unit ßushes all predicted path instructions, and  
instructions are issued from the correct path.  
2.2.2 Instruction Queue and Dispatch Unit  
The instruction queue (IQ), shown in Figure 2-1, holds as many as six instructions and  
loads up to two instructions from the instruction unit during a single cycle. The instruction  
fetch unit continuously loads as many instructions as space in the IQ allows. Instructions  
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Chapter 2. PowerPC Processor Core  
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Part I. Overview  
are dispatched to their respective execution units from the dispatch unit at a maximum rate  
of two instructions per cycle. Reservation stations at the IU, LSU, and SRU facilitate  
instruction dispatch to those units. The dispatch unit checks for source and destination  
register dependencies, determines dispatch serializations, and inhibits subsequent  
instruction dispatching as required. Section 2.7, ÒInstruction Timing,Ó describes instruction  
dispatch in detail.  
2.2.3 Branch Processing Unit (BPU)  
The BPU receives branch instructions from the fetch unit and performs CR lookahead  
operations on conditional branches to resolve them early, achieving the effect of a zero-  
cycle branch in many cases.  
The BPU uses a bit in the instruction encoding to predict the direction of the conditional  
branch. Therefore, when an unresolved conditional branch instruction is encountered,  
instructions are fetched from the predicted target stream until the conditional branch is  
resolved.  
The BPU contains an adder to compute branch target addresses and three user-control  
registersÑthe link register (LR), the count register (CTR), and the CR. The BPU calculates  
the return pointer for subroutine calls and saves it into the LR for certain types of branch  
instructions. The LR also contains the branch target address for the Branch Conditional to  
Link Register (bclrx) instruction. The CTR contains the branch target address for the  
Branch Conditional to Count Register (bcctrx) instruction. The contents of the LR and  
CTR can be copied to or from any GPR. Because the BPU uses dedicated registers rather  
than GPRs or FPRs, execution of branch instructions is largely independent from execution  
of other instructions.  
2.2.4 Independent Execution Units  
The PowerPC architectureÕs support for independent execution units allows  
implementation of processors with out-of-order instruction execution. For example,  
because branch instructions do not depend on GPRs or FPRs, branches can often be  
resolved early, eliminating stalls caused by taken branches.  
In addition to the BPU, the processor core provides three other execution units and a  
completion unit, which are described in the following sections.  
2.2.4.1 Integer Unit (IU)  
The IU executes all integer instructions. The IU executes one integer instruction at a time,  
performing computations with its arithmetic logic unit (ALU), multiplier, divider, and XER  
register. Most integer instructions are single-cycle instructions. Thirty-two general-purpose  
registers are provided to support integer operations. Stalls due to contention for GPRs are  
minimized by the automatic allocation of rename registers. The processor core writes the  
contents of the rename registers to the appropriate GPR when integer instructions are  
retired by the completion unit.  
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Part I. Overview  
2.2.4.2 Load/Store Unit (LSU)  
The LSU executes all load and store instructions and provides the data transfer interface  
between the GPRs, FPRs, and the cache/memory subsystem. The LSU calculates effective  
addresses, performs data alignment, and provides sequencing for load/store string and  
multiple instructions.  
Load and store instructions are issued and translated in program order; however, the actual  
memory accesses can occur out of order. Synchronizing instructions are provided to  
enforce strict ordering where needed.  
Cacheable loads, when free of data dependencies, execute in an out-of-order manner with  
a maximum throughput of one per cycle and a two-cycle total latency. Data returned from  
the cache is held in a rename register until the completion logic commits the value to a GPR  
or FPR. Store operations do not occur until a predicted branch is resolved. They remain in  
the store queue until the completion logic signals that the store operation is deÞnitely to be  
completed to memory.  
The processor core executes store instructions with a maximum throughput of one per cycle  
and a three-cycle total latency. The time required to perform the actual load or store  
operation varies depending on whether the operation involves the cache, system memory,  
or an I/O device.  
2.2.4.3 System Register Unit (SRU)  
The SRU executes various system-level instructions, including condition register logical  
operations and move to/from special-purpose register instructions, and also executes  
integer add/compare instructions. Because SRU instructions affect modes of processor  
operation, most SRU instructions are completion-serialized. That is, the instruction is held  
for execution in the SRU until all prior instructions issued have completed. Results from  
completion-serialized instructions executed by the SRU are not available or forwarded for  
subsequent instructions until the instruction completes.  
2.2.5 Completion Unit  
The completion unit tracks instructions from dispatch through execution, and then retires,  
or completes them in program order. Completing an instruction commits the processor core  
to any architectural register changes caused by that instruction. In-order completion ensures  
the correct architectural state when the processor core must recover from a mispredicted  
branch or any exception.  
Instruction state and other information required for completion is kept in a Þrst-in-Þrst-out  
(FIFO) queue of Þve completion buffers. A single completion buffer is allocated for each  
instruction once it enters the dispatch unit. An available completion buffer is a required  
resource for instruction dispatch; if no completion buffers are available, instruction  
dispatch stalls. A maximum of two instructions per cycle are completed in order from the  
queue.  
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Chapter 2. PowerPC Processor Core  
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Part I. Overview  
2.2.6 Memory Subsystem Support  
The processor core supports cache and memory management through separate instruction  
and data MMUs (IMMU and DMMU). The processor core also provides dual 16-Kbyte  
instruction and data caches, and an efÞcient processor bus interface to facilitate access to  
main memory and other bus subsystems. The memory subsystem support functions are  
described in the following subsections.  
2.2.6.1 Memory Management Units (MMUs)  
The processor coreÕs MMUs support up to 4 Petabytes (252) of virtual memory and  
4 Gbytes (232) of physical memory (referred to as real memory in the PowerPC architecture  
speciÞcation) for instructions and data. The MMUs also control access privileges for these  
spaces on block and page granularities. Referenced and changed status is maintained by the  
processor for each page to assist implementation of a demand-paged virtual memory  
system. A key bit is implemented to provide information about memory protection  
violations prior to page table search operations.  
The LSU calculates effective addresses for data loads and stores, performs data alignment  
to and from cache memory, and provides the sequencing for load and store string and  
multiple word instructions. The instruction unit calculates the effective addresses for  
instruction fetching.  
The MMUs translate effective addresses and enforce the protection hierarchy programmed  
by the operating system in relation to the supervisor/user privilege level of the access and  
in relation to whether the access is a load or store.  
2.2.6.2 Cache Units  
The processor core provides independent 16-Kbyte, four-way set-associative instruction  
and data caches. The cache block size is 32 bytes. The caches are designed to adhere to a  
write-back policy, but the processor core allows control of cacheability, write policy, and  
memory coherency at the page and block levels. The caches use a least recently used (LRU)  
replacement algorithm.  
The load/store and instruction fetch units provide the caches with the address of the data or  
instruction to be fetched. In the case of a cache hit, the cache returns two words to the  
requesting unit.  
2.3 Programming Model  
The following subsections describe the PowerPC instruction set and addressing modes in  
general.  
2.3.1 Register Set  
This section describes the register organization in the processor core as deÞned by the three  
programming environments of the PowerPC architectureÑthe user instruction set  
architecture (UISA), the virtual environment architecture (VEA), and the operating  
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Part I. Overview  
environment architecture (OEA), as well as the MPC8260 core implementation-speciÞc  
registers. Full descriptions of the basic register set deÞned by the PowerPC architecture are  
provided in Chapter 2, ÒPowerPC Register Set,Ó in The Programming Environments  
Manual.  
The PowerPC architecture deÞnes register-to-register operations for all arithmetic  
instructions. Source data for these instructions is accessed from the on-chip registers or is  
provided as an immediate value embedded in the opcode. The three-register instruction  
format allows speciÞcation of a target register distinct from the two source registers, thus  
preserving the original data for use by other instructions and reducing the number of  
instructions required for certain operations. Data is transferred between memory and  
registers with explicit load and store instructions only.  
Figure 2-2 shows the complete MPC8260 register set and the programming environment to  
which each register belongs. This Þgure includes both the PowerPC register set and the  
MPC8260-speciÞc registers.  
Note that there may be registers common to other PowerPC processors that are not  
implemented in the MPC8260Õs processor core. Unsupported SPR values are treated as  
follows:  
¥
¥
Any mtspr with an invalid SPR executes as a no-op.  
Any mfspr with an invalid SPR cause boundedly undeÞned results in the target  
register.  
Conversely, some SPRs in the processor core may not be implemented in other PowerPC  
processors, or may not be implemented in the same way in other PowerPC processors.  
2.3.1.1 PowerPC Register Set  
The PowerPC UISA registers, shown in Figure 2-2, can be accessed by either user- or  
supervisor-level instructions. The general-purpose registers (GPRs) and ßoating-point  
registers (FPRs) are accessed through instruction operands. Access to registers can be  
explicit (that is, through the use of speciÞc instructions for that purpose such as the mtspr  
and mfspr instructions) or implicit as part of the execution (or side effect) of an instruction.  
Some registers are accessed both explicitly and implicitly.  
The number to the right of the register name indicates the number that is used in the syntax  
of the instruction operands to access the register (for example, the number used to access  
the XER is one). For more information on the PowerPC register set, refer to Chapter 2,  
ÒPowerPC Register Set,Ó in The Programming Environments Manual.  
Note that the reset value of the MSR exception preÞx bit (MSR[IP]), described in the  
MPC603e UserÕs Manual, is determined by the CIP bit in the hard reset conÞguration word  
in the MPC8260. This is described in Section 5.4.1, ÒHard Reset ConÞguration Word.Ó  
MOTOROLA  
Chapter 2. PowerPC Processor Core  
2-9  
 
Part I. Overview  
SUPERVISOR MODELÑOEA  
Configuration Registers  
Hardware  
Implementation  
Registers  
Processor Version  
Register  
Machine State  
Register  
1
USER MODEL  
UISA  
HID0  
HID1  
HID2  
SPR 1008  
MSR  
PVR  
SPR 287  
General-Purpose  
Registers  
SPR 1009  
SPR 1011  
GPR0  
GPR1  
Memory Management Registers  
Instruction BAT  
Registers  
Software Table  
Search Registers  
1
Data BAT Registers  
IBAT0U  
IBAT0L  
IBAT1U  
IBAT1L  
IBAT2U  
IBAT2L  
IBAT3U  
IBAT3L  
SPR 528  
DBAT0U  
DBAT0L  
DBAT1U  
DBAT1L  
DBAT2U  
DBAT2L  
DBAT3U  
DBAT3L  
SPR 536  
SPR 537  
SPR 538  
SPR 539  
SPR 540  
SPR 541  
SPR 542  
SPR 543  
DMISS  
DCMP  
HASH1  
HASH2  
IMISS  
ICMP  
SPR 976  
SPR 977  
SPR 978  
SPR 979  
SPR 980  
SPR 981  
SPR 982  
GPR31  
SPR 529  
SPR 530  
SPR 531  
SPR 532  
SPR 533  
SPR 534  
SPR 535  
Floating-Point  
Registers  
2
FPR0  
FPR1  
RPA  
Segment Registers  
SDR1  
SDR1  
SR0  
SR1  
FPR31  
SPR 25  
Condition Register  
CR  
SR15  
XER  
Exception Handling Registers  
XER  
Link Register  
LR  
SPR 1  
Data Address Register  
DSISR  
DSISR  
Save and Restore Registers  
DAR  
SPR 18  
SPR 19  
SPRGs  
SPRG0  
SPR 8  
SPR 272  
SPR 273  
SPR 274  
SPR 275  
SRR0  
SRR1  
SPR 26  
SPR 27  
SPRG1  
SPRG2  
SPRG3  
Count Register  
CTR  
SPR 9  
USER MODEL  
VEA  
Miscellaneous Registers  
Time Base Facility  
(For Writing)  
Time Base Facility  
(For Reading)  
Decrementer  
TBL  
TBU  
SPR 284  
SPR 285  
DEC  
SPR 22  
TBL  
TBU  
TBR 268  
TBR 269  
Instruction Address  
Breakpoint Register  
External Address  
Register (Optional)  
1
IABR  
SPR 1010  
EAR  
SPR 282  
1
2
.
These implementationÐspecific registers may not be supported by other PowerPC processors or processor cores.  
Although the MPC8260 does not implement an FPU, the LSU can access FPRs if MSR[FP] = 1.  
Figure 2-2. MPC8260 Programming ModelÑRegisters  
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Part I. Overview  
Although the MPC8260 does not support ßoating-point arithmetic instructions, the FPRs  
are provided to support ßoating-point load and store instructions, which can be executed by  
the LSU. For these instructions to execute, the FPRs must be enabled (MSR[FP] = 1);  
otherwise, a ßoating-point unavailable exception is taken. It is recommended that the FPRs  
be enabled only when there is a need to access the FPRs, for example, to handle ßash  
memory updates. Otherwise, the processor should run in default mode, with FPRs disabled  
(MSR[FP] = 0).  
2.3.1.2 MPC8260-SpeciÞc Registers  
The set of registers speciÞc to the MPC603e are also shown in Figure 2-2. Most of these  
are described in the MPC603e UserÕs Manual and are implemented in the MPC8260 as  
follows:  
¥
MMU software table search registers: DMISS, DCMP, HASH1, HASH2, IMISS,  
ICMP, and RPA. These registers facilitate the software required to search the page  
tables in memory.  
¥
IABR. This register facilitates the setting of instruction breakpoints.  
The hardware implementation-dependent registers (HIDx) are implemented differently in  
the MPC8260, and they are described in the following subsections.  
2.3.1.2.1 Hardware Implementation-Dependent Register 0 (HID0)  
The processor coreÕs implementation of HID0 differs from the MPC603e UserÕs Manual as  
follows:  
¥
¥
¥
Bit 5, HID0[EICE], has been removed. There is no support for pipeline tracking.  
Bit 24, HID0[IFEM], instruction fetch enable M, has been added.  
Bit 28, HID0[ABE], address broadcast enable, has been added.  
Figure 2-3 shows the MPC8260 implementation of HID0.  
DLOCK  
ABE  
FBIOB  
EMCP  
DOZE  
SLEEP  
ILOCK  
IFEM  
NOOPTI  
EBA EBD  
PAR  
NAP  
DPM  
NHR ICE DCE  
ICFI DCFI  
Ñ
1
Ñ
Ñ
Ñ
Ñ
Ñ
0
2
3
4
6
7
8
9
10 11 12  
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31  
Figure 2-3. Hardware Implementation Register 0 (HID0)  
MOTOROLA  
Chapter 2. PowerPC Processor Core  
2-11  
       
Part I. Overview  
Table 2-1 shows the bit deÞnitions for HID0.  
Table 2-1. HID0 Field Descriptions  
Bits  
Name  
Description  
0
EMCP  
Enable machine check input pin  
0 The assertion of the MCP does not cause a machine check exception.  
1 Enables the entry into a machine check exception based on assertion of the MCP input,  
detection of a Cache Parity Error, detection of an address parity error, or detection of a data  
parity error.  
Note that the machine check exception is further affected by MSR[ME], which speciÞes whether  
the processor checkstops or continues processing.  
1
2
Ñ
Reserved  
EBA  
Enable/disable 60x bus address parity checking  
0 Prevents address parity checking.  
1 Allows a address parity error to cause a checkstop if MSR[ME] = 0 or a machine check  
exception if MSR[ME] = 1.  
EBA and EBD let the processor operate with memory subsystems that do not generate parity.  
3
EBD  
Enable 60x bus data parity checking  
0 Parity checking is disabled.  
1 Allows a data parity error to cause a checkstop if MSR[ME] = 0 or a machine check exception  
if MSR[ME] = 1.  
EBA and EBD let the processor operate with memory subsystems that do not generate parity.  
4Ð6  
7
Ñ
Reserved  
PAR  
Disable precharge of ARTRY.  
0 Precharge of ARTRY enabled  
1 Alters bus protocol slightly by preventing the processor from driving ARTRY to high (negated)  
state, allowing multiple ARTRY signals to be tied together. If this is done, the system must  
restore the signals to the high state.  
1
8
9
DOZE  
NAP  
Doze mode enable. Operates in conjunction with MSR[POW].  
0 Doze mode disabled.  
1 Doze mode enabled. Doze mode is invoked by setting MSR[POW] after this bit is set. In doze  
mode, the PLL, time base, and snooping remain active.  
1
Nap mode enable. Operates in conjunction with MSR[POW].  
0 Nap mode disabled.  
1 Nap mode enabled. Nap mode is invoked by setting MSR[POW] while this bit is set. When this  
occurs, the processor asserts QREQ to indicate that it is ready to enter nap mode. If the  
system logic determines that the processor may enter nap mode, the quiesce acknowledge  
signal, QACK, is asserted back to the processor. Once QACK assertion is detected, the  
processor enters nap mode after several processor clocks. Because bus snooping is disabled  
for nap and sleep modes, this serves as a hardware mechanism for ensuring data coherency.  
In nap mode, the PLL and the time base remain active.  
1
10  
SLEEP Sleep mode enable. Operates in conjunction with MSR[POW].  
0 Sleep mode disabled.  
1 Sleep mode enabled. Sleep mode is invoked by setting MSR[POW] while this bit is set. When  
this occurs, the processor asserts QREQ to indicate that it is ready to enter sleep mode. If the  
system logic determines that the processor may enter sleep mode, the quiesce acknowledge  
signal, QACK, is asserted back to the processor. Once QACK assertion is detected, the  
processor enters sleep mode after several processor clocks. At this point, the system logic  
may turn off the PLL by Þrst conÞguring PLL_CFG[0Ð3] to PLL bypass mode, and then  
disabling SYSCLK.  
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Part I. Overview  
Table 2-1. HID0 Field Descriptions (Continued)  
Bits  
Name  
Description  
1
11  
DPM  
Dynamic power management enable.  
0 Dynamic power management is disabled.  
1 Functional units enter a low-power mode automatically if the unit is idle. This does not affect  
operational performance and is transparent to software or any external hardware.  
12Ð14  
15  
Ñ
Reserved  
NHR  
Not hard reset (software-use only)ÑHelps software distinguish a hard reset from a soft reset.  
0 A hard reset occurred if software had previously set this bit.  
1 A hard reset has not occurred. If software sets this bit after a hard reset, when a reset occurs  
and this bit remains set, software can tell it was a soft reset.  
2
16  
ICE  
Instruction cache enable  
0 The instruction cache is neither accessed nor updated. All pages are accessed as if they were  
marked cache-inhibited (WIM = X1X). Potential cache accesses from the bus (snoop and  
cache operations) are ignored. In the disabled state for the L1 caches, the cache tag state bits  
are ignored and all accesses are propagated to the bus as single-beat transactions. For those  
transactions, however, CI reßects the original state determined by address translation  
regardless of cache disabled status. ICE is zero at power-up.  
1 The instruction cache is enabled  
2
17  
DCE  
Data cache enable  
0 The data cache is neither accessed nor updated. All pages are accessed as if they were  
marked cache-inhibited (WIM = X1X). Potential cache accesses from the bus (snoop and  
cache operations) are ignored. In the disabled state for the L1 caches, the cache tag state bits  
are ignored and all accesses are propagated to the bus as single-beat transactions. For those  
transactions, however, CI reßects the original state determined by address translation  
regardless of cache disabled status. DCE is zero at power-up.  
1 The data cache is enabled.  
18  
ILOCK  
Instruction cache lock  
0 Normal operation  
1 Instruction cache is locked. A locked cache supplies data normally on a hit, but an access is  
treated as a cache-inhibited transaction on a miss. On a miss, the transaction to the bus is  
single-beat, however, CI still reßects the original state as determined by address translation  
independent of cache locked or disabled status.  
To prevent locking during a cache access, an isync must precede the setting of ILOCK.  
19  
DLOCK Data cache lock  
0 Normal operation  
1 Data cache is locked. A locked cache supplies data normally on a hit but an access is treated  
as a cache-inhibited transaction on a miss. On a miss, the transaction to the bus is single-  
beat, however, CI still reßects the original state as determined by address translation  
independent of cache locked or disabled status. A snoop hit to a locked L1 data cache  
performs as if the cache were not locked. A cache block invalidated by a snoop remains invalid  
until the cache is unlocked.  
To prevent locking during a cache access, a sync must precede the setting of DLOCK.  
MOTOROLA  
Chapter 2. PowerPC Processor Core  
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Part I. Overview  
Table 2-1. HID0 Field Descriptions (Continued)  
Bits  
Name  
Description  
2
20  
ICFI  
Instruction cache ßash invalidate  
0 The instruction cache is not invalidated. The bit is cleared when the invalidation operation  
begins (usually the next cycle after the write operation to the register). The instruction cache  
must be enabled for the invalidation to occur.  
1 An invalidate operation is issued that marks the state of each instruction cache block as invalid  
without writing back modiÞed cache blocks to memory. Cache access is blocked during this  
time. Bus accesses to the cache are signaled as a miss during invalidate-all operations.  
Setting ICFI clears all the valid bits of the blocks and the PLRU bits to point to way L0 of each  
set. Once the L1 ßash invalidate bits are set through an mtspr instruction, hardware  
automatically resets these bits in the next cycle (provided that the corresponding cache  
enable bits are set in HID0).  
2
21  
DCFI  
Data cache ßash invalidate  
0 The data cache is not invalidated. The bit is cleared when the invalidation operation begins  
(usually the next cycle after the write operation to the register). The data cache must be  
enabled for the invalidation to occur.  
1 An invalidate operation is issued that marks the state of each data cache block as invalid  
without writing back modiÞed cache blocks to memory. Cache access is blocked during this  
time. Bus accesses to the cache are signaled as a miss during invalidate-all operations.  
Setting DCFI clears all the valid bits of the blocks and the PLRU bits to point to way L0 of each  
set. Once the L1 ßash invalidate bits are set through an mtspr instruction, hardware  
automatically resets these bits in the next cycle (provided that the corresponding cache  
enable bits are set in HID0).  
22Ð23  
24  
Ñ
Reserved  
IFEM  
Enable M bit on 60x bus for instruction fetches  
0 M bit not reßected on 60x bus. Instruction fetches are treated as nonglobal on the bus.  
1 Instruction fetches reßect the M bit from the WIM settings on the 60x bus.  
25Ð26  
27  
Ñ
Reserved  
FBIOB  
Force branch indirect on bus.  
0
1
Register indirect branch targets are fetched normally  
Forces register indirect branch targets to be fetched externally.  
28  
ABE  
Ñ
Address broadcast enable  
0 dcbf, dcbi, and dcbst instructions are not broadcast on the 60x bus.  
1 dcbf, dcbi, and dcbst generate address-only broadcast operations on the 60x bus.  
29Ð30  
31  
Reserved  
NOOPTI No-op the data cache touch instructions.  
0 The dcbt and dcbtst instructions are enabled.  
1 The dcbt and dcbtst instructions are no-oped globally.  
1
2
See Chapter 9, ÒPower Management,Ó of the MPC603e UserÕs Manual for more information.  
See Chapter 3, ÒInstruction and Data Cache Operation,Ó of the MPC603e UserÕs Manual for more information.  
2.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1)  
The MPC8260 implementation of HID1 is shown in Figure 2-4.  
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Part I. Overview  
PLLCFG  
Ñ
0
4
5
31  
Figure 2-4. Hardware Implementation Register 1 (HID1)  
Table 2-2 shows the bit deÞnitions for HID1.  
Table 2-2. HID1 Field Descriptions  
Bits  
0Ð4 PLLCFG PLL conÞguration setting  
5Ð31 Reserved  
Name  
Function  
Ñ
2.3.1.2.3 Hardware Implementation-Dependent Register 2 (HID2)  
The processor core implements an additional hardware implementation-dependent register  
not described in the MPC603e UserÕs Manual, shown in Figure 2-5.  
Ñ
SFP IWLCK  
14 15 16 18 19  
Ñ
DWLCK  
23 24  
Ñ
0
26 27  
31  
Figure 2-5. Hardware Implementation-Dependent Register 2 (HID2)  
Table 2-3 describes the HID2 Þelds.  
Table 2-3. HID2 Field Descriptions  
Bits  
Name  
Function  
0Ð14  
15  
Ñ
Reserved  
SFP  
Speed for low power. Setting SFP reduces power consumption at the cost of reducing the  
maximum frequency, which beneÞts power-sensitive applications that are not frequency-critical.  
16Ð18 IWLCK Instruction cache way lock. Useful for locking blocks of instructions into the instruction cache for  
time-critical applications that require deterministic behavior. See Section 2.4.2.3, ÒCache Locking.Ó  
19Ð23  
Ñ
Reserved  
24Ð26 DWLCK Data cache way lock. Useful for locking blocks of data into the data cache for time-critical  
applications where deterministic behavior is required. See Section 2.4.2.3, ÒCache Locking.Ó  
27Ð31  
Ñ
Reserved  
MOTOROLA  
Chapter 2. PowerPC Processor Core  
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Part I. Overview  
2.3.1.2.4 Processor Version Register (PVR)  
Software can identify the MPC8260Õs processor core by reading the processor version  
register (PVR). The MPC8260Õs processor version number is 0x0081; the processor  
revision level starts at 0x0100 and is incremented for each revision of the chip.  
2.3.2 PowerPC Instruction Set and Addressing Modes  
All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats  
are consistent among all instruction types, permitting efÞcient decoding to occur in parallel  
with operand accesses. This Þxed instruction length and consistent format greatly simpliÞes  
instruction pipelining.  
2.3.2.1 Calculating Effective Addresses  
The effective address (EA) is the 32-bit address computed by the processor when executing  
a memory access or branch instruction or when fetching the next sequential instruction.  
The PowerPC architecture supports two simple memory addressing modes:  
¥
¥
EA = (rA|0) + offset (including offset = 0) (register indirect with immediate index)  
EA = (rA|0) + rB (register indirect with index)  
These simple addressing modes allow efÞcient address generation for memory accesses.  
Calculation of the effective address for aligned transfers occurs in a single clock cycle.  
For a memory access instruction, if the sum of the effective address and the operand length  
exceeds the maximum effective address, the memory operand is considered to wrap around  
from the maximum effective address to effective address 0.  
Effective address computations for both data and instruction accesses use 32-bit unsigned  
binary arithmetic. A carry from bit 0 is ignored in 32-bit implementations.  
In addition to the functionality of the MPC603e, the MPC8260 has additional hardware  
support for misaligned little-endian accesses. Except for string/multiple load and store  
instructions, little-endian load/store accesses not on a word boundary generate exceptions  
under the same circumstances as big-endian requests.  
2.3.2.2 PowerPC Instruction Set  
The PowerPC instructions are divided into the following categories:  
¥
Integer instructionsÑThese include arithmetic and logical instructions.  
Ñ Integer arithmetic  
Ñ Integer compare  
Ñ Integer logical  
Ñ Integer rotate and shift  
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Part I. Overview  
¥
Load/store instructionsÑThese include integer and ßoating-point load and store  
instructions.  
Ñ Integer load and store  
Ñ Integer load and store with byte reverse  
Ñ Integer load and store string/multiple  
Ñ Floating-point load and store. Setting MSR[FPE] allows the MPC8260 to access  
the FPRs with the ßoating-point load and store instructions described in the  
MPC603e UserÕs Manual. This is useful both for systems that require emulation  
of ßoating-point instructions and for increasing data throughput.  
¥
Flow control instructionsÑThese include branching instructions, condition register  
logical instructions, trap instructions, and other synchronizing instructions that  
affect the instruction ßow.  
Ñ Branch and trap  
Ñ Condition register logical  
Ñ Primitives used to construct atomic memory operations (lwarx and stwcx.)  
Ñ Synchronize  
¥
¥
Processor control instructionsÑThese instructions are used for synchronizing  
memory accesses and management of caches, TLBs, and the segment registers.  
Ñ Move to/from SPR  
Ñ Move to/from MSR  
Ñ Instruction synchronize  
Memory control instructionsÑThese provide control of caches, TLBs, and segment  
registers.  
Ñ Supervisor-level cache management  
Ñ User-level cache management  
Ñ Segment register manipulation  
Ñ TLB management  
Note that this grouping of the instructions does not indicate which execution unit executes  
a particular instruction or group of instructions.  
Integer instructions operate on byte, half-word, and word operands. The PowerPC  
architecture uses instructions that are four bytes long and word-aligned. It provides for  
byte, half-word, and word operand loads and stores between memory and a set of 32 GPRs.  
It also provides for word and double-word operand loads and stores between memory and  
a set of 32 ßoating-point registers (FPRs). Although the MPC8260 does use the FPRs for  
64-bit loads and stores, it does not support ßoating-point arithmetic instructions.  
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Computational instructions do not modify memory. To use a memory operand in a  
computation and then modify the same or another memory location, the memory contents  
must be loaded into a register, modiÞed, and then written back to the target location with  
separate instructions. Decoupling arithmetic instructions from memory accesses increases  
throughput by facilitating pipelining.  
PowerPC processors follow the program ßow when they are in the normal execution state.  
However, the ßow of instructions can be interrupted directly by the execution of an  
instruction or by an asynchronous event. Either kind of exception may cause one of several  
components of the system software to be invoked.  
2.3.2.3 MPC8260 Implementation-SpeciÞc Instruction Set  
The MPC8260 processor core instruction set is deÞned as follows:  
¥
¥
The processor core provides hardware support for all 32-bit PowerPC instructions.  
The processor core provides two implementation-speciÞc instructions used for  
software table search operations following TLB misses:  
Ñ Load Data TLB Entry (tlbld)  
Ñ Load Instruction TLB Entry (tlbli)  
¥
The processor core implements the following instructions deÞned as optional by the  
PowerPC architecture:  
Ñ External Control In Word Indexed (eciwx)  
Ñ External Control Out Word Indexed (ecowx)  
Ñ Store Floating-Point as Integer Word Indexed (stÞwx)  
The MPC8260 does not provide the hardware support for misaligned eciwx and  
ecowx instructions provided by the MPC603e processor. An alignment exception is  
taken if these instructions are not word-aligned.  
2.4 Cache Implementation  
The MPC8260 processor core has separate data and instruction caches. The cache  
implementation is described in the following sections.  
2.4.1 PowerPC Cache Model  
The PowerPC architecture does not deÞne hardware aspects of cache implementations. For  
example, some PowerPC processors, including the MPC8260Õs processor core, have  
separate instruction and data caches (Harvard architecture), while others, such as the  
PowerPC 601¨ microprocessor, implement a uniÞed cache.  
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PowerPC microprocessors control the following memory access modes on a page or block  
basis:  
¥
¥
¥
Write-back/write-through mode  
Caching-inhibited mode  
Memory coherency  
The PowerPC cache management instructions provide a means by which the application  
programmer can affect the cache contents.  
2.4.2 MPC8260 Implementation-SpeciÞc Cache Implementation  
As shown in Figure 2-1, the caches provide a 64-bit interface to the instruction fetch unit  
and load/store unit. The surrounding logic selects, organizes, and forwards the requested  
information to the requesting unit. Write operations to the cache can be performed on a byte  
basis, and a complete read-modify-write operation to the cache can occur in each cycle.  
Each cache block contains eight contiguous words from memory that are loaded from an  
8-word boundary (that is, bits A27ÐA31 of the effective addresses are zero); thus, a cache  
block never crosses a page boundary. Misaligned accesses across a page boundary can incur  
a performance penalty.  
The cache blocks are loaded in to the processor core in four beats of 64 bits each. The burst  
load is performed as critical double word Þrst.  
To ensure coherency among caches in a multiprocessor (or multiple caching-device)  
implementation, the processor core implements the MEI protocol. These three states,  
modiÞed, exclusive, and invalid, indicate the state of the cache block as follows:  
¥
¥
¥
ModiÞedÑThe cache block is modiÞed with respect to system memory; that is, data  
for this address is valid only in the cache and not in system memory.  
ExclusiveÑThis cache block holds valid data that is identical to the data at this  
address in system memory. No other cache has this data.  
InvalidÑThis cache block does not hold valid data.  
2.4.2.1 Data Cache  
As shown in Figure 2-6, the data cache is conÞgured as 128 sets of four blocks each. Each  
block consists of 32 bytes, two state bits, and an address tag. The two state bits implement  
the three-state MEI (modiÞed/exclusive/invalid) protocol. Each block contains eight 32-bit  
words. Note that the PowerPC architecture deÞnes the term ÔblockÕ as the cacheable unit.  
For the MPC8260Õs processor core, the block size is equivalent to a cache line.  
MOTOROLA  
Chapter 2. PowerPC Processor Core  
2-19  
   
Part I. Overview  
128 Sets  
Address Tag 0  
Address Tag 1  
Address Tag 2  
Address Tag 3  
State  
State  
State  
State  
Words 0Ð7  
Words 0Ð7  
Block 0  
Block 1  
Block 2  
Block 3  
Words 0Ð7  
Words 0Ð7  
8 Words/Block  
Figure 2-6. Data Cache Organization  
Because the processor core data cache tags are single-ported, simultaneous load or store  
and snoop accesses cause resource contention. Snoop accesses have the highest priority and  
are given Þrst access to the tags, unless the snoop access coincides with a tag write, in which  
case the snoop is retried and must rearbitrate for access to the cache. Loads or stores that  
are deferred due to snoop accesses are executed on the clock cycle following the snoop.  
Because the caches on the processor core are write-back caches, the predominant type of  
transaction for most applications is burst-read memory operations, followed by burst-write  
memory operations, and single-beat (noncacheable or write-through) memory read and  
write operations. When a cache block is Þlled with a burst read, the critical double word is  
simultaneously written to the cache and forwarded to the requesting unit, thus minimizing  
stalls due to load delays.  
Additionally, there can be address-only operations, variants of the burst and single-beat  
operations, (for example, global memory operations that are snooped and atomic memory  
operations), and address retry activity (for example, when a snooped read access hits a  
modiÞed line in the cache).  
The processor core differs from the MPC603e UserÕs Manual with the addition of the  
HIDO[ABE] bit. Setting this bit causes execution of the dcbf, dcbi, and dcbst instructions  
to be broadcast onto the 60x bus. The value ofABE does not affect dcbz instructions, which  
are always broadcast and snooped. The cache operations are intended primarily for  
managing on-chip caches. However, the optional broadcast feature is necessary to allow  
proper management of a system using an external copyback L2 cache.  
The address and data buses operate independently to support pipelining and split  
transactions during memory accesses. The processor core pipelines its own transactions to  
a depth of one level.  
Typically, memory accesses are weakly orderedÑsequences of operations, including load/  
store string and multiple instructions, do not necessarily complete in the order they beginÑ  
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Part I. Overview  
maximizing the efÞciency of the internal bus without sacriÞcing coherency of the data. The  
processor core allows pending read operations to precede previous store operations (except  
when a dependency exists, or in cases where a non-cacheable access is performed), and  
provides support for a write operation to proceed a previously queued read data tenure (for  
example, allowing a snoop push to be enveloped by the address and data tenures of a read  
operation). Because the processor can dynamically optimize run-time ordering of load/  
store trafÞc, overall performance is improved.  
2.4.2.2 Instruction Cache  
The instruction cache also consists of 128 sets of four blocks, and each block consists of 32  
bytes, an address tag, and a valid bit. The instruction cache may not be written to except  
through a block Þll operation caused by a cache miss. In the processor core, internal access  
to the instruction cache is blocked only until the critical load completes.  
The processor core supports instruction fetching from other instruction cache lines  
following the forwarding of the critical Þrst double word of a cache line load operation. The  
processor coreÕs instruction cache is blocked only until the critical load completes (hits  
under reloads allowed). Successive instruction fetches from the cache line being loaded are  
forwarded, and accesses to other instruction cache lines can proceed during the cache line  
load operation.  
The instruction cache is not snooped, and cache coherency must be maintained by software.  
A fast hardware invalidation capability is provided to support cache maintenance. The  
organization of the instruction cache is very similar to the data cache shown in Figure 2-6.  
2.4.2.3 Cache Locking  
The processor core supports cache locking, which is the ability to prevent some or all of a  
microprocessorÕs instruction or data cache from being overwritten. Cache entries can be  
locked for either an entire cache or for individual ways within the cache. Entire data cache  
locking is enabled by setting HID0[DLOCK], and entire instruction cache locking is  
enabled by setting HID0[ILOCK]. For more information, refer to Cache Locking on the G2  
Core application note (order number: AN1767/D). Cache way locking is controlled by the  
IWLCK and DWLCK bits of HID2.  
2.4.2.3.1 Entire Cache Locking  
When an entire cache is locked, hits within the cache are supplied in the same manner as  
hits to an unlocked cache. Any access that misses in the cache is treated as a cache-inhibited  
access. Cache entries that are invalid at the time of locking will remain invalid and  
inaccessible until the cache is unlocked. Once the cache has been unlocked, all entries  
(including invalid entries) are available. Entire cache locking is inefÞcient if the number of  
instructions or the size of data to be locked is small compared to the cache size.  
2.4.2.3.2 Way Locking  
Locking only a portion of the cache is accomplished by locking ways within the cache.  
Locking always begins with the Þrst way (way0) and is sequential. That is, it is valid to lock  
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ways 0, 1, and 2 but it is not possible to lock just way0 and way2). When using way locking  
at least one way must be left unlocked. The maximum number of lockable ways is three.  
Unlike entire cache locking, invalid entries in a locked way are accessible and available for  
data placement. As hits to the cache Þll invalid entries within a locked way, the entries  
become valid and locked. This behavior differs from entire cache locking where nothing is  
placed in the cache, even if invalid entries exist in the cache. Unlocked ways of the cache  
behave normally.  
2.5 Exception Model  
This section describes the PowerPC exception model and implementation-speciÞc details  
of the MPC8260 core.  
2.5.1 PowerPC Exception Model  
The PowerPC exception mechanism allows the processor to change to supervisor state as a  
result of external signals, errors, or unusual conditions arising in the execution of  
instructions. When exceptions occur, information about the state of the processor is saved  
to certain registers and the processor begins execution at an address (exception vector)  
predetermined for each exception. Processing of exceptions occurs in supervisor mode.  
Although multiple exception conditions can map to a single exception vector, a more  
speciÞc condition may be determined by examining a register associated with the  
exceptionÑfor example, the DSISR identiÞes instructions that cause a DSI exception.  
Additionally, some exception conditions can be explicitly enabled or disabled by software.  
The PowerPC architecture requires that exceptions be handled in program order; therefore,  
although a particular implementation may recognize exception conditions out of order,  
exceptions are taken in strict order. When an instruction-caused exception is recognized,  
any unexecuted instructions that appear earlier in the instruction stream, including any that  
have not yet entered the execute stage, are required to complete before the exception is  
taken. Any exceptions caused by those instructions are handled Þrst. Likewise, exceptions  
that are asynchronous and precise are recognized when they occur, but are not handled until  
the instruction currently in the completion stage successfully completes execution or  
generates an exception, and the completed store queue is emptied.  
Unless a catastrophic condition causes a system reset or machine check exception, only one  
exception is handled at a time. If, for example, a single instruction encounters multiple  
exception conditions, those conditions are handled sequentially.After the exception handler  
handles an exception, the instruction execution continues until the next exception condition  
is encountered. However, in many cases there is no attempt to re-execute the instruction.  
This method of recognizing and handling exception conditions sequentially guarantees that  
exceptions are recoverable.  
Exception handlers should save the information stored in SRR0 and SRR1 early to prevent  
the program state from being lost due to a system reset or machine check exception or to  
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an instruction-caused exception in the exception handler. SRR0 and SRR1 should also be  
saved before enabling external interrupts.  
The PowerPC architecture supports four types of exceptions:  
¥
Synchronous, preciseÑThese are caused by instructions. All instruction-caused  
exceptions are handled precisely; that is, the machine state at the time the exception  
occurs is known and can be completely restored. This means that (excluding the trap  
and system call exceptions) the address of the faulting instruction is provided to the  
exception handler and that neither the faulting instruction nor subsequent  
instructions in the code stream will complete execution before the exception is  
taken. Once the exception is processed, execution resumes at the address of the  
faulting instruction (or at an alternate address provided by the exception handler).  
When an exception is taken due to a trap or system call instruction, execution  
resumes at an address provided by the handler.  
¥
¥
Synchronous, impreciseÑThe PowerPC architecture deÞnes two imprecise  
ßoating-point exception modes, recoverable and nonrecoverable. These are not  
implemented on the MPC8260.  
Asynchronous, maskableÑThe external, system management interrupt (SMI), and  
decrementer interrupts are maskable asynchronous exceptions. When these  
exceptions occur, their handling is postponed until the next instruction and any  
exceptions associated with that instruction complete execution. If no instructions are  
in the execution units, the exception is taken immediately upon determination of the  
correct restart address (for loading SRR0).  
¥
Asynchronous, nonmaskableÑThere are two nonmaskable asynchronous  
exceptions: system reset and the machine check exception. These exceptions may  
not be recoverable, or may provide a limited degree of recoverability. All exceptions  
report recoverability through MSR[RI].  
2.5.2 MPC8260 Implementation-SpeciÞc Exception Model  
As speciÞed by the PowerPC architecture, all processor core exceptions can be described  
as either precise or imprecise and either synchronous or asynchronous. Asynchronous  
exceptions (some of which are maskable) are caused by events external to the processorÕs  
execution. Synchronous exceptions, which are all handled precisely by the processor core,  
are caused by instructions. The processor core exception classes are shown in Table 2-4.  
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Table 2-4. Exception Classifications for the Processor Core  
Synchronous/Asynchronous  
Precise/Imprecise  
Imprecise  
Exception Type  
Asynchronous, nonmaskable  
Machine check  
System reset  
Asynchronous, maskable  
Synchronous  
Precise  
Precise  
External interrupt  
Decrementer  
System management interrupt  
Instruction-caused exceptions  
Although exceptions have other characteristics as well, such as whether they are maskable  
or nonmaskable, the distinctions shown in Table 2-4 deÞne categories of exceptions that the  
processor core handles uniquely. Note that Table 2-4 includes no synchronous imprecise  
instructions.  
The processor coreÕs exceptions, and conditions that cause them, are listed in Table 2-5.  
Table 2-5. Exceptions and Conditions  
Exception  
Type  
Vector Offset  
(hex)  
Causing Conditions  
Reserved  
00000  
00100  
Ñ
System reset  
A system reset is caused by the assertion of either SRESET or HRESET. Note that  
the reset value of the MSR exception preÞx bit (MSR[IP]), described in the  
MPC603e UserÕs Manual, is determined by the CIP bit in the hard reset  
conÞguration word. This is described in Section 5.4.1, ÒHard Reset ConÞguration  
Word.Ó  
Machine check 00200  
A machine check is caused by the assertion of the TEA signal during a data bus  
transaction, assertion of MCP, or an address or data parity error.  
DSI  
00300  
The cause of a DSI exception can be determined by the bit settings in the DSISR,  
listed as follows:  
1
Set if the translation of an attempted access is not found in the primary hash  
table entry group (HTEG), or in the rehashed secondary HTEG, or in the range  
of a DBAT register; otherwise cleared.  
4
5
Set if a memory access is not permitted by the page or DBAT protection  
mechanism; otherwise cleared.  
Set by an eciwx or ecowx instruction if the access is to an address that is  
marked as write-through, or execution of a load/store instruction that accesses a  
direct-store segment.  
6 Set for a store operation and cleared for a load operation.  
11 Set if eciwx or ecowx is used and EAR[E] is cleared.  
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Table 2-5. Exceptions and Conditions (Continued)  
Exception  
Type  
Vector Offset  
(hex)  
Causing Conditions  
ISI  
00400  
An ISI exception is caused when an instruction fetch cannot be performed for any of  
the following reasons:  
¥
The effective (logical) address cannot be translated.That is, there is a page fault  
for this portion of the translation, so an ISI exception must be taken to load the  
PTE (and possibly the page) into memory.  
¥
¥
The fetch access is to a direct-store segment (indicated by SRR1[3] set).  
The fetch access violates memory protection (indicated by SRR1[4] set). If the  
key bits (Ks and Kp) in the segment register and the PP bits in the PTE are set to  
prohibit read access, instructions cannot be fetched from this location.  
External  
interrupt  
00500  
00600  
An external interrupt is caused when MSR[EE] = 1 and the INT signal is asserted.  
Alignment  
An alignment exception is caused when the processor core cannot perform a  
memory access for any of the reasons described below:  
¥
¥
¥
¥
The operand of a ßoating-point load or store is to a direct-store segment.  
The operand of a ßoating-point load or store is not word-aligned.  
The operand of a lmw, stmw, lwarx, or stwcx. is not word-aligned.  
The operand of an elementary, multiple or string load or store crosses a segment  
boundary with a change to the direct store T bit.  
¥
The operand of dcbz instruction is in memory that is write-through required  
or caching inhibited, or dcbz is executed in an implementation that has either no  
data cache or a write-through data cache.  
¥
¥
A misaligned eciwx or ecowx instruction  
A multiple or string access with MSR[LE] set  
The processor core differs from MPC603e UserÕs Manual in that it initiates an  
alignment exception when it detects a misaligned eciwx or ecowx instruction and  
does not initiate an alignment exception when a little-endian access is misaligned.  
Program  
00700  
A program exception is caused by one of the following exception conditions, which  
correspond to bit settings in SRR1 and arise during execution of an instruction:  
¥
Illegal instructionÑAn illegal instruction program exception is generated when  
execution of an instruction is attempted with an illegal opcode or illegal  
combination of opcode and extended opcode Þelds (including PowerPC  
instructions not implemented in the processor core), or when execution of an  
optional instruction not provided in the processor core is attempted (these do not  
include those optional instructions that are treated as no-ops).  
¥
¥
Privileged instructionÑA privileged instruction type program exception is  
generated when the execution of a privileged instruction is attempted and the  
MSR register user privilege bit, MSR[PR], is set. In the processor core, this  
exception is generated for mtspr or mfspr with an invalid SPR Þeld if SPR[0] = 1  
and MSR[PR] = 1. This may not be true for all PowerPC processors.  
TrapÑA trap type program exception is generated when any of the conditions  
speciÞed in a trap instruction is met.  
Floating-point 00800  
unavailable  
If MSR[FP] = 0, the FPRs are disabled and attempting to execute any ßoating-point  
instruction causes a ßoating-point unavailable exception. A ßoating-point  
unavailable exception cannot occur if MSR[FP] = 1.  
Decrementer  
00900  
The decrementer exception occurs when the most signiÞcant bit of the decrementer  
(DEC) register transitions from 0 to 1. Must also be enabled with the MSR[EE] bit.  
Reserved  
00A00Ð00BFF  
00C00  
Ñ
System call  
A system call exception occurs when a System Call (sc) instruction is executed.  
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Table 2-5. Exceptions and Conditions (Continued)  
Exception  
Type  
Vector Offset  
Causing Conditions  
(hex)  
Trace  
00D00  
A trace exception is taken when MSR[SE] = 1 or when the currently completing  
instruction is a branch and MSR[BE] = 1.  
Floating-point 00E00  
Not implemented.  
00E10Ð00FFF Ñ  
assist  
Reserved  
Instruction  
translation  
miss  
01000  
An instruction translation miss exception is caused when the effective address for  
an instruction fetch cannot be translated by the ITLB.  
Data load  
translation  
miss  
01100  
A data load translation miss exception is caused when the effective address for a  
data load operation cannot be translated by the DTLB.  
Data store  
translation  
miss  
01200  
A data store translation miss exception is caused when the effective address for a  
data store operation cannot be translated by the DTLB, or when a DTLB hit occurs,  
and the changed bit in the PTE must be set due to a data store operation.  
Instruction  
address  
breakpoint  
01300  
An instruction address breakpoint exception occurs when the address (bits 0Ð29) in  
the IABR matches the next instruction to complete in the completion unit, and the  
IABR enable bit (bit 30) is set.  
System  
management  
interrupt  
01400  
A system management interrupt is caused when MSR[EE] = 1 and the SMI input  
signal is asserted.  
Reserved  
01500Ð02FFF  
Ñ
2.5.3 Exception Priorities  
The exception priorities for the processor core are unchanged from those described in the  
MPC603e UserÕs Manual except for the alignment exception, whose causes are prioritized  
as follows:  
1. Floating-point operand not word-aligned  
2. lmw, stmw, lwarx, or stwcx. operand not word-aligned  
3. eciwx or ecowx operand misaligned  
4. A multiple or string access is attempted with MSR[LE] set  
2.6 Memory Management  
The following subsections describe the memory management features of the PowerPC  
architecture and the MPC8260 implementation.  
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2.6.1 PowerPC MMU Model  
The primary functions of the MMU are to translate logical (effective) addresses to physical  
addresses for memory accesses, and to provide access protection on blocks and pages of  
memory.  
There are two types of accesses generated by the processor core that require address  
translationÑinstruction accesses and data accesses to memory generated by load and store  
instructions.  
The PowerPC MMU and exception models support demand-paged virtual memory. Virtual  
memory management permits execution of programs larger than the size of physical  
memory; demand-paged implies that individual pages are loaded into physical memory  
from system memory only when they are Þrst accessed by an executing program.  
The PowerPC architecture supports the following three translation methods:  
¥
Address translations disabled. Translation is enabled by setting bits in the MSRÑ  
MSR[IR] enables instruction address translations and MSR[DR] enables data  
address translations. Clearing these bits disables translation and the effective address  
is used as the physical address.  
¥
Block address translation. The PowerPC architecture deÞnes independent four-entry  
BAT arrays for instructions and data that maintain address translations for blocks of  
memory. Block sizes range from 128 Kbyte to 256 Mbyte and are software  
selectable. The BAT arrays are maintained by system software. The BAT registers,  
deÞned by the PowerPC architecture for block address translations, are shown in  
Figure 2-2.  
¥
Demand page mode. The page table contains a number of page table entry groups  
(PTEGs). A PTEG contains eight page table entries (PTEs) of eight bytes each;  
therefore, each PTEG is 64 bytes long. PTEG addresses are entry points for table  
search operations.  
The hashed page table is a variable-sized data structure that deÞnes the mapping  
between virtual page numbers and physical page numbers. The page table size is a  
power of 2, and its starting address is a multiple of its size.  
On-chip instruction and data TLBs provide address translation in parallel with the  
on-chip cache access, incurring no additional time penalty in the event of a TLB hit.  
A TLB is a cache of the most recently used page table entries. Software is  
responsible for maintaining the consistency of the TLB with memory. In the  
MPC8260, the processor coreÕs TLBs are 64-entry, two-way set-associative caches  
that contain instruction and data address translations. The MPC8260Õs core provides  
hardware assist for software table search operations through the hashed page table  
on TLB misses. Supervisor software can invalidate TLB entries selectively.  
The MMU also directs the address translation and enforces the protection hierarchy  
programmed by the operating system in relation to the supervisor/user privilege level of the  
access and in relation to whether the access is a load or store.  
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2.6.2 MPC8260 Implementation-SpeciÞc MMU Features  
The instruction and data MMUs in the processor core provide 4-Gbytes of logical address  
space accessible to supervisor and user programs with a 4-Kbyte page size and 256-Mbyte  
segment size.  
The MPC8260Õs MMUs support up to 4 Petabytes (252) of virtual memory and 4 Gbytes  
(232) of physical memory (referred to as real memory in the PowerPC architecture  
speciÞcation) for instructions and data. Referenced and changed status is maintained by the  
processor for each page to assist implementation of a demand-paged virtual memory  
system.  
The MPC8260Õs TLBs are 64-entry, two-way set-associative caches that contain instruction  
and data address translations. The processor core provides hardware assist for software  
table search operations through the hashed page table on TLB misses. Supervisor software  
can invalidate TLB entries selectively.  
After an effective address is generated, the higher-order bits of the effective address are  
translated by the appropriate MMU into physical address bits. Simultaneously, the lower-  
order address bits (that are untranslated and therefore, considered both logical and  
physical), are directed to the on-chip caches where they form the index into the four-way  
set-associative tag array. After translating the address, the MMU passes the higher-order  
bits of the physical address to the cache, and the cache lookup completes. For caching-  
inhibited accesses or accesses that miss in the cache, the untranslated lower-order address  
bits are concatenated with the translated higher-order address bits; the resulting 32-bit  
physical address is then used by the system interface, which accesses external memory.  
For instruction accesses, the MMU performs an address lookup in both the 64 entries of the  
ITLB, and in the IBAT array. If an effective address hits in both the ITLB and the IBAT  
array, the IBAT array translation takes priority. Data accesses cause a lookup in the DTLB  
and DBAT array for the physical address translation. In most cases, the physical address  
translation resides in one of the TLBs and the physical address bits are readily available to  
the on-chip cache.  
When the physical address translation misses in the TLBs, the processor core provides  
hardware assistance for software to search the translation tables in memory. When a  
required TLB entry is not found in the appropriate TLB, the processor vectors to one of the  
three TLB miss exception handlers so that the softawre can perform a table search operation  
and load the TLB. When this occurs, the processor automatically saves information about  
the access and the executing context. Refer to the MPC603e UserÕs Manual for more  
detailed information about these features and the suggested software routines for searching  
the page tables.  
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2.7 Instruction Timing  
The processor core is a pipelined superscalar processor. A pipelined processor is one in  
which the processing of an instruction is broken into discrete stages. Because the  
processing of an instruction is broken into a series of stages, an instruction does not require  
the entire resources of an execution unit at one time. For example, after an instruction  
completes the decode stage, it can pass on to the next stage, while the subsequent  
instruction can advance into the decode stage. This improves the throughput of the  
instruction ßow. The instruction pipeline in the processor core has four major stages,  
described as follows:  
¥
The fetch pipeline stage primarily involves retrieving instructions from the memory  
system and determining the location of the next instruction fetch. Additionally, the  
BPU decodes branches during the fetch stage and folds out branch instructions  
before the dispatch stage if possible.  
¥
The dispatch pipeline stage is responsible for decoding the instructions supplied by  
the instruction fetch stage, and determining which of the instructions are eligible to  
be dispatched in the current cycle. In addition, the source operands of the  
instructions are read from the appropriate register Þle and dispatched with the  
instruction to the execute pipeline stage. At the end of the dispatch pipeline stage,  
the dispatched instructions and their operands are latched by the appropriate  
execution unit.  
¥
During the execute pipeline stage, each execution unit that has an executable  
instruction executes the selected instruction (perhaps over multiple cycles), writes  
the instruction's result into the appropriate rename register, and notiÞes the  
completion stage that the instruction has Þnished execution.  
The execution unit reports any internal exceptions to the completion/writeback  
pipeline stage and discontinues execution until the exception is handled. The  
exception is not signaled until that instruction is the next to be completed. Execution  
of most load/store instructions is also pipelined. The load/store unit has two pipeline  
stages. The Þrst stage is for effective address calculation and MMU translation and  
the second stage is for accessing the data in the cache.  
¥
The complete/writeback pipeline stage maintains the correct architectural machine  
state and transfers the contents of the rename registers to the GPRs and FPRs as  
instructions are retired. If the completion logic detects an instruction causing an  
exception, all following instructions are cancelled, their execution results in rename  
registers are discarded, and instructions are fetched from the correct instruction  
stream.  
The processor core provides support for single-cycle store operations and it provides an  
adder/comparator in the SRU that allows the dispatch and execution of multiple integer add  
and compare instructions on each cycle.  
Performance of integer divide operations has been improved in the processor core. A divide  
instruction takes half the cycles to execute as described in the MPC603e UserÕs Manual.  
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The new latency is reßected in Table 2-6.  
Table 2-6. Integer Divide Latency  
Primary Opcode  
Extended Opcode  
Mnemonic  
Form  
Unit  
Cycles  
31  
31  
459  
491  
divwu[o][.]  
xo  
xo  
IU  
IU  
20  
20  
divw[o][.]  
2.8 Differences between the MPC8260Õs Core and the  
PowerPC 603e Microprocessor  
The MPC8260Õs processor core is a derivative of the MPC603e microprocessor design.  
Some changes have been made and are visible either to a programmer or a system designer.  
Any software designed around an MPC603e is functional when replaced with the  
MPC8260 except for the speciÞc customer-visible changes listed in Table 2-7.  
Software can distinguish between the MPC603e and the MPC8260 by reading the  
processor version register (PVR). The MPC8260Õs processor version number is 0x0081; the  
processor revision level starts at 0x0100 and is incremented for each revision of the chip.  
Table 2-7. Major Differences between MPC8260Õs Core and the MPC603e UserÕs  
Manual  
Description  
Impact  
Added bus multipliers of 4.5x, 5x, 5.5x, Occupies unused encodings of the PLL_CFG[0Ð4]  
6x, 6.5x 7x, 7.5x, 8x  
No FPU  
Floating-point arithmetic instructions are not supported in hardware.  
Added hardware support for  
misaligned little endian accesses  
Except for strings/multiples, little-endian load/store accesses not on a word  
boundary generate exceptions under the same circumstances as big-  
endian accesses.  
Removed misalignment support for  
These instructions take an alignment exception if not on a word boundary.  
eciwx and ecowx instructions.  
Added ability to broadcast dcbf, dcbi, Setting HID0[ABE] enables the new broadcast feature (new in the PID7v-  
and dcbst onto the 60x bus 603e). The default is to not broadcast these operations.  
Added ability to reßect the value of the Setting HID0[IFEM] enables this feature.The default is to not present the M  
M bit onto the 60x bus during  
instruction translations  
bit on the bus.  
Removed HID0[EICE]  
There is no support for ICE pipeline tracking.  
Added instruction and data cache  
locking mechanism  
Implements a cache way locking mechanism for both the instruction and  
data caches. One to three of the four ways in the cache can be locked with  
control bits in the HID2 register. See Section 2.3.1.2.3, ÒHardware  
Implementation-Dependent Register 2 (HID2).Ó  
Added pin-conÞgurable reset vector  
The value of MSR[IP], interrupt preÞx, is determined at hard reset by the  
hardware conÞguration word.  
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Table 2-7. Major Differences between MPC8260Õs Core and the MPC603e UserÕs  
Manual  
Description  
Impact  
Addition of speed-for-power  
functionality  
The processor core implements an additional dynamic power management  
mechanism. HID2[SFP] controls this function. See Section 2.3.1.2.3,  
ÒHardware Implementation-Dependent Register 2 (HID2).Ó  
Improved access to cache during block The MPC8260 provides quicker access to incoming data and instruction on  
Þlls  
a cache block Þll. See Section 2.4.2, ÒMPC8260 Implementation-SpeciÞc  
Cache Implementation.Ó  
Improved integer divide latency  
Performance of integer divide operations has been improved in the  
processor core. A divide takes half the cycles to execute as described in  
MPC603e UserÕs Manual. The new latency is reßected in Table 2-6.  
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Chapter 3  
Memory Map  
30  
30  
The MPC8260's internal memory resources are mapped within a contiguous block of  
memory. The size of the internal space in the MPC8260 is 128 Kbytes. The location of this  
block within the global 4-Gbyte real memory space can be mapped on 128 Kbytes  
resolution through an implementation speciÞc special register called the internal memory  
map register (IMMR). For more information, see Section 4.3.2.7, ÒInternal Memory Map  
Register (IMMR). The following table deÞnes the internal memory map of the MPC8260.  
Table 3-1 deÞnes the internal memory map of the MPC8260.  
Table 3-1. Internal Memory Map  
Internal  
Address  
Abbreviation  
Name  
Size  
Section/Page Number  
CPM Dual-Port RAM  
00000Ð03FFF DPRAM1  
04000Ð07FFF Reserved  
08000Ð08FFF DPRAM2  
09000Ð0AFFF Reserved  
0B000Ð0BFFF DPRAM3  
0C000Ð0FFFF Reserved  
Dual-port RAM  
16 Kbytes 13.5/13-15  
Ñ
16 Kbytes  
4 Kbytes  
8 Kbytes  
4 Kbytes  
16 Kbytes  
Ñ
Dual-port RAM  
13.5/13-15  
Ñ
Ñ
Dual-port RAM  
Ñ
13.5/13-15  
Ñ
General SIU  
10000  
10004  
10008  
1000E  
SIUMCR  
SYPCR  
Reserved  
SWSR  
SIU module conÞguration register  
System protection control register  
Ñ
32 bits  
32 bits  
6 bytes  
16 bits  
20 bytes  
32 bits  
8 bits  
4.3.2.6/4-31  
4.3.2.8/4-35  
Ñ
Software service register  
Ñ
4.3.2.9/4-36  
Ñ
10010Ð10023 Reserved  
10024  
10028  
1002C  
BCR  
Bus conÞguration register  
60x bus arbiter conÞguration register  
4.3.2.1/4-25  
4.3.2.2/4-28  
4.3.2.3/4-28  
PPC_ACR  
PPC ALRH  
60x bus arbitration-level register high 32 bits  
(Þrst 8 clients)  
MOTOROLA  
Chapter 3. Memory Map  
3-1  
                     
Part I. Overview  
Table 3-1. Internal Memory Map (Continued)  
Internal  
Address  
Abbreviation  
Name  
Size  
32 bits  
Section/Page Number  
4.3.2.3/4-28  
10030  
PPC_ALRL  
60x bus arbitration-level register low  
(next 8 clients)  
10034  
10038  
LCL_ACR  
Local arbiter conÞguration register  
8 bits  
4.3.2.4/4-29  
4.3.2.5/4-30  
LCL_ALRH  
Local arbitration-level register (Þrst 8  
clients)  
32 bits  
1003C  
10040  
10044  
10048  
1004C  
LCL_ALRL  
TESCR1  
Local arbitration-level register (next 8 32 bits  
clients)  
4.3.2.3/4-28  
4.3.2.10/4-36  
4.3.2.11/4-37  
4.3.2.12/4-38  
4.3.2.13/4-39  
60x bus transfer error status control  
register 1  
32 bits  
TESCR2  
60x bus transfer error status control  
register 2  
32 bits  
L_TESCR1  
L_TESCR2  
Local bus transfer error status control 32 bits  
register 1  
Local bus transfer error status control 32 bits  
register 2  
10050  
10054  
10055  
10058  
1005C  
PDTEA  
PDTEM  
Reserved  
LDTEA  
60x bus DMA transfer error address  
60x bus DMA transfer error MSNUM  
Ñ
32 bits  
8 bits  
18.2.3/18-4  
18.2.4/18-4  
Ñ
24 bits  
Local bus DMA transfer error address 32 bits  
Local bus DMA transfer error MSNUM 8 bits  
18.2.3/18-4  
18.2.4/18-4  
Ñ
LDTEM  
1005DÐ100FF Reserved  
Ñ
163 bytes  
Memory Controller  
10100  
10104  
10108  
1010C  
10110  
10114  
10118  
1011C  
10120  
10124  
10128  
1012C  
10130  
BR0  
OR0  
BR1  
OR1  
BR2  
OR2  
BR3  
OR3  
BR4  
OR4  
BR5  
OR5  
BR6  
Base register bank 0  
Option register bank 0  
Base register bank 1  
Option register bank 1  
Base register bank 2  
Option register bank 2  
Base register bank 3  
Option register bank 3  
Base register bank 4  
Option register bank 4  
Base register bank 5  
Option register bank 5  
Base register bank 6  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
10.3.1/10-14  
10.3.2/10-16  
10.3.1/10-14  
10.3.2/10-16  
10.3.1/10-14  
10.3.2/10-16  
10.3.1/10-14  
10.3.2/10-16  
10.3.1/10-14  
10.3.2/10-16  
10.3.1/10-14  
10.3.2/10-16  
10.3.1/10-14  
3-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
                                                 
Part I. Overview  
Table 3-1. Internal Memory Map (Continued)  
Internal  
Address  
Abbreviation  
Name  
Size  
32 bits  
Section/Page Number  
10134  
OR6  
Option register bank 6  
Base register bank 7  
Option register bank 7  
Base register bank 8  
Option register bank 8  
Base register bank 9  
Option register bank 9  
Base register bank 10  
Option register bank 10  
Base register bank 11  
Option register bank 11  
Ñ
10.3.2/10-16  
10138  
1013C  
10140  
10144  
10148  
1014C  
10150  
10154  
10158  
1015C  
10160  
10168  
1016C  
10170  
10174  
10178  
1017C  
10184  
10188  
1018C  
10190  
10194  
10198  
1019C  
BR7  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
8 bytes  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
48 bits  
16 bits  
32 bits  
32 bits  
32 bits  
32 bits  
8 bits  
10.3.1/10-14  
10.3.2/10-16  
10.3.1/10-14  
10.3.2/10-16  
10.3.1/10-14  
10.3.2/10-16  
10.3.1/10-14  
10.3.2/10-16  
10.3.1/10-14  
10.3.2/10-16  
Ñ
OR7  
BR8  
OR8  
BR9  
OR9  
BR10  
OR10  
BR11  
OR11  
Reserved  
MAR  
Memory address register  
Ñ
10.3.7/10-29  
Ñ
Reserved  
MAMR  
MBMR  
MCMR  
Reserved  
MPTPR  
MDR  
Machine A mode register  
Machine B mode register  
Machine C mode register  
Ñ
10.3.5/10-26  
Ñ
Memory periodic timer prescaler  
Memory data register  
Ñ
10.3.12/10-32  
10.3.6/10-28  
Ñ
Reserved  
PSDMR  
LSDMR  
PURT  
PSRT  
60x bus SDRAM mode register  
Local bus SDRAM mode register  
60x bus-assigned UPM refresh timer  
10.3.3/10-21  
10.3.4/10-24  
10.3.8/10-30  
10.3.10/10-31  
60x bus-assigned SDRAM refresh  
timer  
8 bits  
101A0  
101A4  
LURT  
LSRT  
Local bus-assigned UPM refresh timer 8 bits  
10.3.9/10-30  
10.3.11/10-32  
Local bus-assigned SDRAM refresh  
timer  
8 bits  
101A8  
IMMR  
Internal memory map register  
32 bits  
4.3.2.7/4-34  
Ñ
101ACÐ101FF Reserved  
84 bytes  
Ñ
MOTOROLA  
Chapter 3. Memory Map  
3-3  
                                               
Part I. Overview  
Table 3-1. Internal Memory Map (Continued)  
Internal  
Address  
Abbreviation  
Name  
Size  
Section/Page Number  
System Integration Timers  
10200Ð10 21F Reserved  
Ñ
32 bytes  
16 bits  
10220  
TMCNTSC  
Time counter status and control  
register  
4.3.2.14/4-40  
10224  
10228  
1022C  
TMCNT  
Time counter register  
32 bits  
32 bits  
32 bits  
16 bytes  
16 bits  
4.3.2.15/4-41  
Ñ
Reserved  
TMCNTAL  
Ñ
Time counter alarm register  
Ñ
4.3.2.16/4-41  
Ñ
10230Ð1023F Reserved  
10240  
PISCR  
Periodic interrupt status and control  
register  
4.3.3.1/4-42  
10244  
10248  
PITC  
PITR  
Periodic interrupt count register  
32 bits  
4.3.3.2/4-43  
Periodic interrupt timer register  
32 bits  
4.3.3.3/4-44  
1024CÐ102A8 Reserved  
102AAÐ10BFF Reserved  
Ñ
Ñ
94 bytes  
2,390bytes  
Ñ
Ñ
Interrupt Controller  
10C00  
10C04  
10C08  
10C0C  
10C10  
10C14  
10C18  
10C1C  
10C20  
10C24  
SICR  
SIU interrupt conÞguration register  
SIU interrupt vector register  
16 bits  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
4.3.1.1/4-17  
4.3.1.6/4-23  
4.3.1.4/4-21  
4.3.1.4/4-21  
4.3.1.2/4-18  
4.3.1.3/4-19  
4.3.1.3/4-19  
4.3.1.5/4-22  
4.3.1.5/4-22  
4.3.1.7/4-24  
SIVEC  
SIPNR_H  
SIPNR_L  
SIPRR  
SIU interrupt pending register (high)  
SIU interrupt pending register (low)  
SIU interrupt priority register  
SCPRR_H  
SCPRR_L  
SIMR_H  
SIMR_L  
SIEXR  
CPM interrupt priority register (high)  
CPM interrupt priority register (low)  
SIU interrupt mask register (high)  
SIU interrupt mask register (low)  
SIU external interrupt control register 32 bits  
10C28Ð10C7F Reserved  
Clocks and Reset  
10C80  
10C88  
10C90  
10C94  
SCCR  
SCMR  
RSR  
System clock control register  
System clock mode register  
Reset status register  
Reset mode register  
Ñ
32 bits  
32 bits  
32 bits  
32 bits  
104 bytes  
9.8/9-8  
9.9/9-9  
5.2/5-4  
5.3/5-5  
Ñ
RMR  
10C98Ð10CFF Reserved  
3-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
                                             
Part I. Overview  
Table 3-1. Internal Memory Map (Continued)  
Internal  
Address  
Abbreviation  
Name  
Size  
Section/Page Number  
Input/Output Port  
10D00  
PDIRA  
PPARA  
PSORA  
PODRA  
PDATA  
Port A data direction register  
32 bits  
35.2.3/35-3  
10D04  
10D08  
10D0C  
10D10  
Port A pin assignment register  
Port A special options register  
Port A open drain register  
Port A data register  
32 bits  
32 bits  
32 bits  
32 bits  
12 bytes  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
12 bytes  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
12 bytes  
32 bits  
32 bits  
32 bits  
32 bits  
32 bits  
35.2.4/35-4  
35.2.5/35-4  
35.2.1/35-2  
35.2.2/35-2  
Ñ
10D14Ð10D1F Reserved  
Ñ
10D20  
10D24  
10D28  
10D2C  
10D30  
PDIRB  
PPARB  
PSORB  
PODRB  
PDATB  
Port B data direction register  
Port B pin assignment register  
Port B special operation register  
Port B open drain register  
Port B data register  
35.2.3/35-3  
35.2.4/35-4  
35.2.5/35-4  
35.2.1/35-2  
35.2.2/35-2  
Ñ
10D34Ð10D3F Reserved  
Ñ
10D40  
10D44  
10D48  
10D4C  
10D50  
PDIRC  
PPARC  
PSORC  
PODRC  
PDATC  
Port C data direction register  
Port C pin assignment register  
Port C special operation register  
Port C open drain register  
Port C data register  
35.2.3/35-3  
35.2.4/35-4  
35.2.5/35-4  
35.2.1/35-2  
35.2.2/35-2  
Ñ
10D54Ð10D5F Reserved  
Ñ
10D60  
10D64  
10D68  
10D6C  
10D70  
PDIRD  
PPARD  
PSORD  
PODRD  
PDATD  
Port D data direction register  
Port D pin assignment register  
Port D special operation register  
Port D open drain register  
Port D data register  
35.2.3/35-3  
35.2.4/35-4  
35.2.5/35-4  
35.2.1/35-2  
35.2.2/35-2  
CPM Timers  
10D80  
TGCR1  
Timer 1 and timer 2 global  
conÞguration register  
8 bits  
17.2.2/17-4  
10D81  
10D84  
Reserved  
TGCR2  
Ñ
3 bytes  
8 bits  
Ñ
Timer 3 and timer 4 global  
conÞguration register  
17.2.2/17-4  
10D85Ð10D8F Reserved  
Ñ
11 bytes  
16 bits  
Ñ
10D90  
TMR1  
Timer 1 mode register  
17.2.3/17-6  
MOTOROLA  
Chapter 3. Memory Map  
3-5  
                                                 
Part I. Overview  
Table 3-1. Internal Memory Map (Continued)  
Internal  
Address  
Abbreviation  
Name  
Size  
16 bits  
Section/Page Number  
17.2.3/17-6  
10D92  
10D94  
10D96  
10D98  
10D9A  
10D9C  
10D9E  
10DA0  
10DA2  
10DA4  
10DA6  
10DA8  
10DAA  
10DAC  
10DAE  
10DB0  
10DB2  
10DB4  
10DB6  
TMR2  
TRR1  
TRR2  
TCR1  
TCR2  
TCN1  
TCN2  
TMR3  
TMR4  
TRR3  
TRR4  
TCR3  
TCR4  
TCN3  
TCN4  
TER1  
TER2  
TER3  
TER4  
Timer 2 mode register  
Timer 1 reference register  
Timer 2 reference register  
Timer 1 capture register  
Timer 2 capture register  
Timer 1 counter  
16 bits  
16 bits  
16 bits  
16 bits  
16 bits  
16 bits  
16 bits  
16 bits  
16 bits  
16 bits  
16 bits  
16 bits  
16 bits  
16 bits  
16 bits  
16 bits  
16 bits  
16 bits  
670 bytes  
17.2.4/17-7  
17.2.4/17-7  
17.2.5/17-8  
17.2.5/17-8  
17.2.6/17-8  
17.2.6/17-8  
17.2.3/17-6  
17.2.3/17-6  
17.2.4/17-7  
17.2.4/17-7  
17.2.5/17-8  
17.2.5/17-8  
17.2.6/17-8  
17.2.6/17-8  
17.2.7/17-8  
17.2.7/17-8  
17.2.7/17-8  
17.2.7/17-8  
Ñ
Timer 2 counter  
Timer 3 mode register  
Timer 4 mode register  
Timer 3 reference register  
Timer 4 reference register  
Timer 3 capture register  
Timer 4 capture register  
Timer 3 counter  
Timer 4 counter  
Timer 1 event register  
Timer 2 event register  
Timer 3 event register  
Timer 4 event register  
Ñ
10D74Ð11017 Reserved  
SDMAÐGeneral  
11018  
11019  
1101C  
1101D  
SDSR  
SDMA status register  
8 bits  
18.2.1/18-3  
Reserved  
SDMR  
Ñ
24 bits  
8 bits  
Ñ
SDMA mask register  
Ñ
18.2.2/18-4  
Ñ
Reserved  
24 bits  
IDMA  
11020  
11021  
11024  
11025  
11028  
IDSR1  
IDMA 1 event register  
8 bits  
24 bits  
8 bits  
24 bits  
8 bits  
18.8.4/18-22  
Ñ
Reserved  
IDMR1  
Ñ
IDMA 1 mask register  
Ñ
18.8.4/18-22  
Ñ
Reserved  
IDSR2  
IDMA 2 event register  
18.8.4/18-22  
3-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
                                               
Part I. Overview  
Table 3-1. Internal Memory Map (Continued)  
Internal  
Address  
Abbreviation  
Name  
Size  
24 bits  
Section/Page Number  
11029  
Reserved  
IDMR2  
Ñ
Ñ
1102C  
1102D  
11030  
11031  
11034  
11035  
11038  
11039  
1103C  
IDMA 2 mask register  
8 bits  
18.8.4/18-22  
Reserved  
IDSR3  
Ñ
24 bits  
8 bits  
Ñ
IDMA 3 event register  
18.8.4/18-22  
Reserved  
IDMR3  
Ñ
24 bits  
8 bits  
Ñ
IDMA 3 mask register  
18.8.4/18-22  
Reserved  
IDSR4  
Ñ
24 bits  
8 bits  
Ñ
IDMA 4 event register  
18.8.4/18-22  
Reserved  
IDMR4  
Ñ
24 bits  
8 bits  
Ñ
IDMA 4 mask register  
Ñ
18.8.4/18-22  
Ñ
1103DÐ112FF Reserved  
707 bytes  
FCC1  
FCC1 general mode register  
11300  
11304  
GFMR1  
32 bits  
28.2/28-3  
FPSMR1  
FCC1 protocol-speciÞc mode register 32 bits  
29.13.2/29-85 (ATM)  
30.18.1/30-20 (Ethernet)  
31.6/31-7 (HDLC)  
11308  
1130A  
1130C  
1130E  
11310  
11314  
FTODR1  
Reserved  
FDSR1  
FCC1 transmit on demand register  
16 bits  
2 bytes  
16 bits  
2 bytes  
32 bits  
32 bits  
28.5/28-7  
Ñ
Ñ
FCC1 data synchronization register  
Ñ
28.4/28-7  
Ñ
Reserved  
FCCE1  
FCC1 event register  
FCC1 mask register  
29.13.3/29-87 (ATM)  
30.18.2/30-21 (Ethernet)  
31.9/31-14 (HDLC)  
FCCM1  
11318  
11319  
1131C  
1131D  
1131E  
1131F  
FCCS1  
FCC1 status register  
Ñ
8 bits  
3 bytes  
8 bits  
8 bits  
8 bits  
8 bits  
31.10/31-16 (HDLC)  
Ñ
Reserved  
FTIRR1_PHY0 FCC1 transmit internal rate registers  
for PHY0Ð3  
FTIRR1_PHY1  
29.13.4/29-88 (ATM)  
FTIRR1_PHY2  
FTIRR1_PHY3  
FCC2  
11320  
11324  
GFMR2  
FCC2 general mode register  
32 bits  
28.2/28-3  
FPSMR2  
FCC2 protocol-speciÞc mode register 32 bits  
29.13.2/29-85 (ATM)  
30.18.1/30-20 (Ethernet)  
31.6/31-7 (HDLC)  
MOTOROLA  
Chapter 3. Memory Map  
3-7  
                                 
Part I. Overview  
Table 3-1. Internal Memory Map (Continued)  
Internal  
Address  
Abbreviation  
Name  
Size  
16 bits  
Section/Page Number  
28.5/28-7  
11328  
1132A  
1132C  
1132E  
11330  
11334  
FTODR2  
Reserved  
FDSR2  
FCC2 transmit on-demand register  
Ñ
2 bytes  
16 bits  
2 bytes  
32 bits  
32 bits  
Ñ
FCC2 data synchronization register  
Ñ
28.4/28-7  
Ñ
Reserved  
FCCE2  
FCC2 event register  
FCC2 mask register  
29.13.3/29-87 (ATM)  
30.18.2/30-21 (Ethernet)  
31.9/31-14 (HDLC)  
FCCM2  
11338  
11339  
1133C  
1133D  
1133E  
1133F  
FCCS2  
FCC2 status register  
Ñ
8 bits  
3 bytes  
8 bits  
8 bits  
8 bits  
8 bits  
31.10/31-16 (HDLC)  
Ñ
Reserved  
FTIRR2_PHY0 FCC2 transmit internal rate registers  
for PHY0Ð3  
FTIRR2_PHY1  
29.13.4/29-88 (ATM)  
FTIRR2_PHY2  
FTIRR2_PHY3  
FCC3  
11340  
11344  
GFMR3  
FCC3 general mode register  
32 bits  
28.2/28-3  
FPSMR3  
FCC3 protocol-speciÞc mode register 32 bits  
29.13.2/29-85 (ATM)  
30.18.1/30-20 (Ethernet)  
31.6/31-7 (HDLC)  
11348  
1134A  
1134C  
1134E  
11350  
11354  
FTODR3  
Reserved  
FDSR3  
FCC3 transmit on-demand register  
16 bits  
2 bytes  
16 bits  
2 bytes  
32 bits  
32 bits  
28.5/28-7  
Ñ
Ñ
FCC3 data synchronization register  
Ñ
28.4/28-7  
Ñ
Reserved  
FCCE3  
FCC3 event register  
FCC3 mask register  
29.13.3/29-87 (ATM)  
30.18.2/30-21 (Ethernet)  
31.9/31-14 (HDLC)  
FCCM3  
11358  
FCCS3  
FCC3 status register  
Reserved  
8 bits  
31.10/31-16 (HDLC)  
Ñ
11359Ð113FF Reserved  
167 bytes  
BRGs 5Ð8  
115F0  
115F4  
115F8  
115FC  
BRGC5  
BRGC6  
BRGC7  
BRGC8  
BRG5 conÞguration register  
BRG6 conÞguration register  
BRG7 conÞguration register  
BRG8 conÞguration register  
Reserved  
32 bits  
32 bits  
32 bits  
32 bits  
608 bytes  
16.1/16-2  
11600Ð1185F Reserved  
Ñ
3-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
                                 
Part I. Overview  
Table 3-1. Internal Memory Map (Continued)  
Internal  
Address  
Abbreviation  
Name  
Size  
Section/Page Number  
2
I C  
2
11860  
I2MOD  
I C mode register  
8 bits  
34.4.1/34-6  
11862  
11864  
11866  
11868  
1186A  
1186C  
1186E  
11870  
11872  
11874  
Reserved  
I2ADD  
Ñ
24 bits  
8 bits  
Ñ
2
I C address register  
34.4.2/34-7  
Reserved  
I2BRG  
Ñ
24 bits  
8 bits  
Ñ
2
I C BRG register  
34.4.3/34-7  
Reserved  
I2COM  
Ñ
24 bits  
8 bits  
Ñ
2
I C command register  
34.4.5/34-8  
Reserved  
I2CER  
Ñ
24 bits  
8 bits  
Ñ
2
I C event register  
34.4.4/34-8  
Reserved  
I2CMR  
Ñ
24 bits  
8 bits  
Ñ
2
I C mask register  
34.4.4/34-8  
Ñ
11875Ð119BF Reserved  
Ñ
315 bytes  
Communications Processor  
119C0  
119C4  
CPCR  
RCCR  
Communications processor command 32 bits  
register  
13.4.1/13-11  
CP conÞguration register  
Ñ
32 bits  
12 bytes  
16 bits  
16 bits  
16 bits  
16 bits  
32 bits  
13.3.6/13-7  
Ñ
119C8Ð119D5 Reserved  
119D6  
119DA  
119DC  
119DE  
119E0  
RTER  
CP timers event register  
CP timers mask register  
CP time-stamp timer control register  
Ñ
13.6.4/13-21  
RTMR  
RTSCR  
Reserved  
RTSR  
13.3.7/13-9  
CP time-stamp register  
13.3.8/13-10  
BRGs 1Ð4  
119F0  
119F4  
119F8  
119FC  
BRGC1  
BRGC2  
BRGC3  
BRGC4  
BRG1 conÞguration register  
BRG2 conÞguration register  
BRG3 conÞguration register  
BRG4 conÞguration register  
32 bits  
32 bits  
32 bits  
32 bits  
16.1/16-2  
SCC1  
11A00  
11A04  
GSMR_L1  
GSMR_H1  
SCC1 general mode register  
SCC1 general mode register  
32 bits  
32 bits  
19.1.1/19-3  
MOTOROLA  
Chapter 3. Memory Map  
3-9  
                                       
Part I. Overview  
Table 3-1. Internal Memory Map (Continued)  
Internal  
Address  
Abbreviation  
Name  
Size  
Section/Page Number  
11A08  
PSMR1  
SCC1 protocol-speciÞc mode register 16 bits  
19.1.2/19-9  
20.16/20-13 (UART)  
21.8/21-7 (HDLC)  
22.11/22-10 (BISYNC)  
23.9/23-9 (Transparent)  
24.17/24-15 (Ethernet)  
11A0A  
11A0C  
11A0E  
11A10  
11A14  
Reserved  
TODR1  
DSR1  
Ñ
2 bytes  
16 bits  
16 bits  
16 bits  
16 bits  
Ñ
SCC1 transmit-on-demand register  
SCC1 data synchronization register  
SCC1 event register  
19.1.4/19-9  
19.1.3/19-9  
SCCE1  
SCCM1  
20.19/20-19 (UART)  
21.11/21-12 (HDLC)  
22.14/22-15 (BISYNC)  
23.12/23-12 (Transparent)  
24.20/24-21 (Ethernet)  
SCC1 mask register  
11A17  
SCCS1  
SCC1 status register  
8 bits  
20.20/20-21 (UART)  
21.12/21-14 (HDLC)  
22.15/22-16 (BISYNC)  
23.13/23-13 (Transparent)  
11A18Ð11A1F Reserved  
Ñ
8 bytes  
Ñ
SCC2  
11A20  
11A24  
11A28  
GSMR_L2  
GSMR_H2  
PSMR2  
SCC2 general mode register (low)  
SCC2 general mode register (high)  
32 bits  
32 bits  
19.1.1/19-3  
SCC2 protocol-speciÞc mode register 16 bits  
19.1.2/19-9  
20.16/20-13 (UART)  
21.8/21-7 (HDLC)  
22.11/22-10 (BISYNC)  
23.9/23-9 (Transparent)  
24.17/24-15 (Ethernet)  
11A2A  
11A2C  
11A2E  
11A30  
11A34  
Reserved  
TODR2  
DSR2  
Ñ
2 bytes  
16 bits  
16 bits  
16 bits  
16 bits  
Ñ
SCC2 transmit-on-demand register  
SCC2 data synchronization register  
SCC2 event register  
19.1.4/19-9  
19.1.3/19-9  
SCCE2  
SCCM2  
20.19/20-19 (UART)  
21.11/21-12 (HDLC)  
22.14/22-15 (BISYNC)  
23.12/23-12 (Transparent)  
24.20/24-21 (Ethernet)  
SCC2 mask register  
11A37  
SCCS2  
SCC2 status register  
8 bits  
20.20/20-21 (UART)  
21.12/21-14 (HDLC)  
22.15/22-16 (BISYNC)  
23.13/23-13 (Transparent)  
11A38Ð11A3F Reserved  
Ñ
8 bytes  
Ñ
3-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
                             
Part I. Overview  
Table 3-1. Internal Memory Map (Continued)  
Internal  
Address  
Abbreviation  
Name  
Size  
Section/Page Number  
SCC3  
11A40  
GSMR_L3  
GSMR_H3  
PSMR3  
SCC3 general mode register  
SCC3 general mode register  
32 bits  
32 bits  
19.1.1/19-3  
11A44  
11A48  
SCC3 protocol-speciÞc mode register 16 bits  
19.1.2/19-9  
20.16/20-13 (UART)  
21.8/21-7 (HDLC)  
22.11/22-10 (BISYNC)  
23.9/23-9 (Transparent)  
24.17/24-15 (Ethernet)  
11A4A  
11A4C  
11A4E  
11A50  
11A54  
Reserved  
TODR3  
DSR3  
Ñ
2 bytes  
16 bits  
16 bits  
16 bits  
16 bits  
Ñ
SCC3 transmit on demand register  
SCC3 data synchronization register  
SCC3 event register  
19.1.4/19-9  
19.1.3/19-9  
SCCE3  
SCCM3  
20.19/20-19 (UART)  
21.11/21-12 (HDLC)  
22.14/22-15 (BISYNC)  
23.12/23-12 (Transparent)  
24.20/24-21 (Ethernet)  
SCC3 mask register  
11A57  
SCCS3  
SCC3 status register  
8 bits  
20.20/20-21 (UART)  
21.12/21-14 (HDLC)  
22.15/22-16 (BISYNC)  
23.13/23-13 (Transparent)  
11A58Ð11A5F Reserved  
Ñ
8 bytes  
Ñ
SCC4  
11A60  
11A64  
11A68  
GSMR_L4  
GSMR_H4  
PSMR4  
SCC4 general mode register  
SCC4 general mode register  
32 bits  
32 bits  
19.1.1/19-3  
SCC4 protocol-speciÞc mode register 16 bits  
19.1.2/19-9  
20.16/20-13 (UART)  
21.8/21-7 (HDLC)  
22.11/22-10 (BISYNC)  
23.9/23-9 (Transparent)  
24.17/24-15 (Ethernet)  
11A6A  
11A6C  
11A6E  
11A70  
11A74  
Reserved  
TODR4  
DSR4  
Ñ
2 bytes  
16 bits  
16 bits  
16 bits  
16 bits  
Ñ
SCC4 transmit on-demand register  
SCC4 data synchronization register  
SCC4 event register  
19.1.4/19-9  
19.1.3/19-9  
SCCE4  
SCCM4  
20.19/20-19 (UART)  
21.11/21-12 (HDLC)  
22.14/22-15 (BISYNC)  
23.12/23-12 (Transparent)  
24.20/24-21 (Ethernet)  
SCC4 mask register  
MOTOROLA  
Chapter 3. Memory Map  
3-11  
                             
Part I. Overview  
Table 3-1. Internal Memory Map (Continued)  
Internal  
Address  
Abbreviation  
SCCS4  
Name  
SCC4 status register  
Size  
8 bits  
Section/Page Number  
11A77  
20.20/20-21 (UART)  
21.12/21-14 (HDLC)  
22.15/22-16 (BISYNC)  
23.13/23-13 (Transparent)  
11A78Ð11A7F Reserved  
Ñ
8 bytes  
Ñ
SMC1  
SMC2  
SPI  
11A82  
11A86  
11A8A  
SMCMR1  
SMCE1  
SMC1 mode register  
SMC1 event register  
SMC1 mask register  
16 bits  
8 bits  
8 bits  
26.2.1/26-3  
26.3.11/26-18 (UART)  
26.4.10/26-28 (Transparent)  
26.5.9/26-34 (GCI)  
SMCM1  
11A8BÐ11A 91 Reserved  
Ñ
7 bytes  
Ñ
11A92  
11A96  
11A9A  
SMCMR2  
SMCE2  
SMC2 mode register  
SMC2 event register  
SMC2 mask register  
16 bits  
8 bits  
8 bits  
26.2.1/26-3  
26.3.11/26-18 (UART)  
26.4.10/26-28 (Transparent)  
26.5.9/26-34 (GCI)  
SMCM2  
11A9BÐ11A9F Reserved  
Ñ
5 bytes  
Ñ
11AA0  
11AA2  
11AA6  
11AA7  
11AAA  
11AAB  
11AAD  
SPMODE  
Reserved  
SPIE  
SPI mode register  
16 bits  
4 bytes  
8 bits  
33.4.1/33-6  
Ñ
Ñ
SPI event register  
33.4.2/33-9  
Reserved  
SPIM  
Ñ
24 bits  
8 bits  
Ñ
SPI mask register  
Ñ
33.4.2/33-9  
Reserved  
SPCOM  
24 bits  
8 bits  
Ñ
SPI command register  
Ñ
33.4.3/33-9  
Ñ
11AA7Ð11AFF Reserved  
89 bytes  
CPM Mux  
11B00  
11B02  
11B03  
11B04  
11B08  
11B0C  
11B0D  
CMXSI1CR  
CMXSI2CR  
Reserved  
CMXFCR  
CMXSCR  
CMXSMR  
Reserved  
CPM mux SI1 clock route register  
CPM mux SI2 clock route register  
Ñ
8 bits  
8 bits  
8 bits  
32 bits  
32 bits  
8 bits  
8 bits  
15.4.2/15-10  
15.4.3/15-11  
Ñ
CPM mux FCC clock route register  
CPM mux SCC clock route register  
CPM mux SMC clock route register  
Ñ
15.4.4/15-12  
15.4.5/15-14  
15.4.6/15-17  
Ñ
3-12  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
                                     
Part I. Overview  
Table 3-1. Internal Memory Map (Continued)  
Internal  
Address  
Abbreviation  
Name  
Size  
16 bits  
Section/Page Number  
11B0E  
CMXUAR  
CPM mux UTOPIA address register  
Ñ
15.4.1/15-7  
11B10Ð11B1F Reserved  
16 bytes  
Ñ
SI1 Registers  
11B20  
11B22  
11B24  
11B26  
11B28  
11B2A  
11B2C  
11B2E  
SI1AMR  
SI1BMR  
SI1CMR  
SI1DMR  
SI1GMR  
SI1CMDR  
SI1STR  
SI1RSR  
SI1 TDMA1 mode register  
SI1 TDMB1 mode register  
SI1 TDMC1 mode register  
SI1 TDMD1 mode register  
SI1 global mode register  
SI1 command register  
16 bits  
16 bits  
16 bits  
16 bits  
8 bits  
14.5.2/14-17  
14.5.1/14-17  
14.5.4/14-24  
14.5.5/14-25  
14.5.3/14-23  
8 bits  
SI1 status register  
8 bits  
SI1 RAM shadow address register  
16 bits  
MCC1 Registers  
11B30  
11B34  
11B36  
11B38  
MCCE1  
MCCM1  
Reserved  
MCCF1  
MCC1 event register  
16 bits  
16 bits  
16 bits  
8 bits  
27.10.1/27-18  
MCC1 mask register  
Ñ
Ñ
MCC1 conÞguration register  
Ñ
27.8/27-15  
Ñ
11B39Ð11B3F Reserved  
7 bytes  
SI2 Registers  
11B40  
11B42  
11B44  
11B46  
11B48  
11B49  
11B4A  
11B4B  
11B4C  
11B4D  
11B4E  
SI2AMR  
SI2BMR  
SI2CMR  
SI2DMR  
SI2GMR  
Reserved  
SI2CMDR  
Reserved  
SI2STR  
SI2 TDMA2 mode register  
SI2 TDMB2 mode register  
SI2 TDMC2 mode register  
SI2 TDMD2 mode register  
SI2 global mode register  
Ñ
16 bits  
16 bits  
16 bits  
16 bits  
8 bits  
14.5.2/14-17  
14.5.1/14-17  
Ñ
8 bits  
SI2 command register  
Ñ
8 bits  
14.5.4/14-24  
Ñ
8 bits  
SI2 status register  
Ñ
8 bits  
14.5.5/14-25  
Ñ
Reserved  
SI2RSR  
8 bits  
SI2 RAM shadow address register  
16 bits  
14.5.3/14-23  
MOTOROLA  
Chapter 3. Memory Map  
3-13  
                                         
Part I. Overview  
Table 3-1. Internal Memory Map (Continued)  
Internal  
Address  
Abbreviation  
Name  
Size  
Section/Page Number  
MCC2 Registers  
11B50  
11B54  
11B58  
MCCE2  
MCCM2  
MCCF2  
MCC2 event register  
16 bits  
27.10.1/27-18  
MCC2 mask register  
MCC2 conÞguration register  
Ñ
16 bits  
8 bits  
27.8/27-15  
Ñ
11B59Ð11FFF Reserved  
1,159  
bytes  
SI1 RAM  
12000Ð121FF SI1TxRAM  
12200Ð123FF Reserved  
12400Ð125FF SI1RxRAM  
12600Ð127FF Reserved  
SI 1 transmit routing RAM  
512  
512  
512  
512  
14.4.3/14-10  
14.4.3/14-10  
SI 1 receive routing RAM  
SI2 RAM  
12800Ð129FF SI2TxRAM  
12A00Ð12BFF Reserved  
12C00Ð12DFF SI2RxRAM  
12E00Ð12FFF Reserved  
13000Ð137FF Reserved  
13800Ð13FFF Reserved  
SI 2 transmit routing RAM  
512  
14.4.3/14-10  
Ñ
512  
Ñ
SI 2 receive routing RAM  
512  
14.4.3/14-10  
Ñ
512  
Ñ
Ñ
Ñ
Reserved  
Reserved  
2048  
2048  
3-14  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part II  
ConÞguration and Reset  
Audience  
Part II is intended for system designers and programmers who need to understand the  
operation of the MPC8260 at start up. It assumes understanding of the PowerPC  
programming model described in the previous chapters and a high level understanding of  
the MPC8260.  
Contents  
Part II describes start-up behavior of the MPC8260.  
It contains the following chapters:  
¥
Chapter 4, ÒSystem Interface Unit (SIU),Ó describes the system conÞguration and  
protection functions which provide various monitors and timers, and the 60x bus  
conÞguration.  
¥
Chapter 5, ÒReset,Ó describes the behavior of the MPC8260 at reset and start-up.  
Suggested Reading  
Supporting documentation for the MPC8260 can be accessed through the world-wide web  
at http://www.motorola.com/netcomm and at http://www.mot.com/PowerPC. This  
documentation includes technical speciÞcations, reference materials, and detailed  
applications notes.  
MOTOROLA  
Part II. Configuration and Reset  
Part II-i  
   
Part II. Configuration and Reset  
Conventions  
This chapter uses the following notational conventions:  
Bold entries in Þgures and tables showing registers and parameter  
RAM should be initialized by the user.  
Bold  
mnemonics  
Instruction mnemonics are shown in lowercase bold.  
italics  
Italics indicate variable command parameters, for example, bcctrx.  
Book titles in text are set in italics.  
0x0  
PreÞx to denote hexadecimal number  
0b0  
PreÞx to denote binary number  
rA, rB  
rD  
Instruction syntax used to identify a source GPR  
Instruction syntax used to identify a destination GPR  
REG[FIELD]  
Abbreviations or acronyms for registers or buffer descriptors are  
shown in uppercase text. SpeciÞc bits, Þelds, or numerical ranges  
appear in brackets. For example, MSR[LE] refers to the little-endian  
mode enable bit in the machine state register.  
x
In certain contexts, such as in a signal encoding or a bit Þeld,  
indicates a donÕt care.  
n
Indicates an undeÞned numerical value  
Acronyms and Abbreviations  
Table i contains acronyms and abbreviations that are used in this document. Note that the  
meanings for some acronyms (such as SDR1 and DSISR) are historical, and the words for  
which an acronym stands may not be intuitively obvious.  
Table v. Acronyms and Abbreviated Terms  
Term  
BIST  
Meaning  
Built-in self test  
DMA  
DRAM  
EA  
Direct memory access  
Dynamic random access memory  
Effective address  
GPR  
IEEE  
LSB  
lsb  
General-purpose register  
Institute of Electrical and Electronics Engineers  
Least-signiÞcant byte  
Least-signiÞcant bit  
LSU  
MSB  
Load/store unit  
Most-signiÞcant byte  
Part II-ii  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part II. Configuration and Reset  
Table v. Acronyms and Abbreviated Terms (Continued)  
Term  
msb  
Meaning  
Most-signiÞcant bit  
MSR  
PCI  
Machine state register  
Peripheral component interconnect  
Real-time operating system  
Receive  
RTOS  
Rx  
SPR  
SWT  
Tx  
Special-purpose register  
Software watchdog timer  
Transmit  
MOTOROLA  
Part II. Configuration and Reset  
Part II-iii  
Part II. Configuration and Reset  
Part II-iv  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Chapter 4  
System Interface Unit (SIU)  
40  
40  
The system interface unit (SIU) consists of several functions that control system start-up  
and initialization, as well as operation, protection, and the external system bus. Key features  
of the SIU include the following:  
¥
¥
¥
¥
¥
¥
¥
¥
System conÞguration and protection  
System reset monitoring and generation  
Clock synthesizer  
Power management  
60x bus interface  
Flexible, high-performance memory controller  
Level-two cache controller interface  
IEEE 1149.1 test-access port (TAP)  
Figure 4-1 is a block diagram of the SIU.  
60x Bus (32-Bit Address/64-Bit Data)  
Core  
Configuration Registers  
Memory  
Controller  
PowerPC  
Control  
Control  
Counters  
Bridge  
Memory  
Controller  
Local  
Interrupt  
Controller  
Communications  
Processor  
Local Bus (18-Bit Address/32-Bit Data)  
Figure 4-1.SIU Block Diagram  
MOTOROLA  
Chapter 4. System Interface Unit (SIU)  
4-1  
       
Part II. ConÞguration and Reset  
The system conÞguration and protection functions provide various monitors and timers,  
including the bus monitor, software watchdog timer, periodic interrupt timer, and time  
counter. The clock synthesizer generates the clock signals used by the SIU and other  
MPC8260 modules. The SIU clocking scheme supports stop and normal modes.  
The 60x bus interface is a standard pipelined bus. The MPC8260 allows external bus  
masters to request and obtain system bus mastership. Chapter 8, ÒThe 60x Bus,Ó describes  
bus operation, but 60x bus conÞguration is explained in this section.  
The memory controller module, described in Chapter 10, ÒMemory Controller,Ó provides a  
seamless interface to many types of memory devices and peripherals. It supports up to  
twelve memory banks, each with its own device and timing attributes.  
The MPC8260Õs implementation supports circuit board test strategies through a user-  
accessible test logic that is fully compliant with the IEEE 1149.1 test access port.  
4.1 System ConÞguration and Protection  
The MPC8260 incorporates many system functions that normally must be provided in  
external circuits. In addition, it is designed to provide maximum system safeguards against  
hardware and/or software faults. Table 4-1 describes functions provided in the system  
conÞguration and protection submodule.  
Table 4-1. System Configuration and Protection Functions  
Function  
Description  
System The SIU allows the user to conÞgure the system according to the particular requirements. The  
conÞguration functions include control of parity checking and part and mask number constants.  
60x bus  
monitor  
Monitors the transfer acknowledge (TA) and address acknowledge (AACK) response time for all bus  
accesses initiated by internal or external masters. TEA is asserted if the TA/AACK response limit is  
exceeded. This function can be disabled if needed.  
Local bus  
monitor  
Monitors transfers between local bus internal masters and local bus slaves. An internal TEA assertion  
occurs if the transfer time limit is exceeded. This function can be disabled.  
Software  
watchdog  
timer  
Asserts a reset or NMI interrupt, selected by the system protection control register (SYPCR) if the  
software fails to service the software watchdog timer for a certain period of time (for example, because  
software is lost or trapped in a loop). After a system reset, this function is enabled, selects a maximum  
time-out period, and asserts a system reset if the time-out is reached. The software watchdog timer  
can be disabled or its time-out period may be changed in the SYPCR. Once the SYPCR is written, it  
cannot be written again until a system reset. For more information, see Section 4.1.5, ÒSoftware  
Watchdog Timer.Ó  
Periodic  
interrupt  
timer (PIT)  
Generates periodic interrupts for use with a real-time operating system or the application software.The  
periodic interrupt timer (PIT) is clocked by the timersclk clock, providing a period from 122 µs to  
8 seconds. The PIT function can be disabled if needed. See Section 4.1.4, ÒPeriodic Interrupt Timer  
(PIT).Ó  
Time  
counter  
Provides a time-of-day information to the operating system/application software. It is composed of a  
45-bit counter and an alarm register. A maskable interrupt is generated when the counter reaches the  
value programmed in the alarm register. The time counter (TMCNT) is clocked by the timersclk clock.  
See Section 4.1.3, ÒTime Counter (TMCNT).Ó  
4-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
             
Part II. ConÞguration and Reset  
Figure 4-2 is a block diagram of the system conÞguration and protection logic.  
Module  
Configuration  
System Reset  
CoreÕs MCP  
TEA  
Bus  
Bus clock/8  
timersclk  
Monitors  
Periodic Interrupt  
Timer  
Interrupt  
System Reset  
CoreÕs MCP  
Software  
Bus Clock  
timersclk  
Watchdog Timer  
Time  
Interrupt  
Counter  
Figure 4-2. System Configuration and Protection Logic  
Many aspects of system conÞguration are controlled by several SIU module conÞguration  
registers, described in Section 4.3.2, ÒSystem ConÞguration and Protection Registers.Ó  
4.1.1 Bus Monitor  
The MPC8260 has two bus monitors, one for the 60x bus and one for the local bus. The bus  
monitor ensures that each bus cycle is terminated within a reasonable period. The bus  
monitor does not count when the bus is idle. When a transaction starts (TS asserted), the  
bus monitor starts counting down from the time-out value. For standard bus transactions  
with an address tenure and a data tenure, the bus monitor counts until a data beat is  
acknowledged on the bus. It then reloads the time-out value and resumes the count down.  
This process continues until the whole data tenure is completed. Following the data tenure  
the bus monitor will idle in case there is no pending transaction; otherwise it will reload the  
time-out value and resume counting.  
For address-only transactions, the bus monitor counts until AACK is asserted. If the  
monitor times out for a standard bus transaction, transfer error acknowledge (TEA) is  
asserted. If the monitor times out for an address-only transaction, the bus monitor asserts  
AACK and a core machine check or reset interrupt is generated, depending on  
SYPCR[SWRI]. To allow variation in system peripheral response times, SYPCR[BMT]  
deÞnes the time-out period, whose maximum value can be 2,040 system bus clocks. The  
timing mechanism is clocked by the system bus clock divided by eight.  
MOTOROLA  
Chapter 4. System Interface Unit (SIU)  
4-3  
       
Part II. ConÞguration and Reset  
4.1.2 Timers Clock  
The two SIU timers (the time counter and the periodic interrupt timer) use the same clock  
source, timersclk, which can be derived from several sources, as described in Figure 4-3.  
The user should select external clock  
and/or BRG1 programming to yield ei-  
PISCR[PTF]  
ther 4 MHz or 32 KHz at this point.  
PC[26]  
Divide by 4  
timersclk for PIT  
Divide by 512  
Ports Programming  
CPM clock  
timersclk for TMCNT  
PC[27]  
BRG1  
PC[29]  
TMCNTSC[TCF]  
Ports Programming  
PC[25]  
Figure 4-3. Timers Clock Generation  
For details, see Section 35.2.4, ÒPort Pin Assignment Register (PPAR).Ó For proper time  
counter operation, the user must ensure that the frequency of timersclk for TMCNT is  
8,192 Hz by properly selecting the external clock and programming BRG1 and the  
prescaler control bits in the time counter status and control register (TMCNTSC[TCF]) and  
periodic interrupt status and control register (PISCR[PTF]).  
4.1.3 Time Counter (TMCNT)  
The time counter (TMCNT) is a 32-bit counter that is clocked by timersclk. It provides a  
time-of-day indication to the operating system and application software. The counter is  
reset to zero on PORESET reset but is not affected by soft or hard reset. It is initialized by  
the software; the user should set the timersclk frequency to 8,192 Hz, as explained in  
Section 4.1.2, ÒTimers Clock.Ó  
TMCNT can be programmed to generate a maskable interrupt when the time value matches  
the value in its associated alarm register. It can also be programmed to generate an interrupt  
every second. The time counter control and status register (TMCNTSC) is used to enable  
or disable the various timer functions and report the interrupt source. Figure 4-4 shows a  
block diagram of TMCNT.  
4-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part II. ConÞguration and Reset  
SEC  
Interrupt  
timersclk for TMCNT (8,192 Hz)  
Divide  
32-Bit Counter  
by 8,192  
Alarm  
=
Interrupt  
32-Bit Register  
Figure 4-4. TMCNT Block Diagram  
Section 4.3.2.15, ÒTime Counter Register (TMCNT),Ó describes the time counter register.  
4.1.4 Periodic Interrupt Timer (PIT)  
The periodic interrupt timer consists of a 16-bit counter clocked by timersclk. The 16-bit  
counter decrements to zero when loaded with a value from the periodic interrupt timer  
count register (PITC); after the timer reaches zero, PISCR[PS] is set and an interrupt is  
generated if PISCR[PIE] = 1. At the next input clock edge, the value in the PITC is loaded  
into the counter and the process repeats. When a new value is loaded into the PITC, the PIT  
is updated, the divider is reset, and the counter begins counting.  
Setting PS creates a pending interrupt that remains pending until PS is cleared. If PS is set  
again before being cleared, the interrupt remains pending until PS is cleared. Any write to  
the PITC stops the current countdown and the count resumes with the new value in PITC.  
If PTE = 0, the PIT cannot count and retains the old count value. The PIT is not affected by  
reads. Figure 4-5 is a block diagram of the PIT.  
PISCR[PTE]  
PITC  
timersclk  
for PIT  
Clock  
Disable  
16-Bit Modulus  
Counter  
PISCR[PS]  
PISCR[PIE]  
PIT  
Interrupt  
Figure 4-5. PIT Block Diagram  
MOTOROLA  
Chapter 4. System Interface Unit (SIU)  
4-5  
           
Part II. ConÞguration and Reset  
The time-out period is calculated as follows:  
PITC + 1  
PITC + 1  
8192  
PIT  
= ------------------------------------- = -------------------------  
timersclk  
period  
F
This gives a range from 122 µs (PITC = 0x0000) to 8 seconds (PITC = 0xFFFF).  
4.1.5 Software Watchdog Timer  
The SIU provides the software watchdog timer option to prevent system lock in case the  
software becomes trapped in loops with no controlled exit. Watchdog timer operations are  
conÞgured in the SYPCR, described in Section 4.3.2.8, ÒSystem Protection Control  
Register (SYPCR).Ó  
The software watchdog timer is enabled after reset to cause a soft reset if it times out. If the  
software watchdog timer is not needed, the user must clear SYPCR[SWE] to disable it. If  
used, the software watchdog timer requires a special service sequence to be executed  
periodically. Without this periodic servicing, the software watchdog timer times out and  
issues a reset or a nonmaskable interrupt, programmed in SYPCR[SWRI]. Once software  
writes SWRI, the state of SWE cannot be changed.  
The software watchdog timer service sequence consists of the following two steps:  
1. Write 0x556C to the software service register (SWSR)  
2. Write 0xAA39 to SWSR  
The service sequence clears the watchdog timer and the timing process begins again. If a  
value other than 0x556C or 0xAA39 is written to the SWSR, the entire sequence must start  
over. Although the writes must occur in the correct order before a time-out, any number of  
instructions can be executed between the writes. This allows interrupts and exceptions to  
occur between the two writes when necessary. Figure 4-6 shows a state diagram for the  
watchdog timer.  
Reset  
0x556C/DonÕt reload  
State 0  
State 1  
Waiting for 0xAA39  
Waiting for 0x556C  
0xAA39/Reload  
Not 0x556C/DonÕt reload  
Not 0xAA39/DonÕt reload  
Figure 4-6. Software Watchdog Timer Service State Diagram  
4-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part II. ConÞguration and Reset  
Although most software disciplines permit or even encourage the watchdog concept, some  
systems require a selection of time-out periods. For this reason, the software watchdog  
timer must provide a selectable range for the time-out period. Figure 4-7 shows how to  
handle this need.  
SWSR  
Service  
Logic  
SYPCR[SWTC]  
SWE  
Bus  
Clock  
Clock  
Divide By  
2,048  
Reload  
Disable  
16-Bit  
SWR/Decrementer  
MUX  
SWP  
Rollover = 0  
Reset  
or MCP  
Time-out  
Figure 4-7. Software Watchdog Timer Block Diagram  
In Figure 4-7, the range is determined by SYPCR[SWTC]. The value in SWTC is then  
loaded into a 16-bit decrementer clocked by the system clock. An additional divide-by-  
2,048 prescaler is used when needed.  
The decrementer begins counting when loaded with a value from SWTC. After the timer  
reaches 0x0, a software watchdog expiration request is issued to the reset or MCP control  
logic. Upon reset, SWTC is set to the maximum value and is again loaded into the software  
watchdog register (SWR), starting the process over. When a new value is loaded into  
SWTC, the software watchdog timer is not updated until the servicing sequence is written  
to the SWSR. If SYPCR[SWE] is loaded with 0, the modulus counter does not count.  
4.2 Interrupt Controller  
Key features of the interrupt controller include the following:  
¥
Communications processor module (CPM) interrupt sources (FCCs, SCCs, MCCs,  
2
timers, SMCs, I C, IDMA, SDMA, and SPI)  
¥
¥
¥
¥
Three SIU interrupt sources (PIT and TMCNT)  
24 external sources (16 port C and 8 IRQ)  
Programmable priority between PIT and TMCNT  
Programmable priority between SCCs, FCCs, and MCCs  
MOTOROLA  
Chapter 4. System Interface Unit (SIU)  
4-7  
           
Part II. ConÞguration and Reset  
¥
¥
¥
Two priority schemes for the SCCs: grouped, spread  
Programmable highest priority request  
Unique vector number for each interrupt source  
4.2.1 Interrupt ConÞguration  
Figure 4-8 shows the MPC8260 interrupt structure. The interrupt controller receives  
interrupts from internal sources, such as the PIT or TMCNT, from the CPM, and from  
external pins (port C parallel I/O pins).  
Software Watchdog Timer  
OR  
IRQ0  
IRQ[0Ð7]  
Fall/  
Level  
16  
MCP  
PowerPC  
Core  
TMCNT  
PIT  
Port C[0Ð15]  
Edge/  
Fall  
16  
Timer1  
Timer2  
Timer3  
Timer4  
FCC1  
FCC2  
FCC3  
MCC1  
MCC2  
SCC1  
SCC2  
SCC3  
SCC4  
SMC1  
SMC2  
SPI  
INT  
2
I C  
IDMA1  
IDMA2  
IDMA3  
IDMA4  
SDMA  
RISC Timers  
Figure 4-8. MPC8260 Interrupt Structure  
4-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part II. ConÞguration and Reset  
If the software watchdog timer is programmed to generate an interrupt, it always generates  
a machine check interrupt to the core. The external IRQ0 can generate MCP as well. Note  
that the core takes the machine check interrupt when MCP is asserted; it takes an external  
interrupt for any other interrupt asserted by the interrupt controller.  
The interrupt controller allows masking of each interrupt source. Multiple events within a  
CPM sub-block event are also maskable.  
All interrupt sources are prioritized and bits are set in the interrupt pending register  
(SIPNR). On the MPC8260, the prioritization of the interrupt sources is ßexible in the  
following two aspects:  
¥
¥
The relative priority of the FCCs, SCCs, and MCCs can be modiÞed  
One interrupt source can be assigned the highest priority  
When an unmasked interrupt source is pending in the SIPNR, the interrupt controller sends  
an interrupt request to the core. When an exception is taken, the interrupt mask bit in the  
machine state register (MSR[EE]) is cleared to disable further interrupt requests until  
software can handle them.  
The SIU interrupt vector register (SIVEC) is updated with a 6-bit vector corresponding to  
the sub-block with the highest current priority.  
4.2.2 Interrupt Source Priorities  
The interrupt controller has 37 interrupt sources that assert one interrupt request to the core.  
Table 4-2 shows prioritization of all interrupt sources. As described in following sections,  
ßexibility exists in the relative ordering of the interrupts, but, in general, relative priorities  
are as shown. A single interrupt priority number is associated with each table entry.  
Note that the group and spread options, shown withYCC entries in Table 4-2, are described  
in Section 4.2.2.1, ÒSCC, FCC, and MCC Relative Priority.Ó  
Table 4-2. Interrupt Source Priority Levels  
Priority Level  
Interrupt Source Description  
Multiple Events  
1
2
3
4
Highest  
XSIU1  
Ñ
No (TMCNT,PIT = Yes)  
No (TMCNT,PIT = Yes)  
No (TMCNT,PIT = Yes)  
XSIU2 (GSIU = 0)  
XSIU3 (GSIU = 0)  
MOTOROLA  
Chapter 4. System Interface Unit (SIU)  
4-9  
     
Part II. ConÞguration and Reset  
Table 4-2. Interrupt Source Priority Levels (Continued)  
Priority Level  
Interrupt Source Description  
Multiple Events  
5
XSIU4 (GSIU = 0)  
XCC1  
No (TMCNT,PIT = Yes)  
6
Yes  
7
XCC2  
Yes  
8
XCC3  
Yes  
9
XCC4  
Yes  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
XSIU2 (GSIU = 1)  
XCC5  
No (TMCNT,PIT = Yes)  
Yes  
XCC6  
Yes  
XCC7  
Yes  
XCC8  
Yes  
XSIU5 (GSIU = 0)  
XSIU6 (GSU = 0)  
XSIU7 (GSU = 0)  
XSIU8 (GSU = 0)  
XSIU3 (GSIU = 1)  
YCC1 (Grouped)  
YCC2 (Grouped)  
YCC3 (Grouped)  
YCC4 (Grouped)  
YCC5 (Grouped)  
YCC6 (Grouped)  
YCC7 (Grouped)  
YCC8 (Grouped)  
XSIU4 (GSIU = 1)  
Parallel I/OÐPC15  
Timer 1  
No (TMCNT,PIT = Yes)  
No (TMCNT,PIT = Yes)  
No (TMCNT,PIT = Yes)  
No (TMCNT,PIT = Yes)  
No (TMCNT,PIT = Yes)  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
No (TMCNT,PIT = Yes)  
Yes  
Yes  
Yes  
Yes  
Yes  
Parallel I/OÐPC14  
YCC1 (Spread)  
Parallel I/OÐPC13  
4-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part II. ConÞguration and Reset  
Table 4-2. Interrupt Source Priority Levels (Continued)  
Priority Level  
Interrupt Source Description  
Multiple Events  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
SDMA Bus Error  
IDMA1  
Yes  
Yes  
YCC2 (Spread)  
Parallel I/OÐPC12  
Parallel I/OÐPC11  
IDMA2  
Yes  
No  
No  
Yes  
Timer 2  
Yes  
Parallel I/OÐPC10  
XSIU5 (GSIU = 1)  
YCC3 (Spread)  
RISC Timer Table  
I2C  
No  
No (TMCNT,PIT = Yes)  
Yes  
Yes  
Yes  
YCC4 (Spread)  
Parallel I/OÐPC9  
Parallel I/OÐPC8  
IRQ6  
Yes  
No  
No  
No  
IDMA3  
Yes  
IRQ7  
No  
Timer 3  
Yes  
XSIU6 (GSIU = 1)  
YCC5 (Spread)  
Parallel I/OÐPC7  
Parallel I/OÐPC6  
Parallel I/OÐPC5  
Timer 4  
No (TMCNT,PIT = Yes)  
Yes  
No  
No  
No  
Yes  
YCC6 (Spread)  
Parallel I/OÐPC4  
XSIU7 (GSIU = 1)  
IDMA4  
Yes  
No  
No (TMCNT,PIT = Yes)  
Yes  
Yes  
No  
SPI  
Parallel I/OÐPC3  
Parallel I/OÐPC2  
No  
MOTOROLA  
Chapter 4. System Interface Unit (SIU)  
4-11  
Part II. ConÞguration and Reset  
Table 4-2. Interrupt Source Priority Levels (Continued)  
Priority Level  
Interrupt Source Description  
Multiple Events  
66  
67  
68  
69  
70  
71  
72  
73  
SMC1  
Yes  
YCC7 (spread)  
SMC2  
Yes  
Yes  
Parallel I/OÐPC1  
Parallel I/OÐPC0  
XSIU8 (GSIU = 1)  
YCC8(spread)  
Reserved  
No  
No  
No (TMCNT,PIT = Yes)  
Yes  
Ñ
Notice the lack of SDMA interrupt sources, which are reported through each individual  
2
FCC, SCC, SMC, SPI, or I C channel. The only true SDMA interrupt source is the SDMA  
channel bus error entry that is reported when a bus error occurs during an SDMA access.  
There are two ways to add ßexibility to the table of CPM interrupt prioritiesÑthe FCC,  
MCC, and SCC relative priority option, described in Section 4.2.2.1, ÒSCC, FCC, and  
MCC Relative Priority,Ó and the highest priority option, described in Section 4.2.2.3,  
ÒHighest Priority Interrupt.Ó  
4.2.2.1 SCC, FCC, and MCC Relative Priority  
The relative priority between the four SCCs, three FCCs, and MCC is programmable and  
can be changed dynamically. In Table 4-2 there is no entry for SCC1ÐSCC4, MCC1Ð  
MCC2, FCC1ÐFCC3, but rather there are entries for XCC1ÐXCC8 and YCC1ÐYCC8.  
Each SCC can be mapped to any YCC location and each FCC and MCC can be mapped to  
any XCC location. The SCC, FCC, and MCC priorities are programmed in the CPM  
interrupt priority registers (SCPRR_H and SCPRR_L) and can be changed dynamically to  
implement a rotating priority.  
In addition, the grouping of the locations of the YCC entries has the following two options  
¥
Group. In the group scheme, all SCCs are grouped together at the top of the priority  
table, ahead of most other CPM interrupt sources. This scheme is ideal for  
applications where all SCCs, FCCs, and MCCs function at a very high data rate and  
interrupt latency is very important.  
¥
Spread. In the spread scheme, priorities are spread over the table so other sources  
can have lower interrupt latencies. This scheme is also programmed in the SICR but  
cannot be changed dynamically.  
4.2.2.2 PIT, TMCNT, and IRQ Relative Priority  
The MPC8260 has seven general-purpose interrupt requests (IRQs), Þve of which, with the  
PIT, and TMCNT, can be mapped to any XSIU location. IRQ6 and IRQ7 have Þxed  
priority.  
4-12  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part II. ConÞguration and Reset  
4.2.2.3 Highest Priority Interrupt  
In addition to the FCC/MCC/SCC relative priority option, SICR[HP] can be used to specify  
one interrupt source as having highest priority. This interrupt remains within the same  
interrupt level as the other interrupt controller interrupts, but is serviced before any other  
interrupt in the table.  
If the highest priority feature is not used, select the interrupt request in XSIU1 to be the  
highest priority interrupt; the standard interrupt priority order is used. SICR[HP] can be  
updated dynamically to allow the user to change a normally low priority source into a high  
priority-source for a certain period.  
4.2.3 Masking Interrupt Sources  
By programming the SIU mask registers, SIMR_H and SIMR_L, the user can mask  
interrupt requests to the core. Each SIMR bit corresponds an interrupt source. To enable an  
interrupt, write a one to the corresponding SIMR bit. When a masked interrupt source has  
a pending interrupt request, the corresponding SIPNR bit is set, even though the interrupt  
is not generated to the core. The user can mask all interrupt sources to implement a polling  
interrupt servicing scheme.  
When an interrupt source has multiple interrupting events, the user can individually mask  
these events by programming a mask register within that block. Table 4-2 shows which  
interrupt sources have multiple interrupting events. Figure 4-9 shows an example of how  
the masking occurs, using an SCC as an example.  
MOTOROLA  
Chapter 4. System Interface Unit (SIU)  
4-13  
       
Part II. ConÞguration and Reset  
SCCE  
SIPNR  
Event  
Bit  
13 Input (or  
13 Event Bits)  
Request to  
the core  
(Other Unmasked Requests)  
SCCM  
SIMR  
Mask  
Bit  
Mask  
Bit  
Figure 4-9. Interrupt Request Masking  
4.2.4 Interrupt Vector Generation and Calculation  
Pending unmasked interrupts are presented to the core in order of priority. The interrupt  
vector that allows the core to locate the interrupt service routine is made available to the  
core by reading SIVEC. The interrupt controller passes an interrupt vector corresponding  
to the highest-priority, unmasked, pending interrupt. Table 4-3 lists encodings for the six  
low-order bits of the interrupt vector.  
Table 4-3. Encoding the Interrupt Vector  
Interrupt Number  
Interrupt Source Description  
Interrupt Vector  
0
1
2
3
4
5
Error (No interrupt)  
0b00_0000  
0b00_0001  
0b00_0010  
0b00_0011  
0b00_0100  
0b00_0101  
2
I C  
SPI  
RISC Timers  
SMC1  
SMC2  
4-14  
MPC8260 PowerQUICC II UserÕs Manual  
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Part II. ConÞguration and Reset  
Table 4-3. Encoding the Interrupt Vector (Continued)  
Interrupt Number  
Interrupt Source Description  
Interrupt Vector  
6
IDMA1  
IDMA2  
IDMA3  
IDMA4  
SDMA  
Reserved  
Timer1  
Timer2  
Timer3  
Timer4  
TMCNT  
PIT  
0b00_0110  
0b00_0111  
0b00_1000  
0b00_1001  
0b00_1010  
0b00_1011  
0b00_1100  
0b00_1101  
0b00_1110  
0b00_1111  
0b01_0000  
0b01_0001  
0b01_0010  
0b01_0011  
0b01_0100  
0b01_0101  
0b01_0110  
0b01_0111  
0b01_1000  
0b01_1001  
0b01_1010Ð01_1111  
0b10_0000  
0b10_0001  
0b10_0010  
0b10_0011  
0b10_0100  
0b10_0101  
0b10_0110  
0b10_0111  
0b10_1000  
0b10_1001  
0b10_1010  
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
Reserved  
IRQ1  
IRQ2  
IRQ3  
IRQ4  
IRQ5  
IRQ6  
IRQ7  
Reserved  
FCC1  
FCC2  
FCC3  
Reserved  
MCC1  
MCC2  
Reserved  
Reserved  
SCC1  
SCC2  
SCC3  
MOTOROLA  
Chapter 4. System Interface Unit (SIU)  
4-15  
Part II. ConÞguration and Reset  
Table 4-3. Encoding the Interrupt Vector (Continued)  
Interrupt Number  
Interrupt Source Description  
Interrupt Vector  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
SCC4  
Reserved  
PC15  
PC14  
PC13  
PC12  
PC11  
PC10  
PC9  
0b10_1011  
0b10_11xx  
0b11_0000  
0b11_0001  
0b11_0010  
0b11_0011  
0b11_0100  
0b11_0101  
0b11_0110  
0b11_0111  
0b11_1000  
0b11_1001  
0b11_1010  
0b11_1011  
0b11_1100  
0b11_1101  
0b11_1110  
0b11_1111  
PC8  
PC7  
PC6  
PC5  
PC4  
PC3  
PC2  
PC1  
PC0  
Note that the interrupt vector table differs from the interrupt priority table in only two ways:  
¥
¥
FCC, SCC, and MCC vectors are Þxed; they are not affected by the SCC group  
mode, spread mode, or the relative priority order of the FCCs, SCCs, and MCC.  
An error vector exists as the last entry in Table 4-3. The error vector is issued when  
no interrupt is requesting service.  
4.2.4.1 Port C External Interrupts  
There are 16 external interrupts, coming from the parallel I/O port C pins,PC[0Ð15]. When  
ones of these pins is conÞgured as an input, a change according to the SIU external interrupt  
control register (SIEXR) causes an interrupt request signal to be sent to the interrupt  
controller. PC[0Ð15] lines can be programmed to assert an interrupt request upon any  
change. Each port C line asserts a unique interrupt request to the interrupt pending register  
and has a different internal interrupt priority level within the interrupt controller.  
Requests can be masked independently in the interrupt mask register (SIMR). Notice that  
the global SIMR is cleared on system reset so pins left ßoating do not cause false interrupts.  
4-16  
MPC8260 PowerQUICC II UserÕs Manual  
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Part II. ConÞguration and Reset  
4.3 Programming Model  
The SIU registers are grouped into the following three categories:  
¥
Interrupt controller registers. These registers control conÞguration, prioritization,  
and masking of interrupts. They also include registers for determining the interrupt  
sources. These registers are described in Section 4.3.1, ÒInterrupt Controller  
Registers.Ó  
¥
System conÞguration and protection registers. These include registers for  
conÞguring the SIU, deÞning the base address for the internal memory map,  
conÞguring the watchdog timer, specifying bus characteristics, as well as general  
functionality of the 60x, and local buses such as arbitration, error status, and control.  
These registers are described in Section 4.3.2, ÒSystem ConÞguration and  
Protection Registers.Ó  
¥
Periodic interrupt registers. These include registers for conÞguring and providing  
status for periodic interrupts. See Section 4.3.3, ÒPeriodic Interrupt Registers.Ó  
4.3.1 Interrupt Controller Registers  
There are seven interrupt controller registers, described in the following sections:  
¥
¥
¥
¥
¥
¥
¥
Section 4.3.1.1, ÒSIU Interrupt ConÞguration Register (SICR)Ó  
Section 4.3.1.2, ÒSIU Interrupt Priority Register (SIPRR)Ó  
Section 4.3.1.3, ÒCPM Interrupt Priority Registers (SCPRR_H and SCPRR_L)Ó  
Section 4.3.1.4, ÒSIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)Ó  
Section 4.3.1.5, ÒSIU Interrupt Mask Registers (SIMR_H and SIMR_L)Ó  
Section 4.3.1.6, ÒSIU Interrupt Vector Register (SIVEC)Ó  
Section 4.3.1.7, ÒSIU External Interrupt Control Register (SIEXR)Ó  
4.3.1.1 SIU Interrupt ConÞguration Register (SICR)  
The SIU interrupt conÞguration register (SICR), shown in Figure 4-10, deÞnes the highest  
priority interrupt and whether interrupts are grouped or spread in the priority table,  
Table 4-2.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Ñ
HP  
Ñ
GSIU SPS  
0000_0000_0000_0000  
R/W  
Addr  
0x10C00  
Figure 4-10. SIU Interrupt Configuration Register (SICR)  
MOTOROLA  
Chapter 4. System Interface Unit (SIU)  
4-17  
             
Part II. ConÞguration and Reset  
The SICR register bits are described in Table 4-4.  
Table 4-4. SICR Field Descriptions  
Bits Name  
Description  
0Ð1  
2Ð7  
Ñ
Reserved, should be cleared.  
HP Highest priority. SpeciÞes the 6-bit interrupt number of the single interrupt controller interrupt source  
that is advanced to the highest priority in the table. HP can be modiÞed dynamically. To retain the  
original priority, program HP to the interrupt number assigned to XSIU1.  
8Ð14  
14  
Ñ
Reserved, should be cleared.  
GSIU Group SIU. Selects the relative XSIU priority scheme. It cannot be changed dynamically.  
0
1
Grouped. The XSIUs are grouped by priority at the top of the table.  
Spread. The XSIUs are spread by priority in the table.  
15  
SPS Spread priority scheme. Selects the relative YCC priority scheme. It cannot be changed dynamically.  
0
1
Grouped. The YCCs are grouped by priority at the top of the table.  
Spread. The YCCs are spread by priority in the table.  
4.3.1.2 SIU Interrupt Priority Register (SIPRR)  
The SIU interrupt priority register (SIPRR), shown in Figure 4-11, deÞnes the priority  
between IRQ1ÐIRQ6, PIT, and TMCNT.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
XS1P  
000  
XS2P  
001  
XS3P  
010  
XS4P  
011  
Ñ
0000  
R/W  
0x10C10  
Addr  
Bits  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
XS5P  
100  
XS6P  
101  
XS7P  
110  
XS8P  
111  
Ñ
0000  
R/W  
0x10C12  
Addr  
Figure 4-11. SIU Interrupt Priority Register (SIPRR)  
4-18  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part II. ConÞguration and Reset  
The SIPRR register bits are described in Table 4-5.  
Table 4-5. SIPRR Field Descriptions  
Bits  
Name  
Description  
0Ð3  
XS1PÐXSIU1 Priority order. DeÞnes which PIT/TMCNT/IRQs asserts its request in the XSIU1 priority  
position. The user should not program the same PIT/TMCNT/IRQs to more than one priority  
position (1Ð8). These bits can be changed dynamically.  
000 TMCNT asserts its request in the XSIU1 position.  
001 PIT asserts its request in the XSIU1 position.  
010 Reserved  
011 IRQ1 asserts its request in the XSIU1 position.  
100 IRQ2 asserts its request in the XSIU1 position.  
101 IRQ3 asserts its request in the XSIU1 position.  
110 IRQ4 asserts its request in the XSIU1 position.  
111 IRQ5 asserts its request in the XSIU1 position.  
4Ð12 XS2PРXS8P Same as XS1P, but for XSIU2ÐXSIU8.  
13Ð15 Reserved, should be cleared.  
Ñ
4.3.1.3 CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L)  
The CPM high interrupt priority register (SCPRR_H), shown in Figure 4-12, deÞne  
priorities between the FCCs and MCCs.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
XC2P  
001  
R
5
6
7
8
9
10  
XC4P  
011  
11  
12  
Ñ
0
13  
14  
Ñ
15  
XC1P  
000  
XC3P  
010  
000  
R
R/W R/W R/W  
R/W  
21  
R
R/W  
R
R/W R/W R/W  
R
R/W R/W R/W  
Addr  
Bits  
0x10C14  
16  
17  
XC5P  
100  
18  
19  
20  
XC6P  
101  
R
22  
23  
XC7P  
110  
24  
25  
26  
XC8P  
111  
27  
28  
Ñ
0
29  
30  
Ñ
31  
Field  
Reset  
R/W  
000  
R
R/W R/W R/W  
R/W R/W R/W  
R
R/W R/W R/W  
R
R/W R/W R/W  
Addr  
0x10C16  
Figure 4-12. CPM High Interrupt Priority Register (SCPRR_H)  
MOTOROLA  
Chapter 4. System Interface Unit (SIU)  
4-19  
         
Part II. ConÞguration and Reset  
Table 4-6 describes SCPRR_H Þelds.  
Table 4-6. SCPRR_H Field Descriptions  
Bits  
Name  
Description  
0Ð2  
XC1PÐXCC1 Priority order. DeÞnes which FCC/MCC asserts its request in the XCC1 priority position.  
The user should not program the same FCC/MCC to more than one priority position (1Ð8).  
These bits can be changed dynamically.  
000 FCC1 asserts its request in the XCC1 position.  
001 FCC2 asserts its request in the XCC1 position.  
010 FCC3 asserts its request in the XCC1 position.  
011 XCC1 position not active.  
100 MCC1 asserts its request in the XCC1 position.  
101 MCC2 asserts its request in the XCC1 position.  
110 XCC1 position not active.  
111 XCC1 position not active.  
3Ð12  
XC2PÐXC8P Same as XC1P, but for XCC2ÐXCC8  
13Ð15  
Ñ
Reserved, should be cleared.  
The CPM low interrupt priority register (SCPRR_L), shown in Figure 4-13, deÞnes  
prioritization of SCCs.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
YC1P  
000  
YC2P  
001  
YC3P  
010  
YC4P  
011  
Ñ
0000  
R/W  
0x10C18  
Addr  
Bits  
16  
17  
YC5P  
100  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
YC6P  
101  
YC7P  
110  
YC8P  
111  
Ñ
0000  
R/W  
0x10C20  
Addr  
Figure 4-13. CPM Low Interrupt Priority Register (SCPRR_L)  
Table 4-7 describes SCPRR_L Þelds.  
Table 4-7. SCPRR_L Field Descriptions  
Bits  
Name  
Description  
0Ð2 YC1PÐYCC1 Priority order. DeÞnes which SCC asserts its request in the YCC1 priority position. Do not  
program the same SCC to multiple priority positions. This Þeld can be changed dynamically.  
000 SCC1 asserts its request in the YCC1 position.  
001 SCC2 asserts its request in the YCC1 position.  
010 SCC3 asserts its request in the YCC1 position.  
011 SCC4 asserts its request in the YCC1 position.  
1XX YCC1 position is not active.  
4-20  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part II. ConÞguration and Reset  
Table 4-7. SCPRR_L Field Descriptions (Continued)  
Bits  
3Ð11 YC2PÐYC8P Same as YC1P, but for YCC2ÐYCC8  
12Ð15 Reserved, should be cleared.  
Name  
Description  
Ñ
4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)  
Each bit in the interrupt pending registers (SIPNR_H and SIPNR_L), shown in Figure 4-14  
and Figure 4-15, corresponds to an interrupt source. When an interrupt is received, the  
interrupt controller sets the corresponding SIPNR bit.  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15  
Reset  
R/W  
Addr  
Bits  
UndeÞned (the user should write 1s to clear these bits before using)  
R/W  
0x10C08  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
Ñ
27  
28  
29  
30  
31  
Ñ
Field IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7  
TMCNT PIT  
1
1
1
Reset  
R/W  
UndeÞned (the user should write 1s to clear these bits before using)  
0
0
0
R/W  
Addr  
0x10C10  
1
These Þelds are zero after reset because their corresponding mask register bits are cleared (disabled).  
Figure 4-14. SIPNR_H Fields  
Figure 4-15 shows SIPNR_L Þelds.  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field FCC1 FCC2 FCC3  
Ñ
MCC1 MCC2  
Ñ
SCC1 SCC2 SCC3 SCC4  
1
Ñ
Reset  
R/W  
0000_0000_0000_0000  
R/W  
Addr  
0x10C0C  
Bits  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
Ñ
27  
28  
29  
30  
31  
Field I2C SPI RTT SMC1 SMC2 IDMA1 IDMA2 IDMA3 IDMA4 SDMA  
1
TIMER1 TIMER2 TIMER3 TIMER4 Ñ  
1
Reset  
0000_0000_0000_000  
0
R/W  
R/W  
Addr  
0x10C0E  
1
These Þelds are zero after reset because their corresponding mask register bits are cleared (disabled).  
Figure 4-15. SIPNR_L Fields  
MOTOROLA  
Chapter 4. System Interface Unit (SIU)  
4-21  
           
Part II. ConÞguration and Reset  
When a pending interrupt is handled, the user clears the corresponding SIPNR bit.  
However, if an event register exists, the unmasked event register bits should be cleared  
instead, causing the SIPNR bit to be cleared.  
SIPNR bits are cleared by writing ones to them. Because the user can only clear bits in this  
register, writing zeros to this register has no effect.  
Note that the SCC/FCC/MCC SIPNR bit positions are not changed according to their  
relative priority.  
4.3.1.5 SIU Interrupt Mask Registers (SIMR_H and SIMR_L)  
Each bit in the SIU interrupt mask register (SIMR) corresponds to a interrupt source. The  
user masks an interrupt by clearing and enables an interrupt by setting the corresponding  
SIMR bit. When a masked interrupt occurs, the corresponding SIPNR bit is set, regardless  
of the SIMR bit although no interrupt request is passed to the core.  
If an interrupt source requests interrupt service when the user clears its SIMR bit, the  
request stops. If the user sets the SIMR bit later, a previously pending interrupt request is  
processed by the core, according to its assigned priority. The SIMR can be read by the user  
at any time.  
Figure 4-16 shows the SIMR_H register.  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15  
Reset  
R/W  
0000_0000_0000_0000  
R/W  
Addr  
Bits  
0x10C1C  
16  
Ñ
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
Ñ
27  
28  
29  
30  
31  
Ñ
Field  
Reset  
R/W  
IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7  
TMCNT PIT  
0000_0000_0000_0000  
R/W  
Addr  
0x10C1E  
Figure 4-16. SIMR_H Register  
Figure 4-17 shows SIMR_L.  
4-22  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part II. ConÞguration and Reset  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field FCC1 FCC2 FCC3  
Ñ
MCC1 MCC2  
Ñ
SCC1 SCC2 SCC3 SCC4  
Ñ
Reset  
R/W  
0000_0000_0000_0000  
R/W  
Addr  
0x10C20  
Bits  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
Ñ
27  
28  
29  
30  
31  
Field I2C SPI RTT SMC1 SMC2 IDMA1 IDMA2 IDMA3 IDMA4 SDMA  
TIMER1 TIMER2 TIMER3 TIMER4 Ñ  
Reset  
R/W  
0000_0000_0000_0000  
R/W  
Addr  
0x10C22  
Figure 4-17. SIMR_L Register  
Note the following:  
¥
¥
SCC/MCC/FCC SIMR bit positions are not affected by their relative priority.  
The user can clear pending register bits that were set by multiple interrupt events  
only by clearing all unmasked events in the corresponding event register.  
¥
If an SIMR bit is masked at the same time that the corresponding SIPNR bit causes  
an interrupt request to the core, the error vector is issued (if no other interrupts  
pending). Thus, the user should always include an error vector routine, even if it  
contains only an rÞ instruction. The error vector cannot be masked.  
4.3.1.6 SIU Interrupt Vector Register (SIVEC)  
The SIU interrupt vector register (SIVEC), shown in Figure 4-18, contains an 8-bit code  
representing the unmasked interrupt source of the highest priority level.  
Bit  
Field  
Reset  
R/W  
Addr  
Bit  
0
1
2
3
4
5
6
0
7
0
8
0
9
0
10  
0
11  
0
12  
0
13  
0
14  
0
15  
0
Interrupt Code  
0000_0000_0000_0000  
R
0x10C04  
16  
0
17  
0
18  
0
19  
0
20  
0
21  
0
22  
0
23  
0
24  
0
25  
0
26  
0
27  
0
28  
0
29  
0
30  
0
31  
0
Field  
Reset  
R/W  
Addr  
0000_0000_0000_0000  
R
0x10C06  
Figure 4-18. SIU Interrupt Vector Register (SIVEC)  
4-23  
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MOTOROLA  
         
Part II. ConÞguration and Reset  
The SIVEC can be read as either a byte, half word, or a word. When read as a byte, a branch  
table can be used in which each entry contains one instruction (branch). When read as a half  
word, each entry can contain a full routine of up to 256 instructions. The interrupt code is  
deÞned such that its two lsbs are zeroes, allowing indexing into the table, as shown in  
Figure 4-19.  
INTR: ¥ ¥ ¥  
Save state  
R3 <- @ SIVEC  
INTR: ¥ ¥ ¥  
Save state  
R3 <- @ SIVEC  
R4 <-- Base of branch table  
R4 <-- Base of branch table  
¥ ¥ ¥  
¥ ¥ ¥  
lbz  
add  
RX, R3 (0)  
RX, RX, R4  
# load as byte  
lhz  
add  
RX, R3 (0)  
RX, RX, R4  
# load as half  
mtspr CTR, RX  
bctr  
mtspr CTR, RX  
bctr  
1st Instruction of Routine1  
BASE  
b
b
b
b
Routine1  
BASE  
•
BASE + 4  
BASE + 8  
BASE + C  
BASE +10  
BASE + n  
Routine2  
BASE + 400  
BASE + 800  
BASE + C00  
BASE +1000  
BASE + n  
1st Instruction of Routine2  
•
Routine3  
1st Instruction of Routine3  
•
Routine4  
1st Instruction of Routine4  
•
•
•
•
•
•
•
Figure 4-19. Interrupt Table Handling Example  
Note that the MPC8260 differs from previous MPC8xx implementations in that when an  
interrupt request occurs, SIVEC can be read. If there are multiple interrupt sources, SIVEC  
latches the highest priority interrupt. Note that the value of SIVEC cannot change while it  
is being read.  
4.3.1.7 SIU External Interrupt Control Register (SIEXR)  
Each deÞned bit in the SIU external interrupt control register (SIEXR), shown in  
Figure 4-20, determines whether the corresponding port C line asserts an interrupt request  
upon either a high-to-low change or any change on the pin. External interrupts can come  
from port C (PC[0-15]).  
4-24  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part II. ConÞguration and Reset  
Bits  
Field  
Reset  
R/W  
Addr  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
EDPC0 EDPC1 EDPC2 EDPC3 EDPC4 EDPC5 EDPC6 EDPC7 EDPC8 EDPC9 EDPC10 EDPC11 EDPC12 EDPC13 EDPC14 EDPC15  
0000_0000_0000_0000  
R/W  
0x10C24  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field EDI0 EDI1 EDI2 EDI3 EDI4 EDI5 EDI6 EDI7  
Ñ
R
Reset  
R/W  
0000_0000_0000_0000  
R/W  
Addr  
0x10C26  
Figure 4-20. SIU External Interrupt Control Register (SIEXR)  
Table 4-8 describes SIEXR Þelds.  
Table 4-8. SIEXR Field Descriptions  
Bits  
Name  
Description  
0Ð15 EDPCx Edge detect mode for port Cx. The corresponding port C line (PCx) asserts an interrupt request  
according to the following:  
0
1
Any change on PCx generates an interrupt request.  
High-to-low change on PCx generates an interrupt request.  
16Ð23  
EDIx  
Edge detect mode for IRQx. The corresponding IRQ line (IRQx) asserts an interrupt request  
according to the following:  
0
1
Low assertion on IRQx generates an interrupt request.  
High-to-low change on IRQx generates an interrupt request.  
4.3.2 System ConÞguration and Protection Registers  
The system conÞguration and protection registers are described in the following sections.  
4.3.2.1 Bus ConÞguration Register (BCR)  
The bus conÞguration register (BCR), shown in Figure 4-21, contains conÞguration bits for  
various features and wait states on the 60x bus.  
4-25  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
             
Part II. ConÞguration and Reset  
Bits  
0
1
2
3
4
5
6
7
8
9
10 11  
12  
13  
14  
15  
Field EBM  
Reset  
APD  
L2C  
L2D  
PLDP EAV Ñ  
ETM LETM EPAR LEPAR  
Depends on reset conÞguration sequence. See Section 5.4.1, ÒHard Reset ConÞguration Word.Ó  
R/W  
R/W  
Bits  
Field  
Reset  
R/W  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25 26 27  
ISPS  
28  
29  
30  
31  
NPQM  
Ñ
EXDD  
Ñ
Ñ
Depends on reset conÞguration sequence. See Section 5.4.1, ÒHard Reset ConÞguration Word.Ó  
R/W  
Addr  
0x10024  
Figure 4-21. Bus Configuration Register (BCR)  
Table 4-9 describes BCR Þelds.  
Table 4-9. BCR Field Descriptions  
Bits  
Name  
Description  
0
EBM External bus mode.  
0 Single MPC8260 bus mode is assumed  
1 60x-compatible bus mode. For more information refer to Section 8.2, ÒBus ConÞguration.Ó  
1Ð3  
APD Address phase delay. SpeciÞes the minimum number of address tenure wait states for address  
operations initiated by a 60x bus master. BCR[APD] speciÞes the minimum number of address  
tenure wait states for address operations initiated by 60x-bus devices. APD indicates how many  
cycles the MPC8260 should wait for ARTRY, but because it is assumed that ARTRY can be  
asserted (by other masters) only on cachable address spaces, APD is considered only on  
transactions that hit one of the 60x-assigned memory controller banks and have the GBL signal  
asserted during address phase.  
4
L2C Secondary cache controller. See Chapter 11, ÒSecondary (L2) Cache Support.Ó  
0 No secondary cache controller is assumed.  
1 An external secondary cache controller is assumed.  
5Ð7  
8
L2D L2 cache hit delay. Controls the number of clock cycles from the assertion of TS until HIT is valid.  
PLDP Pipeline maximum depth. See Section 8.4.5, ÒPipeline Control.Ó  
1 The pipeline maximum depth is zero.  
0 The pipeline maximum depth is one.  
9
EAV Enable address visibility. Normally, when the MPC8260 is in single-MPC8260 bus mode, the bank  
select signalsfor SDRAM accesses are multiplexed on the 60x bus address lines. So, for SDRAM  
accesses, the internal address is not visible for debug purposes. However the bank select signals  
can also be driven on dedicated pins (see SIUMCR[APPC]). In this case EAV can be used to force  
address visibility.  
0 Bank select signals are driven on 60x bus address lines. There is no full address visibility.  
1 Bank select signals are not driven on address bus. During READ and WRITE commands to  
SDRAM devices, the full address is driven on 60x bus address lines.  
10Ð11  
12  
Ñ
Reserved, should be cleared.  
ETM Compatibility mode enable. See Section 8.4.3.8, ÒExtended Transfer Mode.Ó  
0 Strict 60x bus mode. Extended transfer mode is disabled.  
1 Extended transfer mode is enabled.  
4-26  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part II. ConÞguration and Reset  
Table 4-9. BCR Field Descriptions (Continued)  
Bits  
Name  
Description  
13  
LETM Local bus compatibility mode enable. See Section 8.4.3.8, ÒExtended Transfer Mode.Ó  
1 Extended transfer mode is enable on the local bus.  
0 Extended transfer mode is disabled in the local bus.  
Note that if the local bus memory controller is conÞgured to work with read-modify-write parity,  
LETM must be cleared.  
14  
15  
EPAR Even parity. Determines odd or even parity, Writing the memory with EPAR = 1 and reading the  
memory with EPAR = 0 generates parity errors for testing.  
LEPAR Local bus even parity. SpeciÞes odd or even parity in the local bus. Writing the memory with  
LEPAR = 1 and reading the memory with LEPAR = 0 generates parity errors for testing.  
16Ð18 NPQM Non PowerQUICC II master. IdentiÞes the type of bus masters which are connected to the  
arbitration lines when the MPC8260 is in internal arbiter mode. Possible types are PowerQUICC II  
master and non-PowerQUICC II master. This Þeld is related to the data pipelining bits (BRx[DR]) in  
the memory controller. Because an external bus master that is not a MPC8260 cannot use the data  
pipelining feature, the MPC8260, which controls the memory, needs to know when a non-  
PowerQUICC II master is accessing the memory and handle the transaction differently.  
NPQM[0] designates the type of master connected to the set of pins BR, BG, and DBG.  
NPQM[1] designates the type of master connected to the set of pins EXT_BR2, EXT_BG2, and  
EXT_DBG2.  
NPQM[2] designates the type of master which is connected to the set of pins EXT_BR3, EXT_BG3  
and EXT_DBG3  
0 The bus master connected to the arbitration lines is a MPC8260.  
1 The bus master connected to the arbitration lines is not a MPC8260.  
16Ð20  
21  
Ñ
Reserved, should be cleared.  
EXDD External master delay disable. Generally, the MPC8260 adds one clock cycle delay for each  
external master access to a region controlled by the memory controller. This occurs because the  
external master drives the address on the external pins (compared to internal master, like  
MPC8260Õs DMA, which drives the address on an internal bus in the chip).Thus, it is assumed that  
an additional cycle is needed for the memory controllers banks to complete the address match.  
However in some cases (when the bus is operated in low frequency), this extra cycle is not needed.  
The user can disable the extra cycle by setting EXDD.  
0 The memory controller inserts one wait state between the assertion of TS and the assertion of  
CS when external master accesses an address space controlled by the memory controller.  
1 The memory controller asserts CS on the cycle following the assertion of TS by external master  
accessing an address space controlled by the memory controller.  
22Ð26  
27  
Ñ
Reserved, should be cleared.  
ISPS Internal space port size. DeÞnes the port size of MPC8260Õs internal space region as seen to  
external masters. Setting ISPS enables a 32-bit master to access MPC8260 internal space.  
0 MPC8260 acts as a 64-bit slave to external masters accesses to its internal space.  
1 MPC8260 acts as a 32-bit slave to external masters accesses to its internal space.  
28Ð31  
Ñ
Reserved, should be cleared.  
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MPC8260 PowerQUICC II UserÕs Manual  
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Part II. ConÞguration and Reset  
4.3.2.2 60x Bus Arbiter ConÞguration Register (PPC_ACR)  
The 60x bus arbiter conÞguration register (PPC_ACR), shown in Figure 4-22, deÞnes the  
arbiter modes and parked master on the 60x bus.  
Bit  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
Ñ
DBGD  
EARB  
PRKM  
Depends on reset conÞguration sequence. See Section 5.4.1, ÒHard Reset ConÞguration Word.Ó  
R/W  
Addr  
0x10028  
Figure 4-22. PPC_ACR  
Table 4-10 describes PPC_ACR Þelds.  
Table 4-10. PPC_ACR Field Descriptions  
Bits  
Name  
Description  
0Ð1  
2
Ñ
Reserved, should be cleared.  
DBGD Data bus grant delay. SpeciÞes the minimum number of data tenure wait states for 60x bus master-  
initiated data operations. This is the minimum delay between TS and DBG.  
0 DBG is asserted with TS if the data bus is free.  
1 DBG is asserted one cycle after TS if the data bus is not busy.  
See Section 8.5.1, ÒData Bus Arbitration.Ó  
3
EARB External arbitration.  
0 Internal arbitration is performed. See Section 8.3.1, ÒArbitration Phase.Ó  
1 External arbitration is assumed.  
4Ð7  
PRKM Parking master.  
0000 CPM high request level  
0001 CPM middle request level  
0010 CPM low request level  
0011 Reserved  
0100 Reserved  
0101 Reserved  
0110 Internal core  
0111 External master 1  
1000 External master 2  
1001 External master 3  
Values 1010Ð1111 are reserved.  
4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL)  
The 60x bus arbitration-level registers, shown in Figure 4-23 and Figure 4-24, deÞne  
arbitration priority of MPC8260 bus masters. Priority Þeld 0 has highest-priority. For  
information about MPC8260 bus master indexes, see the description of PPC_ACR[PRKM]  
in Table 4-10.  
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Part II. ConÞguration and Reset  
Bit  
Field  
Reset  
R/W  
Addr  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Priority Field 0  
0000  
Priority Field 1  
0001  
Priority Field 2  
0010  
Priority Field 3  
0011  
R/W  
0x1002C  
23 24  
16  
17  
18  
19  
20  
21  
22  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
Addr  
Priority Field 4  
0100  
Priority Field 5  
0101  
Priority Field 6  
0110  
Priority Field 7  
0111  
R/W  
0x1002E  
Figure 4-23. PPC_ALRH  
PPC_ALRL, shown in Figure 4-24, deÞnes arbitration priority of 60x bus masters 8Ð15.  
Priority Þeld 0 is the highest-priority arbitration level. For information about the MPC8260  
bus master indexes, see the description of PPC_ACR[PRKM] in Table 4-10.  
Bit  
Field  
Reset  
R/W  
Addr  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Priority Field 8  
1000  
Priority Field 9  
1001  
Priority Field 10  
1010  
Priority Field 11  
1011  
R/W  
0x10030  
23 24  
16  
17  
18  
19  
20  
21  
22  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
Addr  
Priority Field 12  
1100  
Priority Field 13  
1101  
Priority Field 14  
1110  
Priority Field 15  
1111  
R/W  
0x10032  
Figure 4-24. PPC_AALRL  
4.3.2.4 Local Bus Arbiter ConÞguration Register (LCL_ACR)  
The local bus arbiter conÞguration register (LCL_ACR), shown in Figure 4-25, deÞnes the  
arbiter modes and the parked master on the local bus.  
Bit  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
Ñ
DBGD  
Ñ
PRKM  
0000_0010  
R/W  
Addr  
0x10034  
Figure 4-25. LCL_ACR  
4-29  
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Part II. ConÞguration and Reset  
Table 4-11 describes LCL_ACR register bits.  
Table 4-11. LCL_ACR Field Descriptions  
Bits Name  
Description  
0Ð1  
2
Ñ
Reserved, should be cleared.  
DBGD Data bus grant delay. SpeciÞes the minimum number of data tenure wait states for PowerPC  
master-initiated data operations. This is the minimum delay between TS and DBG.  
0 DBG is asserted with TS if the data bus is free.  
1 DBG is asserted one cycle after TS if the data bus is not busy.  
See Section 8.5.1, ÒData Bus Arbitration.Ó  
3
Ñ
Reserved, should be cleared.  
4Ð7 PRKM Parking master. DeÞnes the parked master.  
0000 CPM high request level  
0001 CPM middle request level  
0010 CPM low request level (default)  
0011 Host bridge  
Values 0100Ð1111 are reserved.  
4.3.2.5 Local Bus Arbitration Level Registers (LCL_ALRH and  
LCL_ACRL)  
The local bus arbitration level registers (LCL_ALRH and LCL_ALRL), shown in  
Figure 4-26 and Figure 4-27, deÞnes arbitration priority for MPC8260 local bus masters 0Ð  
7. Priority Þeld 0 has highest-priority. For information about the MPC8260 local bus master  
indexes see LCL_ACR[PRKM] in Table 4-11.  
Bit  
Field  
Reset  
R/W  
Addr  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Priority Field 0  
0000  
Priority Field 1  
0001  
Priority Field 2  
0010  
Priority Field 3  
0011  
R/W  
0x10038  
23 24  
16  
17  
18  
19  
20  
21  
22  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
Addr  
Priority Field 4  
0100  
Priority Field 5  
0101  
Priority Field 6  
0110  
Priority Field 7  
0111  
R/W  
0x10040  
Figure 4-26. LCL_ALRH  
LCL_ALRL, shown in Figure 4-27, deÞnes arbitration priority of MPC8260 local bus  
masters 8Ð15.  
4-30  
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Part II. ConÞguration and Reset  
Bit  
Field  
Reset  
R/W  
Addr  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Priority Field 8  
1000  
Priority Field 9  
1001  
Priority Field 10  
1010  
Priority Field 11  
1011  
R/W  
0x1003C  
23 24  
16  
17  
18  
19  
20  
21  
22  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
Addr  
Priority Field 12  
1100  
Priority Field 13  
1101  
Priority Field 14  
1110  
Priority Field 15  
1111  
R/W  
0x1003E  
Figure 4-27. LCL_ALRL  
4.3.2.6 SIU Module ConÞguration Register (SIUMCR)  
The SIU module conÞguration register (SIUMCR), shown in Figure 4-28, contains bits that  
conÞgure various features in the SIU module.  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field BBD  
Reset  
ESE  
PBSE CDIS  
DPPC  
L2CPC  
LBPC  
APPC  
CS10PC  
BCTLC  
0000_0000_0000_0000  
R/W  
Depends on reset conÞguration sequence. See Section 5.4.1, ÒHard Reset ConÞguration Word.Ó  
0x10000  
Addr  
Bits  
Field  
Reset  
R/W  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
Ñ
26  
27  
28  
29  
30  
31  
MMR  
LPBSE  
0000_0000_0000_0000  
Depends on reset conÞguration sequence. See Section 5.4.1, ÒHard Reset ConÞguration Word.Ó  
0x10002  
Addr  
Figure 4-28. SIU Model Configuration Register (SIUMCR)  
4-31  
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Part II. ConÞguration and Reset  
Table 4-12 describes SIUMCR Þelds.  
Table 4-12. SIUMCR Register Field Descriptions  
Bits  
Name  
BBD  
Description  
0
1
2
3
Bus busy disable.  
0 ABB/IRQ2 pin is ABB, DBB/IRQ3 pin is DBB  
1 ABB/IRQ2 pin is IRQ2, DBB/IRQ3 pin is IRQ3  
ESE  
External snoop enable. ConÞgures GBL/IRQ1  
0 External snooping disabled. (GBL/IRQ1 pin is IRQ1.)  
1 External snooping enabled. (GBL/IRQ1 pin is GBL.)  
PBSE  
CDIS  
DPPC  
Parity byte select enable.  
0 Parity byte select is disabled. GPL4 output of UPM is available for memory control.  
1 Parity byte select is enabled. GPL4 pin is used as parity byte select output from the MPC8260.  
Core disable.  
0 The MPC8260 core is enabled.  
1 The MPC8260 core is disabled. MPC8260 functions as a slave device.  
4Ð5  
Data parity pins conÞguration. Note that the additional arbitration lines (EXT_BR2, EXT_BG2,  
EXT_DBG2, EXT_BR3, EXT_BG3, and EXT_DBG3) are operational only when ACR[EARB] = 0.  
Setting EARB (to choose external arbiter) combined with programming DPPC to 11 deactivates  
these lines.  
DPPC  
Pin  
00  
01  
10  
11  
DP(0)/RSRV  
DP(1)/IRQ1  
Ñ
DP(0)  
DP(1)  
DP(2)  
DP(3)  
DP(4)  
DP(5)  
DP(6)  
DP(7)  
RSRV  
IRQ1  
EXT_BR2  
EXT_BG2  
EXT_DBG2  
EXT_BR3  
EXT_BG3  
EXT_DBG3  
IRQ6  
IRQ1  
IRQ2  
IRQ3  
IRQ4  
IRQ5  
IRQ6  
IRQ7  
DP(2)/TLBISYNC/IRQ2  
DP(3)/IRQ3  
TLBISYNC  
CKSTP_OUT  
CORE_SRESET  
TBEN  
DP(4)/IRQ4  
DP(5)/TBEN/IRQ5  
DP(6)/CSE(0)/IRQ6  
DP(7)/CSE(1)/IRQ7  
CSE(0)  
CSE(1)  
IRQ7  
6Ð7  
L2CPC L2 cache pins conÞguration.  
Multiplexing  
Pin  
L2CPC = 00 L2CPC = 01  
L2CPC = 10  
CI/BADDR(29)/IRQ2  
WT/BADDR(30)/IRQ3  
L2_HIT/IRQ4  
CI  
IRQ2  
IRQ3  
IRQ4  
IRQ5  
BADDR(29)  
BADDR(30)  
Ñ
WT  
L2_HIT  
CPU_BG  
CPU_BG/BADDR(31)/IRQ5  
BADDR(31)  
8Ð9  
LBPC  
Local bus pins conÞguration.  
00 Local bus pins function as local bus  
01 Reserved  
10 Local bus pins function as core pins  
11 Reserved  
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MOTOROLA  
 
Part II. ConÞguration and Reset  
Table 4-12. SIUMCR Register Field Descriptions (Continued)  
Bits  
Name  
Description  
10Ð11 APPC  
Address parity pins conÞguration. Note that during power on reset the MODCK pins are used for  
PLL conÞguration. The pin multiplexing indicated in the table applies only to normal operation.  
Selection between IRQ7 and INT_OUT is according to CPU state. If the core is disabled, the pin is  
INT_OUT; otherwise it is IRQ7.  
APPC  
Pin  
00  
01  
10  
11  
MODCK1/AP(1)/TC(0)/  
BNKSEL(0)  
TC(0)  
AP(1)  
BNKSEL(0)  
Ñ
MODCK2/AP(2)/TC(1)/  
BNKSEL(1)  
TC(1)  
TC(2)  
AP(2)  
AP(3)  
APE  
BNKSEL(1)  
BNKSEL(2)  
IRQ7/INT_OUT  
CS11  
MODCK3/AP(3)/TC(2)/  
BNKSEL(2)  
IRQ7/INT_OUT/APE  
IRQ7/  
INT_OUT  
IRQ7/  
INT_OUT  
CS11/AP(0)  
CS11  
AP(0)  
Ñ
12Ð13 CS10PC Chip select 10-pin conÞguration.  
CS10PC  
Pin  
00  
01  
10  
CS10/BCTL1/DBG_DIS  
CS10  
BCTL1  
DBG_DIS  
14Ð15 BCTLC Buffer control conÞguration.  
00 BCTL0 is used as W/R control. BCTL1 is used as OE control.  
01 BCTL0 is used as W/R control. BCTL1 is used as OE control.  
10 BCTL0 is used as WE control. BCTL1 is used as RE control.  
11 Reserved  
16-17 MMR  
Mask masters requests. In some systems, several bus masters are active during normal operation;  
only one should be active during boot sequence. The active master, which is the boot device,  
initializes system memories and devices and enables all other masters. MMR facilitates such a  
boot scheme by masking the selected masterÕs bus requests. MMR can be conÞgured through the  
hard reset conÞguration sequence see Section 5.4.2, ÒHard Reset ConÞguration Examples.Ó  
Typically system conÞguration identiÞes only one master is the boot device, which initializes the  
system and then enables all other devices by writing 00 to MMR.  
Note: It is not recommended to mask the request of a master which is deÞned as the parked  
master in the arbiter, since this cannot prevent this master from getting a bus grant.  
00 No masking on bus request lines.  
01 Reserved  
10 The MPC8260Õs internal core bus request masked and external bus requests two and three  
masked (boot master connected to external bus request 1).  
11 All external bus requests masked (boot master is the MPC8260Õs internal core).  
18  
LPBSE Local bus parity byte select enable.  
0
1
Parity byte select is disabled. LGPL4 output of UPM is available for memory control.  
Parity byte select is enabled. LGPL4 pin is used as local bus parity byte select output from the  
MPC8260.  
19Ð31  
Ñ
Reserved, should be cleared.  
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Part II. ConÞguration and Reset  
4.3.2.7 Internal Memory Map Register (IMMR)  
The internal memory map register (IMMR), shown in Figure 4-29, contains identiÞcation  
of a speciÞc device as well as the base address for the internal memory map. Software can  
deduce availability and location of any on-chip system resources from the values in IMMR.  
PARTNUM and MASKNUM are mask programmed and cannot be changed for any  
particular device.  
Bit  
Field  
Reset  
R/W  
Addr  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Ñ
ISB  
Depends on reset conÞguration sequence. See Section 5.4.1, ÒHard Reset ConÞguration Word.Ó  
R/W  
0x101A8  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
Addr  
PARTNUM  
MASKNUM  
Ñ
R
0x101AA  
Figure 4-29. Internal Memory Map Register (IMMR)  
Table 4-13 describes IMMR Þelds.  
Table 4-13. IMMR Field Descriptions  
Bits  
Name  
Description  
0Ð14  
ISB  
Internal space base. DeÞnes the base address of the internal memory space. The value of ISB  
be conÞgured at reset to one of 32 addresses; it can then be changed to any value by the  
software. The default is 0, which maps to address 0x0000_0000.  
ISB deÞnes the 15 msbs of the memory map register base address. IMMR itself is mapped in  
the internal memory space region. As soon as the ISB is written with a new base address, the  
IMMR base address is relocated according to the ISB. ISB can be conÞgured to one of 32  
possible addresses at reset to enable the conÞguration of multiple-MPC8260 systems.  
The number of programmable bits in this Þeld, and hence the resolution of the location of  
internal space, depends on the internal memory space of a speciÞc implementation. In the  
MPC8260, all 15 bits can be programmed. See Chapter 3, ÒMemory Map,Ó for details on the  
deviceÕs internal memory map and to Chapter 5, ÒReset,Ó for the available, default initial values.  
15  
Ñ
Reserved, should be cleared.  
16Ð23 PARTNUM Part number. This read-only Þeld is mask-programmed with a code corresponding to the part  
number of the part on which the SIU is located. It is intended to help factory test and user code  
which is sensitive to part changes. This changes when the part number changes. For example,  
it would change if any new module is added or if the size of any memory module is changed. It  
would not change if the part is changed to Þx a bug in an existing module.The MPC8260 has an  
ID of 0x00.  
24Ð31 MASKNUM Mask number. This read-only Þeld is mask-programmed with a code corresponding to the mask  
number of the part on which the SIU is located. It is intended to help factory test and user code  
which is sensitive to part changes. It is programmed in a commonly changed layer and should  
be changed for all mask set changes. The MPC8260 (Rev 0) has an ID of 0x00.  
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Part II. ConÞguration and Reset  
4.3.2.8 System Protection Control Register (SYPCR)  
The system protection control register, shown in Figure 4-30, controls the system monitors,  
software watchdog period, and bus monitor timing. SYPCR can be read at any time but can  
be written only once after system reset.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
SWTC  
1111_1111_1111_1111  
R/W  
Addr  
Bits  
0x10004  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
Ñ
28  
29  
30  
31  
Field  
Reset  
R/W  
BMT  
1111_1111  
PBME LBME  
SWE SWRI SWP  
0
0
00_0  
1
1
1
R/W  
0x10006  
Addr  
Figure 4-30. System Protection Control Register (SYPCCR)  
Table 4-14 describes SYPCR Þelds.  
Table 4-14. SYPCR Field Descriptions  
Bits  
Name  
Description  
0Ð15 SWTC Software watchdog timer count. Contains the count value for the software watchdog timer.  
16Ð23  
BMT Bus monitor timing. DeÞnes the time-out period for the bus monitor, the granularity of this Þeld is 8  
bus clocks. (BMT = 0xFF is translated to 0x7f8 clock cycles). BMT is used both in the 60x and local  
bus monitors.  
Note that the value 0 in invalid; an error is generated for each bus transaction.  
24  
25  
PBME 60x bus monitor enable.  
0 60x bus monitor is disabled.  
1 The 60x bus monitor is enabled.  
LBME Local bus monitor enable.  
0 Local bus monitor is disabled.  
1 The local bus monitor is enabled.  
26Ð29  
29  
Ñ
Reserved, should be cleared.  
SWE Software watchdog enable. Enables the operation of the software watchdog timer. It should be  
cleared by software after a system reset to disable the software watchdog timer.  
30  
SWRI Software watchdog reset/interrupt select.  
0 Software watchdog timer and bus monitor time-out causes a machine check interrupt to the core.  
1 Software watchdog timer and bus monitor time-out causes a soft reset (this is the default value  
after soft reset).  
31  
SWP Software watchdog prescale. Controls the divide-by-2,048 software watchdog timer prescaler.  
0 The software watchdog timer is not prescaled.  
1 The software watchdog timer clock is prescaled.  
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Part II. ConÞguration and Reset  
4.3.2.9 Software Service Register (SWSR)  
The software service register (SWSR) is the location to which the software watchdog timer  
servicing sequence is written. To prevent software watchdog timer time-out, the user should  
write 0x556C followed by 0xAA39 to this register, which resides at 0x1000E. SWSR can  
be written at any time, but returns all zeros when read.  
4.3.2.10 60x Bus Transfer Error Status and Control Register 1  
(TESCR1)  
The 60x bus transfer error status and control register 1 (TESCR1) is shown in Figure 4-31.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
Ñ
11  
12  
13  
TT  
14  
15  
BM ISBE PAR ECC2 ECC1 WP EXT  
TC  
0000_0000_0000_0000  
R/W  
Addr  
Bits  
0x10040  
16  
Ñ
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
DMD  
Ñ
ECNT  
0000_0000_0000_0000  
R/W  
Addr  
0x10042  
Figure 4-31. The 60x Bus Transfer Error Status and Control Register 1 (TESCR1)  
Table 4-15 describes TESCR1 Þelds.  
Table 4-15. TESCR1 Field Descriptions  
Bits Name  
Description  
0
1
BM 60x bus monitor time-out. Set when TEA is asserted due to the 60x bus monitor time-out.  
ISBE Internal space bus error. Indicates that TEA was asserted due to error on a transaction to MPC8260Õs  
internal memory space. TESCR2[REGS, DPR] indicate which of MPC8260Õs internal slaves caused  
the error.  
2
PAR 60x bus parity error. Indicates that TEA was asserted due to parity error on the 60x bus. TESCR2[PB]  
indicates which byte lane caused the error; TESCR2[BNK] indicates which memory controller bank  
was accessed.  
3
4
ECC2 Double ECC error. Indicates that TEA was asserted due to double ECC error on the 60x bus.  
TESCR2[BNK] indicates which memory controller bank was accessed.  
ECC1 Single ECC error. Indicates that TEA was asserted due to single bit ECC error on the 60x bus.  
TESCR2[BNK] indicates which memory controller bank was accessed. Single-bit errors are usually  
Þxed by the ECC logic. However, if the ECC counter (ECNT) has reached its maximum value, all  
single-bit errors cause the assertion of TEA.  
5
WP Write protect error. Indicates that a write was attempted to a 60x bus memory region that was deÞned  
as read-only in the memory controller. Note that this alone does not cause TEA assertion. Usually, in  
this case, the bus monitor will time-out.  
4-36  
MPC8260 PowerQUICC II UserÕs Manual  
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Table 4-15. TESCR1 Field Descriptions (Continued)  
Bits Name  
Description  
6
EXT External error. Indicates that TEA was asserted by an external bus slave.  
7Ð9  
TC Transfer code. Indicates the transfer code of the 60x bus transaction that caused the TEA. See  
Section 8.4.3.2, ÒTransfer Code Signals TC[0Ð2],Ó for a description of the various transfer codes.  
10  
Ñ
Reserved, should be cleared.  
11Ð15  
TT Transfer type. These bits indicates the transfer type of the 60x bus transaction that caused the TEA.  
See Section 8.4.3.1, ÒTransfer Type Signal (TT[0Ð4]) Encoding,Ó for a description of the various  
transfer types.  
16  
17  
Ñ
Reserved, should be cleared.  
DMD Data errors disable.  
0 Errors are enabled.  
1 All data errors (parity and single and double ECC errors) on the 60x bus are disabled.  
18Ð23  
Ñ
Reserved, should be cleared.  
24Ð31 ECNT Single ECC error counter.Indicates the number of single ECC errors that occurred in the system.  
When the counter reaches its maximum value (255), TEA is asserted for all single ECC errors. This  
feature gives the system the ability to withstand a few random errors yet react to a catastrophic failure.  
The user can set a lower threshold to the number of tolerated single ECC errors by writing some value  
to ECNT. The counter starts from this value instead of zero.  
4.3.2.11 60x Bus Transfer Error Status and Control Register 2  
(TESCR2)  
The 60x bus transfer error status and control register 2 (TESCR2) is shown in Figure 4-32.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Ñ
REGS DPR  
Ñ
LCL  
PB  
0000_0000_0000_0000  
R/W  
Addr  
Bits  
0x10044  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
BNK  
Ñ
0000_0000_0000_0000  
R/W  
Addr  
0x10046  
Figure 4-32. 60x Bus Transfer Error Status and Control Register 2 (TESCR2)  
4-37  
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Part II. ConÞguration and Reset  
The TESCR2 register is described in Table 4-16.  
Table 4-16. TESCR2 Field Descriptions  
Bits  
Name  
Description  
0
1
Ñ
Reserved, should be cleared.  
REGS Internal registers error. An error occurred in a transaction to the MPC8260Õs internal registers.  
DPR Dual port ram error. An error occurred in a transaction to the MPC8260Õs dual-port RAM.  
2
3Ð6  
7
Ñ
Reserved, should be cleared.  
LCL Local bus bridge error. An error occurred in a transaction to the MPC8260Õs 60x bus to local bus  
bridge.  
8Ð15  
PB  
Parity error on byte.There are eight parity error status bits, one per 8-bit lane. A bit is set for the byte  
that had a parity error.  
16Ð27  
BNK Memory controller bank. There are twelve error status bits, one per memory controller bank. A bit is  
set for the 60x bus memory controller bank that had an error. Note that this Þeld is invalid if the error  
was not caused by ECC or parity checks.  
28Ð31  
Ñ
Reserved, should be cleared.  
4.3.2.12 Local Bus Transfer Error Status and Control Register 1  
(L_TESCR1)  
The local bus transfer error status and control register 1 (L_TESCR1) is shown in  
Figure 4-33.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
Ñ
11  
12  
13  
TT  
14  
15  
BM  
Ñ
PAR  
Ñ
WP  
Ñ
TC  
0000_0000_0000_0000  
R/W  
Addr  
Bits  
0x10048  
16  
Ñ
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
DMD  
Ñ
0000_0000_0000_0000  
R/W  
Addr  
0x1004A  
Figure 4-33. Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)  
4-38  
MPC8260 PowerQUICC II UserÕs Manual  
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Part II. ConÞguration and Reset  
The L_TESCR1 register bits are described in Table 4-17.  
Table 4-17. L_TESCR1 Field Descriptions  
Bits  
Name  
Description  
0
1
2
BM  
Ñ
Bus monitor time-out. Indicates that TEA was asserted due to the local bus monitor time-out.  
Reserved, should be cleared.  
PAR Parity error. Indicates that TEA was asserted due to parity error on the local bus. L_TESCR2[PB]  
indicates the byte lane that caused the error and L_TESCR2[BNK] indicates which memory  
controller bank was accessed.  
3Ð4  
5
Ñ
Reserved, should be cleared.  
WP  
Write protect error. Indicates that a write was attempted to a local bus memory region that was  
deÞned as read-only in the memory controller. Note that this alone does not cause TEA assertion.  
Usually, in this case, the bus monitor will time-out.  
6
Ñ
Reserved, should be cleared.  
7Ð9  
TC  
Transfer code. These bits indicates the transfer code of the local bus transaction that caused the  
TEA. Section 8.4.3.2, ÒTransfer Code Signals TC[0Ð2], describes transfer codes.  
10  
Ñ
Reserved, should be cleared.  
11Ð15  
TT  
Transfer type. Indicates the transfer type of the local bus transaction that caused the TEA.  
Section 8.4.3.1, ÒTransfer Type Signal (TT[0Ð4]) Encoding,Ó describes the various transfer types.  
16  
17  
Ñ
DMD  
Ñ
Reserved, should be cleared.  
Data errors disable. Setting this bit disables parity errors on the local bus.  
Reserved, should be cleared.  
18Ð31  
4.3.2.13 Local Bus Transfer Error Status and Control Register 2  
(L_TESCR2)  
The local bus transfer error status and control register 2 (L_TESCR2) is shown in  
Figure 4-34.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Ñ
PB  
0000_0000_0000_0000  
R/W  
Addr  
Bits  
0x1004C  
16  
17  
18  
19  
20  
21  
22  
BNK  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
Ñ
0000_0000_0000_0000  
R/W  
Addr  
0x1004E  
Figure 4-34. Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)  
4-39  
MPC8260 PowerQUICC II UserÕs Manual  
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Part II. ConÞguration and Reset  
Table 4-18 describes L_TESCR2 Þelds.  
Table 4-18. L_TESCR2 Field Descriptions  
Bits  
Name  
Description  
0Ð11  
Ñ
Reserved, should be cleared.  
12Ð15  
PB  
Parity error on byte.There are four parity error status bits, one per 8-bit lane. A bit is set for the byte  
that had a parity error.  
16Ð27  
28Ð31  
BNK Memory controller bank.There are twelve error status bits, one per memory controller bank. A bit is  
set for the local bus memory controller bank that had an error. Note that BNK is invalid if the error  
was not caused by ECC or PARITY checks.  
Ñ
Reserved, should be cleared.  
4.3.2.14 Time Counter Status and Control Register (TMCNTSC)  
The time counter status and control register (TMCNTSC), shown in Figure 4-35, is used to  
enable the different TMCNT functions and for reporting the source of the interrupts. The  
register can be read at any time. Status bits are cleared by writing ones; writing zeros does  
not affect the value of a status bit.  
.
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Ñ
SEC ALR  
Ñ
SIE ALE TCF TCE  
0000_0000_0000_0000  
R/W  
Addr  
0x10220  
Figure 4-35. Time Counter Status and Control Register (TMCNTSC)  
Table 4-19 describes TMCNTSC Þelds.  
Table 4-19. TMCNTSC Field Descriptions  
Bits  
Name  
Description  
0Ð7  
8
Ñ
Reserved, should be cleared.  
SEC Once per second interrupt. This status bit is set every second and should be cleared by software.  
9
ALR Alarm interrupt.This status bit is set when the value of the TMCNT is equal to the value programmed  
in the alarm register.  
10Ð11  
12  
Ñ
Reserved, should be cleared.  
SIE  
Second interrupt enable.  
0 The time counter does not generate an interrupt when SEC is set.  
1 The time counter generates an interrupt when SEC is set.  
13  
ALE  
Alarm interrupt enable. If ALE = 1, the time counter generates an interrupt when ALR is set.  
4-40  
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Part II. ConÞguration and Reset  
Table 4-19. TMCNTSC Field Descriptions (Continued)  
Bits  
Name  
Description  
14  
TCF Time counter frequency. The input clock to the time counter may be either 4 MHz or 32 KHz. The  
user should set the TCF bit according to the frequency of this clock.  
0
1
The input clock to the time counter is 4 MHz.  
The input clock to the time counter is 32 KHz.  
See Section 4.1.2, ÒTimers ClockÓ for further details.  
15  
TCE Time counter enable. Is not affected by soft or hard reset.  
0
1
The time counter is disabled.  
The time counter is enabled.  
4.3.2.15 Time Counter Register (TMCNT)  
The time counter register (TMCNT), shown in Figure 4-36, contains the current value of  
the time counter.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
TMCNT  
Ñ
R/W  
Addr  
Bits  
0x10224  
24  
16  
17  
18  
19  
20  
21  
22  
23  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
TMCNT  
Ñ
R/W  
Addr  
0x10226  
Figure 4-36. Time Counter Register (TCMCNT)  
4.3.2.16 Time Counter Alarm Register (TMCNTAL)  
The time counter alarm register (TMCNTAL), shown in Figure 4-37, holds a value  
(ALARM). When the value of TMCNT equals ALARM, a maskable interrupt is generated.  
4-41  
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Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
ALARM  
Ñ
9
10  
11  
12  
13  
14  
15  
R/W  
Addr  
Bits  
0x1022C  
24  
16  
17  
18  
19  
20  
21  
22  
23  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
ALARM  
Ñ
R/W  
Addr  
0x1222E  
Figure 4-37. Time Counter Alarm Register (TMCNTAL)  
Table 4-20 describes TMCNTAL Þelds.  
Table 4-20. TMCNTAL Field Descriptions  
Bits Name  
Description  
0Ð31 ALARM The alarm interrupt is generated when ALARM Þeld matches the corresponding TMCNT bits. The  
resolution of the alarm is 1 second.  
4.3.3 Periodic Interrupt Registers  
The periodic interrupt registers are described in the following sections.  
4.3.3.1 Periodic Interrupt Status and Control Register (PISCR)  
The periodic interrupt status and control register (PISCR), shown in Figure 4-38, contains  
the interrupt request level and the interrupt status bit. It also contains the controls for the 16  
bits to be loaded in a modulus counter.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Ñ
PS  
Ñ
PIE PTF PTE  
0000_0000_0000_0000  
R/W  
Addr  
0x10240  
Figure 4-38. Periodic Interrupt Status and Control Register (PISCR)  
4-42  
MPC8260 PowerQUICC II UserÕs Manual  
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Part II. ConÞguration and Reset  
Table 4-21 describes PISCR Þelds.  
Table 4-21. PISCR Field Descriptions  
Bits Name  
Description  
0Ð7  
8
Ñ
Reserved, should be cleared.  
PS Periodic interrupt status. Asserted if the PIT issues an interrupt. The PIT issues an interrupt after the  
modulus counter counts to zero.The PS bit can be negated by writing a one to PS. A write of zero has  
no effect on this bit.  
9Ð12  
13  
Ñ
Reserved, should be cleared.  
PIE Periodic interrupt enable. If PIE = 1, the periodic interrupt timer generates an interrupt when PS = 1.  
14  
PTF Periodic interrupt frequency. The input clock to the periodic interrupt timer may be either 4 MHz or  
32 KHz. The user should set the PTF bit according to the frequency of this clock.  
0
1
The input clock to the periodic interrupt timer is 4 MHz.  
The input clock to the periodic interrupt timer is 32 KHz.  
See Section 4.1.2, ÒTimers Clock,Ó for further details  
15  
PTE Periodic timer enable. This bit controls the counting of the periodic interrupt timer. When the timer is  
disabled, it maintains its old value. When the counter is enabled, it continues counting using the  
previous value.  
0
1
Disable counter.  
Enable counter  
4.3.3.2 Periodic Interrupt Timer Count Register (PITC)  
The periodic interrupt timer count register (PITC), shown in Figure 4-39, contains the 16  
bits to be loaded in a modulus counter.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
PITC  
0000_0000_0000_0000  
R/W  
Addr  
Bits  
0x10244  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
Ñ
0000_0000_0000_0000  
R/W  
Addr  
0x10246  
Figure 4-39. Periodic interrupt Timer Count Register (PITC)  
4-43  
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Part II. ConÞguration and Reset  
Table 4-22 describes PITC Þelds.  
Table 4-22. PITC Field Descriptions  
Bits Name  
Description  
0Ð15 PITC Periodic interrupt timing count. Bits 0Ð15 are deÞned as the PITC, which contains the count for the  
periodic timer. Setting PITC to 0xFFFF selects the maximum count period.  
16Ð31  
Ñ
Reserved, should be cleared.  
4.3.3.3 Periodic Interrupt Timer Register (PITR)  
The periodic interrupt timer register (PITR), shown in Figure 4-40, is a read-only register  
that shows the current value in the periodic interrupt down counter. The PITR counter is not  
affected by reads or writes to it.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
PIT  
0000_0000_0000_0000  
Read Only  
Addr  
Bits  
0x10248  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
Ñ
0000_0000_0000_0000  
Read Only  
Addr  
0x1024A  
Figure 4-40. Periodic Interrupt Timer Register (PITR)  
Table 4-23 describes PITR Þelds.  
Table 4-23. PITR Field Descriptions  
Bits  
Name  
Description  
0Ð15  
PITC Periodic interrupt timing count. Bits 0Ð15 are deÞned as the PIT. It contains the current count  
remaining for the periodic timer. Writes have no effect on this Þeld.  
16Ð31  
Ñ
Reserved, should be cleared.  
4.4 SIU Pin Multiplexing  
Some functions share pins. The actual pinout of the MPC8260 is shown in the hardware  
speciÞcations. The control of the actual functionality used on a speciÞc pin is shown in  
4-44  
MPC8260 PowerQUICC II UserÕs Manual  
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Part II. ConÞguration and Reset  
Table 4-24.  
Table 4-24. SIU Pins Multiplexing Control  
Pin Name  
Pin ConÞguration Control  
GBL/IRQ1  
Controlled by SIUMCR programming see Section 4.3.2.6, ÒSIU Module  
ConÞguration Register (SIUMCR),Ó for more details.  
CI/BADDR29/IRQ2  
WT/BADDR30/IRQ3  
L2_HIT/IRQ4  
CPU_BG/BADDR31/IRQ5  
ABB/IRQ2  
DBB/IRQ3  
NC/DP0/RSRV/EXT_BR2  
IRQ1/DP1/EXT_BG2  
IRQ2/DP2/TLBISYNC/EXT_DBG2  
IRQ3/DP3/CKSTP_OUT/EXT_BR3  
IRQ4/DP4/CORE_SRESET/EXT_BG3  
IRQ5/DP5/TBEN/EXT_DBG3  
IRQ6/DP6/CSE0  
IRQ7/DP7/CSE1  
CS[10]/BCTL1/DBG_DIS  
CS[11]/AP[0]  
PAR/L_A14  
SMI/FRAME/L_A15  
TRDY/L_A16  
CKSTOP_OUT/IRDY/L_A17  
STOP/L_A18  
DEVSEL/L_A19  
IDSEL/L_A20  
PERR/L_A21  
SERR/L_A22  
REQ0/L_A23  
REQ1/L_A24  
GNT0/L_A25  
GNT1/L_A26  
CLK/L_A27  
CORE_SRESET/RST/L_A28  
INTA/L_A29  
LOCK/L_A30  
AD[0–31]/LCL_D[0Ð31]  
C/BE[0–3]/LCL_DP[0Ð3]  
BNKSEL[0]/TC[0]/AP[1]/MODCK1  
BNKSEL[1]/TC[1]/AP[2]/MODCK2  
BNKSEL[2]/TC[2]/AP[3]/MODCK3  
PWE[0Ð7]/PSDDQM[0Ð7]/PBS[0Ð7]  
PSDA10/PGPL0  
PSDWE/PGPL1  
Controlled dynamically according to the speciÞc memory controller  
machine that handles the current bus transaction.  
POE/PSDRAS/PGPL2  
PSDCAS/PGPL3  
PGTA/PUPMWAIT/PGPL4/PPBS  
PSDAMUX/PGPL5  
LBS[0Ð3]/LSDDQM[0Ð3]/LWE[0Ð3]  
LGPL0/LSDA10  
LGPL1/LSDWE  
LGPL2/LSDRAS/LOE  
LGPL3/LSDCAS  
LPBS/LGPL4/LUPWAIT/LGTA  
LGPL5/LSDAMUX  
MOTOROLA  
Chapter 4. System Interface Unit (SIU)  
4-45  
 
Part II. ConÞguration and Reset  
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MPC8260 PowerQUICC II UserÕs Manual  
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Chapter 5  
Reset  
50  
50  
The MPC8260 has several inputs to the reset logic:  
¥
¥
¥
¥
¥
¥
¥
Power-on reset (PORESET)  
External hard reset (HRESET)  
External soft reset (SRESET)  
Software watchdog reset  
Bus monitor reset  
Checkstop reset  
JTAG reset  
All of these reset sources are fed into the reset controller and, depending on the source of  
the reset, different actions are taken. The reset status register, described in Section 5.2,  
ÒReset Status Register (RSR),Ó indicates the last sources to cause a reset.  
5.1 Reset Causes  
Table 5-1 describes reset causes.  
Table 5-1. Reset Causes  
Name  
Description  
Power-on reset Input pin. Asserting this pin initiates the power-on reset ßow that resets all the chip and conÞgures  
(PORESET)  
various attributes of the chip including its clock mode.  
Hard reset  
(HRESET)  
This is a bidirectional I/O pin. The MPC8260 can detect an external assertion of HRESET only if it  
occurs while the MPC8260 is not asserting reset. During HRESET, SRESET is asserted. HRESET is  
an open-collector pin.  
Soft reset  
(SRESET)  
Bidirectional I/O pin. The MPC8260 can only detect an external assertion of SRESET if it occurs while  
the MPC8260 is not asserting reset. SRESET is an open-drain pin.  
Software After the MPC8260Õs watchdog counts to zero, a software watchdog reset is signaled. The enabled  
watchdog reset software watchdog event then generates an internal hard reset sequence.  
Bus monitor  
reset  
After the MPC8260s bus monitor counts to zero, a bus monitor reset is asserted. The enabled bus  
monitor event then generates an internal hard reset sequence.  
Checkstop  
reset  
If the core enters checkstop state and the checkstop reset is enabled (RMR[CSRE] = 1), the checkstop  
reset is asserted. The enabled checkstop event then generates an internal hard reset sequence.  
JTAG reset  
When JTAG logic asserts the JTAG soft reset signal, an internal soft reset sequence is generated.  
MOTOROLA  
Chapter 5. Reset  
5-1  
           
Part II. ConÞguration and Reset  
5.1.1 Reset Actions  
The reset block has a reset control logic that determines the cause of reset, synchronizes it  
if necessary, and resets the appropriate logic modules. The memory controller, system  
protection logic, interrupt controller, and parallel I/O pins are initialized only on hard reset.  
Soft reset initializes the internal logic while maintaining the system conÞguration.  
Table 5-2 identiÞes reset actions for each reset source.  
Table 5-2. Reset Actions for Each Reset Source  
Reset Logic  
and PLL  
States Reset  
System  
ConÞguration Module  
Sampled  
Clock  
Other  
Internal  
Logic Reset  
HRESET  
Driven  
SRESET  
Driven  
Core  
Reset  
Reset Source  
Reset  
Power-on reset  
Yes  
No  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
External hard reset  
Software watchdog  
Bus monitor  
Checkstop  
JTAG reset  
External soft reset  
No  
No  
No  
No  
Yes  
Yes  
Yes  
5.1.2 Power-On Reset Flow  
Assertion of the PORESET external pin initiates the power-on reset ßow. PORESET should  
be asserted externally for at least 16 input clock cycles after external power to the chip  
reaches at least 2/3 Vcc. The value driven on RSTCONF while PORESET changes from  
assertion to negation determines the chip conÞguration. If RSTCONF is negated (driven  
high) while PORESET changes, the chip acts as a conÞguration slave. If RSTCONF is  
asserted while PORESET changes, the chip acts as a conÞguration master. Section 5.4,  
ÒReset ConÞguration,Ó explains the conÞguration sequence and the terms ÔconÞguration  
masterÕ and ÔconÞguration slave.Õ  
Directly after the negation of PORESET and choice of the reset operation mode as  
conÞguration master or conÞguration slave, the MPC8260 starts the conÞguration process.  
The MPC8260 asserts HRESET and SRESET throughout the power-on reset process,  
including conÞguration. ConÞguration takes 1,024 CLOCKIN cycles, after which  
MODCK[1Ð3] are sampled to determine the chips working mode. Next the MPC8260 halts  
until the main PLL locks. As described in Section 9.2, ÒClock ConÞguration,Ó the main  
PLL locks according to MODCK[1Ð3], which are sampled, and to MODCK_HI  
(MODCK[4Ð7]) taken from the reset conÞguration word. The main PLL lock can take up  
to 200 µs depending on the speciÞc chip. During this time HRESET and SRESET are  
asserted. When the main PLL is locked, the clock block starts distributing clock signals in  
the chip. HRESET remains asserted for another 512 clocks and is then released. The  
SRESET is released three clocks later.  
5-2  
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Figure 5-3 shows the power-on reset ßow.  
External  
pin is  
asserted  
for min 16  
PORESET  
Input  
RSTCONF is sampled for  
master determination  
PORESET  
Internal  
MODCK[1Ð3] are  
sampled. MODCK_HI  
bits are ready for PLL  
HRESET  
Output  
PLL is locked (no  
external indication)  
SRESET  
Output  
PLL locking period  
HRESET /SRESET are  
extended for 512/515  
CLKIN (respectively), from  
PLL lock time.  
PORESET to internal logic  
is extended for 1024 CLKIN.  
Interval depends on  
PLL locking time.  
In reset conÞguration mode:  
reset conÞguration  
sequence occurs in this  
period.  
5.1.3 HRESET Flow  
The HRESET ßow may be initiated externally by asserting HRESET or internally when the  
chip detects a reason to assert HRESET. In both cases the chip continues asserting  
HRESET and SRESET throughout the HRESET ßow. The HRESET ßow begins with the  
hard reset conÞguration sequence, which conÞgures the chip as explained in Section 5.4,  
ÒReset ConÞguration.Ó After the chip asserts HRESET and SRESET for 1,024 input clock  
cycles, it releases both signals and exits the HRESET ßow. An external pull-up resistor  
should negate the signals. After negation is detected, a 16-cycle period is taken before  
testing the presence of an external (hard/soft) reset.  
5.1.4 SRESET Flow  
The SRESET ßow may be initiated externally by asserting SRESET or internally when the  
chip detects a cause to assert SRESET. In both cases the chip asserts SRESET for 512 input  
clock cycles, after which the chip releases SRESET and exits the SRESET ßow.An external  
pull-up resistor should negate SRESET; after negation is detected, a 16-cycle period is  
taken before testing the presence of an external (hard/soft) reset. While SRESET is  
asserted, internal hardware is reset but hard reset conÞguration does not change.  
MOTOROLA  
Chapter 5. Reset  
5-3  
       
Part II. ConÞguration and Reset  
5.2 Reset Status Register (RSR)  
The reset status register (RSR), shown in Figure 5-1, is memory-mapped into the  
MPC8260Õs SIU register map.  
Bits  
Field  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Ñ
R/W  
Reset  
Addr  
Bits  
0000_0000_0000_0000  
0x10C90  
16  
17  
18 19 20 21 22 23 24 25  
26  
27  
28  
29  
30  
31  
Field  
R/W  
Ñ
JTRS CSRS SWRS BMRS ESRS EHRS  
R/W  
Reset  
Addr  
0000_0000_0000_0011  
0x10C92  
Figure 5-1. Reset Status Register (RSR)  
Table 5-3 describes RSR Þelds.  
Table 5-3. RSR Field Descriptions  
Bits  
Name  
Function  
0Ð25  
26  
Ñ
Reserved, should be cleared.  
JTRS  
JTAG reset status. When the JTAG reset request is set, JTRS is set and remains set until software  
clears it. JTRS is cleared by writing a 1 to it (writing zero has no effect).  
0 No JTAG reset event occurred  
1 A JTAG reset event occurred  
27  
28  
29  
CSRS Check stop reset status. When the core enters a checkstop state and the checkstop reset is  
enabled by the RMR[CSRE], CSRS is set and it remains set until software clears it. CSRS is  
cleared by writing a 1 to it (writing zero has no effect).  
0 No enabled checkstopreset event occurred  
1 An enabled checkstopreset event occurred  
SWRS Software watchdog reset status. When a software watchdog expire event (which causes a reset) is  
detected, the SWRS bit is set and remains that way until the software clears it. SWRS is cleared by  
writing a 1 to it (writing zero has no effect).  
0 No software watchdog reset event occurred  
1 A software watchdog reset event has occurred  
BMRS Bus monitor reset status. When a bus monitor expire event (which causes a reset) is detected,  
BMRS is set and remains set until the software clears it. BMRS can be cleared by writing a 1 to it  
(writing zero has no effect).  
0 No bus monitor reset event has occurred  
1 A bus monitor reset event has occurred  
5-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part II. ConÞguration and Reset  
Table 5-3. RSR Field Descriptions (Continued)  
Bits  
Name  
Function  
30  
ESRS External soft reset status.When an external soft reset event is detected, ESRS is set and it remains  
that way until software clears it. ESRS is cleared by writing a 1 to it (writing zero has no effect).  
0 No external soft reset event has occurred  
1 An external soft reset event has occurred  
31  
EHRS External hard reset status. When an external hard reset event is detected, EHRS is set and it  
remains set until software clears it. EHRS is cleared by writing a 1 (writing zero has no effect).  
0 No external hard reset event has occurred  
1 An external hard reset event has occurred  
Note that RSR accumulates reset events. For example, because software watchdog  
expiration results in a hard reset, which in turn results in a soft reset, RSR[SWRS],  
RSR[ESRS] and RSR[EHRS] are all set after a software watchdog reset.  
5.3 Reset Mode Register (RMR)  
The reset mode register (RMR), shown in Figure 5-2, is memory-mapped into the SIU  
register map.  
Bits  
Field  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Ñ
R/W  
Reset  
Addr  
Bits  
0000_0000_0000_0000  
0x10C94  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
R/W  
Ñ
CSRE  
R/W  
Reset  
Addr  
0000_0000_0000_0000  
0x10C96  
Figure 5-2. Reset Mode Register (RMR)  
Table 5-4 describes RMR Þelds.  
Table 5-4. RMR Field Descriptions  
Bits Name  
Function  
0Ð30  
31  
Ñ
Reserved, should be cleared.  
CSRE Checkstop reset enable. The core can enter checkstop mode as the result of several exception  
conditions. Setting CSRE conÞgures the chip to perform a hard reset sequence whenever the core  
enters checkstop state.  
0 Reset not generated when core enters checkstop state.  
1 Reset generated when core enters checkstop state.  
MOTOROLA  
Chapter 5. Reset  
5-5  
         
Part II. ConÞguration and Reset  
5.4 Reset ConÞguration  
Various features may be conÞgured during hard reset or power-on reset. For example, one  
conÞgurable features is core disable, which can be used to conÞgure a system that uses two  
MPC8260s, one a slave device and the other a the host with an active core. Most  
conÞgurable features are reconÞgured whenever HRESET is asserted. However, the clock  
mode is conÞgured only when PORESET is asserted.  
The 32-bit hard reset conÞguration word is described in Section 5.4.1, ÒHard Reset  
ConÞguration Word.Ó The reset conÞguration sequence is designed to support a system that  
uses up to eight MPC8260 chips, each conÞgured differently. It needs no additional glue  
logic for reset conÞguration.  
The description below explains the operation of this sequence with regard to a multiple-  
MPC8260 system. This and other simpler systems are described in Section 5.4.2, ÒHard  
Reset ConÞguration Examples.Ó In a typical multi-MPC8260 system, one MPC8260  
should act as the conÞguration master while all other MPC8260s should act as  
conÞguration slaves. The conÞguration master in the system typically reads the various  
conÞguration words from EPROM in the system and uses them to conÞgure itself as well  
as the conÞguration slaves. How the MPC8260 acts during reset conÞguration is  
determined by the value of the RSTCONF input while PORESET changes from assertion  
to negation. If RSTCONF is asserted while PORESET changes, MPC8260 is a  
conÞguration master; otherwise, it is a slave.  
In a typical multiple-MPC8260 system, RSTCONF input of the conÞguration master  
should be hard wired to ground, while RSTCONF inputs of other chips should be connected  
to the high-order address bits of the conÞguration master, as described in Table 5-5.  
Table 5-5. RSTCONF Connections in Multiple-MPC8260 Systems  
ConÞgured Device  
ConÞguration master  
RSTCONF Connection  
GND  
A0  
First conÞguration slave  
Second conÞguration slave  
Third conÞguration slave  
Fourth conÞguration slave  
Fifth conÞguration slave  
Sixth conÞguration slave  
Seventh conÞguration slave  
A1  
A2  
A3  
A4  
A5  
A6  
The conÞguration words for all MPC8260s are assumed to reside in an EPROM connected  
to CS0 of the conÞguration master. Because the port size of this EPROM is not known to  
the conÞguration master, before reading the conÞguration words, the conÞguration master  
reads all conÞguration words byte-by-byte only from locations that are independent of port  
size.  
5-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part II. ConÞguration and Reset  
Table 5-6 shows addresses that should be used to conÞgure the various MPC8260s. Byte  
addresses that do not appear in this table have no effect on the conÞguration of the  
MPC8260 chips. The values of the bytes in Table 5-6 are always read on byte lane D[0Ð7]  
regardless of the port size.  
Table 5-6. Configuration EPROM Addresses  
ConÞgured Device  
ConÞguration master  
Byte 0 Address Byte 1 Address Byte 2 Address Byte 3 Address  
0x00  
0x20  
0x40  
0x60  
0x80  
0xA0  
0xC0  
0xE0  
0x08  
0x28  
0x48  
0x68  
0x88  
0xA8  
0xC8  
0xE8  
0x10  
0x30  
0x50  
0x70  
0x90  
0xB0  
0xD0  
0xF0  
0x18  
0x38  
0x58  
0x78  
0x98  
0xB8  
0xD8  
0xF8  
First conÞguration slave  
Second conÞguration slave  
Third conÞguration slave  
Fourth conÞguration slave  
Fifth conÞguration slave  
Sixth conÞguration slave  
Seventh conÞguration slave  
The conÞguration master Þrst reads a value from address 0x00 then reads a value from  
addresses 0x08, 0x10, and 0x18. These four bytes are used to form the conÞguration word  
of the conÞguration master, which then proceeds reading the bytes that form the  
conÞguration word of the Þrst slave device. The conÞguration master drives the whole  
conÞguration word on D[0Ð31] and toggles its A0 address line. Each conÞguration slave  
uses its RSTCONF input as a strobe for latching the conÞguration word during HRESET  
assertion time. Thus, the Þrst conÞguration slave whose RSTCONF input is connected to  
conÞguration masterÕs A0 output latches the word driven on D[0Ð31] as its conÞguration  
word. In this way the conÞguration master continues to conÞgure all MPC8260 chips in the  
system. The conÞguration master always reads eight conÞguration words regardless of the  
number of MPC8260 parts in the system. In a simple system that uses one stand-alone  
MPC8260, it is possible to use the default hard reset conÞguration word (all zeros). This is  
done by tying RSTCONF input to VCC. Another scenario may be a system which has no  
boot EPROM. In this case the user can conÞgure the MPC8260 as a conÞguration slave by  
driving RSTCONF to 1 during PORESET assertion and then applying a negative pulse on  
RSTCONF and an appropriate conÞguration word on D[0Ð31]. In such a system, asserting  
HRESET in the middle of operation causes the MPC8260 to return to the conÞguration  
programmed after PORESET assertion (not the default conÞguration represented by  
conÞguration word of all zeros).  
MOTOROLA  
Chapter 5. Reset  
5-7  
 
Part II. ConÞguration and Reset  
5.4.1 Hard Reset ConÞguration Word  
The contents of the hard reset conÞguration word are shown in Figure 5-3.  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
Ñ
13  
29  
14  
15  
31  
Field EARB EXMC CDIS EBM  
Reset  
BPS  
CIP ISPS  
0000_0000_0000_0000  
22 23 24 25  
APPC CS10PC  
0000_0000_0000_0000  
L2CPC  
DPPC  
ISB  
Bits  
Field  
Reset  
16  
17  
18  
19  
20  
21  
26  
27  
28  
30  
BMS  
BBD  
MMR  
LBPC  
Ñ
MODCK_H  
Figure 5-3. Hard Reset Configuration Word  
Table 5-7 describes hard reset conÞguration word Þelds.  
Table 5-7. Hard Reset Configuration Word Field Descriptions  
Bits  
Name  
Description  
0
EARB  
EXMC  
CDIS  
External arbitration. DeÞnes the initial value for ACR[EARB]. If EARB = 1, external arbitration is  
assumed. See Section 4.3.2.2, Ò60x Bus Arbiter ConÞguration Register (PPC_ACR).Ó  
1
2
External MEMC. DeÞnes the initial value of BR0[EMEMC]. If EXMC = 1, an external memory  
controller is assumed. See Section 10.3.1, ÒBase Registers (BRx).Ó  
Core disable. DeÞnes the initial value for the SIUMCR[CDIS].  
0 The core is active. See Section 4.3.2.6, ÒSIU Module ConÞguration Register (SIUMCR).Ó  
1 The core is disabled. In this mode the MPC8260 functions as a slave.  
3
EBM  
BPS  
External bus mode. DeÞnes the initial value of BCR[EBM]. See Section 4.3.2.1, ÒBus  
ConÞguration Register (BCR).Ó  
4Ð5  
Boot port size. DeÞnes the initial value of BR0[PS], the port size for memory controller bank 0.  
00 64-bit port size  
01 8-bit port size  
10 16-bit port size  
11 32-bit port size  
See Section 10.3.1, ÒBase Registers (BRx).Ó  
6
7
CIP  
Core initial preÞx. DeÞnes the initial value of MSR[IP]. Exception preÞx. The setting of this bit  
speciÞes whether an exception vector offset is prepended with Fs or 0s. In the following  
description, nnnnn is the offset of the exception vector.  
0 MSR[IP] = 1 (default). Exceptions are vectored to the physical address 0xFFFn_nnnn  
1 MSR[IP] = 0 Exceptions are vectored to the physical address 0x000n_nnnn.  
ISPS  
Internal space port size. DeÞnes the initial value of BCR[ISPS]. Setting ISPS conÞgures the  
MPC8260 to respond to accesses from a 32-bit external master to its internal space. See  
Section 4.3.2.1, ÒBus ConÞguration Register (BCR).Ó  
8Ð9  
10Ð11  
12  
L2CPC  
DPPC  
Ñ
L2 cache pins conÞguration. DeÞnes the initial value of SIUMCR[L2CPC]. See Section 4.3.2.6,  
ÒSIU Module ConÞguration Register (SIUMCR).Ó  
Data parity pin conÞguration. DeÞnes the initial value of SIUMCR[DPPC]. For more details refer  
to Section 4.3.2.6, ÒSIU Module ConÞguration Register (SIUMCR).Ó  
Reserved, should be cleared.  
5-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part II. ConÞguration and Reset  
Table 5-7. Hard Reset Configuration Word Field Descriptions (Continued)  
Bits  
Name  
Description  
13Ð15  
ISB  
Initial internal space base select. DeÞnes the initial value of IMMR[0Ð14] and determines the  
base address of the internal memory space.  
000 0x0000_0000  
001 0x00F0_0000  
010 0x0F00_0000  
011 0x0FF0_0000  
100 0xF000_0000  
101 0xF0F0_0000  
110 0xFF00_0000  
111 0xFFF0_0000  
See Section 4.3.2.7, ÒInternal Memory Map Register (IMMR).Ó  
16  
BMS  
Boot memory space. DeÞnes the initial value for BR0[BA].There are two possible boot memory  
regions: HIMEM and LOMEM.  
0 0xFE00_0000Ñ0xFFFF_FFFF  
1 0x0000_0000Ñ0x01FF_FFFF  
See Section 10.3.1, ÒBase Registers (BRx).Ó  
17  
BBD  
MMR  
LBPC  
APPC  
Bus busy disable. DeÞnes the initial value of SIUMCR[BBD]. See Section 4.3.2.6, ÒSIU Module  
ConÞguration Register (SIUMCR).Ó  
18Ð19  
20Ð21  
22Ð23  
24Ð25  
26Ð27  
Mask masters requests. DeÞnes the initial value of SIUMCR[MMR]. See Section 4.3.2.6, ÒSIU  
Module ConÞguration Register (SIUMCR).Ó  
Local bus pin conÞguration. DeÞnes the initial value of SIUMCR[LBPC]. See Section 4.3.2.6,  
ÒSIU Module ConÞguration Register (SIUMCR).Ó  
Address parity pin conÞguration. DeÞnes the initial value of SIUMCR[APPC]. See  
Section 4.3.2.6, ÒSIU Module ConÞguration Register (SIUMCR).Ó  
CS10PC CS10 pin conÞguration. DeÞnes the initial value of SIUMCR[CS10PC]. See Section 4.3.2.6,  
ÒSIU Module ConÞguration Register (SIUMCR).Ó  
Ñ
Reserved, should be cleared.  
28Ð31 MODCK_H High-order bits of the MODCK bus, which determine the clock reset conÞguration. See  
Chapter 9, ÒClocks and Power Control,Ó for details.  
5.4.2 Hard Reset ConÞguration Examples  
This section presents some examples of hard reset conÞgurations in different systems.  
5.4.2.1 Single MPC8260 with Default ConÞguration  
This is the simplest conÞguration scenario. It can be used if the default values achieved by  
clearing the hard reset conÞguration word are desired. This is applicable only for systems  
using single-MPC8260 bus mode (as opposed to 60x bus mode). To enter this mode, tie  
RSTCONF to V  
as shown in Figure 5-4. The MPC8260 does not access the boot  
EPROM; it is assumed that the default conÞguration is used upon exiting hard reset.  
CC  
MOTOROLA  
Chapter 5. Reset  
5-9  
     
Part II. ConÞguration and Reset  
PORESET  
Vcc  
Configuration  
Slave Chip  
HRESET  
A[0Ð31]  
D[0Ð31]  
Vcc  
PORESET  
RSTCONF  
Figure 5-4. Single Chip with Default Configuration  
5.4.2.2 Single MPC8260 ConÞgured from Boot EPROM  
For a conÞguration that differs from the default, the MPC8260 can be used as a  
conÞguration master by tying RSTCONF to GND as shown in Figure 5-5. The MPC8260  
can access the boot EPROM. It is assumed the conÞguration is as deÞned there upon exiting  
hard reset.  
PORESET  
EPROM Control Signals  
VCC  
Boot EPROM  
Configuration Master Chip  
A[..]  
HRESET  
A[0Ð31]  
D[0Ð31]  
D[0Ð7]  
PORESET  
RSTCONF  
Figure 5-5. Configuring a Single Chip from EPROM  
5.4.2.3 Multiple MPC8260s ConÞgured from Boot EPROM  
For a complex system with multiple MPC8260 devices that may each be conÞgured  
differently, conÞguration is done by assigning one conÞguration master and multiple  
conÞguration slaves. The MPC8260 that controls the boot EPROM should be the  
conÞguration masterÑRSTCONF tied to GND. The RSTCONF inputs of the other  
MPC8260 devices are tied to the address bus lines, thus assigning them as conÞguration  
slaves. See Figure 5-6.  
5-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part II. ConÞguration and Reset  
PORESET  
VCC  
EPROM Control Signals  
Boot EPROM  
Configuration Master Chip  
A[0Ð31]  
A[..]  
D[0Ð7]  
HRESET  
D[0Ð31]  
PORESET  
RSTCONF  
Configuration Slave Chip 1  
HRESET  
D[0Ð31]  
PORESET  
RSTCONF  
A0  
Configuration Slave Chip 2  
HRESET  
D[0Ð31]  
PORESET  
RSTCONF  
A1  
Configuration Slave Chip 7  
HRESET  
PORESET  
D[0Ð31]  
RSTCONF  
A6  
Figure 5-6. Configuring Multiple Chips  
MOTOROLA  
Chapter 5. Reset  
5-11  
 
Part II. ConÞguration and Reset  
In this system, the conÞguration master initially reads its own conÞguration word. It then  
reads other conÞguration words and drives them to the conÞguration slaves by asserting  
RSTCONF. As Figure 5-6 shows, this complex conÞguration is done without additional  
glue logic. The conÞguration master controls the whole process by asserting the EPROM  
control signals and the systemÕs address signals as needed.  
5.4.2.4 Multiple MPC8260s in a System with No EPROM  
In some cases, the conÞguration master capabilities of the MPC8260 cannot be used. This  
can happen for example if there is no boot EPROM in the system or the boot EPROM is not  
controlled by an MPC8260.  
If this occurs, the user must do one of the following:  
¥
¥
Accept the default conÞguration,  
Emulate the conÞguration master actions in external logic (where the MPC8260 is  
a conÞguration slave).  
¥
The external hardware should be connected to all RSTCONF pins of the different  
devices and to the upper 32 bits of the data bus. During PORESET, the rising edge  
the external hardware should negate all RSTCONF inputs to put all of the devices in  
their conÞguration slave mode. For 1,024 clocks after PORESET negation, the  
external hardware can conÞgure the different devices by driving appropriate  
conÞguration words on the data bus and asserting RSTCONF for each device to  
strobe the data being received.  
5-12  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part III  
The Hardware Interface  
Intended Audience  
Part III is intended for system designers who need to understand how each MPC8260 signal  
works and how those signals interact.  
Contents  
Part III describes external signals, clocking, memory control, and power management of  
the MPC8260.  
It contains the following chapters:  
¥
Chapter 6, ÒExternal Signals,Ó shows a functional pinout of the MPC8260 and  
describes the MPC8260 signals.  
¥
¥
Chapter 7, Ò60x Signals,Ó describes signals on the 60x bus.  
Chapter 8, ÒThe 60x Bus,Ó describes the operation of the bus used by PowerPC  
processors.  
¥
¥
Chapter 9, ÒClocks and Power Control,Ó describes the clocking architecture of the  
MPC8260.  
Chapter 10, ÒMemory Controller,Ó describes the memory controller, which  
controlling a maximum of eight memory banks shared between a general-purpose  
chip-select machine (GPCM) and three user-programmable machines (UPMs).  
¥
¥
Chapter 11, ÒSecondary (L2) Cache Support,Ó provides information about  
implementation and conÞguration of a level-2 cache.  
Chapter 12, ÒIEEE 1149.1 TestAccess Port,Ó describes the dedicated user-accessible  
test access port (TAP), which is fully compatible with the IEEE 1149.1 Standard  
Test Access Port and Boundary Scan Architecture.  
MOTOROLA  
Part III. The Hardware Interface  
Part III-i  
   
Part III. The Hardware Interface  
Suggested Reading  
This section lists additional reading that provides background for the information in this  
manual as well as general information about the PowerPC architecture.  
MPC8xx Documentation  
Supporting documentation for the MPC8260 can be accessed through the world-wide web  
at http://www.motorola.com/SPS/RISC/netcomm. This documentation includes technical  
speciÞcations, reference materials, and detailed applications notes.  
PowerPC Documentation  
The PowerPC documentation is organized in the following types of documents:  
¥
PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors  
(Motorola order #: MPCBUSIF/AD) provides a detailed functional description of  
the 60x bus interface, as implemented on the PowerPC MPC601ª, MPC603,  
MPC604, and MPC750 family of PowerPC microprocessors. This document is  
intended to help system and chip set developers by providing a centralized reference  
source to identify the bus interface presented by the 60x family of PowerPC  
microprocessors.  
¥
Application notesÑThese short documents contain useful information about  
speciÞc design issues useful to programmers and engineers working with PowerPC  
processors.  
For a current list of PowerPC documentation, refer to the world-wide web at  
http://www.mot.com/PowerPC.  
Conventions  
This document uses the following notational conventions:  
Bold entries in Þgures and tables showing registers and parameter  
RAM should be initialized by the user.  
Bold  
mnemonics  
Instruction mnemonics are shown in lowercase bold.  
italics  
Italics indicate variable command parameters, for example, bcctrx.  
Book titles in text are set in italics.  
0x0  
PreÞx to denote hexadecimal number  
PreÞx to denote binary number  
0b0  
REG[FIELD]  
Abbreviations or acronyms for registers or buffer descriptors are  
shown in uppercase text. SpeciÞc bits, Þelds, or numerical ranges  
appear in brackets. For example, MSR[LE] refers to the little-endian  
mode enable bit in the machine state register.  
x
In certain contexts, such as in a signal encoding or a bit Þeld,  
indicates a donÕt care.  
Part III-ii  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part III. The Hardware Interface  
n
Â
&
|
Indicates an undeÞned numerical value  
NOT logical operator  
AND logical operator  
OR logical operator  
Acronyms and Abbreviations  
Table i contains acronyms and abbreviations used in this document. Note that the meanings  
for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an  
acronym stands may not be intuitively obvious.  
Table vi. Acronyms and Abbreviated Terms  
Term  
Meaning  
BD  
Buffer descriptor  
BIST  
BRI  
Built-in self test  
Basic rate interface  
CAM  
CPM  
CRC  
DMA  
DPLL  
DRAM  
DSISR  
EA  
Content-addressable memory  
Communications processor module  
Cyclic redundancy check  
Direct memory access  
Digital phase-locked loop  
Dynamic random access memory  
Register used for determining the source of a DSI exception  
Effective address  
EEST  
GCI  
Enhanced Ethernet serial transceiver  
General circuit interface  
GPCM  
HDLC  
General-purpose chip-select machine  
High-level data link control  
2
I C  
Inter-integrated circuit  
IDL  
Inter-chip digital link  
IEEE  
IrDA  
ISDN  
JTAG  
LIFO  
LRU  
Institute of Electrical and Electronics Engineers  
Infrared Data Association  
Integrated services digital network  
Joint Test Action Group  
Last-in-Þrst-out  
Least recently used  
MOTOROLA  
Part III. The Hardware Interface  
Part III-iii  
   
Part III. The Hardware Interface  
Table vi. Acronyms and Abbreviated Terms (Continued)  
Term  
LSB  
Meaning  
Least-signiÞcant byte  
lsb  
Least-signiÞcant bit  
LSU  
MAC  
MMU  
MSB  
msb  
MSR  
NMSI  
OSI  
Load/store unit  
Multiply accumulate  
Memory management unit  
Most-signiÞcant byte  
Most-signiÞcant bit  
Machine state register  
Nonmultiplexed serial interface  
Open systems interconnection  
Peripheral component interconnect  
PCI  
PCMCIA  
PRI  
Personal Computer Memory Card International Association  
Primary rate interface  
Rx  
Receive  
SCC  
SCP  
SDLC  
SDMA  
SI  
Serial communications controller  
Serial control port  
Synchronous data link control  
Serial DMA  
Serial interface  
SIU  
System interface unit  
SMC  
SNA  
SPI  
Serial management controller  
Systems network architecture.  
Serial peripheral interface  
Special-purpose register  
Static random access memory  
Time-division multiplexed  
Translation lookaside buffer  
Time-slot assigner  
SPR  
SRAM  
TDM  
TLB  
TSA  
Tx  
Transmit  
UART  
Universal asynchronous receiver/transmitter  
Part III-iv  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III. The Hardware Interface  
Table vi. Acronyms and Abbreviated Terms (Continued)  
Term  
UISA  
Meaning  
User instruction set architecture  
User-programmable machine  
UPM  
USART  
Universal synchronous/asynchronous receiver/transmitter  
MOTOROLA  
Part III. The Hardware Interface  
Part III-v  
Part III. The Hardware Interface  
Part III-vi  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Chapter 6  
External Signals  
60  
60  
This chapter describes the MPC8260 external signals. A more detailed description of 60x  
bus signals is provided in Chapter 8, ÒThe 60x Bus.Ó  
6.1 Functional Pinout  
Figure 6-1 shows MPC8260 signals grouped by function. Note that many of these signals  
are multiplexed and this Þgure does not indicate how these signals are multiplexed.  
NOTE  
A bar over a signal name indicates that the signal is active  
lowÑfor example, BB (bus busy). Active-low signals are  
referred to as asserted (active) when they are low and negated  
when they are high. Signals that are not active low, such as  
TSIZ[0Ð1] (transfer size signals) are referred to as asserted  
when they are high and negated when they are low.  
MOTOROLA  
Chapter 6. External Signals  
6-1  
     
Part III.The Hardware Interface  
VCCSYN/GNDSYN/VCCSYN1//VD-  
DH/VDD/VSS  
¾¾¾>100  
32 <¾¾> A[0Ð31]  
PAR/L_A14 <¾¾>  
SMI/FRAME/L_A15 <¾¾>  
TRDY/L_A16 <¾¾>  
CKSTOP_OUT/IRDY/L_A17 <¾¾>  
STOP/L_A18 <¾¾>  
1
1
1
1
1
1
1
1
5
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
<¾¾> TT[0Ð4]  
<¾¾> TSIZ[0Ð3]  
<¾¾> TBST  
<¾¾> GBL/IRQ1  
<¾¾> CI/BADDR29/IRQ2  
<¾¾> WT/BADDR30/IRQ3  
<¾¾¾ L2_HIT/IRQ4  
<¾¾> CPU_BG/BADDR31/IRQ5  
¾¾¾> CPU_DBG  
¾¾¾> CPU_BR  
<¾¾> BR  
DEVSEL/L_A19 <¾¾>  
IDSEL/L_A20 <¾¾>  
PERR/L_A21 <¾¾>  
L
O
C
A
L
SERR/L_A22 <¾¾>  
REQ0/L_A23 <¾¾>  
REQ1/L_A24 <¾¾>  
GNT0/L_A25 <¾¾>  
GNT1/L_A26 <¾¾¾  
CLK/L_A27 <¾¾>  
1
1
1
1
1
1
1
1
1
1
6
0
x
<¾¾> BG  
<¾¾> ABB/IRQ2  
<¾¾> TS  
<¾¾> AACK  
<¾¾> ARTRY  
<¾¾> DBG  
<¾¾> DBB/IRQ3  
B
U
S
M
P
C
8
2
6
CORE_SRESET/RST/L_A28 <¾¾>  
INTA/L_A29 <¾¾>  
LOCK/L_A30 <¾¾>  
L_A31 <¾¾>  
AD[0–31]/LCL_D[0Ð31] <¾¾> 32  
B
U
S
64 <¾¾> D[0Ð63]  
1
1
1
1
1
1
1
1
1
1
1
1
1
<¾¾> NC/DP0/RSRV/EXT_BR2  
<¾¾> IRQ1/DP1/EXT_BG2  
<¾¾> IRQ2/DP2/TLBISYNC/EXT_DBG2  
<¾¾> IRQ3/DP3/CKSTP_OUT/EXT_BR3  
<¾¾> IRQ4/DP4/CORE_SRESET/EXT_BG3  
<¾¾> IRQ5/DP5/TBEN/EXT_DBG3  
<¾¾> IRQ6/DP6/CSE0  
<¾¾> IRQ7/DP7/CSE1  
<¾¾> PSDVAL  
<¾¾> TA  
<¾¾> TEA  
C/BE[0–3]/LCL_DP[0Ð3] <¾¾>  
LBS[0Ð3]/LSDDQM[0Ð3]/LWE[0Ð3] <¾¾¾  
4
4
LGPL0/LSDA10 <¾¾¾  
LGPL1/LSDWE <¾¾¾  
LGPL2/LSDRAS/LOE <¾¾¾  
LGPL3/LSDCAS <¾¾¾  
LPBS/LGPL4/LUPWAIT/LGTA <¾¾>  
LGPL5 <¾¾>  
1
1
1
1
1
1
1
M
E
M
C
0
LWR <¾¾>  
<¾¾> IRQ0/NMI_OUT  
<¾¾> IRQ7/INT_OUT/APE  
PA[0Ð31] <¾¾> 32  
PB[4Ð31] <¾¾> 28  
PC[0Ð31] <¾¾> 32  
PD[4Ð31] <¾¾> 28  
PORESET¾¾¾> 1  
RSTCONF¾¾¾> 1  
HRESET<¾¾>  
SRESET<¾¾>  
QREQ<¾¾¾ 1  
P
I
O
10 ¾¾¾> CS[0Ð9]  
1
1
2
1
1
8
1
1
1
1
1
1
1
1
1
1
1
<¾¾> CS[10]/BCTL1/DBG_DIS  
<¾¾> CS[11]/AP[0]  
¾¾¾> BADDR[27Ð28]  
¾¾¾> ALE  
M
E
M
C
1
1
¾¾¾> BCTL0  
¾¾¾> PWE[0Ð7]/PSDDQM[0Ð7]/PBS[0Ð7]  
¾¾¾> PSDA10/PGPL0  
¾¾¾> PSDWE/PGPL1  
¾¾¾> POE/PSDRAS/PGPL2  
¾¾¾> PSDCAS/PGPL3  
<¾¾> PGTA/PUPMWAIT/PGPL4/PPBS  
¾¾¾> PSDAMUX/PGPL5  
<¾¾- TMS  
<¾¾¾TDI  
<¾¾- TCK  
<¾¾- TRST  
-¾¾> TDO  
R
S
T
XFC¾¾¾> 1  
CLKIN¾¾¾> 1  
TRIS¾¾¾> 1  
BNKSEL[0]/TC[0]/AP[1]/MODCK1<¾¾>  
BNKSEL[1]/TC[1]/AP[2]/MODCK2<¾¾>  
BNKSEL[2]/TC[2]/AP[3]/MODCK3<¾¾>  
C
L
K
1
1
1
J
T
A
G
TERM[0Ð1] ¾¾¾> 2  
NC ¾¾¾> 4  
Figure 6-1. MPC8260 External Signals  
6.2 Signal Descriptions  
The MPC8260 system bus, shown in Table 6-1, consists of all the signals that interface with  
the external bus. Many of these pins perform different functions, depending on how the user  
assigns them.  
6-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part III.The Hardware Interface  
Table 6-1. External Signals  
Signal  
Description  
BR  
60x bus requestÑThis is an output when an external arbiter is used and an input when an internal  
arbiter is used. As an output the MPC8260 asserts this pin to request ownership of the 60x bus. As  
an input an external master should assert this pin to request 60x bus ownership from the internal  
arbiter.  
BG  
60x bus grantÑThis is an output when an internal arbiter is used and an input when an external  
arbiter is used. As an output the MPC8260 asserts this pin to grant 60x bus ownership to an  
external bus master. As an input the external arbiter should assert this pin to grant 60x bus  
ownership to the MPC8260.  
ABB  
IRQ2  
60x address bus busyÑ(Input/output)As an output the MPC8260 asserts this pin for the duration of  
the address bus tenure. Following an AACK, which terminates the address bus tenure, the  
MPC8260 negates ABB for a fraction of a bus cycle and than stops driving this pin. As an input the  
MPC8260 will not assume 60x bus ownership as long as it senses this pin is asserted by an  
external 60x bus master.  
Interrupt Request 2ÑThis input is one of the eight external lines that can request (by means of the  
internal interrupt controller) a service routine from the core.  
TS  
60x bus transfer startÑ(Input/output)Assertion of this pin signals the beginning of a new address  
bus tenure.The MPC8260 asserts this signal when one of its internal 60x bus masters (core, DMA,  
PCI bridge) begins an address tenure. When the MPC8260 senses this pin being asserted by an  
external 60x bus master, it will respond to the address bus tenure as required (snoop if enabled,  
access internal MPC8260 resources, memory controller support).  
A[0Ð31]  
60x address busÑThese are input/output pins. When the MPC8260 is in external master bus  
mode, these pins function as the 60x address bus. The MPC8260 drives the address of its internal  
60x bus masters and respond to addresses generated by external 60x bus masters. When the  
MPC8260 is in internal master bus mode, these pins are used as address lines connected to  
memory devices and controlled by the MPC8260Õs memory controller.  
TT[0Ð4]  
TBST  
60x bus transfer typeÑThese are input/output pins. The 60x bus master drives these pins during  
the address tenure to specify the type of the transaction.  
60x bus transfer burstÑ(Input/output)The 60x bus master asserts this pin to indicate that the  
current transaction is a burst transaction (transfers 4 double words).  
TSIZ[0Ð3]  
AACK  
60x transfer sizeÑThese are input/output pins. The 60x bus master drives these pins with a value  
indicating the amount of bytes transferred in the current transaction.  
60x address acknowledgeÑThis is an input/output signal. A 60x bus slave asserts this signal to  
indicate that it identiÞed the address tenure. Assertion of this signal terminates the address tenure.  
ARTRY  
60x address retryÑ(Input/output)Assertion of this signal indicates that the bus transaction should  
be retried by the 60x bus master. The MPC8260 asserts this signal to enforce data coherency with  
its internal cache and to prevent deadlock situations.  
DBG  
60x data bus grantÑThis is an output when an internal arbiter is used and an input when an  
external arbiter is used. As an output the MPC8260 asserts this pin to grant 60x data bus  
ownership to an external bus master. As an input the external arbiter should assert this pin to grant  
60x data bus ownership to the MPC8260.  
MOTOROLA  
Chapter 6. External Signals  
6-3  
 
Part III.The Hardware Interface  
Table 6-1. External Signals (Continued)  
Signal  
Description  
DBB  
IRQ3  
60x data bus busyÑ(Input/output)As an output the MPC8260 asserts this pin for the duration of the  
data bus tenure. Following a TA, which terminates the data bus tenure, the MPC8260 negates DBB  
for a fraction of a bus cycle and than stops driving this pin. As an input, the MPC8260 does not  
assume 60x data bus ownership as long as it senses DBB asserted by an external 60x bus master.  
Interrupt request 3ÑThis input is one of the eight external lines that can request (by means of the  
internal interrupt controller) a service routine from the core.  
D[0Ð63]  
60x data busÑThese are input/output pins. In write transactions the 60x bus master drives the valid  
data on this bus. In read transactions the 60x slave drives the valid data on this bus.  
DP[0]  
RSRV  
EXT_BR2  
60x data parity 0Ñ(Input/output)The 60x agent that drives the data bus drives also the data parity  
signals. The value driven on data parity 0 pin should give odd parity (odd number of 1Õs) on the  
group of signals that includes data parity 0 and D[0Ð7].  
ReservationÑThe value driven on this output pin represents the state of the coherency bit in the  
reservation address register that is used by the lwarx and stwcx. instructions.  
External bus request 2Ñ(Input). An external master should assert this pin to request 60x bus  
ownership from the internal arbiter.  
IRQ1  
DP[1]  
EXT_BG2  
Interrupt request 1ÑThis input is one of the eight external lines that can request (by means of the  
internal interrupt controller) a service routine from the core.  
60x data parity 1Ñ(Input/output)The 60x agent that drives the data bus drives also the data parity  
signals. The value driven on data parity 1 pin should give odd parity (odd number of Ô1Õs) on the  
group of signals that includes data parity 1 and D[8Ð15].  
External bus grant 2Ñ(Output) The MPC8260 asserts this pin to grant 60x bus ownership to an  
external bus master.  
IRQ2  
DP[2]  
Interrupt request 2ÑThis input is one of the eight external lines that can request (by means of the  
internal interrupt controller) a service routine from the core.  
TLBISYNC  
EXT_DBG2  
60x data parity 2Ñ(Input/output)The 60x agent that drives the data bus drives also the data parity  
signals. The value driven on data parity 2 pin should give odd parity (odd number of Ô1Õs) on the  
group of signals that includes data parity 2 and S16Ð23].  
TLB syncÑThis input pin can be used to synchronize 60x core instruction execution to hardware  
indications. Asserting this pin will force the core to stop instruction execution following a tlbsync  
instruction execution. The core resumes instructions execution once this pin is negated.  
External data bus grant 2Ñ(Output) The MPC8260 asserts this pin to grant 60x data bus ownership  
to an external bus master.  
IRQ3  
DP[3]  
Interrupt request 3ÑThis input is one of the eight external lines that can request (by means of the  
internal interrupt controller) a service routine from the core.  
CKSTP_OUT 60x data parity 3Ñ(Input/output)The 60x agent that drives the data bus drives also the data parity  
EXT_BR3  
signals. The value driven on data parity 3 pin should give odd parity (odd number of 1Õs) on the  
group of signals that includes data parity 3 and D[24Ð31].  
Checkstop outputÑ(Output) Assertion indicates that the core is in its checkstop mode.  
External bus request 3Ñ(Input). An external master should assert this pin to request 60x bus  
ownership from the internal arbiter.  
IRQ4  
DP[4]  
Interrupt request 4ÑThis input is one of the eight external lines that can request (by means of the  
internal interrupt controller) a service routine from the core.  
CORE_SRESET 60x data parity 4Ñ(Input/output)The 60x agent that drives the data bus drives also the data parity  
EXT_BG3  
signals. The value driven on data parity 4 pin should give odd parity (odd number of Ô1Õs) on the  
group of signals that includes data parity 4 and D[32Ð39].  
Core system resetÑ(Input). Asserting this pin will force the core to branch to its reset vector.  
External bus grant 3Ñ(Output) The MPC8260 asserts this pin to grant 60x bus ownership to an  
external bus master.  
6-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
Table 6-1. External Signals (Continued)  
Signal  
Description  
IRQ5  
DP[5]  
TBEN  
Interrupt request 5ÑThis input is one of the eight external lines that can request (by means of the  
internal interrupt controller) a service routine from the core.  
60x data parity 5Ñ(Input/output)The 60x agent that drives the data bus drives also the data parity  
signals. The value driven on data parity 5 pin should give odd parity (odd number of Ô1Õs) on the  
group of signals that includes data parity 5 and D[40Ð47].  
EXT_DBG3  
Time base enableÑThis is a count enable input to the Time Base counter in the core.  
External data bus grant 3Ñ(Output) The MPC8260 asserts this pin to grant 60x data bus ownership  
to an external bus master.  
IRQ6  
DP[6]  
CSE[0]  
Interrupt request 6ÑThis input is one of the eight external lines that can request (by means of the  
internal interrupt controller) a service routine from the core.  
60x data parity 6Ñ(Input/output)The 60x agent that drives the data bus drives also the data parity  
signals. The value driven on data parity 6 pin should give odd parity (odd number of Ô1Õs) on the  
group of signals that includes data parity 6 and D[48Ð55].  
Cache set entry 0ÑThe cache set entry outputs from the core represent the cache replacement set  
element for the current core transaction reloading into or writing out of the cache.  
IRQ7  
DP[7]  
CSE[1]  
Interrupt request 7ÑThis input is one of the eight external lines that can request (by means of the  
internal interrupt controller) a service routine from the core.  
60x data parity 7Ñ(Input/output)The 60x master or slave that drives the data bus drives also the  
data parity signals.The value driven on data parity 7 pin should give odd parity (odd number of Ô1Õs)  
on the group of signals that includes data parity 7 and D[56Ð63].  
Cache set entry 1ÑThe cache set entry outputs from the core represent the cache replacement set  
element for the current core transaction reloading into or writing out of the cache.  
PSDVAL  
60x data validÑ(Input/output)Assertion of the PSDVAL pin indicates that a data beat is valid on the  
data bus. The difference between the TA pin and the PSDVAL pin is that the TA pin is asserted to  
indicate 60x data transfer terminations while the PSDVAL signal is asserted with each data beat  
movement. Thus always when TA is asserted, PSDVAL will be asserted but when PSDVAL is  
asserted, TA is not necessarily asserted. For example when a double word (2x64 bits) transfer is  
initiated by the SDMA to a memory device that has 32 bits port size, PSDVAL will be asserted 3  
times without TA and Þnally both pins will be asserted to terminate the transfer.  
TA  
Transfer acknowledgeÑ(Input/output) Indicates that a 60x data beat is valid on the data bus. For  
60x single beat transfers, assertion of this pin indicates the termination of the transfer. For 60x burst  
transfers TA is asserted four times to indicate the transfer of four data beats with the last assertion  
indicating the termination of the burst transfer.  
TEA  
Transfer error acknowledgeÑ(Input/output)Assertion of this pin indicates a bus error. 60x masters  
within the MPC8260 monitor the state of this pin. MPC8260Õs internal bus monitor may assert this  
pin in case it identiÞed a 60x bus transfer that is hung.  
GBL  
IRQ1  
GlobalÑ(Input/output)When a 60x master within the chip initiates a bus transaction it drives this  
pin.When an external 60x master initiates a bus transaction it should drive this pin. Assertion of this  
pin indicates that the transfer is global and it should be snooped by caches in the system. The  
MPC8260MPC8260Õs data cache monitors the state of this pin.  
Interrupt request 1ÑThis input is one of the eight external lines that can request (by means of the  
internal interrupt controller) a service routine from the core.  
CI  
BADDR29  
IRQ2  
Cache inhibitÑOutput pin. Used for L2 cache control. For each MPC8260 60x transaction initiated  
in the core, the state of this pin indicates if this transaction should be cached or not. Assertion of the  
CI pin indicates that the transaction should not be cached.  
Burst address 29ÑThere are Þve burst address output pins. These pins are outputs of the 60x  
memory controller.These pins are used in external master conÞguration and are connected directly  
to memory devices controlled by MPC8260Õs memory controller.  
Interrupt request 2ÑThis input is one of the eight external lines that can request (by means of the  
internal interrupt controller) a service routine from the core.  
MOTOROLA  
Chapter 6. External Signals  
6-5  
Part III.The Hardware Interface  
Table 6-1. External Signals (Continued)  
Signal  
Description  
WT  
BADDR30  
IRQ3  
Write throughÑOutput used for L2 cache control. For each core-initiated MPC8260 60x  
transaction, the state of this pin indicates if the transaction should be cached using write-through or  
copy-back mode. Assertion of WT indicates that the transaction should be cached using the  
write-through mode.  
Burst address 30ÑThere are Þve burst address output pins. These pins are outputs of the 60x  
memory controller.These pins are used in external master conÞguration and are connected directly  
to memory devices controlled by MPC8260Õs memory controller.  
Interrupt request 3ÑThis input is one of the eight external lines that can request (by means of the  
internal interrupt controller) a service routine from the core.  
L2_HIT  
IRQ4  
L2 cache hitÑ(Input). It is used for L2 cache control. Assertion of this pin indicates that the 60x  
transaction will be handled by the L2 cache. In this case, the memory controller will not start an  
access to the memory it controls.  
Interrupt request 4ÑThis input is one of the eight external lines that can request (by means of the  
internal interrupt controller) a service routine from the core.  
CPU_BG  
BADDR31  
IRQ5  
CPU bus grantÑ(Output) The value of the 60x core bus grant is driven on this pin for the use of an  
external MPC2605GA L2 cache. The driven bus grant is non qualiÞed, that is, in case of external  
arbiter the user should qualify this signal with the bus grant input to the MPC8260 before  
connecting it to the L2 cache.  
Burst address 31ÑThere are Þve burst address output of the 60x memory controller used in  
external master conÞguration and are connected directly to the memory devices controlled by  
MPC8260Õs memory controller.  
Interrupt Request 5ÑThis input is one of the eight external lines that can request (by means of the  
internal interrupt controller) a service routine from the core.  
CPU_DBG  
CPU_DBG  
CPU bus data bus grantÑ(Output) The value of the 60x core data bus grant is driven on this pin for  
the use of an external MPC2605GA L2 cache.  
CPU data bus grantÑ(Output). The OR of all data bus grant signals for internal masters from the  
internal arbiter is driven on CPU_DBG. CPU_DBG should be connected to the CPU_DBG input of  
an external MPC2605GA L2 cache if the internal arbiter is used (BCR[EARB] = 0). If an external  
arbiter is used in this MPC8260, the CPU_DBG input of the L2 cache should be connected to the  
DBG driven from the external arbiter to this MPC8260.  
CPU_BR  
CS[0Ð9]  
CPU bus requestÑ(Output) The value of the 60x core bus request is driven on this pin for the use  
of an external MPC2605GA L2 cache.  
Chip selectÑThese are output pins that enable speciÞc memory devices or peripherals connected  
to MPC8260 buses.  
CS[10]  
BCTL1  
DBG_DIS  
Chip selectÑThese are output pins that enable speciÞc memory devices or peripherals connected  
to MPC8260 buses.  
Buffer control 1ÑOutput signal whose its function is controlling buffers on the 60x data bus. Usually  
used with BCTL0. The exact function of this pin is deÞned by the value of SIUMCR[BCTLC]. See  
Section 4.3.2.6, ÒSIU Module ConÞguration Register (SIUMCR),Ó for details.  
Data bus grant disableÑThis is an output when the MPC8260 is in external arbiter mode and an  
input when the MPC8260 is in internal arbiter mode. When this pin is asserted, the 60x bus arbiter  
should negate all of its DBG outputs to prevent data bus contention.  
CS[11]  
AP[0]  
Chip selectÑOutput that enable speciÞc memory devices or peripherals connected to MPC8260  
buses.  
Address parity 0Ñ(Input/output)The 60x master that drives the address bus, drives also the  
address parity signals.The value driven on address parity 0 pin should give odd parity (odd number  
of Ô1Õs) on the group of signals that includes address parity 0 and A[0Ð7].  
6-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
Table 6-1. External Signals (Continued)  
Signal  
Description  
BADDR[27Ð28] Burst address 27:28ÑThere are Þve burst address output pins. These pins are outputs of the 60x  
memory controller. Used in external master conÞguration and connected directly to the memory  
devices controlled by MPC8260Õs memory controller.  
ALE  
Address latch enableÑThis output pin controls the external address latch that should be used in  
external master 60x bus conÞguration.  
BCTL0  
Buffer control 0ÑOutput whose function is controlling buffers on the 60x data bus. Usually used  
with BCTL1 that is multiplexed on CS10. The exact function of this pin is deÞned by the value of  
SIUMCR[BCTLC]. See Section 4.3.2.6, ÒSIU Module ConÞguration Register (SIUMCR),Ó for details.  
PWE[0Ð7]  
60x bus write enableÑOutputs of the 60x bus GPCM. These pins select byte lanes for write  
PSDDQM[0Ð7] operations.  
PBS[0Ð7]  
60x bus SDRAM DQMÑThe DQM pins are outputs of the SDRAM control machine. These pins  
select speciÞc byte lanes of SDRAM devices.  
60x bus UPM byte selectÑThe byte select pins are outputs of the UPM in the memory controller.  
They are used to select speciÞc byte lanes during memory operations. The timing of these pins is  
programmed in the UPM. The actual driven value depends on the address and size of the  
transaction and the port size of the accessed device.  
PSDA10  
PGPL0  
60x bus SDRAM A10Ñ(Output) from the 60x bus SDRAM controller. Part of the address when a  
row address is driven and is part of the command when a column address is driven.  
60x bus UPM general purpose line 0ÑThis is one of six general purpose output lines from UPM.  
The values and timing of this pin is programmed in the UPM.  
PSDWE  
PGPL1  
60x bus SDRAM write enableÑ(Output) from the 60x bus SDRAM controller. Should be connected  
to SDRAMsÕ WE input.  
60x bus UPM general purpose line 1ÑThis is one of six general purpose output lines from UPM.  
The values and timing of this pin is programmed in the UPM.  
POE  
PSDRAS  
PGPL2  
60x bus output enableÑThe output enable pin is an output of the 60x bus GPCM. Controls the  
output buffer of memory devices during read operations.  
60x bus SDRAM rasÑOutput from the 60x bus SDRAM controller. Should be connected to  
SDRAMsÕ RAS input.  
60x bus UPM general purpose line 2ÑThis is one of six general purpose output lines from UPM.  
The values and timing of this pin is programmed in the UPM.  
PSDCAS  
PGPL3  
60x bus SDRAM CASÑOutput from the 60x bus SDRAM controller. Should be connected to  
SDRAMsÕ CAS input.  
60x bus UPM general purpose line 3ÑThis is one of six general purpose output lines from UPM.  
The values and timing of this pin is programmed in the UPM.  
PGTA  
PUPMWAIT  
PGPL4  
60x GPCM TAÑThis input pin is used for transaction termination during GPCM operation. Requires  
external pull up resistor for proper operation.  
60x bus UPM waitÑThis is an input to the UPM. An external device may hold this pin low to force  
the UPM to wait until the device is ready for the continuation of the operation.  
60x bus UPM general purpose line 4ÑThis is one of six general purpose output lines from UPM.  
The values and timing of this pin is programmed in the UPM.  
PPBS  
60x bus parity byte selectÑIn systems in which data parity is stored in a separate chip, this output  
is used as the byte-select for that chip.  
PSDAMUX  
PGPL5  
60x bus SDRAM address multiplexerÑThis output pin controls the 60x SDRAM address multiplexer  
when the MPC8260 is in external master mode.  
60x bus UPM general purpose line 5ÑThis is one of six general purpose output lines from UPM.  
The values and timing of this pin is programmed in the UPM.  
MOTOROLA  
Chapter 6. External Signals  
6-7  
Part III.The Hardware Interface  
Table 6-1. External Signals (Continued)  
Signal  
Description  
LWE[0Ð3]  
Local bus write enableÑThe write enable pins are outputs of the Local bus GPCM. These pins  
LSDDQM[0Ð3] select speciÞc byte lanes for write operations.  
LBS[0Ð3]  
Local bus SDRAM DQMÑThe DQM pins are outputs of the SDRAM control machine. These pins  
select speciÞc byte lanes of SDRAM devices.  
Local bus UPM byte selectÑThe byte select pins are outputs of the UPM in the memory controller.  
They are used to select speciÞc byte lanes during memory operations. The timing of these pins is  
programmed in the UPM. The actual driven value depends on the address and size of the  
transaction and the port size of the accessed device.  
LSDA10  
LGPL0  
Local bus SDRAM A10. Output from the 60x bus SDRAM controller. Is part of the address when a  
row address is driven and is part of the command when a column address is driven.  
Local bus UPM general purpose line 0ÑThis is one of six general purpose output lines from UPM.  
The values and timing of this pin is programmed in the UPM.  
LSDWE  
LGPL1  
Local bus SDRAM write enableÑOutput from the local bus SDRAM controller. Should be  
connected to SDRAMsÕ WE input.  
Local bus UPM general purpose line 1ÑThis is one of six general purpose output lines from UPM.  
The values and timing of this pin is programmed in the UPM.  
LOE  
LSDRAS  
LGPL2  
Local bus output enableÑThe output enable pin is an output of the Local bus GPCM. Controls the  
output buffer of memory devices during read operations.  
Local bus SDRAM rasÑOutput from the Local bus SDRAM controller. Should be connected to the  
SDRAM RAS input.  
Local bus UPM general purpose line 2ÑThis is one of six general purpose output lines from UPM.  
The values and timing of this pin is programmed in the UPM.  
LSDCAS  
LGPL3  
Local bus SDRAM CASÑOutput from the Local bus SDRAM controller. Should be connected to  
SDRAMsÕ CAS input.  
Local bus UPM general purpose line 3ÑThis is one of six general purpose output lines from UPM.  
The values and timing of this pin is programmed in the UPM.  
LGTA  
LUPWAIT  
LGPL4  
LPBS  
Local bus GPCM TAÑThis input pin is used for transaction termination during GPCM operation.  
Requires external pull up resistor for proper operation.  
Local bus UPM waitÑThis is an input to the UPM. An external device may hold this pin low to force  
the UPM to wait until the device is ready for the continuation of the operation.  
Local bus UPM general purpose line 4ÑThis is one of six general purpose output lines from UPM.  
The values and timing of this pin is programmed in the UPM.  
Local bus parity byte selectÑIn systems in which the data parity is stored in a separate chip, this  
output is used as the byte select for that chip.  
LGPL5  
LWR  
Local bus UPM general purpose line 5ÑThis is one of six general purpose output lines from UPM.  
The values and timing of this pin is programmed in the UPM.  
Local writeÑThe local write pin is an output from the local bus memory controller. It is used to  
distinguish between read and write transactions.  
L_A14  
PCI_PAR  
Local bus address 14ÑLocal bus address bit 14 output pin. In the local address bus bit 14 is most  
signiÞcant and bit 31 is least signiÞcant.  
PCI parityÑPCI parity input/output pin. Assertion of this pin indicates that odd parity is driven  
across PCI_AD[0Ð31] and PCI_C/BE[0Ð3] during address and data phases. Negation of PCI_PAR  
indicates that even parity is driven across the PCI_AD[0Ð31] and PCI_C/BE[0Ð3] during address  
and data phases.  
6-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
Table 6-1. External Signals (Continued)  
Signal  
Description  
L_A15  
SMI  
PCI_FRAME  
Local bus address 15ÑLocal bus address bit 15 output pin. In the local address bus bit 14 is most  
signiÞcant and bit 31 is least signiÞcant.  
System management interruptÑSystem management interrupt input to the core.  
PCI frameÑPCI cycle frame input output pin. Used by the current PCI master to indicate the  
beginning and duration of an access. Driven by the MPC8260 when its PCI interface is the master  
of the access. Otherwise, it is an input.  
L_A16  
PCI_TRDY  
Local bus address 16ÑLocal bus address bit 16 output pin. In the local address bus bit 14 is most  
signiÞcant and bit 31 is least signiÞcant.  
PCI target readyÑPCI target ready input/output pin. This pin is driven by the MPC8260 when its  
PCI interface is the target of a PCI transfer. Assertion of this pin indicates that the PCI target is  
ready to send or accept a data beat.  
L_A17  
PCI_IRDY  
Local bus address 17ÑLocal bus address bit 17 output pin. In the local address bus bit 14 is most  
signiÞcant and bit 31 is least signiÞcant.  
CKSTOP_OUT PCI initiator readyÑPCI initiator ready input/output pin.This pin is driven by the MPC8260 when its  
PCI interface is the initiator of a PCI transfer. Assertion of this pin indicates that the PCI initiator is  
ready to send or accept a data beat.  
Checkstop outputÑ(Output) Assertion of CKSTOP_OUT indicates the core is in checkstop mode.  
L_A18  
PCI_STOP  
Local bus address 18ÑLocal bus address bit 18 output pin. In the local address bus bit 14 is most  
signiÞcant and bit 31 is least signiÞcant.  
PCI stopÑPCI stop input/output pin. This pin is driven by the MPC8260 when its PCI interface is  
the target of a PCI transfer. Assertion of this pin indicates that the PCI target is requesting the  
master to stop the current PCI transfer.  
L_A19  
Local bus address 19ÑLocal bus address bit 19 output pin. In the local address bus bit 14 is most  
PCI_DEVSEL signiÞcant and bit 31 is least signiÞcant.  
PCI device selectÑPCI device select input/output pin. This pin is driven by the MPC8260 when its  
PCI interface has decoded the address as the target of the current PCI transfer. As an input,  
PCI_DEVSEL indicates whether any device on the PCI bus has been selected.  
L_A20  
PCI_IDSEL  
Local bus address 20ÑLocal bus address bit 20 output pin. In the local address bus bit 14 is most  
signiÞcant and bit 31 is least signiÞcant.  
PCI initialization device selectÑ(Input). Used to select MPC8260Õs PCI interface during a PCI  
conÞguration cycle.  
L_A21  
PCI_PERR  
Local bus address 21ÑLocal bus address bit 21 output pin. In the local address bus bit 14 is most  
signiÞcant and bit 31 is least signiÞcant.  
PCI parity errorÑPCI data parity error input/output pin. Assertion of this pin indicates that a data  
parity error was detected during a PCI transfer (except for a special cycle).  
L_A22  
PCI_SERR  
Local bus address 22ÑLocal bus address bit 22 output pin. In the local address bus bit 14 is most  
signiÞcant and bit 31 is least signiÞcant.  
PCI system errorÑPCI system error input/output pin. Assertion of this pin indicates that a PCI  
system error was detected during a PCI transfer. The PCI system error is for reporting address  
parity errors, data parity errors on a special cycle command, or other catastrophic system errors.  
L_A23  
PCI_REQ0  
Local bus address 23ÑLocal bus address bit 23 output pin. In the local address bus bit 14 is most  
signiÞcant and bit 31 is least signiÞcant.  
PCI arbiter request 0ÑPCI request 0 input/output pin. When MPC8260Õs internal PCI arbiter is  
used, this is an input pin. In this mode assertion of this pin indicates that an external PCI agent is  
requesting the PCI bus. When an external PCI arbiter is used, this is an output pin. In this mode  
assertion of this pin indicates that MPC8260Õs PCI interface is requesting the PCI bus.  
MOTOROLA  
Chapter 6. External Signals  
6-9  
Part III.The Hardware Interface  
Table 6-1. External Signals (Continued)  
Signal  
Description  
L_A24  
PCI_REQ1  
Local bus address 24ÑLocal bus address bit 24 output pin. In the local address bus bit 14 is most  
signiÞcant and bit 31 is least signiÞcant.  
PCI arbiter request 1ÑPCI request 1 input pin. When MPC8260Õs internal PCI arbiter is used,  
assertion of this pin indicates that an external PCI agent is requesting the PCI bus.  
L_A25  
PCI_GNT0  
Local bus address 25ÑLocal bus address bit 25 output pin. In the local address bus bit 14 is most  
signiÞcant and bit 31 is least signiÞcant.  
PCI arbiter grant 0ÑPCI grant 0 input/output pin. When MPC8260Õs internal PCI arbiter is used,  
this is an output pin. In this mode, assertion of PCI_GNT0 indicates that an the external PCI agent  
that requested the PCI bus PCI_REQ0 is granted the bus. When an external PCI arbiter is used,  
this is an input pin. In this mode. assertion of PCI_GNT0 indicates that MPC8260Õs PCI interface is  
granted the PCI bus.  
L_A26  
PCI_GNT1  
Local bus address 26ÑLocal bus address bit 26 output pin. In the local address bus bit 14 is most  
signiÞcant and bit 31 is least signiÞcant.  
PCI arbiter grant 1ÑPCI grant 1 output pin. When MPC8260Õs internal PCI arbiter is used,  
assertion of PCI_GNT1 indicates that the external PCI agent that requested the PCI bus with  
PCI_REQ1 pin is granted the bus.  
L_A27  
CLKOUT  
Local bus address 27ÑLocal bus address bit 27 output pin. In the local address bus bit 14 is most  
signiÞcant and bit 31 is least signiÞcant.  
Clock OutÑClock output pin. In a PCI system where MPC8260Õs PCI interface is conÞgured to  
operate from an external PCI clock, the 60x bus clock is driven on CLKOUT. In a PCI system where  
the MPC8260Õs PCI interface is conÞgured to generate the PCI clock, the PCI clock is driven on  
CLKOUT. The PCI clock frequency range is 25Ð66 MHz.  
L_A28  
PCI_RST  
Local bus address 28ÑLocal bus address bit 28 output pin. In the local address bus bit 14 is most  
signiÞcant and bit 31 is least signiÞcant.  
CORE_SRESET PCI resetÑPCI reset input/output pin. When the MPC8260 is the host in the PCI system, PCI_RST  
is an output. When the MPC8260 is not the host of the PCI system, PCI_RST is an input.  
Core system resetÑThis is an input to the core. When this input pin is asserted the core branches  
to its reset vector.  
L_A29  
PCI_INTA  
Local bus address 29ÑLocal bus address bit 29 output pin. In the local address bus bit 14 is most  
signiÞcant and bit 31 is least signiÞcant.  
PCI INTAÑ(Input/output) When the MPC8260 is the host in the PCI system, this pin is an input for  
delivering PCI interrupts to the host. When the MPC8260 is not the host of the PCI system, this pin  
is an output used by the MPC8260 to signal an interrupt to the PCI host.  
L_A30  
Local bus address 30ÑLocal bus address bit 30 output pin. In the local address bus bit 14 is most  
signiÞcant and bit 31 is least signiÞcant.  
L_A31  
DLLSYNC  
Local bus address 31ÑLocal bus address bit 31 output pin. In the local address bus bit 14 is most  
signiÞcant and bit 31 is least signiÞcant.  
DLLSYNCÑDLL synchronization input. Used to eliminate skew for the clock driven on CLKOUT.  
LCL_D[0Ð31] Local bus dataÑLocal bus data input/output pins. In the local data bus bit 0 is most signiÞcant and  
PCI_AD[0Ð31] bit 31 is least signiÞcant.  
PCI address/dataÑPCI bus address/data input/output pins. During an address phase  
PCI_AD[0Ð31] contains a physical address, during data phase PCI_AD[0Ð31] contains the data  
bytes. In the PCI address/data bus, bit 31 is msb and bit 0 is lsb.  
6-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
Table 6-1. External Signals (Continued)  
Signal  
Description  
LCL_DP[0Ð3] Local bus data parityÑLocal bus data parity input/output pins. In local bus write operations the  
PCI_C/BE[0Ð3] MPC8260 drives these pins. In local bus read operations the accessed device drives these pins.  
LCL_DP[0] is driven with a value that gives odd parity with LCL_D[0Ð7]. LCL_DP[1] is driven with a  
value that gives odd parity with LCL_D[8Ð15]. LCL_DP[2] is driven with a value that gives odd parity  
with LCL_D[16Ð23]. LCL_DP[3] is driven with a value that gives odd parity with LCL_D[24Ð31].  
PCI command/byte enableÑPCI command/byte enable input/output pins. The MPC8260 drives  
these pins when it is the initiator of a PCI transfer. During an address phase the PCI_C/BE[0Ð3]  
deÞnes the command, during the data phase PCI_C/BE[0Ð3] deÞnes the byte enables.  
IRQ0  
NMI_OUT  
Interrupt request 0ÑThis input is one of the eight external lines that can request (by means of the  
internal interrupt controller) a service routine from the core.  
Non-maskable interrupt outputÑThis is an output driven from MPC8260Õs internal interrupt  
controller. Assertion of this output indicates that an unmasked interrupt is pending in MPC8260Õs  
internal interrupt controller.  
IRQ7  
INT_OUT  
APE  
Interrupt request 7ÑThis input is one of the eight external lines that can request (by means of the  
internal interrupt controller) a service routine from the core.  
Interrupt outputÑThis is an output driven from MPC8260Õs internal interrupt controller. Assertion of  
this output indicates that an unmasked interrupt is pending in MPC8260Õs internal interrupt  
controller.  
Address parity errorÑThis output pin will be asserted when the MPC8260 detects wrong parity  
driven on its address parity pins by an external master.  
TRST  
Test reset (JTAG)Ñ Input only. This is the reset input to MPC8260Õs JTAG/COP controller. See  
Section 12.1, ÒOverview,Ó and Section 12.6, ÒNonscan Chain Operation.Ó  
TCK  
TMS  
Test clock (JTAG)ÑInput only. Provides the clock input for MPC8260Õs JTAG/COP controller.  
Test mode select (JTAG)ÑInput only. Controls the state of MPC8260Õs JTAG/COP controller.  
Test data in (JTAG)ÑInput only. Data input to MPC8260Õs JTAG/COP controller.  
TDI  
TDO  
Test data out (JTAG)ÑOutput only. Data output from MPC8260Õs JTAG/COP controller.  
Three-stateÑAsserting TRIS forces all other MPC8260Õs pins to high impedance state.  
TRIS  
PORESET  
Power-on resetÑWhen asserted, this input line causes the MPC8260 to enter power-on reset  
state.  
HRESET  
SRESET  
QREQ  
Hard resetÑThis open drain line, when asserted causes the MPC8260 to enter hard reset state.  
Soft resetÑThis open drain line, when asserted causes the MPC8260 to enter the soft reset state.  
Quiescent requestÑ Output only. Indicates that MPC8260Õs internal core is about to enter its low  
power mode. In the MPC8260 this pin will be typically used for debug purposes.  
RSTCONF  
RSTCONF -ÑInput used during reset conÞguration sequence of the chip. Find detailed explanation  
of its function in Section 5.1.2, ÒPower-On Reset Flow,Ó and Section 5.4, ÒReset ConÞguration.Ó  
MODCK1  
AP[1]  
TC[0]  
MODCK1ÑClock mode input. DeÞnes the operating mode of internal clock circuits.  
Address parity 1Ñ(Input/output)The 60x master that drives the address bus, drives also the  
address parity signals.The value driven on address parity 1 pin should give odd parity (odd number  
of 1s) on the group of signals that includes address parity 1 and A[8Ð15].  
Transfer Code 0ÑThe transfer code output pins supply information that can be useful for debug  
purposes for each of the MPC8260Õs initiated bus transactions.  
BNKSEL[0]  
Bank Select 0ÑThe bank select outputs are used for selecting SDRAM bank when the MPC8260 is  
in 60x compatible bus mode.  
MOTOROLA  
Chapter 6. External Signals  
6-11  
Part III.The Hardware Interface  
Table 6-1. External Signals (Continued)  
Signal  
Description  
MODCK2  
AP[2]  
TC[1]  
MODCK2ÑClock mode input. DeÞnes the operating mode of internal clock circuits.  
Address parity 2Ñ(Input/output)The 60x master that drives the address bus, drives also the  
address parity signals.The value driven on address parity 2 pin should give odd parity (odd number  
of 1s) on the group of signals that includes address parity 2 and A[16Ð23].  
Transfer code 1ÑThe transfer code output pins supply information that can be useful for debug  
purposes for each of the MPC8260Õs initiated bus transactions.  
BNKSEL[1]  
Bank select 1ÑThe bank select outputs are used for selecting SDRAM bank when the MPC8260 is  
in 60x-compatible bus mode.  
MODCK3  
AP[3]  
TC[2]  
MODCK3ÑClock mode input. DeÞnes the operating mode of internal clock circuits.  
Address parity 3Ñ(Input/output)The 60x master that drives the address bus, drives also the  
address parity signals.The value driven on address parity 3 pin should give odd parity (odd number  
of 1s) on the group of signals that includes address parity 3 and A[24Ñ31].  
Transfer code 2ÑThe transfer code output pins supply information that can be useful for debug  
purposes for each of the MPC8260Õs initiated bus transactions.  
BNKSEL[2]  
Bank select 2ÑThe bank select outputs are used for selecting SDRAM bank when the MPC8260 is  
in 60x-compatible bus mode.  
XFC  
External Þlter capacitanceÑInput connection for an external capacitor Þlter for PLL circuitry.  
CLKIN  
Clock InÑPrimary clock input to MPC8260Õs PLL. In a PCI system, where the MPC8260 PCI  
interface is operated from the PCI bus clock, CLKIN should be connected to the PCI bus clock. In  
that case, the 60x bus clock is driven on CLKOUT.  
PA[0Ð31]  
PB[4Ð31]  
PC[0Ð31]  
PD[4Ð31]  
General-purpose I/O port A bits 0Ð31. See Chapter 35, ÒParallel I/O Ports.Ó  
General-purpose I/O port B bits 4Ð31. See Chapter 35, ÒParallel I/O Ports.Ó  
General-purpose I/O port C bits 0Ð31. See Chapter 35, ÒParallel I/O Ports.Ó  
General-purpose I/O port D bits 4Ð31. See Chapter 35, ÒParallel I/O Ports.Ó  
Power Supply VDDÑThis is the power supply of the internal logic.  
VDDHÑThis is the power supply of the I/O Buffers.  
VCCSYNÑThis is the power supply of the PLL circuitry.  
GNDSYNÑThis is a special ground of the PLL circuitry.  
VCCSYN1ÑThis is the power supply of the coreÕs PLL circuitry.  
Note that CPM port multiplexing is described in the Chapter 35, ÒParallel I/O Ports.Ó  
6-12  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Chapter 7  
60x Signals  
70  
70  
This chapter describes the MPC8260 PowerPC processorÕs external signals. It contains a  
concise description of individual signals, showing behavior when a signal is asserted and  
negated, when the signal is an input and an output, and the differences in how signals work  
in external-master or internal-only conÞgurations.  
NOTE  
A bar over a signal name indicates that the signal is active lowÐ  
for example, ARTRY (address retry) and TS (transfer start).  
Active-low signals are referred to as asserted (active) when  
they are low and negated when they are high. Signals that are  
not active-low, such as TSIZ[0Ð3] (transfer size signals) and  
TT[0Ð4] (transfer type signals) are referred to as asserted when  
they are high and negated when they are low.  
The 60x bus signals used with MPC8260 are grouped as follows:  
¥
Address arbitration signalsÑIn external arbiter mode, MPC8260 uses these signals  
to arbitrate for address bus mastership. The MPC8260 arbiter uses these signals to  
enable an external device to arbitrate for address bus mastership.  
¥
¥
¥
Address transfer start signalsÑThese signals indicate that a bus master has begun a  
transaction on the address bus.  
Address transfer signals (address bus)ÑThese signals are used to transfer the  
address.  
Transfer attribute signalsÑThese signals provide information about the type of  
transfer, such as the transfer size and whether the transaction is single, single  
extended, bursted, write-through or cache-inhibited.  
¥
¥
Address transfer termination signalsÑThese signals are used to acknowledge the  
end of the address phase of the transaction. They also indicate whether a condition  
exists that requires the address phase to be repeated.  
Data arbitration signalsÑThe MPC8260, in external arbiter mode, uses these  
signals to arbitrate for data bus mastership. The MPC8260 arbiter uses these signals  
to enable an external device to arbitrate for data bus mastership.  
MOTOROLA  
Chapter 7. 60x Signals  
7-1  
   
Part III.The Hardware Interface  
¥
¥
Data transfer signalsÑThese signals, which consist of the data bus, data parity, and  
data parity error signals, transfer the data and ensure its integrity.  
Data transfer termination signalsÑData termination signals are required after each  
data beat in a data transfer. In a single-beat transaction, the data termination signals  
also indicate the end of the tenure. For burst accesses or extended port-size accesses,  
the data termination signals apply to individual beats and indicate the end of the  
tenure only after the Þnal data beat.  
7.1 Signal ConÞguration  
Figure shows the grouping of the MPC8260Õs 60x bus signal conÞguration.  
NOTE  
The MPC8260 hardware speciÞcations provides a pinout  
showing pin numbers. These are shown in Figure 7-1.  
Bus Request (BR)  
Data Bus Grant (DBG)  
Data Bus Busy (DBB)  
1
1
1
1
1
Bus Grant (BG)  
Address  
Arbitration  
Data  
Arbitration  
Address Bus Busy (ABB)  
Transfer Start (TS)  
Address  
Start  
1
Data (D[0Ð63])  
64  
8
Address (A[0Ð31])  
Address Parity (AP[0Ð3])  
Address Parity Enable  
Data  
Transfer  
32  
4
Data Parity (DP[0Ð7])  
Address  
Bus  
1
Partial Data Valid Indication (PSDVAL)  
Transfer Acknowledge (TA)  
1
1
Transfer Type (TT[0Ð4])  
Transfer Code (TC[0Ð2])  
Transfer Burst (TBST)  
Transfer Size (TSIZ[0Ð3])  
Global (GBL)  
5
3
1
4
1
1
1
Data  
Termination  
Transfer Error Acknowledge (TEA)  
1
Transfer  
Attributes  
Cache Inhibit (CI)  
Write-Through (WT)  
Address Acknowledge (AACK)  
Address Retry (ARTRY)  
Reservation  
TLBI SYNC  
1
1
1
1
Address  
ermination  
Processor  
State  
Figure 7-1. PowerPC Signal Groupings  
7-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part III.The Hardware Interface  
7.2 Signal Descriptions  
This section describes individual MPC8260 60x signals, grouped according to Figure 7-1.  
Note that the following sections brießy summarize signal functions. Chapter 8, ÒThe 60x  
Bus,Ó describes many of these signals in greater detail, both in terms of their function and  
how groups of signals interact.  
7.2.1 Address Bus Arbitration Signals  
The address arbitration signals are a collection of input and output signals devices use to  
request address bus mastership, recognize when the request is granted, and indicate to other  
devices when mastership is granted. For a detailed description of how these signals interact,  
see Section 8.4.1, ÒAddress Arbitration.Ó  
Bus arbitration signals have no meaning in internal-only mode.  
7.2.1.1 Bus Request (BR)ÑOutput  
The bus request (BR) signal is both an input and an output signal on the MPC8260.  
7.2.1.1.1 Address Bus Request (BR)ÑOutput  
Following are the state meaning and timing comments for the BR signal output in external  
master mode.  
State Meaning  
AssertedÑIndicates that MPC8260 is requesting mastership of the  
address bus. Note that BR may be asserted for one or more cycles  
and then deasserted due to an internal cancellation of the bus request  
(for example, due to a load hit in the touch load buffer). See  
Section 8.4.1, ÒAddress Arbitration.Ó  
NegatedÑIndicates that the MPC8260 is not requesting the address  
bus. The MPC8260 may have no bus operation pending, it may be  
parked, or the ARTRY input was asserted on the previous bus clock  
cycle.  
Timing Comments AssertionÑMay occur on any cycle; does not occur if the MPC8260  
is parked and the address bus is idle (BG asserted and ABB input  
negated).  
NegationÑOccurs for at least one cycle following a qualiÞed BG  
even if another transaction is pending; also negated for at least one  
cycle following any qualiÞed ARTRY on the bus unless MPC8260  
asserted ARTRY and requires a snoop copyback; may also be  
negated if MPC8260 cancels the bus request internally before  
receiving a qualiÞed BG.  
High ImpedanceÑOccurs during a hard reset or checkstop condition  
MOTOROLA  
Chapter 7. 60x Signals  
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Part III.The Hardware Interface  
7.2.1.1.2 Address Bus Request (BR)ÑInput  
Following are the state meaning and timing comments for the BR signal input in external  
master mode.  
State Meaning  
AssertedÑIndicates that the external master has a bus transaction to  
perform and is waiting for a qualiÞed BG to begin the address tenure.  
BR may be asserted even if the two possible pipelined address  
tenures have already been granted.  
NegatedÑIndicates that the external master has no bus transaction to  
perform, or if the device is parked, that it is potentially ready to start  
a bus transaction on the next clock cycle (with proper qualiÞcation,  
see BG).  
Timing Comments AssertionÑMay occur on any cycle; does not occur if the external  
master is parked and the address bus is idle (BG asserted and ABB  
input negated).  
NegationÑOccurs for at least one cycle after a qualiÞed BG even if  
another transaction is pending; also negated for at least one cycle  
following any qualiÞed ARTRY on the bus unless this chip asserted  
the ARTRY and requires to perform a snoop copyback; may also be  
negated if the external master cancels a bus request internally before  
receiving a qualiÞed BG.  
High ImpedanceÑOccurs during a hard reset or checkstop  
condition.  
7.2.1.2 Bus Grant (BG)  
The address bus grant (BG) signal is both an input and an output signal.  
7.2.1.2.1 Bus Grant (BG)ÑInput  
The following are the state meaning and timing comments for the BG signal input in  
external master mode.  
State Meaning  
AssertedÑIndicates that the MPC8260 may, with the proper  
qualiÞcation, begin a bus transaction and assume ownership of the  
address bus. A qualiÞed bus grant is generally determined from the  
bus state as follows: QBG = BG ¥ ÂABB ¥ ÂARTRY where ARTRY  
is asserted only during the cycle after AACK. Note that the assertion  
of BR is not required for a qualiÞed bus grant (for bus parking).  
NegatedÑIndicates that the MPC8260 is not granted next address  
ownership.  
Timing Comments AssertionÑMay occur on any cycle. Once the MPC8260 has  
assumed address bus ownership, it does not begin checking for BG  
again until the cycle after AACK.  
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NegationÑMay occur whenever the MPC8260 must be prevented  
from using the address bus. The MPC8260 may still assume address  
bus ownership on the cycle BG is negated if it was asserted the  
previous cycle with other bus grant qualiÞcations.  
7.2.1.2.2 Bus Grant (BG)ÑOutput  
Following are the state meaning and timing comments for the BG signal output in external  
master mode.  
State Meaning  
AssertedÑIndicates that the external device may, with the proper  
qualiÞcation, begin a bus transaction and assume ownership of the  
address bus. A qualiÞed bus grant is generally determined from the  
bus state as follows: QBG = BG ¥ ÂABB ¥ ÂARTRY where ARTRY  
is asserted only during the cycle after AACK. Note that the assertion  
of BR is not required for a qualiÞed bus grant (for bus parking).  
NegatedÑIndicates that the external device is not granted next  
address ownership.  
Timing Comments AssertionÑMay occur on any cycle. Once the external device has  
assumed address bus ownership, it does not begin checking for BG  
again until the cycle after AACK.  
NegationÑMay occur when an external device must be kept from  
using the address bus. The external device may still assume address  
bus ownership on the cycle that BG is negated if it was asserted the  
previous cycle with other bus grant qualiÞcations.  
7.2.1.3 Address Bus Busy (ABB)  
The address bus busy (ABB) signal is both an input and an output signal.  
7.2.1.3.1 Address Bus Busy (ABB)ÑOutput  
Following are the state meaning and timing comments for the ABB output signal.  
State Meaning  
AssertedÑIndicates that the MPC8260 is the current address bus  
master. The MPC8260 may not assume address bus ownership in  
case a bus request is internally cancelled by the cycle a qualiÞed BG  
would have been recognized.  
NegatedÑIndicates that MPC8260 is not the current address bus  
master.  
Timing Comments AssertionÑOccurs the cycle after a qualiÞed BG is accepted by  
MPC8260 and remains asserted for the duration of the address  
tenure.  
Turn-Off SequencingÑNegates for a fraction of a bus cycle (1/2  
minimum, depends on clock mode) starting the cycle following the  
assertion of AACK. It then goes to the high impedance state.  
MOTOROLA  
Chapter 7. 60x Signals  
7-5  
     
Part III.The Hardware Interface  
7.2.1.3.2 Address Bus Busy (ABB)ÑInput  
Following are the state meaning and timing comments for the ABB input signal.  
State Meaning  
AssertedÑIndicates that external device is the address bus master.  
NegatedÑIndicates that the address bus may be available for use by  
the MPC8260 (see BG). The MPC8260 also tracks the state of ABB  
on the bus from the TS and AACK inputs. (See section on address  
arbitration phase.)  
Timing Comments AssertionÑMay occur whenever the MPC8260 must be prevented  
from using the address bus.  
NegationÑMay occur whenever the MPC8260 may use the address  
bus.  
7.2.2 Address Transfer Start Signal  
In the internal only mode the address transfer start signal has no meaning.  
Address transfer start signal are input and output signals that indicate that an address bus  
transfer has begun.  
7.2.2.1 Transfer Start (TS)  
The TS signal is both an input and an output signal on the MPC8260.  
7.2.2.1.1 Transfer Start (TS)ÑOutput  
Following are the state meaning and timing comments for the TS output signal.  
State Meaning  
AssertedÑIndicates that the MPC8260 has started a bus transaction  
and that the address bus and transfer attribute signals are valid. It is  
also an implied data bus request if the transfer attributes TT[0Ð4]  
indicate that a data tenure is required for the transaction.  
NegatedÑHas no special meaning during a normal transaction.  
Timing Comments Assertion/NegationÑDriven and asserted on the cycle after a  
qualiÞed BG is accepted by MPC8260; remains asserted for one  
clock only. Negated for the remainder of the address tenure.  
Assertion is coincident with the Þrst clock that ABB is asserted.  
High ImpedanceÑOccurs the cycle following the assertion of  
AACK (same cycle as ABB negation).  
7.2.2.2 Transfer Start (TS)ÑInput  
Following are the state meaning and timing comments for the TS input signal.  
State Meaning  
AssertedÑIndicates that another device has begun a bus transaction  
and that the address bus and transfer attribute signals are valid for  
snooping.  
NegatedÑHas no special meaning.  
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Timing Comments Assertion/NegationÑMust be asserted for one cycle only and then  
immediately negated. Assertion may occur at any time during the  
assertion of ABB.  
7.2.3 Address Transfer Signals  
In internal only mode the memory controller uses these signals for glueless address  
transfers to memory and I/O devices.  
The address transfer signals are used to transmit the address.  
7.2.3.1 Address Bus (A[0Ð31])  
The address bus (A[0Ð31]) consists of 32 signals that are both input and output signals.  
7.2.3.1.1 Address Bus (A[0Ð31])ÑOutput  
Following are the state meaning and timing comments for the A[0Ð31] output signals.  
State Meaning  
ContentÑSpeciÞes the physical address of the bus transaction. For  
burst or extended operations, the address is a double-word.  
Timing Comments Assertion/NegationÑDriven valid on the same cycle that TS is  
driven/asserted; remains driven/valid for the duration of the address  
tenure.  
High ImpedanceÑ Occurs the cycle following the assertion of  
AACK; no precharge action performed on release.  
7.2.3.1.2 Address Bus (A[0Ð31])ÑInput  
Following are the state meaning and timing comments for the A[0Ð31] input signals.  
State Meaning  
AssertedÑIndicates that another device has begun a bus transaction  
and that the address bus and transfer attribute signals are valid for  
snooping and in slave mode.  
NegatedÑHas no special meaning.  
Timing Comments Assertion/NegationÑMust be valid on the same cycle that TS is  
asserted; sampled by the processor only on this cycle.  
7.2.4 Address Transfer Attribute Signals  
In internal only mode the address transfer attribute signals have no meaning.  
The transfer attribute signals are a set of signals that further characterize the transferÑsuch  
as the size of the transfer, whether it is a read or write operation, and whether it is a burst  
or single-beat transfer. For a detailed description of how these signals interact, see  
Section 7.2.4, ÒAddress Transfer Attribute Signals.Ó  
MOTOROLA  
Chapter 7. 60x Signals  
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Part III.The Hardware Interface  
7.2.4.1 Transfer Type (TT[0Ð4])  
The transfer type signals (TT[0Ð4]) consist of Þve input/output signals on the MPC8260.  
For a complete description of TT[0Ð4] signals and transfer type encoding, see  
Section 8.4.3.1, ÒTransfer Type Signal (TT[0Ð4]) Encoding.Ó  
7.2.4.1.1 Transfer Type (TT[0Ð4])ÑOutput  
Following are the state meaning and timing comments for the TT[0Ð4] output signals on  
the MPC8260.  
State Meaning  
Asserted/NegatedÑSpeciÞes the type of transfer in progress.  
Timing Comments Assertion/NegationÑSame as A[0Ð31].  
High ImpedanceÑSame as A[0Ð31].  
7.2.4.1.2 Transfer Type (TT[0Ð4])ÑInput  
Following are the state meaning and timing comments for the TT[0Ð4] input signals on the  
MPC8260.  
State Meaning  
Asserted/NegatedÑSpeciÞes the type of transfer in progress for  
snooping by the MPC8260  
Timing Comments Assertion/NegationÑSame as A[0Ð31].  
7.2.4.2 Transfer Size (TSIZ[0Ð3])  
The transfer size (TSIZ[0Ð3]) signals consist of four input/output signals on the MPC8260,  
following are the state meaning and timing comments for the TSIZ[0Ð3] signals on the  
MPC8260.  
State Meaning  
Asserted/NegatedÑSpeciÞes the data transfer size for the  
transaction (see Section 8.4.3.3, ÒTBST and TSIZ[0Ð3] Signals and  
Size of TransferÓ). During graphics transfer operations, these signals  
form part of the Resource ID (see TBST).  
Timing Comments Assertion/NegationÑSame as A[0Ð31].  
High ImpedanceÑSame as A[0Ð31].  
7.2.4.3 Transfer Burst (TBST)  
The transfer burst (TBST) signal is an input/output signal on the MPC8260. Following are  
the state meaning and timing comments for the TBST output/input signal.  
State Meaning  
AssertedÑIndicates that a burst transfer is in progress (see  
Section 8.4.3.3, ÒTBST and TSIZ[0Ð3] Signals and Size of  
TransferÓ). During graphics transfer operations, this signal forms  
part of the Resource ID Þeld from the EAR as follows:  
TBST || TSIZ[0Ð3] = EAR[28Ð31]. (See TBST.)  
NegatedÑIndicates that a burst transfer is not in progress.  
Timing Comments Assertion/NegationÑSame as A[0Ð31].  
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High ImpedanceÑSame as A[0Ð31].  
7.2.4.4 Global (GBL)  
The global (GBL) signal is an input/output signal on the MPC8260.  
7.2.4.4.1 Global (GBL)ÑOutput  
Following are the state meaning and timing comments for the GBL output signal.  
State Meaning  
AssertedÑIndicates that the transaction is global and should be  
snooped by other devices. GBL reßects the M bit (WIM bits) from  
the MMU except during certain transactions.  
NegatedÑIndicates that the transaction is not global and should not  
be snooped by other devices.  
Timing Comments Assertion/NegationÑSame as A[0Ð31].  
High ImpedanceÑSame as A[0Ð31].  
7.2.4.4.2 Global (GBL)ÑInput  
Following are the state meaning and timing comments for the GBL input signal.  
State Meaning  
AssertedÑIndicates that a transaction must be snooped by  
MPC8260.  
NegatedÑIndicates that a transaction should not be snooped by  
MPC8260. (In addition, certain non-global transactions are snooped  
for reservation coherency.)  
Timing Comments Assertion/NegationÑSame as A[0Ð31].  
7.2.4.5 Caching-Inhibited (CI)ÑOutput  
The cache inhibit (CI) signal is an output signal on the MPC8260. Following are the state  
meaning and timing comments for CI.  
State Meaning  
AssertedÑIndicates that the transaction in progress should not be  
cached. CI reßects the I bit (WIM bits) from the MMU except during  
certain transactions.  
NegatedÑIndicates that the transaction should be cached.  
Timing Comments Assertion/NegationÑSame as A[0Ð31].  
High ImpedanceÑSame as A[0Ð31].  
7.2.4.6 Write-Through (WT)ÑOutput  
The write-through (WT) signal is an output signal on the MPC8260. Following are the state  
meaning and timing comments for WT.  
State Meaning  
AssertedÑIndicates that the transaction should operate in write-  
through mode. WT reßects the W bit (WIM bits) from the MMU  
except during certain transactions. WT may be asserted during read  
transactions.  
MOTOROLA  
Chapter 7. 60x Signals  
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Part III.The Hardware Interface  
NegatedÑIndicates that the transaction should not operate in write-  
through mode.  
Timing Comments Assertion/NegationÑSame as A[0Ð31].  
High ImpedanceÑSame as A[0Ð31].  
7.2.5 Address Transfer Termination Signals  
The address transfer termination signals are used to indicate either that the address phase  
of the transaction has completed successfully or must be repeated, and when it should be  
terminated. For detailed information about how these signals interact, see Section 7.2.5,  
ÒAddress Transfer Termination Signals.Ó  
The address transfer termination signals have no meaning in internal only mode.  
7.2.5.1 Address Acknowledge (AACK)  
The address acknowledge (AACK) signal is an input/output on the MPC8260.  
7.2.5.1.1 Address Acknowledge (AACK)ÑOutput  
.Following are the state meaning and timing comments for AACK as an output signal.  
State Meaning  
AssertedÑIndicates that the address tenure of a transaction is  
terminated. On the cycle following the assertion of AACK, the bus  
master releases the address-tenure-related signals to the high-  
impedance state and samples ARTRY.  
NegatedÑIndicates that the address bus and the transfer attributes  
must remain driven, if negated during ABB.  
Timing Comments AssertionÑOccurs a programmable number of clocks after TS or  
whenever ARTRY conditions are resolved.  
NegationÑOccurs one clock after assertion.  
7.2.5.1.2 Address Acknowledge (AACK)ÑInput  
Following are the state meaning and timing comments for AACK as an input signal.  
State Meaning  
AssertedÑIndicates that a 60x bus slave is terminating the address  
tenure. On the cycle following the assertion ofAACK, the bus master  
releases the address tenure related signals to the high-impedance  
state and samples ARTRY.  
NegatedÑIndicates that the address tenure must remain active and  
the address tenure related signals driven.  
Timing Comments AssertionÑOccurs during the 60x bus slave access, at least two  
clocks after TS.  
NegationÑOccurs one clock after assertion.  
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7.2.5.2 Address Retry (ARTRY)  
The address retry (ARTRY) signal is both an input and output signal on the MPC8260  
7.2.5.2.1 Address Retry (ARTRY)ÑOutput  
.Following are the state meaning and timing comments for ARTRY as an output signal.  
State Meaning  
AssertedÑIndicates that the MPC8260 detects a condition in which  
an address tenure must be retried. If the MPC8260 processor needs  
to update memory as a result of snoop that caused the retry, the  
MPC8260 asserts BR the second cycle after AACK if ARTRY is  
asserted.  
High ImpedanceÑIndicates that the MPC8260 does not need the  
address tenure to be retried.  
Timing Comments AssertionÑAsserted the third bus cycle following the assertion of  
TS if a retry is required.  
NegationÑOccurs the second bus cycle after the assertion ofAACK.  
Since this signal may be simultaneously driven by multiple devices,  
it negates in a unique fashion. First the buffer goes to high impedance  
for a minimum of one-half processor cycle (dependent on the clock  
mode), then it is driven negated for one bus cycle before returning to  
high impedance.  
7.2.5.2.2 Address Retry (ARTRY)ÑInput  
Following are the state meaning and timing comments for the ARTRY input.  
State Meaning  
AssertedÑIf the MPC8260 is the address bus master, ARTRY  
indicates that the MPC8260 must retry the preceding address tenure  
and immediately negate BR (if asserted). If the associated data  
tenure has started, the MPC8260 also aborts the data tenure  
immediately even if the burst data has been received. If the  
MPC8260 is not the address bus master, this input indicates that the  
MPC8260 should negate BR for one bus clock cycle immediately  
after external device assertsARTRY to permit a copy-back operation  
to main memory. Note that the subsequent address presented on the  
address bus may not be the one that generated the assertion of  
ARTRY.  
Negated/High ImpedanceÑIndicates that the MPC8260 does not  
need to retry the last address tenure.  
Timing Comments AssertionÑMay occur as early as the second cycle following the  
assertion of TS and must occur by the bus clock cycle immediately  
following the assertion of AACK if an address retry is required.  
NegationÑMust occur during the second cycle after the assertion of  
AACK.  
MOTOROLA  
Chapter 7. 60x Signals  
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Part III.The Hardware Interface  
7.2.6 Data Bus Arbitration Signals  
The data bus arbitration signals have no meaning in internal-only mode.  
Like the address bus arbitration signals, data bus arbitration signals maintain an orderly  
process for determining data bus mastership. Note that there is no data bus arbitration signal  
equivalent to the address bus arbitration signal BR (bus request), because, except for  
address-only transactions, TS implies data bus requests. For a detailed description on how  
these signals interact, see Section 8.5.1, ÒData Bus Arbitration.Ó  
7.2.6.1 Data Bus Grant (DBG)  
The data bus grant signal (DBG) is an output/input on the MPC8260  
7.2.6.1.1 Data Bus Grant (DBG)ÑInput  
DBG an input when MPC8260 is conÞgured to an external arbiter. The following are the  
state meaning and timing comments for DBG.  
State Meaning  
AssertedÑIndicates that the MPC8260 may, with the proper  
qualiÞcation, assume mastership of the data bus. The MPC8260  
derives a qualiÞed data bus grant when DBG is asserted and DBB  
and ARTRY are negated; that is, the data bus is not busy (DBB is  
negated), and there is no outstanding attempt to perform an ARTRY  
of the associated address tenure.  
NegatedÑIndicates that the MPC8260 must hold off its data tenures.  
Timing Comments AssertionÑMay occur any time to indicate the MPC8260 is free to  
take data bus mastership. It is not sampled until TS is asserted.  
NegationÑMay occur at any time to indicate the MPC8260 cannot  
assume data bus mastership.  
7.2.6.1.2 Data Bus Grant (DBG)ÑOutput  
DBG signal is output when the MPC8260 conÞgured to Internal Arbiter. Following are the  
state meaning and timing comments for the DBG signal.  
State Meaning  
AssertedÑIndicates that the external device may, with the proper  
qualiÞcation, assume mastership of the data bus.A qualiÞed data bus  
grant is deÞned as the assertion of DBG, negation of DBB, and  
negation of ARTRY. The requirement for the ARTRY signal is only  
for the address bus tenure associated with the data bus tenure about  
to be granted (that is, not for another address tenure available  
because of address pipelining).  
NegatedÑIndicates that an external device is not granted mastership  
of the data bus.  
Timing Comments AssertionÑOccurs on the Þrst clock in which the data bus is not  
busy and the processor has the highest priority outstanding data  
transaction.  
NegationÑOccurs one clock after assertion.  
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7.2.6.2 Data Bus Busy (DBB)  
The data bus busy (DBB) signal is both an input and output signal on the MPC8260  
7.2.6.2.1 Data Bus Busy (DBB)ÑOutput  
Following are the state meaning and timing comments for the DBB output signal.  
State Meaning  
AssertedÑIndicates that the MPC8260 is the data bus master. The  
MPC8260 always assumes data bus mastership if it needs the data  
bus and determines a qualiÞed data bus grant (see DBG).  
NegatedÑIndicates that the MPC8260 is not using the data bus.  
Timing Comments AssertionÑOccurs during the bus clock cycle following a qualiÞed  
DBG.  
NegationÑOccurs for a minimum of one-half bus clock cycle  
following the assertion of the Þnal TA following TEA or certain  
ARTRY cases.  
High ImpedanceÑOccurs after DBB is negated.  
7.2.6.2.2 Data Bus Busy (DBB)ÑInput  
Following are the state meaning and timing comments for the DBB input signal.  
State Meaning  
AssertedÑIndicates that another device is bus master.  
NegatedÑIndicates that the data bus is free (with proper  
qualiÞcation, see DBG) for use by the MPC8260.  
Timing Comments AssertionÑMust occur when the MPC8260 must be prevented from  
using the data bus.  
NegationÑMay occur whenever the data bus is available.  
7.2.7 Data Transfer Signals  
Data transfer signals are used in the same way in both internal only and external master  
modes. Like the address transfer signals, the data transfer signals are used to transmit data  
and to generate and monitor parity for the data transfer. For a detailed description of how  
data transfer signals interact, see Section 7.2.7, ÒData Transfer Signals.Ó  
7.2.7.1 Data Bus (D[0Ð63])  
The data bus (D[0Ð63]) states have the same meanings in both internal only mode external  
master mode. The data bus consists of 64 signals that are both inputs and outputs on the  
MPC8260. Following are the state meaning and timing comments for the data bus.  
State Meaning  
The data bus holds 8 byte lanes assigned as shown in Table 7-1.  
Timing Comments The number of times the data bus is driven depends on the transfer  
size, port size, and whether the transfer is a single-beat or burst  
operation.  
MOTOROLA  
Chapter 7. 60x Signals  
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7.2.7.1.1 Data Bus (D[0Ð63])ÑOutput  
Following are the state meaning and timing comments for the D[0Ð63] output signals.  
State Meaning  
Asserted/NegatedÑRepresents the state of data during a data write.  
Byte lanes not selected for data transfer do not supply valid data.  
MPC8260 duplicates data to enable valid data to be sent to different  
port sizes.  
Timing Comments Assertion/NegationÑInitial beat coincides with DBB, for bursts,  
transitions on the bus clock cycle following each assertion of TA and,  
for port size, transitions on the bus clock cycle following each  
assertion of PSDVAL.  
High ImpedanceÑOccurs on the bus clock cycle after the Þnal  
assertion of TA, TEA, or certain ARTRY cases.  
Table 0-1. Data Bus Lane Assignments  
Data Bus Signals  
Byte Lane  
D0ÐD7  
0
1
2
3
4
5
6
7
D8ÐD15  
D16ÐD23  
D24ÐD31  
D32ÐD39  
D40ÐD47  
D48ÐD55  
D56ÐD63  
7.2.7.1.2 Data Bus (D[0Ð63])ÑInput  
Following are the state meaning and timing comments for the D[0Ð63] input signals.  
State Meaning  
Asserted/NegatedÑRepresents the state of data during a data read  
transaction.  
Timing Comments Assertion/NegationÑData must be valid on the same bus clock cycle  
that TA and/or PSDVAL is asserted.  
7.2.7.2 Data Bus Parity (DP[0Ð7])  
The eight data bus parity (DP[0Ð7]) signals both output and input signals.  
7.2.7.2.1 Data Bus Parity (DP[0Ð7])ÑOutput  
Following are the state meaning and timing comments for the DP[0Ð7] output signals.  
State Meaning  
Asserted/NegatedÑRepresents odd parity for each of 8 bytes of data  
write transactions. Odd parity means that an odd number of bits,  
including the parity bit, are driven high. The signal assignments are  
listed in Table 7-1.  
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Table 7-1. DP[0Ð7] Signal Assignments  
Signal Name  
Data Bus Signal Assignments  
DP0  
DP1  
DP2  
DP3  
DP4  
DP5  
DP6  
DP7  
D[0Ð7]  
D[8Ð15  
D[16Ð23]  
D[24Ð31]  
D[32Ð39]  
D[40Ð47]  
D[48Ð55]  
D[56Ð63]  
Timing Comments Assertion/NegationÑThe same as the data bus.  
High ImpedanceÑThe same as the data bus.  
7.2.7.2.2 Data Bus Parity (DP[0Ð7])ÑInput  
Following are the state meaning and timing comments for the DP input signals.  
State Meaning  
Asserted/NegatedÑRepresents odd parity for each byte of read data.  
Parity is checked on all data byte lanes, regardless of the size of the  
transfer. Detected even parity causes a checkstop if data parity errors  
are enabled in the BCS[PAR_EN].  
Timing Comments Assertion/NegationÑThe same as D[0Ð63].  
7.2.8 Data Transfer Termination Signals  
Data termination signals are required after each data beat in a data transfer. Note that in a  
single-beat transaction that is not a port-size transfer, the data termination signals also  
indicate the end of the tenure. In burst or port size accesses, the data termination signals  
apply to individual beats and indicate the end of the tenure only after the Þnal data beat. For  
a detailed description of how these signals interact, see Section 8.5, ÒData Tenure  
Operations.Ó  
7.2.8.1 Transfer Acknowledge (TA)  
The transfer acknowledge (TA) signal is both input and output on the MPC8260.  
7.2.8.1.1 Transfer Acknowledge (TA)ÑInput  
Following are the state meaning and timing comments for the TA input signal.  
State Meaning  
AssertedÑIndicates that a single-beat data transfer completed  
successfully or that a data beat in a burst transfer completed  
successfully. Note that TA must be asserted for each data beat in a  
burst transaction. For more information, see Section 8.5.3, ÒData  
Bus Transfers and Normal Termination.Ó  
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NegatedÑ(During assertion of DBB) indicates that, until TA is  
asserted, the MPC8260 must continue to drive the data for the  
current write or must wait to sample the data for reads.  
Timing Comments AssertionÑMust not occur before AACK for the current transaction  
(if the address retry mechanism is to be used to prevent invalid data  
from being used by the MPC8260); otherwise, assertion may occur  
at any time during the assertion of DBB. The system can withhold  
assertion of TA to indicate that the MPC8260 should insert wait  
states to extend the duration of the data beat.  
NegationÑMust occur after the bus clock cycle of the Þnal (or only)  
data beat of the transfer. For a burst transfer, the system can assert TA  
for one bus clock cycle and then negate it to advance the burst  
transfer to the next beat and insert wait states during the next beat.  
(Note: when conÞgured for 1:1 clock mode and is performing a burst  
read into the data cache, the MPC8260 requires two wait states  
between the assertion of TS and the Þrst assertion of TA for that  
transaction, or one wait state for 1.5:1 clock mode.)  
7.2.8.1.2 Transfer Acknowledge (TA)ÑOutput  
Following are the state meaning and timing comments for TA as an output signal.  
State Meaning  
AssertedÑIndicates that the data has been latched for a write  
operation, or that the data is valid for a read operation, thus  
terminating the current data beat. If it is the last or only data beat, this  
also terminates the data tenure.  
NegatedÑIndicates that master must extend the current data beat  
(insert wait states) until data can be provided or accepted by the  
MPC8260.  
Timing Comments AssertionÑOccurs on the clock in which the current data transfer  
can be completed.  
NegationÑOccurs after the clock cycle of the Þnal (or only) data  
beat of the transfer. For a burst transfer, TA may be negated between  
beats to insert one or more wait states before the completion of the  
next beat.  
7.2.8.2 Transfer Error Acknowledge (TEA)  
The transfer error acknowledge (TEA) signal is both input and output on the MPC8260,  
This signal can be ignored if BCR[TEA_EN] is cleared.  
7.2.8.2.1 Transfer Error Acknowledge (TEA)ÑInput  
Following are the state meaning and timing comments for the TEA input signal.  
State Meaning  
AssertedÑIndicates that a bus error occurred. The assertion of TEA  
causes the negation/high impedance of DBB in the next clock cycle.  
However, data entering the MPC8260 internal memory resources  
such as GPRs or caches are not invalidated.  
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Part III.The Hardware Interface  
NegatedÑIndicates that no bus error was detected.  
Timing Comments AssertionÑMay be asserted while DBB is asserted and for the cycle  
after is TA is asserted during a read operation. TEA should be  
asserted for one cycle only.  
NegationÑTEA must be negated no later than the negation of DBB.  
7.2.8.2.2 Transfer Error Acknowledge (TEA)ÑOutput  
Following are the state meaning and timing comments for the TEA output.  
State Meaning  
AssertedÑIndicates that a bus error has occurred. Assertion of TEA  
terminates the transaction in progress; that is, asserting TA is  
unnecessary because it is ignored by the target device. An  
unsupported memory transaction, such as a direct-store access or a  
graphics read or write, causes the assertion of TEA (provided TEA  
is enabled and the address transfer matches the MPC8260 memory  
map).  
NegatedÑIndicates that no bus error was detected.  
Timing Comments AssertionÑOccurs on the Þrst clock after the bus error is detected.  
NegationÑOccurs one clock after assertion.  
7.2.8.3 Partial Data Valid Indication (PSDVAL)  
The partial data valid indication (PSDVAL) is both an input and output on the MPC8260  
7.2.8.3.1 Partial Data Valid (PSDVAL)ÑInput  
Following are the state meaning and timing comments for the PSDVAL input signal. Note  
that TA asserts with PSDVAL to indicate the termination of the current transfer and for each  
complete data beat in burst transactions.  
State Meaning  
AssertedÑIndicates that a beat data transfer completed successfully.  
Note that PSDVAL must be asserted for each data beat in a single  
beat, port size and burst transaction,. For more information, see  
Section 8.5.5, ÒPort Size Data Bus Transfers and PSDVAL  
Termination.Ó  
NegatedÑ(During DBB) indicates that, until PSDVAL is asserted,  
the MPC8260 must continue to drive the data for the current write or  
must wait to sample the data for reads.  
Timing Comments AssertionÑMust not occur before AACK for the current transaction  
(if the address retry mechanism is to be used to prevent invalid data  
from being used by the MPC8260); otherwise, assertion may occur  
at any time during the assertion of DBB. The system can withhold  
assertion of PSDVAL to indicate that the MPC8260 should insert  
wait states to extend the duration of the data beat.  
NegationÑMust occur after the bus clock cycle of the Þnal (or only)  
data beat of the transfer. For a burst and/or port size transfer, the  
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system can assert PSDVAL for one bus clock cycle and then negate  
it to insert wait states during the next beat. (Note: when the  
MPC8260 Processor is conÞgured for 1:1 clock mode and is  
performing a burst read into the data cache, the MPC8260 requires  
two wait state between the assertion of TS and the Þrst assertion of  
PSDVAL for that transaction, or 1 wait state for 1.5:1 clock mode.)  
7.2.8.3.2 Partial Data Valid (PSDVAL)ÑOutput  
Following are the state meaning and timing comments for PSDVAL as an output signal.  
State Meaning  
AssertedÑIndicates that the data has been latched for a write  
operation, or that the data is valid for a read operation, thus  
terminating the current data beat. If it is the last or only data beat, this  
also terminates the data tenure.  
NegatedÑIndicates that the master must extend the current data beat  
(insert wait states) until data can be provided or accepted by the  
MPC8260.  
Timing Comments AssertionÑOccurs on the clock in which the current data transfer  
can be completed.  
NegationÑOccurs after the clock cycle of the Þnal (or only) data  
beat of the transfer. For a burst transfer, PSDVAL may be negated  
between beats to insert one or more wait states before the completion  
of the next beat.  
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MOTOROLA  
 
Chapter 8  
The 60x Bus  
80  
80  
The 60x bus, which is used by PowerPC processors, provides ßexible support for the on-  
chip PowerPC MPC603 processor as well as other internal and external bus devices. The  
60x bus supports 32-bit addressing, a 64-bit data bus, and burst operations that transfer as  
many as 256 bits of data in a four-beat burst. The 60x data bus can be accessed in 8-, 16-,  
32-, and 64-bit data ports. The 60x bus supports accesses of 1, 2, 3, and 4 bytes, aligned or  
unaligned, on 4-byte (word) boundaries; it also supports 64-, 128-, 192-, and 256-bit  
accesses.  
The address and data buses support synchronous, one-level pipeline transactions. The 60x  
bus interface can be conÞgured to support both external and internal masters or internal  
masters only.  
8.1 Terminology  
Table 8-1 deÞnes terms used in this chapter.  
Table 8-1. Terminology  
Term  
Atomic  
DeÞnition  
A bus access that attempts to be part of a read-write operation to the same address uninterrupted  
by any other access to that address. The MPC8260 initiates the read and write separately, but  
signals the memory system that it is attempting an atomic operation. If the operation fails, status is  
kept so that MPC8260 can try again.  
Beat  
A single state on the MPC8260 interface that may extend across multiple bus cycles. (An MPC8260  
transaction can be composed of multiple address or data beats.)  
Burst  
A multiple-beat data transfer whose total size is typically equal to a cache block size (in MPC8260:  
32 bytes, or 4 data beats at 8 bytes per beat).  
Cache block  
Clean  
Flush  
The PowerPC architecture deÞnes the basic unit of coherency as a cache block, which can be  
considered the same thing as a cache line.  
An operation that causes a cache block to be written to memory if modiÞed, and then left in a valid,  
unmodiÞed state in the cache.  
An operation that causes a cache block to be invalidated in the cache, and its data, if modiÞed, to be  
written back to main memory.  
Kill  
An operation that causes a cache block to be invalidated in the cache without writing any modiÞed  
data to memory.  
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Part III.The Hardware Interface  
Table 8-1. Terminology (Continued)  
Term  
DeÞnition  
Lane  
A sub-grouping of signals within a bus. An 8-bit section of the address or data bus may be referred  
to as a byte lane for that bus.  
Master  
The device that owns the address or data bus, the device that initiates or requests the transaction.  
IdentiÞes a cache block The M state in a MESI or MEI protocol.  
ModiÞed  
Parking  
Granting potential bus mastership without requiring a bus request from that device. This eliminates  
the arbitration delay associated with the bus request.  
Pipelining  
Slave  
Initiating a bus transaction before the current one Þnishes. This involves running an address tenure  
for a new bus transaction before the data tenure for a current bus transaction completes.  
The device addressed by the master.The slave is identiÞed in the address tenure and is responsible  
for sourcing or sinking the requested data for the master during the data tenure.  
Snooping  
Monitoring addresses driven by a bus master to detect the need for coherency actions.  
Split-transaction A transaction with separate request and response tenures.  
Tenure  
The period of bus mastership. For MPC8260, there can be separate address bus tenures and data  
bus tenures.  
Transaction  
A complete exchange between two bus devices. A typical transaction is composed of an address  
tenure and a data tenure, which may overlap or occur separately from the address tenure. A  
transaction can minimally consist of an address tenure alone.  
8.2 Bus ConÞguration  
The 60x bus supports separate bus conÞgurations for internal masters and external bus  
masters.  
¥
¥
Single-MPC8260 bus mode connects external devices by using only the memory  
controller. This is described in Section 8.2.1, ÒSingle MPC8260 Bus Mode.Ó  
The 60x-compatible bus mode, described in Section 8.2.2, Ò60x-Compatible Bus  
Mode,Ó enables connections to other masters and 60x-bus slaves, such as an external  
L2 cache controller.  
The Þgures in the following sections show how the MPC8260 can be connected in these  
two conÞgurations.  
8.2.1 Single MPC8260 Bus Mode  
In single-MPC8260 bus mode, the MPC8260 is the only bus device in the system. The  
internal memory controller controls all devices on the external pins. Figure 8-1 shows the  
signal connections for single-MPC8260 bus mode.  
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MPC8260  
APE  
TS  
Latch &  
A[0Ð31]  
DRAM MUX  
I/O  
TT[0Ð4]  
TSIZ[0Ð3]  
TBST  
CI  
WT  
MEM  
GBL  
AACK  
ARTRY  
DBG  
D[0Ð63]  
DP[0Ð7]  
TA  
TEA  
Memory Control Signals  
Figure 8-1. Single MPC8260 Bus Mode  
Note that in single MPC8260 bus mode, the MPC8260 uses the address bus as a memory  
address bus. Slaves cannot use the 60x bus signals because the addresses have memory  
timing, not address tenure timing.  
8.2.2 60x-Compatible Bus Mode  
The 60x-compatible bus mode can include one or more potential external masters (for  
example, an L2 cache, an ASIC DMA, a high-end PowerPC processor, or a second  
MPC8260). When operating in a multiprocessor conÞguration, the MPC8260 snoops bus  
operations and maintains coherency between the primary caches and main memory.  
Figure 8-2 shows how an external processor is attached to the MPC8260.  
MOTOROLA  
Chapter 8. The 60x Bus  
8-3  
     
Part III.The Hardware Interface  
MPC8260  
APE  
TS  
BR  
BG  
TS  
A[0Ð31]  
AP[0Ð3]  
TT[0Ð4]  
TSIZ[0Ð3]  
TBST  
Latch  
I/O  
CI  
Latch &  
WT  
MEM  
DRAM MUX  
GBL  
AACK  
ARTRY  
DBG  
External Device  
Memory Control Signals  
D[0Ð63]  
BR  
BG  
DP[0Ð7]  
DBG  
TA  
TEA  
Figure 8-2. 60x-Compatible Bus Mode  
8.3 60x Bus Protocol Overview  
Typically, 60x bus accesses consist of address and data tenures, which in turn each consist  
of three phasesÑarbitration, transfer, and termination, as shown in Figure 8-3 The  
independence of the tenures is indicated by showing the data tenure overlap the next  
address tenure), which allows split-bus transactions to be implemented at the system level  
in multiprocessor systems. Figure 8-3 shows a data transfer that consists of a single-beat  
transfer of as many as 256 bits. Four-beat burst transfers of 32-byte cache blocks require  
data transfer termination signals for each beat of data. Note that the MPC8260 supports port  
sizes of 8, 16, 32, and 64 bits and requires the additional bus signal, PSDVAL, which is not  
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Part III.The Hardware Interface  
deÞned by the 60x bus speciÞcation. For more information, see Section 8.5.5, ÒPort Size  
Data Bus Transfers and PSDVAL Termination.Ó  
Data Tenure  
Arbitration  
1- or 4-Beat Transfer  
Termination  
Independent Address and Data Tenures  
Next Address Tenure  
Arbitration  
Transfer  
Termination  
Figure 8-3. Basic Transfer Protocol  
The basic functions of the address and data tenures are as follows:  
¥
Address tenure  
Ñ Arbitration:Address bus arbitration signals are used to request and grant address  
bus mastership.  
Ñ Transfer: After a device is granted address bus mastership, it transfers the  
address. The address signals and the transfer attribute signals control the address  
transfer.  
Ñ Termination: After the address transfer, the system acknowledges that the  
address tenure is complete or that it must be repeated, signalled by the assertion  
of the address retry signal (ARTRY).  
¥
Data tenure  
Ñ Arbitration:After the address tenure begins, the bus device arbitrates for data bus  
mastership.  
Ñ Transfer: After the device is granted data bus mastership, it samples the data bus  
for read operations or drives the data bus for write operations.  
Ñ Termination:Acknowledgment of a successful data transfer is required after each  
beat in a data transfer. In single-beat transactions, the data termination signals  
also indicate the end of the tenure. In burst or port-size accesses, data termination  
signals indicate the completion of individual beats and, after the Þnal data beat,  
the end of the tenure.  
8.3.1 Arbitration Phase  
The external bus design permits one device (either the MPC8260 or a bus-attached external  
device) to be granted bus mastership at a time. Bus arbitration can be handled either by an  
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external central bus arbiter or by the internal on-chip arbiter. In the latter case, the system  
is optimized for three external bus masters besides the MPC8260. The arbitration  
conÞguration (external or internal) is determined at system reset by sampling conÞguration  
pins. See Section 10.9, ÒExternal Master Support (60x-Compatible Mode),Ó for more  
information.  
The MPC8260 controls bus access through the bus request (BR) and bus grant (BG) signals.  
It determines the state of the address and data bus busy signals by monitoring DBG, TS,  
AACK, and TA, and it qualiÞes them with ABB and DBB.  
The following signals are used for address bus arbitration:  
¥
¥
BR (bus request)ÑA device asserts BR to request address bus mastership.  
BG (bus grant)ÑAssertion indicates that a bus device may, with proper  
qualiÞcation, assume mastership of the address bus. A qualiÞed bus grant occurs  
when BG is asserted while ABB and ARTRY are negated.  
¥
ABB (address bus busy)ÑA device asserts ABB to indicate it is the current address  
bus master. Note that if all devices assertAACK with TS and would normally negate  
ABB afterAACK is asserted, the devices can ignoreABB because the MPC8260 can  
internally generate ABB. The MPC8260Õs ABB, if enabled, must be tied to a pull-  
up resistor.  
The following signals are used for data bus arbitration:  
¥
DBG (data bus grant)ÑIndicates that a bus device can, with the proper qualiÞcation,  
assume data bus mastership.A qualiÞed data bus grant occurs when DBG is asserted  
while DBB and ARTRY are negated.  
¥
DBB (data bus busy)ÑAssertion by the device indicates that the device is the  
current data bus master. The device master always assumes data bus mastership if it  
needs the data bus and is given a qualiÞed data bus grant (see DBG). Note that if all  
devices assert DBB in conjunction with qualiÞed data bus grant and would normally  
negate DBB after the last TA is asserted, the devices can ignore DBB because the  
MPC8260 can generate DBB internally. The MPC8260Õs DBB signal, if enabled,  
must be tied to a pull-up resistor.  
The following is a summary of rules for arbitration:  
¥
¥
Preference among devices is determined at the request level. The MPC8260 supports  
eight levels of bus requests.  
When no bus device is requesting the address bus, the MPC8260 parks the device  
selected in the arbiter conÞguration register on the bus.  
For more information, see Section 4.3.2.2, Ò60x Bus Arbiter ConÞguration Register  
(PPC_ACR).Ó  
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8.3.2 Address Pipelining and Split-Bus Transactions  
The 60x bus protocol provides independent address and data bus capability to support  
pipelined and split-bus transaction system organizations. Address pipelining allows the  
next address tenure to begin before the current data tenure has Þnished. Although this  
ability does not inherently reduce memory latency, support for address pipelining and split-  
bus transactions can greatly improve effective bus/memory throughput. These beneÞts are  
most fully realized in shared-memory, multiple-master implementations where bus  
bandwidth is critical to system performance.  
External arbitration (as provided by the MPC8260) is required in systems in which multiple  
devices share the system bus. The MPC8260 uses the address acknowledge (AACK) signal  
to control pipelining. The MPC8260 supports both one- and zero-level bus pipelining. One-  
level pipelining is achieved by asserting AACK to the current address bus master and  
granting mastership of the address bus to the next requesting master before the current data  
bus tenure has completed. Two address tenures can occur before the current data bus tenure  
completes. The MPC8260 also supports non-pipelined accesses.  
8.4 Address Tenure Operations  
This section describes the three phases of the address tenureÑaddress bus arbitration,  
address transfer, and address termination.  
8.4.1 Address Arbitration  
Bus arbitration can be handled either by an external arbiter or by the internal on-chip  
arbiter. The arbitration conÞguration (external or internal) is chosen at system reset. For  
internal arbitration, the MPC8260 provides arbitration for the 60x address bus and the  
system is optimized for three external bus masters besides the MPC8260. The bus request  
(BR) for the external device is an external input to the arbiter. The bus grant signal for the  
external device (BG) is output to the external device.The BG signal asserted by MPC8260Õs  
on-chip arbiter is asserted one clock after the current master on the bus has asserted AACK;  
therefore, it can be called a qualiÞed BG. Assuming that all potential masters negate ABB  
one clock after receiving AACK, the device receiving BG can start the address tenure (by  
asserting TS) one clock after receiving BG. In addition to the external signals, there are  
internal request and grant signals for the MPC8260 processor, communications processor,  
refresh controller, and the PCI internal bridge. Bus accesses are prioritized, with  
programmable priority. When a MPC8260Õs internal master needs the 60x bus, it asserts the  
internal bus request along with the request level. The arbiter asserts the internal bus grant  
for the highest priority request.  
The MPC8260 supports address bus parking through the use of the parked master bits in  
the arbiter conÞguration register. The MPC8260 parks the address bus (asserts the address  
bus grant signal in anticipation of an address bus request) to the external master or internal  
masters. When a device is parked, the arbiter can hold BG asserted for a device even if that  
device has not requested the bus. Therefore, when the parked device needs to perform a bus  
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Chapter 8. The 60x Bus  
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transaction, it skips the bus request delay and assumes address bus mastership on the next  
cycle. For this case, BR is not asserted and the access latency seen by the device is  
shortened by one cycle.  
The MPC8260 and external device bus devices qualify BG by sampling ARTRY in the  
negated state prior to taking address bus mastership. The negation of ARTRY during the  
address retry window (one cycle after the assertion of AACK) indicates that no address  
retry is requested. If a device detects ARTRY asserted, it cannot accept a address bus grant  
during the ARTRY cycle or the cycle following. A device that asserts ARTRY due to a  
modiÞed cache block hit, for example, asserts its bus request during the cycle after the  
assertion of ARTRY and assumes bus mastership for the cache block push when it is given  
a bus grant.  
The series of address transfers in Figure 8-4 shows the transfer protocol when the  
MPC8260 is conÞgured in 60x-compatible bus mode. In this example, MPC8260 is initially  
parked on the bus with BG INT-asserted (note that BG INT is an internal signal not seen by  
the user at the pins), which lets it start an address bus tenure by asserting TS. During the  
same clock cycle, the external masterÕs bus request is asserted to request access to the 60x  
bus, thereby causing the negation of BG INT internally and the assertion of BG at the pin.  
Following MPC8260Õs address tenure, the external master takes the bus and initiates its  
address transaction. The on-chip arbiter samples BR during the clock cycle in whichAACK  
is asserted; if BR is not asserted (no pending request), it negates BG and asserts the parked  
bus grant (BG_INT in this example).  
The master can assert BR and receive a qualiÞed bus grant without subsequently using the  
bus. It can negate (cancel) BR before accepting a qualiÞed bus grant. This can occur when  
a replacement copyback transaction waiting to be run on the bus is killed by a snoop of  
another bus master. This can also occur when the reservation set by a pending stwcx.  
transaction is cancelled by a snoop of another master. In both cases, the pending transaction  
by the processor is cancelled and BR is negated.  
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Part III.The Hardware Interface  
CLKOUT  
BR INT  
BG INT  
BR  
MPC8260  
BG  
ABB  
MPC8260  
External  
External  
ADDR+  
TS  
AACK  
ARTRY  
Figure 8-4. Address Bus Arbitration with External Bus Master  
8.4.2 Address Pipelining  
The MPC8260 supports one-level address pipelining by asserting AACK to the current bus  
master when its data tenure starts and by granting the address bus to the next requesting  
device before the current data bus tenure completes. Address pipelining improves data  
throughput by allowing the memory-control hardware to decode a new set of address and  
control signals while the current data transaction Þnishes. The MPC8260 pipelines data bus  
operations in strict order with the associated address operations. Figure 8-5 shows how  
address pipelining allows address tenures to overlap the associated data tenures.  
MOTOROLA  
Chapter 8. The 60x Bus  
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Part III.The Hardware Interface  
CLKOUT  
ADDR + ATTR  
TS  
AACK  
DBG  
TA  
Address  
Tenure  
Address 1  
Address 2  
Data Tenure  
Data 1  
Data 2  
Figure 8-5. Address Pipelining  
8.4.3 Address Transfer Attribute Signals  
During the address transfer, the address is placed on the address signals, A[0Ð31]. The bus  
master provides other signals that characterize the address transferÑtransfer type (TT[0Ð  
4]), transfer code (TC[0Ð2]), transfer size (TSIZ[0Ð3]), and transfer burst (TBST) signals.  
These signals are discussed in the following sections.  
8.4.3.1 Transfer Type Signal (TT[0Ð4]) Encoding  
The transfer type signals deÞne the nature of the transfer requested. They indicate whether  
the operation is an address-only transaction or whether both address and data are to be  
transferred. Table 8-2 describes the MPC8260Õs action as master, slave, and snooper.  
Table 8-2. Transfer Type Encoding  
MPC8260 as  
Snooper  
2
60x Bus SpeciÞcation  
MPC8260 as Bus Master  
MPC8260 as Slave  
1
TT[0Ð4]  
Command Transaction  
Bus Trans.  
Transaction Source Action on Hit Action on Slave Hit  
00000 Clean block Address  
only  
Address only (if dcbst (if enabled)  
enabled)  
Notapplicable AACK asserted;  
to MPC8260 MPC8260 takes no  
further action.  
00100 Flush block Address  
only  
Address only (if dcbf (if enabled)  
enabled)  
Notapplicable AACK is asserted;  
to MPC8260 MPC8260 takes no  
further action.  
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Part III.The Hardware Interface  
Table 8-2. Transfer Type Encoding (Continued)  
MPC8260 as  
Snooper  
2
60x Bus SpeciÞcation  
MPC8260 as Bus Master  
MPC8260 as Slave  
1
TT[0Ð4]  
Command Transaction  
Bus Trans.  
Transaction Source Action on Hit Action on Slave Hit  
01000 sync  
Address  
only  
Address only (if sync (if enabled)  
enabled)  
Notapplicable Assert AACK. BG is  
to MPC8260 negated until  
MPC8260 buffers are  
ßushed.  
01100 Kill block  
10000 eieio  
Address  
only  
Address only  
dcbz or dcbi (if  
enabled)  
Flush, cancel AACK is asserted.  
reservation  
Address  
only  
Address only (if eieio (if enabled)  
enabled)  
Notapplicable Assert AACK. BG is  
to MPC8260 negated until  
MPC8260 buffers are  
ßushed.  
101 00 Graphics  
write  
Single-beat Single-beat  
ecowx  
Notapplicable No action.  
to MPC8260  
write  
write (non-  
GLB)  
11000 TLB  
invalidate  
Address  
only  
Not applicable Not applicable to  
Notapplicable AACK is asserted;  
to MPC8260 MPC8260 takes no  
further action.  
to MPC8260  
MPC8260  
11100 Graphics  
read  
Single-beat Single-beat  
eciwx  
Notapplicable MPC8260 takes no  
to MPC8260 action.  
read  
read (non-GBL)  
00001 lwarx  
Address  
Not applicable Not applicable to  
Notapplicable Address-only  
to MPC8260 operation. AACK is  
asserted; MPC8260  
reservation only  
set  
to MPC8260  
MPC8260  
takes no further action.  
00101 Reserved  
01001 tlbsync  
Ñ
Not applicable Not applicable to  
to MPC8260 MPC8260  
Notapplicable Illegal  
to MPC8260  
Address  
only  
Not applicable Not applicable to  
to MPC8260 MPC8260  
Notapplicable Address-only  
to MPC8260 operation. AACK is  
asserted; MPC8260  
takes no further action.  
01101 icbi  
Address  
only  
Not applicable Not applicable to  
to MPC8260 MPC8260  
Notapplicable Address-only  
to MPC8260 operation. AACK is  
asserted; MPC8260  
takes no further action.  
1XX01 Reserved  
for customer  
Ñ
Not applicable Not applicable to  
to MPC8260 MPC8260  
Notapplicable Illegal  
to MPC8260  
00010 WR w/ßush Single-beat Single-beat  
CI, WT store, or non- Flush, cancel Write, assert AACK  
write or  
Burst  
write  
processor master  
under  
reservation  
and TA.  
00110 WR w/Kill  
01010 Read  
Burst  
Burst (non-  
GLB)  
Castout, ca-op push, Kill, cancel  
Write, assert AACK  
and TA.  
or snoop copyback  
reservation  
Single-beat Single-beat  
read or burst read  
CI load, CI I-fetch or  
nonprocessor master  
Clean or ßush Read, assert AACK  
and TA.  
MOTOROLA  
Chapter 8. The 60x Bus  
8-11  
Part III.The Hardware Interface  
Table 8-2. Transfer Type Encoding (Continued)  
MPC8260 as  
Snooper  
2
60x Bus SpeciÞcation  
MPC8260 as Bus Master  
MPC8260 as Slave  
1
TT[0Ð4]  
Command Transaction  
Bus Trans.  
Burst  
Transaction Source Action on Hit Action on Slave Hit  
01110 Read with  
intent to  
modify  
Burst  
Load miss, store miss, Flush  
or I-fetch  
Read, assert AACK  
and TA.  
10010 WR w/ßush Single-beat Single-beat  
stwcx  
Flush, cancel Write, assert AACK  
reservation and TA  
atomic  
write  
write  
10110 Reserved  
Not  
Not applicable Not applicable to  
Notapplicable Illegal  
to MPC8260  
applicableto to MPC8260  
MPC8260  
MPC8260  
11010 Read  
atomic  
Single-beat Single-beat  
read or burst read  
lwarx (CI load)  
lwarx (load miss)  
Clean or ßush Read, assert AACK  
and TA  
11110 Read with  
intent to  
modify  
Burst  
Burst  
Flush  
Read, assert AACK  
and TA  
atomic  
00011 Reserved  
00111 Reserved  
01011 Read with  
Ñ
Ñ
Not applicable Not applicable to  
to MPC8260 MPC8260  
Notapplicable Illegal  
to MPC8260  
Not applicable Not applicable to  
to MPC8260 MPC8260  
Notapplicable Illegal  
to MPC8260  
Single-beat Not applicable Not applicable to  
Clean  
Read, assert AACK  
and TA  
no intent to read or burst to MPC8260  
cache  
MPC8260  
01111 Reserved  
Ñ
Ñ
Not applicable Not applicable to  
Notapplicable Illegal  
to MPC8260  
to MPC8260  
MPC8260  
1XX11 Reserved  
for customer  
Not applicable Not applicable to  
to MPC8260 MPC8260  
Notapplicable Illegal  
to MPC8260  
1
2
TT1 can be interpreted as a read-versus-write indicator for the bus.  
This column speciÞes the TT encoding for the general 60x protocol. The processor generates or snoops only a  
subset of those encodings.  
Note the following regarding Table 8-2:  
¥
For reads, the processor cleans or ßushes during a snoop based on the TBST input.  
The processor cleans for single-beat reads (TBST negated) to emulate read-with-no-  
intent-to-cache operations.  
¥
Castouts and snoop copybacks are generally marked as non-global and are not  
snooped (except for reservation monitoring). However, other masters performing  
DMA write operations with the same TT encoding and marked as a global WR  
operation (whether global or non-global) will cancel an active reservation during a  
snoop hit in the reservation register (independent of a snoop hit in the cache).  
¥
A non-processor read can cause the internal processor to invalidate the  
corresponding cache line if it exists.  
8-12  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
8.4.3.2 Transfer Code Signals TC[0Ð2]  
The transfer code signals, TC[0Ð2], provide supplemental information about the  
corresponding address (mainly regarding the source of the transaction). Note that TCx  
signals can be used with the TT[0Ð4] and TBST to further deÞne the current transaction.  
Table 8-3 Transfer Code Encoding  
TC[0Ð2]  
Read  
Write  
000  
001  
010  
011  
100  
101  
110  
111  
Core data transaction  
Core touch load  
Core instruction fetch  
Reserved  
Any write  
Ñ
Ñ
Ñ
Reserved  
Reserved  
DMA function code 0  
DMA function code 1  
8.4.3.3 TBST and TSIZ[0Ð3] Signals and Size of Transfer  
As shown in Table 8-4, the transfer size signals (TSIZ[0Ð3]) and the transfer burst signal  
(TBST) together indicate the size of the requested data transfer. These signals can be used  
with address bits A[27Ð31] and the device port size to determine which portion of the data  
bus contains valid data for a write transaction or which portion of the bus should contain  
valid data for a read transaction.  
The MPC8260 uses four double-word burst transactions for transferring cache blocks. For  
these transactions, TSIZ[0Ð3] are encoded as 0b0010, and address bits A[27Ð28] determine  
which double-word is sent Þrst.  
The MPC8260 supports critical-word-Þrst burst transactions (double-word-aligned) from  
the processor. The MPC8260 transfers the critical double word of data Þrst, followed by the  
double words from increasing addresses, wrapping back to the beginning of the eight-word  
block as required.  
Table 8-4. Transfer Size Signal Encoding  
TBST  
TSIZ[0Ð3]  
Transfer Size  
Comments  
Source  
Negated  
Negated  
Negated  
Negated  
Negated  
Negated  
0 0 0 1  
0 0 1 0  
0 0 1 1  
0 1 0 0  
0 1 0 1  
0 1 1 0  
1 Byte  
2 Bytes  
3 Bytes  
4 Bytes  
5 Bytes  
6 Bytes  
Byte  
Core and DMA  
Half-word  
Ñ
Core and DMA  
Core and DMA  
Word  
Core and DMA  
Extended 5 bytes  
Extended 6 bytes  
SDMA (MPC8260 only)  
SDMA (MPC8260 only)  
MOTOROLA  
Chapter 8. The 60x Bus  
8-13  
               
Part III.The Hardware Interface  
Table 8-4. Transfer Size Signal Encoding (Continued)  
TBST  
TSIZ[0Ð3]  
Transfer Size  
Comments  
Extended 7 bytes  
Source  
Negated  
Negated  
Negated  
Negated  
Asserted  
0 1 1 1  
0 0 0 0  
1 0 0 1  
1 0 1 0  
0 0 1 0  
7 Bytes  
8 Bytes  
SDMA (MPC8260 only)  
Core and DMA  
Double-word (maximum data bus size)  
Extended double double-word  
Extended triple double-word  
16 Bytes  
24 Bytes  
32 bytes  
SDMA (MPC8260 only)  
SDMA (MPC8260 only)  
Quad double-word (4 maximum data beats) Core and DMA  
Note that the basic coherency size of the bus is 32 bytes for the processor (cache-block  
size). Data transfers that cross an aligned 32-byte boundary must present a new address  
onto the bus at that boundary for proper snoop operation, or must operate as non-coherent  
with respect to the MPC8260.  
8.4.3.4 Burst Ordering During Data Transfers  
During burst transfers, 32 bytes of data (one cache block) are transferred to or from the  
cache. Burst write transfers are performed zero double-word-Þrst. However, because burst  
reads are performed critical-double-word-Þrst, a burst-read transfer may not start with the  
Þrst double word of the cache block and the cache-block-Þll operation may wrap around  
the end of the cache block. Table 8-5 describes MPC8260 burst ordering.  
Table 8-5. Burst Ordering  
Double-Word Starting Address:  
Data Transfer  
1
A[27Ð28] = 00  
A[27Ð28] = 01  
A[27Ð28] = 10  
A[27Ð28] = 11  
2
1st data beat  
2nd data beat  
3rd data beat  
4th data beat  
DW0  
DW1  
DW2  
DW3  
DW0  
DW2  
DW3  
DW0  
DW1  
DW3  
DW0  
DW1  
DW2  
DW1  
DW2  
DW3  
1
2
A[27Ð28] speciÞes the Þrst double word of the 32-byte block being transferred; any subsequent double words must  
wrap-around the block. A[29Ð31] are always 0b000 for burst transfers by the MPC8260.  
DWx represents the double word that would be addressed by A[27Ð28] = x if a nonburst transfer were performed.  
Each data beat is terminated with an assertion of TA.  
8.4.3.5 Effect of Alignment on Data Transfers  
Table 8-6 lists the aligned transfers that can occur to and from the MPC8260. These are  
transfers in which the data is aligned to an address that is an integer multiple of the size of  
the data. For example, Table 8-6 shows that 1-byte data is always aligned; however, a 4-byte  
word must reside at an address that is a multiple of 4 to be aligned.  
In Figure 8-6, Table 8-8, and Table 8-9, OP0 is the most-signiÞcant byte of a word operand  
and OP7 is the least-signiÞcant byte.  
8-14  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part III.The Hardware Interface  
Table 8-6. Aligned Data Transfers  
Data Bus Byte Lanes  
...D31 D32...  
B3 B4  
Program Transfer  
Size  
TSIZ[0Ð3]  
A[29Ð31]  
D0...  
B0  
...D63  
B7  
B1  
B2  
B5  
B6  
1
2
Byte  
0 0 0 1  
0 0 0 1  
0 0 0 1  
0 0 0 1  
0 0 0 1  
0 0 0 1  
0 0 0 1  
0 0 0 1  
0 0 1 0  
0 0 1 0  
0 0 1 0  
0 0 1 0  
0 1 0 0  
0 1 0 0  
0 0 0 0  
0 0 0  
0 0 1  
0 1 0  
0 1 1  
1 0 0  
1 0 1  
1 1 0  
1 1 1  
0 0 0  
0 1 0  
1 0 0  
1 1 0  
0 0 0  
1 0 0  
0 0 0  
OP0  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP1  
Ñ
Ñ
OP2  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP3  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP4  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP5  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP6  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP7  
Ñ
Half-Word  
OP0 OP1  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP2 OP3  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP4 OP5  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP6 OP7  
Word  
OP0 OP1 OP2 OP3  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP4 OP5 OP6 OP7  
Double-Word  
OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7  
1
OPn: These lanes are read or written during that bus transaction. OP0 is the most-signiÞcant byte of a word  
operand and OP7 is the least-signiÞcant byte.  
2
Ñ: These lanes are ignored during reads and driven with undeÞned data during writes.  
The MPC8260 supports misaligned memory operations, although they may degrade  
performance substantially. A misaligned memory address is one that is not aligned to the  
size of the data being transferred (such as, a word read from an odd byte address). The  
MPC8260Õs processor bus interface supports misaligned transfers within a word (32-bit  
aligned) boundary, as shown in Table 8-7. Note that the 4-byte transfer in Table 8-7 is only  
one example of misalignment. As long as the attempted transfer does not cross a word  
boundary, the MPC8260 can transfer the data to the misaligned address within a single bus  
transfer (for example, a half-word read from an odd byte-aligned address). It takes two bus  
transfers to access data that crosses a word boundary.  
Due to the performance degradation, misaligned memory operations should be avoided. In  
addition to the double-word straddle boundary condition, the processorÕs address  
translation logic can generate substantial exception overhead when the load/store multiple  
and load/store string instructions access misaligned data. It is strongly recommended that  
MOTOROLA  
Chapter 8. The 60x Bus  
8-15  
 
Part III.The Hardware Interface  
software attempt to align code and data where possible.  
Table 8-7. Unaligned Data Transfer Example (4-Byte Example)  
Data Bus Byte Lanes  
...D31 D32...  
B3 B4  
Program Size of  
Word (4 bytes)  
TSIZ[1Ð3]  
A[29Ð31]  
D0...  
B0  
...D63  
B7  
B1  
B2  
B5  
B6  
1
2
Aligned  
1 0 0  
0 1 1  
0 0 1  
0 1 0  
0 1 0  
0 0 1  
0 1 1  
1 0 0  
0 1 1  
0 0 1  
0 1 0  
0 1 0  
0 0 1  
0 1 1  
0 0 0  
0 0 1  
1 0 0  
0 1 0  
1 0 0  
0 1 1  
1 0 0  
1 0 0  
1 0 1  
0 0 0  
1 1 0  
0 0 0  
1 1 1  
0 0 0  
A
A
A
A
Ñ
Ñ
Ñ
Ñ
Ñ
A
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
A
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
A
MisalignedÑ1st access  
2nd access  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
A
A
A
A
Ñ
A
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
A
Ñ
A
Ñ
A
MisalignedÑ1st access  
2nd access  
Ñ
A
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
A
Ñ
A
MisalignedÑ1st access  
2nd access  
Ñ
A
Ñ
A
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Aligned  
A
A
A
MisalignedÑ1st access  
2nd access  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
A
A
A
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
A
Ñ
A
MisalignedÑ1st access  
2nd access  
Ñ
A
Ñ
Ñ
Ñ
Ñ
A
MisalignedÑ1st access  
2nd access  
Ñ
A
Ñ
A
Ñ
1
A: Byte lane used  
2
Ñ: Byte lane not used  
8.4.3.6 Effect of Port Size on Data Transfers  
The MPC8260 can transfer operands through its 64-bit data port. If the transfer is controlled  
by the internal memory controller, the MPC8260 can support 8-, 16-, 32-, and 64-bit data  
port sizes. The bus requires that the portion of the data bus used for a transfer to or from a  
particular port size be Þxed. A 64-bit port must reside on data bus bits D[0Ð63], a 32-bit  
port must reside on bits D[0Ð31], a 16-bit port must reside on bits D[0Ð15], and an 8-bit  
port must reside on bits D[0Ð7]. The MPC8260 always tries to transfer the maximum  
amount of data on all bus cycles: for a word operation, it always assumes the port is 64 bits  
wide when beginning the bus cycle; for burst and extended byte cycles, a 64-bit bus is  
assumed.  
Figure 8-6 shows the device connections on the data bus. Table 8-8 lists the bytes required  
on the data bus for read cycles.  
8-16  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part III.The Hardware Interface  
Interface Output Register  
63  
0
31  
OP0  
OP1  
OP2  
OP3  
OP4  
OP5  
OP6  
OP7  
D[0Ð7]  
D[8Ð15]  
D[15Ð23]  
D[24Ð31]  
OP3  
D[32Ð39]  
OP4  
D[40Ð47]  
D[48Ð55]  
OP6  
D[56Ð63]  
OP0  
OP1  
OP2  
OP5  
OP7  
64-Bit Port Size  
OP0  
OP4  
OP1  
OP5  
OP2  
OP6  
OP3  
OP7  
32-Bit Port Size  
OP0  
OP2  
OP4  
OP6  
OP1  
OP3  
OP5  
OP7  
16-Bit Port Size  
OP0  
OP7  
8-Bit Port Size  
Figure 8-6. Interface to Different Port Size Devices  
MOTOROLA  
Chapter 8. The 60x Bus  
8-17  
   
Part III.The Hardware Interface  
Table 8-8. Data Bus Requirements For Read Cycle  
Port Size/Data Bus Assignments  
32-Bit  
0Ð7 8Ð15 16Ð23 24Ð31 32Ð39 40Ð47 48Ð55 56Ð63 0Ð7 8Ð15 16Ð23 24Ð31 0Ð7 8Ð15 0Ð7  
Transfer Address  
1
Size  
State  
64-Bit  
16-Bit 8-Bit  
TSIZ[0Ð3] A[29Ð31]  
2
3
Byte  
(0001)  
000  
001  
010  
011  
100  
101  
110  
111  
000  
001  
010  
100  
101  
110  
000  
001  
100  
101  
000  
100  
000  
OP0  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP0  
Ñ
Ñ
OP1  
Ñ
Ñ
Ñ
Ñ
Ñ
OP0  
Ñ
Ñ
OP0  
OP1 OP1  
OP2  
OP3 OP3  
OP4  
OP5 OP5  
OP6  
OP7 OP7  
Ñ
OP1  
Ñ
Ñ
OP2  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP2  
Ñ
Ñ
OP2  
Ñ
Ñ
Ñ
Ñ
OP3  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP3  
Ñ
Ñ
Ñ
Ñ
OP4  
Ñ
Ñ
Ñ
Ñ
OP4  
Ñ
Ñ
Ñ
OP4  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP5  
Ñ
Ñ
Ñ
OP5  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP6  
Ñ
Ñ
Ñ
OP6  
Ñ
Ñ
OP6  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP7  
Ñ
Ñ
Ñ
OP7  
Ñ
Half Word  
(0010)  
OP0 OP1  
Ñ
Ñ
Ñ
Ñ
Ñ
OP0 OP1  
Ñ
OP0 OP1 OP0  
OP1 OP1  
Ñ
Ñ
Ñ
Ñ
Ñ
OP1 OP2  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP1 OP2  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP2 OP3  
Ñ
Ñ
Ñ
Ñ
Ñ
OP2 OP3 OP2 OP3 OP2  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP4 OP5  
Ñ
Ñ
OP4 OP5  
Ñ
Ñ
Ñ
OP4 OP5 OP4  
OP5 OP5  
Ñ
Ñ
Ñ
Ñ
OP5 OP6  
Ñ
Ñ
Ñ
OP5 OP6  
Ñ
Ñ
Ñ
Ñ
OP6 OP7  
Ñ
OP6 OP7 OP6 OP7 OP6  
OP0 OP1 OP0  
OP1 OP1  
OP4 OP5 OP4  
OP5 OP5  
OP0 OP1 OP2 OP3 OP0 OP1 OP0  
Triple Byte  
(0011)  
OP0 OP1 OP2  
Ñ
Ñ
Ñ
Ñ
Ñ
OP0 OP1 OP2  
OP1 OP2 OP3  
OP4 OP5 OP6  
OP5 OP6 OP7  
Ñ
Ñ
Ñ
Ñ
OP1 OP2 OP3  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP4 OP5 OP6  
Ñ
Ñ
Ñ
OP5 OP6 OP7  
Ñ
Ñ
Word  
(0100)  
OP0 OP1 OP2 OP3  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP4 OP5 OP6 OP7 OP4 OP5 OP6 OP7 OP4 OP5 OP4  
Double  
Word  
(0000)  
OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 OP0 OP1 OP2 OP3 OP0 OP1 OP0  
1
Address state is the calculated address for port size.  
2
OPn:These lanes are read or written during that bus transaction. OP0 is the most-signiÞcant byte of a word operand  
and OP7 is the least-signiÞcant byte.  
3
Ñ Denotes a byte not required during that read cycle.  
Table 8-9 lists data transfer patterns for write cycles for accesses initiated by the MPC8260.  
8-18  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part III.The Hardware Interface  
Table 8-9. Data Bus Contents for Write Cycles  
Transfer  
Size  
TSIZ[0Ð3]  
Address  
1
External Data Bus Pattern  
State  
A[29Ð31]  
0Ð7  
8Ð15  
16Ð23  
24Ð31  
32Ð39  
40Ð47  
48Ð55  
56Ð63  
2
3
Byte  
(0001)  
000  
001  
010  
011  
100  
101  
OP0  
OP1  
OP2  
OP3  
OP4  
OP5  
OP6  
OP7  
OP0  
OP1  
OP2  
OP4  
OP5  
OP6  
OP0  
OP1  
OP4  
OP5  
OP0  
OP4  
OP0  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP1  
Ñ
OP2  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP3  
Ñ
OP3  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP4  
Ñ
Ñ
Ñ
Ñ
OP5  
Ñ
Ñ
Ñ
OP5  
Ñ
Ñ
Ñ
1
110  
OP6  
Ñ
Ñ
Ñ
OP6  
Ñ
Ñ
111  
000  
001  
010  
100  
101  
110  
000  
001  
100  
101  
000  
100  
000  
OP7  
OP1  
OP1  
OP3  
OP5  
OP5  
OP7  
OP1  
OP1  
OP5  
OP5  
OP1  
OP5  
OP1  
OP7  
Ñ
Ñ
Ñ
OP7  
Ñ
Half Word  
(0010)  
Ñ
Ñ
Ñ
Ñ
OP2  
OP2  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP3  
Ñ
Ñ
Ñ
Ñ
Ñ
OP4  
Ñ
OP5  
OP5  
Ñ
Ñ
Ñ
OP6  
OP6  
OP2  
OP2  
OP6  
OP6  
OP2  
OP6  
OP2  
Ñ
OP6  
OP6  
Ñ
Ñ
OP7  
Ñ
Ñ
OP7  
Ñ
Triple Byte  
(0011)  
Ñ
Ñ
OP3  
Ñ
Ñ
Ñ
Ñ
Ñ
OP4  
Ñ
OP5  
OP5  
Ñ
OP6  
OP6  
Ñ
Ñ
OP7  
OP3  
OP7  
OP3  
OP7  
Ñ
Word  
(0100)  
Ñ
OP4  
OP4  
OP5  
OP5  
OP6  
OP6  
OP7  
OP7  
Double Word  
(0000)  
1
Address state is the calculated address for port size  
2
OPn: These lanes are read or written during that bus transaction. OP0 is the most-signiÞcant byte of a word  
operand and OP7 is the least-signiÞcant byte.  
3
Ñ Denotes a byte not driven during that write cycle.  
8.4.3.7 60x-Compatible Bus ModeÑSize Calculation  
To comply with the requirements listed in Table 8-8 and Table 8-9, the transfer size and a  
new address must be calculated at the termination of each beat of a port-size transaction. In  
single-MPC8260 bus mode, these calculations are internal and do not constrain the system.  
In 60x-compatible bus mode, the external slave or master must determine the new address  
and size. Table 8-10 describes the address and size calculation state machine. Note that the  
address and size states are for internal use and are not transferred on the address or TSIZ  
pins. Extended transactions (16- and 24-byte) are not described here but can be determined  
by extending this table for 9-, 10-, 16-, 23-, and 24-byte transactions.  
MOTOROLA  
Chapter 8. The 60x Bus  
8-19  
         
Part III.The Hardware Interface  
Table 8-10. Address and Size State Calculations  
Size State  
Address State [0Ð4]  
Port Size  
Next Size State  
Next Address State [0Ð4]  
Stop  
Byte  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
x
x
0
0
1
1
0
0
1
1
x
x
x
x
0
0
0
0
0
0
0
0
x
x
0
0
0
x
0
0
0
0
0
0
0
0
x
0
0
x
1
1
1
0
0
0
0
0
x
0
1
1
1
0
0
1
0
1
0
1
0
1
x
x
2-Byte  
Byte  
Byte  
Byte  
Byte  
Byte  
x
x
x
x
x
x
0
1
x
x
1
1
1
1
0
0
0
x
x
Half  
x
Stop  
3-Byte  
Byte  
2-Byte  
2-Byte  
2-Byte  
2-Byte  
Byte  
x
x
x
x
x
x
x
x
x
0
0
1
1
0
0
1
1
0
1
0
1
1
1
1
1
1
0
1
0
0
0
0
0
x
x
x
Half  
x
2-Byte  
Byte  
x
x
2-Byte  
x
Word  
Byte  
Half  
Stop  
4-Byte  
0
0
x
3-Byte  
2-Byte  
x
x
x
x
x
0
1
1
0
x
Word  
Byte  
Byte  
Half  
Stop  
5-Byte  
6-Byte  
1
0
0
1
0
0
0
0
4-Byte  
5-Byte  
4-Byte  
6-Byte  
7-Byte  
6-Byte  
4-Byte  
x
x
x
x
x
x
x
x
1
0
1
0
0
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
0
x
x
7-Byte  
8-Byte  
Byte  
Byte  
Half  
x
x
x
Word  
Double  
x
Stop  
8.4.3.8 Extended Transfer Mode  
The MPC8260 supports an extended transfer mode that improves bus performance. This  
should not be confused with the extended bus protocol used to support direct-store  
operations supported in some earlier PowerPC processors. The MPC8260 can generate 5-,  
6-, 7-, 16-, or 24-byte extended transfers. These transactions are compatible with the 60x  
8-20  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part III.The Hardware Interface  
bus, but some slaves or masters do not support these features. Clear BCR[ETM] to disable  
this type of transaction. This places the MPC8260 in strict 60x bus mode. The following  
tables are extensions to Table 8-9, Table 8-8, and Table 8-10.  
Table 8-11 lists the patterns of the extended data transfer for write cycles when MPC8260  
initiates an access. Note that 16- and 24-byte transfers are always eight-byte aligned and  
use a 64-bit or less port size.  
Table 8-11. Data Bus Contents for Extended Write Cycles  
External Data Bus Pattern  
Transfer  
Size  
TSIZ[0Ð3])  
Address  
State A[29Ð  
31]  
D[0Ð7] D[8Ð15] D[16Ð23] D[24Ð31] D[32Ð39] D[40Ð47] D[48Ð55] D[56Ð63]  
5 Bytes  
(0101)  
000  
011  
000  
010  
000  
001  
OP0  
OP3  
OP0  
OP2  
OP0  
OP1  
OP1  
OP3  
OP1  
OP3  
OP1  
OP1  
OP2  
Ñ
OP3  
OP3  
OP3  
OP3  
OP3  
OP3  
OP4  
OP4  
OP4  
OP4  
OP4  
OP4  
Ñ
Ñ
Ñ
OP7  
Ñ
OP5  
OP5  
OP5  
OP5  
OP5  
OP6  
Ñ
6 Bytes  
(0110)  
OP2  
OP2  
OP2  
OP2  
OP6  
OP6  
OP6  
OP7  
Ñ
7 Bytes  
(0111)  
OP7  
Table 8-12 lists the bytes required on the data bus for extended read cycles. Note that 16-  
and 24-byte transfers are always 8-byte aligned and use a maximum 64-bit port size.  
Table 8-12. Data Bus Requirements for Extended Read Cycles  
Port Size/Data Bus Assignments  
Transfer Address  
Size  
State  
64-Bit  
0Ð7 8Ð15 16Ð23 24Ð31 32Ð39 40Ð47 48Ð55 56Ð63 0Ð7 8Ð15 16Ð23 24Ð31 0Ð7 8Ð15 0Ð7  
OP0 OP1 OP2 OP3 OP4 OP0 OP1 OP2 OP3 OP0 OP1 OP0  
OP3 OP4 OP5 OP6 OP7 OP3 OP3 OP3  
OP0 OP1 OP2 OP3 OP4 OP5 OP0 OP1 OP2 OP3 OP0 OP1 OP0  
OP2 OP3 OP4 OP5 OP6 OP7 OP2 OP3 OP2 OP3 OP2  
OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP0 OP1 OP2 OP3 OP0 OP1 OP0  
OP1 OP2 OP3 OP4 OP5 OP6 OP7 OP1 OP2 OP3 OP1 OP1  
32-Bit  
16-Bit  
8-Bit  
TSIZ[0Ð3] A[29-31]  
5 Byte  
(0101)  
000  
011  
000  
010  
000  
001  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
6 Byte  
(0110)  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
7 Byte  
(0111)  
Ñ
Ñ
Ñ
Ñ
Table 8-13 includes added states to the transfer size calculation state machine. Only  
extended transfers use these states.  
MOTOROLA  
Chapter 8. The 60x Bus  
8-21  
     
Part III.The Hardware Interface  
Table 8-13. Address and Size State for Extended Transfers  
Size State [0Ð3]  
Address State[0Ð4]  
Port Size  
Next Size State [0Ð3]  
Next Address State[0Ð4]  
Half  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
x
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
x
0
0
0
0
0
0
0
x
0
0
0
0
0
0
x
1
0
x
1
0
1
0
0
1
0
0
1
1
0
1
1
0
1
x
0
0
1
0
1
0
1
x
0
0
0
0
0
0
x
1
1
x
0
0
0
0
1
1
0
1
0
1
0
0
1
0
1
x
0
1
0
0
0
0
0
x
0
1
0
1
0
1
x
Byte  
Byte  
x
x
x
1
1
0
1
0
0
x
Half  
Stop  
3-Byte  
Byte  
Half  
Byte  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
1
1
0
1
0
0
0
1
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
0
0
x
Half  
Byte  
Byte  
x
x
Word  
3-Byte  
Word  
x
x
5-Byte  
x
x
x
x
Half  
3-Byte  
x
x
Word  
Byte  
x
Word  
x
Word  
x
Double  
Byte  
Stop  
6-Byte  
5-Byte  
Word  
x
x
x
x
x
x
x
x
0
0
0
0
1
1
1
0
1
1
1
0
0
0
1
0
1
0
0
0
0
x
x
Half  
x
x
Word  
Half  
x
Word  
x
Double  
Byte  
Stop  
7-Byte  
6-Byte  
x
x
x
x
x
x
x
0
0
0
0
1
1
0
1
1
1
0
0
1
0
0
0
0
0
x
Half  
Word  
5-Byte  
6-Byte  
3-Byte  
4-Byte  
x
x
x
x
Double  
Stop  
Extended transfer mode is enabled by setting the BCR[ETM].  
8-22  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part III.The Hardware Interface  
8.4.4 Address Transfer Termination  
Address transfer termination occurs with the assertion of the address acknowledge (AACK)  
signal, or retried with the assertion of ARTRY. ARTRY must remain asserted until one  
clock after AACK; the bus clock cycle after AACK is called the ARTRY window. The  
MPC8260 controls assertion ofAACK unless the cycle is claimed by an external slave, such  
as an external L2 cache controller. Following the assertion of L2_HIT, the L2 cache  
controller is responsible for assertingAACK. WhenAACK is asserted by the external slave,  
it should be asserted for one clock cycle and then negated for one clock cycle before  
entering a high-impedance state. The MPC8260 holds AACK in a high-impedance state  
until it is required to assert AACK to terminate the address cycle.  
The MPC8260 uses AACK to enforce a pipeline depth of one to its internal slaves.  
NOTE  
If the MPC8260 processor clock is conÞgured for 1x or 1.5x  
clock mode, the ARTRY snoop response cannot be determined  
in the minimum allowed address tenure period. For this clock  
mode, AACK must not be asserted to the chip until at least the  
third clock of the address tenure (one address wait state) to give  
the processor time to assert ARTRY on the bus. For the other  
clock conÞguration modes, the ARTRY snoop response can be  
determined in the minimum address tenure period, and AACK  
may be asserted as early as the second bus clock of the address  
tenure (zero address wait states).  
8.4.4.1 Address Retried with ARTRY  
The address transfer can be terminated with the requirement to retry if ARTRY is asserted  
during the address tenure and through the cycle following AACK. The assertion causes the  
entire transaction (address and data tenure) to be rerun.As a snooping device, the MPC8260  
processor assertsARTRY for a snooped transaction that hits modiÞed data in the data cache  
that must be written back to memory, or if the snooped transaction could not be serviced.  
As a bus master, the MPC8260 responds to an assertion of ARTRY by aborting the bus  
transaction and requesting the bus again, as shown in Figure 8-7. Note that after  
recognizing an assertion of ARTRY and aborting the current transaction, the MPC8260  
may not run the same transaction the next time it is granted the bus.  
MOTOROLA  
Chapter 8. The 60x Bus  
8-23  
       
Part III.The Hardware Interface  
CLKOUT  
BR INT  
BG INT  
BR  
External  
BG  
ABB  
ADDR + ATTR  
TS  
MPC8260  
External  
MPC8260  
AACK  
ARTRY  
Figure 8-7. Retry Cycle  
As a bus master, the MPC8260 recognizes either an early or qualiÞed ARTRY and prevents  
the data tenure associated with the retried address tenure. If the data tenure has begun, the  
MPC8260 terminates the data tenure immediately even if the burst data has been received.  
If the assertion of ARTRY is received up to or on the bus cycle after the Þrst (or only)  
assertion of TA for the data tenure, the MPC8260 ignores the Þrst data beat. If it is a read  
operation, the MPC8260 does not forward data internally to the cache, execution unit, or  
any other MPC8260 internal storage. This address retry case succeeds because the data  
tenure is aborted in time, and the entire transaction is rerun. This retry mechanism allows  
the memory system to begin operating in parallel with the bus snoopers, provided external  
devices do not present data sooner than the bus cycle before all snoop responses can be  
determined and asserted on the bus.  
Note that the system must ensure that the Þrst (or only) assertion of TA for a data transfer  
does not occur sooner than the cycle before the Þrst assertion of ARTRY on the bus, (or  
conversely, that ARTRY is never asserted later than the cycle after the Þrst or only assertion  
of TA). This guarantees the relationship between TA and ARTRY such that, in case of an  
address retry, the data may be cancelled in the chip before it can be forwarded internally to  
the internal memory resources (registers or cache). Generally, the memory system must  
8-24  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part III.The Hardware Interface  
also detect this event and abort any transfer in progress. If this TA/ARTRY relationship is  
not met, the master may enter an undeÞned state. Users may use PPC_ACR[DBGD] to  
ensure correct operation of the system.  
During the clock of a qualiÞed ARTRY, each device master determines whether it should  
negate BR and ignore BG on the following cycle. The following cycle is referred to as the  
window-of-opportunity for the snooping master. During this window, only the snooping  
master that asserted ARTRY and requires a snoop copyback operation is allowed to assert  
BR. This guarantees the snooping master a window of opportunity to request and be granted  
the bus before the just-retried master can restart its transaction. BG is also blocked in the  
window-of-opportunity, so the arbiter has a chance to negate BG to an already granted  
potential bus master to perform a new arbitration.  
Note that in some systems, an external processor may be unable to perform a pending snoop  
copyback when a new snoop operation is performed. In this case, the MPC8260 requests  
the window of opportunity if it hits on the new snooped address. To clear its internal snoop  
queue, it performs the snoop copyback operation for the earlier snooped address instead of  
the current snooped address.  
8.4.4.2 Address Tenure Timing ConÞguration  
During address tenures initiated by 60x-bus devices, the timing of the assertion of AACK  
by the MPC8260 is determined by the BCR[APD] and the pipeline status of the 60x bus.  
Because the MPC8260 can support one level of pipelining, it uses AACK to control the  
60x-bus pipeline condition. To maintain the one-level pipeline, AACK is not asserted for a  
pipelined address tenure until the current data tenure ends. The MPC8260 also delays  
asserting AACK until no more address retry conditions can occur. Note that the earliest the  
MPC8260 can assertAACK is the clock cycle when the wait-state values set by BCR[APD]  
have expired.  
BCR[APD] speciÞes the minimum number of address tenure wait states for address  
operations initiated by 60x-bus devices. APD indicates how many cycles the MPC8260  
should wait for ARTRY, but because it is assumed that ARTRY can be asserted (by other  
masters) only on cacheable address spaces, APD is considered only on transactions that hit  
a 60x-assigned memory controller bank and that have GBL asserted during the address  
phase.  
Extra wait states may occur because of other MPC8260 conÞguration parameters. Note that  
in a system with an L2 cache, the number of wait states conÞgured by BCR[APD] should  
be at least as large as the value needed by the L2 controller to assert hit response. In systems  
with multiple potential masters, the number of wait states conÞgured by BCR[APD] should  
be at least as large as the value the slowest master would need by to assert a snoop response.  
For example, additional wait states are required when the internal processor is in 1:1 clock  
mode; this case requires at least one wait state to generate the ARTRY response.  
MOTOROLA  
Chapter 8. The 60x Bus  
8-25  
   
Part III.The Hardware Interface  
8.4.5 Pipeline Control  
The MPC8260 supports the two following modes:  
¥
One-level pipeline modeÑTo maintain the one-level pipeline,AACK is not asserted  
for a pipelined address tenure until the current data tenure ends. In 60x-compatible  
bus mode, a two-level pipeline depth can occur (for example, when an external 60x-  
bus slave does not support one-level pipelining). When the internal arbiter counts a  
pipeline depth of two (two assertions of AACK before the assertion of the current  
data tenure) it negates all address bus grant (BG) signals.  
¥
No-pipeline modeÑThe MPC8260 does not assert AACK until the corresponding  
data tenure ends.  
8.5 Data Tenure Operations  
This section describes the operation of the MPC8260 during the data bus arbitration,  
transfer, and termination phases of the data tenure.  
8.5.1 Data Bus Arbitration  
The beginning of an address transfer, marked by the assertion of transfer start (TS), is also  
an implicit data bus request provided that the transfer type signals (TT[0Ð4]) indicate that  
the transaction is not address-only.  
The MPC8260 arbiter supports one external master and uses DBG to grant the external  
master data bus.The DBG signals are not asserted if the data bus, which is shared with  
memory, is busy with a transaction.  
A qualiÞed data bus grant (QDBG) can be expressed as the assertion of DBG while DBB  
and ARTRY (associated with the data bus operation) are negated.  
Note that the MPC8260 arbiter should assert DBG only when it is certain that the Þrst TA  
will be asserted with or after the associated ARTRY. The MPC8260 DBG is asserted with  
TS if the data bus is free and if the PPC_ACR[DBGD] = 0. If PPC_ACR[DBGD] = 1, DBG  
is asserted one cycle after TS if the data bus is not busy. The DBG delay should be used to  
ensure that ARTRY is not asserted after the Þrst or only TA assertion. For the programming  
model, see Section 4.3.2.2, Ò60x Bus Arbiter ConÞguration Register (PPC_ACR).Ó  
Note that DBB should not be asserted after the data tenure is Þnished. Assertion of DBB  
after the last TA causes improper operation of the bus. (MPC8260 internal masters do not  
assert DBB after the last TA.)  
Note the following:  
¥
External bus arbiters must comply with the following restriction on assertion of  
DBG which is connected to the MPC8260. In case the data bus is not busy with the  
data of a previous transaction on the bus, external arbiter must assert DBG in the  
same cycle in which TS is asserted (by a master which was granted the bus) or in the  
8-26  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
                 
Part III.The Hardware Interface  
following cycle. In case the external arbiter asserts DBG on the cycle in which TS  
was asserted, PPC_ACR[DBGD] should be zero. Otherwise, PPC_ACR[DBGD]  
should be set.  
¥
External masters connected to the 60x bus must assert DBB only for the duration of  
its data tenure. External masters should not use DBB to prevent other masters from  
using the data bus after their data tenure has ended.  
8.5.2 Data Streaming Mode  
The MPC8260 supports a special data streaming mode that can improve bus performance  
in some conditions. Generally, the bus protocol requires one idle cycle between any two  
data tenures. This idle cycle is essential to prevent contention on the data bus when the  
driver of the data is changing. However, when the driver on the data bus is the same for both  
data tenures, this idle cycle may be omitted.  
In data streaming mode, the MPC8260 omits the idle cycle where possible. MPC8260  
applications often require data stream transfers of more than 4 x 64 bits. For example, the  
ATM cellÕs payload is 6 x 64 bits. All this data is driven from a single device on the bus, so  
data-streaming saves a cycle for such a transfer. When data-streaming mode is enabled,  
transactions initiated by the core are not affected, while transactions initiated by other bus  
masters within the chip omit the idle cycle if the data driver is the same. Note that data  
streaming mode cannot be enabled when the MPC8260 is in 60x-compatible bus mode and  
a device that uses DBB is connected to the bus. This restriction is due to the fact that a  
MPC8260 for which data streaming mode is enabled may leave DBB asserted after the last  
TA of a transaction and this is a violation of the strict bus protocol. The data streaming  
mode is enabled by setting BCR[ETM].  
8.5.3 Data Bus Transfers and Normal Termination  
The data transfer signals include D[0Ð63] and DP[0Ð7]. For memory accesses, the data  
signals form a 64-bit data path, D[0Ð63], for read and write operations.  
The MPC8260 handles data transfers in either single-beat or burst operations. Single-beat  
operations can transfer from 1 to 24 bytes of data at a time. Burst operations always transfer  
eight words in four double-word beats. A burst transaction is indicated by the assertion of  
TBST by the bus master. A transaction is terminated normally by asserting TA.  
The three following signals are used to terminate the individual data beats of the data tenure  
and the data tenure itself:  
¥
TA indicates normal termination of data transactions. It must always be asserted on  
the bus cycle coincident with the data that it is qualifying. It may be withheld by the  
slave for any number of clocks until valid data is ready to be supplied or accepted.  
¥
Asserting TEA indicates a nonrecoverable bus error event. Upon receiving a Þnal (or  
only) termination condition, the MPC8260 always negates DBB for one cycle,  
except when fast data bus grant is performed.  
MOTOROLA  
Chapter 8. The 60x Bus  
8-27  
         
Part III.The Hardware Interface  
¥
Asserting ARTRY causes the data tenure to be terminated immediately if the  
ARTRY is for the address tenure associated with the data tenure in operation (the  
data tenure may not be terminated due to address pipelining). The earliest allowable  
assertion of TA depends directly on the latest possible assertion of ARTRY.  
Figure 8-8 shows both a single-beat and burst data transfer. The MPC8260 asserts TA to  
mark the cycle in which data is accepted. In a normal burst transfer, the fourth assertion of  
TA signals the end of a transfer.  
CLKOUT  
ADDR + ATTR  
TS  
AACK  
DBG  
TA  
PSDVAL  
D[0Ð63]  
D0  
D1  
D2  
D3  
Figure 8-8. Single-Beat and Burst Data Transfers  
8.5.4 Effect of ARTRY Assertion on Data Transfer and Arbitration  
The MPC8260 allows an address tenure to overlap its associated data tenure. The MPC8260  
internally guarantees that the Þrst TA of the data tenure is delayed to be at the same time or  
after the ARTRY window (the clock after the assertion of AACK).  
8.5.5 Port Size Data Bus Transfers and PSDVAL Termination  
The MPC8260 can transfer data via data ports of 8, 16, 32, and 64 bits, as shown in  
Section 8.4.3, ÒAddress Transfer Attribute Signals.Ó Single-beat transaction sizes can be 8,  
16, 32, 64, 128, and 192 bits; burst transactions are 256 bits. Single-beat and burst  
transactions are divided into to a number of intermediate beats depending on the port size.  
The MPC8260 asserts PSDVAL to mark the cycle in which data is accepted. Assertion of  
PSDVAL in conjunction with TA marks the end of the transfer in single-beat mode. The  
fourth assertion of PSDVAL in conjunction with TA signals the end of a burst transfer.  
8-28  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
           
Part III.The Hardware Interface  
Figure 8-9 shows an extended transaction of 4 words to a port size of 32 bits. The single-  
beat transaction is translated to four port-sized beats.  
CLKOUT  
ADDR + ATTR  
TS  
AACK  
DBG  
PSDVAL  
TA  
D[0Ð31]  
D0  
D1  
D2  
D3  
Figure 8-9. 128-Bit Extended Transfer to 32-Bit Port Size  
Figure 8-10 shows a burst transfer to a 32-bit port. Each double-word burst beat is divided  
into two port-sized beats such that the four double words are transferred in eight beats.  
MOTOROLA  
Chapter 8. The 60x Bus  
8-29  
 
Part III.The Hardware Interface  
CLKOUT  
ADDR + ATTR  
TS  
AACK  
DBG  
PSDVAL  
TA  
D[0Ð31]  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
Figure 8-10. Burst Transfer to 32-Bit Port Size  
8.5.6 Data Bus Termination by Assertion of TEA  
If a device initiates a transaction that is not supported by the MPC8260, the MPC8260  
signals an error by asserting TEA. Because the assertion of TEA is sampled by the device  
only during the data tenure of the bus transaction, the MPC8260 ensures that the device  
master receives a qualiÞed data bus grant by asserting DBG before asserting TEA. The data  
tenure is terminated by a single assertion of TEA regardless of the port size or whether the  
data tenure is a single-beat or burst transaction. This sequence is shown in Figure 8-11. In  
Figure 8-11 the data bus is busy at the beginning of the transaction, thus delaying the  
assertion of DBG. Note that data errors (parity and ECC) are reported not by assertion of  
TEA but by assertion of MCP.  
Because the assertion of TEA is sampled by the device only during the data tenure of the  
bus transaction, the MPC8260 ensures that the device receives a qualiÞed data bus grant by  
asserting DBG before asserting TEA. The data tenure is terminated by a single assertion of  
TEA regardless of the port size or whether the data tenure is a single-beat or burst  
transaction. This sequence is shown in Figure 8-11. In Figure 8-11 the data bus is busy at  
the beginning of the transaction, thus delaying the assertion of DBG.  
8-30  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part III.The Hardware Interface  
CLKOUT  
ADDR + ATTR  
TS  
For Single  
For Burst  
AACK  
DBG  
TA  
TEA  
Data  
Figure 8-11. Data Tenure Terminated by Assertion of TEA  
MPC8260 interprets the following bus transactions as bus errors:  
¥
¥
Direct-store transactions, as indicated by the assertion of XATS.  
Bus errors asserted by slaves (internal or external).  
8.6 Memory CoherencyÑMEI Protocol  
The MPC8260 provides dedicated hardware to ensure memory coherency by snooping bus  
transactions, by maintaining information about the status of data in a cache block, and by  
the address retry capability. Each data cache block includes status bits that support the  
modiÞed/exclusive/invalid, or MEI, cache-coherency protocol.  
Asserting the global (GBL) output signal indicates whether the current transaction must be  
snooped by other snooping devices on the bus. Address bus masters assert GBL to indicate  
that the current transaction is a global access (that is, an access to memory shared by more  
than one device). If GBL is not asserted for the transaction, that transaction is not snooped.  
When other devices detect the GBL input asserted, they must respond by snooping any  
addresses broadcast. Normally, GBL reßects the M bit value speciÞed for the memory  
reference in the corresponding translation descriptor. Care must be taken to minimize the  
number of pages marked as global, because the retry protocol discussed in the previous  
section used to enforce coherency can require signiÞcant bus bandwidth.  
MOTOROLA  
Chapter 8. The 60x Bus  
8-31  
     
Part III.The Hardware Interface  
When the MPC8260 processor is not the address bus master, GBL is an input. The  
MPC8260 processor snoops a transaction if TS and GBL are asserted together in the same  
bus clock cycle (a qualiÞed snooping condition). No snoop update to the MPC8260  
processor cache occurs if the transaction is not marked global. This includes invalidation  
cycles.  
When the MPC8260 processor detects a qualiÞed snoop condition, the address associated  
with the TS is compared against the data cache tags. Snooping completes if no hit is  
detected. However, if the address hits in the cache, the MPC8260 processor reacts  
according to the MEI protocol shown in Figure 8-12. This Þgure assumes that  
WIM = 0b001 (memory space is marked for write-back, caching-allowed, and coherency-  
enforced modes).  
Invalid  
SH/CRW  
SH/CRW  
WM  
RM  
WH  
Modified  
Exclusive  
SH  
RH  
RH  
WH  
SH/CIR  
SH = Snoop hit  
RH = Read hit  
WH = Write hit  
WM = Write miss  
RM = Read miss  
= Snoop push  
= Cache line fill  
SH/CRW = Snoop hit, cacheable read/write  
SH/CIR = Snoop hit, cache-inhibited read  
Figure 8-12. MEI Cache Coherency ProtocolÑState Diagram (WIM = 001)  
8.7 Processor State Signals  
This section describes the MPC8260Õs support for atomic update and memory through the  
use of the lwarx/stwcx. instruction pair. It also describes the TLBISYNC input.  
8-32  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part III.The Hardware Interface  
8.7.1 Support for the lwarx/stwcx. Instruction Pair  
The load word and reserve indexed (lwarx) and the store word conditional indexed (stwcx.)  
instructions provide a way to update memory atomically by setting a reservation on the load  
and checking that the reservation is still valid before the store is performed. In the  
MPC8260, reservations are made on behalf of aligned, 32-byte sections of the memory  
address space.  
The reservation (RSRV) output signal is driven synchronously with the bus clock and  
reßects the status of the reservation coherency bit in the reservation address register.  
Note that each external master must do its own snooping; the MPC8260 does not provide  
external reservation snooping.  
8.7.2 TLBISYNC Input  
The TLBISYNC input permits hardware synchronization of changes to MMU tables when  
the MPC8260 and another DMA master share the MMU translation tables in system  
memory. A DMA master asserts TLBISYNC when it uses shared addresses that the  
MPC8260 could change in the MMU tables during the DMA masterÕs tenure.  
When the TLBISYNC input is asserted, the MPC8260 cannot complete any instructions  
past a tlbsync instruction. Generally, during the execution of an eciwx or ecowx  
instruction, the selected DMA device should assert the MPC8260Õs TLBISYNC signal and  
hold it asserted during its DMA tenure if it is using a shared translation address. Subsequent  
instructions by the MPC8260 processor should include a sync and tlbsync instruction  
before any MMU table changes are performed. This prevents the MPC8260 from making  
disruptive table changes during the DMA tenure.  
8.8 Little-Endian Mode  
The MPC8260 supports a little-endian mode in which low-order address bits are operated  
on (munged) based on the size of the requested data transfer. This mode allows a little-  
endian program running on the processor with a big-endian memory system to offset into  
a data structure and receive the same results as it would if it were operating on a true little-  
endian processor and memory system. For example, writing a word to memory as a word  
operation on the bus and then reading in the second byte of that word as a byte operation  
on the bus.  
Note that when the processor is selected for little-endian operation, the bus interface is still  
operating in big-endian mode. That is, byte address 0 of a double word (as selected by  
A[29Ð31] on the busÑafter the internal address munge) still selects the most signiÞcant  
(left most) byte of the double word on D[0Ð7]. If the processor interfaces with a true little-  
endian environment, the system may need to perform byte-lane swapping or other  
operations external to the processor.  
MOTOROLA  
Chapter 8. The 60x Bus  
8-33  
           
Part III.The Hardware Interface  
8-34  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Chapter 9  
Clocks and Power Control  
90  
90  
The MPC8260Õs clocking architecture includes two PLLsÑthe main PLL and the core  
PLL.  
The clock block, which contains the main PLL, provides the following:  
¥
¥
Internal clocks for all blocks in the chip except core blocks  
The internal 60x bus clock in the chip  
The core input clock has the 60x bus frequency, which the core PLL multiplies by a  
conÞgurable factor and provides to all core blocks.  
Seven bits, three that are dedicated (MODCK[1Ð3]) and four that are from the hardware  
conÞguration word, (MODCK_H) map the MPC8260 clocks to one of 49 work options.  
Each option determines the bus, core, and CPM frequencies. Assuming the four  
conÞguration bits are zero, the three dedicated pins MODCK[1Ð3] select one of eight work  
options, see Section 9.2, ÒClock ConÞguration.Ó  
The CLOCKIN signal is the main timing reference for the MPC8260. The CLOCKIN  
frequency is equal to the 60x and local bus frequencies. The main PLL can multiply the  
frequency of the input clock to the Þnal CPM frequency.  
9.1 Clock Unit  
The MPC8260Õs clock module consists of the input clock interface (OSCM), the PLL, the  
system frequency dividers, the clock generator/driver blocks, the conÞguration control unit,  
and the clock control block. The clock module and the conÞguration control unit are  
managed through the system clock mode register (SCMR), the conÞguration bits  
MODCK[1Ð7], and reset block.  
To improve noise immunity, the charge pump and the VCO of the main PLL have their own  
set of power supply pins (VCCSYN and GNDSYN). All other circuits are powered by the  
normal supply pins, VDD and VSS.  
MOTOROLA  
Chapter 9. Clocks and Power Control  
9-1  
           
Part III.The Hardware Interface  
9.2 Clock ConÞguration  
To conÞgure the main PLL multiplication factor and the core, CPM, and 60x bus  
frequencies, the MODCK[1Ð3] pins are sampled while HRESET is asserted. Table 9-1  
shows the eight basic conÞguration modes. Another 49 modes are available by using the  
conÞguration pin (RSTCONF) and driving four pins on the data bus.  
Table 9-1. Clock Default Modes  
Input Clock CPM Multiplication  
CPM  
Frequency  
Core Multiplication  
Factor  
Core  
Frequency  
MODCK[1Ð3]  
Frequency  
Factor  
000  
001  
010  
011  
100  
101  
110  
111  
33 MHz  
33 MHz  
33 MHz  
33 MHz  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
3
3
100 MHz  
100 MHz  
133 MHz  
133 MHz  
133 MHz  
133 MHz  
166 MHz  
166 MHz  
4
5
133 MHz  
166 MHz  
133 MHz  
166 MHz  
166 MHz  
200 MHz  
166 MHz  
200 MHz  
4
4
4
5
2
2.5  
3
2
2.5  
2.5  
2.5  
3
Table 9-2 describes all possible clock conÞgurations when using the hard reset  
conÞguration sequence. Note that clock conÞguration changes only after POR is asserted.  
Note also that basic modes are bolded in this table.  
Table 9-2. Clock Configuration Modes  
Input Clock CPM Multiplication  
CPM  
Frequency  
Core Multiplication  
Factor  
Core  
Frequency  
MODCK_HÐMODCK[1Ð3]  
Frequency  
Factor  
0001_000  
0001_001  
0001_010  
0001_011  
0001_100  
33 MHz  
33 MHz  
33 MHz  
33 MHz  
33 MHz  
2
2
2
2
2
66 MHz  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
4
5
6
7
8
133 MHz  
166 MHz  
200 MHz  
233 MHz  
266 MHz  
0001_101  
0001_110  
0001_111  
0010_000  
0010_001  
33 MHz  
33 MHz  
33 MHz  
33 MHz  
33 MHz  
3
3
3
3
3
100 MHz  
100 MHz  
100 MHz  
100 MHz  
100 MHz  
4
5
6
7
8
133 MHz  
166 MHz  
200 MHz  
233 MHz  
266 MHz  
0010_010  
33 MHz  
4
133 MHz  
4
133 MHz  
9-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part III.The Hardware Interface  
Table 9-2. Clock Configuration Modes (Continued)  
Input Clock CPM Multiplication  
CPM  
Frequency  
Core Multiplication  
Factor  
Core  
Frequency  
MODCK_HÐMODCK[1Ð3]  
Frequency  
Factor  
0010_011  
0010_100  
0010_101  
0010_110  
33 MHz  
33 MHz  
33 MHz  
33 MHz  
4
4
4
4
133 MHz  
133 MHz  
133 MHz  
133 MHz  
5
6
7
8
166 MHz  
200 MHz  
233 MHz  
266 MHz  
0010_111  
0011_000  
0011_001  
0011_010  
0011_011  
33 MHz  
33 MHz  
33 MHz  
33 MHz  
33 MHz  
5
5
5
5
5
166 MHz  
166 MHz  
166 MHz  
166 MHz  
166 MHz  
4
5
6
7
8
133 MHz  
166 MHz  
200 MHz  
233 MHz  
266 MHz  
0011_100  
0011_101  
0011_110  
0011_111  
0100_000  
33 MHz  
33 MHz  
33 MHz  
33 MHz  
33 MHz  
6
6
6
6
6
200 MHz  
200 MHz  
200 MHz  
200 MHz  
200 MHz  
4
5
6
7
8
133 MHz  
166 MHz  
200 MHz  
233 MHz  
266 MHz  
0100_001  
0100_010  
0100_011  
0100_100  
0100_101  
0100_110  
Reserved  
Reserved  
133 MHz  
0100_111  
0101_000  
0101_001  
0101_010  
0101_011  
0101_100  
0101_101  
66 MHz  
2
2
133 MHz  
MOTOROLA  
Chapter 9. Clocks and Power Control  
9-3  
Part III.The Hardware Interface  
Table 9-2. Clock Configuration Modes (Continued)  
Input Clock CPM Multiplication  
CPM  
Frequency  
Core Multiplication  
Factor  
Core  
Frequency  
MODCK_HÐMODCK[1Ð3]  
Frequency  
Factor  
0101_110  
0101_111  
0110_000  
0110_001  
0110_010  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
2
2
2
2
2
133 MHz  
133 MHz  
133 MHz  
133 MHz  
133 MHz  
2.5  
3
166 MHz  
200 MHz  
233 MHz  
266 MHz  
300 MHz  
3.5  
4
4.5  
0110_011  
0110_100  
0110_101  
0110_110  
0110_111  
0111_000  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
166 MHz  
166 MHz  
166 MHz  
166 MHz  
166 MHz  
166 MHz  
2
2.5  
3
133 MHz  
166 MHz  
200 MHz  
233 MHz  
266 MHz  
300 MHz  
3.5  
4
4.5  
0111_001  
0111_010  
0111_011  
0111_100  
0111_101  
0111_110  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
3
3
3
3
3
3
200 MHz  
200 MHz  
200 MHz  
200 MHz  
200 MHz  
200 MHz  
2
2.5  
3
133 MHz  
166 MHz  
200 MHz  
233 MHz  
266 MHz  
300 MHz  
3.5  
4
4.5  
0111_111  
1000_000  
1000_001  
1000_010  
1000_011  
1000_100  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
66 MHz  
3.5  
3.5  
3.5  
3.5  
3.5  
3.5  
233 MHz  
233 MHz  
233 MHz  
233 MHz  
233 MHz  
233 MHz  
2
2.5  
3
133 MHz  
166 MHz  
200 MHz  
233 MHz  
266 MHz  
300 MHz  
3.5  
4
4.5  
Because of speed dependencies, not all conÞgurations in Table 9-2 may be applicable.  
The 66 MHz conÞgurations are required for input clock frequencies higher than 50 MHz;  
33 MHz conÞgurations are required for input clock frequencies below 50 MHz.  
9-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
9.3 External Clock Inputs  
The input clock source to the PLL is an external clock oscillator at the bus frequency. The  
PLL skew elimination between the CLOCKIN pin and the internal bus clock is guaranteed.  
9.4 Main PLL  
The main PLL performs frequency multiplication and skew elimination. It allows the  
processor to operate at a high internal clock frequency using a low-frequency clock input,  
which has two immediate beneÞts: A lower clock input frequency reduces overall  
electromagnetic interference generated by the system, and oscillating at different  
frequencies eliminates the need for another oscillator to the system.  
9.4.1 PLL Block Diagram  
Figure 9-1 shows how clocking is implemented and the interdependencies of the SCMR  
Þelds:  
¥
¥
¥
BUSDFÑ60x bus division factor  
CPMDFÑCPM division factor. This value is always 1.  
PLLDFÑPLL pre-divider value. Ensures that PLLMF is an integer value regardless  
of whether CPM_CLK/CLKIN is an integer.  
¥
PLLMFÑPLL multiplication factor  
These Þelds are described in detail in Table 9-5.  
VCO_OUT  
(2*CPM_CLK)  
CLKIN  
CPM_CLK  
÷ (CPMDF + 1)  
(÷2)  
÷ (PLLDF + 1)  
´ 2(PLLMF + 1)  
CPM_CLK_90°  
PLLDF ensures that PLLMF is an integer, according to the  
following formula:  
BUS_CLK (= CLKIN)  
BUS_CLK_90°  
÷ (BUSDF + 1)  
CPM_CLK  
CLKIN  
PLLMF =  
´ (PLLDF + 1) Ð 1  
General-Purpose Divider  
÷ 4  
SCC_CLK  
SCC_CLK_90°  
2 (DFBRG + 1)  
2
BRG  
Figure 9-1. System PLL Block Diagram  
The reference signal (CLKIN) goes to the phase comparator that controls the direction (up  
or down) that the charge pump drives the voltage across the external Þlter capacitor (XFC).  
MOTOROLA  
Chapter 9. Clocks and Power Control  
9-5  
               
Part III.The Hardware Interface  
The direction selected depends on whether the feedback signal phase lags or leads the  
reference signal. The output of the charge pump drives the VCO whose output frequency is  
divided and fed back to the phase comparator for comparison with the reference signal,  
CLKIN. Ranging between 1 and 4,096, the PLL multiplication factor is held in the system  
clock mode register (SCMR[PLLMF]). Also, when the PLL is operating, its output  
frequency is twice the CPM frequency. This double frequency is required to generate the  
CPM_CLK and CPM_CLK_90 clocks. See the block diagram in Figure 9-1 for details.  
On initial system power-up, power-on reset (PORESET) should be asserted by external  
logic for 16 input clocks after a valid level is reached on the power supply. Whenever  
power-on reset is asserted, SCMR[PLLMF, PLLDF] are programmed by the conÞguration  
pins; see Table 9-2. This value then drives the clock block to generate the correct CPM and  
bus frequencies.  
9.4.2 Skew Elimination  
The PLL can tighten synchronous timings by eliminating skew between phases of the  
internal clock and the external clock entering the chip (CLOCKIN). Skew elimination is  
always active when the PLL is enabled. Disabling the PLL can greatly increase clock skew.  
9.5 Clock Dividers  
The PLL output is twice the maximum frequency needed for all the clocks. The PLL output  
is sent to general-purpose dividers (CPMDF, BUSDF), either of which can divide the  
double clock by a programmable number between 1 and 16. The delay is the same for all  
dividers independent on the programmable number, so the clocks are synchronized.  
The output of each divider has two phases, one shifted 90¡ from the other, as shown in  
Table 9-1. Each phase has a 50% duty cycle.  
9.6 The MPC8260Õs Internal Clock Signals  
The internal logic of the MPC8260 uses the following internal clock lines:  
¥
¥
¥
¥
CPM general system clocks (CPM_CLK, CPM_CLK_90)  
60x bus, core bus (BUS_CLK, BUS_CLK_90)  
SCC clocks (SCC_CLK, SCC_CLK_90)  
Baud-rate generator clock (BRG_CLK)  
The PLL synchronizes these clock signals to each other (but does not synchronize to  
BRG_CLK).  
9-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
             
Part III.The Hardware Interface  
9.6.1 General System Clocks  
The general system clocks (CPM_CLK, CPM_CLK_90) are the basic clocks supplied to  
most modules and sub-modules on the CPM. The following points should be kept in mind:  
¥
¥
¥
BUS_CLK and BUS_CLK_90 are supplied to the 60x bus and to the core.  
Many modules use both clocks (SIU, serials)  
The external clock, CLKIN, is the same as BUS_CLK  
9.7 PLL Pins  
Table 9-3 shows dedicated PLL pins.  
Table 9-3. Dedicated PLL Pins  
Signal  
Description  
VCCSYN1 Drain voltageÑAnalog VDD dedicated to core analog PLL circuits. To ensure core clock stability, Þlter the  
power to the VCCSYN1 input with a circuit similar to the one in Figure 9-2. To Þlter as much noise as  
possible, place the circuit as close as possible to VCCSYN1. The 0.1-µF capacitor should be closest to  
VCCSYN1, followed by the 10-µF capacitor, and Þnally the 10-W resistor to Vdd. These traces should be  
kept short and direct.  
VCCSYN Drain voltageÑAnalog VDD dedicated to analog main PLL circuits. To ensure internal clock stability, Þlter  
the power to the VCCSYN input with a circuit similar to the one in Figure 9-2. To Þlter as much noise as  
possible, place the circuit should as close as possible to VCCSYN. The 0.1-µF capacitor should be closest  
to VCCSYN, followed by the 10-µF capacitor, and Þnally the 10-W resistor to Vdd. These traces should be  
kept short and direct.  
GNDSYN Source voltageÑAnalog VSS dedicated to analog main PLL circuits. Should be provided with an extremely  
low impedance path to ground and should be bypassed to VCCSYN by a 0.1-µF capacitor located as close  
as possible to the chip package. The user should also bypass GNDSYN to VCCSYN with a 0.01-µF  
capacitor as close as possible to the chip package.  
XFC  
External Þlter capacitorÑConnects to the off-chip capacitor for the main PLL Þlter. One terminal of the  
capacitor is connected to XFC while the other terminal is connected to VCCSYN.  
30 MW is the minimum parasitic resistance value that ensures proper PLL operation when connected in  
parallel with the XFC capacitor. XFC capacitor values are shown in the table below:  
Multiplication  
Factor  
2 Volts (Minimum)  
2.5 Volts (Maximum)  
Unit  
1 £ Factor £ 4  
XFC = Factor * 935- 90  
XFC = Factor * 1370  
XFC = Factor * 680 - 90  
XFC = Factor * 970  
pF  
pF  
Factor > 4  
Note that the multiplication factor ranges between 1 and 4,096. See the PLLMF Þeld  
description in Section 9.9, ÒSystem Clock Mode Register (SCMR).Ó  
Figure 9-2 shows the Þltering circuit for VCCSYN and VCCSYN1, described in Table 9-3.  
MOTOROLA  
Chapter 9. Clocks and Power Control  
9-7  
         
Part III.The Hardware Interface  
VDD  
VCCSYN  
10 W  
10 µF  
0.1 µF  
Figure 9-2. PLL Filtering Circuit  
9.8 System Clock Control Register (SCCR)  
The system clock control register (SCCR), shown in Figure 9-3, is memory-mapped into  
the MPC8260Õs internal space.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10 11 12  
13  
14 15  
Ñ
Ñ
R/W  
Addr  
Bits  
0x10C80  
16 17 18 19 20 21 22 23 24 25 26 27 28  
29  
CLPD DFBRG  
01  
30 31  
Field  
Reset  
R/W  
Ñ
Ñ
0
R/W  
0x10C82  
Addr  
Figure 9-3. System Clock Control Register (SCCR)  
Table 9-4 describes SCCR Þelds.  
Table 9-4. SCCR Field Descriptions  
Defaults  
Bits  
Name  
Description  
POR Hard Reset  
0Ð28  
29  
Ñ
Reserved  
CLPD  
0
Unaffected  
CPM low power disable.  
0 Default. CPM does not enter low power mode when the core enters low  
power mode.  
1 CPM and SIU enter low power mode when the core does. This may be  
useful for debug tools that use the assertion of QREQ as an indication of  
breakpoint in the core.  
9-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part III.The Hardware Interface  
Table 9-4. SCCR Field Descriptions  
Defaults  
Bits  
Name  
Description  
POR Hard Reset  
30Ð31 DFBRG 01  
Unaffected  
Division factor of BRGCLK from VCO_OUT (twice the CPM clock). DeÞnes  
the BRGCLK frequency. Changing the value does not result in a loss of lock  
condition. The BRGCLK is divided from the CPM clock.  
00 Divide by 4  
01 Divide by 16 (normal operation)  
10 Divide by 64  
11 Divide by 128  
9.9 System Clock Mode Register (SCMR)  
The system clock mode register (SCMR), shown in Figure 9-4, holds the parameters which  
determine the output clock frequencies. To understand how these values interact, see  
Section 9.4, ÒMain PLL.Ó  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field  
Ñ
CORECNF  
BUSDF  
CPMDF  
Reset  
R/W  
Addr  
Bits  
See Table 9-5  
R
0x10C88  
16  
17  
Ñ
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
PLLDF  
PLLMF  
Reset  
R/W  
See Table 9-5  
R
Addr  
0x10C8A  
Figure 9-4. System Clock Mode Register (SCMR)  
Table 9-5 describes SCMR Þelds.  
Table 9-5. SCMR Field Descriptions  
Defaults  
Hard Reset  
Bits  
Name  
Description  
POR  
0Ð2  
Ñ
Ñ
Ñ
Reserved  
3Ð7 CORECNF ConÞg pins Unaffected Core conÞguration. PLL conÞguration of the core.  
8Ð11  
12Ð15  
16Ð18  
BUSDF  
CPMDF  
Ñ
ConÞg pins Unaffected 60x bus division factor  
ConÞg pins Unaffected CPM division factor. This value is always 1.  
Ñ
Ñ
Reserved  
MOTOROLA  
Chapter 9. Clocks and Power Control  
9-9  
       
Part III.The Hardware Interface  
Table 9-5. SCMR Field Descriptions (Continued)  
Defaults  
POR Hard Reset  
Bits  
Name  
Description  
19  
PLLDF  
ConÞg pins Unaffected PLL pre-divider value. Ensures that PLLMF is an integer value  
regardless of whether CPM_CLK/CLKIN is an integer.  
0 The ratio, CPM_CLK/CLKIN, is an integer  
1 The ratio, CPM_CLK/CLKIN, is not an integer  
PLL division factor can be either 1 or 2.  
20Ð31  
PLLMF  
ConÞg pins Unaffected PLL multiplication factor. (A PLLMF value of 0x000 corresponds to 1,  
and 0xFFF to 4,096.) The VCO output is divided to generate the  
feedback signal that goes to the phase comparator. PLLMF and  
PLLDF bits control the value of the divider in the PLL feedback loop.  
The phase comparator determines the phase shift between the  
feedback signal and the reference clock. This difference causes an  
increase or decrease in the VCO output frequency.  
The relationships among these parameters are described in the formulas in Figure 9-5.  
CPM_CLK  
CLKIN  
PLLMF =  
´ (PLLDF + 1) Ð 1  
(PLLMF + 1) ´ 2  
(PLLDF + 1)  
BUSDF =  
Ð 1  
Figure 9-5. Relationships of SCMR Parameters  
9.10 Basic Power Structure  
The I/O buffers, logic, and clock block are fed by a 3.3-V power supply that allows them to  
function in a TTL-compatible voltage range. Internal logic can be fed by a 2.0-V source  
considerably reducing power consumption. The PLL is fed by a separate power supply  
(VCCSYN) to achieve a highly stable output frequency. The VCCSYN value is equal to the  
internal supply (2.0 V).  
The MPC8260 supports the two following power modes:  
¥
¥
Full mode: Both the chip PLL and core PLL work.  
Stop mode: Main PLL is working, core PLL is stopped, internal clocks are disabled.  
Ñ When stop mode is entered, software sets the sleep bit in the core (HID0[10] =  
1) and the clock block freezes all clocks to the chip (the core clock and all other  
clocks) the main PLL remains active  
Ñ When stop mode is exited, the SRESET_B input must be asserted to the chip, the  
clock block resumes clocks to all blocks and then releases the reset to the whole  
chip.  
9-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Chapter 10  
Memory Controller  
100  
1T00 he memory controller is responsible for controlling a maximum of twelve memory banks  
shared by a high performance SDRAM machine, a general-purpose chip-select machine  
(GPCM), and three user-programmable machines (UPMs). It supports a glueless interface  
to synchronous DRAM (SDRAM), SRAM, EPROM, ßash EPROM, burstable RAM,  
regular DRAM devices, extended data output DRAM devices, and other peripherals. This  
ßexible memory controller allows the implementation of memory systems with very  
speciÞc timing requirements.  
¥
The SDRAM machine provides an interface to synchronous DRAMs, using  
SDRAM pipelining, bank interleaving, and back-to-back page mode to achieve the  
highest performance.  
¥
The GPCM provides interfacing for simpler, lower-performance memory resources  
and memory-mapped devices. The GPCM has inherently lower performance  
because it does not support bursting. For this reason, GPCM-controlled banks are  
used primarily for boot-loading and access to low-performance memory-mapped  
peripherals.  
¥
The UPM supports address multiplexing of the external bus, refresh timers, and  
generation of programmable control signals for row address and column address  
strobes to allow for a glueless interface to DRAMs, burstable SRAMs, and almost  
any other kind of peripheral. The refresh timers allow refresh cycles to be initiated.  
The UPM can be used to generate different timing patterns for the control signals  
that govern a memory device. These patterns deÞne how the external control signals  
behave during a read, write, burst-read, or burst- write access request. Refresh timers  
are also available to periodically generate user-deÞned refresh cycles.  
Unless stated otherwise, this chapter describes the 60x bus memory controller. The local  
bus memory controller provides the same functionality as the 60x bus memory controller  
except 64-bit port size ECC and external master support.  
MOTOROLA  
Chapter 10. Memory Controller  
10-1  
       
Part III.The Hardware Interface  
The MPC8260 supports the following new features as compared to the MPC860 and  
MPC850.  
¥
The synchronous DRAM machine enables back-to-back memory read or write  
operations using page mode, pipelined operation and bank interleaving for  
high-performance systems.  
¥
The memory controller supports the local bus and the 60x bus in parallel. The 60x  
bus and the local bus share twelve memory banks as well as two SDRAM machines,  
three user-programmable machines (UPMs) and GPCMs.  
¥
¥
¥
¥
¥
The memory controller supports atomic operation.  
The memory controller supports read-modify-write (RMW) data parity check.  
The memory controller supports ECC data check and correction.  
Two data buffer controls (one for the local bus).  
ECC/parity byte select pin, which enables a fast, glueless connection to ECC/  
RMW-parity devices.  
¥
18-bit address and 32-bit local data bus memory controller. The local bus memory  
controller supports the following:  
Ñ 8-, 16-, and 32-bit port sizes  
Ñ Parity checking and generation  
Ñ Ability to work in parallel with the 60x bus memory controller  
Unless stated otherwise, this chapter describes the 60x bus memory controller. The  
local bus memory controller provides the same functionality as the 60x bus memory  
controller except 64-bit port size, ECC, and external master support.  
¥
¥
Flexible chip-select assignmentÑThe 60x bus and local bus share twelve  
chip-select lines (controlled by a memory controller bank). The user can allocate the  
twelve banks as needed between the 60x bus and the local bus.  
Flexible UPM assignmentÑThe user can assign any of the three UPMs to the 60x  
bus or the Local bus  
Figure 10-1 shows the dual-bus architecture.  
10-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part III.The Hardware Interface  
MPC8260  
External  
Master  
CPM/PCI  
Core  
A[0Ð31]  
D[0Ð63]  
60x Address [0Ð31]  
60x Data[0Ð63]  
60x Address  
Bus Interface  
60x Data  
Bus Interface  
60x Memory  
Control Signals  
SDRAM  
60x  
60x  
Memory  
Devices  
Memory  
GPCM  
60x  
Controller  
Slave  
60x-to-Local  
Transactions  
3 UPM  
Arrays  
CS[0Ð11]  
Local  
Slave  
Local  
Local  
Memory  
Devices  
Memory  
Controller  
GPCM  
Local Memory  
Control Signals  
CPM/Local  
Master  
SDRAM  
Local Address LA[14Ð31]  
Bus Interface  
Local Address [0Ð31]  
Local Data [0Ð63]  
Local Data  
LD[0Ð31]  
Bus Interface  
Figure 10-1. Dual-Bus Architecture  
10.1 Features  
The memory controllerÕs main features are as follows:  
¥
Twelve memory banks  
Ñ 32-bit address decoding with mask  
Ñ Variable block sizes (32 Kbytes to 4 Gbytes)  
Ñ Three types of data errors check/correction:  
Ð Normal odd/even parity  
Ð Read-modify-write (RMW) odd/even parity for single accesses  
Ð ECC  
MOTOROLA  
Chapter 10. Memory Controller  
10-3  
       
Part III.The Hardware Interface  
Ñ Write-protection capability  
Ñ Control signal generation machine selection on a per-bank basis  
Ñ Flexible chip-select assignment between the 60x bus and the local bus  
Ñ Supports internal or external masters on the 60x bus  
Ñ Data buffer controls activated on a per-bank basis  
Ñ Atomic operation  
Ñ Extensive external memory-controller/bus-slave support  
Ñ ECC/parity byte-select  
Ñ Data pipeline to reduce data setup time for synchronous devices  
¥
Synchronous DRAM machine (60x or local bus)  
Ñ Provides the control functions and signals for glueless connection to  
JEDEC-compliant SDRAM devices  
Ñ Back-to-back page mode for consecutive, back-to-back accesses  
Ñ Supports 2-, 4- and 8-way bank interleaving  
Ñ Supports SDRAM port size of 64-bit (60x only), 32-bit, 16-bit and 8-bit  
Ñ Supports external address and/or command lines buffering  
General-purpose chip-select machine (GPCM)Ñ60x or local bus  
Ñ Compatible with SRAM, EPROM, FEPROM, and peripherals  
Ñ Global (boot) chip-select available at system reset  
Ñ Boot chip-select support for 8-, 16-, 32-, and 64-bit devices  
Ñ Minimum two clock accesses to external device  
Ñ Eight byte write enable signals (WE)Ñfour on the local bus  
Ñ Output enable signal (OE)  
¥
Ñ External access termination signal (GTA)  
¥
Three UPMs  
Ñ Each machine can be assigned to the 60x or local bus.  
Ñ Programmable-array-based machine controls external signal timing with a  
granularity of up to one quarter of an external bus clock period  
Ñ User-speciÞed control-signal patterns run when an internal or external master  
requests a single-beat or burst read or write access.  
Ñ UPM refresh timer runs a user-speciÞed control signal pattern to support refresh  
Ñ User-speciÞed control-signal patterns can be initiated by software  
10-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
Ñ Each UPM can be deÞned to support DRAM devices with depths of 64, 128, 256,  
and 512 Kbytes, and 1, 2, 4, 8, 16, 32, 64, 128, and 256 Mbytes  
Ð Chip-select line  
Ð Byte-select lines  
Ð Six external general-purpose lines  
Ñ Supports 8-, 16-, 32-, and 64-bit memory port sizes, 8-, 16-, and 32-bit port sizes  
on the local bus  
Ñ Page mode support for successive transfers within a burst  
Ñ Internal address multiplexing for all on-chip bus masters supporting 64-, 128-,  
256-, and 512-Kbyte, and 1-, 2-, 4-, 8-, 16-, 32-, 64-, 128-, 256-Mbyte page  
banks  
10.2 Basic Architecture  
The memory controller consists of three basic machines:  
¥
¥
¥
Synchronous DRAM machine  
General-purpose chip-select machine (GPCM)  
Three UPMs  
Each bank can be assigned to any one of these machines via BRx[MS] as shown in  
Figure 10-2. The MS and MxMR[BS] bits (for UPMs) assign banks to the 60x bus or local  
bus, as shown in Figure 10-2. Addresses are decoded by comparing (A[0Ð16] bit-wise and  
ORx[AM]) with BRx[BA]. If an address match occurs in multiple banks, the lowest  
numbered bank has priority. However, if a 60x bus access hits a bank allocated to the local  
bus, the access is transferred to the local bus. Local bus access hits to 60x assigned banks  
are ignored.  
When a memory address matches BRx[BA], the corresponding machine takes ownership  
of the external signals that control access and maintains control until the cycle ends.  
MOTOROLA  
Chapter 10. Memory Controller  
10-5  
   
Part III.The Hardware Interface  
MxMR[BS]  
Bank 0  
Bank 1  
Bank 2  
Bank 3  
MS  
MS  
MS  
MS  
60x  
User-Programmable  
Machine (A/B/C)  
Local  
60x  
60x SDRAM  
Machine  
Local SDRAM  
Machine  
Local  
60x  
60x General-Purpose  
Chip-Select Machine  
Bank 10  
Bank11  
MS  
MS  
Local General-Purpose  
Chip-Select Machine  
Local  
Figure 10-2. Memory Controller Machine Selection  
Some features are common to all machines.  
¥
¥
A 17-bit most-signiÞcant address decode on each memory bank  
The block size of each memory bank can vary between 32 Kbytes (1 Mbyte for  
SDRAM) and 4 Gbytes (128 Mbytes for SDRAM).  
¥
¥
Normal parity may be generated and checked for any memory bank.  
Read-modify-write parity may be generated and checked for any memory bank with  
either 32- or 64-bit port size. Using RMW parity on 32-bit port size bank, requires  
the bus to be in strict 60x mode (BCR[ETM] = 0. See Section 4.3.2.1, ÒBus  
ConÞguration Register (BCR).Ó  
¥
¥
¥
ECC may be generated and checked for any memory bank with a 64-bit port size  
Each memory bank can be selected for read-only or read/write operation.  
Each memory bank can use data pipelining, which reduces the required data setup  
time for synchronous devices.  
¥
Each memory bank can be controlled by an external memory controller or bus slave.  
The memory controller functionality minimizes the need for glue logic in MPC8260-based  
systems. In Figure 10-3, CS0 is used with the 16-bit boot EPROM with BR0[MS]  
defaulting to select the GPCM. CS1 is used as the RAS signal for 64-bit DRAM with  
BR1[MS] conÞgured to select UPMA. BS[0Ð7] are used as CAS signals on the DRAM.  
10-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part III.The Hardware Interface  
EPROM  
MPC8260  
Address  
Address  
CE  
CS0  
GPL1/OE  
BS/WE[0Ð7]  
Data  
GPCM  
OE  
WE  
Data  
DRAM  
Address  
RAS  
CS1  
UPMA  
CAS[0Ð7]  
W
GPLx  
Data  
Figure 10-3. Simple System Configuration  
Implementation differences between the supported machines are described in the  
following:  
¥
The SDRAM machine provides a glueless interface to JEDEC-compliant SDRAM  
devices, and using SDRAM pipelining, page mode, and bank interleaving delivers  
very high performance. To allow Þne tuning of system performance, the SDRAM  
machine provides two types of page modes selectable per memory bank:  
Ñ Page mode for consecutive back-to-back accesses (normal operation)  
Ñ Page mode for intermittent accesses  
SDRAM machines are available on the 60x and local buses; each memory bank can  
be assigned to any SDRAM machine.  
¥
¥
The GPCM provides a glueless interface to EPROM, SRAM, ßash EPROM  
(FEPROM), and other peripherals. The GPCM is available on both buses on  
CS[0Ð11]. CS0 also functions as the global (boot) chip-select for accessing the boot  
EPROM or FLASH device. The chip-select allows 0 to 30 wait states.  
The UPMs provide a ßexible interface to many types of memory devices. Each UPM  
can control the address multiplexing for accessing DRAM devices and the timings  
of BS[0Ð7] and GPL. Each UPM can be assigned either to the 60x or to the local  
bus. Each memory bank can be assigned to any UPM.  
Each UPM is a programmable RAM-based machine. The UPM toggles the memory  
controller external signals as programmed in RAM when an internal or external  
master initiates any external read or write access. The UPM also controls address  
multiplexing, address increment, and transfer acknowledge (TA) assertion for each  
memory access. The UPM speciÞes a set of signal patterns for a user-speciÞed  
number of clock cycles. The UPM RAM pattern run by the memory controller is  
MOTOROLA  
Chapter 10. Memory Controller  
10-7  
   
Part III.The Hardware Interface  
selected according to the type of external access transacted.At every clock cycle, the  
logical value of the external signals speciÞed in the RAM array is output on the  
corresponding UPM pins.  
Figure 10-4 shows a basic conÞguration.  
Internal/External Memory Access Request Select  
Address (A),  
Address  
Type (AT)  
Address  
Comparator  
Bank Select  
SDRAM Machine  
UPMx  
GPCM  
Signals  
Timing  
Generator  
MS/BS  
Fields  
MUX  
External Signals  
Figure 10-4. Basic Memory Controller Operation  
The SDRAM mode registers (LSDMR and PSDMR) deÞne the global parameters for the  
60x and local SDRAM devices. MachineA/B/C mode registers (MxMR) deÞne most of the  
global features for each UPM. GPCM parameters are deÞned in the option register (ORx).  
Some SDRAM and UPM parameters are also deÞned in ORx.  
10.2.1 Address and Address Space Checking  
The deÞned base address is written to the BRx. The bank size is written to the ORx. Each  
time a bus cycle access is requested on the 60x or local bus, addresses are compared with  
each bank. If a match is found on a memory controller bank, the attributes deÞned in the  
BRx and ORx for that bank are used to control the memory access. If a match is found in  
more than one bank, the lowest-numbered bank handles the memory access (that is, bank 0  
has priority over bank 1).  
Note that although 60x bus accesses that hit a bank allocated to the local bus are transferred  
to the local bus, local bus access hits to banks allocated to the 60x bus are ignored.  
60x-to-local bus transactions has priority over regular memory bank hits.  
10-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part III.The Hardware Interface  
10.2.2 Page Hit Checking  
The SDRAM machine supports page-mode operation. Each time a page is activated on the  
SDRAM device, the SDRAM machine stores its address in a page register. The page  
information, which the user writes to the ORx register, is used along with the bank size to  
compare page bits of the address to the page register each time a bus-cycle access is  
requested. If a match is found together with bank match, the bus cycle is deÞned as a page  
hit. An open page is automatically closed by the SDRAM machine if the bus becomes idle,  
unless ORx[PMSEL] is set.  
10.2.3 Error Checking and Correction (ECC)  
ECC can be conÞgured for any bank as long as it is assigned to the 60x bus and is connected  
to a 64-bit port size memory. ECC is generated and checked on a 64-bit basis using DP[0Ð7]  
for the bank if BRx[DECC] = 11. If ECC is used, single errors can be corrected and all  
double-bit errors can be detected.  
10.2.4 Parity Generation and Checking  
Parity can be conÞgured for any bank, if it is preferred. Parity is generated and checked on  
a per-byte basis using DP[0Ð7] or LDP[0Ð3] for the bank if BR[DECC] = 01 for normal  
parity and 10 for RMW parity. SIUMCR[EPAR] determines the global type of parity (odd  
or even).  
Note that RMW parity can be used only for 32- or 64-bit port size banks. Also, using RMW  
parity on a 32-bit port size bank, requires that the bus is placed is strict 60x mode. This is  
done by setting BCR[ETM] (BCR[LETM] for the local bus) see Section 4.3.2.1, ÒBus  
ConÞguration Register (BCR),Ó for more details.  
10.2.5 Transfer Error Acknowledge (TEA) Generation  
The memory controller asserts the transfer error acknowledge signal (TEA) (if enabled) in  
the following cases:  
¥
An unaligned or burst access is attempted to internal MPC8260 space (registers or  
dual-port RAM).  
¥
¥
The core or an external master attempts a burst access to the local bus address space  
A bus monitor timeout  
10.2.6 Machine Check Interrupt (MCP) Generation  
The memory controller asserts machine check interrupt (MCP) in the following cases:  
¥
¥
¥
A parity error  
An ECC double-bit error  
An ECC single bit error when the maximum number of ECC errors has been reached  
MOTOROLA  
Chapter 10. Memory Controller  
10-9  
                 
Part III.The Hardware Interface  
10.2.7 Data Buffer Controls (BCTLx)  
The memory controller provides two data buffer controls for the 60x bus (BCTL0 and  
BCTL1) and one for the local bus (LWR). These controls are activated when a GPCM- or  
UPM-controlled bank is accessed. The BCTLx controls can be disabled by setting  
ORx[BCTLD]. Access to SDRAM-machine controlled bank does not activate the BCTLx  
controls. The BCTL signals are asserted on the rising edge of CLKIN on the Þrst cycle of  
the memory controller operation. They are negated on the rising edge of CLKIN after the  
last assertion of PSDVAL of the access is asserted. (See Section 10.2.13, ÒPartial DataValid  
Indication (PSDVAL).Ó) If back-to-back memory controller operations are pending,  
BCTLx is not negated.  
The BCTL signals have a programmable polarity. See Section 4.3.2.6, ÒSIU Module  
ConÞguration Register (SIUMCR).Ó  
10.2.8 Atomic Bus Operation  
The MPC8260 supports the following kinds of atomic bus operations BRx[ATOM]:  
¥
Read-after-write (RAWA). When a write access hits a memory bank in which  
ATOM = 01, the MPC8260 locks the bus for the exclusive use of the accessing  
master (internal or external).  
While the bus is locked, no other device can be granted the bus. The lock is released  
when the master that created the lock access the same bank with a read transaction.  
If the master fails to release the lock within 256 bus clock cycles, the lock is released  
and a special interrupt is generated. This feature is intended for CAM operations.  
¥
Write-after-read (WARA). When a read access hit a memory bank in which  
ATOM = 10, the MPC8260 locks the bus for the exclusive use of the accessing  
master (internal or external).  
During the lock period, no other device can be granted bus mastership. The lock is  
released when the device that created the lock access the same bank with a write  
transaction. If the device fails to release the lock within 256 bus clock cycles, the  
lock is released and a special interrupt is generated.  
Note that this mechanism does not replace the PowerPC reservation mechanism.  
10.2.9 Data Pipelining  
Multiple-MPC8260 systems that use that use data checking, such as ECC or parity, face a  
timing problem when synchronous memories, such as SDRAM, are used. Because these  
devices can output data every cycle and because the data checking requires additional data  
setup time, the timing constraints are extremely hard to meet. In such systems, the user  
should set the data pipelining bit, BRx[DR]. This creates data pipelining of one stage within  
the memory controller in which the data check calculations are done, thus eliminating the  
additional data setup time requirement.  
10-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part III.The Hardware Interface  
Note that this feature cannot be used with L2 cacheable banks and that in systems that  
involve both PowerQUICC II-type masters and 60x compatible master, this feature can still  
be used on the 60x bus under the following restrictions:  
1. The arbiter and the memory controller are in the same MPC8260.  
2. The register Þeld BCR[NPQM] is setup correctly.  
See ÒSection 10.9, ÒExternal Master Support (60x-Compatible Mode)Ó and  
ÒSection 4.3.2.1, ÒBus ConÞguration Register (BCR).Ó  
10.2.10 External Memory Controller Support  
The MPC8260 has an option to allocate speciÞc banks (address spaces) to be controlled by  
an external memory controller or bus slave, while retaining all the bank properties: port  
size, data check/correction, atomic operation, and data pipelining. This is done by  
programming BRx and ORx[AM] and by setting the external memory controller bit,  
BRx[EMEMC]. This action automatically assigns the bank to the 60x bus. For an access  
that hits the bank, all bus acknowledgment signals (such as AACK, PSDVAL, and TA) and  
the memory-device control strobes are driven by an external memory controller or slave. If  
the device that initiates the transaction is internal to the MPC8260, the memory controller  
handles the port size, data checking, atomic locking, and data pipelining as if the access  
were governed by it.  
This feature allows multiple MPC8260 systems to be connected in 60x-compatible mode  
without loosing functionality and performance. It also make it easy to connect other  
60x-compatible slaves on the 60x bus.  
10.2.11 External Address Latch Enable Signal (ALE)  
The memory controller provides control for an external address latch, needed on the 60x  
bus in 60x compatible mode. ALE is asserted for one clock cycle on the Þrst cycle of each  
memory-controller transaction. In this section, whenever ALE is not on a timing diagram,  
assume that it is asserted on the Þrst cycle in which CS can be asserted. Note that ALE is  
relevant only on the 60x bus and only in 60x-compatible mode.  
10.2.12 ECC/Parity Byte Select (PBSE)  
Systems that use ECC or read-modify-write parity, require an additional memory device  
that requires byte-select like a normal data device. ANDing BS[0Ð7] through external logic  
to achieve the logical function of this byte-select can affect the memory access timing  
because it adds a delay to the byte-select path. The MPC8260Õs memory controller provides  
optional byte-select pins that are an internal AND of the eight byte selects, allowing  
glueless, faster connection to ECC/RMW-parity devices.  
This option is enabled by setting SIUMCR[PBSE], as described in Section 4.3.2.6, ÒSIU  
Module ConÞguration Register (SIUMCR).Ó  
MOTOROLA  
Chapter 10. Memory Controller  
10-11  
           
Part III.The Hardware Interface  
10.2.13 Partial Data Valid Indication (PSDVAL)  
The 60x and local buses have an internal 64-bit data bus. According to the 60x bus  
speciÞcation, TA is asserted when up to a double word of data is transferred. Because the  
MPC8260 supports memories with port sizes smaller than 64 bits, there is a need for partial  
data valid indication. The memory controller uses PSDVAL to indicate that data is latched  
by the memory on write accesses or valid data is present on read accesses. The quantity of  
the data depends on the memory port size and the transfer size. The memory controller  
accumulates PSDVAL assertions, and when a double word (or the transfer size) is  
transferred, the memory controller asserts TA to indicate that a 60x data beat was  
transferred. Table 10-1 shows the number of PSDVAL assertions needed for one TA  
assertion under various circumstances.  
Table 10-1. Number of PSDVAL Assertions Needed for TA Assertion  
Port Size  
Transfer Size  
PSDVAL Assertions  
TA Assertions  
64  
32  
32  
16  
16  
16  
8
Any  
1
2
1
4
2
1
8
4
2
1
1
1
1
1
1
1
1
1
1
1
Double word  
Word/half word/byte (32-bit aligned)  
Double Word  
Word  
Half/byte  
Double word  
Word  
8
8
Half  
8
Byte  
Figure 10-5 shows a double-word transfer on 32-bit port size memory.  
10-12  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part III.The Hardware Interface  
Clock  
External  
Data Bus  
(32 msb)  
Upper 4 bytes  
Lower 4 bytes  
PSDVAL  
Internal  
Data Bus  
(32 msb)  
Upper 4 bytes  
Internal  
Data Bus  
(32 lsb)  
Lower 4 bytes  
TA  
Figure 10-5. Partial Data Valid for 32-Bit Port Size Memory, Double-Word Transfer  
10.3 Register Descriptions  
Table 10-2 lists registers used to control the 60x bus memory controller.  
Table 10-2. 60x Bus Memory Controller Registers  
Abbreviation  
BR0ÐBR11  
Name  
Reference  
Base register banks 0Ð11  
Section 10.3.1  
Section 10.3.2  
Section 10.3.3  
OR0ÐOR11]  
PSDMR  
LSDMR  
MAMR  
MBMR  
MCMR  
MDR  
Option register banks 0Ð11  
60x bus SDRAM machine mode register  
Local bus SDRAM machine mode register Section 10.3.4  
UPMA mode register  
Section 10.3.5  
UPMB mode register  
UPMC mode register  
Memory data register  
Section 10.3.6  
Section 10.3.7  
Section 10.3.12  
Section 10.3.8  
Section 10.3.10  
Section 10.3.9  
Section 10.3.11  
Section 10.3.13  
Section 10.3.14  
MAR  
Memory address register  
MPTPR  
PURT  
Memory refresh timer prescaler register  
60x bus assigned UPM refresh timer  
60x bus assigned SDRAM refresh timer  
Local bus assigned UPM refresh timer  
Local bus assigned SDRAM refresh timer  
60x bus error status and control registers  
Local bus error status and control regs  
PSRT  
LURT  
LSRT  
TESCRx  
LTESCRx  
MOTOROLA  
Chapter 10. Memory Controller  
10-13  
       
Part III.The Hardware Interface  
10.3.1 Base Registers (BRx)  
The base registers (BR0ÐBR11) contain the base address and address types that the  
memory controller uses to compare the address bus value with the current address accessed.  
Each register also includes a memory attribute and selects the machine for memory  
operation handling. Figure 10-6 shows the BRx register format.  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field  
Reset  
R/W  
BA  
Depends on reset conÞguration sequence. See Section 5.4.1, ÒHard Reset ConÞguration Word.Ó  
R/W  
Addr  
0x10100 (BR0); 0x10108 (BR1); 0x10110 (BR2); 0x10118 (BR3); 0x10120 (BR4); 0x10128 (BR5); 0x10130  
(BR6); 0x10138 (BR7); 0x10140 (BR8); 0x10148 (BR9); 0x10150 (BR10); 0x10158 (BR11)  
Bit  
16  
17  
18  
19  
20 21  
22  
23 24 25  
WP MS  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
BA  
Ñ
PS  
DECC  
EMEMC  
ATOM  
DR  
V
1
0000_0000_0000_0000  
Depends on reset conÞguration sequence. See Section 5.4.1, ÒHard Reset ConÞguration Word.Ó  
Addr 0x10102 (BR0); 0x1010A (BR1); 0x10112 (BR2); 0x1011A (BR3); 0x10122 (BR4); 0x1012A (BR5); 0x10132  
(BR6); 0x1013A (BR7); 0x10142 (BR8); 0x1014A (BR9); 0x10152 (BR10); 0x1015A (BR11)  
1
After a system reset, the V bit is set in BR0 and reset in BR[1-11].  
Figure 10-6. Base Registers (BRx)  
Table 10-3 describes BRx Þelds.  
Table 10-3. BRx Field Descriptions  
Bits  
Name  
Description  
0Ð16  
BA  
Base address. The upper 17 bits of each base address register are compared to the address on  
the address bus to determine if the bus master is accessing a memory bank controlled by the  
memory controller. Used with ORx[BSIZE].  
17Ð18  
19Ð20  
Ñ
Reserved, should be cleared.  
PS  
Port size. SpeciÞes the port size of this memory region.  
01 8-bit  
10 16-bit  
11 32-bit  
00 64-bit (60x bus only)  
21Ð22 DECC Data error correction and checking. SpeciÞes the method for data error checking and correction.  
See Section 10.2.3, ÒError Checking and Correction (ECC),Ó and Section 10.2.4, ÒParity  
Generation and Checking.Ó  
00 Data errors checking disabled  
01 Normal parity checking  
10 Read-modify-write parity checking  
11 ECC correction and checking  
10-14  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part III.The Hardware Interface  
Table 10-3. BRx Field Descriptions (Continued)  
Bits  
Name  
Description  
23  
WP  
Write protect. Can restrict write accesses within the address range of a BR. An attempt to write to  
this address range while WP = 1 can cause TEA to be asserted by the bus monitor logic (if  
enabled) which terminates the cycle.  
0 Read and write accesses are allowed.  
1 Only read accesses are allowed. The memory controller does not assert CSx and PSDVAL on  
write cycles to this memory bank. MSTAT[WPER] is set if a write to this memory bank is  
attempted.  
24Ð26  
MS  
Machine select. speciÞes machine select for the memory operations handling and assigns the  
bank to the 60x or local bus if GPCM or SDRAM are selected. If UPMx is selected, the bus  
assignment is determined by MxMR[BSEL].  
000 GPCMÑ60x bus (reset value)  
001 GPCMÑlocal bus  
010 SDRAMÑ60x Bus  
011 SDRAMÑlocal bus  
100 UPMA  
101 UPMB  
110 UPMC  
111 Reserved  
27  
EMEMC External MEMC enable. Overrides MSEL and assigns the bank to the 60x bus. However, other  
BRx Þelds remain in effect. See Section 10.2.10, ÒExternal Memory Controller Support.Ó  
0 Access are handled by the memory controller according to MSEL.  
1 Access are handled by an external memory controller (or other slave) on the 60x bus. The  
external memory controller is expected to assert AACK, TA, and PSDVAL.  
28Ð29 ATOM Atomic operation. See Section 10.2.8, ÒAtomic Bus Operation.Ó  
00 The address space controlled by the memory controller bank is not used for atomic operations.  
01 Read-after-write-atomic (RAWA).Writes to the address space handled by the memory  
controller bank cause the MPC8260 to lock the bus for the exclusive use of the master. The  
lock is released when the master performs a read operation from this address space. This  
feature is intended for CAM operations.  
10 Write-after-read-atomic (WARA). Reads from the address space handled by the memory  
controller bank cause the MPC8260 to lock the bus for the exclusive use of the accessing  
device. The lock is released when the device performs a write operation to this address space.  
11 Reserved  
Note that If the device fails to release the bus, the lock is released after 256 clock cycles.  
30  
31  
DR  
Data pipelining. See Section 10.2.9, ÒData Pipelining.Ó  
0 No data pipelining is done.  
1 Data beats of accesses to the address space controlled by the memory controller bank are  
delayed by one cycle.This feature is intended for memory regions that use ECC or parity checks  
and need to improve data setup time.  
V
Valid bit. Indicates that the contents of the BRx and ORx pair are valid. The CS signal does not  
assert until V is set.  
0 This bank is invalid.  
1 This bank is valid  
Notes: An access to a region that has no V bit set may cause a bus monitor time-out. After a  
system reset, BR0[V] is set.  
MOTOROLA  
Chapter 10. Memory Controller  
10-15  
Part III.The Hardware Interface  
10.3.2 Option Registers (ORx)  
The ORx registers deÞne the sizes of memory banks and access attributes. The ORx  
attributes bits support the following three modes of operation as deÞned by BR[MS].  
¥
¥
¥
SDRAM mode  
GPCM mode  
UPM mode  
Figure 10-7 shows the ORx as it is formatted for SDRAM mode.  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field  
Reset  
R/W  
SDAM  
LSDAM...  
0000_0000_0000_0000  
R/W  
Addr 0x10104 (OR0); 0x1010C (OR1); 0x10114 (OR2); 0x1011C (OR3); 0x10124 (OR4); 0x1012C (OR5); 0x10134  
(OR6); 0x1013C (OR7); 0x10144 (OR8); 0x1014C (OR9); 0x10154 (OR10); 0x1015C (OR11)  
Bit  
16  
17  
18  
19  
20  
21  
22  
Ñ
23 24 25  
NUMR  
26  
27  
28  
29  
30  
31  
Field ...LSDAM  
Reset  
BPD  
ROWST  
PMSEL IBID  
Ñ
0000_0000_0000_0000  
R/W  
R/W  
Addr 0x10106 (OR0); 0x1010E (OR1); 0x10116 (OR2); 0x1011E (OR3); 0x10126 (OR4); 0x1012E (OR5); 0x10136  
(OR6); 0x1013E (OR7); 0x10146 (OR8); 0x1014E (OR9); 0x10156 (OR10); 0x1015E (OR11)  
Figure 10-7. Option Registers (ORx)ÑSDRAM Mode  
Table 10-4 describes ORx Þelds in SDRAM mode. For more details see Section 10.4.12,  
ÒSDRAM ConÞguration Examples.Ó  
Table 10-4. ORx Field Descriptions (SDRAM Mode)  
Bits  
Name  
Description  
0Ð4  
SDAM SDRAM address mask. Provides masking for corresponding BRx bits. By masking address bits  
independently, SDRAM devices of different size address ranges can be used. Clearing bits masks  
the corresponding address bit. Setting bits causes the corresponding address bit to be compared  
with the address pins. Address mask bits can be set or cleared in any order, allowing a resource to  
reside in more than one area of the address map. SDAM can be read or written at any time.  
0000_0000_0000 = 4Gbyte  
1111_1111_1111 = 1 Mbyte  
Note: if xSDMR[PBI]=0, the maximum size of the memory bank should not exceed 128 Mbytes.  
10-16  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part III.The Hardware Interface  
Table 10-4. ORx Field Descriptions (SDRAM Mode) (Continued)  
Bits  
Name  
Description  
5Ð11  
SDAM SDRAM address mask. Provides masking for corresponding bits in the associated BRx. By  
masking address bits independently, SDRAM devices of different size address ranges can be  
used. Any clear bit masks the corresponding address bit. Any set bit causes the corresponding  
address bit to be compared with the address pins. Address mask bits can be set or cleared in any  
order, allowing a resource to reside in more than one area of the address map. SDAM can be read  
or written at any time.  
0000000128 Mbyte  
100000064 Mbyte  
110000032 Mbyte  
111000016 Mbyte  
11110008 Mbyte  
11111004 Mbyte  
11111102 Mbyte  
11111111 Mbyte  
12Ð16 LSDAM Lower SDRAM address mask. The user should reset LSDAM to 0x0 to implements a minimum  
size of 1 Mbyte when using SDRAM  
SDRAM Page Information  
17Ð18  
BPD  
Banks per device. Sets the number of internal banks per SDRAM device.  
00 2 internal banks per device  
01 4 internal banks per device  
10 8 internal banks per device (not valid for 128-Mbyte SDRAMs)  
11 Reserved  
Note that for 128-Mbyte SDRAMs, BPD must be 00 or 01.  
19Ð21 ROWST Row start address bit. Sets the demultiplexed row start address bit.The value of ROWST depends  
on SDMR[PBI].  
For xSDMR[PBI] = 0:  
0010 A7  
0100 A8  
For xSDMR[PBI] = 1:  
0000 A0  
0001 A1  
0110 A9  
1000 A10  
...  
1100 A12  
1010 A11  
1100 A12  
1101Ð1111 Reserved  
1110 A13  
Other values are reserved  
22  
Ñ
Reserved  
23Ð25 NUMR Number of row address lines. Sets the number of row address lines in the SDRAM device.  
000 9 row address lines  
001 10 row address lines  
010 11 row address lines  
011 12 row address lines  
100 13 row address lines  
101 14 row address lines  
110 15 row address lines  
111 16 row address lines  
26  
PMSEL Page mode select. Selects page mode for the SDRAM connected to the memory controller bank.  
0 Back-to-back page mode (normal operation). Page is closed when the bus becomes idle.  
1 Page is kept open until a page miss or refresh occurs.  
MOTOROLA  
Chapter 10. Memory Controller  
10-17  
Part III.The Hardware Interface  
Table 10-4. ORx Field Descriptions (SDRAM Mode) (Continued)  
Bits  
Name  
Description  
27  
IBID  
Internal bank interleaving within same device disable. Setting this bit disables bank interleaving  
between internal banks of a SDRAM device connected to the chip-select line. IBID should be set  
in 60x-compatible mode if the SDRAM device is not connected to the BANKSEL pins.  
28Ð31  
Ñ
Reserved, should be cleared.  
Figure 10-8 shows ORx as it is formatted for GPCM mode.  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field  
Reset  
R/W  
AM...  
1111_1110_0000_0000  
R/W  
Addr  
0x10104 (OR0); 0x1010C (OR1); 0x10114 (OR2); 0x1011C (OR3); 0x10124 (OR4); 0x1012C (OR5);  
0x10134 (OR6); 0x1013C (OR7); 0x10144 (OR8); 0x1014C (OR9); 0x10154 (OR10); 0x1015C (OR11)  
Bit  
16  
17 18  
Ñ
19  
20  
21 22  
ACS  
23 24 25  
26  
SCY  
1111  
27  
28  
29  
30  
31  
Ñ
0
Field ...AM  
BCTLD CSNT  
Ñ
SETA TRLX EHTR  
Reset  
R/W  
0
00  
0
1
11  
0
0
1
0
R/W  
Addr 0x10106 (OR0); 0x1010E (OR1); 0x10116 (OR2); 0x1011E (OR3); 0x10126 (OR4); 0x1012E (OR5); 0x10136  
(OR6); 0x1013E (OR7); 0x10146 (OR8); 0x1014E (OR9); 0x10156 (OR10); 0x1015E (OR11)  
Figure 10-8. ORx ÑGPCM Mode  
Table 10-5 describes ORx Þelds in GPCM mode.  
Table 10-5. ORxÑGPCM Mode Field Descriptions  
Bits  
Name  
Description  
0Ð16  
AM  
Address mask. Masks corresponding BRx bits. Masking address bits independently allows external  
devices of different size address ranges to be used.  
0 Corresponding address bits are masked.  
1 The corresponding address bits are used in the comparison with address pins. Address mask bits  
can be set or cleared in any order in the Þeld, allowing a resource to reside in more than one area  
of the address map. AM can be read or written at any time.  
Note: After system reset, OR0[AM] is 1111_1110_0000_0000_0.  
17Ð18  
19  
Ñ
Reserved, should be cleared.  
BCTLD Data buffer control disable. Disables the assertion of BCTLx during access to the current memory  
bank. See Section 10.2.7, ÒData Buffer Controls (BCTLx).Ó  
0 BCTLx is asserted upon access to the current memory bank.  
1 BCTLx is not asserted upon access to the current memory bank.  
20  
CSNT Chip-select negation time. Determines when CS/WE are negated during an external memory write  
access handled by the GPCM. This helps meet address/data hold times for slow memories and  
peripherals.  
0 CS/WE are negated normally.  
1 CS/WE are negated a quarter of a clock earlier.  
Note: After system reset OR0[CSNT] is set.  
10-18  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part III.The Hardware Interface  
Table 10-5. ORxÑGPCM Mode Field Descriptions (Continued)  
Bits  
Name  
Description  
21Ð22  
ACS Address to chip select setup. Can be used when the external memory access is handled by the  
GPCM. It allows the delay of the CS assertion relative to the address change.  
00 CS is output at the same time as the address lines  
01 Reserved  
10 CS is output a quarter of a clock after the address lines  
11 CS is output half a clock after the address lines  
Note: After a system reset, OR0[ACS] = 1.  
23  
Ñ
Reserved, should be cleared.  
24Ð27 SCY Cycle length in clocks. Determines the number of wait states inserted in the cycle, when the GPCM.  
handles the external memory access.Thus it is the main parameter for determining cycle length.The  
total cycle length depends on other timing attribute settings.  
The total memory access length is (2 + SCY) x Clocks.  
If the user selects an external PSDVAL response for this memory bank (by setting the SETA bit),  
SCY is not used.  
0000 = 0 clock cycle wait states...1111 = 15 clock cycles wait states  
Note: After a system reset, OR0[SCY] = 1111.  
28  
SETA External access termination (PSDVAL generation). Used to specify that when the GPCM is selected  
to handle the memory access initiated to this memory region, the access is terminated externally by  
asserting the GTA external pin. In this case, PSDVAL is asserted one clock later on the bus.  
0 PSDVAL is generated internally by the memory controller unless GTA is asserted earlier externally.  
1 PSDVAL is generated after external logic asserts GTA.  
Note: After a system reset, the OR0[SETA] is cleared.  
29  
30  
TRLX Timing relaxed. Works in conjunction with EHTR (bit 30).  
0 Normal timing is generated by the GPCM  
1 Relaxed timing is generated by the GPCM for accesses initiated to this memory region.  
EHTR Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between a  
read access from the current bank and the next access. ORx[29,30] are interpreted as follows:  
00 Normal timing is generated by the memory controller. No additional cycles are inserted.  
01 One idle clock cycle is inserted.  
10 Four idle clock cycles are inserted.  
11 Eight idle clock cycles are inserted.  
31  
Ñ
Reserved, should be cleared.  
10-19  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
Figure 10-9 shows ORx as it is formatted for UPM mode.  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field  
Reset  
R/W  
AM  
0000_0000_0000_0000  
R/W  
Addr  
0x10104 (OR0); 0x1010C (OR1); 0x10114 (OR2); 0x1011C (OR3); 0x10124 (OR4); 0x1012C (OR5);  
0x10134 (OR6); 0x1013C (OR7); 0x10144 (OR8); 0x1014C (OR9); 0x10154 (OR10); 0x1015C (OR11)  
Bit  
16  
17  
18  
19  
20  
21  
Ñ
22  
23  
BI  
24  
25  
26  
Ñ
27  
28  
29  
30  
31  
Ñ
Field AM  
Reset  
Ñ
BCTLD  
EHTR  
0000_0000_0000_0000  
R/W  
R/W  
Addr  
0x10106 (OR0); 0x1010E (OR1); 0x10116 (OR2); 0x1011E (OR3); 0x10126 (OR4); 0x1012E (OR5);  
0x10136 (OR6); 0x1013E (OR7); 0x10146 (OR8); 0x1014E (OR9); 0x10156 (OR10); 0x1015E (OR11)  
Figure 10-9. ORxÑUPM Mode  
Table 10-6 describes the ORx Þelds in UPM mode.  
Table 10-6. Option Register (ORx)ÑUPM Mode  
Bits  
Name  
Description  
0Ð16  
AM  
Address mask. Provides masking for corresponding BRx bits. By masking address bits  
independently, external devices of different size address ranges can be used. Any clear bit masks  
the corresponding address bit. Any set bit causes the corresponding address bit to be used in the  
comparison with the address pins. Address mask bits can be set or cleared in any order in the Þeld,  
allowing a resource to reside in more than one area of the address map. AM can be read or written  
at any time.  
17Ð19  
19  
Ñ
Reserved, should be cleared.  
BCTLD Data buffer control disable. Used to disable the assertion of BCTLx) during access to the current  
memory bank. See Section 10.2.7, ÒData Buffer Controls (BCTLx)Ó.  
0 BCTLx is asserted upon access to the current memory bank.  
1 BCTLx is not asserted upon access to the current memory bank.  
20Ð22  
23  
Ñ
BI  
Reserved, should be cleared.  
Burst inhibit. Indicates if this memory bank supports burst accesses.  
0 The bank supports burst accesses  
1 The bank does not support burst accesses.The UPMx executes burst accesses as series of single  
accesses.  
24Ð28  
Ñ
Reserved, should be cleared.  
29Ð30 EHTR Extended hold time on read accesses. Indicates how many cycles are inserted between a read  
access from the current bank and the next access.  
00 Normal timing is generated by the memory controller. No additional cycles are inserted.  
01 One idle clock cycle is inserted.  
10 Four idle clock cycles are inserted.  
11 Eight idle clock cycles are inserted.  
31  
Ñ
Reserved, should be cleared.  
10-20  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part III.The Hardware Interface  
10.3.3 60x SDRAM Mode Register (PSDMR)  
The 60x SDRAM mode register (PSDMR), shown in Figure 10-10, is used to conÞgure  
operations pertaining to SDRAM.  
Bit  
Field  
Reset  
R/W  
Addr  
Bit  
0
1
2
3
4
5
6
7
8
9
10 11  
12  
SDA10  
13  
14 15  
RFRC  
PBI RFEN  
OP  
SDAM  
BSMA  
0000_0000_0000_0000  
R/W  
0x10190 (PSDMR), 0x10194 (LSDMR)  
16  
17  
18 19 20 21 22 23  
24  
25  
26 27  
WRC  
28  
29  
30 31  
Field RFRC  
Reset  
PRETOACT  
ACTTORW BL LDOTOPRE  
EAMUX BUFCMD  
CL  
0000_0000_0000_0000  
R/W  
R/W  
Addr  
0x10192 (PSDMR), 0x10196 (LSDMR)  
Figure 10-10. 60x/Local SDRAM Mode Register (PSDMR/LSDMR)  
Table 10-7 describes PSMDR Þelds. LSMDR Þelds are described in Table 10-8.  
Table 10-7. PSDMR Field Descriptions  
Bits  
Name  
Description  
0
PBI  
Page-based interleaving. Selects the address multiplexing method. PBI works in conjunction  
with ORx[SDA10]. See Section 10.4.5, ÒBank Interleaving.Ó  
0 Bank-based interleaving  
1 Page-based interleaving (normal operation)  
1
RFEN  
Refresh enable. Indicates that the UPM needs refresh services.  
0 Refresh services are not required  
1 Refresh services are required  
Note: After system reset, RFEN is cleared.  
See Section 10.3.8, Ò60x Bus-Assigned UPM Refresh Timer (PURT),Ó Section 10.3.9, ÒLocal  
Bus-Assigned UPM Refresh Timer (LURT),Ó Section 10.3.10, Ò60x Bus-Assigned SDRAM  
Refresh Timer (PSRT),Ó and Section 10.3.11, ÒLocal Bus-Assigned SDRAM Refresh Timer  
(LSRT).Ó  
2Ð4  
OP  
SDRAM operation. Determines which operation occurs when the SDRAM device is accessed.  
000 Normal operation  
001 CBR refresh, used in SDRAM initialization.  
010 Self refresh (for debug purpose).  
011 Mode Register write, used in SDRAM initialization.  
Note that if 60x-compatible mode is in effect on the 60x bus, the bus master must supply the  
mode register data on the low bits of the address during the access.  
100 Precharge bank (for debug purpose).  
101 Precharge all banks, used in SDRAM initialization.  
110 Activate bank (for debug purpose).  
111 Read/write (for debug purpose).  
5Ð7  
SDAM  
Address multiplex size. Determines how the address of the current memory cycle can be output  
on the address pins. See Section 10.4.5.1, ÒSDRAM Address Multiplexing (SDAM and BSMA).Ó  
MOTOROLA  
Chapter 10. Memory Controller  
10-21  
         
Part III.The Hardware Interface  
Table 10-7. PSDMR Field Descriptions (Continued)  
Bits  
Name  
Description  
8Ð10  
BSMA  
Bank select multiplexed address line. Selects the address pins to serve as bank-select address  
for the 60x SDRAM. The bank select address can also be output on the BANKSEL pins  
(optional). See Section 10.4.5.1, ÒSDRAM Address Multiplexing (SDAM and BSMA).Ó  
000 A12ÐA14  
001 A13ÐA15  
010 A14ÐA16  
011 A15ÐA17  
100 A16ÐA18  
101 A17ÐA19  
110 A18ÐA20  
111 A19ÐA21  
11Ð13  
SDA10  
ÒA10Ó control. With ORx[PBI], determines which address line can be output to SDA10 during an  
ACTIVATE command, when SDRAM is selected, to control the memory access. See  
Section 10.4.12.1, ÒSDRAM ConÞguration Example (Page-Based Interleaving).Ó  
For PBI = 0: For PBI = 1:  
000 A12  
001 A11  
010 A10  
011 A9  
100 A8  
101 A7  
110 A6  
111 A5  
000 A10  
001 A9  
010 A8  
011 A7  
100 A6  
101 A5  
110 A4  
111 A3  
SDRAM DeviceÐSpeciÞc Parameters:  
14Ð16  
RFRC  
Refresh recovery. DeÞnes the earliest timing for an activate command after a REFRESH  
command. Sets the refresh recovery interval in clock cycles. See Section 10.4.6.6, ÒRefresh  
Recovery Interval (RFRC),Ó for how to set this Þeld.  
000 Reserved  
001 3 clocks  
010 4 clocks  
011 5 clocks  
100 6 clocks  
101 7 clocks  
110 8 clocks  
111 16 clocks  
17Ð19 PRETOACT Precharge to activate interval. DeÞnes the earliest timing for ACTIVATE or REFRESH command  
after a precharge command. See Section 10.4.6.1, ÒPrecharge-to-Activate Interval.Ó  
001 1 clock-cycle wait states  
010 2 clock-cycle wait states  
...  
111 7 clock-cycle wait states  
000 8 clock-cycle wait states  
20Ð22 ACTTORW Activate to read/write interval. DeÞnes the earliest timing for READ/WRITE command after an  
ACTIVATE command. See Section 10.4.6.2, ÒActivate to Read/Write Interval.Ó  
001 1 clock cycle  
010 2 clock cycles  
...  
111 7 clock cycles  
000 8 clock cycles  
10-22  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
Table 10-7. PSDMR Field Descriptions (Continued)  
Bits  
Name  
Description  
23  
BL  
Burst length  
0 SDRAM burst length is 4. Use this value if the device port size is 64 or 16  
1 SDRAM burst length is 8. Use this value if the device port size is 32 or 8  
24Ð25 LDOTOPRE Last data out to precharge. DeÞnes the earliest timing for PRECHARGE command after the last  
data was read from the SDRAM. See Section 10.4.6.4, ÒLast Data Out to Precharge.Ó  
00 0 clock cycles  
01 -1 clock cycle  
10 -2 clock cycles  
11 Reserved  
26Ð27  
WRC  
Write recovery time. DeÞnes the earliest timing for PRECHARGE command after the last data was  
written to the SDRAM. See Section 10.4.6.5, ÒLast Data In to PrechargeÑWrite Recovery.Ó  
01 1 clock cycles  
10 2 clock cycles  
11 3 clock cycles  
00 4 clock cycles  
28  
EAMUX  
External address multiplexing enable/disable.  
0 No external address multiplexing. Fastest timing.  
1 The memory controller asserts SDAMUX for an extra cycle before issuing an ACTIVATE  
command to the SDRAM. This is useful when external address multiplexing can cause a  
delay on the address lines. Note that if this bit is set, ACTTORW should be a minimum of 2.  
In 60x-compatible mode, external address multiplexing is placed on the address lines. If the  
additional delay of the multiplexing endangers the device setup time, EAMUX should be set.  
Setting this bit causes the memory controller to add another cycle for each address phase.  
Note that EAMUX can also be set in any case of delays on the address lines, such as address  
buffers. See Section 10.4.6.7, ÒExternal Address Multiplexing Signal.Ó  
29  
BUFCMD If external buffers are placed on the control lines going to both the SDRAM and address lines,  
setting BUFCMD causes all SDRAM control lines except CS to be asserted for two cycles,  
instead of one. See Section 10.4.6.8, ÒExternal Address and Command Buffers (BUFCMD).Ó  
0 Normal timing for the control lines  
1 All control lines except CS are asserted for two cycles  
In 60x-compatible mode, external buffers may be placed on the command strobes, except CS,  
as well as the address lines. If the additional delay of the buffers endangers the device setup  
time, BUFCMD should be set, which causes the memory controller to add a cycle for each  
SDRAM command.  
30Ð31  
CL  
CAS latency. DeÞnes the timing for Þrst read data after SDRAM samples a column address.  
See Section 10.4.6.3, ÒColumn Address to First Data OutÑCAS Latency.Ó  
00 Reserved  
01 1  
10 2  
11 3  
MOTOROLA  
Chapter 10. Memory Controller  
10-23  
Part III.The Hardware Interface  
10.3.4 Local Bus SDRAM Mode Register (LSDMR)  
The LSDMR, shown in Figure 10-10, has the same Þelds as the PSDMR. Table 10-8  
describes LSDMR Þelds.  
Table 10-8. LSDMR Field Descriptions  
Bits  
Name  
Description  
0
PBI  
Page-based interleaving. Selects the address multiplexing method. PBI works in conjunction  
with ORx[SDA10]. See Section 10.4.5, ÒBank Interleaving.Ó  
0 Bank-based interleaving  
1 Page-based interleaving (normal operation)  
1
RFEN  
OP  
Refresh enable. Indicates that the SDRAM requires refresh services.  
0 Refresh services are not required  
1 Refresh services are required  
2Ð4  
SDRAM operation. Selects the operation that occurs when the SDRAM device is accessed.  
000 Normal operation  
001 CBR refresh, used in SDRAM initialization.  
010 Self refresh (for debug purpose).  
011 Mode Register write, used in SDRAM initialization.  
100 Precharge bank (for debug purpose).  
101 Precharge all banks, used in SDRAM initialization.  
110 Activate bank (for debug purpose).  
111 Read/write (for debug purpose).  
5Ð7  
SDAM  
BSMA  
Address multiplex size. Determines how the address of the current memory cycle is output on  
the address pins. See Section 10.4.5.1, ÒSDRAM Address Multiplexing (SDAM and BSMA).Ó  
8Ð10  
Bank select multiplexed address line. Selects which MPC8260 address pins serve as  
bank-select address for the local bus SDRAM. See Section 10.4.5.1, ÒSDRAM Address  
Multiplexing (SDAM and BSMA).Ó  
000 L_A14 (ORx[BPD] must be 00)  
001 L_AÐL_A15 (ORx[BPD] must be 00 or 01)  
010 L_A14ÐL_A16  
011 L_A15ÐL_A17  
100 L_A16ÐL_A18  
101 L_A17ÐL_A19  
110 L_A18ÐL_A20  
111 L_A19ÐL_A21  
11Ð13  
SDA10  
ÒA10Ó control. When SDRAM is selected, with ORx[PBI], determines which address line is  
output to SDA10 during an ACTIVATE command, to control the memory access. See  
Section 10.4.12.1, ÒSDRAM ConÞguration Example (Page-Based Interleaving).Ó  
For PBI=0: For PBI=1:  
000 A12  
001 A11  
010 A10  
011 A9  
100 A8  
101 A7  
110 A6  
111 A5  
000 A10  
001 A9  
010 A8  
011 A7  
100 A6  
101 A5  
110 A4  
111 A3  
10-24  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part III.The Hardware Interface  
Table 10-8. LSDMR Field Descriptions (Continued)  
Bits  
Name  
Description  
SDRAM DeviceÐSpeciÞc Parameters:  
14Ð16  
RFRC  
Refresh recovery. DeÞnes the earliest timing for an activate command after a REFRESH  
command. Sets the refresh recovery interval in clock cycles. See Section 10.4.6.6, ÒRefresh  
Recovery Interval (RFRC),Ó for how to set this Þeld.  
000 Reserved  
001 3 clocks  
010 4 clocks  
011 5 clocks  
100 6 clocks  
101 7 clocks  
110 8 clocks  
111 16 clocks  
17Ð19 PRETOACT Precharge to activate interval. DeÞnes the earliest timing for ACTIVATE or REFRESH command  
after a precharge command. See Section 10.4.6.1, ÒPrecharge-to-Activate Interval.Ó  
001 1 clock-cycle wait states  
010 2 clock-cycle wait states  
...  
111 7 clock-cycle wait states  
000 8 clock-cycle wait states  
20Ð22 ACTTORW Activate to read/write interval. DeÞnes the earliest timing for READ/WRITE command after an  
ACTIVATE command. See Section 10.4.6.2, ÒActivate to Read/Write Interval.Ó  
001 1 clock cycle  
010 2 clock cycles  
...  
111 7 clock cycles  
000 8 clock cycles  
23  
BL  
Burst length  
0 SDRAM burst length is 4. Use this value if the device port size is16  
1 SDRAM burst length is 8. Use this value if the device port size is 32 or 8  
24Ð25 LDOTOPRE Last data out to precharge. DeÞnes the earliest timing for PRECHARGE command after the last  
data was read from the SDRAM. See Section 10.4.6.4, ÒLast Data Out to Precharge.Ó  
00 0 clock cycles  
01 -1 clock cycle  
10 -2 clock cycles  
11 Reserved  
26Ð27  
WRC  
Write recovery time. DeÞnes the earliest timing for PRECHARGE command after the last data is  
written to the SDRAM. See Section 10.4.6.5, ÒLast Data In to PrechargeÑWrite Recovery.Ó  
01 1 clock cycles  
10 2 clock cycles  
11 3 clock cycles  
00 4 clock cycles  
MOTOROLA  
Chapter 10. Memory Controller  
10-25  
Part III.The Hardware Interface  
Table 10-8. LSDMR Field Descriptions (Continued)  
Bits  
Name  
Description  
28  
EAMUX  
External address multiplexing enable/disable.  
0 No external address multiplexing. Fastest timing.  
1 The memory controller asserts SDAMUX for an extra cycle before issuing an ACTIVATE  
command to the SDRAM. This is useful when external address multiplexing can cause a  
delay on the address lines. Note that if EAMUX is set, ACTTORW should be at least 2.  
In 60x-compatible mode, external address multiplexing is placed on the address lines. If the  
additional delay of the multiplexing endangers the device setup time, EAMUX should be set.  
Setting this bit causes the memory controller to add another cycle for each address phase.  
Note that EAMUX can also be set in case of address line delays, such as address buffers.  
See Section 10.4.6.7, ÒExternal Address Multiplexing Signal.Ó  
29  
BUFCMD If external buffers are placed on the control lines going to both the SDRAM and address lines,  
setting BUFCMD causes all SDRAM control lines except CS to be asserted for two cycles,  
instead of one. See Section 10.4.6.8, ÒExternal Address and Command Buffers (BUFCMD).Ó  
0 Normal timing for the control lines  
1 All control lines except CS are asserted for two cycles  
In 60x-compatible mode, external buffers may be placed on the command strobes, except  
CS, as well as the address lines. If the additional delay of the buffers is endangering the  
device setup time, BUFCMD should be set to cause the memory controller to add another  
cycle for each SDRAM command.  
30Ð31  
CL  
CAS latency. DeÞnes the timing for Þrst read data after a column address is sampled by the  
SDRAM. See Section 10.4.6.3, ÒColumn Address to First Data OutÑCAS Latency.Ó  
00 Reserved  
01 1 clock cycle  
10 2 clock cycles  
11 3 clock cycles  
10.3.5 Machine A/B/C Mode Registers (MxMR)  
The machine x mode registers (MxMR), shown in Figure 10-11, contain the conÞguration  
for the three UPMs.  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field BSEL RFEN  
OP  
Ñ
AMx  
DSx  
G0CLx  
GPL_x4DIS  
RLFx  
Reset  
R/W  
0000_0000_0000_0  
1
00  
R/W  
0x10170 (MAMR); 0x10174 (MBMR); 0x10178 (MCMR)  
20 21 22 23 24 25 26 27 28  
TLFx  
Addr  
Bit  
16  
17  
18  
19  
29  
30  
31  
Field  
Reset  
R/W  
RLFx  
WLFx  
MAD  
0000_0000_0000_0000  
R/W  
Addr  
0x10172 (MAMR); 0x10176 (MBMR); 0x1017A (MCMR)  
Figure 10-11. Machine x Mode Registers (MxMR)  
10-26  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part III.The Hardware Interface  
Table 10-9 describes MxMR bits.  
Table 10-9. Machine x Mode Registers (MxMR)  
Bits  
Name  
Description  
0
BSEL  
Bus select. Assigns banks that select UPMx to the 60x or local bus.  
0 Banks that select UPMx are assigned to the 60x bus.  
1 Banks that select UPMx are assigned to the local bus.  
Note: if refresh is required, the UPMÕs should be assigned as follows:  
UPMA: 60x bus (if 60x bus refresh needed)  
UPMB: Local bus (if local bus refresh required)  
UPMC: any bus, as long as UPMA or UPMB is used on the relevant bus.  
See Section 10.6.1.2, ÒUPM Refresh Timer Requests.Ó  
1
RFEN  
Refresh enable. Indicates that the UPM needs refresh services.  
0 Refresh services are not required  
1 Refresh services are required  
See Section 10.3.8, Ò60x Bus-Assigned UPM Refresh Timer (PURT),Ó Section 10.3.9, ÒLocal  
Bus-Assigned UPM Refresh Timer (LURT),Ó Section 10.3.10, Ò60x Bus-Assigned SDRAM  
Refresh Timer (PSRT),Ó and Section 10.3.11, ÒLocal Bus-Assigned SDRAM Refresh Timer  
(LSRT).Ó  
2Ð3  
OP  
Command opcode. Determines the command executed by the UPMx when a memory access  
hit a UPM assigned bank.  
00 Normal operation.  
01 Write to array. On the next memory access that hits a UPM assigned bank, write the  
contents of the MDR into the RAM location pointed by MAD. After the access, the MAD Þeld  
is automatically incremented.  
10 Read from array. On the next memory access that hits a UPM assigned bank, read the  
contents of the RAM location pointed by MAD into the MDR. After the access, the MAD Þeld  
is automatically incremented  
11 Run pattern. On the next memory access that hits a UPM assigned bank, run the pattern  
written in the RAM array. The pattern run starts at the location pointed by MAD and  
continues until the LAST bit is set in the RAM.  
Note: RLF determines the number of times a loop is executed during a pattern run.  
4
Ñ
Reserved, should be cleared.  
5Ð7  
AMx  
Address multiplex size. Determines how the address of the current memory cycle can be output  
on the address pins. The address output on the pins controlled by the contents of the UPMx  
RAM array. This Þeld is useful when connecting the MPC8260 to DRAM devices requiring row  
and column addresses multiplexed on the same pins.  
See Section 10.6.4.2, ÒAddress Multiplexing.Ó  
8Ð9  
DSx  
Disable timer period. Guarantees a minimum time between accesses to the same memory bank  
if it is controlled by the UPMx.The disable timer is turned on by the TODT in the RAM array, and  
when expired, the UPMx allows the machine access to handle a memory pattern to the same  
memory region. Accesses to a different memory region by the same UPMx will be allowed.  
00 1-cycle disable period  
01 2-cycle disable period  
10 3-cycle disable period  
11 4-cycle disable period  
Note: To avoid conßicts between successive accesses to different memory regions, the  
minimum pattern in the RAM array for a request serviced should not be shorter than the period  
established by DSx.  
MOTOROLA  
Chapter 10. Memory Controller  
10-27  
 
Part III.The Hardware Interface  
Table 10-9. Machine x Mode Registers (MxMR) (Continued)  
Bits  
Name  
Description  
10Ð12  
G0CLx  
General line 0 control. Determines which address line can be output to the GPL0 pin when the  
UPMx is selected to control the memory access.  
000 A12  
001 A11  
010 A10  
011 A9  
100 A8  
101 A7  
110 A6  
111 A5  
13  
GPL_x4DIS GPL_A4 output line disable. Determines if the UPWAIT/GTA/GPL_4 pin behaves as an output  
line controlled by the corresponding bits in the UPMx array (GPL4x).  
0 UPWAIT/GTA/GPL_x4 behaves as GPL_4.  
UPMx[G4T4/DLT3] is interpreted as G4T4.  
The UPMx[G4T3/WAEN] is interpreted as G4T3.  
1 UPWAIT/GTA/GPL_x4 behaves as UPWAIT.  
UPMx[G4T4/DLT3] is interpreted as DLT3.  
UPMx[G4T3/WAEN] is interpreted as WAEN.  
Note: After a system reset, GPL_x4DIS = 1.  
14Ð17  
18Ð21  
22Ð25  
26Ð31  
RLFx  
WLFx  
TLFx  
MAD  
Read loop Þeld. Determines the number of times a loop deÞned in the UPMx will be executed  
for a burst- or single-beat read pattern or when MxMR[OP] = 11 (RUN command)  
0001 The loop is executed 1 time  
0010 The loop is executed 2 times  
...  
1111 The loop is executed 15 times  
0000 The loop is executed 16 times  
Write loop Þeld. Determines the number of times a loop deÞned in the UPMx will be executed for  
a burst- or single-beat write pattern.  
0001 The loop is executed 1 time  
0010 The loop is executed 2 times  
...  
1111 The loop is executed 15 times  
0000 The loop is executed 16 times  
Refresh loop Þeld. Determines the number of times a loop deÞned in the UPMx will be executed  
for a refresh service pattern.  
0001 The loop is executed 1 time  
0010 The loop is executed 2 times  
...  
1111 The loop is executed 15 times  
0000 The loop is executed 16 times  
Machine address. RAM address pointer for the command executed.This Þeld is incremented by  
1, each time the UPM is accessed and the OP Þeld is set to WRITE or READ.  
10.3.6 Memory Data Register (MDR)  
The memory data register (MDR), shown in Figure 10-12, contains data written to or read  
from the RAM array for UPM READ or WRITE commands. MDR must be set up before  
issuing a write command to the UPM.  
10-28  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part III.The Hardware Interface  
Bit  
Field  
Reset  
R/W  
Addr  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
MD  
0000_0000_0000_0000  
R/W  
0x10188  
16 17 18 19 20 21 22 23 24 25  
MD  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
Addr  
0000_0000_0000_0000  
R/W  
0x1018A  
Figure 10-12. Memory Data Register (MDR)  
Table 10-10 describes MDR Þelds.  
Table 10-10. MDR Field Descriptions  
Bits Name  
0Ð31  
Description  
MD Memory data. The data to be read or written into the RAM array when a WRITE or READ command is  
supplied to the UPM.  
10.3.7 Memory Address Register (MAR)  
The memory address register (MAR) is shown in Figure 10-13.  
Bit  
Field  
Reset  
R/W  
Addr  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
A
0000_0000_0000_0000  
R/W  
0x10168  
16  
17  
18  
19  
20  
21  
22  
23  
24  
A
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
Addr  
0000_0000_0000_0000  
R/W  
0x10116A  
Figure 10-13. Memory Address Register (MAR)  
MOTOROLA  
Chapter 10. Memory Controller  
10-29  
         
Part III.The Hardware Interface  
Table 10-11 describes MAR Þelds.  
Table 10-11. MAR Field Description  
Bits Name  
0Ð31  
Description  
A
Memory address. The memory address register can be output to the address lines under control of  
the AMX bits in the UPM  
10.3.8 60x Bus-Assigned UPM Refresh Timer (PURT)  
The 60x bus assigned UPM refresh timer register (PURT) is shown in Figure 10-14.  
Bit  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
PURT  
0000_0000  
R/W  
Addr  
0x10198  
Figure 10-14. 60x Bus-Assigned UPM Refresh Timer (PURT)  
Table 10-12 describes PURT Þelds.  
Table 10-12. 60x Bus-Assigned UPM Refresh Timer (PURT)  
Bits Name  
Description  
0Ð7 PURT Refresh timer period. Determines the timer period according to the following equation:  
PURT  
----------------  
FMPTC  
æ
è
ö
ø
TimerPeriod =  
This timer generates a refresh request for all valid banks that selected a UPM machine assigned to  
the 60x bus (MxMR[BSEL] = 0) and is refresh-enabled (MxMR[RFEN] = 1). Each time the timer  
expires, a qualiÞed bank generates a refresh request using the selected UPM. The qualiÞed banks  
are rotating their requests.  
Example: For a 25-MHz SYSTEM CLOCK and a required service rate of 15.6 µs, given  
MPTPR[PTP] = 32, the PURT value should be 12 decimal. 12/(25 MHz/32) = 15.36 µs, which is less  
than the required service period of 15.6 µs.  
10.3.9 Local Bus-Assigned UPM Refresh Timer (LURT)  
The local bus assigned UPM refresh timer register (LURT) is shown in Figure 10-15.  
Bit  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
LURT  
0000_0000  
R/W  
Addr  
0x101A0  
Figure 10-15. Local Bus-Assigned UPM Refresh Timer (LURT)  
10-30  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
                   
Part III.The Hardware Interface  
Table 10-13 describes LURT Þelds.  
Table 10-13. Local Bus-Assigned UPM Refresh Timer (LURT)  
Bits  
Name  
Description  
0Ð7  
LURT Refresh timer period. Determines the timer period according to the following equation:  
LURT  
----------------  
FMPTC  
æ
è
ö
ø
TimerPeriod =  
This timer generates a refresh request for all valid banks that selected a UPM machine assigned to  
the local bus (MxMR[BSEL] =1) and is refresh-enabled (MxMR[RFEN] =1). Each time the timer  
expires, a qualiÞed bank generates a refresh request using the selected UPM. The qualiÞed banks  
are rotating their requests.  
Example: For a 25-MHz system clock and a required service rate of 15.6 µs, given  
MPTPR[PTP] = 32, the LURT value should be 12 decimal. 12/(25 MHz/32) = 15.36 µs, which is less  
than the required service period of 15.6 µs.  
10.3.10 60x Bus-Assigned SDRAM Refresh Timer (PSRT)  
The 60x bus assigned SDRAM refresh timer register (PSRT) is shown in Figure 10-16.  
Bit  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
PSRT  
0000_0000  
R/W  
Addr  
0x1019C  
Figure 10-16. 60x Bus-Assigned SDRAM Refresh Timer (PSRT)  
Table 10-14 describes PSRT Þelds.  
Table 10-14. 60x Bus-Assigned SDRAM Refresh Timer (PSRT)  
Bits Name  
Description  
0Ð7 PSRT Refresh timer period. Determines the timer period according to the following equation:  
PSRT  
----------------  
FMPTC  
æ
è
ö
ø
TimerPeriod =  
This timer generates refresh requests for all valid banks that selected a SDRAM machine assigned to  
the 60x bus and is refresh-enabled (PSDMR[RFEN] = 1). Each time the timer expires, all banks that  
qualify generate a bank staggering auto refresh request using the SDRAM machine. See  
Section 10.4.10, ÒSDRAM Refresh.Ó  
Example: For a 25-MHz system clock and a required service rate of 15.6 µs, given MPTPR[PTP] = 32,  
the PSRT value should be 12 decimal. 12/(25 MHz/32) = 15.36 µs, which is less than the required  
service period of 15.6 µs.  
MOTOROLA  
Chapter 10. Memory Controller  
10-31  
           
Part III.The Hardware Interface  
10.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT)  
The local bus-assigned SDRAM refresh timer register (LSRT) is shown in Figure 10-17.  
Bit  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
LSRT  
0000_0000  
R/W  
Addr  
0x101A4  
Figure 10-17. Local Bus-Assigned SDRAM Refresh Timer (LSRT)  
Table 10-15 describes LSRT Þelds.  
Table 10-15. LSRT Field Descriptions  
Bits Name  
Description  
0Ð7 LSRT Refresh timer period. Determines the timer period according to the following equation:  
LSRT  
----------------  
FMPTC  
æ
è
ö
ø
TimerPeriod =  
This timer generates refresh requests for all valid banks that selected a SDRAM machine assigned  
to the local bus and is refresh enabled (LSDMR[RFEN] = 1). Each time the timer expires, all banks  
that qualify generate a bank staggering auto refresh request using the SDRAM machine. See  
Section 10.4.10, ÒSDRAM Refresh.Ó  
Example: For a 25-MHz system clock and a required service rate of 15.6 µs, given  
MPTPR[PTP] = 32, the LSRT value should be 12 (decimal). 12/(25 MHz/32) = 15.36 µs, which is less  
than the required service period of 15.6 µs.  
10.3.12 Memory Refresh Timer Prescaler Register (MPTPR)  
Figure 10-18 shows the memory refresh timer prescaler register (MPTPR).  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field  
Reset  
R/W  
PTP  
0000_001x  
Ñ
0000_0000  
R/W  
0x10184  
Addr  
Figure 10-18. Memory Refresh Timer Prescaler Register (MPTPR)  
Table 10-16 describes MPTPR Þelds.  
Table 10-16. MPTPR Field Descriptions  
Bits Name  
Description  
0Ð7  
PTP Refresh timers prescaler. Determines the period of the memory refresh timers input clock. It divides  
the system clock.  
8Ð15  
Ñ
Reserved, should be cleared  
10-32  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
                   
Part III.The Hardware Interface  
10.3.13 60x Bus Error Status and Control Registers (TESCRx)  
These registers indicate the source of an error that caused TEA or MCP to be asserted on  
the 60x bus. See Section 4.3.2.10, Ò60x Bus Transfer Error Status and Control Register 1  
(TESCR1),Ó and Section 4.3.2.11, Ò60x Bus Transfer Error Status and Control Register 2  
(TESCR2).Ó  
10.3.14 Local Bus Error Status and Control Registers (L_TESCRx)  
These registers indicate the source of an error that causes TEA or MCP to be asserted on  
the local bus. See Section 4.3.2.12, ÒLocal Bus Transfer Error Status and Control Register 1  
(L_TESCR1),Ó and Section 4.3.2.13, ÒLocal Bus Transfer Error Status and Control  
Register 2 (L_TESCR2).Ó  
10.4 SDRAM Machine  
The MPC8260 provides one SDRAM interface (machine) for the 60x bus and one for the  
local bus. The machines provide the necessary control functions and signals for  
JEDEC-compliant SDRAM devices.  
Each bank can control a SDRAM device on the 60x or the local bus. Table 10-17 describes  
the SDRAM interface signals controlled by the memory controller.  
Table 10-17. SDRAM Interface Signals  
60x Bus  
Local Bus  
Comments  
CS[0Ð11]  
Device select  
RAS  
PSDRAS  
SDCAS  
SDWE  
LSDRAS  
LSDCAS  
LSDWE  
CAS  
WEN  
SDA10  
LSDA10  
ÒA10Ó control  
Byte select  
DQM[0Ð7]  
LDQM[0Ð3]  
Additional controls are available in 60x-compatible mode (60x bus only):  
¥
¥
ALEÑExternal address latch enable  
PSDAMUXÑExternal address multiplexing control (asserted = row,  
negated = column)  
¥
BNKSEL[0Ð2]ÑBank select address to allow internal bank interleaving  
Throughout this section, whenever a signal is named, the reference is to the 60x or local bus  
signal, according to the accessed bankÕs machine-select.  
Figure 10-19 shows an eight-bank, 128-Mbyte system. Each bank consists of eight 2 x  
1-Mbit x 8 SDRAMs. Note that the SDRAM memory clock must operate at the same  
frequency as, and be phase-aligned with, the system clock.  
MOTOROLA  
Chapter 10. Memory Controller  
10-33  
               
Part III.The Hardware Interface  
y
MPC8260  
PSDDQM[0Ð7]  
A[17]  
PSDA10  
12-bit  
A[19Ð28]  
D[0Ð63]  
CS[0Ð7]  
PSDRAS  
PSDWE  
PSDCAS  
CAS  
CS  
RAS  
WE  
CKE  
CLK  
CAS  
CS  
RAS  
WE  
CKE  
CLK  
CS7  
CS7  
x8  
2x1M x8  
SDRAM  
2x1M x8  
SDRAM  
DQM  
ADDR[0Ð11]  
DQM  
ADDR[0Ð11]  
DQ[0Ð7]  
DQ[0Ð7]  
DATA[0Ð7]  
DATA[56Ð63]  
x8  
x8  
CAS  
CS  
RAS  
WE  
CKE  
CLK  
CAS  
CS  
RAS  
WE  
CKE  
CLK  
CS0  
x8  
CS0  
2x1M x8  
SDRAM  
2x1M x8  
SDRAM  
DQM  
ADDR[0Ð11]  
DQM  
ADDR[0Ð11]  
DQ[0Ð7]  
DQ[0Ð7]  
DATA[0Ð7]  
DATA[56Ð63]  
Figure 10-19. 128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown)  
10-34  
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MOTOROLA  
 
Part III.The Hardware Interface  
10.4.1 Supported SDRAM ConÞgurations  
The MPC8260 memory controller supports any SDRAM conÞguration under the  
restrictions that all SDRAM devices that reside on the same bus (60x or local) should have  
the same port size and timing parameters.  
10.4.2 SDRAM Power-On Initialization  
At system reset, initialization software must set up the programmable parameters in the  
memory controller banks registers (ORx, BRx, P/LSDMR). After all memory parameters  
are conÞgured, system software should execute the following initialization sequence for  
each SDRAM device.  
1. Issue a PRECHARGE-ALL-BANKS command  
2. Issue eight CBR REFRESH commands  
3. Issue a MODE-SET command to initialize the mode register  
The initial commands are executed by setting P/LSDMR[OP] and accessing the SDRAM  
with a single-byte transaction. See Figure 10-10.  
Note that software should ensure that no memory operations begin until this process  
completes.  
10.4.3 JEDEC-Standard SDRAM Interface Commands  
The MPC8260 performs all accesses to SDRAM by using JEDEC-standard SDRAM  
interface commands. The SDRAM device samples the command and data inputs on the  
rising edge of the MPC8260 bus clock. Data at the output of the SDRAM device must be  
sampled on the rising edge of the MPC8260 bus clock.  
The MPC8260 provides the following SDRAM interface commands:  
Table 10-18. SDRAM Interface Commands  
Command  
Description  
BANK-ACTIVATE Latches the row address and initiates a memory read of that row. Row data is latched in SDRAM  
sense ampliÞers and must be restored with a PRECHARGE command before another BANK-ACTIVATE is  
issued.  
MODE-SET  
Allows setting of SDRAM optionsÑCAS latency, burst type, and burst length. CAS latency depends  
on the SDRAM device used (some SDRAMs provide CAS latency of 1, 2, or 3; some provide a latency  
of 1, 2, 3, or 4, etc.). Burst type must be chosen according to the 60x cache wrap (sequential).  
Although some SDRAMs provide burst lengths of 1, 2, 4, 8, or a page, MPC8260 supports only a  
4-beat burst for 64-bit port size and an 8-beat burst for 32-bit port size. MPC8260 does not support  
burst lengths of 1, 2, and a page for SDRAMs.The mode register data (CAS latency, burst length, and  
burst type) is programmed into the P/LSDMR register by initialization software at reset. After the P/  
LSDMR is set, the MPC8260 transfers the information in the SDMODE Þeld to the SDRAM array by  
issuing a MODE-SET command. Section 10.4.9, ÒSDRAM Mode-Set Command Timing,Ó gives timing  
information.  
MOTOROLA  
Chapter 10. Memory Controller  
10-35  
             
Part III.The Hardware Interface  
Table 10-18. SDRAM Interface Commands (Continued)  
Command  
Description  
PRECHARGE  
(SINGLE BANK/  
ALL BANKS)  
Restores data from the sense ampliÞers to the appropriate row. Also initializes the sense ampliÞers to  
prepare for reading another row in the SDRAM array. A PRECHARGE command must be issued after a  
read or write if the row address changes on the next access. Note that the MPC8260 uses the SDA10  
pin to distinguish the PRECHARGE-ALL-BANKS command. The SDRAMs must be compatible with this  
format.  
READ  
Latches the column address and transfers data from the selected sense ampliÞer to the output buffer  
as determined by the column address. During each successive clock, additional data is output without  
additional READ commands.The amount of data transferred is determined by the burst size. At the end  
of the burst, the page remains open.  
REFRESH  
WRITE  
Causes a row to be read in both memory banks (JEDEC SDRAM) as determined by the refresh row  
address counter (similar to CBR). The refresh row address counter is internal to the SDRAM device.  
After being read, a row is automatically rewritten into the memory array. Both banks must be in a  
precharged state before executing REFRESH.  
Latches the column address and transfers data from the data signals to the selected sense ampliÞer  
as determined by the column address. During each successive clock, additional data is transferred to  
the sense ampliÞers from the data signals without additional WRITE commands. The amount of data  
transferred is determined by the burst size. At the end of the burst, the page remains open.  
10.4.4 Page-Mode Support and Pipeline Accesses  
The SDRAM interface supports back-to-back page mode. A page remains open as long as  
back-to-back accesses that hit the page are generated on the bus. The page is closed once  
the bus becomes idle unless ORx[PMSEL] is set.  
The use of SDRAM pipelining allows data phases to occur on with zero bubbles for CPM  
accesses and with one bubble for core accesses, as required by the 60x bus speciÞcation.  
If ETM/LETM = 1, the use of SDRAM pipelining also allows for back-to-back data  
phases to occur with zero clocks of separation for CPM accesses and with one clock of  
separation for core accesses, as required by the 60x bus speciÞcation.  
10.4.5 Bank Interleaving  
The SDRAM interface supports bank interleaving. This means that if a missed page is in a  
different SDRAM bank than the currently open page, the SDRAM machine Þrst issues an  
ACTIVATE command to the new page and later issues a DEACTIVATE command to the old  
page, thus eliminating the DEACTIVATE time overhead.  
This procedure can be done if both pages reside on different SDRAM devices or on  
different internal SDRAM banks. The second option can be disabled by setting ORx[IBID].  
The user should set this bit if the BNKSEL pins are not used in 60x-compatible mode.  
10-36  
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Part III.The Hardware Interface  
The following two methods are used for internal bank interleaving:  
¥
Page-based interleavingÑPage-based interleaving yields the best performance and  
is the preferred interleaving method. This method uses low address bits as the  
Bank-Select for the SDRAM, thus allowing interleaving on every page boundary. It  
is activated by setting xSDMR[PBI]=1. See Ò0xSDRAM ConÞguration Example  
(Page-Based Interleaving)Ó.  
¥
Bank-based interleaving ÑThis method uses the most-signiÞcant address bits as the  
bank-select for the SDRAM, thus allowing interleaving only on bank boundaries. It  
is activated by clearing xSDMR[PBI]. See Section 10.4.12, ÒSDRAM  
ConÞguration Examples.Ó  
10.4.5.1 SDRAM Address Multiplexing (SDAM and BSMA)  
In single MPC8260 mode, the lower bits of the address bus are connected to the deviceÕs  
address port, and the memory controller multiplex the row/column and the internal banks  
select lines, according to the PL/SDMR[SDAM] and PL/SDMR[BSMA].  
Table 10-37 shows how P/LSDMR[SDAM] settings affect address multiplexing. For the  
effect of PL/SDMR[BSMA] see Section 10.4.12, ÒSDRAM ConÞguration Examples.Ó  
Note that in 60x-compatible mode, the 60x address must be latched and multiplexed by  
glue logic that is controlled by ALE and SDAMUX, however, the user still has to conÞgure  
PSDMR[SDAM].  
On the local bus, only the lower 18 bits of the address are output. Table 10-19 shows  
SDRAM address multiplexing for A0ÐA15.  
Table 10-19. SDRAM Address Multiplexing (A0ÐA15)  
External Bus  
Address  
Pins  
SDAM  
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15  
000  
001  
010  
011  
100  
101  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
A5 A6 A7  
Ñ
Ñ
Ñ
Ñ
Ñ
A5 A6  
Signaldriven  
on external  
pins when  
address  
multiplexing  
is enabled  
Ñ
Ñ
Ñ
Ñ
A5  
Ñ
Ñ
Ñ
MOTOROLA  
Chapter 10. Memory Controller  
10-37  
     
Part III.The Hardware Interface  
Table 10-20 shows SDRAM address multiplexing for A16ÐA31.  
Table 10-20. SDRAM Address Multiplexing (A16ÐA31)  
External Bus  
SDAM  
Address  
Pins  
A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31  
000  
001  
010  
011  
100  
101  
A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23  
A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22  
A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21  
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20  
Signaldriven  
on external  
pins when  
address  
multiplexing  
is enabled  
Ñ
Ñ
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19  
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18  
Ñ
10.4.6 SDRAM Device-SpeciÞc Parameters  
The software is responsible for setting correct values to some device-speciÞc parameter that  
can be extracted from the data sheet. The values are stored in the ORx and P/LSDMR  
registers. These parameters include the following:  
¥
¥
¥
¥
¥
¥
¥
¥
Precharge to activate interval (P/LSDMR[PRETOACT]). See Section 10.4.6.1,  
ÒPrecharge-to-Activate Interval.Ó  
Activate to read/write interval (P/LSDMR[ACTTORW]). See Section 10.4.6.2,  
ÒActivate to Read/Write Interval.Ó  
CAS latency, column address to Þrst data out (P/LSDMR[CL]). See  
Section 10.4.6.3, ÒColumn Address to First Data OutÑCAS Latency.Ó  
Last data out to precharge (P/LSDMR[LDOTOPRE]). Section 10.4.6.4, ÒLast Data  
Out to Precharge.Ó  
Write recovery, last data in to precharge (P/LSDMR[WRC]). See Section 10.4.6.5,  
ÒLast Data In to PrechargeÑWrite Recovery.Ó  
Refresh recovery interval (P/LSDMR[RFRC]). See Section 10.4.6.6, ÒRefresh  
Recovery Interval (RFRC).Ó  
External address multiplexing present (P/LSDMR[EAMUX]). See Section 10.4.6.7,  
ÒExternal Address Multiplexing Signal.Ó  
External buffers on the control lines present (P/LSDMR[BUFCMD]). See  
Section 10.4.6.8, ÒExternal Address and Command Buffers (BUFCMD).Ó  
The following sections describe the SDRAM parameters that are programmed in the P/  
LSDMR register.  
10.4.6.1 Precharge-to-Activate Interval  
This parameter, controlled by P/LSDMR[PRETOACT] deÞnes the earliest timing for  
activate or refresh command after a precharge command.  
10-38  
MPC8260 PowerQUICC II UserÕs Manual  
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Part III.The Hardware Interface  
CLK  
ALE  
CS  
SDRAS  
SDCAS  
MA11  
RAy  
RAy  
MA10  
MA[0Ð9]  
WE  
DQM  
PRETOACT = 2  
PRECHARGE  
Command  
Bank A  
ACTIVATE  
Command  
Bank A  
Figure 10-20. PRETOACT = 2 (2 Clock Cycles)  
10.4.6.2 Activate to Read/Write Interval  
This parameter, controlled by P/LSDMR[ACTTORW], deÞnes the earliest timing for  
READ/WRITE command after an ACTIVATE command.  
CLK  
ALE  
CS  
SDRAS  
SDCAS  
Rbz  
Cbz  
D0  
MA[0Ð11]  
WE  
DQM  
DATA  
D1  
D2  
D3  
ACTTORW = 2  
ACTIVATE  
Command  
WRITE  
Command  
Figure 10-21. ACTTORW = 2 (2 Clock Cycles)  
MOTOROLA  
Chapter 10. Memory Controller  
10-39  
       
Part III.The Hardware Interface  
10.4.6.3 Column Address to First Data OutÑCAS Latency  
This parameter, controlled by P/LSDMR[CL], deÞnes the timing for Þrst read data after a  
column address is sampled by the SDRAM.  
Activate  
Read  
First data out  
CLK  
ALE  
CL = 2  
CSn  
SDRAS  
SDCAS  
WE  
Row  
Column  
MA[0Ð11]  
DQMn  
Data  
D0  
D2  
D1  
D3  
Figure 10-22. CL = 2 (2 Clock Cycles)  
10.4.6.4 Last Data Out to Precharge  
This parameter, controlled by P/LSDMR[LDOTOPRE], deÞnes the earliest timing for the  
PRECHARGE command after the last data was read from the SDRAM. It is always related to  
the CL parameter.  
Activate  
Read  
Deactivate  
Last Data Out  
CLK  
ALE  
LDOTOPRE = 2  
CS  
SDRAS  
SDCAS  
WE  
Column  
MA[0Ð11]  
Row  
DQM  
Data  
D0  
D2  
D1  
D3  
Figure 10-23. LDOTOPRE = 2 (-2 Clock Cycles)  
10-40  
MPC8260 PowerQUICC II UserÕs Manual  
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Part III.The Hardware Interface  
10.4.6.5 Last Data In to PrechargeÑWrite Recovery  
This parameter, controlled by P/LSDMR[WRC], deÞnes the earliest timing for PRECHARGE  
command after the last data was written to the SDRAM.  
Activate  
WRITE  
Last data in  
Deactivate  
CLK  
ALE  
WRC = 2  
CS  
SDRAS  
SDCAS  
WE  
Column  
MA[0Ð11]  
Row  
DQM  
Data  
D0  
D2  
D1  
D3  
Figure 10-24. WRC = 2 (2 Clock Cycles)  
10.4.6.6 Refresh Recovery Interval (RFRC)  
This parameter, controlled by P/LSDMR[RFRC], deÞnes the earliest timing for an  
ACTIVATE command after a REFRESH command.  
CLK  
ALE  
CS  
SDRAS  
SDCAS  
A8 = 1  
MA[0Ð11]  
RAx  
WE  
DQM  
PRETOACT = 3  
RFRC = 4 (6 clocks)  
Precharge  
if needed  
Activate command  
Bank A  
Auto refresh  
Figure 10-25. RFRC = 4 (6 Clock Cycles)  
10.4.6.7 External Address Multiplexing Signal  
In 60x-compatible mode, external address multiplexing is placed on the address lines. If the  
additional delay of multiplexing is endangers the device setup time, P/LSDMR[EAMUX]  
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Chapter 10. Memory Controller  
10-41  
               
Part III.The Hardware Interface  
should be set. Setting this bit causes the memory controller to add another cycle for each  
address phase.  
Note that EAMUX can also be set in any case of delays on the address lines, such as address  
buffers.  
CLK  
ALE  
SDAMUX  
CMD  
NOP  
Act  
NOP  
Read  
NOP  
MA[0Ð11]  
Row  
Column  
Address setup cycle  
Figure 10-26. EAMUX = 1  
10.4.6.8 External Address and Command Buffers (BUFCMD)  
In 60x-compatible mode, external buffers may be placed on the command strobes, except  
CS, as well as the address lines. If the additional delay of the buffers is endangering the  
device setup time, P/LSDMR[BUFCMD] should be set. Setting this bit causes the memory  
controller to add one cycle for each SDRAM command.  
CLK  
ALE  
SDAMUX  
CMD strobes  
(without cs)  
Activate  
NOP  
Read  
NOP  
MA[0Ð11]  
CS  
Row  
Column  
Command setup cycle  
Command setup cycle  
Figure 10-27. BUFCMD = 1  
10.4.7 SDRAM Interface Timing  
The following Þgures show SDRAM timing for various types of accesses.  
10-42  
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Part III.The Hardware Interface  
CLK  
ALE  
CS  
SDRAS  
SDCAS  
MA[0Ð11]  
WE  
Row  
Column  
DQM  
D0  
Data  
Figure 10-28. SDRAM Single-Beat Read, Page Closed, CL = 3  
CLK  
ALE  
CS  
SDRAS  
SDCAS  
MA[0Ð11]  
WE  
Z
Column  
DQM  
D0  
Data  
Figure 10-29. SDRAM Single-Beat Read, Page Hit, CL = 3  
CLK  
ALE  
CS  
SDRAS  
SDCAS  
MA[0Ð11]  
WE  
Row  
Column  
DQM  
Data  
D1  
D0  
Figure 10-30. SDRAM Two-Beat Burst Read, Page Closed, CL = 3  
MOTOROLA  
Chapter 10. Memory Controller  
10-43  
     
Part III.The Hardware Interface  
Deactivate  
Activate  
CLK  
ALE  
CS  
SDRAS  
SDCAS  
BS  
*
A10 = 1  
Row  
Col  
MA[0Ð11]  
WE  
Z
DQM  
D0  
D2  
D1  
D4  
Data  
* BSÑBank select according to SDRAM organization. A10 = 1 means not all banks will be precharged.  
CAS Latency = 3  
Figure 10-31. SDRAM Four-Beat Burst Read, Page Miss, CL = 3  
CLK  
ALE  
CS  
SDRAS  
SDCAS  
MA[0Ð11]  
WE  
Column  
DQM  
D0  
Data  
Figure 10-32. SDRAM Single-Beat Write, Page Hit  
CLK  
ALE  
CS  
SDRAS  
SDCAS  
MA[0Ð11]  
WE  
Row  
Column  
DQM  
Data  
D0  
D1  
D2  
Figure 10-33. SDRAM Three-Beat Burst Write, Page Closed  
10-44  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part III.The Hardware Interface  
CLK  
ALE  
CS  
SDRAS  
SDCAS  
MA[0Ð11]  
WE  
Z
Column1  
Column2  
DQM  
D0  
D1  
D0  
D1  
Data  
DQM latency (affects negation only) = 2  
Figure 10-34. SDRAM Read-after-Read Pipeline, Page Hit, CL = 3  
CLK  
ALE  
CS  
SDRAS  
SDCAS  
MA[0Ð11]  
WE  
Column1  
Column2  
DQM  
D1  
D2  
D3  
D0  
D1  
D2  
D3  
D0  
Data  
Figure 10-35. SDRAM Write-after-Write Pipelined, Page Hit  
CLK  
ALE  
CS  
SDRAS  
SDCAS  
MA[0Ð11]  
WE  
Z
Column1  
Column2  
DQM  
D1  
D2  
D3  
D0  
D1  
D2  
D3  
D0  
Data  
Figure 10-36. SDRAM Read-after-Write Pipelined, Page Hit  
MOTOROLA  
Chapter 10. Memory Controller  
10-45  
     
Part III.The Hardware Interface  
10.4.8 SDRAM Read/Write Transactions  
The SDRAM interface supports the following read/write transactions:  
¥
¥
Single-beat reads/writes up to double word size  
Bursts of two, three, or four double words  
SDRAM devices perform bursts for each transaction, the burst length depends on the port  
size. For 64-bit port size, it is a burst of 4. For 32-bit port size, it is a burst of 8. For reads  
that require less than the full burst length, extraneous data in the burst is ignored. For writes  
that require less than the full burst length, the MPC8260 protects non-targeted addresses by  
driving DQMn high on the irrelevant cycles of the burst. However, system performance is  
not compromised since, if a new transaction is pending, the MPC8260 begins executing it  
immediately, effectively terminating the burst early.  
10.4.9 SDRAM MODE-SET Command Timing  
The MPC8260 transfers mode register data (CAS latency, burst length, burst type) stored  
in P/LSDMR[SDMODE] to the SDRAM array by issuing the MODE-SET command.  
Figure 10-37 shows timing for the MODE-SET command.  
Mode Set  
Page Activate  
Write (Burst)  
CLK  
ALE  
CS  
SDRAS  
SDCAS  
MA[0Ð11]  
WE  
*Mode Data  
Row  
Column  
DQM  
D3  
Z
D0  
D1  
D2  
Z
Data  
*The mode data is the address value during a mode-set cycle. It is driven by the memory controller, in single  
MPC8260 mode, according to P/LSDMR[CL] register. In 60x-compatible mode, software must drive the correct  
value on the address lines. Figure 10-38 shows the actual value.  
Figure 10-37. SDRAM MODE-SET Command Timing  
Figure 10-38 shows mode data bit settings.  
10-46  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part III.The Hardware Interface  
Bit number  
0
1
2
3
4
5
6
7
8
0
9
10 11  
BL  
lsb  
CL  
burst length:  
4(010) for 16- and 64-bit port sizes  
8(011) for 8- and 32-bit port sizes  
latency modeÑcan be 1(001), 2(010), or 3(011).  
Figure 10-38. Mode Data Bit Settings  
10.4.10 SDRAM Refresh  
The memory controller supplies auto (CBR) refreshes to SDRAM according to the interval  
speciÞed in PSRT or LSRT. This represents the time period required between refreshes. The  
value of P/LSRT depends on the speciÞc SDRAM devices used and the operating frequency  
of the MPC8260Õs bus. This value should allow for a potential collision between memory  
accesses and refresh cycles. The period of the refresh interval must be greater than the  
access time to ensure that read and write operations complete successfully.  
There are two levels of refresh request priorityÑlow and high. The low priority request is  
generated as soon as the refresh timer expires, this request is granted only if no other  
requests to the memory controller are pending. If the request is not granted (memory  
controller is busy) and the refresh timer expires two more times, the request becomes high  
priority and is served when the current memory controller operation Þnishes.  
Note that there are two SDRAM refresh timers, one for 60x SDRAM machines and one for  
local bus SDRAM machines.  
10.4.11 SDRAM Refresh Timing  
The memory controller implements bank staggering for the auto refresh function. This  
reduces instantaneous current consumption for memory refresh operations.  
Once a refresh request is granted the memory controller begins issuing auto-refresh  
command to each device associated with the refresh timer, in one clock intervals. After the  
last REFRESH command is issued, the memory controller waits for the number of clocks  
written in the SDRAM machineÕs mode register (RFRC in P/LSDMR). The timing is  
shown in Figure 10-39  
MOTOROLA  
Chapter 10. Memory Controller  
10-47  
       
Part III.The Hardware Interface  
Activate  
CBR  
CBR  
CBR  
CBR  
RFRC  
CLK  
ALE  
CS0  
CS1  
CS2  
CS3  
SDRAS  
SDCAS  
WE  
MA[0Ð11]  
DQM  
Z
Data  
Figure 10-39. SDRAM Bank-Staggered CBR Refresh Timing  
10.4.12 SDRAM ConÞguration Examples  
The following sections provide SDRAM conÞguration examples for page- and bank-based  
interleaving.  
10.4.12.1 SDRAM ConÞguration Example (Page-Based Interleaving)  
Consider the following SDRAM organization:  
¥
¥
64-bit port size organized as 8 x 8 x 64 Mbit.  
Each device has 4 internal banks, 12 rows, and 9 columns  
For page-based interleaving, the address bus should be partitioned as shown in Table 10-21.  
Table 10-21. 60x Address Bus Partition  
A[0Ð5]  
A[6Ð17]  
Row  
A[18Ð19]  
A[20Ð28]  
Column  
A[29Ð31]  
lsb  
msb of start address  
Bank select  
The following parameters can be extracted:  
¥
¥
¥
¥
PSDMR[PBI] = 1ÑPage-based interleaving  
ORx[BPD] = 01ÑFour internal banks  
ORx[ROWST] = 0110ÑRow starts at A[6]  
ORx[NUMR] = 011ÑTwelve row lines  
10-48  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part III.The Hardware Interface  
Now, from the SDRAM device point of view, during an ACTIVATE command, its address  
port should look like Table 10-22.  
Table 10-22. SDRAM Device Address Port during ACTIVATE Command  
ÒA[0Ð14]Ó  
Ñ
A[15Ð16]  
A[17Ð28]  
A[29Ð31]  
n.c.  
Internal bank select (A[18Ð19])  
Row (A[6Ð17])  
Table 10-19 indicates that to multiplex A[6Ð17] over A[17Ð28], PSDMR[SDAM] must be  
011 and, because the internal bank selects are multiplexed overA[15Ð16], PSDMR[BSMA]  
must be 010 (only the lower two bank select lines are used).  
Note that if the device is connected to the BNKSEL pins, the value of PSDMR[BSMA] has  
no effect. In the above example, address lines [18Ð19] are output on BNKSEL1 and  
BNKSEL0, accordingly.  
During a READ/WRITE command, the address port should look like Table 10-23.  
Table 10-23. SDRAM Device Address Port during READ/WRITE Command  
ÒA[0Ð14]Ó  
Ñ
A[15Ð16]  
A[17]  
A[18]  
AP  
A[19]  
A[20Ð28]  
Column  
A[29Ð31]  
n.c.  
Internal bank select DonÕt care  
DonÕt care  
Because AP alternates with A[7] of the row lines, set PSDMR[SDA10] = 011. This outputs  
A[7] on the SDA10 line during the ACTIVATE command and AP during READ/WRITE and  
CBR commands.  
Table 10-24 shows the register conÞguration. Not shown are PSRT and MPTPR, which  
should be programmed according to the device refresh requirements:  
Table 10-24. Register Settings (Page-Based Interleaving  
Register  
Settings  
BRx  
BA  
PS  
DECC  
WP  
MS  
Base address  
00 = 64-bit port size  
00  
EMEMC  
ATOM  
DR  
0
00  
0
0
V
1
010 = SDRAM-60x bus  
ORx  
AM  
1111_1100_0000  
NUMR  
PMSEL  
IBID  
011  
0
0
LSDAM  
BPD  
ROWST  
00000  
01  
0110  
PSDMR  
PBI  
1
ACTTOROW from device data sheet  
RFEN  
OP  
1
BL  
LDOTOPRE  
WRC  
EAMUX  
BUFCMD  
0
000  
011  
010  
011  
from device data sheet  
from device data sheet  
0
0
SDAM  
BSMA  
SDA10  
RFRC  
PRETOACT  
from device data sheet CL  
from device data sheet  
from device data sheet  
MOTOROLA  
Chapter 10. Memory Controller  
10-49  
     
Part III.The Hardware Interface  
10.4.13 SDRAM ConÞguration Example (Bank-Based Interleaving)  
Consider the following SDRAM organization:  
¥
¥
64-bit port size organized as 8 x 8 x 64 Mbit.  
Each device has four internal banks, 12 rows, and 9 columns  
For bank-based Interleaving, this means that the address bus should be partitioned as shown  
in Table 10-25.  
Table 10-25. 60x Address Bus Partition  
A[0Ð5]  
A[6Ð7]  
A[8Ð19]  
Row  
A[20Ð28]  
Column  
A[29Ð31]  
lsb  
msb of start address Internal bank select  
The following parameters can be extracted:  
¥
¥
¥
¥
PSDMR[PBI] = 0  
ORx[BPD] = 01Ñ4 internal banks  
ORx[ROWST] = 0100Ñrow starts at A[8]  
ORx[NUMR] = 011Ñthere are 12 row lines  
Now, from the SDRAM device point of view, during an ACTIVATE command, its address  
port should look like Table 10-26.  
Table 10-26. SDRAM Device Address Port during ACTIVATE Command  
ÒA[0Ð14]Ó  
Ñ
A[15Ð16]  
A[17Ð28]  
A[29Ð31]  
n.c.  
Internal bank select (A[6Ð7])  
Row (A[8Ð19])  
Table 10-19 indicates that in order to multiplex A[6Ð19] over A[15Ð28] PSDMR[SDAM]  
must be 001 and, because the internal bank selects are multiplexed over A[15Ð16]  
PSDMR[BSMA] must be 010 (only the lower two bank select lines are used).  
During a READ/WRITE command, the address port should look like Table 10-27.  
Table 10-27. SDRAM Device Address Port during READ/WRITE Command  
ÒA[0Ð14]Ó  
Ñ
A[15Ð16]  
A[17]  
A[18]  
AP  
A[19]  
A[20Ð28]  
Column  
A[29Ð31]  
n.c.  
Internal bank select DonÕt care  
DonÕt care  
Because AP alternates with A[9] of the row lines, set PSDMR[SDA10] = 011. This outputs  
A[9] on the SDA10 line during the ACTIVATE command and AP during READ/WRITE  
and CBR commands.  
Table 10-28 shows the register conÞguration. Not shown are PSRT and MPTPR, which  
should be programmed according to the device refresh requirements.  
10-50  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part III.The Hardware Interface  
Table 10-28. Register Settings (Bank-Based Interleaving)  
Register  
Settings  
BRx  
BA  
PS  
DECC  
WP  
MS  
Base address  
00 = 64-bit port size  
00  
EMEMC  
ATOM  
DR  
0
00  
0
0
V
1
010 = SDRAM-60x bus  
ORx  
SDAM  
LSDAM  
BPD  
1111_1100_0000  
00000  
01  
NUMR  
PMSEL  
IBID  
011  
0
0
ROWST  
010  
PSDMR  
PBI  
0
ACTTOROW from device data sheet  
RFEN  
OP  
1
000  
001  
010  
BL  
LDOTOPRE  
WRC  
EAMUX  
BUFCMD  
CL  
0
from device data sheet  
from device data sheet  
0
0
SDAM  
BSMA  
SDA10  
RFRC  
PRETOACT  
011  
from device data sheet  
from device data sheet  
from device data sheet  
10.5 General-Purpose Chip-Select Machine (GPCM)  
Users familiar with the MPC8xx memory controller should read Section 10.5.4,  
ÒDifferences between MPC8xxÕs GPCM and MPC8260Õs GPCM,Ó Þrst.  
The GPCM allows a glueless and ßexible interface between the MPC8260, SRAM,  
EPROM, FEPROM, ROM devices, and external peripherals. The GPCM contains two basic  
conÞguration register groupsÑBRx and ORx.  
Table 10-29 lists the GPCM interface signals on the 60x and local bus.  
Table 10-29. GPCM Interfaces Signals  
60x Bus  
Local Bus  
Comments  
CS[0Ð11]  
Device select  
WE[0Ð7]  
OE  
LWE[0Ð3]  
LOE  
Write enables for write cycles  
Output enable for read cycles  
GPCM-controlled devices can use BCTLx as read/write indicators. The BCTLx signals  
appears as R/W in the timing diagrams. See Section 10.2.7, ÒData Buffer Controls  
(BCTLx).Ó  
Additional control is available in 60x-compatible mode (60x bus only)ÑALEÐexternal  
address latch enable  
In this section, when a signal is named, the reference is to the 60x or local bus signal,  
according to the bank being accessed. Figure 10-40 shows a simple connection between a  
32-bit port size SRAM device and the MPC8260.  
MOTOROLA  
Chapter 10. Memory Controller  
10-51  
           
Part III.The Hardware Interface  
MPC8260  
32-Bit Wide SRAM  
CSx  
CE  
128K  
WE[0–3]  
GPL_x1/OE  
A[15–29]  
WE[0–3]  
OE  
Address  
Data  
D[0–31]  
Figure 10-40. GPCM-to-SRAM ConÞguration  
10.5.1 Timing ConÞguration  
If BRx[MS] selects the GPCM, the attributes for the memory cycle are taken from ORx.  
These attributes include the CSNT, ACS[0Ð1], SCY[0Ð3], TRLX, EHTR, and SETA Þelds.  
Table 10-30 shows signal behavior and system response.  
Table 10-30. GPCM Strobe Signal Behavior  
Option Register Attributes  
TRLX Access ACS CSNT  
Signal Behavior  
Address to CS  
Asserted  
CS Negated to  
Address Change  
WE Negated to  
Address/Data Invalid  
Total Cycles  
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
Read  
Read  
Read  
Write  
Write  
Write  
Write  
Write  
Write  
Read  
Read  
Read  
Write  
Write  
Write  
Write  
Write  
Write  
00  
10  
11  
00  
10  
11  
00  
10  
11  
00  
10  
11  
00  
10  
11  
00  
10  
11  
x
x
x
0
0
0
1
1
1
x
x
x
0
0
0
1
1
1
0
0
x
2+SCY  
1/4*Clock  
1/2*Clock  
0
0
x
2+SCY  
2+SCY  
0
x
0
0
2+SCY  
1/4*Clock  
1/2*Clock  
0
0
0
2+SCY  
0
0
2+SCY  
0
-1/4*Clock  
2+SCY  
1/4*Clock  
1/2*Clock  
0
-1/4*Clock  
-1/4*Clock  
2+SCY  
-1/4*Clock  
-1/4*Clock  
2+SCY  
0
x
2+2*SCY  
3+2*SCY  
3+2*SCY  
2+2*SCY  
3+2*SCY  
3+2*SCY  
3+2*SCY  
4+2*SCY  
4+2*SCY  
(1+1/4)*Clock  
(1+1/2)*Clock  
0
0
x
0
x
0
0
(1+1/4)*Clock  
(1+1/2)*Clock  
0
0
0
0
0
0
-1-1/4*Clock  
-1-1/4*Clock  
-1-1/4*Clock  
(1+1/4)*Clock  
(1+1/2)*Clock  
-1-1/4*Clock  
-1-1/4*Clock  
1
SCY is the number of wait cycles from the option register.  
10-52  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part III.The Hardware Interface  
10.5.1.1 Chip-Select Assertion Timing  
From 0 to 30 wait states can be programmed for PSDVAL generation. Byte-write enable  
signals (WE) are available for each byte written to memory. Also, the output enable signal  
(OE) is provided to eliminate external glue logic. The memory banks selected to work with  
the GPCM have unique features. On system reset, a global (boot) chip-select is available  
that provides a boot ROM chip-select prior to the system being fully conÞgured. The banks  
selected to work with the GPCM support an option to output the CS line at different timings  
with respect to the external address bus. CS can be output in any of three conÞgurations:  
¥
¥
¥
Simultaneous with the external address  
One quarter of a clock cycle later  
One half of a clock cycle later  
Figure 10-41 shows a basic connection between the MPC8260 and an external peripheral  
device. Here, CS (the strobe output for the memory access) is connected directly to CE of  
the memory device and BCTL0 is connected to the respective R/W in the peripheral device.  
MPC8260  
Peripheral  
Address  
Address  
CS  
BCTL0  
Data  
CE  
R/W  
Data  
Figure 10-41. GPCM Peripheral Device Interface  
Figure 10-42 shows CS as deÞned by the setup time required between the address lines and  
CE. The user can conÞgure ORx[ACS] to specify CS to meet this requirement.  
Clock  
Address  
PSDVAL  
ACS = 11  
ACS = 10  
CS  
OE  
Data  
Figure 10-42. GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0)  
MOTOROLA  
Chapter 10. Memory Controller  
10-53  
       
Part III.The Hardware Interface  
10.5.1.2 Chip-Select and Write Enable Deassertion Timing  
Figure 10-43 shows a basic connection between the MPC8260 and a static memory device.  
Here, CS is connected directly to CE of the memory device. The WE signals are connected  
to the respective W signal in the memory device where each WE corresponds to a different  
data byte.  
MEMORY  
Address  
MPC8260  
Address  
CS  
OE  
CE  
OE  
W
WE  
Data  
Data  
Figure 10-43. GPCM Memory Device Interface  
As Figure 10-45 shows, the timing for CS is the same as for the address lines. The strobes  
for the transaction are supplied by OE or WE, depending on the transaction direction (read  
or write). ORx[CSNT] controls the timing for the appropriate strobe negation in write  
cycles. When this attribute is asserted, the strobe is negated one quarter of a clock before  
the normal case. For example, when ACS = 00 and CSNT = 1, WE is negated one quarter  
of a clock earlier, as shown in Figure 10-44.  
Clock  
Address  
PSDVAL  
CS  
CSNT = 1  
WE  
OE  
Data  
Figure 10-44. GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0)  
When ACS ¹ 00 and CSNT = 1, WE and CS are negated one quarter of a clock earlier, as  
shown in Figure 10-45.  
10-54  
MPC8260 PowerQUICC II UserÕs Manual  
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Part III.The Hardware Interface  
Clock  
Address  
PSDVAL  
ACS = 11  
ACS = 10  
CS  
WE  
CSNT = 1  
Data  
Figure 10-45. GPCM Memory Device Basic Timing (ACS ¹ 00, CSNT = 1, TRLX = 0)  
10.5.1.3 Relaxed Timing  
ORx[TRLX] is provided for memory systems that require more relaxed timing between  
signals. When TRLX = 1 and ACS ¹ 00, an additional cycle between the address and  
strobes is inserted by the MPC8260 memory controller. See Figure 10-46 and  
Figure 10-47.  
Clock  
Address  
PSDVAL  
CS  
ACS = 10  
ACS = 11  
R/W  
WE  
OE  
Data  
Figure 10-46. GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1)  
MOTOROLA  
Chapter 10. Memory Controller  
10-55  
       
Part III.The Hardware Interface  
Clock  
Address  
PSDVAL  
CS  
ACS = 10  
ACS = 11  
R/W  
WE  
OE  
Data  
Figure 10-47. GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0,TRLX = 1)  
When TRLX and CSNT are set in a write-memory access, the strobe lines, WE[0Ð7] are  
negated one clock earlier than in the normal case. If ACS ¹ 0, CS is also negated one clock  
earlier, as shown in Figure 10-48 and Figure 10-49. When a bank is selected to operate with  
external transfer acknowledge (SETA and TRLX = 1), the memory controller does not  
support external devices that provide PSDVAL to complete the transfer with zero wait  
states. The minimum access duration in this case is three clock cycles.  
Clock  
Address  
CSNT = 1  
PSDVAL  
CS  
ACS = 10  
R/W  
WE  
OE  
Data  
Figure 10-48. GPCM Relaxed-Timing Write (ACS = 10, SCY = 0, CSNT = 1, TRLX = 1)  
10-56  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part III.The Hardware Interface  
Clock  
Address  
PSDVAL  
CS  
R/W  
WE  
OE  
Data  
Figure 10-49. GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1)  
10.5.1.4 Output Enable (OE) Timing  
The timing of the OE is affected only by TRLX. It always asserts and negates on the rising  
edge of the external bus clock. OE always asserts on the rising clock edge after CS is  
asserted, and therefore its assertion can be delayed (along with the assertion of CS) by  
programming TRLX = 1. OE deasserts on the rising clock edge coinciding with or  
immediately after CS deassertion.  
10.5.1.5 Programmable Wait State ConÞguration  
The GPCM supports internal PSDVAL generation. It allows fast accesses to external  
memory through an internal bus master or a maximum 17-clock access by programming  
ORx[SCY]. The internal PSDVAL generation mode is enabled if ORx[SETA] = 0. If GTA  
is asserted externally at least two clock cycles before the wait state counter has expired, the  
current memory cycle is terminated. When TRLX = 1, the number of wait states inserted  
by the memory controller is deÞned by 2 x SCY or a maximum of 30 wait states.  
10.5.1.6 Extended Hold Time on Read Accesses  
Slow memory devices that take a long time to turn off their data bus drivers on read accesses  
should chose some combination of ORx[29Ð30] (TRLX and EHTR). Any access following  
a read access to the slower memory bank is delayed by the number of clock cycles speciÞed  
by Table 10-31. See Figure 10-50 through Figure 10-53 for timing examples.  
MOTOROLA  
Chapter 10. Memory Controller  
10-57  
           
Part III.The Hardware Interface  
Table 10-31. TRLX and EHTR Combinations  
ORx[TRLX] ORx[EHTR] Number of Hold Time Clock Cycles  
0
0
1
1
0
1
0
1
0
1
4
8
Figure 10-50 through Figure 10-53 show timing examples.  
Clock  
Address  
PSDVAL  
CSx  
CSy  
R/W  
OE  
Data  
Figure 10-50. GPCM Read Followed by Read (ORx[29Ð30] = 0x, Fastest Timing)  
10-58  
MPC8260 PowerQUICC II UserÕs Manual  
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Part III.The Hardware Interface  
Clock  
Address  
PSDVAL  
CSx  
CSy  
R/W  
OE  
Data  
Hold Time  
1-cycle hold time allowed  
Figure 10-51. GPCM Read Followed by Read (ORx[29Ð30] = 01)  
Clock  
Address  
PSDVAL  
CSx  
CSy  
R/W  
OE  
Data  
Hold Time  
Long hold time allowed  
Figure 10-52. GPCM Read Followed by Write (ORx[29Ð30] = 01)  
MOTOROLA  
Chapter 10. Memory Controller  
10-59  
   
Part III.The Hardware Interface  
Clock  
Address  
PSDVAL  
CSx  
CSy  
R/W  
OE  
Data  
Hold Time  
Figure 10-53. GPCM Read Followed by Read (ORx[29Ð30] = 10)  
10.5.2 External Access Termination  
External access termination is supported by the GPCM using GTA, which is synchronized  
and sampled internally by the MPC8260. If, during a GPCM data phase (second cycle or  
later), the sampled signal is asserted, it is converted to PSDVAL, which terminates the  
current GPCM access. GTA should be asserted for one cycle. Note that because GTA is  
synchronized, bus termination may occur up to two cycles after GTA assertion, so in case  
of read cycle, the device still must output data as long is OE is asserted. The user selects  
whether PSDVAL is generated internally or externally (by means of GTA assertion) by  
resetting/setting BRx[SETA].  
Figure 10-54 shows how a GPCM access is terminated by GTA assertion. Asserting GTA  
terminates an access even if BRx[SETA] = 0 (internal PSDVAL generation).  
10-60  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part III.The Hardware Interface  
Clock  
Address  
R/W  
CS  
OE  
D
GTA  
PSDVAL  
Figure 10-54. External Termination of GPCM Access  
10.5.3 Boot Chip-Select Operation  
Boot chip-select operation allows address decoding for a boot ROM before system  
initialization. The CS0 signal is the boot chip-select output; its operation differs from the  
other external chip-select outputs on system reset. When the MPC8260 internal core begins  
accessing memory at system reset, CS0 is asserted for every address in the boot address  
range, unless an internal register is accessed. The address range is conÞgured during reset.  
The boot chip-select also provides a programmable port size during system reset by using  
the conÞguration mechanism described in Section 5.4, ÒReset ConÞguration.Ó The boot  
chip-select does not provide write protection. CS0 operates this way until the Þrst write to  
OR0 and it can be used as any other chip-select register once the preferred address range is  
loaded into BR0. After the Þrst write to OR0, the boot chip-select can be restarted only on  
hardware reset. Table 10-32 describes the initial values of the boot bank in the memory  
controller.  
MOTOROLA  
Chapter 10. Memory Controller  
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Part III.The Hardware Interface  
Table 10-32. Boot Bank Field Values after Reset  
Register  
BR0  
Setting  
BA  
PS  
From hard reset conÞguration word. See Section 5.4.1, ÒHard Reset ConÞguration Word.Ó  
From hard reset conÞguration word. See Section 5.4.1, ÒHard Reset ConÞguration WordÓ  
DECC  
WP  
0
0
MS[0Ð12] 000  
EMEMC  
V
From hard reset conÞguration word. See Section 5.4.1, ÒHard Reset ConÞguration WordÓ  
1
OR0  
AM[0Ð16] 1111_1110_0000_0000_0 (32 MByte)  
BCTLD  
CSNT  
0
1
ACS[0Ð1] 11  
SCY[0Ð3] 1111  
SETA  
TRLX  
EHTR  
0
1
0
10.5.4 Differences between MPC8xxÕs GPCM and MPC8260Õs GPCM  
Users familiar with the MPC8xx GPCM should read this section Þrst:  
¥
External terminationÑIn the MPC8xx the external termination connects to the  
external bus TA and so must be asserted in sync with the system clock. In the  
MPC8260, this signal is separated from the bus and named GTA. The signal is  
synchronized internally and sampled. The sampled signal is used to generate TA,  
which terminates the bus transaction.  
¥
Extended hold time for reads can be up to 8 clock cycles (instead of 1 in the  
MPC8xx).  
10.6 User-Programmable Machines (UPMs)  
Users familiar with MPC8xx memory controller should Þrst read Section 10.6.6,  
ÒDifferences between MPC8xx UPM and MPC8260 UPM.Ó Table 10-33 lists the UPM  
interface signals on the 60x and local bus.  
Table 10-33. UPM Interfaces Signals  
60x Bus  
Local Bus  
Comments  
CS[0Ð11]  
Device select  
Byte Select  
PBS[0Ð7]  
PGPL_0  
LBS[0Ð3]  
LGPL_0  
General-purpose line 0  
General-purpose line 1  
General-purpose line 2  
General-purpose line 3  
General-purpose line 4/UPM WAIT  
General-purpose line 5  
PGPL_1  
LGPL_1  
PGPL_2  
LGPL_2  
PGPL_3  
LGPL_3  
PGPL_4/UPWAIT  
PGPL_5  
LGPL_4/UPWAIT  
LGPL_5  
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Additional control is available in 60x-compatible mode (60x bus only)ÑALEÑExternal  
address latch enable (not a UPM-controlled signal).  
Note that in this section, when a signal is named, the reference is to the 60x or local bus  
signal, according to the bank being accessed.  
The three user-programmable machines (UPMs) are ßexible interfaces that connect to a  
wide range of memory devices. At the heart of each UPM is an internal-memory RAM  
array that speciÞes the logical value driven on the external memory controller pins for a  
given clock cycle. Each word in the RAM array provides bits that allow a memory access  
to be controlled with a resolution of up to one quarter of the external bus clock period on  
the byte-select and chip-select lines. Figure 10-55 shows the basic operation of each UPM.  
The following events initiate a UPM cycle:  
¥
Any internal or external device requests an external memory access to an address  
space mapped to a chip-select serviced by the UPM  
¥
¥
A UPM refresh timer expires and requests a transaction, such as a DRAM refresh  
A transfer error or reset generates an exception request  
Internal/external  
memory access request  
UPM refresh  
Array  
Index  
timer request  
Index  
RAM Array  
RUN command  
Generator  
(issued in software)  
Exception request  
Increment  
Index  
(LAST = 0)  
Wait  
Request  
Logic  
Internal  
Signals  
Latch  
Signals  
Timing  
Generator  
Hold  
UPWAIT  
WAEN Bit  
GPLx, BS_x, CSx  
Internal Controls  
Figure 10-55. User-Programmable Machine Block Diagram  
The RAM array contains 64 32-bit RAM words. The signal timing generator loads the  
RAM word from the RAM array to drive the general-purpose lines, byte-selects, and  
chip-selects. If the UPM reads a RAM word with WAEN set, the external UPWAIT signal  
is sampled and synchronized by the memory controller and the current request is frozen.  
When a new access to external memory is requested by any device on the 60x or local bus,  
the addresses of the transfer are compared to each one of the valid banks deÞned in the  
memory controller. When an address match is found in one of the memory banks, BRx[MS]  
selects the UPM to handle this memory access. MxMR[BS] assigns the UPM to the 60x or  
the local bus.  
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Note that 60x bus accesses that hit a bank allocated to the local bus are transferred to the  
local bus. However, local bus accesses that hit a bank allocated to the 60x bus are ignored.  
10.6.1 Requests  
An internal or external deviceÕs request for a memory access initiates one of the following  
patterns (MxMR[OP] = 00):  
¥
¥
¥
¥
Read single-beat pattern (RSS)  
Read burst cycle pattern (RBS)  
Write single-beat pattern (WSS)  
Write burst cycle pattern (WBS)  
These patterns are described in Section 10.6.1.1, ÒMemory Access Requests.Ó  
A UPM refresh timer request pattern initiates a refresh timer pattern (PTS), as described in  
Section 10.6.1.2, ÒUPM Refresh Timer Requests.Ó  
An exception (caused by a soft reset or the assertion of TEA) occurring while another UPM  
pattern is running initiates an exception condition pattern (EXS).  
A special pattern in the RAM array is associated with each of these cycle type. Figure 10-56  
shows the start addresses of these patterns in the UPM RAM, according to cycle type. RUN  
commands (MxMR[OP] = 11), however, can initiate patterns starting at any of the 64 UPM  
RAM words.  
Array Index  
Generator  
RSS  
Read Single-Beat Request  
RBS  
Read Burst Request  
WSS  
Write Single-Beat Request  
Write Burst Request  
64 RAM  
Words  
RAM Array  
WBS  
PTS  
EXS  
Refresh Timer Request  
Exception Condition Request  
Figure 10-56. RAM Array Indexing  
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Table 10-34 show the start address of each pattern.  
Table 10-34. UPM Routines Start Addresses  
UPM Routine  
Routine Start Address  
Read single-beat (RSS)  
Read burst (RBS)  
0x00  
0x08  
0x18  
0x20  
0x30  
0x3C  
Write single-beat (WSS)  
Write burst (WBS)  
Refresh timer (PTS)  
Exception condition (EXS)  
10.6.1.1 Memory Access Requests  
When an internal device requests a new access to external memory, the address of transfer  
are compared to each valid bank deÞned in BRx. The value in BRx[MS] selects the UPM  
to handle the memory access. The user must ensure that the UPM is appropriately  
initialized before a request.  
The UPM supports two types of memory reads and writes:  
¥
A single-beat transfer transfers one operand consisting of up to double word. A  
single-beat cycle starts with one transfer start and ends with one transfer  
acknowledge.  
¥
A burst transfer transfers four double words. For 64-bit accesses, the burst cycle  
starts with one transfer start but ends after four transfer acknowledges. A 32-bit  
device requires 8 data acknowledges; an 8-bit device requires 32. See  
Section 10.2.13, ÒPartial Data Valid Indication (PSDVAL).Ó  
The MPC8260 deÞnes two additional transfer sizes: bursts of two and three doublewords.  
These access are treated by the UPM as back-to-back, single-beat transfers.  
10.6.1.2 UPM Refresh Timer Requests  
Each UPM contains a refresh timer that can be programmed to generate refresh service  
requests of a particular pattern in the RAM array. Figure 10-57 shows the hardware  
associated with memory refresh timer request generation. PURT deÞnes the period for the  
timers associated with UPMx on the 60x bus and LURT deÞnes it on the local bus. See  
Section 10.3.8, Ò60x Bus-Assigned UPM Refresh Timer (PURT),Ó and Section 10.3.9,  
ÒLocal Bus-Assigned UPM Refresh Timer (LURT).Ó  
All 60x bus refreshes are done using the refresh pattern of UPMA. This means that if  
refresh is required on the 60x bus, UPMA must be assigned to the 60x bus and  
MxMR[RFEN] must be set. It also means that only one refresh routine should be  
programmed for the 60x bus and be placed in UPMA, which serves as the 60x bus refresh  
executor. If refresh is not required on the 60x bus, UPMA can be assigned to any bus.  
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All local bus refreshes are done using the refresh pattern of UPMB. This means that if  
refresh is required on the local bus, UPMB must be assigned to the local bus and  
MBMR[RFEN] must be set. It also means that only one refresh routine should be  
programmed for the local bus, and be placed in UPMB, which serves as the local bus refresh  
executor. If refresh is not required on the local bus, UPMB can be assigned to any bus.  
UPMC can be assigned to any bus; there is no need to program its refresh routine because  
it will use the one in UPMA or UPMB, according to the bus to which it is assigned.  
PTP Prescaling  
60x bus assigned UPM  
refresh timer request  
System  
Clock  
Divide by PURT  
Divide by LURT  
Local bus assigned UPM  
refresh timer request  
Figure 10-57. Memory Refresh Timer Request Block Diagram  
10.6.1.3 Software RequestsÑRUN Command  
Software can start a request to the UPM by issuing a RUN command to the UPM. Some  
memory devices have their own signal handshaking protocol to put them into special  
modes, such as self-refresh mode. Other memory devices require special commands to be  
issued on their control signals, such as for SDRAM initialization.  
For these special cycles, the user creates a special RAM pattern that can be stored in any  
unused areas in the UPM RAM. Then the RUN command is used to run the cycle. The UPM  
runs the pattern beginning at the speciÞed RAM location until it encounters a RAM word  
with its LAST bit set. The RUN command is issued by setting MxMR[OP] = 11 and  
accessing the UPMx memory region with a single-byte transaction.  
Note that the pattern must contain exactly one assertion of PSDVAL (UTA bit in the RAM  
word, described in Table 10-35), otherwise bus timeout may occur.  
10.6.1.4 Exception Requests  
When the MPC8260 under UPM control initiates an access to a memory device, the  
external device may assert TEA or SRESET. The UPM provides a mechanism by which  
memory control signals can meet the timing requirements of the device without losing data.  
The mechanism is the exception pattern that deÞnes how the UPM deasserts its signals in  
a controlled manner.  
10.6.2 Programming the UPMs  
The UPM is a microsequencer that requires microinstructions or RAM words to generate  
signal timings for different memory cycles. Follow these steps to program the UPMs:  
1. Set up BRx and ORx.  
2. Write patterns into the RAM array.  
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3. Program MPTPR and L/PSRT if refresh is required.  
4. Program the machine mode register (MxMR).  
Patterns are written to the RAM array by setting MxMR[OP] = 01 and accessing the UPM  
with a single byte transaction. See Figure 10-11.  
10.6.3 Clock Timing  
Fields in the RAM word specify the value of the various external signals at each clock edge.  
The signal timing generator causes external signals to behave according to the timing  
speciÞed in the current RAM word. Figure 10-58 and Figure 10-59 show the clock schemes  
of the UPMs in the memory controller for integer and non-integer clock ratios. The clock  
phases shown reßect timing windows during which generated signals can change state. If  
speciÞed in the RAM, the value of the external signals can be changed after any of the  
positive edges of T[1Ð4], plus a circuit delay time as speciÞed in the MPC8260 Hardware  
SpeciÞcations.  
Note that for integer clock ratios, the widths of T1/2/3/4 are equal, for a 1:2.5 clock ratio,  
T1 = 4/3*T2 and T3 = 4/3*T4, and for a 1:3.5 clock ratio, the ticks widths are T1 = 3/2*T2  
and T3 = 3/2*T4.  
CLKIN  
T1  
T2  
T3  
T4  
Figure 10-58. Memory Controller UPM Clock Scheme for Integer Clock Ratios  
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CLKIN  
T1  
T2  
T3  
T4  
Figure 10-59. Memory Controller UPM Clock Scheme for Non-Integer (2.5:1/3.5:1)  
Clock Ratios  
The state of the external signals may change (if speciÞed in the RAM array) at any positive  
edge of T1, T2, T3, or T4 (there is a propagation delay speciÞed in the MPC8260 Hardware  
SpeciÞcations). Note however that only the CS signal corresponding to the currently  
accessed bank is manipulated by the UPM pattern when it runs. The BS signal assertion and  
negation timing is also speciÞed for each cycle in the RAM word; which of the four BS  
signals are manipulated depends on the port size of the speciÞed bank, the external address  
accessed, and the value of TSIZn. The GPL lines toggle as programmed for any access that  
initiates a particular pattern, but resolution of control is limited to T1 and T3.  
Figure 10-60 shows how CSx, GPL1, and GPL2 can be controlled. A word is read from the  
RAM that speciÞes on every clock cycle the logical bits CST1, CST2, CST3, CST4, G1T1,  
G1T3, G2T1, and G2T3. These bits indicate the electrical value for the corresponding  
output pins at the appropriate timing.  
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CLKIN  
T1  
T2  
T3  
T4  
CSx  
GPL1  
GPL2  
CST1 CST2 CST3 CST4  
CST1 CST2 CST3 CST4  
G1T1  
G2T1  
G1T3  
G2T3  
G1T1  
G2T1  
G1T3  
G2T3  
Word 1  
Word 2  
Figure 10-60. UPM Signals Timing Example  
10.6.4 The RAM Array  
The RAM array for each UPM is 64 locations deep and 32 bits wide, as shown in  
Figure 10-61. The signals at the bottom of Figure 10-61 are UPM outputs. The selected CS  
is for the bank that matches the current address. The selected BS is for the byte lanes read  
or written by the access.  
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32 Bits  
RAM Array  
64  
T1, T2, T3, T4  
Current Bank  
External Signals Timing Generator (60x or Local)  
TSIZ, PS, A[30,31]  
CS Line  
Selector  
Byte Select  
Packaging  
CS[0Ð11]  
BS  
GPL0 GPL1 GPL2 GPL3 GPL4 GPL5  
Figure 10-61. RAM Array and Signal Generation  
10.6.4.1 RAM Words  
The RAM word, shown in Figure 10-62, is a 32-bit microinstruction stored in one of 64  
locations in the RAM array. It speciÞes timing for external signals controlled by the UPM.  
Bit  
0
1
2
3
4
5
6
7
8
9
10 11 12  
13  
14  
15  
Field CST1 CST2  
CST3  
CST4 BST1 BST2 BST3 BST4  
G0L  
G0H G1T1 G1T3 G2T1 G2T3  
Reset  
R/W  
Ñ
R/W  
Addr  
(MCR[MAD] indirect addressing of 1 of 64 entries  
20 21 22 23 24 25 26 27 28  
REDO LOOP EXEN AMX NA  
Bit  
16  
17  
18  
19  
29  
30  
31  
Field G3T1 G3T3  
G4T1/  
DLT3  
G4T3/ G5T1 G5T3  
WAEN  
UTA TODT LAST  
Reset  
R/W  
Ñ
R/W  
Addr  
(All 32 bits of the RAM word are addressed as shown in the address row above.)  
Figure 10-62. The RAM Word  
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Table 10-35 describes RAM word Þelds.  
Table 10-35. RAM Word Bit Settings  
Bit  
Name  
Description  
0
CST1 Chip-select timing 1. DeÞnes the state of CS during clock phase 1.  
0 The value of the CS line at the rising edge of T1 will be 0  
1 The value of the CS line at the rising edge of T1 will be 1  
See Section 10.6.4.1.1, ÒChip-Select Signals (CxTx).Ó  
1
2
3
4
CST2 Chip-select timing 2. DeÞnes the state of CS during clock phase 2.  
0 The value of the CS line at the rising edge of T2 will be 0  
1 The value of the CS line at the rising edge of T2 will be 1  
CST3 Chip-select timing 3. DeÞnes the state of CS during clock phase 3.  
0 The value of the CS line at the rising edge of T3 will be 0  
1 The value of the CS line at the rising edge of T3 will be 1  
CST4 Chip-select timing4. DeÞnes the state of CS during clock phase 4.  
0 The value of the CS line at the rising edge of T4 will be 0  
1 The value of the CS line at the rising edge of T4 will be 1  
BST1 Byte-select timing 1. DeÞnes the state of BS during clock phase 1.  
0 The value of the BS lines at the rising edge of T2 will be 0  
1 The value of the BS lines at the rising edge of T2 will be 1  
The Þnal value of the BS lines depends on the values of BRx[PS], the TSIZ lines, and A[30Ð31] for  
the access. See Section 10.6.4.1.2, ÒByte-Select Signals (BxTx).Ó  
5
6
BST2 Byte-select timing 2. DeÞnes the state of BS during clock phase 2.  
0 The value of the BS lines at the rising edge of T2 will be 0  
1 The value of the BS lines at the rising edge of T2 will be 1  
The Þnal value of the BS lines depends on the values of BRx[PS], TSIZx, and A[30Ð31] for the  
access.  
BST3 Byte-select timing 3. DeÞnes the state of BS during clock phase 3.  
0 The value of the BS lines at the rising edge of T3 will be 0  
1 The value of the BS lines at the rising edge of T3 will be 1  
The Þnal value of the BS lines depends on the values of BRx[PS], TSIZx, and A[30Ð31] for the  
access.  
7
BST4 Byte-select timing 4. DeÞnes the state of BS during clock phase 4.  
0 The value of the BS lines at the rising edge of T4 will be 0  
1 The value of the BS lines at the rising edge of T4 will be 1  
The Þnal value of the BS lines depends on the values of BRx[PS], TSIZx, and A[30Ð31] for the  
access.  
8Ð9  
G0L General-purpose line 0 lower. DeÞnes the state of GPL0 during phases 1Ð2.  
00 The value of GPL0 at the rising edge of T1 is as deÞned in MxMR[G0CL]  
10 The value of the GPL0 line at the rising edge of T1 will be 0  
11 The value of the GPL0 line at the rising edge of T1 will be 1  
See Section 10.6.4.1.3, ÒGeneral-Purpose Signals (GxTx, GOx).Ó  
10Ð11 G0H General-purpose line 0 higher. DeÞnes the state of GPL0 during phase 3Ð4.  
00 The value of GPL0 at the rising edge of T3 is as deÞned in MxMR[G0CL]  
10 The value of the GPL0 line at the rising edge of T3 will be 0  
11 The value of the GPL0 line at the rising edge of T3 will be 1  
See Section 10.6.4.1.3, ÒGeneral-Purpose Signals (GxTx, GOx).Ó  
MOTOROLA  
Chapter 10. Memory Controller  
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Table 10-35. RAM Word Bit Settings (Continued)  
Bit  
Name  
Description  
12  
G1T1 General-purpose line 1 timing 1. DeÞnes the state of GPL1 during phase 1Ð2.  
0 The value of the GPL0 line at the rising edge of T1 will be 0  
1 The value of the GPL0 line at the rising edge of T1 will be 1  
See Section 10.6.4.1.3, ÒGeneral-Purpose Signals (GxTx, GOx).Ó  
13  
14  
15  
16  
17  
18  
G1T3 General-purpose line 1 timing 3. DeÞnes the state of GPL1 during phase 3Ð4.  
0 The value of the GPL1 line at the rising edge of T3 will be 0  
1 The value of the GPL1 line at the rising edge of T3 will be 1  
See Section 10.6.4.1.3, ÒGeneral-Purpose Signals (GxTx, GOx).Ó  
G2T1 General-purpose line 2 timing 1. DeÞnes the state of GPL2 during phase 1Ð2.  
0 The value of the GPL2 line at the rising edge of T1 will be 0  
1 The value of the GPL2 line at the rising edge of T1 will be 1  
See Section 10.6.4.1.3, ÒGeneral-Purpose Signals (GxTx, GOx).Ó  
G2T3 General-purpose line 2 timing 3. DeÞnes the state of GPL2 during phase 3Ð4.  
0 The value of the GPL2 line at the rising edge of T3 will be 0  
1 The value of the GPL2 line at the rising edge of T3 will be 1  
See Section 10.6.4.1.3, ÒGeneral-Purpose Signals (GxTx, GOx).Ó  
G3T1 General-purpose line 3 timing 1. DeÞnes the state of GPL3 during phase 1Ð2.  
0 The value of the GPL3 line at the rising edge of T1 will be 0  
1The value of the GPL3 line at the rising edge of T1 will be 1  
See Section 10.6.4.1.3, ÒGeneral-Purpose Signals (GxTx, GOx).Ó  
G3T3 General-purpose line 3 timing 3. DeÞnes the state of GPL3 during phase 3Ð4.  
0 The value of the GPL3 line at the rising edge of T3 will be 0  
1 The value of the GPL3 line at the rising edge of T3 will be 1  
See Section 10.6.4.1.3, ÒGeneral-Purpose Signals (GxTx, GOx).Ó  
G4T/ General-purpose line 4 timing 1/delay time 2. The function is determined by MxMR[GPLx4DIS].  
DLT2  
G4T1 If MxMR deÞnes UPWAITx/GPL_x4 as an output (GPL_x4), this bit functions as G4T1:  
0 The value of the GPL4 line at the rising edge of T1 will be 0  
1 The value of the GPL4 line at the rising edge of T1 will be 1  
See Section 10.6.4.1.3, ÒGeneral-Purpose Signals (GxTx, GOx).Ó  
DLT3 If MxMR[GPLx4DIS] = 1, UPWAITx is chosen and this bit functions as DLT3.  
0 In the current word, indicates that the data bus should be sampled at the rising edge of T1 (if a read  
burst or a single read service is executed).  
1 In the current word, indicates that the data bus should be sampled at the rising edge of T3 (if a read  
burst or a single read service is executed).  
For an example, see Section 10.6.4.3, ÒData Valid and Data Sample Control.Ó  
19  
G4T3/ General-purpose line 4 timing 3/wait enable. Function depends on the value of MxMR[GPLx4DIS].  
AEN  
W
G4T3 If MxMR[GPLx4DIS] = 0, G4T3 is selected.  
0 The value of the GPL4 line at the rising edge of T3 will be 0  
1 The value of the GPL4 line at the rising edge of T3 will be 1  
WAEN If MxMR[GPLx4DIS] = 1, WAEN is selected. See Section 10.6.4.5, ÒThe Wait Mechanism.Ó  
0 The UPWAITx function is disabled.  
1 A freeze in the external signals logical value occurs if the external WAIT signal is detected  
asserted. This condition lasts until WAIT is negated.  
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Table 10-35. RAM Word Bit Settings (Continued)  
Bit  
Name  
Description  
20  
G5T1 General-purpose line 5 timing 1. DeÞnes the state of GPL5 during phase 1Ð2.  
0 The value of the GPL5 line at the rising edge of T1 will be 0  
1 The value of the GPL5 line at the rising edge of T1 will be 1  
21  
G5T3 General-purpose line 5 timing 3. DeÞnes the state of GPL5 during phase 3Ð4.  
0 The value of the GPL5 line at the rising edge of T3 will be 0  
1 The value of the GPL5 line at the rising edge of T3 will be 1  
22Ð23  
Ñ
Redo current RAM word. See ÒSection 10.6.4.1.5, ÒRepeat Execution of Current RAM Word (REDO).Ó  
00 Normal operation  
01 The current RAM word is executed twice.  
10 The current RAM word is executed tree times.  
11 The current RAM word is executed four times.  
24  
LOOP Loop. The Þrst RAM word in the RAM array where LOOP is 1 is recognized as the loop start word.  
The next RAM word where LOOP is 1 is the loop end word. RAM words between the start and end  
are deÞned as the loop. The number of times the UPM executes this loop is deÞned in the  
corresponding loop Þeld of the MxMR.  
0 The current RAM word is not the loop start word or loop end word.  
1 The current RAM word is the start or end of a loop.  
See Section 10.6.4.1.4, ÒLoop Control.Ó  
25  
EXEN Exception enable. If an external device asserts TEA or RESET, EXEN allows branching to an  
exception pattern at the exception start address (EXS) at a Þxed address in the RAM array.  
When the MPC8260 under UPM control begins accessing a memory device, the external device may  
assert TEA or SRESET. An exception occurs when one of these signals is asserted by an external  
device and the MPC8260 begins closing the memory cycle transfer. When one of these exceptions is  
recognized and EXEN in the RAM word is set, the UPM branches to the special exception start  
address (EXS) and begins operating as the pattern deÞned there speciÞes. See Table 10-34. The  
user should provide an exception pattern to deassert signals controlled by the UPM in a controlled  
fashion. For DRAM control, a handler should negate RAS and CAS to prevent data corruption. If  
EXEN = 0, exceptions are deferred and execution continues. After the UPM branches to the  
exception start address, it continues reading until the LAST bit is set in the RAM word.  
0 The UPM continues executing the remaining RAM words.  
1 The current RAM word allows a branch to the exception pattern after the current cycle if an  
exception condition is detected. The exception condition can be an external device asserting TEA  
or SRESET.  
26Ð27 AMX Address multiplexing. Determines the source of A[0Ð31] at the rising edge of t1 (single-MPC8260  
mode only). See Section 10.6.4.2, ÒAddress Multiplexing.Ó  
00 A[0Ð31] is the non-multiplexed address. For example, column address.  
01 Reserved.  
10 A[0Ð31] is the address requested by the internal master multiplexed according to MxMR[AMx].  
For example, row address.  
11 A[0Ð31] is the contents of MAR. Used for example, during SDRAM mode initialization.  
28  
NA Next address. Determines when the address is incremented during a burst access.  
0 The address increment function is disabled  
1 The address is incremented in the next cycle. In conjunction with the BRx[PS], the increment value  
of A[27Ð31] and/or BADDR[27Ð31] at the rising edge of T1 is as follows  
If the accessed bank has a 64-bit port size, the value is incremented by 8.  
If the accessed bank has a 32-bit port size, the value is incremented by 4.  
If the accessed bank has a 16-bit port size, the value is incremented by 2.  
If the accessed bank has an 8-bit port size, the value is incremented by 1.  
Note: The value of NA is relevant only when the UPM serves a burst-read or burst-write request. NA  
is reserved under other patterns.  
MOTOROLA  
Chapter 10. Memory Controller  
10-73  
 
Part III.The Hardware Interface  
Table 10-35. RAM Word Bit Settings (Continued)  
Bit  
Name  
Description  
29  
UTA UPM transfer acknowledge. Indicates assertion of PSDVAL, sampled by the bus interface in the  
current cycle.  
0 PSDVAL is not asserted in the current cycle.  
1 PSDVAL is asserted in the current cycle.  
30  
TODT Turn-on disable timer. The disable timer associated with each UPM allows a minimum time to be  
guaranteed between two successive accesses to the same memory bank. This feature is critical  
when DRAM requires a RAS precharge time. TODT, turns the timer on to prevent another UPM  
access to the same bank until the timer expires.The disable timer period is determined in  
MxMR[DSx]. The disable timer does not affect memory accesses to different banks.  
0 The disable timer is turned off.  
1 The disable timer for the current bank is activated preventing a new access to the same bank  
(when controlled by the UPMs) until the disable timer expires. For example, precharge time.  
Note: TODT must be set together with LAST. Otherwise it is ignored.  
31  
LAST Last. If this bit is set, it is the last RAM word in the program. When the LAST bit is read in a RAM  
word, the current UPM pattern terminates and the highest priority pending UPM request (if any) is  
serviced immediately in the external memory transactions. If the disable timer is activated and the  
next access is top the same bank, the execution of the next UPM pattern is held off for the number of  
clock cycles speciÞed in MxMR[DSx].  
0 The UPM continues executing RAM words.  
1 The service to the UPM request is done.  
Additional information about some of the RAM word Þelds is provided in the following  
sections.  
10.6.4.1.1 Chip-Select Signals (CxTx)  
If BRx[MS] of the accessed bank selects a UPM on the currently requested cycle the UPM  
manipulates the CS signal for that bank with timing as speciÞed in the UPM RAM word.  
The selected UPM affects only assertion and negation of the appropriate CS signal. The  
state of the selected CSx signal of the corresponding bank depends on the value of each  
CSTn bit.  
Figure 10-63 and the timing diagrams in Figure 10-60 show how UPMs control CS signals.  
10-74  
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MOTOROLA  
   
Part III.The Hardware Interface  
Bank Selected  
CS0  
CS1  
CS2  
CS3  
CS4  
CS5  
CS6  
CS7  
CS8  
CS9  
CS10  
CS11  
Switch  
UPMA/B/C  
SDRAM  
GPCM  
MS[0–1] in BRx  
MUX  
Figure 10-63. CS Signal Selection  
10.6.4.1.2 Byte-Select Signals (BxTx)  
BRx[MS] of the accessed memory bank selects a UPM on the currently requested cycle.  
The selected UPM affects only the assertion and negation of the appropriate BS signal; its  
timing as speciÞed in the RAM word. The BS signals are controlled by the port size of the  
accessed bank, the transfer size of the transaction, and the address accessed. Figure 10-64  
shows how UPMs control BS signals.  
Bank Selected  
A[29–31]  
TSIZ  
MS/BUS_SEL  
PS[0–1] in BRx  
BS0  
BS1  
BS2  
BS3  
BS4  
BS5  
BS6  
BS7  
UPMA  
UPMB  
UPMC  
Byte-Select  
Logic  
MUX  
Figure 10-64. BS Signal Selection  
The uppermost byte select (BS0) indicates that D[0Ð7] contains valid data during a cycle.  
Likewise, BS1 indicates that D[8Ð15] contains valid data, BS2 indicates that D[16Ð23]  
contains valid data, and BS3 indicates that D[24Ð31] contains valid data during a cycle, and  
so forth. Table 10-31 shows how BS signals affect 64-, 32-, 16-, and 8-bit accesses. Note  
that for a refresh timer request, all the BS signals are asserted/negated by the UPM.  
MOTOROLA  
Chapter 10. Memory Controller  
10-75  
       
Part III.The Hardware Interface  
10.6.4.1.3 General-Purpose Signals (GxTx, GOx)  
The general-purpose signals (GPL[1Ð5]) each have two bits in the RAM word that deÞne  
the logical value of the signal to be changed at the rising edge of T1 and/or at the rising edge  
of T3. GPL0 offer enhancements beyond the other GPLx lines.  
GPL0 can be controlled by an address line speciÞed in MxMR[G0CLx]. To use this feature,  
set G0H and G0L in the RAM word. For example, for a SIMM with multiple banks, this  
address line can be used to switch between banks.  
10.6.4.1.4 Loop Control  
The LOOP bit in the RAM word (bit 24) speciÞes the beginning and end of a set of UPM  
RAM words that are to be repeated. The Þrst time LOOP = 1, the memory controller  
recognizes it as a loop start word and loads the memory loop counter with the  
corresponding contents of the loop Þeld shown in Table 10-36. The next RAM word for  
which LOOP = 1 is recognized as a loop end word. When it is reached, the loop counter is  
decremented by one.  
Continued loop execution depends on the loop counter. If the counter is not zero, the next  
RAM word executed is the loop start word. Otherwise, the next RAM word executed is the  
one after the loop end word. Loops can be executed sequentially but cannot be nested.  
Table 10-36. MxMR Loop Field Usage  
Request Serviced  
Loop Field  
Read single-beat cycle  
Read burst cycle  
RLFx  
RLFx  
WLFx  
WLFx  
TLFx  
RLFx  
Write single-beat cycle  
Write burst cycle  
Refresh timer expired  
RUN command  
10.6.4.1.5 Repeat Execution of Current RAM Word (REDO)  
The REDO function is useful for wait-state insertion in a long UPM routine that would  
otherwise need too many RAM words. Setting the REDO bits of the RAM word to a  
nonzero value to cause the UPM to reexecute the current RAM word up to three times,  
according to Table 10-35.  
Special care must be taken in the following cases:  
¥
When UTA and REDO are set together, PSDVAL is asserted the number of times  
speciÞed by the REDO function.  
¥
When LOOP and REDO are set together, the loop mechanism works as usual and  
the line is repeated according to the REDO function.  
¥
¥
LAST and REDO should not be set together.  
REDO should not be used within the exception routine.  
10-76  
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Part III.The Hardware Interface  
Figure 10-79 shows an example of REDO use.  
10.6.4.2 Address Multiplexing  
The address lines can be controlled by the pattern the user provides in the UPM. The  
address multiplex bits can choose between outputting an address requested by the internal  
master as is and outputting it according to the multiplexing speciÞed by the MxMR[AMx].  
The last option is to output the contents of the MAR on the address pins.  
Note that in 60x-compatible mode, MAR cannot be output on the 60x bus external address  
line.  
Note that on the local bus, only the lower 18 bits of the MAR are output.  
Table 10-37 shows how MxMR[AMx] settings affect address multiplexing.  
Table 10-37. UPM Address Multiplexing  
External Bus  
AMx  
A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31  
Address Pin  
000  
001  
010  
011  
100  
101  
A8  
A7  
A6  
A5  
Ñ
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23  
A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22  
A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21  
A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20  
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19  
Signal Driven  
on External  
Pin when  
Address  
Multiplexing  
is Enabled  
Ñ
Ñ
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18  
See Section 10.6.5, ÒUPM DRAM ConÞguration Example,Ó for more details.  
10.6.4.3 Data Valid and Data Sample Control  
When a read access is handled by the UPM and the UTA bit is 1, the value of the DLT3 bit  
in the same RAM word indicates when the data input is sampled by the internal bus master,  
assuming that MxMR[GPLx4DIS] = 1.  
¥
If G4T4/DLT3 functions as DLT3 and DLT3 = 1 in the RAM word, data is latched  
on the falling edge of CLKIN instead of the rising edge. The data is sampled by the  
internal master on the next rising edge as is required by the MPC8260 bus operation  
spec. This feature lets the user speed up the memory interface by latching data 1/2  
clock early, which can be useful during burst reads. This feature should be used only  
in systems without external synchronous bus devices.  
¥
If G4T4/DLT3 functions as G4T4, data is latched on the rising edge of CLKIN, as  
is normal in MPC8260 bus operation.  
Figure 10-65 shows data sampling that is controlled by the UPM.  
MOTOROLA  
Chapter 10. Memory Controller  
10-77  
           
Part III.The Hardware Interface  
M
U
L
T
I
To internal  
data bus  
P
L
E
X
E
R
Data Bus  
CLKIN  
UPMx selected to handle the transfer  
AND  
(GPL4xDIS = 1) and RD/WR and DLT2x  
Figure 10-65. UPM Read Access Data Sampling  
10.6.4.4 Signals Negation  
When the LAST bit is read in a RAM word, the current UPM pattern terminates. On the  
next cycle all the UPM signals are negated unconditionally (driven to logic Ô1Õ).  
This negation will not occur only if there is a back-to-back UPM request pending. In this  
case the signals value on the cycle following the LAST bit, will be taken from the Þrst line  
of the pending UPM routine.  
10.6.4.5 The Wait Mechanism  
The WAEN bit in the RAM array word, shown in Table 10-35, can be used to enable the  
UPM wait mechanism in selected UPM RAM words.  
If the UPM reads a RAM word with the WAEN bit set, the external UPWAIT signal is  
sampled and synchronized by the memory controller and the current request is frozen. The  
UPWAIT signal is sampled at the rising edge of CLKIN. If UPWAIT is asserted and  
WAEN = 1 in the current UPM word, the UPM is frozen until UPWAIT is negated. The  
value of the external pins driven by the UPM remains as indicated in the previous word read  
by the UPM. When UPWAIT is negated, the UPM continues its normal functions. Note that  
during the WAIT cycles, the UPM negates PSDVAL.  
Figure 10-66 shows how the WAEN bit in the word read by the UPM and the UPWAIT  
signal are used to hold the UPM in a particular state until UPWAIT is negated. As the  
example in Figure 10-66 shows, the CSx and GPL1 states (C12 and F) and the WAEN value  
(C) are frozen until UPWAIT is recognized as deasserted. WAEN is typically set before the  
line that contain UTA = 1.  
10-78  
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MOTOROLA  
         
Part III.The Hardware Interface  
CLKIN  
T1  
T2  
T3  
T4  
CSx  
GPL1  
c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11  
c12  
c13 c14  
D
A
B
C
PSDVAL  
WAEN  
UPWAIT  
Word n  
Word n+1  
Word n+2  
Wait  
Wait  
Word n+3  
Figure 10-66. Wait Mechanism Timing for Internal and External Synchronous  
Masters  
10.6.4.6 Extended Hold Time on Read Accesses  
Slow memory devices that take a long time to turn off their data bus drivers on read accesses  
should chose some combination of ORx[EHTR]. Accesses after a read access to the slower  
memory bank is delayed by the number of clock cycles speciÞed by Table 10-31. The  
information in Section 10.5.1.6, ÒExtended Hold Time on Read Accesses,Ó provides  
additional information.  
10.6.5 UPM DRAM ConÞguration Example  
Consider the following DRAM organization:  
¥
¥
64-bit port size organized as 8 x 8 x 16 Mbits  
Each device has 12 row lines and 9 column lines.  
MOTOROLA  
Chapter 10. Memory Controller  
10-79  
       
Part III.The Hardware Interface  
This means that the address bus should be partitioned as shown in Table 10-38.  
Table 10-38. 60x Address Bus Partition  
A[0Ð7]  
A[8Ð19]  
Row  
A[20Ð28]  
Column  
A[29Ð31]  
lsb  
msb of start address  
From the device perspective, during RAS assertion, its address port should look like  
Table 10-39:  
Table 10-39. DRAM Device Address Port during an ACTIVATE command  
ÒA[0Ð16]Ó  
Ñ
A[17Ð28]  
A[29Ð31]  
n.c.  
Row (A[8Ð19])  
Table 10-37 indicates that to multiplex A[8Ð19] over A[17Ð28], choose AMx = 001.  
Table 10-40 shows the register conÞguration. Not shown are PURT and MPTPR, which  
should be programmed according to the device refresh requirements.  
Table 10-40. Register Settings  
Register  
Settings  
BRx  
BA  
PS  
DECC  
WP  
MS  
msb of base address  
00 = 64-bit port size  
00  
0
100 = UPMA  
EMEMC  
ATOM  
DR  
0
00  
0
V
1
ORx  
AM  
BI  
1111_1111_0000_0000_0 = 16 Mbyte  
0
EHTR  
0
MxMR  
BSEL  
RFEN  
OP  
AM  
DSA  
G0CLA  
0 = 60x bus  
1
00  
001  
As needed  
N/A  
GPL_A4DIS  
RLFA  
WLFA  
TLFA  
MAD  
0
As needed  
As needed  
As needed  
N/A  
10.6.6 Differences between MPC8xx UPM and MPC8260 UPM  
Users familiar with the MPC8xx UPM should read this section Þrst.  
Below is a list of the major differences between the MPC8xx devices and the MPC8260:  
¥
First cycle timing transferred to the UPM arrayÑIn the MPC8xxÕs UPM, the Þrst  
cycle value of some of the signals is determined from ORx[SAM,G5LA,G5LS].  
This is eliminated in the MPC8260. All signals are controlled only by the pattern  
written to the array.  
10-80  
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Part III.The Hardware Interface  
¥
¥
Timing of GPL[0Ð5]ÑIn the MPC8xxÕs UPM, the GPL lines could change on the  
positive edge of T2 or T3. In the MPC8260 these signals can change in the positive  
edge of T1 or T3 to allow connection to high-speed synchronous devices such as  
burst SRAM.  
UPM controlled signals negated at end of an accessÑIn the MPC8xxÕs UPM, if the  
user did not negate the UPM signals at end of an access, those signals kept their  
previous value. In the PowerQUICC II, all UPM signals are negated  
(CS,BS,GPL[0:4] driven to logic 1 and GPL5 driven to logic 0) at the end of that  
cycle, unless there is a back-to-back UPM cycle pending. In many cases this allows  
the UPM routine to Þnish one cycle earlier because it is now possible and desired to  
assert both UTA and LAST.  
¥
MCR is eliminatedÑIn the MPC8260, MCR is eliminated. The function of RAM  
read/write and RUN is done via the MxMR.  
¥
¥
UTA polarity is reversedÑIn the MPC8260, UTA is active-high.  
The disable timer control (TODT) and LAST bit in the RAM array word must be set  
together, otherwise TODT is ignored.  
¥
¥
Refresh timer value is in a separate registerÑIn the MPC8260, the refresh timer  
value has moved to two registers, PURT and LURT, which can serve multiple UPMs.  
Refresh on the 60x bus must be done in UPMA; on the local bus, it must be done in  
UPMB.  
¥
¥
New feature: Repeated execution of the current RAM word (REDO).  
Extended hold time on reads can be up to 8 clock cycles instead of 1 in the MPC8xx.  
10.7 Memory System Interface Example Using UPM  
Connecting the MPC8260 to a DRAM device requires a detailed examination of the timing  
diagrams representing the possible memory cycles that must be performed when accessing  
this device. This section provides timing diagrams for various UPM conÞgurations.  
MOTOROLA  
Chapter 10. Memory Controller  
10-81  
   
Part III.The Hardware Interface  
MPC8260  
BS[0–7]  
1M x 16  
1M x 16  
RAS  
CS1  
RAS  
CAS[0–1]  
W
CAS[0–1]  
W
BCTL0  
A[0–9]  
A[0–9]  
A[19–28]  
D[0–15]  
16  
D[0–15  
16  
16  
D[0–63]  
16  
D[0–15]  
D[0–15]  
RAS  
RAS  
CAS[0–1]  
W
CAS[0–1]  
W
A[0–9]  
A[0–9]  
1M x 16  
1M x 16  
Figure 10-67. DRAM Interface Connection to the 60x Bus (64-Bit Port Size)  
After timings are created, programming the UPM continues with translating these timings  
into tables representing the RAM array contents for each possible cycle. When a table is  
completed, the global parameters of the UPM must be deÞned for handling the disable  
timer (precharge) and the refresh timer relative to Figure 10-67. Table 10-41 shows settings  
of different Þelds.  
Table 10-41. UPMs Attributes Example  
Explanation  
Field  
Value  
Machine select UPMA  
Port size 64-bit  
BRx[MS]  
BRx[PS]  
0b100  
0b00  
0b0  
No write protect (R/W)  
BRx[WP]  
Refresh timer value (1024 refresh cycles)  
Refresh timer enable  
PURT[PURT]  
MxMR[RFEN]  
MxMR[AMx]  
MxMR[DSx]  
MxMR[GPL_x4DIS]  
ORx[BI]  
0x0C  
0b1  
Address multiplex size  
0b010  
0b01  
0b0  
Disable timer period  
Select between GPL4 and Wait = GPL4 data sample at clock rising edge  
Burst inhibit device  
0b0  
The OR and BR of the speciÞc bank must be initialized according to the address mapping  
of the DRAM device used. The MS Þeld should indicate the speciÞc UPM selected to  
handle the cycle. The RAM array of the UPM can than be written through use of the  
10-82  
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Part III.The Hardware Interface  
MxMR[OP] = 11. Figure 10-56 shows the Þrst locations addressed by the UPM, according  
to the different services required by the DRAM.  
CLKIN  
A
Row  
Column 1  
RD/WR  
D
PSDVAL  
CS1  
(RAS)  
BS  
(CAS)  
cst1  
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Bit 0  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Bit 7  
cst2  
cst3  
cst4  
bst1  
bst2  
bst3  
bst4  
g0l0  
g0l1  
g0h0  
g0h1  
g1t1  
g1t3  
g2t1  
g2t3  
g3t1  
g3t3  
g4t1  
g4t3  
g5t1  
g5t3  
redo[0]  
redo[1]  
loop  
exen  
amx0  
amx1  
na  
Bit 8  
Bit 9  
Bit 10  
Bit 11  
Bit 12  
Bit 13  
Bit 14  
Bit 15  
Bit 16  
Bit 17  
Bit 18  
Bit 19  
Bit 20  
Bit 21  
Bit 22  
Bit 23  
Bit 24  
Bit 25  
Bit 26  
Bit 27  
Bit 28  
Bit 29  
Bit 30  
Bit 31  
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
uta  
todt  
last  
RSS  
RSS+1  
RSS+2  
Figure 10-68. Single-Beat Read Access to FPM DRAM  
MOTOROLA  
Chapter 10. Memory Controller  
10-83  
 
Part III.The Hardware Interface  
CLKIN  
A
Row  
Column 1  
RD/WR  
D
PSDVAL  
CS1  
(RAS)  
BS  
(CAS)  
cst1  
cst2  
cst3  
cst4  
bst1  
bst2  
bst3  
bst4  
g0l0  
g0l1  
g0h0  
g0h1  
g1t1  
g1t3  
g2t1  
g2t3  
g3t1  
g3t3  
g4t1  
g4t3  
g5t1  
g5t3  
redo[0]  
redo[1]  
loop  
exen  
amx0  
amx1  
na  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
1
Bit 0  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Bit 7  
Bit 8  
Bit 9  
Bit 10  
Bit 11  
Bit 12  
Bit 13  
Bit 14  
Bit 15  
Bit 16  
Bit 17  
Bit 18  
Bit 19  
Bit 20  
Bit 21  
Bit 22  
Bit 23  
Bit 24  
Bit 25  
Bit 26  
Bit 27  
Bit 28  
Bit 29  
Bit 30  
Bit 31  
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
uta  
todt  
last  
WSS  
WSS+1 WSS+2  
Figure 10-69. Single-Beat Write Access to FPM DRAM  
10-84  
MPC8260 PowerQUICC II UserÕs Manual  
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Part III.The Hardware Interface  
CLKIN  
A
Row  
Column 1  
Column 2  
Column 3  
Column 4  
RD/WR  
D
PSDVAL  
CS1  
(RAS)  
BS  
(CAS)  
cst1  
cst2  
cst3  
cst4  
bst1  
bst2  
bst3  
bst4  
g0l0  
g0l1  
g0h0  
g0h1  
g1t1  
g1t3  
g2t1  
g2t3  
g3t1  
g3t3  
g4t1  
g4t3  
g5t1  
g5t3  
redo[0]  
redo[1]  
loop  
exen  
amx0  
amx1  
na  
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
Bit 0  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Bit 7  
0
0
0
1
1
1
1
Bit 8  
Bit 9  
Bit 10  
Bit 11  
Bit 12  
Bit 13  
Bit 14  
Bit 15  
Bit 16  
Bit 17  
Bit 18  
Bit 19  
Bit 20  
Bit 21  
Bit 22  
Bit 23  
Bit 24  
Bit 25  
Bit 26  
Bit 27  
Bit 28  
Bit 29  
Bit 30  
Bit 31  
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
uta  
todt  
last  
RBS  
RBS+1  
RBS+2  
RBS+3  
RBS+4  
RBS+5  
RBS+6  
RBS+7  
RBS+8  
Figure 10-70. Burst Read Access to FPM DRAM (No LOOP)  
MOTOROLA  
Chapter 10. Memory Controller  
10-85  
 
Part III.The Hardware Interface  
CLKIN  
A
Row  
Column 1  
Column 2  
Column 3  
Column 4  
RD/WR  
D
PSDVAL  
CS1  
(RAS)  
BS  
(CAS)  
cst1  
cst2  
cst3  
cst4  
bst1  
bst2  
bst3  
bst4  
g0l0  
g0l1  
g0h0  
g0h1  
g1t1  
g1t3  
g2t1  
g2t3  
g3t1  
g3t3  
g4t1  
g4t3  
g5t1  
g5t3  
redo[0]  
redo[1]  
loop  
exen  
amx0  
amx1  
na  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
Bit 0  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Bit 7  
Bit 8  
Bit 9  
Bit 10  
Bit 11  
Bit 12  
Bit 13  
Bit 14  
Bit 15  
Bit 16  
Bit 17  
Bit 18  
Bit 19  
Bit 20  
Bit 21  
Bit 22  
Bit 23  
Bit 24  
Bit 25  
Bit 26  
Bit 27  
Bit 28  
Bit 29  
Bit 30  
Bit 31  
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
uta  
todt  
last  
RBS  
RBS+1  
RBS+2  
RBS+3  
RBS+4  
Figure 10-71. Burst Read Access to FPM DRAM (LOOP)  
10-86  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part III.The Hardware Interface  
CLKIN  
A
Row  
Column 1  
Column 2  
Column 3  
Column 4  
RD/WR  
D
PSDVAL  
CS1  
(RAS)  
BS  
(CAS)  
cst1  
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
1
Bit 0  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Bit 7  
cst2  
cst3  
cst4  
bst1  
bst2  
bst3  
bst4  
g0l0  
g0l1  
g0h0  
g0h1  
g1t1  
g1t3  
g2t1  
g2t3  
g3t1  
g3t3  
g4t1  
g4t3  
g5t1  
g5t3  
redo[0]  
redo[1]  
loop  
exen  
amx0  
amx1  
na  
0
0
0
1
1
1
1
Bit 8  
Bit 9  
Bit 10  
Bit 11  
Bit 12  
Bit 13  
Bit 14  
Bit 15  
Bit 16  
Bit 17  
Bit 18  
Bit 19  
Bit 20  
Bit 21  
Bit 22  
Bit 23  
Bit 24  
Bit 25  
Bit 26  
Bit 27  
Bit 28  
Bit 29  
Bit 30  
Bit 31  
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
uta  
todt  
last  
WBS  
WBS+1 WBS+2 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 WBS+8  
Figure 10-72. Burst Write Access to FPM DRAM (No LOOP)  
MOTOROLA  
Chapter 10. Memory Controller  
10-87  
 
Part III.The Hardware Interface  
CLKIN  
MA  
RD/WR  
D
PSDVAL  
CS1  
(RAS)  
BS  
(CAS)  
cst1  
cst2  
cst3  
cst4  
bst1  
bst2  
bst3  
bst4  
g0l0  
g0l1  
g0h0  
g0h1  
g1t1  
g1t3  
g2t1  
g2t3  
g3t1  
g3t3  
g4t1  
g4t3  
g5t1  
g5t3  
redo[0]  
redo[1]  
loop  
exen  
amx0  
amx1  
na  
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
Bit 0  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Bit 7  
Bit 8  
Bit 9  
Bit 10  
Bit 11  
Bit 12  
Bit 13  
Bit 14  
Bit 15  
Bit 16  
Bit 17  
Bit 18  
Bit 19  
Bit 20  
Bit 21  
Bit 22  
Bit 23  
Bit 24  
Bit 25  
Bit 26  
Bit 27  
Bit 28  
Bit 29  
Bit 30  
Bit 31  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
uta  
todt  
last  
PTS  
PTS+1  
PTS+2  
Figure 10-73. Refresh Cycle (CBR) to FPM DRAM  
10-88  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part III.The Hardware Interface  
CLKIN  
MA  
RD/WR  
D
PSDVAL  
CS1  
(RAS)  
BS  
(CAS)  
cst1  
cst2  
cst3  
cst4  
bst1  
bst2  
bst3  
bst4  
g0l0  
g0l1  
g0h0  
g0h1  
g1t1  
g1t3  
g2t1  
g2t3  
g3t1  
g3t3  
g4t1  
g4t3  
g5t1  
g5t3  
redo[0]  
redo[1]  
loop  
exen  
amx0  
amx1  
na  
1
1
1
1
1
1
1
1
Bit 0  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Bit 7  
Bit 8  
Bit 9  
Bit 10  
Bit 11  
Bit 12  
Bit 13  
Bit 14  
Bit 15  
Bit 16  
Bit 17  
Bit 18  
Bit 19  
Bit 20  
Bit 21  
Bit 22  
Bit 23  
Bit 24  
Bit 25  
Bit 26  
Bit 27  
Bit 28  
Bit 29  
Bit 30  
Bit 31  
0
0
0
0
0
0
1
1
uta  
todt  
last  
EXS  
Figure 10-74. Exception Cycle  
MOTOROLA  
Chapter 10. Memory Controller  
10-89  
 
Part III.The Hardware Interface  
¥
If GPL_4 is not used as an output, the performance for a page read access can be  
improved by setting MxMR[GPL_x4DIS]. The following example shows how the  
burst read access to FPM DRAM (no LOOP) can be modiÞed using this feature. In  
this case the conÞguration registers are deÞned in the following way.  
Table 10-42. UPMs Attributes Example  
Explanation  
Field  
Value  
Machine select UPMA  
Port size 64-bit  
BRx[MS]  
BRx[PS]  
0b100  
0b00  
0b0  
No write protect (R/W)  
BRx[WP]  
Refresh timer value (1024 refresh cycles)  
Refresh timer enable  
PURT[PURT]  
MxMR[RFEN]  
MxMR[AMx]  
MxMR[DSx]  
MxMR[GPL_x4DIS]  
ORx[BI]  
0x0C  
0b1  
Address multiplex size  
0b010  
0b01  
0b1  
Disable timer period  
Select between GPL4 and Wait = Wait, data sampled at clock negative edge  
Burst inhibit device  
0b0  
The timing diagram in Figure 10-75 shows how the burst-read access shown in  
Figure 10-70 can be reduced.  
10-90  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part III.The Hardware Interface  
CLKIN  
A
row  
col 1  
col 2  
col 3  
col 4  
RD/WR  
D
D1  
D2  
D3  
D4  
PSDVAL  
CS1  
(RAS)  
BS  
(CAS)  
cst1  
cst2  
cst3  
cst4  
bst1  
bst2  
bst3  
bst4  
0
0
0
0
1
1
1
1
0
0
0
0
Bit 0  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Bit 7  
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
1
1
0
0
1
1
g0l0  
g0l1  
Bit 8  
Bit 9  
g0h0  
g0h1  
g1t1  
g1t3  
g2t1  
g2t3  
g3t1  
g3t3  
g4t1 -> DLT3  
g4t3  
g5t1  
g5t3  
redo[0]  
redo[1]  
loop  
exen  
amx0  
amx1  
na  
uta  
todt  
Bit 10  
Bit 11  
Bit 12  
Bit 13  
Bit 14  
Bit 15  
Bit 16  
Bit 17  
Bit 18  
Bit 19  
Bit 20  
Bit 21  
Bit 22  
Bit 23  
Bit 24  
Bit 25  
Bit 26  
Bit 27  
Bit 28  
Bit 29  
Bit 30  
Bit 31  
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
last  
RBS  
RBS+1  
RBS+2  
RBS+3  
RBS+4  
RBS+5  
Figure 10-75. FPM DRAM Burst Read Access (Data Sampling on Falling Edge of  
CLKIN)  
MOTOROLA  
Chapter 10. Memory Controller  
10-91  
 
Part III.The Hardware Interface  
10.7.0.1 EDO Interface Example  
Figure 10-76 shows a memory connection to extended data-out type devices. For this  
connection, GPL1 is connected to the memory deviceÕs OE pins.  
MPC8260  
BS[0Ð7]  
CS1  
RAS  
RAS  
CASl/h  
CASl/h  
1M x 16  
MCM516165  
1M x 16  
MCM516165  
OE  
W
OE  
W
R/W  
A[0Ð9]  
A[0Ð9]  
A[19Ð28]  
D[0Ð15]  
16  
D[0Ð15]  
16  
D[0Ð63]  
16  
16  
RAS  
CASl/h  
OE  
RAS  
CASl/h  
OE  
D[0Ð15]  
1M x 16  
D[0Ð15]  
1M x 16  
GPL1  
MCM516165  
MCM516165  
W
W
A[0Ð9]  
A[0Ð9]  
Figure 10-76. MPC8260/EDO Interface Connection to the 60x Bus  
Table 10-43 shows the programming of the register Þeld for supporting the conÞguration  
shown in Figure 10-76. The example assumes a CLKIN frequency of 66 MHz and that the  
device needs a 1,024-cycle refresh every 10 µs.  
Table 10-43. EDO Connection Field Value Example  
Explanation  
Machine select UPMA  
Field  
Value  
BRx[MS]  
BRx[PS]  
0b100  
0b00  
0b0  
Port size 64-bit  
No write protect (R/W)  
Refresh timer prescaler  
Refresh timer value (1024 refresh cycles)  
Refresh timer enable  
BRx[WP]  
MPTPR  
0x04  
0x07  
0b1  
PURT[PURT]  
MxMR[RFEN]  
MxMR[AMx]  
MxMR[DSx]  
ORx[BI]  
Address multiplex size  
Disable timer period  
0b001  
0b10  
Burst inhibit device  
0b0  
10-92  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part III.The Hardware Interface  
CLKIN  
A
Row  
Column 1  
RD/WR  
D
PSDVAL  
CS1  
(RAS)  
BS  
(CAS)  
GPL1  
(OE)  
cst1  
cst2  
cst3  
cst4  
bst1  
bst2  
bst3  
bst4  
g0l0  
g0l1  
g0h0  
g0h1  
g1t1  
g1t3  
g2t1  
g2t3  
g3t1  
g3t3  
g4t1  
g4t3  
g5t1  
g5t3  
redo[0]  
redo[1]  
loop  
exen  
amx0  
amx1  
na  
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
Bit 0  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Bit 7  
0
0
0
1
1
1
1
Bit 8  
Bit 9  
Bit 10  
Bit 11  
Bit 12  
Bit 13  
Bit 14  
Bit 15  
Bit 16  
Bit 17  
Bit 18  
Bit 19  
Bit 20  
Bit 21  
Bit 22  
Bit 23  
Bit 24  
Bit 25  
Bit 26  
Bit 27  
Bit 28  
Bit 29  
Bit 30  
Bit 31  
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
uta  
todt  
last  
RSS  
RSS+1  
RSS+2  
RSS+3  
RSS+4  
Figure 10-77. Single-Beat Read Access to EDO DRAM  
MOTOROLA  
Chapter 10. Memory Controller  
10-93  
 
Part III.The Hardware Interface  
CLKIN  
A
Row  
Column 1  
RD/WR  
D
PSDVAL  
CS1  
(RAS)  
BS  
(CAS)  
GPL1  
(OE)  
cst1  
cst2  
cst3  
cst4  
bst1  
bst2  
bst3  
bst4  
g0l0  
g0l1  
g0h0  
g0h1  
g1t1  
g1t3  
g2t1  
g2t3  
g3t1  
g3t3  
g4t1  
g4t3  
g5t1  
g5t3  
redo[0]  
redo[1]  
loop  
exen  
amx0  
amx1  
na  
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
1
Bit 0  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Bit 7  
0
0
0
1
1
1
1
Bit 8  
Bit 9  
Bit 10  
Bit 11  
Bit 12  
Bit 13  
Bit 14  
Bit 15  
Bit 16  
Bit 17  
Bit 18  
Bit 19  
Bit 20  
Bit 21  
Bit 22  
Bit 23  
Bit 24  
Bit 25  
Bit 26  
Bit 27  
Bit 28  
Bit 29  
Bit 30  
Bit 31  
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
uta  
todt  
last  
WSS  
WSS+1 WSS+2 WSS+3  
Figure 10-78. Single-Beat Write Access to EDO DRAM  
10-94  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part III.The Hardware Interface  
CLKIN  
A
RD/WR  
D
Row  
Column 1  
PSDVAL  
CS1  
(RAS)  
BS  
(CAS)  
GPL1  
(OE)  
cst1  
cst2  
cst3  
cst4  
bst1  
bst2  
bst3  
bst4  
g0l0  
g0l1  
g0h0  
g0h1  
g1t1  
g1t3  
g2t1  
g2t3  
g3t1  
g3t3  
g4t1  
g4t3  
g5t1  
g5t3  
redo[0]  
redo[1]  
loop  
exen  
amx0  
amx1  
na  
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Bit 0  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Bit 7  
0
0
0
1
1
1
1
0
1
1
0
0
1
1
Bit 8  
Bit 9  
Bit 10  
Bit 11  
Bit 12  
Bit 13  
Bit 14  
Bit 15  
Bit 16  
Bit 17  
Bit 18  
Bit 19  
Bit 20  
Bit 21  
Bit 22  
Bit 23  
Bit 24  
Bit 25  
Bit 26  
Bit 27  
Bit 28  
Bit 29  
Bit 30  
Bit 31  
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
uta  
todt  
last  
WSS  
WSS+1 WSS+2 REDO1 REDO2 REDO3 WSS+3  
Figure 10-79. Single-Beat Write Access to EDO DRAM Using REDO to Insert Three  
Wait States  
MOTOROLA  
Chapter 10. Memory Controller  
10-95  
 
Part III.The Hardware Interface  
CLKIN  
A
Row  
Column 1  
Column 2  
Column 3  
Column 4  
RD/WR  
D
PSDVAL  
CS1  
(RAS)  
BS  
(CAS)  
GPL1  
(OE)  
cst1  
cst2  
cst3  
cst4  
bst1  
bst2  
bst3  
bst4  
g0l0  
g0l1  
g0h0  
g0h1  
g1t1  
g1t3  
g2t1  
g2t3  
g3t1  
g3t3  
g4t1  
g4t3  
g5t1  
g5t3  
redo[0]  
redo[1]  
loop  
exen  
amx0  
amx1  
na  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
Bit 0  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Bit 7  
Bit 8  
Bit 9  
Bit 10  
Bit 11  
Bit 12  
Bit 13  
Bit 14  
Bit 15  
Bit 16  
Bit 17  
Bit 18  
Bit 19  
Bit 20  
Bit 21  
Bit 22  
Bit 23  
Bit 24  
Bit 25  
Bit 26  
Bit 27  
Bit 28  
Bit 29  
Bit 30  
Bit 31  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
uta  
todt  
last  
RBS+10  
RBS  
RBS+1  
RBS+2  
RBS+3  
RBS+4  
RBS+5  
RBS+6  
RBS+7  
RBS+8  
RBS+9  
Figure 10-80. Burst Read Access to EDO DRAM  
10-96  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part III.The Hardware Interface  
CLKIN  
A
Row  
Column 1  
Column 2  
Column 3  
Column 4  
RD/WR  
D
PSDVAL  
CS1  
(RAS)  
BS  
(CAS)  
GPL1  
(OE)  
cst1  
cst2  
cst3  
cst4  
bst1  
bst2  
bst3  
bst4  
g0l0  
g0l1  
g0h0  
g0h1  
g1t1  
g1t3  
g2t1  
g2t3  
g3t1  
g3t3  
g4t1  
g4t3  
g5t1  
g5t3  
redo[0]  
redo[1]  
loop  
exen  
amx0  
amx1  
na  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
1
Bit 0  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Bit 7  
Bit 8  
Bit 9  
Bit 10  
Bit 11  
Bit 12  
Bit 13  
Bit 14  
Bit 15  
Bit 16  
Bit 17  
Bit 18  
Bit 19  
Bit 20  
Bit 21  
Bit 22  
Bit 23  
Bit 24  
Bit 25  
Bit 26  
Bit 27  
Bit 28  
Bit 29  
Bit 30  
Bit 31  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
uta  
todt  
last  
WBS  
WBS+1 WBS+2 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 WBS+8 WBS+9  
Figure 10-81. Burst Write Access to EDO DRAM  
MOTOROLA  
Chapter 10. Memory Controller  
10-97  
 
Part III.The Hardware Interface  
CLKIN  
A
RD/WR  
D
PSDVAL  
CS1  
(RAS)  
BS  
(CAS)  
GPL1  
(OE)  
cst1  
cst2  
cst3  
cst4  
bst1  
bst2  
bst3  
bst4  
g0l0  
g0l1  
g0h0  
g0h1  
g1t1  
g1t3  
g2t1  
g2t3  
g3t1  
g3t3  
g4t1  
g4t3  
g5t1  
g5t3  
redo[0]  
redo[1]  
loop  
exen  
amx0  
amx1  
na  
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
Bit 0  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Bit 7  
Bit 8  
Bit 9  
Bit 10  
Bit 11  
Bit 12  
Bit 13  
Bit 14  
Bit 15  
Bit 16  
Bit 17  
Bit 18  
Bit 19  
Bit 20  
Bit 21  
Bit 22  
Bit 23  
Bit 24  
Bit 25  
Bit 26  
Bit 27  
Bit 28  
Bit 29  
Bit 30  
Bit 31  
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
uta  
todt  
last  
PTS  
PTS+1  
PTS+2  
PTS+3  
PTS+4  
Figure 10-82. Refresh Cycle (CBR) to EDO DRAM  
10-98  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part III.The Hardware Interface  
CLKIN  
A
RD/WR  
D
PSDVAL  
CS1  
(RAS)  
BS  
(CAS)  
GPL1  
(OE)  
cst1  
1
1
1
1
1
1
1
1
Bit 0  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Bit 7  
cst2  
cst3  
cst4  
bst1  
bst2  
bst3  
bst4  
g0l0  
g0l1  
g0h0  
g0h1  
g1t1  
g1t3  
g2t1  
g2t3  
g3t1  
g3t3  
g4t1  
g4t3  
g5t1  
g5t3  
redo[0]  
redo[1]  
loop  
exen  
amx0  
amx1  
na  
Bit 8  
Bit 9  
Bit 10  
Bit 11  
Bit 12  
Bit 13  
Bit 14  
Bit 15  
Bit 16  
Bit 17  
Bit 18  
Bit 19  
Bit 20  
Bit 21  
Bit 22  
Bit 23  
Bit 24  
Bit 25  
Bit 26  
Bit 27  
Bit 28  
Bit 29  
Bit 30  
Bit 31  
1
1
0
0
0
0
0
0
1
1
uta  
todt  
last  
EXS  
Figure 10-83. Exception Cycle For EDO DRAM  
MOTOROLA  
Chapter 10. Memory Controller  
10-99  
 
Part III.The Hardware Interface  
10.8 Handling Devices with Slow or Variable Access  
Times  
The memory controller provides two ways to interface with slave devices that are very slow  
(access time is greater than the maximum allowed by the user programming model) or  
cannot guarantee a predeÞned access time (for example some FIFO, hierarchical bus  
interface, or dual-port memory devices). These mechanisms are as follows:  
¥
¥
The wait mechanismÑUsed only in accesses controlled by the UPM. Setting  
MxMR[GPLx4DIS] enables this mechanism.  
The external termination (GTA) mechanism is used only in accesses controlled by  
the GPCM. ORx[SETA] speciÞes whether the access is terminated internally or  
externally.  
The following examples show how the two mechanisms work.  
10.8.1 Hierarchical Bus Interface Example  
Assume that the core initiates a local-bus read cycle that addresses main memory connected  
to the system bus. The hierarchical bus interface accepts local bus requests and generates a  
read cycle on the system bus. The programmer cannot predict when valid data can be  
latched by the core because a DMA device may be occupying the system bus.  
¥
The wait solution (UPM)ÑThe external module asserts UPWAIT to the memory  
controller to indicate that data is not ready. The memory controller synchronized this  
signal because the wait signal is asynchronous. As a result of the wait signal being  
asserted, the UPM enters a freeze mode at the rising edge of CLKIN upon  
encountering the WAEN bit being set in the UPM word. The UPM stays in that state  
until UPWAIT is negated. After UPWAIT is negated, the UPM continues executing  
from the next entry to the end of the pattern (LAST bit is set).  
¥
The external termination solution (GPCM)ÑThe bus interface module asserts GTA  
to the memory controller when it can sample data. Note that GTA is also  
synchronized.  
10.8.2 Slow Devices Example  
Assume that the core initiates a read cycle from a device whose access time exceeds the  
maximum allowed by the user programming model.  
¥
The wait solution (UPM)ÑThe core generates a read access from the slow device.  
The device in turn asserts the wait signal until the data is ready. The core samples  
data only after the wait signal is negated.  
¥
The external termination solution (GPCM)ÑThe core generates a read access from  
the slow device, which must generate the asynchronous GTA when it is ready.  
10-100  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part III.The Hardware Interface  
10.9 External Master Support (60x-Compatible Mode)  
The memory controller supports internal and external bus masters. Accesses from the core  
or the CPM are considered internal; accesses from an external bus master are external.  
External bus master support is available only if the MPC8260 is placed in 60x-compatible  
mode. This is done by setting the BCR[EBM], described in Section 4.3.2.1, ÒBus  
ConÞguration Register (BCR).Ó  
There are two types of external bus masters:  
¥
¥
Any 60x-compatible device that uses a 64-bit data bus, such as: MPC603e,  
MPC604e, MPC750, MPC2605 (L2 cache) in copy-back mode and others  
MPC8260 type devices  
10.9.1 60x-Compatible External Masters  
Any 60x-compatible devices that use a 64-bit data bus can access the MPC8260 internal  
registers and local bus. These devices can also use memory controller services under the  
following restrictions, which apply only to 60x-assigned memory banks accessed by the  
external device:  
¥
¥
64-bit port size only  
No ECC or RMW-parity  
For 60x bus compatibility, the following connections should be observed:  
¥
¥
¥
MPC8260Õs TSIZ[1Ð3] should be connected to the external masterÕs TSIZ[0Ð2]  
MPC8260Õs TSIZ[0] should be pulled down  
MPC8260Õs PSDVAL should be pulled up  
10.9.2 MPC8260-Type External Masters  
An MPC8260 external master is a 60x-compatible master with additional functionality. As  
described in the following, it has fewer the restrictions than other 60x-compatible masters:  
¥
¥
Any port size is allowed  
ECC and RMW-parity are supported  
10.9.3 Extended Controls in 60x-Compatible Mode  
In 60x-compatible mode, the memory controller provided extended controls for the glue  
logic. The extended control consists of the following:  
¥
¥
Memory address latch (ALE) to latch the 60x address for memory use  
The address multiplex pin (GPL5/SDAMUX), which controls external multiplexing  
for DRAM and SDRAM devices  
¥
LSB address pins (BADDR[27Ð31]) for incrementing memory addresses  
MOTOROLA  
Chapter 10. Memory Controller  
10-101  
           
Part III.The Hardware Interface  
¥
¥
PSDVAL as a termination to a partial transaction (such as port-size beat access).  
Internal SDRAM bank selects (BNKSEL[0Ð2]) to allow SDRAM bank interleaving,  
as described in Section 10.9.4, ÒUsing BNKSEL SIgnals in Single-MPC8260 Bus  
Mode.Ó  
10.9.4 Using BNKSEL SIgnals in Single-MPC8260 Bus Mode  
The BNKSEL signals provide the following functionality in single-MPC8260 bus mode  
¥
If bank-based interleaving is used, BNKSEL signals facilitate compatibility with  
SDRAMs that have different numbers of row or column address lines. The address  
lines of the MPC8260 bus and the BNKSEL lines can be routed independently to the  
address lines and BA lines of the DIMM. Note that all SDRAMs populated on an  
MPC8260 bus must still have the same organization. This ßexibility merely allows  
the SDRAMs to be populated as a group with larger or smaller devices as  
appropriate.  
If BNKSEL lines were not used, the number of row and column address lines of the  
SDRAMs would affect which MPC8260 address bus lines on which the bank select  
signals would be driven, and would thus require that the BA signals of the SDRAMs  
be routed to those address lines, thus limiting ßexibility.  
¥
If BCR[HP] is programmed, BNKSEL signals facilitate logic analysis of the system.  
Otherwise, the logic analyzer equipment must understand the address multiplexing  
scheme of the board and intelligently reconstruct the address of bus transactions.  
10.9.5 Address Incrementing for External Bursting Masters  
BADDR[27Ð31] should be used to generate addresses to memory devices for burst  
accesses. In 60x-compatible mode, when a master initiates an external bus transaction, it  
reßects the value of A[27Ð31] on the Þrst clock cycle of the memory access. These signals  
are latched by the memory controller and on subsequent clock cycles, BADDR[27Ð31]  
increments as programmed in the UPM or after each data beat is sampled in the GPCM or  
after each READ/WRITE command in the SDRAM machine (the SDRAM machine uses  
BADDR only for port sizes of 16 or 8 bits).  
10.9.6 External Masters Timing  
External and internal masters have similar memory access timings. However, because it  
takes more time to decode the addresses of external masters, memory accesses by external  
masters start one cycle later than those of internal masters.  
As soon as the external master asserts TS, the memory controller compares the address with  
each of its deÞned valid banks. If a match is found, the memory controller asserts the  
address latch enable (ALE) and control signals to the memory devices. The memory  
controller asserts PSDVAL for each data beat to indicate data beat termination on write  
transactions and data valid on read transactions.  
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Part III.The Hardware Interface  
The 60x bus is pipelined. The ALE pins control the external latch that latches the address  
from the 60x bus and keeps the address stable for the memory access. The memory  
controller asserts ALE only on the start of new memory controller access.  
Figure 10-84 shows the pipelined bus operation in 60x-compatible mode.  
CLKIN  
ADDR + ATTR  
TS  
AACK  
DBG  
PSDVAL  
TA  
D
ALE  
MA  
CS  
WE  
OE  
BADDR[27–28]  
02  
03  
00  
01  
Figure 10-84. Pipelined Bus Operation and Memory Access in 60x-Compatible  
Mode  
MOTOROLA  
Chapter 10. Memory Controller  
10-103  
 
Part III.The Hardware Interface  
Figure 10-85 shows the 1-cycle delay for external master access. For systems that use the  
60x bus with low frequency (33 MHz), the 1-cycle delay for external masters can be  
eliminated by setting BCR[EXDD].  
CLKIN  
A[0–28]  
A[27–31]  
TT  
TBST  
TSIZ  
TS  
TA  
CS  
WE  
OE  
Data  
Address  
Match and  
Compare  
Memory  
Device  
Access  
Figure 10-85. External Master Access (GPCM)  
10.9.6.1 Example of External Master Using the SDRAM Machine  
Figure 10-86 shows an interconnection in which a 60x-compatible external master and the  
MPC8260 can share access to a SDRAM bank. Note that the address multiplexer is  
controlled by SDAMUX, while the address latch is controlled by ALE. Also note that  
because this is a 64-bit port size SDRAM, BADDR is not needed.  
10-104  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part III.The Hardware Interface  
BNKSEL,SDWE,SDRAS,SDCAS  
CS1  
SDRAM  
64-Bit Port Size  
DQM[0–7]  
SDAMUX  
Multiplexer  
MA  
Latch  
ALE  
MPC8260  
External Master  
A[0–31]  
D[0–63]  
TT[0–4]  
TS  
TBST  
TA  
TSIZ[1–3]  
TSIZ[0]  
TSIZ[0–2]  
(pull down)  
PSDVAL  
(pull up)  
Arbitration signals  
Figure 10-86. External Master Configuration with SDRAM Device  
MOTOROLA  
Chapter 10. Memory Controller  
10-105  
 
Part III.The Hardware Interface  
10-106  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Chapter 11  
Secondary (L2) Cache Support  
110  
1T10 he MPC8260 has features to support an externally controlled secondary (L2) cache such  
as the Motorola MPC2605 integrated secondary cache for PowerPC microprocessors. This  
chapter describes the MPC8260Õs L2 cache interfaceÑconÞgurations, operation,  
programmable parameters, system requirements, and timing.  
11.1 L2 Cache ConÞgurations  
The MPC8260 supports three L2 cache conÞgurationsÑcopy-back mode, write-through  
mode, and ECC/parity mode. The following sections describe the L2 cache modes.  
11.1.1 Copy-Back Mode  
The use of a copy-back L2 cache offers several advantages over direct access to the memory  
system. In copy-back mode, cacheable write operations are performed to the L2 cache  
without updating main memory. Since every cacheable write operation does not go to main  
memory but to the L2 cache which can be accessed more quickly, write operation latency  
is reduced along with contention for the memory system. In copy-back mode, cacheable  
read operations that hit in the L2 cache are serviced from the L2 cache without requiring a  
memory transaction and its associated latency. Copy-back mode offers the greatest  
performance of all the L2 cache modes.  
Copy-back L2 cache blocks implement a dirty bit in their tag RAM, which indicates  
whether the contents of the L2 cache block have been modiÞed from that in main memory.  
During L2 cache line replacement, L2 cache blocks that have been modiÞed (dirty) are  
written back to memory; unmodiÞed (not dirty) L2 cache blocks are invalidated and  
overwritten without being written back to memory.  
Copy-back mode requires that the L2 cache is able to initiate copy-backs to main memory.  
To do this, the L2 cache must act as a bus master and implement the bus arbitration signals  
BR, BG, and DBG. The MPC8260 can also support additional bus masters (60x or  
MPC8260 type) in copy-back mode.  
Figure 11-1 shows a MPC8260 connected to a MPC2605 integrated L2 cache in copy-back  
mode.  
MOTOROLA  
Chapter 11. Secondary (L2) Cache Support  
11-1  
       
Part III.The Hardware Interface  
(pull up)  
MPC8260  
MPC2605  
BR  
BG  
L2BR  
L2BG  
L2DBG  
DBG  
CPU_BR, CPU_BG, CPU_DBG  
TS, TT[0Ð4], TBST, TSIZ[1Ð3]  
CI, WT, GBL, TA, DBB, TEA  
AACK, ARTRY  
CPU_BR,CPU_BG,CPU_DBG  
TS, TT[0Ð4], TBST, TSIZ[0Ð2]]  
CI, WT, GBL, TA, DBB, TEA  
AACK, ARTRY  
TSIZ[0]  
(pull down)  
L2_HIT  
L2_CLAIM  
A[0Ð31]  
D[0Ð63]  
A[0Ð31]  
D[0Ð63]  
Latch  
MUX  
Memory Controller  
SDRAM Main Memory  
I/O Devices  
Figure 11-1. L2 Cache in Copy-Back Mode  
11.1.2 Write-Through Mode  
In write-through mode, cacheable write operations are performed to both the L2 cache and  
to main memory. Since every cacheable write operation goes to the L2 cache and to main  
memory, write operation latency is the same as an ordinary memory write transaction. In  
write-through mode, cacheable read operations that hit in the L2 cache are serviced from  
the L2 cache without requiring a memory transaction and its associated latency. Thus, reads  
11-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part III.The Hardware Interface  
are serviced just as they are for copy-back mode. Write-through mode sacriÞces some of  
the write performance of copy-back mode, but guarantees L2 cache coherency with main  
memory.  
Since write-through mode keeps memory coherent with the contents of the L2 cache, there  
is never any need to perform an L2 copy-back. This removes the need for the L2 cache to  
maintain a dirty bit in the tag RAM (all cache blocks are unmodiÞed) and it also removes  
the need for bus arbitration signals.  
The L2 cache is conÞgured for write-through mode by pulling down itÕs WT signal. There  
are no conÞguration changes to the MPC8260 required in write-through mode. The  
MPC8260 can also support additional bus masters (60x or MPC8260 type) in write-through  
mode.  
Figure 11-2 shows a MPC8260 connected to a MPC2605 integrated L2 cache in write-  
through mode.  
MOTOROLA  
Chapter 11. Secondary (L2) Cache Support  
11-3  
Part III.The Hardware Interface  
MPC8260  
MPC2605  
(pull up)  
(pull up)  
BR  
BG  
L2BR  
L2BG  
L2DBG  
DBG  
CPU_BR, CPU_BG, CPU_DBG  
TS, TT[0:4], TBST, TSIZ[1Ð3]  
CI, GBL, TA, DBB, TEA  
AACK, ARTRY  
CPU_BR,CPU_BG,CPU_DBG  
TS, TT[0Ð4], TBST, TSIZ[0Ð2]  
CI, GBL, TA, DBB, TEA  
AACK, ARTRY  
TSIZ[0]  
WT  
(pull down)  
(pull down)  
L2_HIT  
L2_CLAIM  
A[0Ð31]  
D[0Ð63]  
A[0Ð31]  
D[0Ð63]  
Latch  
MUX  
Memory Controller  
SDRAM Main Memory  
I/O Devices  
Figure 11-2. External L2 Cache in Write-Through Mode  
11.1.3 ECC/Parity Mode  
ECC/parity mode is a subset of write-through mode with some connection changes that  
allow the L2 cache to support ECC or Parity. The connection changes are:  
¥
¥
The MPC8260Õs DP[0:7] signals are connected to the L2 cacheÕs DP[0:7] signals.  
The L2Õs TSIZ[0:2] signals are pulled down to always indicate 8-byte transaction  
size.  
¥
The L2Õs A[29:31] signals are pulled down.  
11-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part III.The Hardware Interface  
In ECC/parity mode the L2 cache can support memory regions with ECC/Parity under the  
following restrictions:  
¥
All non-write-protected (BRx[WP] = 0) memory banks marked caching-allowed  
must use either ECC (BRx[DECC] = 0b11) or read-modify-write parity  
(BRx[DECC] = 0b10). See Section 10.3.1, ÒBase Registers (BRx),Ó for more  
information about the MPC8260 base register parameters.  
¥
Only MPC8260-type masters are supported in systems that use ECC/parity L2 cache  
mode. See Section 10.9, ÒExternal Master Support (60x-Compatible Mode),Ó for  
more information about external master types.  
Figure 11-3 shows a MPC8260 connected to an MPC2605 integrated L2 cache in ECC/  
Parity mode.  
MOTOROLA  
Chapter 11. Secondary (L2) Cache Support  
11-5  
Part III.The Hardware Interface  
MPC8260  
MPC2605  
(pull up)  
(pull up)  
BR  
BG  
L2BR  
L2BG  
L2DBG  
DBG  
CPU_BR, CPU_BG, CPU_DBG  
TS, TT[0Ð4], TBST  
CPU_BR,CPU_BG,CPU_DBG  
TS, TT[0Ð4], TBST  
TSIZ[0Ð2]  
(pull downs)  
CI, GBL, TA, DBB, TEA  
AACK, ARTRY  
TSIZE[0]  
CI, GBL, TA, DBB, TEA  
AACK, ARTRY  
WT  
(pull down)  
(pull down)  
L2_HIT  
L2_CLAIM  
A[29Ð31]  
(pull downs)  
A[0Ð31]  
A[0Ð28]  
D[0Ð63],DP[0Ð7]  
D[0Ð63], DP[0Ð7]  
Latch  
MUX  
Memory Controller  
SDRAM Main Memory  
I/O Devices  
Figure 11-3. External L2 Cache in ECC/Parity Mode  
11-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part III.The Hardware Interface  
11.2 L2 Cache Interface Parameters  
The L2 cache interface parameters in the bus conÞguration register (BCR) control the  
conÞguration and operation of the MPC8260Õs L2 interface. The parameters should be  
conÞgured as follows:  
¥
¥
¥
BCR[EBM] = 1ÑMPC8260 in 60x-compatible mode.  
BCR[L2C] = 1ÑL2 cache is present.  
BCR[L2D] = 0ÑL2 response time. In this case, the L2 will claim a bus transaction  
one clock cycle after TS assertion.  
¥
BCR[APD] = 1: This parameter is not L2 speciÞc, but should consider the L2  
ARTRY assertion timing.  
See Section 4.3.2.1, ÒBus ConÞguration Register (BCR),Ó for more details about these  
parameters.  
11.3 System RequirementsWhen Using the L2 Cache  
Interface  
The following requirements apply to MPC8260-based systems that implement an external  
L2 cache:  
¥
For systems that use copy-back mode, all cachable memory regions must be marked  
as global in the CPUÕs MMU and the CPMÕs RBA. This causes the assertion of the  
GBL signal on every cachable transaction. Systems that use write-through mode (or  
ECC/Parity mode) have no such restriction.  
¥
¥
¥
All cachable memory regions must have a 64-bit port size.  
All cachable memory regions must not set the BRx[DR] bit.  
All cachable memory regions must not use ECC or parity unless the external L2 is  
connected as described in Section 11.1.3, ÒECC/Parity Mode.Ó  
¥
All non-cachable memory regions must be marked as caching-inhibited in the  
CPUÕs MMU. This causes the assertion of the CI signal on every non-cachable  
transaction. Note that the MPC8260Õs internal space (IMMR) and any memory  
banks assigned to the local bus are always considered non-cachable.  
11.4 L2 Cache Operation  
When conÞgured for an L2 cache (BCR[L2C] = 1), the MPC8260 samples the L2_HIT  
input signal when the delay time programmed in BCR[L2D] expires. For 60x bus cycles, if  
L2_HIT is asserted, the external L2 cache drives AACK and TA to complete the transaction  
without the MPC8260 initiating a system memory transfer.  
The external L2 cache can assert ARTRY to retry 60x bus cycles, and can request the bus  
by asserting BR to perform L2 cast-out operations. The arbiter grants the address and data  
MOTOROLA  
Chapter 11. Secondary (L2) Cache Support  
11-7  
     
Part III.The Hardware Interface  
bus to the external L2 cache by asserting BG and DBG, respectively. If the external L2  
cache asserts ARTRY, it should not assert L2_HIT.  
For more information about the timing and behavior of the MPC2605 integrated L2 cache,  
refer to the MPC2605 data sheet.  
11.5 Timing Example  
Figure 11-4 shows a read access performed by the MPC8260 with an externally controlled  
L2 cache. For the Þrst transaction (A0), the MPC8260 grants the bus and asserts TS with  
the address and address transfer attributes. In this example, BCR[L2D] = 0, which means  
that L2_HIT is valid one clock cycle after the assertion of TS. The MPC8260 samples  
L2_HIT when L2D expires. In the second transaction (A1), the access misses in the L2  
cache and the memory controller starts the transaction a minimum of three cycles after the  
assertion of TS.  
11-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part III.The Hardware Interface  
CLK  
BR  
BG  
ABB  
Addr  
TS  
A0 & TBST& CI  
A1 & TBST  
disabled  
L2  
active  
Memc controls  
AACK  
MPC8260  
DBG  
DBB  
DATA  
TA  
D00  
D01  
D02  
D03  
0
L2D = 0  
L2 HIT  
0
Figure 11-4. Read Access with L2 Cache  
MOTOROLA  
Chapter 11. Secondary (L2) Cache Support  
11-9  
 
Part III.The Hardware Interface  
11-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Chapter 12  
IEEE 1149.1 Test Access Port  
120  
1T20 he MPC8260 provides a dedicated user-accessible test access port (TAP) that is fully  
compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan  
Architecture. Problems associated with testing high-density circuit boards have led to  
development of this proposed standard under the sponsorship of the Test Technology  
Committee of IEEE and the Joint Test Action Group (JTAG). The MPC8260Õs  
implementation supports circuit-board test strategies based on this standard.  
The TAP consists of Þve dedicated signal pinsÑa 16-state TAP controller and two test data  
registers. A boundary scan register links all device signal pins into a single shift register.  
The test logic, which is implemented using static logic design, is independent of the device  
system logic. The MPC8260Õs implementation provides the capability to do the following:  
¥
¥
Perform boundary scan operations to check circuit-board electrical continuity.  
Bypass the MPC8260 for a given circuit-board test by effectively reducing the  
boundary scan register to a single cell.  
¥
¥
Sample the MPC8260 system pins during operation and transparently shift out the  
result in the boundary-scan register.  
Disable the output drive to pins during circuit-board testing.  
NOTE  
Precautions must be observed to ensure that the IEEE 1149.1-  
like test logic does not interfere with nontest operation.  
12.1 Overview  
The MPC8260Õs implementation includes a TAP controller, a 4-bit instruction register, and  
two test registers (a 1-bit bypass register and a 475-bit boundary scan register). Figure 12-1  
shows an overview of the MPC8260Õs scan chain implementation.  
MOTOROLA  
Chapter 12. IEEE 1149.1Test Access Port  
12-1  
         
Part III.The Hardware Interface  
Boundary Scan Register  
M
U
X
TDI  
Bypass  
Instruction Apply & Decode Register  
3
2
1
0
M
U
X
TDO  
4ÐBit Instruction Register  
TRST  
TMS  
TCK  
TAP Controller  
Figure 12-1. Test Logic Block Diagram  
The TAP consists of the signals in Table 12-1.  
Table 12-1. TAP Signals  
Signal  
TCK A test clock input to synchronize the test logic.  
Description  
TMS A test mode select input (with an internal pull-up resistor) that is sampled on the rising edge of TCK to  
sequence the TAP controllerÕs state machine.  
TDI  
A test data input (with an internal pull-up resistor) that is sampled on the rising edge of TCK.  
TDO A data output that can be three-stated and actively driven in the shift-IR and shift-DR controller states. TDO  
changes on the falling edge of TCK.  
TRST An asynchronous reset with an internal pull-up resistor that provides initialization of the TAP controller and  
other logic required by the standard.  
12.2 TAP Controller  
The TAP controller is responsible for interpreting the sequence of logical values on the  
TMS signal. It is a synchronous state machine that controls the operation of the JTAG logic.  
The value shown adjacent to each bubble represents the value of the TMS signal sampled  
on the rising edge of the TCK signal. Figure 12-2 shows the state machine.  
12-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part III.The Hardware Interface  
Test Logic  
Reset  
1
0
0
1
1
1
RunÑTest/Idle  
SelectÑDR_SCAN  
SelectÑIR_SCAN  
0
0
CaptureÑDR  
CaptureÑIR  
0
0
ShiftÑDR  
ShiftÑIR  
1
1
Exit1ÑDR  
Exit1ÑIR  
0
0
PauseÑDR  
PauseÑIR  
1
Exit2ÑDR  
1
1
Exit2ÑIR  
1
UpdateÑDR  
0
UpdateÑIR  
0
1
1
Figure 12-2. TAP Controller State Machine  
12.3 Boundary Scan Register  
The MPC8260Õs scan chain implementation has a 475-bit boundary scan register that  
contains bits for all device signal, clock pins, and associated control signals. The XTAL,  
EXTAL, and XFC pins are associated with analog signals and are not included in the  
boundary scan register. An IEEE-1149.1-compliant boundary-scan register has been  
included on the MPC8260 that can be connected between TDI and TDO when EXTEST or  
SAMPLE/PRELOAD instructions are selected. It is used for capturing signal pin data on  
the input pins, forcing Þxed values on the output signal pins, and selecting the direction and  
drive characteristics (a logic value or high impedance) of the bidirectional and three-state  
signal pins. Figure 12-3, Figure 12-4, Figure 12-5, and Figure 12-6 show various cell types.  
MOTOROLA  
Chapter 12. IEEE 1149.1Test Access Port  
12-3  
     
Part III.The Hardware Interface  
Shift DR  
To Next Cell  
1 Ñ EXTEST | Clamp  
0 Ñ Otherwise  
G1  
Data from  
System  
Logic  
1
1
To Output  
Buffer  
MUX  
G1  
1
1
D
C
MUX  
D
C
From Last Cell  
Clock DR  
Update DR  
Figure 12-3. Output Pin Cell (O.Pin)  
To Next Cell  
Data to  
System  
Logic  
Input  
Pin  
G1  
D
C
1
1
MUX  
Shift DR  
From Last Cell  
Clock DR  
Figure 12-4. Observe-Only Input Pin Cell (I.Obs)  
12-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part III.The Hardware Interface  
Shift DR  
To Next Cell  
1 Ñ EXTEST | Clamp  
0 Ñ Otherwise  
G1  
Output Control  
from System  
Logic  
1
1
To Output  
Buffer  
MUX  
G1  
1
1
D
C
MUX  
D
C
From Last Cell  
Clock DR  
Update DR  
Figure 12-5. Output Control Cell (IO.CTL)  
From Last Cell  
Output Enable  
from System Logic  
I/O.CTL  
I/O  
Pin  
EN  
Output Data  
O.PIN  
Input Data  
I.OBS  
To Next Pin Pair  
To Next Cell  
Figure 12-6. General Arrangement of Bidirectional Pin Cells  
The control bit value controls the output function of the bidirectional pin. One or more  
bidirectional data cells can be serially connected to a control cell. Bidirectional pins include  
two scan cell for data (IO.Cell) as shown in Figure 12-6 and these bits are controlled by the  
cell shown in Figure 12-5.  
It is important to know the boundary scan bit order and pins that are associated with them.  
Table 12-2 shows the bit order starting with the TDO output and ending with the TDI input.  
The Þrst column of the table deÞnes the bitÕs ordinal position in the boundary scan register.  
The shift register cell nearest TDO (Þrst to be shifted in) is deÞned as Bit 1 and the last bit  
to be shifted in is bit 475. The second column references one of the three MPC8260Õs cell  
types depicted in Figure 12-3 through Figure 12-5 that describe the cell structure for each  
MOTOROLA  
Chapter 12. IEEE 1149.1Test Access Port  
12-5  
   
Part III.The Hardware Interface  
type. The third column lists the pin name for all pin-related cells and deÞnes the name of  
the bidirectional control register bits. The fourth column lists the pin type, and the last  
column indicates the associated boundary scan register control bit for the bidirectional  
output pins.  
Table 12-2. Boundary Scan Bit Definition  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
0
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
pa[4]  
pa[4]  
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
g2.ctl  
Ñ
1
2
g2.ctl  
3
spare5  
spare5  
g287.ctl  
pa[5]  
Ñ
4
g287.ctl  
Ñ
5
6
Ñ
7
pa[5]  
g286.ctl  
Ñ
8
g286.ctl  
pd[8]  
9
Ñ
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
pd[8]  
g285.ctl  
Ñ
g285.ctl  
pb[8]  
Ñ
pb[8]  
g284.ctl  
Ñ
g284.ctl  
pa[6]  
Ñ
pa[6]  
g283.ctl  
Ñ
g283.ctl  
pd[9]  
Ñ
pd[9]  
g282.ctl  
Ñ
g282.ctl  
pc[5]  
Ñ
pc[5]  
g281.ctl  
Ñ
g281.ctl  
pb[9]  
Ñ
pb[9]  
g280.ctl  
Ñ
g280.ctl  
pa[7]  
Ñ
pa[7]  
g279.ctl  
Ñ
g279.ctl  
pd[10]  
pd[10]  
g278.ctl  
pc[6]  
Ñ
g278.ctl  
Ñ
Ñ
pc[6]  
g277.ctl  
12-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
g277.ctl  
pb[10]  
pb[10]  
g276.ctl  
pa[8]  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
Ñ
g276.ctl  
Ñ
Ñ
pa[8]  
g275.ctl  
Ñ
g275.ctl  
pd[12]  
pd[12]  
g274.ctl  
pc[7]  
Ñ
g274.ctl  
Ñ
Ñ
pc[7]  
g273.ctl  
Ñ
g273.ctl  
pb[11]  
pb[11]  
g272.ctl  
pa[9]  
Ñ
g272.ctl  
Ñ
Ñ
pa[9]  
g271.ctl  
Ñ
g271.ctl  
pa[10]  
pa[10]  
g269.ctl  
pd[11]  
pd[11]  
g268.ctl  
pc[8]  
Ñ
g269.ctl  
Ñ
Ñ
g268.ctl  
Ñ
Ñ
pc[8]  
g267.ctl  
Ñ
g267.ctl  
pb[12]  
pb[12]  
g266.ctl  
pa[11]  
pa[11]  
g265.ctl  
pd[13]  
pd[13]  
g264.ctl  
pc[9]  
Ñ
g266.ctl  
Ñ
Ñ
g265.ctl  
Ñ
Ñ
g264.ctl  
Ñ
Ñ
pc[9]  
g263.ctl  
MOTOROLA  
Chapter 12. IEEE 1149.1Test Access Port  
12-7  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
74  
75  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
g263.ctl  
pb[13]  
pb[13]  
g262.ctl  
pa[12]  
pa[12]  
g261.ctl  
pd[14]  
pd[14]  
g260.ctl  
pc[10]  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
Ñ
76  
g262.ctl  
Ñ
77  
78  
Ñ
79  
g261.ctl  
Ñ
80  
81  
Ñ
82  
g260.ctl  
Ñ
83  
84  
Ñ
85  
pc[10]  
g259.ctl  
Ñ
86  
g259.ctl  
pb[14]  
pb[14]  
g258.ctl  
pa[13]  
pa[13]  
g257.ctl  
pd[15]  
pd[15]  
g256.ctl  
pc[11]  
87  
Ñ
88  
g258.ctl  
Ñ
89  
90  
Ñ
91  
g257.ctl  
Ñ
92  
93  
Ñ
94  
g256.ctl  
Ñ
95  
96  
Ñ
97  
pc[11]  
g255.ctl  
Ñ
98  
g255.ctl  
pb[15]  
pb[15]  
g254.ctl  
pa[14]  
pa[14]  
g253.ctl  
pc[12]  
99  
Ñ
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
g254.ctl  
Ñ
Ñ
g253.ctl  
Ñ
Ñ
pc[12]  
g252.ctl  
Ñ
g252.ctl  
pa[15]  
pa[15]  
g251.ctl  
pd[16]  
pd[16]  
Ñ
g251.ctl  
Ñ
Ñ
g250.ctl  
12-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
g250.ctl  
pc[13]  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
Ñ
pc[13]  
g249.ctl  
Ñ
g249.ctl  
pb[16]  
pb[16]  
g248.ctl  
pa[16]  
pa[16]  
g247.ctl  
pd[17]  
pd[17]  
g246.ctl  
pc[14]  
Ñ
g248.ctl  
Ñ
Ñ
g247.ctl  
Ñ
Ñ
g246.ctl  
Ñ
Ñ
pc[14]  
g245.ctl  
Ñ
g245.ctl  
pb[17]  
pb[17]  
g244.ctl  
pa[17]  
pa[17]  
g243.ctl  
pd[18]  
pd[18]  
g242.ctl  
pc[15]  
Ñ
g244.ctl  
Ñ
Ñ
g243.ctl  
Ñ
Ñ
g242.ctl  
Ñ
Ñ
pc[15]  
g241.ctl  
Ñ
g241.ctl  
pb[22]  
pb[22]  
g240.ctl  
pa[18]  
pa[18]  
g239.ctl  
pd[19]  
pd[19]  
g238.ctl  
pc[16]  
Ñ
g240.ctl  
Ñ
Ñ
g239.ctl  
Ñ
Ñ
g238.ctl  
Ñ
Ñ
pc[16]  
g237.ctl  
MOTOROLA  
Chapter 12. IEEE 1149.1Test Access Port  
12-9  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
174  
175  
176  
177  
178  
179  
180  
181  
182  
183  
184  
185  
186  
187  
188  
189  
190  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
g237.ctl  
pb[23]  
pb[23]  
g236.ctl  
pa[19]  
pa[19]  
g235.ctl  
pc[17]  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
Ñ
g236.ctl  
Ñ
Ñ
g235.ctl  
Ñ
Ñ
pc[17]  
g234.ctl  
Ñ
g234.ctl  
pd[20]  
pd[20]  
g233.ctl  
pc[18]  
Ñ
g233.ctl  
Ñ
Ñ
pc[18]  
g232.ctl  
Ñ
g232.ctl  
pb[18]  
pb[18]  
g231.ctl  
pa[20]  
pa[20]  
g230.ctl  
pd[21]  
pd[21]  
g229.ctl  
pc[19]  
Ñ
g231.ctl  
Ñ
Ñ
g230.ctl  
Ñ
Ñ
g229.ctl  
Ñ
Ñ
pc[19]  
g228.ctl  
Ñ
g228.ctl  
pb[19]  
pb[19]  
g227.ctl  
pa[21]  
pa[21]  
g226.ctl  
pd[22]  
pd[22]  
g225.ctl  
pc[20]  
Ñ
g227.ctl  
Ñ
Ñ
g226.ctl  
Ñ
Ñ
g225.ctl  
Ñ
Ñ
pc[20]  
g224.ctl  
12-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
191  
192  
193  
194  
195  
196  
197  
198  
199  
200  
201  
202  
203  
204  
205  
206  
207  
208  
209  
210  
211  
212  
213  
214  
215  
216  
217  
218  
219  
220  
221  
222  
223  
224  
225  
226  
227  
228  
229  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
g224.ctl  
pb[20]  
pb[20]  
g223.ctl  
pa[22]  
pa[22]  
g222.ctl  
pd[23]  
pd[23]  
g221.ctl  
pc[21]  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
Ñ
g223.ctl  
Ñ
Ñ
g222.ctl  
Ñ
Ñ
g221.ctl  
Ñ
Ñ
pc[21]  
g220.ctl  
Ñ
g220.ctl  
pb[21]  
pb[21]  
g219.ctl  
pa[23]  
pa[23]  
g218.ctl  
spare1  
spare1  
g121.ctl  
pc[22]  
Ñ
g219.ctl  
Ñ
Ñ
g218.ctl  
Ñ
Ñ
g121.ctl  
Ñ
Ñ
pc[22]  
g217.ctl  
Ñ
g217.ctl  
pd[24]  
pd[24]  
g216.ctl  
pc[23]  
Ñ
g216.ctl  
Ñ
Ñ
pc[23]  
g215.ctl  
Ñ
g215.ctl  
pb[24]  
pb[24]  
g214.ctl  
pa[24]  
pa[24]  
g213.ctl  
pd[25]  
pd[25]  
Ñ
g214.ctl  
Ñ
Ñ
g213.ctl  
Ñ
Ñ
g212.ctl  
MOTOROLA  
Chapter 12. IEEE 1149.1Test Access Port  
12-11  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
230  
231  
232  
233  
234  
235  
236  
237  
238  
239  
240  
241  
242  
243  
244  
245  
246  
247  
248  
249  
250  
251  
252  
253  
254  
255  
256  
257  
258  
259  
260  
261  
262  
263  
264  
265  
266  
267  
268  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
i.obs  
o.pin  
IO.ctl  
i.obs  
g212.ctl  
pc[24]  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
i
Ñ
Ñ
pc[24]  
g211.ctl  
Ñ
g211.ctl  
pb[25]  
Ñ
pb[25]  
g210.ctl  
Ñ
g210.ctl  
pa[25]  
Ñ
pa[25]  
g209.ctl  
Ñ
g209.ctl  
pd[26]  
Ñ
pd[26]  
g208.ctl  
Ñ
g208.ctl  
pc[25]  
Ñ
pc[25]  
g207.ctl  
Ñ
g207.ctl  
pb[26]  
Ñ
pb[26]  
g206.ctl  
Ñ
g206.ctl  
pa[26]  
Ñ
pa[26]  
g205.ctl  
Ñ
g205.ctl  
pd[27]  
Ñ
pd[27]  
g204.ctl  
Ñ
g204.ctl  
pc[26]  
Ñ
pc[26]  
g203.ctl  
Ñ
g203.ctl  
pb[27]  
Ñ
pb[27]  
g202.ctl  
Ñ
g202.ctl  
pa[27]  
Ñ
pa[27]  
g201.ctl  
Ñ
g201.ctl  
rstconf_b  
hreset_b  
hreset_b  
g171.ctl  
sreset_b  
Ñ
io  
io  
Ñ
io  
Ñ
g171.ctl  
Ñ
Ñ
12-12  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
269  
270  
271  
272  
273  
274  
275  
276  
277  
278  
279  
280  
281  
282  
283  
284  
285  
286  
287  
288  
289  
290  
291  
292  
293  
294  
295  
296  
297  
298  
299  
300  
301  
302  
303  
304  
305  
306  
307  
o.pin  
IO.ctl  
i.obs  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
sreset_b  
g170.ctl  
clkin  
io  
Ñ
i
g170.ctl  
Ñ
Ñ
pc[27]  
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
Ñ
pc[27]  
g166.ctl  
Ñ
g166.ctl  
pd[28]  
pd[28]  
g165.ctl  
pc[28]  
Ñ
g165.ctl  
Ñ
Ñ
pc[28]  
g164.ctl  
Ñ
g164.ctl  
pb[28]  
pb[28]  
g163.ctl  
pa[28]  
pa[28]  
g162.ctl  
pd[29]  
pd[29]  
g161.ctl  
pc[29]  
Ñ
g163.ctl  
Ñ
Ñ
g162.ctl  
Ñ
Ñ
g161.ctl  
Ñ
Ñ
pc[29]  
g160.ctl  
Ñ
g160.ctl  
pb[29]  
pb[29]  
g159.ctl  
pa[29]  
pa[29]  
g158.ctl  
pd[30]  
pd[30]  
g157.ctl  
pc[30]  
Ñ
g159.ctl  
Ñ
Ñ
g158.ctl  
Ñ
Ñ
g157.ctl  
Ñ
Ñ
pc[30]  
g156.ctl  
Ñ
g156.ctl  
pb[30]  
pb[30]  
g155.ctl  
Ñ
g155.ctl  
Ñ
MOTOROLA  
Chapter 12. IEEE 1149.1Test Access Port  
12-13  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
308  
309  
310  
311  
312  
313  
314  
315  
316  
317  
318  
319  
320  
321  
322  
323  
324  
325  
326  
327  
328  
329  
330  
331  
332  
333  
334  
335  
336  
337  
338  
339  
340  
341  
342  
343  
344  
345  
346  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
pa[30]  
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
i
Ñ
g154.ctl  
Ñ
pa[30]  
g154.ctl  
pd[31]  
Ñ
pd[31]  
g153.ctl  
Ñ
g153.ctl  
pc[31]  
Ñ
pc[31]  
g152.ctl  
Ñ
g152.ctl  
pb[31]  
Ñ
pb[31]  
g151.ctl  
Ñ
g151.ctl  
pa[31]  
Ñ
pa[31]  
g150.ctl  
g150.ctl  
Ñ
tris_b  
Ñ
qreq_b  
o
Ñ
l2_hit_b_irq4_b  
cpu_br_b  
i
Ñ
o
Ñ
br_b  
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
br_b  
g139.ctl  
Ñ
g139.ctl  
modclk3_ap3_tc2_bnksel2  
modclk3_ap3_tc2_bnksel2  
g138.ctl  
Ñ
g138.ctl  
Ñ
modclk2_ap2_tc1_bnksel1  
modclk2_ap2_tc1_bnksel1  
g137.ctl  
Ñ
g137.ctl  
Ñ
modclk1_ap1_tc0_bnksel0  
modclk1_ap1_tc0_bnksel0  
g136.ctl  
Ñ
g136.ctl  
Ñ
gbl_b_irq1_b  
gbl_b_irq1_b  
g133.ctl  
Ñ
g133.ctl  
Ñ
tea_b  
Ñ
tea_b  
g132.ctl  
Ñ
g132.ctl  
spare6  
Ñ
spare6  
g89.ctl  
12-14  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
347  
348  
349  
350  
351  
352  
353  
354  
355  
356  
357  
358  
359  
360  
361  
362  
363  
364  
365  
366  
367  
368  
369  
370  
371  
372  
373  
374  
375  
376  
377  
378  
379  
380  
381  
382  
383  
384  
385  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
o.pin  
o.pin  
o.pin  
i.obs  
o.pin  
IO.ctl  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
g89.ctl  
psdval_b  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
o
Ñ
Ñ
psdval_b  
g130.ctl  
Ñ
g130.ctl  
dbb_b_irq3_b  
dbb_b_irq3_b  
g129.ctl  
Ñ
g129.ctl  
Ñ
dbg_b  
Ñ
dbg_b  
g128.ctl  
Ñ
g128.ctl  
spare4  
Ñ
spare4  
g127.ctl  
Ñ
g127.ctl  
cpu_bg_b_baddr31_irq5_b  
cpu_bg_b_baddr31_irq5_b  
g126.ctl  
Ñ
g126.ctl  
Ñ
wt_b_baddr30_irq3_b  
wt_b_baddr30_irq3_b  
g125.ctl  
Ñ
g125.ctl  
Ñ
ci_b_baddr29_irq2_b  
ci_b_baddr29_irq2_b  
g124.ctl  
Ñ
g124.ctl  
Ñ
baddr[28]  
Ñ
baddr[27]  
o
Ñ
ale  
o
Ñ
irq0_b_nmi_out_b  
irq0_b_nmi_out_b  
g120.ctl  
io  
io  
Ñ
o
Ñ
g120.ctl  
Ñ
cpu_dbg_b  
a[31]  
Ñ
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
a[31]  
g111.ctl  
Ñ
a[30]  
a[30]  
g111.ctl  
Ñ
a[29]  
a[29]  
g111.ctl  
Ñ
a[28]  
a[28]  
g111.ctl  
Ñ
a[27]  
a[27]  
g111.ctl  
MOTOROLA  
Chapter 12. IEEE 1149.1Test Access Port  
12-15  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
386  
387  
388  
389  
390  
391  
392  
393  
394  
395  
396  
397  
398  
399  
400  
401  
402  
403  
404  
405  
406  
407  
408  
409  
410  
411  
412  
413  
414  
415  
416  
417  
418  
419  
420  
421  
422  
423  
424  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
g111.ctl  
a[26]  
a[26]  
a[25]  
a[25]  
a[24]  
a[24]  
a[23]  
a[23]  
a[22]  
a[22]  
a[21]  
a[21]  
a[20]  
a[20]  
a[19]  
a[19]  
g110.ctl  
a[18]  
a[18]  
a[17]  
a[17]  
a[16]  
a[16]  
a[15]  
a[15]  
a[14]  
a[14]  
a[13]  
a[13]  
a[12]  
a[12]  
a[11]  
a[11]  
g109.ctl  
a[10]  
a[10]  
a[9]  
Ñ
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
io  
io  
Ñ
Ñ
g111.ctl  
Ñ
g111.ctl  
Ñ
g111.ctl  
Ñ
g110.ctl  
Ñ
g110.ctl  
Ñ
g110.ctl  
Ñ
g110.ctl  
Ñ
g110.ctl  
Ñ
Ñ
g110.ctl  
Ñ
g110.ctl  
Ñ
g110.ctl  
Ñ
g109.ctl  
Ñ
g109.ctl  
Ñ
g109.ctl  
Ñ
g109.ctl  
Ñ
g109.ctl  
Ñ
Ñ
g109.ctl  
Ñ
a[9]  
g109.ctl  
12-16  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
425  
426  
427  
428  
429  
430  
431  
432  
433  
434  
435  
436  
437  
438  
439  
440  
441  
442  
443  
444  
445  
446  
447  
448  
449  
450  
451  
452  
453  
454  
455  
456  
457  
458  
459  
460  
461  
462  
463  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
a[8]  
a[8]  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
Ñ
g109.ctl  
Ñ
a[7]  
a[7]  
g108.ctl  
Ñ
a[6]  
a[6]  
g108.ctl  
Ñ
a[5]  
a[5]  
g108.ctl  
Ñ
a[4]  
a[4]  
g108.ctl  
Ñ
a[3]  
a[3]  
g108.ctl  
Ñ
g108.ctl  
a[2]  
Ñ
a[2]  
g108.ctl  
Ñ
a[1]  
a[1]  
g108.ctl  
Ñ
a[0]  
a[0]  
g108.ctl  
Ñ
tt[3]  
tt[3]  
g112.ctl  
Ñ
tt[2]  
tt[2]  
g112.ctl  
Ñ
g112.ctl  
tt[1]  
Ñ
tt[1]  
g112.ctl  
Ñ
tt[0]  
tt[0]  
g112.ctl  
Ñ
tt[4]  
tt[4]  
g112.ctl  
Ñ
artry_b  
artry_b  
g118.ctl  
aack_b  
aack_b  
g117.ctl  
abb_b_irq2_b  
abb_b_irq2_b  
g116.ctl  
g118.ctl  
Ñ
Ñ
g117.ctl  
Ñ
Ñ
g116.ctl  
Ñ
MOTOROLA  
Chapter 12. IEEE 1149.1Test Access Port  
12-17  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
464  
465  
466  
467  
468  
469  
470  
471  
472  
473  
474  
475  
476  
477  
478  
479  
480  
481  
482  
483  
484  
485  
486  
487  
488  
489  
490  
491  
492  
493  
494  
495  
496  
497  
498  
499  
500  
501  
502  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
bg_b  
bg_b  
io  
io  
Ñ
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
g115.ctl  
Ñ
g115.ctl  
irq7_b_int_out_b_ape_b  
irq7_b_int_out_b_ape_b  
g114.ctl  
ts_b  
Ñ
g114.ctl  
Ñ
Ñ
ts_b  
g113.ctl  
Ñ
tsize[3]  
tsize[3]  
tsize[2]  
tsize[2]  
g113.ctl  
tsize[1]  
tsize[1]  
tsize[0]  
tsize[0]  
tbst_b  
g113.ctl  
Ñ
g113.ctl  
Ñ
Ñ
g113.ctl  
Ñ
g113.ctl  
Ñ
tbst_b  
g113.ctl  
Ñ
d[63]  
d[63]  
g91.ctl  
Ñ
g91.ctl  
d[55]  
Ñ
d[55]  
g107.ctl  
Ñ
d[47]  
d[47]  
g107.ctl  
Ñ
d[39]  
d[39]  
g107.ctl  
Ñ
d[31]  
d[31]  
g107.ctl  
Ñ
g107.ctl  
d[23]  
Ñ
d[23]  
g107.ctl  
Ñ
d[15]  
d[15]  
g107.ctl  
Ñ
d[7]  
d[7]  
g107.ctl  
Ñ
d[62]  
d[62]  
g106.ctl  
12-18  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
503  
504  
505  
506  
507  
508  
509  
510  
511  
512  
513  
514  
515  
516  
517  
518  
519  
520  
521  
522  
523  
524  
525  
526  
527  
528  
529  
530  
531  
532  
533  
534  
535  
536  
537  
538  
539  
540  
541  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
d[54]  
d[54]  
d[46]  
d[46]  
d[38]  
d[38]  
d[30]  
d[30]  
g106.ctl  
d[22]  
d[22]  
d[14]  
d[14]  
d[6]  
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
g106.ctl  
Ñ
g106.ctl  
Ñ
g106.ctl  
Ñ
g106.ctl  
Ñ
Ñ
g106.ctl  
Ñ
g106.ctl  
Ñ
d[6]  
g106.ctl  
Ñ
d[61]  
d[61]  
d[53]  
d[53]  
d[45]  
d[45]  
d[37]  
d[37]  
d[29]  
d[29]  
g105.ctl  
d[21]  
d[21]  
d[13]  
d[13]  
d[5]  
g105.ctl  
Ñ
g105.ctl  
Ñ
g105.ctl  
Ñ
g105.ctl  
Ñ
g105.ctl  
Ñ
Ñ
g105.ctl  
Ñ
g105.ctl  
Ñ
d[5]  
g105.ctl  
Ñ
d[60]  
d[60]  
d[52]  
d[52]  
d[44]  
d[44]  
d[36]  
g104.ctl  
Ñ
g104.ctl  
Ñ
g104.ctl  
Ñ
MOTOROLA  
Chapter 12. IEEE 1149.1Test Access Port  
12-19  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
542  
543  
544  
545  
546  
547  
548  
549  
550  
551  
552  
553  
554  
555  
556  
557  
558  
559  
560  
561  
562  
563  
564  
565  
566  
567  
568  
569  
570  
571  
572  
573  
574  
575  
576  
577  
578  
579  
580  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
d[36]  
d[28]  
d[28]  
g104.ctl  
d[20]  
d[20]  
d[12]  
d[12]  
d[4]  
io  
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
io  
g104.ctl  
Ñ
g104.ctl  
Ñ
Ñ
g104.ctl  
Ñ
g104.ctl  
Ñ
d[4]  
g104.ctl  
Ñ
d[59]  
d[59]  
d[51]  
d[51]  
d[43]  
d[43]  
d[35]  
d[35]  
d[27]  
d[27]  
g103.ctl  
d[19]  
d[19]  
d[11]  
d[11]  
d[3]  
g103.ctl  
Ñ
g103.ctl  
Ñ
g103.ctl  
Ñ
g103.ctl  
Ñ
g103.ctl  
Ñ
Ñ
g103.ctl  
Ñ
g103.ctl  
Ñ
d[3]  
g103.ctl  
Ñ
d[58]  
d[58]  
d[50]  
d[50]  
d[42]  
d[42]  
d[34]  
d[34]  
d[26]  
d[26]  
g102.ctl  
d[18]  
g102.ctl  
Ñ
g102.ctl  
Ñ
g102.ctl  
Ñ
g102.ctl  
Ñ
g102.ctl  
Ñ
Ñ
12-20  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
581  
582  
583  
584  
585  
586  
587  
588  
589  
590  
591  
592  
593  
594  
595  
596  
597  
598  
599  
600  
601  
602  
603  
604  
605  
606  
607  
608  
609  
610  
611  
612  
613  
614  
615  
616  
617  
618  
619  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
d[18]  
d[10]  
d[10]  
d[2]  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
g102.ctl  
Ñ
g102.ctl  
Ñ
d[2]  
g102.ctl  
Ñ
d[57]  
d[57]  
d[49]  
d[49]  
d[41]  
d[41]  
d[33]  
d[33]  
d[25]  
d[25]  
g101.ctl  
d[17]  
d[17]  
d[9]  
g101.ctl  
Ñ
g101.ctl  
Ñ
g101.ctl  
Ñ
g101.ctl  
Ñ
g101.ctl  
Ñ
Ñ
g101.ctl  
Ñ
d[9]  
g101.ctl  
Ñ
d[1]  
d[1]  
g101.ctl  
Ñ
d[56]  
d[56]  
d[48]  
d[48]  
d[40]  
d[40]  
d[32]  
d[32]  
d[24]  
d[24]  
g100.ctl  
d[16]  
d[16]  
d[8]  
g100.ctl  
Ñ
g100.ctl  
Ñ
g100.ctl  
Ñ
g100.ctl  
Ñ
g100.ctl  
Ñ
Ñ
g100.ctl  
Ñ
d[8]  
g100.ctl  
Ñ
d[0]  
d[0]  
g100.ctl  
MOTOROLA  
Chapter 12. IEEE 1149.1Test Access Port  
12-21  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
620  
621  
622  
623  
624  
625  
626  
627  
628  
629  
630  
631  
632  
633  
634  
635  
636  
637  
638  
639  
640  
641  
642  
643  
644  
645  
646  
647  
648  
649  
650  
651  
652  
653  
654  
655  
656  
657  
658  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
o.pin  
i.obs  
o.pin  
IO.ctl  
o.pin  
o.pin  
o.pin  
o.pin  
o.pin  
o.pin  
o.pin  
o.pin  
dp7_cse1_irq7_b  
dp7_cse1_irq7_b  
g99.ctl  
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
o
Ñ
g99.ctl  
Ñ
dp6_cse0_irq6_b  
dp6_cse0_irq6_b  
g98.ctl  
Ñ
g98.ctl  
Ñ
dp5_tben_irq5_b  
dp5_tben_irq5_b  
g97.ctl  
Ñ
g97.ctl  
Ñ
dp4_irq4_b  
Ñ
dp4_irq4_b  
g96.ctl  
Ñ
g96.ctl  
dp3_irq3_b  
Ñ
dp3_irq3_b  
g95.ctl  
Ñ
g95.ctl  
dp2_tlbisync_b_irq2_b  
dp2_tlbisync_b_irq2_b  
g94.ctl  
Ñ
g94.ctl  
Ñ
dp1_irq1_b  
Ñ
dp1_irq1_b  
g93.ctl  
Ñ
g93.ctl  
dp0_rsrv_b  
Ñ
dp0_rsrv_b  
g92.ctl  
Ñ
g92.ctl  
ta_b  
Ñ
ta_b  
g131.ctl  
Ñ
g131.ctl  
sdamux_gpl5  
gta_b_upwait_gpl4_pbs  
gta_b_upwait_gpl4_pbs  
g87.ctl  
Ñ
io  
io  
Ñ
o
Ñ
g87.ctl  
Ñ
sdcas_b_gpl3  
oe_b_sdras_b_gpl2  
sdwe_b_gpl1  
sda10_gpl0  
Ñ
o
Ñ
o
Ñ
o
Ñ
we_dqm_bs_b[7]  
we_dqm_bs_b[6]  
we_dqm_bs_b[5]  
we_dqm_bs_b[4]  
o
Ñ
o
Ñ
o
Ñ
o
Ñ
12-22  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
659  
660  
661  
662  
663  
664  
665  
666  
667  
668  
669  
670  
671  
672  
673  
674  
675  
676  
677  
678  
679  
680  
681  
682  
683  
684  
685  
686  
687  
688  
689  
690  
691  
692  
693  
694  
695  
696  
697  
o.pin  
o.pin  
o.pin  
o.pin  
o.pin  
o.pin  
i.obs  
o.pin  
IO.ctl  
o.pin  
o.pin  
o.pin  
o.pin  
o.pin  
o.pin  
o.pin  
o.pin  
o.pin  
o.pin  
o.pin  
o.pin  
o.pin  
o.pin  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
o.pin  
o.pin  
o.pin  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
we_dqm_bs_b[3]  
we_dqm_bs_b[2]  
we_dqm_bs_b[1]  
bctl0_b  
o
o
Ñ
Ñ
o
Ñ
o
Ñ
we_dqm_bs_b[0]  
lsdamux_gpl5  
lgta_b_upwait_gpl4_pbs  
lgta_b_upwait_gpl4_pbs  
g66.ctl  
o
Ñ
o
Ñ
io  
io  
Ñ
o
Ñ
g66.ctl  
Ñ
lsdcas_b_gpl3  
loe_b_sdras_b_gpl2  
lsdwe_b_gpl1  
lsda10_gpl0  
lwr_b  
Ñ
o
Ñ
o
Ñ
o
Ñ
o
Ñ
cs_b[0]  
o
Ñ
cs_b[1]  
o
Ñ
cs_b[2]  
o
Ñ
cs_b[3]  
o
Ñ
cs_b[4]  
o
Ñ
cs_b[5]  
o
Ñ
cs_b[6]  
o
Ñ
cs_b[7]  
o
Ñ
cs_b[8]  
o
Ñ
cs_b[9]  
o
Ñ
cs10_b_bctl1_b_dbg_dis  
cs10_b_bctl1_b_dbg_dis  
g59.ctl  
io  
io  
Ñ
io  
io  
Ñ
o
Ñ
g59.ctl  
Ñ
cs11_b_ap0  
cs11_b_ap0  
g60.ctl  
Ñ
g60.ctl  
Ñ
lwe_dqm_bs_b[3]  
lwe_dqm_bs_b[2]  
lwe_dqm_bs_b[1]  
lwe_dqm_bs_b[0]  
lcl_d_ad[0]  
Ñ
o
Ñ
o
Ñ
o
Ñ
io  
io  
io  
io  
Ñ
Ñ
lcl_d_ad[0]  
g40.ctl  
Ñ
lcl_d_ad[5]  
lcl_d_ad[5]  
g48.ctl  
Ñ
g48.ctl  
MOTOROLA  
Chapter 12. IEEE 1149.1Test Access Port  
12-23  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
698  
699  
700  
701  
702  
703  
704  
705  
706  
707  
708  
709  
710  
711  
712  
713  
714  
715  
716  
717  
718  
719  
720  
721  
722  
723  
724  
725  
726  
727  
728  
729  
730  
731  
732  
733  
734  
735  
736  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
lcl_d_ad[4]  
lcl_d_ad[4]  
lcl_d_ad[3]  
lcl_d_ad[3]  
lcl_d_ad[2]  
lcl_d_ad[2]  
lcl_d_ad[1]  
lcl_d_ad[1]  
lcl_d_ad[6]  
lcl_d_ad[6]  
g40.ctl  
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
g40.ctl  
Ñ
g40.ctl  
Ñ
g40.ctl  
Ñ
g40.ctl  
Ñ
g40.ctl  
Ñ
lcl_d_ad[10]  
lcl_d_ad[10]  
lcl_d_ad[9]  
lcl_d_ad[9]  
lcl_d_ad[8]  
lcl_d_ad[8]  
lcl_dp_c_be[0]  
lcl_dp_c_be[0]  
g49.ctl  
Ñ
g40.ctl  
Ñ
g40.ctl  
Ñ
g40.ctl  
Ñ
g49.ctl  
Ñ
lcl_d_ad[7]  
lcl_d_ad[7]  
lcl_d_ad[14]  
lcl_d_ad[14]  
lcl_d_ad[13]  
lcl_d_ad[13]  
g41.ctl  
Ñ
g41.ctl  
Ñ
g41.ctl  
Ñ
g41.ctl  
Ñ
lcl_d_ad[12]  
lcl_d_ad[12]  
lcl_d_ad[11]  
lcl_d_ad[11]  
l_a26_gnt1_b  
l_a26_gnt1_b  
g32.ctl  
Ñ
g41.ctl  
Ñ
g41.ctl  
Ñ
g32.ctl  
Ñ
l_a22_serr_b  
l_a22_serr_b  
g28.ctl  
Ñ
g28.ctl  
Ñ
l_a14_par  
Ñ
l_a14_par  
g20.ctl  
12-24  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
737  
738  
739  
740  
741  
742  
743  
744  
745  
746  
747  
748  
749  
750  
751  
752  
753  
754  
755  
756  
757  
758  
759  
760  
761  
762  
763  
764  
765  
766  
767  
768  
769  
770  
771  
772  
773  
774  
775  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
g20.ctl  
lcl_dp_c_be[1]  
lcl_dp_c_be[1]  
g44.ctl  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
io  
io  
io  
Ñ
Ñ
g44.ctl  
Ñ
lcl_d_ad[15]  
lcl_d_ad[15]  
g47.ctl  
Ñ
g47.ctl  
Ñ
l_a30_lock_b  
l_a30_lock_b  
g36.ctl  
Ñ
g36.ctl  
Ñ
l_a21_perr_b  
l_a21_perr_b  
g27.ctl  
Ñ
g27.ctl  
Ñ
l_a24_req1_b  
l_a24_req1_b  
g30.ctl  
Ñ
g30.ctl  
Ñ
l_a19_devsel_b  
l_a19_devsel_b  
g25.ctl  
Ñ
g25.ctl  
Ñ
l_a17_irdy_b_ckstp_out  
l_a17_irdy_b_ckstp_out  
g23.ctl  
Ñ
g23.ctl  
Ñ
l_a16_trdy_b  
l_a16_trdy_b  
g22.ctl  
Ñ
g22.ctl  
Ñ
l_a18_stop_b  
l_a18_stop_b  
g24.ctl  
Ñ
g24.ctl  
Ñ
l_a15_frm_b_smi_b  
l_a15_frm_b_smi_b  
g21.ctl  
Ñ
g21.ctl  
Ñ
lcl_dp_c_be[2]  
lcl_dp_c_be[2]  
g46.ctl  
Ñ
g46.ctl  
Ñ
lcl_d_ad[16]  
lcl_d_ad[16]  
lcl_d_ad[17]  
lcl_d_ad[17]  
lcl_d_ad[18]  
Ñ
g42.ctl  
Ñ
g42.ctl  
Ñ
MOTOROLA  
Chapter 12. IEEE 1149.1Test Access Port  
12-25  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
776  
777  
778  
779  
780  
781  
782  
783  
784  
785  
786  
787  
788  
789  
790  
791  
792  
793  
794  
795  
796  
797  
798  
799  
800  
801  
802  
803  
804  
805  
806  
807  
808  
809  
810  
811  
812  
813  
814  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
i.obs  
o.pin  
IO.ctl  
i.obs  
lcl_d_ad[18]  
lcl_d_ad[19]  
lcl_d_ad[19]  
g42.ctl  
io  
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
io  
io  
io  
io  
io  
io  
io  
io  
io  
io  
Ñ
io  
g42.ctl  
Ñ
g42.ctl  
Ñ
lcl_d_ad[20]  
lcl_d_ad[20]  
lcl_d_ad[21]  
lcl_d_ad[21]  
lcl_d_ad[22]  
lcl_d_ad[22]  
lcl_d_ad[23]  
lcl_d_ad[23]  
l_a20_idsel_b  
l_a20_idsel_b  
g26.ctl  
Ñ
g42.ctl  
Ñ
g42.ctl  
Ñ
g42.ctl  
Ñ
g42.ctl  
Ñ
g26.ctl  
Ñ
lcl_dp_c_be[3]  
lcl_dp_c_be[3]  
g45.ctl  
Ñ
g45.ctl  
Ñ
lcl_d_ad[24]  
lcl_d_ad[24]  
lcl_d_ad[25]  
lcl_d_ad[25]  
lcl_d_ad[26]  
lcl_d_ad[26]  
lcl_d_ad[27]  
lcl_d_ad[27]  
g43.ctl  
Ñ
g43.ctl  
Ñ
g43.ctl  
Ñ
g43.ctl  
Ñ
g43.ctl  
Ñ
lcl_d_ad[28]  
lcl_d_ad[28]  
lcl_d_ad[29]  
lcl_d_ad[29]  
lcl_d_ad[30]  
lcl_d_ad[30]  
lcl_d_ad[31]  
lcl_d_ad[31]  
l_a23_req0_b  
l_a23_req0_b  
g29.ctl  
Ñ
g43.ctl  
Ñ
g43.ctl  
Ñ
g43.ctl  
Ñ
g43.ctl  
Ñ
g29.ctl  
Ñ
l_a25_gnt0_b  
Ñ
12-26  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
815  
816  
817  
818  
819  
820  
821  
822  
823  
824  
825  
826  
827  
828  
829  
830  
831  
832  
833  
834  
835  
836  
837  
838  
839  
840  
841  
842  
843  
844  
845  
846  
847  
848  
849  
850  
851  
852  
853  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
l_a25_gnt0_b  
g31.ctl  
l_a27_pclk  
l_a27_pclk  
g33.ctl  
l_a28_rst_b  
l_a28_rst_b  
g34.ctl  
l_a29_inta_b  
l_a29_inta_b  
g35.ctl  
l_a31  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
g31.ctl  
Ñ
Ñ
g33.ctl  
Ñ
Ñ
g34.ctl  
Ñ
Ñ
g35.ctl  
Ñ
Ñ
l_a31  
g37.ctl  
Ñ
g37.ctl  
pc[0]  
Ñ
pc[0]  
g19.ctl  
Ñ
g19.ctl  
pa[0]  
Ñ
pa[0]  
g18.ctl  
Ñ
g18.ctl  
pd[4]  
Ñ
pd[4]  
g17.ctl  
Ñ
g17.ctl  
pc[1]  
Ñ
pc[1]  
g16.ctl  
Ñ
g16.ctl  
pb[4]  
Ñ
pb[4]  
g15.ctl  
Ñ
g15.ctl  
pa[1]  
Ñ
pa[1]  
g14.ctl  
Ñ
g14.ctl  
pd[5]  
Ñ
pd[5]  
g13.ctl  
Ñ
g13.ctl  
pc[2]  
Ñ
pc[2]  
g12.ctl  
Ñ
g12.ctl  
pb[5]  
Ñ
MOTOROLA  
Chapter 12. IEEE 1149.1Test Access Port  
12-27  
Part III.The Hardware Interface  
Table 12-2. Boundary Scan Bit Definition (Continued)  
Bit  
Cell Type  
Pin/Cell Name  
Pin Type  
Output Control Cell  
854  
855  
856  
857  
858  
859  
860  
861  
862  
863  
864  
865  
866  
867  
868  
869  
870  
871  
872  
873  
874  
875  
876  
877  
878  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
IO.ctl  
i.obs  
o.pin  
pb[5]  
g11.ctl  
pa[2]  
pa[2]  
g10.ctl  
pd[6]  
pd[6]  
g9.ctl  
pc[3]  
pc[3]  
g8.ctl  
pb[6]  
pb[6]  
g7.ctl  
pa[3]  
pa[3]  
g6.ctl  
pd[7]  
pd[7]  
g5.ctl  
pc[4]  
pc[4]  
g4.ctl  
pb[7]  
pb[7]  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
Ñ
io  
io  
g11.ctl  
Ñ
Ñ
g10.ctl  
Ñ
Ñ
g9.ctl  
Ñ
Ñ
g8.ctl  
Ñ
Ñ
g7.ctl  
Ñ
Ñ
g6.ctl  
Ñ
Ñ
g5.ctl  
Ñ
Ñ
g4.ctl  
Ñ
Ñ
g3.ctl  
12.4 Instruction Register  
The MPC8260Õs JTAG implementation includes the public instructions (EXTEST,  
SAMPLE/PRELOAD, and BYPASS) and also supports the CLAMP instruction. One  
additional public instruction (HI-Z) can be used to disable all device output drivers. The  
MPC8260 includes a 4-bit instruction register (no parity) that consists of a shift register  
with four parallel outputs. Data is transferred from the shift register to the parallel outputs  
during the update-IR controller state. The four bits are used to decode the Þve unique  
instructions listed in Table 12-3.  
12-28  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part III.The Hardware Interface  
Table 12-3. Instruction Decoding  
Code  
B7 B6 B5 B4 B3 B2 B1 B0  
0 0 0 0 0 0 0 0  
Instruction  
Description  
EXTEST  
External test. Selects the 475-bit boundary scan register.  
EXTEST also asserts an internal reset for the MPC8260Õs  
system logic to force a known beginning internal state while  
performing external boundary scan operations. By using the  
TAP, the register is capable of scanning user-deÞned values  
into the output buffers, capturing values presented to input pins,  
and controlling the output drive of three-state output or  
bidirectional pins. For more details on the function and use of  
EXTEST, refer to the IEEE 1149.1 standard.  
1
1
0
0
0
0
0
0
SAMPLE/  
Initializes the boundary scan register output cells before the  
PRELOAD selection of EXTEST.This initialization ensures that known data  
appears on the outputs when entering an EXTEST instruction.  
SAMPLE/PRELOAD also provides a chance to obtain a  
snapshot of system data and control signals.  
NOTE: Since there is no internal synchronization between the  
TCK and CLKOUT, the user must provide some form of external  
synchronization between the JTAG operation at TCK frequency  
and the system operation CLKOUT frequency to achieve  
meaningful results.  
1
1
1
1
1
1
1
1
BYPASS  
The BYPASS instruction creates a shift register path from TDI  
to the bypass register and, Þnally, to TDO, circumventing the  
475-bit boundary scan register. This instruction is used to  
enhance test efÞciency when a component other than the  
MPC8260 becomes the device under test. It selects the single-  
bit bypass register as shown below.  
Shift DR  
G1  
0
1
1
D
MUX  
To TDO  
C
From TDI  
Clock DR  
When the bypass register is selected by the current instruction,  
the shift register stage is cleared on the rising edge of TCK in  
the capture-DR controller state. Thus, the Þrst bit to be shifted  
out after selecting the bypass register is always a logic zero.  
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
HIÐZ  
Provided as a manufacturerÕs optional public instruction to avoid  
back driving the output pins during circuit-board testing. When  
HI-Z is invoked all output drivers, including the two-state  
drivers, are turned off (high impedance).The instruction selects  
the bypass register.  
CLAMP  
and  
BYPASS  
CLAMP selects the single-bit bypass register as shown in the  
BYPASS instruction Þgure above, and the state of all signals  
driven from the system output pins is completely deÞned by the  
data previously shifted into the boundary scan register. For  
example, using the SAMPLE/PRELOAD instruction.  
B0 (lsb) is shifted Þrst.  
MOTOROLA  
Chapter 12. IEEE 1149.1Test Access Port  
12-29  
   
Part III.The Hardware Interface  
The parallel output of the instruction register is set to all ones in the test-logic-reset  
controller state. Notice that this preset state is equivalent to the BYPASS instruction.  
During the capture-IR controller state, the parallel inputs to the instruction shift register are  
loaded with the CLAMP command code.  
12.5 MPC8260 Restrictions  
The control afforded by the output enable signals using the boundary-scan register and the  
EXTEST instruction requires a compatible circuit-board test environment to avoid  
device-destructive conÞgurations. The user must avoid situations in which the MPC8260Õs  
output drivers are enabled into actively driven networks.  
12.6 Nonscan Chain Operation  
In nonscan chain operation, the TCK input does not include an internal pull-up resistor and  
should be tied high or low to preclude mid-level inputs.  
To ensure that the scan chain test logic is kept transparent to the system logic, the TAP  
controller is forced into the test-logic-reset state. This is done inside the chip by connecting  
TRST to PORESET  
TMS should remain connected to V or should not change state, so that the TAP controller  
cc  
will not leave the test-logic-reset state.  
12-30  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part IV  
Communications Processor Module  
Intended Audience  
Part IV is intended for system designers who need to implement various communications  
protocols on the MPC8260. It assumes a basic understanding of the PowerPC exception  
model, the MPC8260 interrupt structure, as well as a working knowledge of the  
communications protocols to be used. A complete discussion of these protocols is beyond  
the scope of this book.  
Contents  
Part IV describes behavior of the MPC8260 communications processor module (CPM) and  
the RISC communications processor (CP) that it contains (note that this is separate from  
the embedded PowerPC processor).  
It contains the following chapters:  
¥
¥
Chapter 13, ÒCommunications Processor Module Overview,Ó provides a brief  
overview of the MPC8260 CPM.  
Chapter 14, ÒSerial Interface with Time-Slot Assigner,Ó describes the SIU, which  
controls system start-up, initialization and operation, protection, as well as the  
external system bus.  
¥
¥
Chapter 15, ÒCPM Multiplexing,Ó describes the CPM multiplexing logic (CMX)  
which connects the physical layerÑUTOPIA, MII, modem lines,  
Chapter 16, ÒBaud-Rate Generators (BRGs),Ó describes the eight independent,  
identical baud-rate generators (BRGs) that can be used with the FCCs, SCCs, and  
SMCs.  
¥
¥
Chapter 17, ÒTimers,Ó describes the MPC8260 timer implementation, which can be  
conÞgured as four identical 16-bit or two 32-bit general-purpose timers.  
Chapter 18, ÒSDMA Channels and IDMA Emulation,Ó describes the two physical  
serial DMA (SDMA) channels on the MPC8260.  
MOTOROLA  
Part IV. Communications Processor Module  
Part IV-i  
   
Part IV. Communications Processor Module  
¥
Chapter 19, ÒSerial Communications Controllers (SCCs),Ó describes the four serial  
communications controllers (SCC), which can be conÞgured independently to  
implement different protocols for bridging functions, routers, and gateways, and to  
interface with a wide variety of standard WANs, LANs, and proprietary networks.  
¥
Chapter 20, ÒSCC UART Mode,Ó describes the MPC8260 implementation of  
universal asynchronous receiver transmitter (UART) protocol that is used for  
sending low-speed data between devices.  
¥
¥
¥
Chapter 21, ÒSCC HDLC Mode,Ó describes the MPC8260 implementation of  
HDLC protocol.  
Chapter 22, ÒSCC BISYNC Mode,Ó describes the MPC8260 implementation of  
byte-oriented BISYNC protocol developed by IBM for use in networking products.  
Chapter 23, ÒSCC Transparent Mode,Ó describes the MPC8260 implementation of  
transparent mode (also called totally transparent mode), which provides a clear  
channel on which the SCC can send or receive serial data without bit-level  
manipulation.  
¥
¥
¥
Chapter 24, ÒSCC Ethernet Mode,Ó describes the MPC8260 implementation of  
Ethernet protocol.  
Chapter 25, ÒSCC AppleTalk Mode,Ó describes the MPC8260 implementation of  
AppleTalk.  
Chapter 26, ÒSerial Management Controllers (SMCs),Ó describes two serial  
management controllers, full-duplex ports that can be conÞgured independently to  
support one of three protocolsÑUART, transparent, or general-circuit interface  
(GCI).  
¥
¥
¥
Chapter 27, ÒMulti-Channel Controllers (MCCs),Ó describes the MPC8260Õs multi-  
channel controller (MCC), which handles up to 128 serial, full-duplex data  
channels.  
Chapter 28, ÒFast Communications Controllers (FCCs),Ó describes the MPC8260Õs  
fast communications controllers (FCCs), which are SCCs optimized for  
synchronous high-rate protocols.  
Chapter 29, ÒATM Controller,Ó describes the MPC8260 ATM controller, which  
provides the ATM and AAL layers of the ATM protocol. The ATM controller  
performs segmentation and reassembly (SAR) functions of AAL5, AAL1, and  
AAL0, and most of the common parts convergence sublayer (CP-CS) of these  
protocols.  
¥
¥
¥
Chapter 30, ÒFast Ethernet Controller,Ó describes the MPC8260Õs implementation of  
the Ethernet IEEE 802.3 protocol.  
Chapter 31, ÒFCC HDLC Controller,Ó describes the FCC implementation of the  
HDLC protocol.  
Chapter 32, ÒFCC Transparent Controller,Ó describes the FCC implementation of  
the transparent protocol.  
Part IV-ii  
MOTOROLA  
Part IV. Communications Processor Module  
¥
Chapter 33, ÒSerial Peripheral Interface (SPI),Ó describes the serial peripheral  
interface, which allows the MPC8260 to exchange data between other MPC8260  
chips, the MC68360, the MC68302, the M68HC11, and M68HC05 microcontroller  
families, and peripheral devices such as EEPROMs, real-time clocks, A/D  
converters, and ISDN devices.  
¥
¥
Chapter 34, ÒI2C Controller,Ó describes the MPC8260 implementation of the inter-  
integrated circuit (I2C¨) controller, which allows data to be exchanged with other  
I2C devices, such as microcontrollers, EEPROMs, real-time clock devices, and A/D  
converters.  
Chapter 35, ÒParallel I/O Ports,Ó describes the four general-purpose I/O ports AÐD.  
Each signal in the I/O ports can be conÞgured as a general-purpose I/O signal or as  
a signal dedicated to supporting communications devices, such as SMCs, SCCs.  
MCCs, and FCCs.  
Suggested Reading  
This section lists additional reading that provides background for the information in this  
manual as well as general information about the PowerPC architecture.  
MPC8xx Documentation  
Supporting documentation for the MPC8260 can be accessed through the world-wide web  
at http://www.mot.com/netcomm. This documentation includes technical speciÞcations,  
reference materials, and detailed applications notes.  
PowerPC Documentation  
The PowerPC documentation is organized in the following types of documents:  
¥
Programming environments manualsÑThese books provide information about  
resources deÞned by the PowerPC architecture that are common to PowerPC  
processors. There are two versions, one that describes the functionality of the  
combined 32- and 64-bit architecture models and one that describes only the 32-bit  
model.  
Ñ PowerPC Microprocessor Family: The Programming Environments, Rev 1  
(Motorola order #: MPCFPE/AD)  
Ñ PowerPC Microprocessor Family: The Programming Environments for 32-Bit  
Microprocessors, Rev. 1 (Motorola order #: MPCFPE32B/AD)  
¥
PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors  
(Motorola order #: MPCBUSIF/AD) provides a detailed functional description of  
the 60x bus interface, as implemented on the PowerPC 601ª, 603, and 604 family  
of PowerPC microprocessors. This document is intended to help system and chip set  
developers by providing a centralized reference source to identify the bus interface  
presented by the 60x family of PowerPC microprocessors.  
MOTOROLA  
Part IV. Communications Processor Module  
Part IV-iii  
Part IV. Communications Processor Module  
¥
PowerPC Microprocessor Family: The ProgrammerÕs Reference Guide  
(Motorola order #: MPCPRG/D) is a concise reference that includes the register  
summary, memory control model, exception vectors, and the PowerPC instruction  
set.  
For a current list of PowerPC documentation, refer to the world-wide web at  
http://www.mot.com/PowerPC.  
Conventions  
This document uses the following notational conventions:  
Bold entries in Þgures and tables showing registers and parameter  
RAM should be initialized by the user.  
Bold  
mnemonics  
Instruction mnemonics are shown in lowercase bold.  
italics  
Italics indicate variable command parameters, for example, bcctrx.  
Book titles in text are set in italics.  
0x0  
PreÞx to denote hexadecimal number  
0b0  
PreÞx to denote binary number  
rA, rB  
rD  
Instruction syntax used to identify a source GPR  
Instruction syntax used to identify a destination GPR  
REG[FIELD]  
Abbreviations or acronyms for registers or buffer descriptors are  
shown in uppercase text. SpeciÞc bits, Þelds, or numerical ranges  
appear in brackets. For example, MSR[LE] refers to the little-endian  
mode enable bit in the machine state register.  
x
In certain contexts, such as in a signal encoding or a bit Þeld,  
indicates a donÕt care.  
n
Â
&
|
Indicates an undeÞned numerical value  
NOT logical operator  
AND logical operator  
OR logical operator  
Acronyms and Abbreviations  
Table i contains acronyms and abbreviations used in this document. Note that the meanings  
for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an  
acronym stands may not be intuitively obvious.  
Part IV-iv  
MOTOROLA  
   
Part IV. Communications Processor Module  
Table vii. Acronyms and Abbreviated Terms  
Term  
AAL  
Meaning  
ATM adaptation layer  
Availabe bit rate  
ABR  
ACR  
ALU  
APC  
ATM  
BD  
Allowed cell rate  
Arithmetic logic unit  
ATM pace control  
Asynchronous transfer mode  
Buffer descriptor  
BIST  
BT  
Built-in self test  
Burst tolerance  
CBR  
CEPT  
Constant bit rate  
Conference des administrations Europeanes des Postes et Telecommunications (European  
Conference of Postal and Telecommunications Administrations).  
C/I  
Condition/indication channel used in the GCI protocol  
Cell loss priority  
CLP  
CP  
Communications processor  
CP-CS  
CPM  
Common part convergence sublayer  
Communications processor module  
Cells per slot  
CPS  
CSMA  
CSMA/CD  
DMA  
Carrier sense multiple access  
Carrier sense multiple access with collision detection  
Direct memory access  
DPLL  
DPR  
Digital phase-locked loop  
Dual-port RAM  
DRAM  
DSISR  
EA  
Dynamic random access memory  
Register used for determining the source of a DSI exception  
Effective address  
EEST  
EPROM  
FBP  
Enhanced Ethernet serial transceiver  
Erasable programmable read-only memory  
Free buffer pool  
FIFO  
GCI  
First-in-Þrst-out (buffer)  
General circuit interface  
GCRA  
GPCM  
Generic cell rate algorithm (leaky bucket)  
General-purpose chip-select machine  
MOTOROLA  
Part IV. Communications Processor Module  
Part IV-v  
 
Part IV. Communications Processor Module  
Table vii. Acronyms and Abbreviated Terms (Continued)  
Term  
GUI  
Meaning  
Graphical user interface  
High-level data link control  
Inter-integrated circuit  
Inter-chip digital link  
HDLC  
2
I C  
IDL  
IEEE  
IrDA  
ISDN  
JTAG  
JTAG  
LAN  
LIFO  
LRU  
LSB  
lsb  
Institute of Electrical and Electronics Engineers  
Infrared Data Association  
Integrated services digital network  
Joint Test Action Group  
Joint Test Action Group  
Local area network  
Last-in-Þrst-out  
Least recently used  
Least-signiÞcant byte  
Least-signiÞcant bit  
MAC  
MBS  
MII  
Multiply accumulate or media access control  
Maximum burst size  
Media-independent interface  
Most-signiÞcant byte  
MSB  
msb  
MSR  
NaN  
NIC  
Most-signiÞcant bit  
Machine state register  
Not a number  
Network interface card  
Network interface unit  
Nonmultiplexed serial interface  
Non-real time  
NIU  
NMSI  
NRT  
OSI  
Open systems interconnection  
Peripheral component interconnect  
Protocol data unit  
PCI  
PDU  
PCR  
PHY  
PPM  
RM  
Peak cell rate  
Physical layer  
Pulse-position modulation  
Resource management  
Part IV-vi  
MOTOROLA  
Part IV. Communications Processor Module  
Table vii. Acronyms and Abbreviated Terms (Continued)  
Term  
Meaning  
RT  
Real-time  
RTOS  
Rx  
Real-time operating system  
Receive  
SAR  
SCC  
SCP  
SCR  
SDLC  
SDMA  
SI  
Segmentation and reassembly  
Serial communications controller  
Serial control port  
Sustained cell rate  
Synchronous Data Link Control  
Serial DMA  
Serial interface  
SIU  
System interface unit  
SMC  
SNA  
SPI  
Serial management controller  
Systems network architecture  
Serial peripheral interface  
Static random access memory  
Synchronous residual time stamp  
Time-division multiplexed  
Terminal endpoint of an ISDN connection  
Translation lookaside buffer  
Time-slot assigner  
SRAM  
SRTS  
TDM  
TE  
TLB  
TSA  
Tx  
Transmit  
UBR  
UBR+  
UART  
UPM  
USART  
WAN  
UnspeciÞed bit rate  
UnspeciÞed bit rate with minimum cell rate guarantee  
Universal asynchronous receiver/transmitter  
User-programmable machine  
Universal synchronous/asynchronous receiver/transmitter  
Wide area network  
MOTOROLA  
Part IV. Communications Processor Module  
Part IV-vii  
Part IV. Communications Processor Module  
Part IV-viii  
MOTOROLA  
Chapter 13  
Communications Processor Module  
Overview  
130  
1T30 he MPC8260Õs communications processor module (CPM) is a superset of the MPC860  
PowerQUICC CPM, with enhancements in performance and the addition of hardware and  
microcode routines for supporting high bit-rate protocols like ATM and Fast Ethernet. The  
support for multiple HDLC channels is enhanced to support up to 256 HDLC channels.  
13.1 Features  
The CPM includes various blocks to provide the system with an efÞcient way to handle data  
communication tasks. The following is a list of the CPMÕs important features.  
¥
Communications processor (CP)  
Ñ One instruction per clock  
Ñ Executes code from internal ROM or dual-port RAM  
Ñ 32-bit RISC architecture  
Ñ Tuned for communication environments: instruction set supports CRC  
computation and bit manipulation.  
Ñ Internal timer  
Ñ Interfaces with the PowerPCª embedded core processor through a 24-Kbyte  
dual-port RAM and virtual DMA channels for each peripheral controller  
Ñ Handles serial protocols and virtual DMA.  
¥
¥
Three full-duplex fast serial communications controllers (FCCs) support the  
following protocols:  
Ñ ATM protocol through UTOPIA interface (FCC1 and FCC2 only)  
Ñ IEEE802.3/Fast Ethernet  
Ñ HDLC  
Ñ Totally transparent operation  
Two multi-channel controllers (MCCs) that together can handle up to 256 HDLC/  
transparent channels at 64 Kbps each, multiplexed on up to eight TDM interfaces  
MOTOROLA  
Chapter 13. Communications Processor Module Overview  
13-1  
       
Part IV. Communications Processor Module  
¥
Four full-duplex serial communications controllers (SCCs) support the following  
protocols:  
Ñ IEEE802.3/Ethernet  
Ñ High level/synchronous data link control (HDLC/SDLC)  
Ñ LocalTalk (HDLC-based local area network protocol)  
Ñ Universal asynchronous receiver transmitter (UART)  
Ñ Synchronous UART (1x clock mode)  
Ñ Binary synchronous communication (BISYNC)  
Ñ Totally transparent operation  
¥
¥
Two full-duplex serial management controllers (SMCs) support the following  
protocols:  
Ñ GCI (ISDN interface) monitor and C/I channels  
Ñ UART  
Ñ Transparent operation  
Serial peripheral interface (SPI) support for master or slave  
2
¥
¥
I C bus controller  
Time-slot assigner supports multiplexing of data from any of the SCCs, FCCs,  
SMCs, and MCCs onto eight time-division multiplexed (TDM) interfaces. The time-  
slot assigner supports the following TDM formats:  
Ñ T1/CEPT lines  
Ñ T3/E3  
Ñ Pulse code modulation (PCM) highway interface  
Ñ ISDN primary rate  
Ñ Motorola interchip digital link (IDL)  
Ñ General circuit interface (GCI)  
Ñ User-deÞned interfaces  
¥
¥
¥
Eight independent baud rate generators (BRGs)  
Four general-purpose 16-bit timers or two 32-bit timers  
General-purpose parallel portsÑsixteen parallel I/O lines with interrupt capability  
Figure 13-1 shows the MPC8260Õs CPM block diagram.  
13-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part IV. Communications Processor Module  
Local Bus  
60x Bus  
To SIU  
Interrupt  
Controller  
Bus Interface  
SDMA  
Internal Bus  
4 Timers  
Communications Processor  
ROM  
Dual-Port  
RAM  
Parallel I/O Ports  
Baud Rate Generators  
Peripheral Bus  
2
2 MCCs  
3 FCCs  
4 SCCs  
2 SMCs  
SPI  
I C  
Serial Interface (SI) and Time-Slot Assigner (TSA)  
Figure 13-1. MPC8260 CPM Block Diagram  
13.2 MPC8260 Serial ConÞgurations  
The MPC8260 offers a ßexible set of communications capabilities. A subset of the possible  
conÞgurations using an MPC8260 is shown in Table 13-1.  
Table 13-1. Possible MPC8260 Applications  
Application  
MCC1 MCC2  
FCC1  
FCC2 FCC3 SCC1 SCC2 SCC3 SCC4 SMC1 SMC2  
ISDN router  
ATM switch  
ATM access  
4 E1  
4 E1  
FEnet or ATM FEnet  
UART UART UART UART  
UART  
ATM  
ATM  
FEnet  
FEnet FEnet  
E3 or  
E1Õs  
E3 or ATM  
E1Õs  
UART  
GSM mobile  
switching center  
E1Õs  
FEnet or ATM 10 M  
Backbone  
10 M  
HDLC HDLC  
MOTOROLA  
Chapter 13. Communications Processor Module Overview  
13-3  
         
Part IV. Communications Processor Module  
13.3 Communications Processor (CP)  
The communications processor (CP), also called the RISC microcontroller, is a 32-bit  
controller for the CPM that resides on a separate bus from the core and, therefore, can  
perform tasks independent of the PowerPC core. The CP handles lower-layer  
communications tasks and DMA control, freeing the core to handle higher-layer activities.  
The CP works with the peripheral controllers and parallel port to implement  
user-programmable protocols and manage the serial DMA (SDMA) channels that transfer  
data between the I/O channels and memory. It also manages the IDMA (independent DMA)  
channels and contains an internal timer used to implement up to 16 additional software  
timers.  
The CPÕs architecture and instruction set are optimized for data communications and data  
processing required by many wire-line and wireless communications standards.  
13.3.1 Features  
The following is a list of the CPÕs important features.  
¥
¥
¥
¥
¥
¥
¥
One system clock cycle per instruction  
32-bit instruction object code  
Executes code from internal ROM or RAM  
32-bit ALU data path  
64-bit dual-port RAM access  
Optimized for communications processing  
Performs DMA bursting of serial data from/to dual-port RAM to/from external  
memory  
13.3.2 CP Block Diagram  
The CP contains the following functional units:  
¥
¥
¥
¥
¥
¥
¥
Scheduler and sequencer  
Instruction decoder  
Execution unit  
Load/store unit (LSU)  
Block transfer unit (BTM)Ñmoves data between serial FIFO and RAM  
Eight general purpose registers (GPRs)  
Special registers, CRC machine, HDLC framer  
The CP also gives SDMA commands to the SDMA. The CP interfaces with the dual-port  
RAM for loading and storing data and for fetching instructions while running microcode  
from dual-port RAM.  
13-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part IV. Communications Processor Module  
Figure 13-2 shows the CP block diagram.  
Communications Processor (CP)  
Timer  
Data  
General-  
Special  
Registers  
Execution  
Purpose  
Unit  
Registers  
Source Buses  
Destination Bus  
Block Transfer  
Data  
Load/Store  
Unit  
Module  
(BTM)  
Instruction  
Scheduler  
Sequencer  
Decoder  
To all units  
Microcode  
ROM  
Address  
Data  
Dual-Port RAM  
DMA  
Address  
Data  
Bus  
Interface  
60x Bus  
Local Bus  
Figure 13-2. Communications Processor (CP) Block Diagram  
MOTOROLA  
Chapter 13. Communications Processor Module Overview  
13-5  
   
Part IV. Communications Processor Module  
13.3.3 PowerPC Core Interface  
The CP communicates with the PowerPC core in several ways:  
¥
¥
Many parameters are exchanged through the dual-port RAM.  
The CP can execute special commands issued by the core. These commands should  
only be issued in special situations like exceptions or error recovery.  
¥
¥
The CP generates interrupts through the SIU interrupt controller.  
The PowerPC core can read the CPM status/event registers at any time.  
13.3.4 Peripheral Interface  
The CP uses the peripheral bus to communicate with all of its peripherals. Each FCC and  
each SCC has a separate receive and transmit FIFOs. The FCC FIFOs are 192 bytes. The  
SCC FIFOs are 32 bytes. The SMCs, SPI, and I2C are all double-buffered, creating effective  
FIFO sizes of two characters.  
Table 13-2 shows the order in which the CP handles requests from peripherals from highest  
to lowest priority.  
Table 13-2. Peripheral Prioritization  
Priority  
Request  
Reset in the CPCR or SRESET  
1
2
SDMA bus error  
3
Commands issued to the CPCR  
Emergency (from FCCs, MCCs, and SCCs)  
4
1
5
IDMA[1Ð4] emulation (defaultÑoption 1)  
6
FCC1 receive  
FCC1 transmit  
MCC1 receive  
MCC2 receive  
MCC1 transmit  
MCC2 transmit  
FCC2 receive  
FCC2 transmit  
FCC3 receive  
FCC3 transmit  
SCC1 receive  
SCC1 transmit  
SCC2 receive  
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
13-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part IV. Communications Processor Module  
Table 13-2. Peripheral Prioritization (Continued)  
Priority  
Request  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
SCC2 transmit  
SCC3 receive  
SCC3 transmit  
SCC4 receive  
SCC4 transmit  
1
IDMA[1Ð4] emulation (option 2)  
SMC1 receive  
SMC1 transmit  
SMC2 receive  
SMC2 transmit  
SPI receive  
SPI transmit  
2
I C receive  
2
I C transmit  
RISC timer table  
1
IDMA[1Ð4] emulation (option 3)  
1
The priority of each IDMA channel is programmed independently. See the  
RCCR[DRxQP] description in Section 13.3.6, ÒRISC Controller ConÞguration  
Register (RCCR).Ó  
13.3.5 Execution from RAM  
The CP has an option to execute microcode from a portion of user RAM located in the dual-  
port RAM. In this mode, the CP fetches instructions from both the dual-port RAM and its  
own private ROM. This mode allows Motorola to add new protocols or enhancements to  
the MPC8260 in the form of RAM microcode packages. If preferred, the user can obtain  
binary microcode from Motorola and load it into the dual-port RAM.  
13.3.6 RISC Controller ConÞguration Register (RCCR)  
The RISC controller conÞguration register (RCCR) conÞgures the CP to run microcode  
from ROM or RAM and controls the CPÕs internal timer.  
MOTOROLA  
Chapter 13. Communications Processor Module Overview  
13-7  
         
Part IV. Communications Processor Module  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field TIME  
Reset  
Ñ
TIMEP  
DR1M DR2M DR1QP  
EIE  
SCD  
DR2QP  
0000_0000_0000_0000  
R/W  
R/W  
Addr  
0x119C4  
Bits  
Field  
Reset  
R/W  
16  
17  
18  
19  
Ñ
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
ERAM  
EDM1 EDM2 EDM3 EDM4 DR3M DR4M DR3QP DEM12 DEM34 DR4QP  
0000_0000_0000_0000  
R/W  
Addr  
0X119C6  
Figure 13-3. RISC Controller Configuration Register (RCCR)  
RCCR bit Þelds are described in Table 13-3.  
Table 13-3. RISC Controller Configuration Register Field Descriptions  
Bits  
Name  
Description  
0
1
TIME  
Timer enable. Enables the CP internal timer that generates a tick to the CP based on the value  
programmed into the TIMEP Þeld.TIME can be modiÞed at any time to start or stop the scanning of  
the RISC timer tables.  
Ñ
Reserved  
2Ð7  
TIMEP Timer period controls the CP timer tick. The RISC timer tables are scanned on each timer tick and  
the input to the timer tick generator is the general system clock (133/166MHZ) divided by 1,024.  
The formula is (TIMEP + 1) ´ 1,024 = (general system clock period). Thus, a value of 0 stored in  
these bits gives a timer tick of 1 ´ (1,024) = 1,024 general system clocks and a value of 63  
(decimal) gives a timer tick of 64 ´ (1,024) = 65,536 general system clocks.  
8, 9,  
24, 25  
DRxM  
IDMAx request mode. Controls the IDMA request x (DREQx) sensitivity mode. DREQx is used to  
activate IDMA channel x. See Section 18.7, ÒIDMA Interface Signals.Ó  
0 DREQx is edge sensitive (according to EDMx).  
1 DREQx is level sensitive.  
10Ð11, DRxQP IDMAx request priority. Controls the priority of DREQx relative to the communications controllers.  
14Ð15,  
26Ð27,  
30Ð31  
See Section 18.7, ÒIDMA Interface Signals.Ó  
00 DREQx has more priority than the communications controllers (default).  
01 DREQx has less priority than the communications controllers (option 2).  
10 DREQx has the lowest priority (option 3).  
11 Reserved  
12  
13  
EIE  
External interrupt enable. When EIE is set, DREQ1 acts as an external interrupt to the CP.  
ConÞgure as instructed in the download process of a Motorola-supplied RAM microcode package.  
0 DREQ1 cannot interrupt the CP.  
1 DREQ1 will interrupt the CP.  
SCD  
Scheduler conÞguration. ConÞgure as instructed in the download process of a Motorola-supplied  
RAM microcode package.  
0 Normal operation.  
1 Alternate conÞguration of the scheduler.  
13-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
Table 13-3. RISC Controller Configuration Register Field Descriptions (Continued)  
Bits  
Name  
Description  
16Ð18 ERAM Enable RAM microcode. ConÞgure as instructed in the download process of a Motorola-supplied  
RAM microcode package.  
000 Disable microcode program execution from the dual-port RAM.  
001 Microcode uses the Þrst 2 Kbytes of the dual-port RAM.  
010 Microcode uses the Þrst 4 Kbytes of the dual-port RAM.  
011 Microcode uses the Þrst 6 Kbytes of the dual-port RAM.  
100 Microcode uses the Þrst 8 Kbytes of the dual-port RAM.  
101 Microcode uses the Þrst 10 Kbytes of the dual-port RAM.  
110 Microcode uses the Þrst 12 Kbytes of the dual-port RAM.  
111 Reserved  
19  
Ñ
Reserved  
20, 21, EDMx  
22, 23  
Edge detect mode. DREQx asserts as follows:  
0 Low-to-high change  
1 High-to-low change  
28  
29  
DEM12 Edge detect mode for DONE[1, 2] for IDMA[1, 2]. See Section 18.7.2, ÒDONEx.Ó DONE[1, 2]  
asserts as follows:  
0 High-to-low change  
1 Low-to-high change  
DEM34 Edge detect mode for DONE[3, 4] for IDMA[3, 4]. See Section 18.7.2, ÒDONEx.Ó DONE[3, 4]  
asserts as follows:  
0 High-to-low change  
1 Low-to-high change  
13.3.7 RISC Time-Stamp Control Register (RTSCR)  
The RISC time-stamp control register (RTSCR), shown in Figure 13-4, conÞgures the  
RISC time-stamp timer (RTSR). The time-stamp timer is used by the ATM and the HDLC  
controllers. For application examples, see Section 29.5.3, ÒABR Flow Control Setup,Ó and  
Section 31.6, ÒHDLC Mode Register (FPSMR).Ó  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Ñ
RTE  
RTPS (Timer Prescale)  
0000_0000_0000_0000  
R/W  
Addr  
0x119DC  
Figure 13-4. RISC Time-Stamp Control Register (RTSCR)  
MOTOROLA  
Chapter 13. Communications Processor Module Overview  
13-9  
     
Part IV. Communications Processor Module  
Table 13-4 describes RTSCR Þelds.  
Table 13-4. RTSCR Field Descriptions  
Bits  
0Ð4  
Name  
Description  
Ñ
Reserved  
5
RTE  
Time stamp enable.  
0 Disable time-stamp timer.  
1 Enable time-stamp timer.  
6Ð15 RTPS  
Time-stamp timer pre-scale. Must be programmed to generate a 1-µs period input clock to the  
time-stamp timer. (Time-stamp frequency = (CPM frequency)/(RTPS+2)  
13.3.8 RISC Time-Stamp Register (RTSR)  
The RISC time-stamp register (RTSR), shown in Figure 13-5, contains the time stamp.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Time Stamp  
Ñ
R
Addr  
Bits  
0x119E0  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
Time Stamp  
Ñ
R
Addr  
0X119E2  
Figure 13-5. RISC Time-Stamp Register (RTSR)  
After reset, setting RTSCR[RTE] causes the time stamp to start counting microseconds  
from zero.  
13.3.9 RISC Microcode Revision Number  
The CP writes a revision number stored in its ROM to an dual-port RAM location called  
REV_NUM that resides in the miscellaneous parameter RAM. The other locations are  
reserved for future use.  
Table 13-5. RISC Microcode Revision Number  
Address  
Name  
Width  
Hword  
Hword  
Description  
Microcode revision number  
Reserved  
RAM Base + 0x8AF0  
RAM Base + 0x8AF2  
REV_NUM  
Ñ
13-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
               
Part IV. Communications Processor Module  
13.4 Command Set  
The core issues commands to the CP by writing to the CP command register (CPCR). The  
CPCR rarely needs to be accessed. For example, to terminate the transmission of an SCCÕs  
frame without waiting until the end, a STOP TX command must be issued through the CP  
command register (CPCR).  
13.4.1 CP Command Register (CPCR)  
The core should set CPCR[FLG], shown in Figure 13-6, when it issues a command and the  
CP clears FLG after completing the command, thus indicating to the core that it is ready for  
the next command. Subsequent commands to the CPCR can be given only after FLG is  
clear. However, the software reset command issued by setting RST does not depend on the  
state of FLG, but the core should still set FLG when setting RST.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
RST  
PAGE  
Sub-block code (SBC)  
Ñ
FLG  
0000_0000_0000_0000  
R/W  
Addr  
Bits  
0x119CE  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
Ñ
MCC channel number (MCN)  
Ñ
OPCODE  
0000_0000_0000_0000  
R/W  
Addr  
0x119D0  
Figure 13-6. CP Command Register (CPCR)  
Table 13-6 describes CPCR Þelds.  
Table 13-6. CP Command Register Field Descriptions  
Bit  
Name  
Description  
0
RST  
Software reset command. Set by the core and cleared by the CP. When this command is  
executed, RST and FLG bit are cleared within two general system clocks. The CPM reset routine  
is approximately 60 clocks long, but the user can begin initialization of the CPM immediately after  
this command is issued.  
RST is useful when the core wants to reset the registers and parameters for all the channels  
2
(FCCs, SCCs, SMCs, SPI, I C, MCC) as well as the CP and RISC timer tables. However, this  
command does not affect the serial interface (SIx) or parallel I/O registers.  
1Ð5  
PAGE  
Indicates the parameter RAM page number associated with the sub-block being served. See the  
SBC description for page numbers.  
MOTOROLA  
Chapter 13. Communications Processor Module Overview  
13-11  
               
Part IV. Communications Processor Module  
Table 13-6. CP Command Register Field Descriptions (Continued)  
Bit  
Name  
Description  
6Ð10 SBC  
Sub-block code. Set by the core to specify the sub-block on which the command is to operate.  
Sub-block  
Code  
Page  
Sub-block  
Code  
Page  
FCC1  
10000  
(for ATM: 01110)  
00100  
SPI  
01010  
01001  
2
FCC2  
10001  
(for ATM: 01110)  
00101  
I C  
01011  
01010  
FCC3  
SCC1  
SCC2  
SCC3  
SCC4  
SMC1  
SMC2  
RAND  
10010  
00100  
00101  
00110  
00111  
01000  
01001  
01110  
00110  
00000  
00001  
00010  
00011  
00111  
01000  
01010  
Timer  
01111  
11100  
11101  
10100  
10101  
10110  
10111  
01010  
00111  
01000  
00111  
01000  
01001  
01010  
MCC1  
MCC2  
IDMA1  
IDMA2  
IDMA3  
IDMA4  
11Ð14  
15  
Ñ
Reserved  
FLG  
Command semaphore ßag. Set by the core and cleared by the CP.  
0 The CP is ready to receive a new command.  
1 The CPCR contains a command that the CP is currently processing. The CP clears this bit at  
the end of command execution or after reset.  
16Ð17  
Ñ
Reserved  
18Ð25 MCN  
MCC channel number. SpeciÞes the channel number in the case of an MCC command.  
In FCC protocols, this Þeld contains the protocol code as follows:  
0x00 HDLC  
0x0A ATM  
0x0C Ethernet  
0x0F Transparent  
26-27  
Ñ
Reserved  
28Ð31 OPCODE Operation code. Settings are listed in Table 13-7 below.  
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Part IV. Communications Processor Module  
13.4.1.1 CP Commands  
The CP command opcodes are shown in Table 13-7.  
Table 13-7. CP Command Opcodes  
Channel  
SPI  
Opcode  
SMC (UART/  
Transparent)  
SMC  
(GCI)  
2
FCC  
SCC  
I C  
IDMA  
MCC  
Timer Special  
0000  
INIT RX AND INIT RX AND  
INIT RX AND  
TX PARAMS  
INIT RX  
AND TX  
PARAMS  
INIT RX  
AND TX  
PARAMS  
INIT RX  
AND TX  
PARAMS  
Ñ
INIT RX  
AND TX  
PARAMS  
Ñ
Ñ
TX PARAMS  
TX PARAMS  
0001  
0010  
0011  
0100  
0101  
INIT RX  
INIT RX  
INIT RX  
Ñ
Ñ
Ñ
Ñ
Ñ
INIT RX  
INIT RX  
Ñ
Ñ
Ñ
Ñ
Ñ
INIT RX  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
PARAMS  
PARAMS  
PARAMS  
PARAMS  
PARAMS  
PARAMS  
INIT TX  
INIT TX  
INIT TX  
INIT TX  
INIT TX  
INIT TX  
PARAMS  
PARAMS  
PARAMS  
PARAMS  
PARAMS  
PARAMS  
ENTER HUNT  
MODE  
ENTER  
ENTER HUNT  
MODE  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
HUNT MODE  
STOP TX  
STOP TX  
STOP TX  
Ñ
MCC  
STOP TX  
GRACEFUL  
STOP TX  
GRACEFUL  
STOP TX  
Ñ
0110  
0111  
RESTART TX RESTART TX RESTART TX  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
CLOSE  
RX BD  
CLOSE  
RX BD  
CLOSE  
RX BD  
CLOSE  
RX BD  
CLOSE  
RX BD  
1000  
1001  
1010  
SET GROUP SET GROUP  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
SET  
Ñ
Ñ
Ñ
ADDRESS  
ADDRESS  
TIMER  
Ñ
Ñ
GCI  
START  
IDMA  
MCC  
Ñ
Ñ
TIMEOUT  
STOP RX  
ATM  
RESET BCS  
GCI ABORT  
REQUEST  
Ñ
Ñ
TRANSMIT  
COMMAND  
1011  
1100  
11XX  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
STOP  
IDMA  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
RANDOM  
NUMBER  
UndeÞned. Reserved for use by Motorola-supplied RAM microcodes.  
MOTOROLA  
Chapter 13. Communications Processor Module Overview  
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Part IV. Communications Processor Module  
The commands in Table 13-7 are described in Table 13-8.  
Table 13-8. Command Descriptions  
Command  
Description  
INIT TX AND RX Initialize transmit and receive parameters. Initializes the transmit and receive parameters in the  
PARAMS  
parameter RAM to the values that they had after the last reset of the CP. This command is especially  
useful when switching protocols on a given peripheral controller.  
INIT RX  
Initialize receive parameters. Initializes the receive parameters of the peripheral controller. Note that for  
the MCCs, issuing this command initializes only 32 channels at a time; see Section 27.9, ÒMCC  
Commands.Ó  
PARAMS  
INIT TX  
Initialize transmit parameters. Initializes the transmit parameters of the peripheral controller. Note that  
for the MCCs, issuing this command initializes only 32 channels at a time; see Section 27.9, ÒMCC  
Commands.Ó  
PARAMS  
ENTER HUNT  
MODE  
Enter hunt mode. Causes the receiver to stop receiving and begin looking for a new frame. The exact  
operation of this command may vary depending on the protocol used.  
STOP TX  
Stop transmission. Aborts the transmission from this channel as soon as the transmit FIFO has been  
emptied. It should be used in cases where transmission needs to be stopped as quickly as possible.  
Transmission proceeds when the RESTART command is issued.  
GRACEFUL  
STOP TX  
Graceful stop transmission. Stops the transmission from this channel as soon as the current frame has  
been fully transmitted from the transmit FIFO.Transmission proceeds when the RESTART command is  
issued and the R-bit is set in the next TxBD.  
RESTART TX  
CLOSE RXBD  
Restart transmission. Once the STOP TX command has been issued, this command is used to restart  
transmission at the current BD.  
Close RxBD. Causes the receiver to close the current RxBD, making the receive buffer immediately  
available for manipulation by the user. Reception continues using the next available BD. Can be used to  
access the buffer without waiting until the buffer is completely Þlled by the SCC.  
START IDMA  
STOP IDMA  
SET TIMER  
See Section 18.9, ÒIDMA Commands.Ó  
See Section 18.9, ÒIDMA Commands.Ó  
Set timer. Activates, deactivates, or reconÞgures one of the 16 timers in the RISC timer table.  
SET GROUP  
ADDRESS  
Set group address. Sets a bit in the hash table for the Ethernet logical group address recognition  
function.  
GCI ABORT  
REQUEST  
GCI abort request. The GCI receiver sends an abort request on the E-bit.  
GCI TIMEOUT  
RESET BCS  
GCI time-out. The GCI performs the timeout function.  
Reset block check sequence. Used in BISYNC mode to reset the block check sequence calculation.  
See Section 27.9, ÒMCC Commands.Ó  
MCC STOP  
TRANSMIT  
MCC STOP  
RECEIVE  
See Section 27.9, ÒMCC Commands.Ó  
ATM TRANSMIT See Section 29.14, ÒATM Transmit Command.Ó  
RANDOM  
NUMBER  
Generate a random number and put it in dual-port RAM; see RAND in Table 13-10.  
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Part IV. Communications Processor Module  
13.4.2 Command Register Example  
To perform a complete reset of the CP, the value 0x8001_0000 should be written to the  
CPCR. Following this command, the CPCR returns the value 0x0000_0000 after two  
clocks.  
13.4.3 Command Execution Latency  
The worst-case command execution latency is 200 clocks and the typical command  
execution latency is about 40 clocks.  
13.5 Dual-Port RAM  
The CPM has 24 Kbytes of static RAM. Figure 13-7 is a block diagram of the dual-port  
RAM.  
Slave Address  
CP Instruction Address  
CP Data Address  
Slave Data  
Dual-Port RAM  
CP Instruction  
CP Data  
24 KBytes  
DMA (60x) Address  
DMA (Local) Address  
BTM Address  
DMA (60x) Data  
DMA (Local) Data  
BTM Data  
(BDs, Buffers  
and Microcode)  
Figure 13-7. Dual-Port RAM Block Diagram  
The dual-port RAM can be accessed by the following:  
¥
¥
¥
¥
¥
¥
CP load/store unit  
CP block transfer module (BTM)  
CP instruction fetcher (when executing microcode from RAM)  
PowerPCª 60x slave  
SDMA 60x bus  
SDMA local bus  
Figure 13-8 shows the memory map of the dual-port RAM.  
MOTOROLA  
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Part IV. Communications Processor Module  
0x0000  
0x0800  
0x1000  
0x1800  
0x2000  
0x2800  
0x3000  
0x3800  
0x4000  
0x8000  
0x8800  
0x9000  
Bank #1  
BD/Data/µCode  
2 KBytes  
Bank #9  
Parameter RAM  
2 KBytes  
Bank #10  
Parameter RAM  
2 KBytes  
Bank #2  
BD/Data/µCode  
2 KBytes  
(Partially Reserved)  
Bank #3  
BD/Data/µCode  
2 KBytes  
Bank #4  
BD/Data/µCode  
2 KBytes  
Reserved  
Reserved  
Bank #5  
BD/Data/µCode  
2 KBytes  
Bank #6  
BD/Data/µCode  
2 KBytes  
0xB000  
0xB800  
Bank #7  
BD/Data  
2 KBytes  
Bank #11  
FCC Data  
2 KBytes  
Bank #8  
BD/Data  
2 KBytes  
Bank #12  
FCC Data  
2 KBytes  
Figure 13-8. Dual-Port RAM Memory Map  
The dual-port RAM data bus is 64-bits wide. The RAM is used for six possible tasks:  
¥
To store parameters associated with the FCCs, SCCs, MCCs, SMCs, SPI, I2C, and  
IDMAs in the parameter RAM.  
¥
¥
¥
To store buffer descriptors (BDs).  
To hold data buffers (optional because data can also be stored in external memory).  
For temporary storage of FCC data moving to/from an FCC FIFO (using the BTM)  
from/to external memory (using SDMA).  
¥
¥
To store RAM microcode for the CP. This feature allows Motorola to add protocols  
in the future.  
For additional scratch-pad RAM space for user software.  
The RAM is designed to serve multiple requests at the same cycle, as long as they are not  
in the same bank.  
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Only the parameters in the parameter RAM and the microcode RAM option require Þxed  
addresses to be used. The BDs, buffer data, and scratchpad RAM can be located in the dual-  
port system RAM or in any unused parameter RAM, such as, in the area made available  
when a peripheral controller or sub-block is not being used.  
Microcode can be executed from the Þrst 12 Kbytes. To ensure an uninterrupted instruction  
stream (one per cycle), no other agent is allowed to use a RAM bank used by the microcode.  
Since the Þrst 12 Kbytes are divided to six 2-Kbyte banks, RAM microcode occupies 2, 4,  
6, 8, 10, or 12 Kbytes of RAM, depending on RCCR[ERAM]; see Section 13.3.6, ÒRISC  
Controller ConÞguration Register (RCCR).Ó  
13.5.1 Buffer Descriptors (BDs)  
The peripheral controllers (FCCs, SCCs, SMCs, MCCs, SPI, and I2C) always use BDs for  
controlling buffers and their BD formats are all the same, as shown in Table 13-9.  
Table 13-9. Buffer Descriptor Format  
Address  
Descriptor  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
Status and control  
Data length  
High-order buffer pointer  
Low-order buffer pointer  
If the IDMA is used in the buffer chaining or auto-buffer mode, the IDMA channel also uses  
BDs. They are described in Section 18.3, ÒIDMA Emulation.Ó  
13.5.2 Parameter RAM  
The CPM maintains a section of RAM called the parameter RAM, which contains many  
parameters for the operation of the FCCs, SCCs, SMCs, SPI, I2C, and IDMA channels. An  
overview of the parameter RAM structure is shown in Table 13-10.  
The exact deÞnition of the parameter RAM is contained in each protocol subsection  
describing a device that uses a parameter RAM. For example, the Ethernet parameter RAM  
is deÞned differently in some locations from the HDLC-speciÞc parameter RAM.  
MOTOROLA  
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Part IV. Communications Processor Module  
Table 13-10. Parameter RAM  
1
Page  
Address  
Peripheral  
SCC1  
Size (Bytes)  
256  
1
2
3
4
5
6
7
8
0x8000  
0x8100  
0x8200  
0x8300  
0x8400  
0x8500  
0x8600  
0x8700  
0x8780  
SCC2  
256  
256  
256  
256  
256  
256  
128  
124  
2
SCC3  
SCC4  
FCC1  
FCC2  
FCC3  
MCC1  
Reserved  
SMC1_BASE  
IDMA1_BASE  
MCC2  
0x87FC  
0x87FE  
0x8800  
0x8880  
0x88FC  
0x88FE  
0x8900  
0x89FC  
0x89FE  
0x8A00  
0x8AE0  
0x8AF0  
0x8AF2  
0x8AF4  
0x8AF8  
0x8AFC  
0x8AFE  
0x8B00  
2
9
128  
124  
2
Reserved  
SMC2_BASE  
IDMA2_BASE  
Reserved  
SPI_BASE  
IDMA3_BASE  
Reserved  
RISC Timers  
REV_NUM  
Reserved  
Reserved  
RAND  
2
10  
11  
252  
2
2
224  
16  
2
2
4
4
2
I C_BASE  
2
IDMA4_BASE  
Reserved  
2
12-16  
1280  
1
Offset from RAM_BASE  
13.6 RISC Timer Tables  
The CP can control up to 16 software timers that are separate from the four general-purpose  
timers and the BRGs in the CPM. These timers are best used in protocols that do not require  
extreme precision, but in which it is preferable to free the core from scanning the softwareÕs  
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Part IV. Communications Processor Module  
timer tables. These timers are clocked from an internal timer that only the CP uses. The  
following is a list of the RISC timer tables important features.  
¥
¥
¥
¥
¥
¥
Supports up to 16 timers.  
Two timer modes: one-shot and restart.  
Maskable interrupt on timer expiration.  
Programmable timer resolution as Þne as 7.7µs at 133 MHz (6.17 µs at 166 MHz).  
Maximum timeout period of 31.8 seconds at 133 MHz (25.5 seconds at 166 MHz).  
Continuously updated reference counter.  
All operations on the RISC timer tables are based on a fundamental tick of the CPÕs internal  
timer that is programmed in the RCCR. The tick is a multiple of 1,024 general system  
clocks; see Section 13.3.6, ÒRISC Controller ConÞguration Register (RCCR).Ó  
The RISC timer tables have the lowest priority of all CP operations. Therefore, if the CP is  
so busy with other tasks that it does not have time to service the timer during a tick interval,  
one or more timer may not be updated accurately. This behavior can be used to estimate the  
worst-case loading of the CP; see Section 13.6.10, ÒUsing the RISC Timers to Track CP  
Loading.Ó  
The timer table is conÞgured using the RCCR, the timer table parameter RAM, and the  
RISC controller timer event/mask registers (RTER/RTMR), and by issuing SET TIMER to  
the CPCR.  
13.6.1 RISC Timer Table Parameter RAM  
Two areas of dual-port RAM, shown in Figure 13-9, are used for the RISC timer tables:  
¥
¥
The RISC timer table parameter RAM  
The RISC timer table entries  
16 RISC  
Timer Table  
Entries  
(Up to 64 Bytes)  
Timer Table Base Pointer  
0x8AE0  
TM_BASE  
RISC  
Timer Table  
Parameter RAM  
Figure 13-9. RISC Timer Table RAM Usage  
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Part IV. Communications Processor Module  
The RISC timer table parameter RAM area begins at the RISC timer base address and is  
used for the general timer parameters; see Table 13-11.  
Table 13-11. RISC Timer Table Parameter RAM  
1
Offset  
Name  
Description  
0x00  
TM_BASE RISC timer table base address. The actual timers are a small block of memory in the dual-port  
RAM.TM_BASE is the offset from the beginning of the dual-port RAM where that block resides.  
Four bytes must be reserved at the TM_BASE for each timer used, (64 bytes if all 16 timers are  
used). If fewer than 16 timers are used, timers should be allocated in ascending order to save  
space. For example, only 8 bytes are required if two timers are needed and RISC timers 0 and 1  
are enabled. TM_BASE should be word-aligned.  
0x02  
0x04  
TM_PTR RISC timer table pointer. This value is used exclusively by the CP to point to the next timer  
accessed in the timer table. It should not be modiÞed by the user.  
R_TMR RISC timer mode register. This value is used exclusively by the CP to store the mode of the  
timerÑone-shot (bit is 0) or restart (bit is 1). R_TMR should not be modiÞed by the user. The  
SET TIMER command should be used instead.  
0x06  
0x08  
0x0C  
R_TMV RISC timer valid register. Used exclusively by the CP to determine if a timer is currently  
enabled. If the corresponding timer is enabled, a bit is 1. R_TMV should not be modiÞed by the  
user. The SET TIMER command should be used instead.  
TM_CMD RISC timer command register. Used as a parameter location when the SET TIMER command is  
issued. The user should write this location before issuing the SET TIMER command. This register  
is deÞned in Section 13.6.2, ÒRISC Timer Command Register (TM_CMD).Ó  
TM_CNT RISC timer internal count. A tick counter that the CP updates after each tick.The update occurs  
after the CP complete scanning the timer table.All 16 timers are scanned every tick interval  
regardless of whether any of them is enabled.It is updated if the CPÕs internal timer is enabled,  
regardless of whether any of the 16 timers are enabled and it can be used to track the number  
of ticks the CP receives and responds to.TM_CNT is updated only after the last timer (timer 15)  
has been serviced. If the CP is so busy with other tasks that it does not have time to service all  
the timers during a tick interval, and timer 15 has not been serviced, then TM_CNT would not  
be updated in that tick interval.  
1
Offset from timer base address (0x8AE0)  
13.6.2 RISC Timer Command Register (TM_CMD)  
Figure 13-10 shows the RISC timer command register (TM_CMD).  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
28  
13  
29  
14  
30  
15  
31  
Field  
V
R
Ñ
TN  
Bits  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
Field  
TIMER PERIOD (TP)  
Figure 13-10. RISC Timer Command Register (TM_CMD)  
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Part IV. Communications Processor Module  
TM_CMD Þelds are described in Figure 13-11.  
Figure 13-11. TM_CMD Field Descriptions  
Bits Name  
Description  
0
1
V
R
Valid. This bit should be set to enable the timer and cleared to disable it.  
Restart. Should be set for an automatic restart or cleared for a one-shot operation of the timer.  
Reserved. These bits should be written with zeros.  
2Ð11  
Ñ
TN  
TP  
12Ð15  
16Ð31  
Timer number. A value from 0Ð15 signifying which timer to useÑan offset into the timer table entries.  
Timer period. The 16-bit timeout value of the timer is zero-based. The minimum value is 1 and is  
programmed by writing 0x0000 to the timer period.The maximum value of the timer is 65,536 and is  
programmed by writing 0xFFFF.  
13.6.3 RISC Timer Table Entries  
The 16 timers are located in the block of memory following the TM_BASE location; each  
timer occupies 4 bytes. The Þrst half-word forms the initial value of the timer written during  
the execution of the SET TIMER command and the next half-word is the current value of the  
timer that is decremented until it reaches zero. These locations should not be modiÞed by  
the user. They are documented only as a debugging aid for user code. Use the SET TIMER  
command to initialize table values.  
13.6.4 RISC Timer Event Register (RTER)/Mask Register (RTMR)  
The RTER is used to report events recognized by the 16 timers and to generate interrupts.  
RTER can be read at any time. Bits are cleared by writing ones; writing zeros does not affect  
bit values.  
The RISC timer mask register (RTMR) is used to enable interrupts that can be generated in  
the RTER. Setting an RTMR bit enables the corresponding interrupt in the RTER; clearing  
a bit masks the corresponding interrupt. An interrupt is generated only if the RISC timer  
table bit is set in the SIU interrupt mask register; see Section 4.3.1.5, ÒSIU Interrupt Mask  
Registers (SIMR_H and SIMR_L).Ó  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field TMR1 TMR1 TMR1 TMR1 TMR1 TMR1 TMR TMR TMR TMR TMR TMR TMR TMR TMR TMR  
0
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
Res  
et  
0000_0000_0000_0000  
R/W  
Addr  
R/W  
0x119D6 (RTER)/0x119DA (RTMR)  
Figure 13-12. RISC Timer Event Register (RTER)/Mask Register (RTMR)  
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Part IV. Communications Processor Module  
13.6.5 SET TIMER Command  
The SET TIMER command is used to enable, disable, and conÞgure the 16 timers in the RISC  
timer table and is issued to the CPCR. This means the value 0x29E1008 should be written  
to CPCR. However, before writing this value, the user should program the TM_CMD Þelds.  
See Section 13.6.2, ÒRISC Timer Command Register (TM_CMD).Ó  
13.6.6 RISC Timer Initialization Sequence  
The following sequence initializes the RISC timers:  
1. ConÞgure RCCR to determine the preferred tick interval for the entire timer table.  
The TIME bit is normally set at this time but can be set later if all RISC timers need  
to be synchronized.  
2. Determine the maximum number of timers to be located in the timer table.  
ConÞgure the TM_BASE in the RISC timer table parameter RAM to point to a  
location in the dual-port RAM with 4 ´ n bytes available, where n is the number of  
timers. If n is less than 16, use timer 0 through timer nÐ1 to save space.  
3. Clear the TM_CNT Þeld in the RISC timer table parameter RAM to show how many  
ticks elapsed since the RISC internal timer was enabled. This step is optional.  
4. Clear RTER, if it is not already cleared. Write ones to clear this register.  
5. ConÞgure RTMR to enable the timers that should generate interrupts. Ones enable  
interrupts.  
6. Set the RISC timer table bit in the SIU interrupt mask register (SIMR_L[RTT]) to  
generate interrupts to the system. The SIU interrupt controller may require other  
initialization not mentioned here.  
7. ConÞgure the TM_CMD Þeld of the RISC timer table parameter RAM. At this  
point, determine whether a timer is to be enabled or disabled, one-shot or restart, and  
what its timeout period should be. If the timer is being disabled, the parameters  
(other than the timer number) are ignored.  
8. Issue the SET TIMER command by writing 0x29E1_0008 to the CPCR.  
9. Repeat the preceding two steps for each timer to be enabled or disabled.  
13.6.7 RISC Timer Initialization Example  
The following sequence initializes RISC timer 0 to generate an interrupt approximately  
every second using a 133-MHz general system clock:  
1. Write 111111 to RCCR[TIMEP] to generate the slowest clock. This value generates  
a tick every 64,512 clocks, which is every 485 µs at 133 MHz.  
2. ConÞgure the TM_BASE in the RISC timer table parameter RAM to point to a  
location in the dual-port RAM with 4 bytes available. Assuming the beginning of  
dual-port RAM is available, write 0x0000 to TM_BASE.  
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Part IV. Communications Processor Module  
3. (Optional) Write 0x0000 to the TM_CNT Þeld in the RISC timer table parameter  
RAM to see how many ticks elapsed since the RISC internal timer was enabled.  
4. Write 0xFFFF to the RTER to clear any previous events.  
5. Write 0x0001 to the RTMR to enable RISC timer 0 to generate an interrupt.  
6. Write 0x0002_0000 to the SIU interrupt mask register (SIMR_L) to allow the RISC  
timers to generate a system interrupt. Initialize the SIU interrupt conÞguration  
register.  
7. Write 0xC000_080D to the TM_CMD Þeld of the RISC timer table parameter  
RAM. This enables RISC timer 0 to timeout after 2,061(decimal) ticks of the timer.  
The timer automatically restarts after it times out.  
8. Write 0x29E1_0008 to the CPCR to issue the SET TIMER command.  
9. Set RCCR[TIME] to enable the RISC timer to begin operation.  
13.6.8 RISC Timer Interrupt Handling  
The following sequence describes what normally would occur within an interrupt handler  
for the RISC timer tables:  
1. Once an interrupt occurs, read RTER to see which timers have caused interrupts. The  
RISC timer event bits are usually cleared by this time.  
2. Issue additional SET TIMER commands at this time or later, as preferred. Nothing  
needs to be done if the timer is being automatically restarted for a repetitive  
interrupt.  
3. Clear the RTT bit in the SIU interrupt pending register (SIPNR_L).  
4. Execute the RTE instruction.  
13.6.9 RISC Timer Table Scan Algorithm  
The CP scans the timer table once every tick. It handles each of the 16 timers at its turn and  
checks for other requests with higher priority to service, before handling the next one. For  
each valid timer in the table, the CP decrements the count and checks for a timeout. If none  
occurs, the CP moves to the next timer. If a timeout occurs, the CP sets the corresponding  
event bit in RTER. Then the CP checks to see if the timer is to be restarted and if it is, the  
CP leaves the timerÕs valid bit set in the R_TMV location and resets the current count to the  
initial count. Otherwise, it clears R_TMV. Once the timer table scanning has completed, the  
CP updates the TM_CNT value in the RISC timer table parameter RAM and stops working  
on the timer tables until the next tick.  
If a SET TIMER command is issued, the CP makes the appropriate modiÞcations to the timer  
table and parameter RAM, but does not scan the timer table until the next tick of the internal  
timer. It is important to use the SET TIMER command to properly synchronize timer table  
modiÞcations to the execution of the CP.  
MOTOROLA  
Chapter 13. Communications Processor Module Overview  
13-23  
       
Part IV. Communications Processor Module  
13.6.10 Using the RISC Timers to Track CP Loading  
The RISC timers can be used to track CP loading. The following sequence provides a way  
to use the 16 RISC timers to determine if the CP ever exceeds the 96% utilization level  
during any tick interval. Removing the timers adds a 4% margin to the CP utilization level,  
but the aggressive user can use this technique to push CP performance to its limit. The user  
should use the standard initialization sequence and incorporate the following differences:  
1. Program the tick of the RISC timers to be every 1,024 x 16 = 16,384 system clocks.  
2. Disable RISC timer interrupts, if preferred.  
3. Using the SET TIMER command, initialize all 16 RISC timers to have a timer period  
of 0xFFFF, which equates to 65,536.  
4. Program one of the four general-purpose timers to increment once every tick. The  
general-purpose timer should be free-running and should have a timeout of 65,536.  
5. After a few hours of operation, compare the general-purpose timer to the current  
count of RISC timer 15. If it is more than two ticks different from the  
general-purpose timer, the CP has, during some tick interval, exceeded the 96%  
utilization level.  
NOTE:  
General-purpose timers are up counters, but RISC timers are  
down counters. The user should take this under consideration  
when comparing timer counts.  
13-24  
MPC8260 PowerQUICC II UserÕs Manual  
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Chapter 14  
Serial Interface with Time-Slot Assigner  
140  
1F40 igure 14-1 shows a block diagram of the TSA. Two SI blocks in the MPC8260 (SI1 and  
SI2), can be programmed to handle eight TDM lines concurrently with the same ßexibility  
described in this manual. TDM channels on SI1 are referred to as TDMa1, TDMb1,  
TDMc1, TDMd1; TDM channels on SI2 are TDMa2, TDMb2, TDMc2, TDMd2.  
MOTOROLA  
Chapter 14. Serial Interface withTime-Slot Assigner  
14-1  
   
Part IV. Communications Processor Module  
Tx/Rx  
Route  
Shadow  
Address  
Register  
Mode  
Register  
Command  
Register  
Status  
RAM  
SI RAM  
Register  
Control  
Peripheral Bus  
CPM Mux  
Channel #  
Clock  
Route  
Multi-Channel  
Controllers  
(MCCs)  
RAM  
To: SMC1 SMC2 SCC1 SCC2 SCC3 SCC4 FCC1 FCC2 FCC3  
MUX MUX MUX MUX MUX MUX MUX MUX MUX  
Time-Slot  
Assigner (TSA)  
SMC1 SMC2 SCC1  
SCC2 SCC3 SCC4  
MII2/ MII3  
UTOPIA  
MII1/  
UTOPIA  
16  
8
Nonmultiplexed Serial Interface (NMSI) Pins  
Note:  
The CPM mux and the MCCs are not part of the SI.  
(See their respective chapters for details.)  
TDM A, B, C, D  
Strobes  
TDM A, B, C, D  
Pins  
Figure 14-1. SI Block Diagram  
If the time-slot assigner (TSA) is not used as intended, it can be used to generate complex  
wave forms on dedicated output pins. For instance, it can program these pins to implement  
stepper motor control or variable-duty cycle and period control on-the-ßy.  
14-2  
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Part IV. Communications Processor Module  
14.1 Features  
Each SI has the following features:  
¥
Can connect to four independent TDM channels. Each TDM can be one of the  
following:  
Ñ T1 or E1 line  
Ñ Integrated services digital network primary rate (PRI)  
Ñ An ISDN basic rateÐinterchip digital link (IDL) channel in up to four TDM  
channelsÑeach IDL channel requires support from a separate SCC  
Ñ ISDN basic rateÐgeneral circuit interface (GCI) in up to two TDM channelsÑ  
each GCI channel requires support from a separate SMC  
Ñ E3 or DS3 clear channel (on TDMa only)  
Ñ User-deÞned interfaces  
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
Independent, programmable transmit and receive routing paths  
Independent transmit and receive frame syncs allowed  
Independent transmit and receive clocks allowed  
Selection of rising/falling clock edges for the frame sync and data bits  
Supports 1´ and 2´ input clocks (1 or 2 clocks per data bit)  
Selectable delay (0Ð3 bits) between frame sync and frame start  
Four programmable strobe outputs and four (2´) clock output pins  
1- or 8-bit resolution in routing, masking, and strobe selection  
Supports frames up to 16,384 bits long  
Internal routing and strobe selection can be dynamically programmed  
Supports automatic echo and loopback mode for each TDM  
Supports parallel-nibble interface for E3 or DS3 on TDMa channel  
For the MCC route, the SI performs the following features:  
¥
¥
¥
Up to 128 independent communication channels (64-Kbps per channel)  
Arbitrary mapping of any TDM time slots  
Can connect up to four independent TDM channels. Each TDM channel can support  
up to 128 channels (all four channels can support up to 128 channels together).  
¥
¥
¥
Independent mapping for receive/transmit  
Individual channel echo or loop mode  
Global echo or loop mode through the SI  
MOTOROLA  
Chapter 14. Serial Interface withTime-Slot Assigner  
14-3  
     
Part IV. Communications Processor Module  
14.2 Overview  
The TSA implements both internal route selection and time-division multiplexing (TDM)  
for multiplexed serial channels. The TSA supports the serial bus rate and format for most  
standard TDM buses, including T1 and E1 highways, pulse-code modulation (PCM)  
highway, and the ISDN buses in both basic and primary rates. The two popular ISDN basic  
rate buses (interchip digital link (IDL) and general-circuit interface (GCI), also known as  
IOM-2) are supported.  
Because each SI supports four TDMs, it is possible to simultaneously support a  
combination of up to eight T1 or E1 lines, and basic rate or primary rate ISDN channels.  
The TDMa channel can support E3 or DS-3 rates as a clear channel in either a parallel-  
nibble or serial interface.  
TSA programming is independent of the protocol used. The serial controllers can be  
programmed for any synchronous protocol without affecting TSA programming. The TSA  
simply routes programmed portions of the received data frame from the TDM pins to the  
target controller, while the target controller handles the received data in the actual protocol.  
In its simplest mode, the TSA identiÞes the frame using one sync pulse and one clock signal  
provided externally by the user. This can be enhanced to allow independent routing of the  
receive and transmit data on the TDM. Additionally, the deÞnition of a time-slot need not  
be limited to 8 bits or even to a single contiguous position within the frame. Finally, the user  
can provide separate receive and transmit syncs as well as clocks. Figure 14-2 shows  
example TSA conÞgurations ranging from the simplest to the most complex.  
14-4  
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MOTOROLA  
   
Part IV. Communications Processor Module  
MPC8260  
Simplest TDM example  
1 TDM Sync  
1 TDM Clock  
SCC2  
SMC1  
TDM  
TSA  
Slot  
Slot  
3
3
Slot  
Slot  
N
TDM Tx  
TDM Rx  
N
SCC2  
More complex TDM exampleÑunique routing  
1 TDM Sync  
SMC1  
MPC8260  
1 TDM Clock  
SCC2  
SMC1  
TSA  
TDM  
Slot 1 Slot  
2
TDM Tx  
TDM Rx  
Slot  
3
Slot  
N
SMC1  
SCC2  
Even more complex TDM exampleÑmultiple time slot per  
channel with varying sizes of time slots  
MPC8260  
1 TDM Sync  
1 TDM Clock  
SCC2 SMC1  
SCC2  
TSA  
TDM  
TDM Tx  
TDM Rx  
SCC2  
SMC1 SCC2  
NOTE: The two shaded areas off SCC2 Rx are received as one high-speed data stream by SCC2 Rx  
stored together in the same data buffers  
Most complex TDM example ÑTotally independent Rx and Tx  
MPC8260  
1 TDM Sync  
1 TDM Clock  
SCC2 SMC1  
SCC2  
TSA  
TDM  
TDM Tx  
1 TDM Sync  
1 TDM Clock  
TDM Rx  
SMC1  
SCC2  
Figure 14-2. Various Configurations of a Single TDM Channel  
MOTOROLA  
Chapter 14. Serial Interface withTime-Slot Assigner  
14-5  
 
Part IV. Communications Processor Module  
At its most ßexible, the TSA can provide four separate TDM channels, each with  
independent receive and transmit routing assignments and independent sync pulse and  
clock inputs. Thus, the TSA can support eight, independent, half-duplex TDM sources, four  
in reception and four in transmission, using eight sync inputs and eight clock inputs.  
Figure 14-3 shows a dual-channel example.  
TDMa Tx SYNC  
TDMa Tx CLOCK  
SCC2 SMC1  
SCC2  
TDMa Rx  
TDMa Rx Sync  
TDMa Rx Clock  
TDMa Rx  
TDMa  
TDMb  
SMC1  
SCC3  
TSA  
TDMb Tx Sync  
TDMb Tx Clock  
SCC3  
SCC4  
TDMa Tx  
TDMb Rx Sync  
TDMb Rx Clock  
TDMb Rx  
SCC2  
SCCs can receive on one TDM and transmit on another (SCC2 and SCC3).  
SMC1  
Note:  
Figure 14-3. Dual TDM Channel Example  
In addition to channel programming, the TSA supports up to four strobe outputs that may  
be asserted on a bit or byte basis. These strobes are completely independent from the  
channel routing used by the SCCs and SMCs. The strobe outputs are useful for interfacing  
to other devices that do not support the multiplexed interface or for enabling/disabling  
three-state I/O buffers in a multiple-transmitter architecture. Notice that open-drain  
programming on the TXDx pins that supports a multiple-transmitter architecture occurs in  
the parallel I/O block. These strobes can also be used for generating output wave forms to  
support such applications as stepper-motor control.  
Most TSA programming is done in the two 256- ´ 16-bit SIx RAMs. These SIx RAMs are  
directly accessible by the core in the internal register section of the MPC8260 and are not  
14-6  
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MOTOROLA  
 
Part IV. Communications Processor Module  
associated with the dual-port RAM. One SIx RAM is always used to program the transmit  
routing; the other is always used to program the receive routing. SIx RAMs can be used to  
deÞne the number of bits/bytes to be routed to the MCC, FCC, SCC, or SMC and determine  
when external strobes are to be asserted and negated.  
The size of the SIx RAM available for time-slot programming depends on the userÕs  
conÞguration. The user deÞnes how many of the 256 entries are related to each TDM. The  
resolution of the division is by fractions of 32. If on-the-ßy changes are allowed, the SIx  
RAM entries are reduced according to the userÕs programming. The maximum frame length  
that can be supported in any conÞguration is 16,384 bits.  
The maximum external serial clock that may be an input to the TSA is CPM CLK/3.  
The SI supports two testing modesÑecho and loopback.  
¥
The echo mode provides a return signal from the physical interface by retransmitting  
the signal it has received. The physical interface echo mode differs from the  
individual FCC or SCC echo mode in that it can operate on the entire TDM signal  
rather than just on a particular serial channel.  
¥
Loopback mode causes the physical interface to receive the same signal it is sending.  
The SI loopback mode checks more than the individual serial loopback; it checks  
both the SI and the internal channel routes.  
Note that the ßexibility described in the preceding section can be applied to each of the four  
TDM channels and to all serial interfaces independently.  
14.3 Enabling Connections to TSA  
Each serial interface can be independently enabled to connect to one of the following: TSA,  
UTOPIA, MII, or dedicated external pins. Note the following:  
¥
Each FCC can be connected to a dedicated MII or one of four TDMs. FCC1 can also  
be connected to a 8-/16-bit UTOPIA level-2 interface; FCC2 can also be connected  
to an 8-bit UTOPIA level-2 interface.  
¥
¥
Each SCC or SMC can be connected to one of four TDMs or to its own set of pins.  
The MCC can be connected to one of the four TDMs with different numbers of  
channels.  
The four TDMs are connected to four independent TDM interfaces. Figure 14-4 illustrates  
the connection between the TSA and the serial interfaces. The connection is made by  
programming the CPM mux. See Chapter 15, ÒCPM Multiplexing.Ó Once the connections  
are made, the exact routing decisions are made in the SIx RAM.  
MOTOROLA  
Chapter 14. Serial Interface withTime-Slot Assigner  
14-7  
         
Part IV. Communications Processor Module  
TDM a channels  
TDM b channels  
TDM c channels  
MCCx  
TDM d channels  
TDM a,b,c,d Enable = 1  
En  
En  
En  
En  
TDM a Pins  
TDM b Pins  
TDM c Pins  
TDM d Pins  
Time-Slot  
Assigner  
SIx RAM  
FC1 = 0  
MII1/UTOPIA 16  
FCC1  
FCC2  
FCC3  
SCC1  
SCC2  
FC2 = 0  
FC3 = 0  
SC1 = 0  
SC2 = 0  
SC3 = 0  
MII2/UTOPIA 8  
MII3  
SCC1 pins  
SCC2 pins  
SCC3 pins  
SCC3  
SC4 = 0  
SCC4 pins  
SMC1 pins  
SMC2 pins  
SCC4  
SMC1  
SMC2  
SMC1 = 0  
SMC2 = 0  
In the CPM mux  
Figure 14-4. Enabling Connections to the TSA  
14.4 Serial Interface RAM  
Each SI has a transmit RAM and a receive RAM, each with four banks of 64 halfword  
entries that enable it to control TDM channel routing to all serial devices, including the  
MCCs. The SIx RAMs are uninitialized after power-on reset; unwanted results can occur if  
the user does not program them before enabling the multiplexed channels.  
Each 16-bit SI RAM entry deÞnes the routing of 1Ð8 bits or bytes at a time. In addition to  
the routing, up to four strobe pins (logic OR of four strobes in the transmit RAM and four  
in receive RAM) can be asserted according to the programming of the RAMs. The four SIx  
RAM banks can be conÞgured in many different ways to support various TDM channels.  
The user can deÞne the size of each SIx RAM that is related to a certain TDM channel by  
programming the starting bank of that TDM. Programming the starting shadow bank  
address, described in Section 14.5.3, ÒSIx RAM Shadow Address Registers (SIxRSR),Ó  
determines whether this RAM has a shadow for changing SIx RAM entries while the TDM  
channel is active. This reduces the number of available SIx RAM entries for that TDM.  
14-8  
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MOTOROLA  
     
Part IV. Communications Processor Module  
14.4.1 One Multiplexed Channel with Static Frames  
The example in Figure 14-5 shows one of many possible settings. With this conÞguration,  
the SIx RAM has 256 entries for transmit data and strobe routing and 256 entries for receive  
data and strobe routing. This conÞguration should be chosen only when one TDM is  
required and the routing on that TDM does not need to be dynamically changed. The  
number of entries available in the SIx RAM is determined by the user.  
Framing Signals  
SIx RAM address:  
0
L1TCLKax  
L1TSYNCax  
(16 bits wide)  
256 Entries  
TXa  
Route  
511  
1024  
L1RCLKax  
256 Entries  
RXa  
Route  
L1RSYNCax  
1535  
Figure 14-5. One TDM Channel with Static Frames and Independent Rx and Tx  
Routes  
14.4.2 One Multiplexed Channel with Dynamic Frames  
In the conÞguration shown in Figure 14-6, one multiplexed channel has 256 entries for  
transmit data and strobe routing and 256 entries for receive data and strobe routing. Each  
RAM has two sections, the current-route RAM and a shadow RAM for changing serial  
routing dynamically.  
After programming the shadow RAM, the user sets SIxCMDR[CSRxn] for the associated  
channel. When the next frame sync arrives, the SI automatically exchanges the current-  
route RAM for the shadow RAM. See Section 14.4.5, ÒStatic and Dynamic Routing.Ó  
MOTOROLA  
Chapter 14. Serial Interface withTime-Slot Assigner  
14-9  
     
Part IV. Communications Processor Module  
Framing Signals  
256  
SIx RAM Address:  
(16 Bits Wide)  
0
L1TCLKax  
L1TSYNCax  
128 Entries  
TXa  
Route  
255  
511  
1024  
1280  
L1RCLKax  
L1RSYNCax  
128 Entries  
RXa  
Route  
1279  
1535  
Figure 14-6. One TDM Channel with Shadow RAM for Dynamic Route Change  
This conÞguration should be chosen when only one TDM is needed, but dynamic rerouting  
may be needed on that TDM. Similarly, for two TDM channels, the number of SIx RAM  
entries are reduced for every TDM channel programmed for shadow mode.  
14.4.3 Programming SIx RAM Entries  
The programming of each entry in the SIx RAM determines the routing of the serial bits (or  
bit groups) and the assertion of strobe outputs. If MCC is set, the entry refers to the  
corresponding MCC; otherwise, it refers to other serial controllers. Figure 14-7 shows the  
entry Þelds for both cases.  
Bits  
0
1
2
3
4
5
6
0
7
8
9
10 11 12 13 14  
15  
Field MCC = 0  
SWTR  
SSEL1 SSEL2 SSEL3 SSEL4  
CSEL  
CNT  
CNT  
BYT LST  
BYT LST  
MCC = 1 LOOP/ECHO SUPER  
MCSEL  
R/W  
Addr  
R/W  
See Chapter 3, ÒMemory Map.Ó  
Figure 14-7. SIx RAM Entry Fields  
When MCC = 0, the SIx RAM entry Þelds function as described in Table 14-1.  
14-10  
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MOTOROLA  
       
Part IV. Communications Processor Module  
Table 14-1. SIx RAM Entry (MCC = 0)  
Bits  
Name  
Description  
0
1
MCC  
The entry controls the functionality of the other bits in the SIx RAM entry.  
0 The entry refers to other serial controllers (FCCs, SCCs, SMC, according to the CSEL Þeld).  
1 The entry refers to the MCC.  
SWTR Switch Tx and Rx. Valid only in the receive route RAM and ignored in the transmit route RAM. SWTR  
affects the operation of both L1RXD and L1TXD. SWTR is set only in special situations where the  
user prefers to receive data from a transmit pin and transmit data on a receive pin. For instance,  
where devices A and B are connected to the same TDM, each with different time-slots. Normally,  
there is no opportunity for stations A and B to communicate with each other directly over the TDM,  
because they both receive the same TDM receive data and transmit on the same TDM transmit  
signal.  
0 Normal operation of L1TXD and L1RXD.  
1 Data for this entry is sent on L1RXD and received from L1TXD.  
See Figure 14-8 for details.  
2Ð5  
SSELx Strobe select. There are four strobes available that can be assigned to the receive RAM and  
asserted/negated with the received clock of this TDM channel (L1RCLKx).They can also be assigned  
to the transmit RAM and asserted/negated with the transmit clock of this TDM channel (L1TCLKx).  
Each bit corresponds to the value the strobe should have during this bit/byte group. There are four  
strobe pins for all eight strobe bits in the SIx RAM entries, so the value on a strobe pin is the logical  
OR of the Rx and Tx RAM entry strobe bit.s Multiple strobes can be asserted simultaneously. A  
strobe conÞgured to be asserted in consecutive SIx RAM entries remains continuously asserted for  
both entries. A strobe asserted on the last entry in a table is negated after the last entry is processed.  
Note: Each strobe is changed with the corresponding RAM clock and is output only if the  
corresponding parallel I/O is conÞgured as a dedicated pin. If a strobe is programmed to be asserted  
in more than one set of entries (the SI route entries for more then one TDM channel select the same  
strobe), the assertion of the strobe corresponds to the logical OR of all possible sources. This use of  
strobes is not useful for most applications. A given strobe should be selected in only one set of SIx  
RAM entries.  
6
Ñ
Reserved, should be cleared.  
7Ð10  
CSEL Channel select  
0000 The bit/byte group is not supported by the MPC8260.The transmit data pin is three-stated and  
the receive data pin is ignored.  
0001 The bit/byte group is routed to SCC1.  
0010 The bit/byte group is routed to SCC2.  
0011 The bit/byte group is routed to SCC3.  
0100 The bit/byte group is routed to SCC4.  
0101 The bit/byte group is routed to SMC1.  
0110 The bit/byte group is routed to SMC2.  
0111 The bit/byte group is not supported by the MPC8260. This code is also used in SCIT mode as  
the D channel grant. See Section 14.7.2.2, ÒSCIT Programming.Ó  
1000 Reserved.  
1001 The bit/byte group is routed to FCC1.  
1010 The bit/byte group is routed to FCC2.  
1011 The bit/byte group is routed to FCC3.  
11xx Reserved.  
MOTOROLA  
Chapter 14. Serial Interface withTime-Slot Assigner  
14-11  
 
Part IV. Communications Processor Module  
Table 14-1. SIx RAM Entry (MCC = 0) (Continued)  
Bits  
Name  
Description  
11Ð13 CNT  
Count. Indicates the number of bits/bytes (according to the BYT bit) that the routing and strobe select  
of this entry controls. 000 = 1 bit/byte; 111= 8 bits/bytes.  
14  
15  
BYT  
LST  
Byte resolution  
0 Bit resolution. The CNT value indicates the number of bits in this group.  
1 Byte resolution. The CNT value indicates the number of bytes in this group.  
Last entry in the RAM. Whenever SIx RAM is used, LST must be set in one of the Tx or Rx entries of  
each group. Even if all entries of a group are used, this bit must still be set in the last entry.  
0 Not the last entry in this section of the route RAM.  
1 Last entry in this RAM. After this entry, the SI waits for the sync signal to start the next frame.  
Note that there must be only an even number of entries in an SIx RAM frame, because LST is active  
only in odd-numbered entries (assuming the entry count starts with 0). Therefore, to obtain an even  
number of entries, an entry may need to be split into two entries.  
Figure 14-8 shows how SWTR can be used.  
L1RXD  
L1TXD  
L1RXD  
L1TXD  
Rx  
Tx  
Rx  
Tx  
Rx  
Tx  
Tx  
Rx  
Station A  
Station B  
Station A  
Station B  
Tx and Rx SIx RAMn[SWTR] = 0  
Tx and Rx SIx RAMn[SWTR] = 1  
Figure 14-8. Using the SWTR Feature  
The SWTR option lets station B listen to transmissions from station A and send data to  
station A. To do this, station B would set SWTR in its receive route RAM. For this entry,  
receive data is taken from the L1TXD pin and data is sent on the L1RXD pin. If the user  
wants to listen only to station A transmissions and not send data on L1RXD, the CSEL bits  
in the corresponding transmit route RAM entry should be cleared to prevent transmission  
on the L1RXD pin.  
Station B can transmit data to station A by setting the SWTR bit of the entry in its receive  
route RAM. Data is sent on L1RXD rather than L1TXD, according to the transmit route  
RAM. Note that this conÞguration could cause collisions with other data on L1RXD unless  
an available (quiet) time slot is used. To transmit on L1RXD and not receive data on  
L1TXD, clear the CSEL bits in the receive route RAM.  
Note that if the transmit and receive sections of the TDM do not use a common clock  
source, the SWTR feature can cause erratic behavior. Note also this feature does not work  
with nibble operation.  
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Part IV. Communications Processor Module  
When MCC = 1, the SIx RAM entry Þelds function as described in Table 14-2.  
Table 14-2. SIx RAM Entry (MCC = 1)  
Bits  
Name  
Description  
0
1
MCC  
If MCC =1, the other SIx RAM entries in this table are valid:  
LOOP/ Channel loopback or echo.  
ECHO 0 Normal mode of operation.  
1 Operation depends on the following conÞgurations:  
In the receive SIx RAM, this bit selects loopback mode for this MCC channel. The channelÕs  
transmit data is sent to both the receiverÕs input and to the data output line.  
In the transmit SIx RAM, this bit selects echo mode for this MCC channel. The channelÕs receive  
data is sent both to the transmitterÕs line and to the receiverÕs input.  
To use the loop/echo modes, program the receive and transmit SIx RAMs identically, except that  
the LOOP/ECHO bit should be set in only one of the entry pairs; that is, select only one of the  
modes (echo or loopback, not both) per MCC slot. Also, the receive and transmit clocks must be  
identical.  
2
SUPER MCC super channel enable. See Section 27.5, ÒSuper-Channel Table.Ó  
0 The current entry refers to a regular channel.  
1 The current entry refers to a super channel.  
3Ð10  
MCSEL MCC channel select. Indicates the MCC channel the bit/byte group is routed to. 0000_0000 selects  
channel 0; 1111_1111, selects channel 255.  
For SI1 use values 0Ð127 and for SI2 use values 128Ð255. Note that the channel programming  
must be coherent with the MCCF; see Section 27.8, ÒMCC ConÞguration Registers (MCCFx).Ó  
11Ð13 CNT  
Count.  
If SUPER = 0 (normal mode), CNT indicates the number of bits/bytes (according to the BYT bit)  
that the routing select of this entry controls. 000 = 1 bit/byte; 111 = 8 bits/bytes.  
If SUPER = 1 (MCC super channel), CNT and BYT together indicate whether the current entry is  
the Þrst byte of the MCC super channel.  
CNT= 000 and BYT = 1ÑThe current entry is the Þrst byte of this MCC super channel.  
CNT= 111 and BYT = 0ÑThe current entry is not the Þrst byte of this MCC super channel.  
Note that because all SIx RAM entries relating to super channels must be 1-byte in resolution, only  
the above two combinations of CNT and BYT are allowed when SUPER = 1.  
14  
15  
BYT  
LST  
Byte resolution  
0 Bit resolution. The CNT value indicates the number of bits in this group.  
1 Byte resolution. The CNT value indicates the number of bytes in this group.  
Last entry in the RAM. Whenever the SIx RAM is used, LST must be set in one of the Tx or Rx  
entries of each group. Even if all entries of a group are used, LST must still be set in the last entry.  
0 Not the last entry in this section of the route RAM.  
1 Last entry in this RAM. After this entry, the SI waits for the sync signal to start the next frame.  
Note that there must be only an even number of entries in an SIx RAM frame, because LST is  
active only in odd-numbered entries (assuming the entry count starts with 0). Therefore, to obtain  
an even number of entries, an entry may need to be split into two entries.  
14.4.4 SIx RAM Programming Example  
This example shows how to program the RAM to support the 10-bit IDL bus. Figure 14-23  
shows the 10-bit IDL bus format. In this example, the TSA supports the B1 channel with  
SCC2, the D channel with SCC1, the Þrst 4 bits of the B2 channel with an external device  
(using a strobe to enable the external device), and the last 4 bits of B2 with SMC1.  
Additionally, the TSA marks the D channel with another strobe signal.  
MOTOROLA  
Chapter 14. Serial Interface withTime-Slot Assigner  
14-13  
     
Part IV. Communications Processor Module  
First, divide the frame from the start (the sync) to the end of the frame according to the  
support that is required:  
¥
¥
¥
¥
¥
¥
8 bits (B1)ÑSCC2  
1 bit (D)ÑSCC1 + strobe 1  
1 bitÑno support  
4 bits (B2)Ñstrobe 2  
4 bits (B2)ÑSMC1  
1 bit (D)ÑSCC1 + strobe 1  
Each of these six divisions can be supported by a single SIx RAM entry. Thus, six SIx RAM  
entries are needed. See Table 14-3.  
Table 14-3. SIx RAM Entry Descriptions  
SIx RAM Entry  
Entry  
Number  
MCC  
SWTR  
SSEL  
CSEL  
CNT  
BYT  
LST  
Description  
0
1
2
3
4
5
0
0
0
0
0
0
0
0
0
0
0
0
0000  
1000  
0000  
0100  
0000  
1000  
0010  
0001  
0000  
0000  
0101  
0001  
000  
000  
000  
011  
011  
000  
1
0
0
0
0
0
0
0
0
0
0
1
8-bit SCC2  
1-bit SCC1 strobe1  
1-bit no support  
4-bit strobe2  
4-bit SMC1  
1-bit SCC1 strobe1  
Note that because IDL requires the same routing for both receive and transmit, an exact  
duplicate of the above entries should be written to both the receive and transmit sections of  
the SIx RAM. Then SIxMR[CRTx] can be used to instruct the SIx RAM to use the same  
clock and sync to simultaneously control both sets of SIx RAM entries.  
14.4.5 Static and Dynamic Routing  
The SIx RAM has two operating modes for the TDMs:  
¥
Static routing. The number of SIx RAM entries is determined by the banks the user  
relates to the corresponding TDM and is divided into two parts (Rx and Tx). Three  
requirements must be met before the new routing takes effect.  
Ñ All serial devices connected to the TSA must be disabled.  
Ñ SI routing can be modiÞed.  
Ñ All appropriate serial devices connected to the TSA must be reenabled.  
14-14  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
¥
Dynamic routing. A TDMÕs routing deÞnition can be modiÞed while FCCs, MCCs,  
SCCs, or SMCs are connected to the TDM. The number of SIx RAM entries is  
determined by the banks the user relates to the corresponding TDM channel and is  
divided into four parts (Rx, Rx shadow, Tx, and Tx shadow).  
Dynamic changes divide portions of the SIx RAM into current-route and shadow RAM.  
Once the current-route RAM is programmed, the TSA and SI channels are enabled, and  
TSA operation begins. When a change in routing is required, the shadow RAM must be  
programmed with the new route and SIxCMDR[CSRxn] must be set. As a result, as soon  
as the corresponding sync arrives the SI exchanges the shadow RAM with the current-route  
RAM and resets CSRxn to indicate that the operation is complete. At this time, the user may  
change the routing again. Notice that the original current-route RAM is now the shadow  
RAM and vice versa. Figure 14-9 shows an example of the shadow RAM exchange process  
for two TDM channels both with half of the RAM as a shadow.  
If for instance one TDM with dynamic changes is programmed to own all four banks, and  
the shadow is programmed to the last two banks, the initial current-route RAM addresses  
in the SIx RAM are as follows.  
¥
¥
0Ð255: TXa route  
1024Ð1279: RXa route  
The initial shadow RAMs are at addresses:  
¥
¥
256Ð511: TXa route  
1280Ð1535: RXa route  
The user can read any RAM at any time, but for proper SI operation the user must not  
attempt to write the current-route RAM. The SIx status register (SIxSTR) can be read to Þnd  
out which part of the RAM is the current-route RAM. The user can also externally connect  
one of the strobes to an interrupt pin to generate an interrupt on a particular SIx RAM entry  
starting or ending execution by the TSA.  
An example is shown in Figure 14-9.  
MOTOROLA  
Chapter 14. Serial Interface withTime-Slot Assigner  
14-15  
Part IV. Communications Processor Module  
Initial State  
RAM Address:  
0
127 128  
64 TXa  
Shadow  
255 256  
383 384  
511  
1)  
64 TXb  
Route  
64 TXb  
Shadow  
64 TXa  
Route  
The TSA uses the first part of  
the RAM, and the shadow is  
the second part of the RAM.  
CSRxn = 0  
L1TCLKa  
L1TSYNCa  
L1TCLKb  
L1TSYNCb  
Framing Signals:  
CSRRa=0  
CSRTa=0  
CSRRb=0  
CSRTb=0  
1024  
1151 1152  
12791280  
14071408  
1535  
RAM Address:  
64 RXb  
64 RXb  
Shadow  
64 RXa  
Route  
64 RXa  
Shadow  
Route  
L1RCLKa  
L1RSYNCa  
L1RCLKb  
L1RSYNCb  
Framing Signals:  
RAM Address:  
0
127 128  
255 256  
383 384  
511  
Programming  
2)  
64 TXb  
Route  
64 TXb  
Shadow  
64 TXa  
Route  
64 TXa  
Shadow  
The user programs the  
shadow RAM for the new  
Rx and Tx route and sets  
CSRxn.  
L1TCLKa  
L1TSYNCa  
L1TCLKb  
L1TSYNCb  
Framing Signals:  
CSRRa=1  
CSRTa=1  
CSRRb=1  
CSRTb=1  
1024  
1151 1152  
12791280  
14071408  
1535  
RAM Address:  
64 RXb  
64 RXb  
Shadow  
64 RXa  
Route  
64 RXa  
Shadow  
Route  
L1RCLKa  
L1RSYNCa  
L1RCLKb  
L1RSYNCb  
Framing Signals:  
RAM Address:  
0
127 128  
255 256  
383 384  
511  
Swap  
3)  
64 TXb  
Route  
64 TXb  
Shadow  
64 TXa  
Shadow  
64 TXa  
Route  
The SI swaps between  
the shadow and the  
current-route RAMs  
and resets CSRxn.  
L1TCLKa  
L1TSYNCa  
L1TCLKb  
L1TSYNCb  
Framing Signals:  
CSRRa=0  
CSRTa=0  
CSRRb=0  
CSRTb=0  
RAM Address: 1024  
64 RXa  
Shadow  
1151 1152  
12791280  
14071408  
1535  
64 RXb  
Route  
64 RXb  
Shadow  
64 RXa  
Route  
L1RCLKa  
L1RSYNCa  
L1RCLKb  
L1RSYNCb  
Framing Signals:  
Figure 14-9. Example: SIx RAM Dynamic Changes, TDMa and b, Same SIx RAM Size  
14-16  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part IV. Communications Processor Module  
14.5 Serial Interface Registers  
The serial interface registers are described in the following sections. The MCC  
conÞguration registers, which deÞne the TDM mapping of the MCC channels, are  
described in Section 27.8, ÒMCC ConÞguration Registers (MCCFx).Ó Note that the  
programming of SI registers and SIx RAM must be coherent with the MCCF programming.  
14.5.1 SI Global Mode Registers (SIxGMR)  
The SI global mode registers (SIxGMR), shown in Figure 14-10, deÞnes the activation state  
of the TDM channels for each SI.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
STZD  
STZC  
STZB  
STZA  
END  
ENC  
ENB  
ENA  
0000_0000  
R/W  
Addr  
0x11B28 (SI1GMR), 0x11B48 (SI2GMR)  
Figure 14-10. SI Global Mode Registers (SIxGMR)  
Table 14-4 describes SIxGMR.  
Table 14-4. SIxGMR Field Descriptions  
Bit  
0Ð3  
Name  
Description  
STZx Program L1TXDx to zero for TDM a, b, c or d  
0 Normal operation  
1 L1TXDx = 0 until serial clocks are available, which is useful for GCI activation. See Section 14.7.1,  
ÒSI GCI Activation/Deactivation Procedure.Ó  
4Ð7  
ENx  
Enable TDMx. Note that enabling a TDM is the last step in initialization.  
0 TDM channel x is disabled. The SIx RAMs and routing for TDMx are in a state of reset, but all other  
SI functions still operate.  
1 All TDMx functions are enabled.  
14.5.2 SI Mode Registers (SIxMR)  
There are eight SI mode registers (SIxMR), shown in Figure 14-11, one for each TDM  
channel (SIxAMR, SIxBMR, SIxCMR, and SIxDMR). They are used to deÞne SI operation  
modes and allow the user (with SIx RAM) to support any or all of the ISDN channels  
independently when in IDL or GCI mode. Any extra serial channel can then be used for  
other purposes.  
MOTOROLA  
Chapter 14. Serial Interface withTime-Slot Assigner  
14-17  
                 
Part IV. Communications Processor Module  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14 15  
Ñ
SADx  
SDMx  
RFSDx  
DSCx CRTx SLx CEx FEx GMx TFSDx  
0000_0000_0000_0000  
R/W  
Addr  
0x11B20 (SI1AMR), 0x11B22 (SI1BMR), 0x11B24 (SI1CMR), 0x11B26 (SI1DMR)/  
0x11B40 (SI2AMR), 0x11B42 (SI2BMR), 0x11B44 (SI2CMR), 0x11B46 (SI2DMR)  
Figure 14-11. SI Mode Registers (SIxMR)  
Table 14-5 describes SIxMR Þelds.  
Table 14-5. SIxMR Field Descriptions  
Bits  
Name  
Description  
0
Ñ
Reserved. Should be cleared.  
1Ð3  
SADx Starting bank address for the RAM of TDM a, b, c or d. These three bits deÞne the starting bank  
address of the SIx RAM section that belongs to TDMx channel.  
Note: As noted previously, the SIx RAM contains four banks of 64 entries for receive and four banks  
of 64 entries for transmit. The starting bank address of each TDM can be programmed with a  
granularity of 32 entries. The user can put the shadow RAM section of the same TDM on the same  
bank, but the user cannot put two different TDMs on the same bank.  
The last entry of a certain TDM is determined by the LST bit in the SIx RAM entry. The user must  
set LST within the entries of SIx RAM blocks for every TDM used, that is, before the starting  
address of the next TDM.  
000 Þrst bank, Þrst 32 entries  
001 Þrst bank, second 32 entries  
010 second bank, Þrst 32entries  
011 second bank, second 32 entries  
100 third bank, Þrst 32 entries  
101 third bank, second 32 entries  
110 fourth bank, Þrst 32 entries  
111 fourth bank, second 32 entries  
4Ð5  
SDMx SI Diagnostic Mode for TDM a, b, c or d  
00 Normal operation.  
01 Automatic echo. In this mode, the TDM transmitter automatically retransmits the TDM received  
data on a bit-by-bit basis. The receive section operates normally, but the transmit section can  
only retransmit received data. In this mode, the L1GRx line is ignored.  
10 Internal loopback. In this mode, the TDM transmitter output is internally connected to the TDM  
receiver input (L1TXDx is connected to L1RXDx). The receiver and transmitter operate  
normally. The data appears on the L1TXDx pin and in this mode, L1RQx is asserted normally.  
The L1GRx line is ignored.  
11 Loopback control. In this mode, the TDM transmitter output is internally connected to the TDM  
receiver input (L1TXDx is connected to L1RXDx). The transmitter output (L1TXDx) and L1RQx  
are inactive. This mode is used to accomplish loopback testing of the entire TDM without  
affecting the external serial lines.  
Note: In modes 01, 10, and 11, the receive and transmit clocks should be identical.  
14-18  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
Table 14-5. SIxMR Field Descriptions (Continued)  
Bits  
6Ð7  
Name  
Description  
RFSDx Receive frame sync delay for TDM a, b, c, or d. Determines the number of clock delays between the  
receive sync and the Þrst bit of the receive frame. Even if CRTx is set, these bits do not control the  
delay for the transmit frame.  
00 No bit delay.The Þrst bit of the frame is transmitted/received on the same clock as the sync; use  
for GCI.  
01 1-bit delay. Use for IDL  
10 2-bit delay  
11 3-bit delay  
Figure 14-12 and Figure 14-13 show how these bits are used.  
8
9
DSCx Double speed clock for TDM a, b, c or d. Some TDMs, such as GCI, deÞne the input clock to be  
twice as fast as the data rate and this bit controls this option.  
0 The channel clock (L1RCLKx and/or L1TCLKx) is equal to the data clock. Use for IDL and most  
TDM formats.  
1 The channel clock rate is twice the data rate. Use for GCI.  
CRTx Common receive and transmit pins for TDM a, b, c or d. Useful when the transmit and receive  
sections of a given TDM use the same clock and sync signals. In this mode, L1TCLKx and  
L1TSYNCx pins can be used as general-purpose I/O pins.  
0 Separate pins. The receive section of this TDM uses L1RCLKx and L1RSYNCx pins for framing  
and the transmit section uses L1TCLKx and L1TSYNCx for framing.  
1 Common pins. The receive and transmit sections of this TDM use L1RCLKx as clock pin of  
channel x and L1RSYNCx as the receive and transmit sync pin. Use for IDL and GCI. RFSD and  
TFSD are independent of one another in this mode.  
10  
11  
SLx  
CEx  
Sync level for TDM a, b, c, or d.  
0 The L1RSYNCx and L1TSYNCx signals are active on logic Ò1Ó.  
1 The L1RSYNCx and L1TSYNCx signals are active on logic Ò0Ó.  
Clock edge for TDM a, b, c or d. The function depends on DSCx.  
When DSCx = 0:  
0 The data is sent on the rising edge of the clock and received on the falling edge (use for IDL).  
1 The data is sent on the falling edge of the clock and received on the rising edge.  
When DSCx = 1:  
0 The data is sent on the rising edge of the clock and received on the rising edge.  
1 The data is sent on the falling edge of the clock and received on the falling edge (use for GCI).  
See Figure 14-14 and Figure 14-15.  
12  
FEx  
Frame sync edge for TDM a, b, c or d. Determines whether L1RSYNCx and L1TSYNCx pulses are  
sampled with the falling/rising edge of the channel clock. See Figure 14-13, Figure 14-14,  
Figure 14-15, and Figure 14-16.  
0 Falling edge. Use for IDL and GCI.  
1 Rising edge.  
MOTOROLA  
Chapter 14. Serial Interface withTime-Slot Assigner  
14-19  
Part IV. Communications Processor Module  
Table 14-5. SIxMR Field Descriptions (Continued)  
Bits  
13  
Name  
Description  
GMx  
Grant mode for TDM a, b, c or d  
0 GCI/SCIT mode. The GCI/SCIT D channel grant mechanism for transmission is internally  
supported. The grant is one bit from the receive channel. This bit is marked by programming the  
channel select bits of the SIx RAM with 0111 to assert an internal strobe on it. See  
Section 14.7.2.2, ÒSCIT Programming.Ó  
1 IDL mode. A grant mechanism is supported if the corresponding CMXSCR[GRx] bit is set. The  
grant is a sample of L1GRx while L1TSYNCx is asserted. This grant mechanism implies the IDL  
access controls for transmission on the D channel. See Section 14.6.2, ÒIDL Interface  
Programming.Ó  
14Ð15 TFSDx Transmit frame sync delay for TDM a, b, c or d. Determines the number of clock delays between the  
transmit sync and the Þrst bit of the transmit frame. See Figure 14-16.  
00 No bit delay. The Þrst bit of the frame is transmitted/received on the same clock as the sync.  
01 1-bit delay  
10 2-bit delay  
11 3-bit delay  
Figure 14-12 shows the one-clock delay from sync to data when xFSD = 01.  
L1CLK  
(CE=0)  
End of Frame  
L1SYNC  
(FE=1)  
Data  
Bit-0  
Bit-1  
Bit-2  
Bit-3  
Bit-4  
Bit-5  
Bit-0  
One-Clock Delay from Sync Latch to First Bit of Frame  
Figure 14-12. One-Clock Delay from Sync to Data (xFSD = 01)  
Figure 14-13 shows the elimination of the single-clock delay shown in Figure 14-12 by  
clearing xFSD.  
L1CLK  
(CE=0)  
L1SYNC  
(FE=1)  
Data  
Bit-0  
Bit-1  
Bit-2  
Bit-3  
Bit-4  
Bit-0  
Bit-1  
Bit-2  
No Delay from Sync Latch to First Bit of Frame  
Figure 14-13. No Delay from Sync to Data (xFSD = 00)  
14-20  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
Figure 14-14 shows the effects of changing FE when CE = 1 with a 1-bit frame sync delay.  
CE=1  
xFSD=01  
L1CLK  
L1SYNC  
L1SYNC  
(FE=0)  
(FE=1)  
L1TxD  
(Bit-0)  
L1ST  
(On Bit-0)  
L1ST Driven from Clock High for Both FE Settings  
Rx Sampled Here  
Figure 14-14. Falling Edge (FE) Effect When CE = 1 and xFSD = 01  
Figure 14-15 shows the effects of changing FE when CE = 0 with a 1-bit frame sync delay.  
CE=0  
xFSD=01  
L1CLK  
L1SYNC  
L1SYNC  
(FE=0)  
(FE=1)  
L1TXD  
(Bit-0)  
L1ST is Driven from Clock Low  
in Both the FE Settings  
L1ST  
(On Bit-0)  
Rx Sampled Here  
Figure 14-15. Falling Edge (FE) Effect When CE = 0 and xFSD = 01  
MOTOROLA  
Chapter 14. Serial Interface withTime-Slot Assigner  
14-21  
   
Part IV. Communications Processor Module  
Figure 14-16 shows the effects of changing FE when CE = 1 with no frame sync delay.  
CE=1  
xFSD=00  
L1CLK  
L1SYNC  
(FE=0)  
L1TXD  
(Bit-0)  
The L1ST is Driven from Sync.  
Data is Driven from Clock Low.  
L1ST  
(On Bit-0)  
Rx Sampled Here  
L1SYNC  
(FE=0)  
L1TXD  
(Bit-0)  
L1ST is Driven from Clock High.  
L1ST  
(On Bit-0)  
L1SYNC  
(FE=1)  
L1TXD  
(Bit-0)  
Both Data Bit-0 and L1ST are  
Driven from Sync.  
L1ST  
(On Bit-0)  
Rx Sampled Here  
L1SYNC  
(FE=1)  
L1TXD  
(Bit-0)  
L1ST and Data Bit-0 is Driven  
from Clock Low.  
L1ST  
(On Bit-0)  
Figure 14-16. Falling Edge (FE) Effect When CE = 1 and xFSD = 00  
14-22  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part IV. Communications Processor Module  
Figure 14-17 shows the effects of changing FE when CE = 0 with no frame sync delay.  
CE=0  
xFSD=00  
(FE=1)  
L1CLK  
L1SYNC  
L1TXD  
(Bit-0)  
The L1ST is Driven from Sync.  
Data is Driven From Clock High.  
L1ST  
(On Bit-0)  
Rx Sampled Here  
L1SYNC  
(FE=1)  
(FE=0)  
(FE=0)  
L1TXD  
(Bit-0)  
L1ST is Driven from Clock Low.  
L1ST  
(On Bit-0)  
L1SYNC  
L1TXD  
(Bit-0)  
Both the Data and L1ST from Sync  
when Asserted during Clock High.  
L1ST  
(On Bit-0)  
L1SYNC  
L1TXD  
(Bit-0)  
Both the Data and L1ST from the Clock  
when Asserted during Clock Low.  
L1ST  
(On Bit-0)  
Figure 14-17. Falling Edge (FE) Effect When CE = 0 and xFSD = 00  
14.5.3 SIx RAM Shadow Address Registers (SIxRSR)  
The SIx RAM shadow address registers (SIxRSR), shown in Figure 14-18, deÞne the  
starting addresses of the shadow section in the SIx RAM for each of the TDM channels.  
MOTOROLA  
Chapter 14. Serial Interface withTime-Slot Assigner  
14-23  
       
Part IV. Communications Processor Module  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
Ñ
13  
14  
15  
Ñ
SSADA  
Ñ
SSADB  
Ñ
SSADC  
SSADD  
0000_0000_0000_0000  
R/W  
Addr  
0x11B2E (SI1RSR), 0x11B4E (SI2RSR)  
Figure 14-18. SIx RAM Shadow Address Registers (SIxRSR)  
Table 14-6 describes SIxRSR Þelds.  
Table 14-6. SIxRSR Field Descriptions  
Bits  
Name  
Description  
0, 4, 8,  
12  
Ñ
Reserved. Should be cleared.  
1Ð3,  
5Ð7,  
SSADx Starting bank address for the shadow RAM of TDM a, b, c, or d. DeÞnes the starting bank  
address of the shadow SIx RAM section that belongs to the corresponding TDM channel.  
9Ð11,  
13Ð15  
Note: As noted before, the SIx RAM contain four banks of 64 entries for receive and four banks of  
64 entries for transmit.  
In spite of the above, the starting bank address of each TDM can be programmed by the user in  
a granularity of 32 entries, but the user cannot put two different TDMs on the same bank.  
The user can put the shadow RAM section of the same TDM on the same bank.  
The last entry of a certain TDM frame is determined by the LST bit in the SIx RAM entry. The  
user must set this bit within the entries of SIx RAM shadow blocks for every TDM used. That  
means before the starting address of the next TDM.  
14.5.4 SI Command Register (SIxCMDR)  
The SI command registers (SIxCMDR), shown in Figure 14-19, allow the user to  
dynamically program the SIx RAM. When the user sets bits in the SIxCMDR, the SIx  
switches to the shadow SIx RAM at the end of the current-route RAM programming frame.  
For more information about dynamic programming, see Section 14.4.5, ÒStatic and  
Dynamic Routing.Ó  
Bits  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
Addr  
CSRRA  
CSRTA  
CSRRB  
CSRTB  
CSRRC  
CSRTC  
CSRRD  
CSRTD  
0000_0000  
R/W  
0x11B2A (SI1CMDR), 0x11B4A (SI2CMDR)  
Figure 14-19. SI Command Register (SIxCMDR)  
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Part IV. Communications Processor Module  
Table 14-7 describes SIxCMDR Þelds.  
Table 14-7. SIxCMDR Field Description  
Bits  
Name  
Description  
0, 2, CSRRx Change shadow RAM for TDM a, b, c, or d receiver. Set CSRRx causes the SI receiver to replace  
4, 6  
the current route RAM with the shadow RAM. Set by the user and cleared by the SI.  
0 The receiver shadow RAM is not valid. The user can write into the shadow RAM to program a  
new routing.  
1 The receiver shadow RAM is valid. The SI exchanges between the RAMs and take the new  
receive routing from the receiver shadow RAM. Cleared as soon as the switch has completed.  
1, 3, CSRTx Change shadow RAM for TDM a, b, c, or d transmitter. Set CRSTx causes the SI transmitter to  
5, 7  
replace the current route RAM with the shadow RAM. Set by the user and cleared by the SI.  
0 The transmitter shadow RAM is not valid. The user can write into the shadow RAM to program a  
new routing.  
1 The transmitter shadow RAM is valid. The SI exchanges between the RAMs and take the new  
transmitter routing from the receiver shadow RAM. Cleared as soon as the switch has completed.  
14.5.5 SI Status Registers (SIxSTR)  
The SI status register (SIxSTR), shown in Figure 14-20, identiÞes the current-route RAM.  
SIxSTR values are valid only when the corresponding SIxCMDR bit = 0.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
CRORA  
CROTA  
CRORB  
CROTB  
CRORC  
CROTC  
CRORD  
CROTD  
0000_0000  
R
Addr  
0x11B2C (SI1STR), 0x11B4C (SI2STR)  
Figure 14-20. SI Status Registers (SIxSTR)  
Table 14-8 describes SIxSTR Þelds.  
Table 14-8. SIxSTR Field Descriptions  
Bits  
Name  
Description  
0, 2,  
4, 6  
CRORx Current-route original receiver. Determines whether the current-route receiver RAM is the original  
or the shadow.  
0 The current-route receiver RAM is the original one.  
1 The current-route receiver RAM is the shadow.  
1, 3,  
5, 7  
CROTx Current-route original transmitter. Determines whether the current-route transmitter RAM is the  
original or the shadow.  
0 The current-route transmitter RAM is the original one.  
1 The current-route transmitter RAM is the shadow.  
14.6 Serial Interface IDL Interface Support  
The IDL interface is a full-duplex ISDN interface used to connect a physical layer device  
to the MPC8260. The MPC8260 supports both the basic and primary rate of the IDL bus.  
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Chapter 14. Serial Interface withTime-Slot Assigner  
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Part IV. Communications Processor Module  
In the basic rate of IDL, data on three channels (B1, B2, and D) is transferred in a 20-bit  
frame, providing a full-duplex bandwidth of 160 Kbps. The MPC8260 is an IDL slave  
device that is clocked by the IDL bus master (physical layer device) and has separate  
receive and transmit sections. Although the MPC8260 has eight TDMs, it can support only  
four independent IDL buses (limited by the number of serials that support IDL) using  
separate clocks and sync pulses. Figure 14-21 shows an application with two IDL buses.  
ISDN TE  
NT  
IDL1  
S/T  
S/T  
U
U
S/T  
MPC8260  
Interfaces  
Interfaces  
IDL2  
S/T  
S/T  
U
Figure 14-21. Dual IDL Bus Application Example  
14.6.1 IDL Interface Example  
An example of the IDL application is the ISDN terminal adaptor shown in Figure 14-22. In  
such an application, the IDL interface is used to connect the 2B+D channels between the  
MPC8260, CODEC, and S/T transceiver. One of the MPC8260Õs SCCs is conÞgured to  
HDLC mode to handle the D channel; another MPC8260Õs SCC is used to rate adapt the  
terminal data stream over the Þrst B channel. That SCC is conÞgured for HDLC mode if  
V.120 rate adoption is required. The second B channel is then routed to the CODEC as a  
digital voice channel, if preferred. The SPI is used to send initialization commands and  
periodically check status from the S/T transceiver. The SMC connected to the terminal is  
conÞgured for UART.  
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Part IV. Communications Processor Module  
System Bus (ROM and RAM)  
PCM  
CODEC/Filter  
Monocircuit  
POTS  
B1  
ASYNC  
SMC1  
SPI  
MPC8260  
IDL  
(Data)  
SMC2  
SCC2  
SCC3  
TSA  
B2+D  
ICL  
(Control)  
SCC1  
S/T  
Transceiver  
4 wire  
Ethernet  
B1+B2+D  
Ethernet  
PHY  
LAN  
Figure 14-22. IDL Terminal Adaptor  
The MPC8260 can identify and support each IDL channel or can output strobe lines for  
interfacing devices that do not support the IDL bus. The IDL signals for each transmit and  
receive channel are described in Table 14-9.  
Table 14-9. IDL Signal Descriptions  
Signal  
Description  
L1RCLKx  
IDL clock; input to the MPC8260.  
L1RSYNCx IDL sync signal; input to the MPC8260. This signal indicates that the clock periods following the pulse  
designate the IDL frame.  
L1RXDx  
IDL receive data; input to the MPC8260. Valid only for the bits supported by the IDL; ignored for any  
other signals present.  
L1TXDx  
IDL transmit data; output from the MPC8260. Valid only for the bits that are supported by the IDL;  
otherwise, three-stated.  
L1RQx  
IDL request permission to transmit on the D channel; output from the MPC8260 on the L1RQx pin.  
IDL grant permission to transmit on the D Channel; input to the MPC8260 on the L1TSYNCx pin.  
L1GRx  
Note: x = a, b, c, and d for TDMa, TDMb, TDMc, and TDMd (for SI1 and SI2).  
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Part IV. Communications Processor Module  
The basic rate IDL bus has the three following channels:  
¥
¥
¥
B1 is a 64-Kbps bearer channel  
B2 is a 64-Kbps bearer channel  
D is a 16-Kbps signaling channel  
There are two deÞnitions of the IDL bus frame structureÑ8 and 10 bits. The only difference  
between them is the channel order within the frame. See Figure 14-23.  
L1CLK  
L1SYNC  
10-Bit IDL  
L1RXD  
L1TXD  
B1  
B1  
D1  
B2  
B2  
D2  
D2  
D1  
8-Bit IDL  
L1RXD  
L1TXD  
B1  
B1  
B2  
B2  
D1 D2  
D1 D2  
Notes:  
1. Clocks are not to scale.  
2. L1RQx and L1GRx are not shown.  
Figure 14-23. IDL Bus Signals  
Note that previous versions of Motorola IDL-deÞned bit functions called auxiliary (A) and  
maintenance (M) were removed from the IDL deÞnition when it was concluded that the  
IDL control channel would be out-of-band. These functions were deÞned as a subset of the  
Motorola SPI format called serial control port (SCP). To implement the A and M bits as  
originally deÞned, program the TSA to access these bits and route them transparently to an  
SCC or SMC. Use the SPI to perform out-of-band signaling.  
The MPC8260 supports all channels of the IDL bus in the basic rate. Each bit in the IDL  
frame can be routed to any SCC and SMC or can assert a strobe output for supporting an  
external device. The MPC8260 supports the request-grant method for contention detection  
on the D channel of the IDL basic rate and when the MPC8260 has data to transmit on the  
D channel, it asserts L1RQx. The physical layer device monitors the physical layer bus for  
activity on the D channel and indicates that the channel is free by asserting L1GRx. The  
MPC8260 samples the L1GRx signal when the IDL sync signal (L1RSYNCx) is asserted.  
If L1GRx is asserted, the MPC8260 sends the Þrst zero of the opening ßag in the Þrst bit  
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Part IV. Communications Processor Module  
of the D channel. If a collision is detected on the D channel, the physical layer device  
negates L1GRx. The MPC8260 then stops sending and retransmits the frame when L1GRx  
is reasserted. This procedure is handled automatically for the Þrst two buffers of a frame.  
For the primary rate IDL, the MPC8260 supports up to four 8-bit channels in the frame,  
determined by the SIx RAM programming. To support more channels, the user can route  
more than one channel to each SCC and the SCC treats it as one high-speed stream and  
store it in the same data buffers (appropriate only for transparent data). Additionally, the  
MPC8260 can be used to assert strobes for support of additional external IDL channels.  
The IDL interface supports the CCITT I.460 recommendation for data-rate adaptation since  
it separately accesses each bit of the IDL bus. The current-route RAM speciÞes which bits  
are supported by the IDL interface and by which serial controller. The receiver only  
receives bits that are enabled by the receiver route RAM. Otherwise, the transmitter sends  
only bits that are enabled by the transmitter route RAM and three-states L1TXDx.  
14.6.2 IDL Interface Programming  
To program an IDL interface, Þrst program SIxMR[GMx] to the IDL grant mode for that  
channel. If the receive and transmit sections interface to the same IDL bus, set  
SIxMR[CRTx] to internally connect the Rx clock and sync signals to the transmit section.  
Then, program the SIx RAM used for the IDL channels to the preferred routing. See  
Section 14.4.4, ÒSIx RAM Programming Example.Ó  
DeÞne the IDL frame structure by programming SIxMR[xFSDx] to have a 1-bit delay from  
frame sync to data, SIxMR[FEx] to sample on the falling edge, and SIxMR[CEx] to transmit  
on the rising edge of the clock. Program the parallel I/O open-drain register so that L1TXDx  
is three-stated when inactive; see Section 35.2.1, ÒPort Open-Drain Registers (PODRAÐ  
PODRD).Ó To support the D channel, program the appropriate CMXSCR[GRx] bit, as  
described in Section 15.4.5, ÒCMX SCC Clock Route Register (CMXSCR),Ó and program  
the SIx RAM entry to route data to the chosen serial controller. The two deÞnitions of IDL,  
8 or 10 bits, are implemented by simply modifying the SIx RAM programming. In both  
cases, L1GRx is sampled with L1TSYNCx and transferred to the D-channel SCC as a grant  
indication.  
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Part IV. Communications Processor Module  
For example, based on the same 10-bit format as in Section 14.4.4, ÒSIx RAM  
Programming Example,Ó implement an IDL bus using SCC1, SCC2, and SMC1 connected  
to TDMa1 as follows:  
1. Program both the Tx and Rx sections of the SIx RAM as in Table 14-10.  
Table 14-10. SIx RAM Entries for an IDL Interface  
SIx RAM Entry  
Entry  
Number  
MCC  
SWTR  
SSEL  
CSEL  
CNT  
BYT  
LST  
Description  
0
1
2
3
4
5
0
0
0
0
0
0
0
0
0
0
0
0
0000  
0000  
0000  
0000  
0000  
1000  
0010  
0001  
0000  
0101  
0101  
0001  
000  
000  
000  
011  
011  
000  
1
0
0
1
1
0
0
0
0
0
0
1
8-bit SCC2  
1-bit SCC1  
1-bit no support  
4-bit SMC1  
4-bit SMC1  
1-bit SCC1 strobe1  
2. CMXSI1CR = 0x00. TDMA receive clock is CLK1.  
3. CMXSMR = 0x80. SMC1 is connected to the TSA.  
4. CMXSCR = 0xC040_0000. SCC1 and SCC2 are connected to the TSA. SCC1  
supports the grant mechanism because it handles the D channel.  
5. SI1AMR = 0x0145. TDMA grant mode is used with 1-bit frame sync delay in Tx  
and Rx and common receive-transmit mode.  
6. Set PPARA[6Ð9]. ConÞgures L1TXDa[0], L1RXDa[0], L1TSYNCa, and  
L1RSYNCa.  
7. Set PSORA[6Ð9]. ConÞgures L1TXDa[0], L1RXDa[0], L1TSYNCa, and  
L1RSYNCa.  
8. Set PDIRA[9]. ConÞgures L1TXDa[0].  
9. Set PODRA[9]. ConÞgures L1TXDa[0] to an open-drain output.  
10.Set PPARC[30,31]. ConÞgures L1TCLKa and L1RCLKa.  
11.Clear PDIRC[30,31] ConÞgures L1TCLKa and L1RCLKa.  
12.Clear PSORC[30,31]. ConÞgures L1TCLKa and L1RCLKa.  
13.Set PPARB[17]. ConÞgures L1RQa.  
14.Clear PSORB[17]. ConÞgures L1RQa.  
15.Set PDIRB[17]. ConÞgures L1RQa.  
16.Set PPARD[13]. ConÞgures L1ST1.  
17.Clear PSORD[13]. ConÞgures L1ST1.  
18.Set PDIRD[13]. ConÞgures L1ST1.  
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Part IV. Communications Processor Module  
19.SI1CMDR is not used.  
20.SI1STR does not need to be read.  
21.ConÞgure the SCC1 for HDLC operation (to handle the LAPD protocol of the D  
channel), and conÞgure SCC2 and SMC1 as preferred.  
22.SI1GMR = 0x01. Enable TDM A (one static TDM).  
23.Enable SCC1, SCC2 and SMC1.  
14.7 Serial Interface GCI Support  
The MPC8260 fully supports the normal mode of the GCI, also known as the ISDN-  
oriented modular revision 2.2 (IOM-2), and the SCIT. The MPC8260 also supports the D-  
channel access control in S/T interface terminals using the command/indication (C/I)  
channel.  
The GCI bus consists of four linesÑtwo data lines, a clock, and a frame synchronization  
line. Usually, an 8-kHz frame structure deÞnes the various channels within the 256-kbps  
data rate. The MPC8260 supports two (limited by the number of SMCs) independent GCI  
buses, each with independent receive and transmit sections. The interface can also be used  
in a multiplexed frame structure on which up to eight physical layer devices multiplex their  
GCI channels. In this mode, the data rate would be 2,048 kbps.  
In the GCI bus, the clock rate is twice the data rate. The SI divides the input clock by two  
to produce the data clock. The MPC8260 also has data strobe lines and the 1´ data rate  
clock L1CLKOx output pins. These signals are used for interfacing devices to GCI that do  
not support the GCI bus. Table 14-11 describes GCI signals for each transmit and receive  
channel.  
Table 14-11. GCI Signals  
Signal  
Description  
L1RSYNCx  
Used as a GCI sync signal; input to the MPC8260. This signal indicates that the clock periods  
following the pulse designate the GCI frame.  
L1RCLKx  
L1RXDx  
L1TXDx  
Used as a GCI clock; input to the MPC8260. The L1RCLKx signal frequency is twice the data clock.  
Used as a GCI receive data; input to the MPC8260.  
Used as a GCI transmit data; open-drain output. Valid only for the bits that are supported by the IDL;  
otherwise, three-stated.  
L1CLKOx  
Optional signal; output from the MPC8260. This 1´ clock output is used to clock devices that do not  
interface directly to the GCI. If the double-speed clock is used, (DSCx bit is set in the SIxMR), this  
output is the L1RCLKx divided by 2; otherwise, it is simply a 1´ output of the L1RCLKx signal.  
Note: x = a, b, c, and d for TDMa, TDMb, TDMc, and TDMd (for SI1 and SI2).  
The GCI bus signals are shown in Figure 14-24.  
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Part IV. Communications Processor Module  
L1CLK  
(2X the data rate)  
L1SYNC  
L1RXD  
L1TXD  
B1  
B1  
B2  
B2  
M (Monitor)  
M (Monitor)  
D1 D2  
D1 D2  
C/I  
C/I  
A
A
E
E
Notes: Clock is not to scale.  
L1CLKO is not shown.  
Figure 14-24. GCI Bus Signals  
In addition to the 144-Kbps ISDN 2B+D channels, the GCI provides Þve channels for  
maintenance and control functions:  
¥
¥
¥
¥
¥
B1 is a 64-Kbps bearer channel  
B2 is a 64-Kbps bearer channel  
M is a 64-Kbps monitor channel  
D is a 16-Kbps signaling channel  
C/I is a 48-Kbps C/I channel (includes A and E bits)  
The M channel is used to transfer data between layer 1 devices and the control unit (the  
CPU); the C/I channel is used to control activation/deactivation procedures or to switch test  
loops by the control unit. The M and C/I channels of the GCI bus should be routed to SMC1  
or SMC2, which have modes to support the channel protocols. The MPC8260 can support  
any channel of the GCI bus in the primary rate by modifying SIx RAM programming.  
The GCI supports the CCITT I.460 recommendation as a method for data rate adaptation  
since it can access each bit of the GCI separately. The current-route RAM speciÞes which  
bits are supported by the interface and which serial controller support them. The receiver  
only receives the bits that are enabled by the SIx RAM and the transmitter only transmits  
the bits that are enabled by the SIx RAM and does not drive L1TXDx. Otherwise, L1TXDx  
is an open-drain output and should be pulled high externally.  
The MPC8260 supports contention detection on the D channel of the SCIT bus. When the  
MPC8260 has data to transmit on the D channel, it checks a SCIT bus bit that is marked  
with a special route code (usually, bit 4 of C/I channel 2). The physical layer device  
monitors the physical layer bus for activity on the D channel and indicates on this bit that  
the channel is free. If a collision is detected on the D channel, the physical layer device sets  
bit 4 of C/I channel 2 to logic high. The MPC8260 then aborts its transmission and  
retransmits the frame when this bit is set again. This procedure is automatically handled for  
the Þrst two buffers of a frame.  
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Part IV. Communications Processor Module  
14.7.1 SI GCI Activation/Deactivation Procedure  
In the deactivated state, the clock pulse is disabled and the data line is at a logic one. The  
layer 1 device activates the MPC8260 by enabling the clock pulses and by an indication in  
the channel 0 C/I channel. The MPC8260 reports to the core (via a maskable interrupt) that  
a valid indication is in the SMC RxBD.  
When the core activates the line, the data output of L1TXDn is programmed to zero by  
setting SIxGMR[STZx]. Code 0 (command timing TIM) is transmitted on channel 0 C/I  
channel to the layer 1 device until STZx is reset. The physical layer device resumes the  
clock pulses and gives an indication in the channel 0 C/I channel. The core should reset  
STZx to enable data output.  
14.7.2 Serial Interface GCI Programming  
The following sections describe serial interface GCI programming.  
14.7.2.1 Normal Mode GCI Programming  
The user can program and conÞgure the channels used for the GCI bus interface. First, the  
SIxMR register to the GCI/SCIT mode for that channel must be programmed, using the  
DSCx, FEx, CEx, and RFSDx bits. This mode deÞnes the sync pulse to GCI sync for  
framing and data clock as one-half the input clock rate. The user can program more than  
one channel to interface to the GCI bus. Also, if the receive and transmit section are used  
for interfacing the same GCI bus, the user internally connects the receive clock and sync  
signals to the SIx RAM transmit section, using the CRTx bits. The user should then deÞne  
the GCI frame routing and strobe select using the SIx RAM.  
When the receive and transmit section uses the same clock and sync signals, these sections  
should be programmed to the same conÞguration. Also, the L1TXDx pin in the I/O register  
should be programmed to be an open-drain output. To support the monitor and the C/I  
channels in GCI, those channels should be routed to one of the SMCs. To support the D  
channel when there is no possibility of collision, the user should clear the SIxMR[GRx] bit  
corresponding to the SCC that supports the D channel.  
14.7.2.2 SCIT Programming  
For interfacing the GCI/SCIT bus, SIxMR must be programmed to the GCI/SCIT mode.  
The SIx RAM is programmed to support a 96-bit frame length and the frame sync is  
programmed to the GCI sync pulse. Generally, the SCIT bus supports the D channel access  
collision mechanism. For this purpose, the user should program the CRTx bits so the  
receive and transmit sections use the same clock and sync signals and program the GRx bits  
to transfer the D channel grant to the SCC that supports this channel. The received (grant)  
bit should be marked by programming the channel select bits of the SIx RAM to 0b0111  
for an internal assertion of a strobe on this bit. This bit is sampled by the SI and transferred  
to the D-channel SCC as the grant. The bit is generally bit 4 of the C/I in channel 2 of the  
GCI, but any other bit can be selected using the SIx RAM.  
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Chapter 14. Serial Interface withTime-Slot Assigner  
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Part IV. Communications Processor Module  
For example, assuming that SCC1 is connected to the D channel, SCC2 to the B1 channel,  
and SMC2 to the B2 channel, SMC1 is used to handle the C/I channels, and the D-channel  
grant is on bit 4 of the C/I on SCIT channel 2, the initialization sequence is as follows:  
1. Program both the Tx and Rx sections of the SIx RAM as in Table 14-12 beginning  
at addresses 0 and 1024, respectively.  
Table 14-12. SIx RAM Entries for a GCI Interface (SCIT Mode)  
SIx RAM Entry  
Entry  
Number  
MCC  
SWTR  
SSEL  
CSEL  
CNT  
BYT  
LST  
Description  
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0010  
0110  
0101  
0001  
0101  
0000  
0000  
0111  
000  
000  
000  
001  
101  
110  
001  
000  
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
1
8 Bits SCC2  
8 Bits SMC2  
8 Bits SMC1  
2 Bits SCC1  
6 Bits SMC1  
Skip 7 bytes  
Skip 2 bits  
D grant bit  
2. SI1AMR = 0x00c0. TDMa is used in double speed clock and common Rx/Tx  
modes. SCIT mode is used in this example.  
Note: If SCIT mode is not used, delete the last three entries of  
the SIx RAM, divide one entry into two and set the LST bit in  
the new last entry.  
3. CMXSMR = 0x88. SMC1 and SMC2 are connected to the TSA.  
4. CMXSCR = 0xC040_0000. SCC2 and SCC1 are connected to the TSA. SCC1  
supports the grant mechanism since it is on the D channel.  
5. CMXSI1CR = 0x00. TDMa uses CLK1.  
6. Set PPARA[6Ð9]. ConÞgures L1TXDa[0], L1RXDa[0], L1TSYNCa and  
L1RSYNCa.  
7. Set PSORA[6Ð9]. ConÞgures L1TXDa[0], L1RXDa[0], L1TSYNCa and  
L1RSYNCa.  
8. Set PDIRA[9]. ConÞgures L1TXDa[0].  
9. Set PODRA[9]. ConÞgures L1TXDa[0] to an open-drain output.  
10.Set PPARC[30,31]. ConÞgures L1TCLKa and L1RCLKa.  
11.Clear PDIRC[30,31]. ConÞgures L1TCLKa and L1RCLKa.  
12.Clear PSORC[30,31]. ConÞgures L1TCLKa and L1RCLKa.  
13.Set PPARB[17]. ConÞgures L1CLKO and L1RQa.  
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Part IV. Communications Processor Module  
14.Clear PSORB[17]. ConÞgures L1CLKO and L1RQa.  
15.Set PDIRB[17]. ConÞgures L1CLKO and L1RQa.  
16.If the 1x GCI data clock is required, set PBPAR bit 16 and PBDIR bit 16 and clear  
PSORB 16, which conÞgures L1CLKOa as an output.  
17.ConÞgure SCC1 for HDLC operation (to handle the LAPD protocol of the D  
channel). ConÞgure SMC1 for SCIT operation and conÞgure SCC2 and SMC2 as  
preferred.  
18.SI1GMR = 0x11. Enable TDMa (one static TDM), STZ for TDMa.  
19.SI1CMDR is not used.  
20.SI1STR does not need to be read.  
21.Enable the SCC1, SCC2, SMC1 and SMC2.  
MOTOROLA  
Chapter 14. Serial Interface withTime-Slot Assigner  
14-35  
Part IV. Communications Processor Module  
14-36  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Chapter 15  
CPM Multiplexing  
150  
1T50 he CPM multiplexing logic (CMX) connects the physical layerÑUTOPIA, MII, modem  
lines, TDM lines and proprietary serial lines to the FCCs, SCCs and SMCs. The CMX  
features the following two modes:  
¥
¥
In NMSI mode, the CMX allows all serial devices to be connected to their own set  
of individual pins. Each serial device that connects to the external world in this way  
is said to connect to a nonmultiplexed serial interface (NMSI). In the NMSI  
conÞguration, the CMX provides a ßexible clocking assignment for each FCC, SCC  
and SMC from a bank of external clock pins and/or internal BRGs.  
In TDM mode, the CMX performs the connection of the serial devices to the SIs for  
using the time-slot assigner (TSA). This allows any combination of MCCs, FCCs,  
SCCs, and SMCs to multiplex data on any of the eight TDM channels. The CMX  
connects the serial device only to the TSA in the SIx. The actual multiplexing of the  
TDM is made by programming the SIx RAM. In TDM mode, all other pins used in  
NMSI mode are available for other purposes. See Chapter 14, ÒSerial Interface with  
Time-Slot Assigner.Ó  
The CMX also allows the user to route the multiple-PHY address to FCC1 or to FCC2 in  
various combinations, allowing the use of both FCCs in multiple-PHY mode.  
NOTE  
The CMX serves both SI1 and SI2. When the user programs the  
CMX to connect a serial device to the SI, the CMX connects  
that serial device to both SIs. Programming both SIs to use one  
serial device in the same time slot causes erratic behavior.  
Figure 15-1 shows a block diagram of the CMX.  
MOTOROLA  
Chapter 15. CPM Multiplexing  
15-1  
     
Part IV. Communications Processor Module  
Register Bus  
CPM Mux  
SIx  
Clock  
Registers  
(CMXSIxCR)  
UTOPIA  
Address  
Register  
SMC  
Clock  
Register  
(CMXSMR)  
SCC  
Clock  
Register  
(CMXSCR)  
FCC  
Clock  
Register  
(CMXFCR)  
(CMXUAR)  
BRGs  
MCCs  
To Serials:  
SMC1 SMC2 SCC1 SCC2 SCC3 SCC4 FCC1 FCC2 FCC3  
MUX MUX MUX MUX MUX MUX MUX MUX MUX  
MUX  
Time-Slot Assigner  
SIx  
SMC1 SMC2 SCC1 SCC2 SCC3 SCC4 MII1/  
MII2/ MII3  
8
Clocks  
UTOPIA UTOPIA  
8/16  
Nonmultiplexed Serial Interface (NMSI) Pins  
TDM Ax, Bx, Cx, Dx TDM Ax, Bx, Cx, Dx  
Strobes  
Pins  
Figure 15-1. CPM Multiplexing Logic (CMX) Block Diagram  
15.1 Features  
The NMSI mode supports the following:  
¥
Each FCC, SCC, and SMC can be programmed independently to work with a serial  
deviceÕs own set of pins in a non-multiplexed manner.  
¥
¥
¥
¥
¥
¥
Each FCC can be connected to its own MII (media-independent interface).  
FCC1 can also be connected to an 8- or 16-bit ATM UTOPIA level-2 interface.  
FCC2 can also be connected also to an 8-bit ATM UTOPIA level-2 interface.  
Each SCC can have its own set of modem control pins.  
Each SMC can have its own set of four pins.  
Each FCC, SCC, and SMC can be driven from a bank of twenty clock pins or a bank  
of eight BRGs.  
15-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part IV. Communications Processor Module  
The multiple-PHY addressing selection supports the following options for FCC1 and  
FCC2:  
¥
In master mode:  
Ñ FCC1 connect up to 31 PHYs and FCC2 connect up to 7 PHYs.  
Ñ FCC1 connect up to 15 PHYs and FCC2 connect up to 15 PHYs.  
Ñ FCC1 connect up to 7 PHYs and FCC2 connect up to 31 PHYs.  
In slave mode:  
¥
Ñ FCC1 connect up to 31 PHYs and FCC2 connect to 0 PHYs.  
Ñ FCC1 connect up to 15 PHYs and FCC2 connect up to 1 PHYs.  
Ñ FCC1 connect up to 7 PHYs and FCC2 connect up to 3 PHYs.  
Ñ FCC1 connect up to 3 PHYs and FCC2 connect up to 7 PHYs.  
Ñ FCC1 connect up to 1 PHYs and FCC2 connect up to 15 PHYs.  
Ñ FCC1 connect to 0 PHYs and FCC2 connect up to 31 PHYs.  
15.2 Enabling Connections to TSA or NMSI  
Each serial device can be independently enabled to connect to the TSA or to dedicated  
external pins, as shown in Figure 15-2. Each FCC can be connected to a dedicated MII or  
to the eight TDMs. FCC1 can also be connected to an 8- or 16-bit UTOPIA level-2  
interface. FCC2 can also be connected to an 8-bit UTOPIA level-2 interface. Each SCC or  
SMC can be connected to the eight TDMs or to its own set of pins. Once connections are  
made to the TSA, the exact routing decisions are made in the SIx RAMs.  
MOTOROLA  
Chapter 15. CPM Multiplexing  
15-3  
 
Part IV. Communications Processor Module  
TDM a channels  
TDM b channels  
TDM c channels  
MCCs  
TDM d channels  
TDM a,b,c,d Enable = 1  
En  
En  
En  
En  
TDM a Pins  
TDM b Pins  
TDM c Pins  
TDM d Pins  
Time-Slot  
Assigners  
SI RAMs  
FC1 = 0  
MII1/UTOPIA 8/16/M-phy  
FCC1  
FCC2  
FCC3  
SCC1  
SCC2  
FC2 = 0  
FC3 = 0  
SC1 = 0  
SC2 = 0  
SC3 = 0  
MII2/UTOPIA 8/M-phy  
MII3  
SCC1 Pins  
SCC2 Pins  
SCC3 Pins  
SCC3  
SC4 = 0  
SCC4 Pins  
SMC1 Pins  
SMC2 Pins  
SCC4  
SMC1  
SMC2  
SMC1 = 0  
SMC2 = 0  
Figure 15-2. Enabling Connections to the TSA  
15.3 NMSI ConÞguration  
The CMX supports an NMSI mode for each of the FCCs, SCCs, and SMCs. Each serial  
device is connected independently either to the NMSI or to the TSA using the clock route  
registers. The user should note, however, that NMSI pins are multiplexed with other  
functions at the parallel I/O lines. Therefore, if a combination of TDM and NMSI channels  
are used, consult the MPC8260Õs pinout to determine which FCC, SCC, and SMC to  
connect and where to connect them.  
The clocks provided to the FCCs, SCCs, and SMCs are derived from a bank of 8 internal  
BRGs and 20 external CLK pins; see Figure 15-3. There are two main advantages to the  
bank-of-clocks approach. First, a serial device is not forced to choose a serial device clock  
from a predeÞned pin or BRG; this allows a ßexible pinout-mapping strategy. Second, a  
group of serial receivers and transmitters that needs the same clock rate can share the same  
pin. This conÞguration leaves additional pins for other functions and minimizes potential  
skew between multiple clock sources.  
15-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part IV. Communications Processor Module  
BRG5  
BRG6  
BRG7  
BRG8  
BRGO5  
BRGO6  
BRGO7  
BRGO8  
BRG1  
BRG2  
BRG3  
BRG4  
Rx  
Tx  
FCC1  
FCC2  
FCC3  
SCC1  
SCC2  
SCC3  
SCC4  
BRGO1  
BRGO2  
BRGO3  
BRGO4  
Rx  
Tx  
Rx  
Tx  
CLK1  
CLK2  
CLK3  
CLK4  
Rx  
Tx  
CLK5  
CLK6  
CLK7  
CLK8  
CLK9  
Rx  
Tx  
Bank of Clocks  
Selection Logic  
CLK10  
Rx  
Tx  
CLK11  
CLK12  
(Partially filled cross-switch logic  
programmed in the CMX registers.)  
CLK13  
CLK14  
Rx  
Tx  
CLK15  
CLK16  
CLK17  
CLK18  
SMC1  
SMC2  
CLK19  
CLK20  
Rx Tx Rx Tx Rx Tx Rx Tx Rx Tx Rx Tx Rx Tx Rx Tx  
TDMA1 TDMB1 TDMC1 TDMD1 TDMA2 TDMB2 TDMC2 TDMD2  
Figure 15-3. Bank of Clocks  
The eight BRGs also make their clocks available to external logic, regardless of whether  
the BRGs are being used by a serial device. Notice that the BRG outputs are multiplexed  
with other functions; thus, all BRGOx pins may not always be available. Chapter 35,  
ÒParallel I/O Ports,Ó shows the function multiplexing.  
There are two restrictions in the bank-of-clocks mapping:  
¥
¥
Only four of the twenty sources can be connected to any given FCC or SCC receiver  
or transmitter.  
The SMC transmitter and receiver share the same clock source when connected to  
the NMSI.  
Table 15-1 shows the clock source options for the serial controllers and TDM channels.  
MOTOROLA  
Chapter 15. CPM Multiplexing  
15-5  
 
Part IV. Communications Processor Module  
Table 15-1. Clock Source Options  
CLK  
BRG  
Clock  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20  
1
2
3
4
5
6
7
8
SCC1 Rx  
SCC1 Tx  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SCC2 Rx  
SCC2 Tx  
SCC3 Rx  
SCC3 Tx  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SCC4 Rx  
SCC4 Tx  
FCC1 Rx  
FCC1 Tx  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
FCC2 Rx  
FCC2 Tx  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
FCC3 Rx  
FCC3 Tx  
TDMA1 Rx  
TDMA1 Tx  
TDMB1 Rx  
TDMB1 Tx  
TDMC1 Rx  
TDMC1 Tx  
TDMD1 Rx  
TDMD1 Tx  
TDMA2 Rx  
TDMA2 Tx  
TDMB2 Rx  
TDMB2 Tx  
TDMC2 Rx  
TDMC2 Tx  
TDMD2 Rx  
TDMD2 Tx  
SMC1 Rx  
SMC1 Tx  
SMC2 Rx  
SMC2 Tx  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Note that after a clock source is selected, the clock is given an internal name. For the FCCs  
and SCCs, the names are RCLKx and TCLKx; for SMCs, the name is simply SMCLKx.  
These internal names are used only in NMSI mode to specify the clocks sent to the FCCs,  
SCCs or SMCs. These names do not correspond to any MPC8260 pins.  
15.4 CMX Registers  
The following sections describe the CMX registers.  
15-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
15.4.1 CMX UTOPIA Address Register (CMXUAR)  
The CMX UTOPIA address register (CMXUAR), shown in Figure 15-4, deÞnes the  
connection of FCC1 and FCC2 UTOPIA multiple-PHY addresses to the twenty UTOPIA  
address pins of the MPC8260; it also deÞnes the connection of a BRG to the FCCs when  
an internal rate feature is used. This enables the user to implement a multiple-PHY  
UTOPIA master or slave on both FCC1 and FCC2 using only twenty pins. The user chooses  
how many PHYs to use with each interface and how many address lines are needed for each  
FCC.  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field SAD0 SAD1 SAD2 SAD3 SAD4  
Ñ
MAD4 MAD3  
F1IRB  
F2IRB  
Ñ
Reset  
R/W  
0000_0000_0000_0000  
R/W  
Addr  
0x11B0E  
Figure 15-4. CMX UTOPIA Address Register (CMXUAR)  
Table 15-2 describes CMXUAR Þelds.  
Table 15-2. CMXUAR Field Descriptions  
Bits  
0Ð4  
Name  
Description  
SADx  
Slave address input pin x connection. Note that the address indexes are relative to FCC1; see  
Figure 15-7.  
0 This address input pin is used by FCC2 in slave mode.  
1 This address input pin is used by FCC1 in slave mode.  
5
Ñ
Reserved, should be cleared.  
6Ð7  
MADx Master address output pin x connection. Note that the address indexes are relative to FCC1; see  
Figure 15-7.  
0 This address output pin is used by FCC2 in master mode.  
1 This address output pin is used by FCC1 in master mode.  
8Ð9  
F1IRB FCC1 internal rate BRG selection. Selects the BRG to be connected to FCC 1 for internal rate  
operation. Used by the ATM controller; see Section 29.2.1.4, ÒTransmit External Rate and Internal  
Rate Modes.Ó  
00 FCC1 internal rate clock is BRG5.  
01 FCC1 internal rate clock is BRG6.  
10 FCC1 internal rate clock is BRG7.  
11 FCC1 internal rate clock is BRG8.  
10Ð11 F12IRB FCC2 internal rate BRG selection. Selects the BRG to be connected to FCC 2 for internal rate  
operation. Used by the ATM controller; see Section 29.2.1.4, ÒTransmit External Rate and Internal  
Rate Modes.Ó  
00 FCC2 internal rate clock is BRG5.  
01 FCC2 internal rate clock is BRG6.  
10 FCC2 internal rate clock is BRG7.  
11 FCC2 internal rate clock is BRG8.  
12Ð15  
Ñ
Reserved, should be cleared.  
MOTOROLA  
Chapter 15. CPM Multiplexing  
15-7  
         
Part IV. Communications Processor Module  
Note that each SADx and MADx corresponds to a pair of separate receive and transmit  
address pins.  
The MPC8260 has 16 output address pins and 10 input address pins dedicated for the  
UTOPIA interface. However, it has two FCCs with two parts eachÑreceiver and  
transmitter that can be ether master or slave concurrently. The MPC8260 allows both FCC1  
and FCC2 to connect to the address lines without putting limitations on being a master or  
slave, as described in the following:  
¥
For master mode: The user has two groups of eight address pins each. Three pins  
from each group are always connected to FCC1 and three are always connected to  
FCC2. The user decides which FCC uses the remaining two pins by programming  
CMXUAR[MADx]. See Figure  
Pins  
FCC1  
5
5
M
These three bits always relate  
to an FCC1 master.  
8
5
S
5
5
M
S
0
1
These two address bits relate to the  
master of FCC1 or FCC2 according  
to the programming. Bit 4 is the  
msb.  
2
4 3  
4
3
2
1
0
FCC2  
5
5
M
S
These three bits always relate  
to FCC2 master  
8
5
5
5
M
S
Figure 15-5. Connection of the Master Address  
¥
For slave modeÑThe user has two groups of Þve address pins each. The user  
decides which FCC uses each pin by programming CMXUAR[SADx]. Connect any  
UTOPIA pins that are not connected to MPC8260 pins to GND. See Figure 15-6.  
15-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part IV. Communications Processor Module  
Pins  
FCC1  
5
M
5
8
5
S
5
5
M
0
4
3
2
1
0
1
2
3
4
S
These 5 address bits relate to the  
slave of FCC1 or FCC2 according to  
the programming. Bit 4 is the msb.  
FCC2  
5
5
M
S
8
5
5
5
NOTE:To use FCC2 as shown, connect the FCC2 address bits reversed with  
respect to the pinout address indexes. PHY address pins with no pin  
connection should be connected to GND.  
M
S
Figure 15-6. Connection of the Slave Address  
Note that the user must program the addresses of the PHYs to be consecutive for each FCC;  
that is, the address lines connected to each FCC must be consecutive.  
Figure 15-7 describes the interconnection between the receive external multi-PHY bus and  
the internal FCC1 and FCC2 receive multi-PHY addresses. The same diagram applies to  
the transmit multi-PHY bus using different dedicated parallel I/O pins.  
MOTOROLA  
Chapter 15. CPM Multiplexing  
15-9  
 
Part IV. Communications Processor Module  
MAD4  
MAD3  
FCC1 Rx Master Address  
msb  
1
0
FCC1-RxAddr[4]  
PIO  
FCC2-RxAddr[3] (master)  
PD18  
FCC2-RxAddr[0] (slave)  
FCC1-RxAddr[3]  
1
0
PIO  
FCC2-RxAddr[4] (master)  
PD29  
lsb  
FCC2-RxAddr[1] (slave)  
FCC1-RxAddr[2]  
PIO  
FCC1 Rx Slave Address  
msb  
PC6  
FCC2-RxAddr[2] (slave)  
1
0
GND  
FCC1-RxAddr[1]  
PIO  
PC12  
SAD4  
FCC2-RxAddr[3] (slave)  
1
0
GND  
FCC1-RxAddr[0]  
lsb  
PIO  
PC14  
SAD3  
FCC2-RxAddr[4] (slave)  
FCC1  
1
0
GND  
SAD2  
1
0
GND  
SAD1  
PIO  
PA5  
1
0
FCC2-RxAddr[2] (master)  
FCC2-RxAddr[1] (master)  
FCC2-RxAddr[0] (master)  
GND  
SAD0  
PIO  
PA4  
FCC2 Rx Master Address  
msb  
1
0
PIO  
PA3  
GND  
ÂSAD0  
1
0
GND  
lsb  
ÂSAD1  
1
0
FCC2 Rx Slave Address  
msb  
GND  
ÂSAD2  
1
0
GND  
ÂSAD3  
1
0
lsb  
GND  
FCC2  
ÂSAD4  
Figure 15-7. Multi-PHY Receive Address Multiplexing  
15.4.2 CMX SI1 Clock Route Register (CMXSI1CR)  
The CMX SI1 clock route register (CMXSI1CR) deÞnes the connection of SI1 to the clock  
sources that can be input from the bank of clocks.  
15-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part IV. Communications Processor Module  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
RTA1CS  
RTB1CS  
RTC1CS  
RTD1CS  
TTA1CS  
TTB1CS  
TTC1CS  
TTD1CS  
0000_0000  
R/W  
Addr  
0x11B00  
Figure 15-8. CMX SI1 Clock Route Register (CMXSI1CR)  
Table 15-3 describes CMXSI1CR Þelds.  
Table 15-3. CMXSI1CR Field Descriptions  
Bits  
Name  
Description  
0
RTA1CS  
Receive TDM A1 clock source  
0 TDM A1 receive clock is CLK1.  
1 TDM A1 receive clock is CLK19.  
1
2
3
4
5
6
7
RTB1CS  
RTC1CS  
RTD1CS  
TTA1CS  
TTB1CS  
TTC1CS  
TTD1CS  
Receive TDM B1 clock source  
0 TDM B1 receive clock is CLK3.  
1 TDM B1 receive clock is CLK9.  
Receive TDM C1 clock source  
0 TDM C1 receive clock is CLK5.  
1 TDM C1 receive clock is CLK13.  
Receive TDM D1 clock source  
0 TDM D1 receive clock is CLK7.  
1 TDM D1 receive clock is CLK15.  
Transmit TDM A1 clock source  
0 TDM A1 transmit clock is CLK2.  
1 TDM A1 transmit clock is CLK20.  
Transmit TDM B1 clock source  
0 TDM B1 transmit clock is CLK4.  
1 TDM B1 transmit clock is CLK10.  
Transmit TDM C1 clock source  
0 TDM C1 transmit clock is CLK6.  
1 TDM C1 transmit clock is CLK14.  
Transmit TDM D1 clock source  
0 TDM D1 transmit clock is CLK8.  
1 TDM D1 transmit clock is CLK16.  
15.4.3 CMX SI2 Clock Route Register (CMXSI2CR)  
The CMX SI2 clock route register (CMXSI2CR) deÞnes the connection of SI2 to the clock  
sources that can be input from the bank of clocks.  
MOTOROLA  
Chapter 15. CPM Multiplexing  
15-11  
         
Part IV. Communications Processor Module  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
RTA2CS  
RTB2CS  
RTC2CS  
RTD2CS  
TTA2CS  
TTB2CS  
TTC2CS  
TTD2CS  
0000_0000  
R/W  
Addr  
0x11B02  
Figure 15-9. CMX SI2 Clock Route Register (CMXSI2CR)  
Table 15-4 describes CMXSI2CR Þelds.  
Table 15-4. CMXSI2CR Field Descriptions  
Bits  
Name  
Description  
0
RTA2CS  
Receive TDM A2 clock source  
0 TDM A2 receive clock is CLK13.  
1 TDM A2 receive clock is CLK5.  
1
2
3
4
5
6
7
RTB2CS  
RTC2CS  
RTD2CS  
TTA2CS  
TTB2CS  
TTC2CS  
TTD2CS  
Receive TDM B2 clock source  
0 TDM B2 receive clock is CLK15.  
1 TDM B2 receive clock is CLK17.  
Receive TDM C2 clock source  
0 TDM C2 receive clock is CLK3.  
1 TDM C2 receive clock is CLK17.  
Receive TDM D2 clock source  
0 TDM D2 receive clock is CLK1.  
1 TDM D2 receive clock is CLK19.  
Transmit TDM A2 clock source  
0 TDM A2 transmit clock is CLK14.  
1 TDM A2 transmit clock is CLK6.  
Transmit TDM B2 clock source  
0 TDM B2 transmit clock is CLK16.  
1 TDM B2 transmit clock is CLK18.  
Transmit TDM C2 clock source  
0 TDM C2 transmit clock is CLK4.  
1 TDM C2 transmit clock is CLK18.  
Transmit TDM D2 clock source  
0 TDM D2 transmit clock is CLK2.  
1 TDM D2 transmit clock is CLK20.  
15.4.4 CMX FCC Clock Route Register (CMXFCR)  
The CMX FCC clock route register (CMXFCR) deÞnes the connection of the FCCs to the  
TSA and to the clock sources from the bank of clocks.  
15-12  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part IV. Communications Processor Module  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Ñ
FC1  
RF1CS  
TF1CS  
Ñ
FC2  
RF2CS  
TF2CS  
0000_0000_0000_0000  
R/W  
Addr  
Bits  
0x11B04  
16  
Ñ
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
FC3  
RF3CS  
TF3CS  
Ñ
0000_0000_0000_0000  
R/W  
Addr  
0x11B06  
Figure 15-10. CMX FCC Clock Route Register (CMXFCR)  
Table 15-5 describes CMXFCR Þelds.  
Table 15-5. CMXFCR Field Descriptions  
Bits  
Name  
Description  
0
1
Ñ
Reserved, should be cleared  
DeÞnes the FCC1 connection  
FC1  
0 FCC1 is not connected to the TSA and is either connected directly to the NMSIx pins or is not  
used. The choice of general-purpose I/O port pins versus FCCn pins is made in the parallel I/O  
control register.  
1 FCC1 is connected to the TSA of the SIs. The NMSIx pins are available for other purposes.  
2Ð4  
RF1CS Receive FCC1 clock source (NMSI mode). Ignored if FCC1 is connected to the TSA (FC1 = 1).  
000 FCC1 receive clock is BRG5.  
001 FCC1 receive clock is BRG6.  
010 FCC1 receive clock is BRG7.  
011 FCC1 receive clock is BRG8.  
100 FCC1 receive clock is CLK9.  
101 FCC1 receive clock is CLK10.  
110 FCC1 receive clock is CLK11.  
111 FCC1 receive clock is CLK12.  
5Ð7  
TF1CS  
Transmit FCC1 clock source (NMSI mode). Ignored if FCC1 is connected to the TSA (FC1 = 1).  
000 FCC1 transmit clock is BRG5.  
001 FCC1 transmit clock is BRG6.  
010 FCC1 transmit clock is BRG7.  
011 FCC1 transmit clock is BRG8.  
100 FCC1 transmit clock is CLK9.  
101 FCC1 transmit clock is CLK10.  
110 FCC1 transmit clock is CLK11.  
111 FCC1 transmit clock is CLK12.  
8
9
Ñ
Reserved, should be cleared  
FC2  
DeÞnes the FCC2 connection  
0 FCC2 is not connected to the TSA and is either connected directly to the NMSIx pins or is not  
used. The choice of general-purpose I/O port pins versus FCCn pins is made in the parallel I/O  
control register.  
1 FCC2 is connected to the TSA of the SIs. The NMSIx pins are available for other purposes.  
MOTOROLA  
Chapter 15. CPM Multiplexing  
15-13  
   
Part IV. Communications Processor Module  
Table 15-5. CMXFCR Field Descriptions (Continued)  
Bits  
Name  
Description  
10Ð12 RF2CS Receive FCC2 clock source (NMSI mode). Ignored if FCC2 is connected to the TSA (FC2 = 1).  
000 FCC2 receive clock is BRG5.  
001 FCC2 receive clock is BRG6.  
010 FCC2 receive clock is BRG7.  
011 FCC2 receive clock is BRG8.  
100 FCC2 receive clock is CLK13.  
101 FCC2 receive clock is CLK14.  
110 FCC2 receive clock is CLK15.  
111 FCC2 receive clock is CLK16.  
13Ð15 TF2CS  
Transmit FCC2 clock source (NMSI mode). Ignored if FCC2 is connected to the TSA (FC2 = 1).  
000 FCC2 transmit clock is BRG5.  
001 FCC2 transmit clock is BRG6.  
010 FCC2 transmit clock is BRG7.  
011 FCC2 transmit clock is BRG8.  
100 FCC2 transmit clock is CLK13.  
101 FCC2 transmit clock is CLK14.  
110 FCC2 transmit clock is CLK15.  
111 FCC2 transmit clock is CLK16.  
16  
17  
Ñ
Reserved, should be cleared  
FC3  
DeÞnes the FCC3 connection  
0 FCC3 is not connected to the TSA and is either connected directly to the NMSIx pins or is not  
used. The choice of general-purpose I/O port pins versus FCCn pins is made in the parallel I/O  
control register.  
1 FCC3 is connected to the TSA of the SIs. The NMSIx pins are available for other purposes.  
18Ð20 RF3CS Receive FCC3 clock source (NMSI mode). Ignored if FCC3 is connected to the TSA (FC3 = 1).  
000 FCC3 receive clock is BRG5.  
001 FCC3 receive clock is BRG6.  
010 FCC3 receive clock is BRG7.  
011 FCC3 receive clock is BRG8.  
100 FCC3 receive clock is CLK13.  
101 FCC3 receive clock is CLK14.  
110 FCC3 receive clock is CLK15.  
111 FCC3 receive clock is CLK16.  
21Ð23 TF3CS  
Transmit FCC3 clock source (NMSI mode). Ignored if FCC3 is connected to the TSA (FC3 = 1).  
000 FCC3 transmit clock is BRG5.  
001 FCC3 transmit clock is BRG6.  
010 FCC3 transmit clock is BRG7.  
011 FCC3 transmit clock is BRG8.  
100 FCC3 transmit clock is CLK13.  
101 FCC3 transmit clock is CLK14.  
110 FCC3 transmit clock is CLK15.  
111 FCC3 transmit clock is CLK16.  
24Ð31  
Ñ
Reserved, should be cleared  
15.4.5 CMX SCC Clock Route Register (CMXSCR)  
The CMX SCC clock route register (CMXSCR) deÞnes the connection of the SCCs to the  
TSA and to the clock sources from the bank of clocks. This register also enables the use of  
the external grant pin.  
15-14  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part IV. Communications Processor Module  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
GR1 SC1  
RS1CS  
TS1CS  
GR2 SC2  
RS2CS  
TS2CS  
0000_0000_0000_0000  
R/W  
Addr  
Bits  
0x11B08  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
GR3 SC3  
RS3CS  
TS3CS  
GR4 SC4  
RS4CS  
TS4CS  
0000_0000_0000_0000  
R/W  
Addr  
0x11B0A  
Figure 15-11. CMX SCC Clock Route Register (CMXSCR)  
Table 15-6 describes CMXSCR Þelds.  
Table 15-6. CMXSCR Field Descriptions  
Bits  
Name  
GR1  
Description  
0
Grant support of SCC1  
0 SCC1 transmitter does not support the grant mechanism. The grant is always asserted  
internally.  
1 SCC1 transmitter supports the grant mechanism as determined by the GMx bit of a serial  
device channel.  
1
SC1  
SCC1 connection  
0 SCC1 is not connected to the TSA and is either connected directly to the NMSIx pins or is not  
used. The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O  
control register.  
1 SCC1 is connected to TSA of the SIs. The NMSIx pins are available for other purposes.  
2Ð4  
RS1CS  
Receive SCC1 clock source (NMSI mode). Ignored if SCC1 is connected to the TSA (SC1 = 1).  
000 SCC1 receive clock is BRG1.  
001 SCC1 receive clock is BRG2.  
010 SCC1 receive clock is BRG3.  
011 SCC1 receive clock is BRG4.  
100 SCC1 receive clock is CLK11.  
101 SCC1 receive clock is CLK12.  
110 SCC1 receive clock is CLK3.  
111 SCC1 receive clock is CLK4.  
5Ð7  
TS1CS  
Transmit SCC1 clock source (NMSI mode). Ignored if SCC1 is connected to the TSA (SC1 = 1).  
000 SCC1 transmit clock is BRG1.  
001 SCC1 transmit clock is BRG2.  
010 SCC1 transmit clock is BRG3.  
011 SCC1 transmit clock is BRG4.  
100 SCC1 transmit clock is CLK11.  
101 SCC1 transmit clock is CLK12.  
110 SCC1 transmit clock is CLK3.  
111 SCC1 transmit clock is CLK4.  
MOTOROLA  
Chapter 15. CPM Multiplexing  
15-15  
   
Part IV. Communications Processor Module  
Table 15-6. CMXSCR Field Descriptions (Continued)  
Bits  
Name  
GR2  
Description  
8
Grant support of SCC2  
0 SCC2 transmitter does not support the grant mechanism. The grant is always asserted  
internally.  
1 SCC2 transmitter supports the grant mechanism as determined by the GMx bit of a serial  
device channel.  
9
SC2  
SCC2 connection  
0 SCC2 is not connected to the TSA and is either connected directly to the NMSIx pins or is not  
used. The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O  
control register.  
1 SCC2 is connected to TSA of the SIs. The NMSIx pins are available for other purposes.  
10Ð12 RS2CS  
Receive SCC2 clock source (NMSI mode). Ignored if SCC2 is connected to the TSA (SC2 = 1).  
000 SCC2 receive clock is BRG1.  
001 SCC2 receive clock is BRG2.  
010 SCC2 receive clock is BRG3.  
011 SCC2 receive clock is BRG4.  
100 SCC2 receive clock is CLK11.  
101 SCC2 receive clock is CLK12.  
110 SCC2 receive clock is CLK3.  
111 SCC2 receive clock is CLK4.  
13Ð15 TS2CS  
Transmit SCC2 clock source (NMSI mode). Ignored if SCC2 is connected to the TSA (SC2 = 1).  
000 SCC2 transmit clock is BRG1.  
001 SCC2 transmit clock is BRG2.  
010 SCC2 transmit clock is BRG3.  
011 SCC2 transmit clock is BRG4.  
100 SCC2 transmit clock is CLK11.  
101 SCC2 transmit clock is CLK12.  
110 SCC2 transmit clock is CLK3.  
111 SCC2 transmit clock is CLK4.  
16  
17  
GR3  
SC3  
Grant support of SCC3  
0 SCC3 transmitter does not support the grant mechanism. The grant is always asserted  
internally.  
1 SCC3 transmitter supports the grant mechanism as determined by the GMx bit of a serial  
device channel.  
SCC3 connection  
0 SCC3 is not connected to the TSA and is either connected directly to the NMSIx pins or is not  
used. The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O  
control register.  
1 SCC3 is connected to TSA of the SIs. The NMSIx pins are available for other purposes.  
18Ð20 RS3CS  
Receive SCC3 clock source (NMSI mode). Ignored if SCC3 is connected to the TSA (SC3 = 1).  
000 SCC3 receive clock is BRG1.  
001 SCC3 receive clock is BRG2.  
010 SCC3 receive clock is BRG3.  
011 SCC3 receive clock is BRG4.  
100 SCC3 receive clock is CLK5.  
101 SCC3 receive clock is CLK6.  
110 SCC3 receive clock is CLK7.  
111 SCC3 receive clock is CLK8.  
15-16  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part IV. Communications Processor Module  
Table 15-6. CMXSCR Field Descriptions (Continued)  
Bits  
Name  
Description  
21Ð23 TS3CS  
Transmit SCC3 clock source (NMSI mode). Ignored if SCC3 is connected to the TSA (SC3 = 1).  
000 SCC3 transmit clock is BRG1.  
001 SCC3 transmit clock is BRG2.  
010 SCC3 transmit clock is BRG3.  
011 SCC3 transmit clock is BRG4.  
100 SCC3 transmit clock is CLK5.  
101 SCC3 transmit clock is CLK6.  
110 SCC3 transmit clock is CLK7.  
111 SCC3 transmit clock is CLK8.  
24  
25  
GR4  
SC4  
Grant support of SCC4  
0 SCC4 transmitter does not support the grant mechanism. The grant is always asserted  
internally.  
1 SCC4 transmitter supports the grant mechanism as determined by the GMx bit of a serial  
device channel.  
SCC4 connection  
0 SCC4 is not connected to the TSA and is either connected directly to the NMSIx pins or is not  
used. The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O  
control register.  
1 SCC4 is connected to TSA of the SIs. The NMSIx pins are available for other purposes.  
26Ð28 RS4CS  
Receive SCC4 clock source (NMSI mode). Ignored if SCC4 is connected to the TSA (SC4 = 1).  
000 SCC4 receive clock is BRG1.  
001 SCC4 receive clock is BRG2.  
010 SCC4 receive clock is BRG3.  
011 SCC4 receive clock is BRG4.  
100 SCC4 receive clock is CLK5.  
101 SCC4 receive clock is CLK6.  
110 SCC4 receive clock is CLK7.  
111 SCC4 receive clock is CLK8  
29Ð31 TS4CS  
Transmit SCC4 clock source (NMSI mode). Ignored if SCC4 is connected to the TSA (SC4 = 1).  
000 SCC4 transmit clock is BRG1.  
001 SCC4 transmit clock is BRG2.  
010 SCC4 transmit clock is BRG3.  
011 SCC4 transmit clock is BRG4.  
100 SCC4 transmit clock is CLK5.  
101 SCC4 transmit clock is CLK6.  
110 SCC4 transmit clock is CLK7.  
111 SCC4 transmit clock is CLK8  
15.4.6 CMX SMC Clock Route Register (CMXSMR)  
The CMX SMC clock route register (CMXSMR) deÞnes the connection of the SMCs to the  
TSA and to the clock sources from the bank of clocks.  
MOTOROLA  
Chapter 15. CPM Multiplexing  
15-17  
     
Part IV. Communications Processor Module  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
SMC1  
Ñ
SMC1CS  
SMC2  
Ñ
SMC2CS  
0000_0000  
R/W  
Addr  
0x11B0C  
Figure 15-12. CMX SMC Clock Route Register (CMXSMR)  
Table 15-7 describes CMXSMR Þelds.  
Table 15-7. CMXSMR Field Descriptions  
Name  
Name  
SMC1  
Description  
0
SMC1 connection  
0 SMC1 is not connected to the TSA and is either connected directly to the NMSIx pins or is not  
used. The choice of general-purpose I/O port pins versus SMCn pins is made in the parallel I/O  
control register.  
1 SMC1 is connected to the TSA of the SIs. The NMSIx pins are available for other purposes.  
1
Ñ
Reserved, should be cleared  
2Ð3  
SMC1CS SMC1 clock source (NMSI mode). SMC1 can take its clocks from one of the two BRGs or one of  
two pins from the bank of clocks. However, the SMC1 transmit and receive clocks must be the  
same when it is connected to the NMSI.  
00 SMC1 transmit and receive clocks are BRG1.  
01 SMC1 transmit and receive clocks are BRG7.  
10 SMC1 transmit and receive clocks are CLK7.  
11 SMC1 transmit and receive clocks are CLK9.  
4
SMC2  
SMC2 connection  
0 SMC2 is not connected to the TSA and is either connected directly to the NMSIx pins or is not  
used. The choice of general-purpose I/O port pins versus SMCn pins is made in the parallel I/O  
control register.  
1 SMC2 is connected to the TSA of the SIs. The NMSIx pins are available for other purposes.  
5
Ñ
Reserved, should be cleared  
6Ð7  
SMC2CS SMC2 clock source (NMSI mode). SMC2 can take its clocks from one of the eight BRGs or one of  
eight pins from the bank of clocks. However, the SMC2 transmit and receive clocks must be the  
same when it is connected to the NMSI.  
00 SMC2 transmit and receive clocks are BRG2.  
01 SMC2 transmit and receive clocks are BRG8.  
10 SMC2 transmit and receive clocks are CLK19.  
11 SMC2 transmit and receive clocks are CLK20.  
15-18  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Chapter 16  
Baud-Rate Generators (BRGs)  
160  
1T60 he CPM contains eight independent, identical baud-rate generators (BRGs) that can be  
used with the FCCs, SCCs, and SMCs. The clocks produced by the BRGs are sent to the  
bank-of-clocks selection logic, where they can be routed to the controllers. In addition, the  
output of a BRG can be routed to a pin to be used externally. The following is a list of  
BRGsÕ main features:  
¥
¥
¥
¥
¥
¥
Eight independent and identical BRGs  
On-the-ßy changes allowed  
Each BRG can be routed to one or more FCCs, SCCs, or SMCs  
A 16x divider option allows slow baud rates at high system frequencies  
Each BRG contains an autobaud support option  
Each BRG output can be routed to a pin (BRGOn)  
Figure 16-1 shows a BRG.  
EXTC  
DIV 16  
CD[0Ð11]  
CLK Pin x  
Clock  
Prescaler  
12-Bit Counter  
1Ð4,096  
BRGOn Clock  
Divide by  
1 or 16  
To Pin and/or  
Bank of Clocks  
CLK Pin y  
Source  
MUX  
BRGCLK  
ATB  
Autobaud  
Control  
RXDn  
BRGn  
Figure 16-1. Baud-Rate Generator (BRG) Block Diagram  
MOTOROLA  
Chapter 16. Baud-Rate Generators (BRGs)  
16-1  
     
Part IV. Communications Processor Module  
Each BRG clock source can be BRGCLK, or a choice of two external clocks (selected in  
BRGCx[EXTC]). The BRGCLK is an internal signal generated in the MPC8260 clock  
2
synthesizer speciÞcally for the BRGs, the SPI, and the I C internal BRG. Alternatively,  
external clock pins can be conÞgured as clock sources. The external source option allows  
ßexible baud-rate frequency generation, independent of the system frequency.Additionally,  
the external source option allows a single external frequency to be the source for multiple  
BRGs. The external source signals are not synchronized internally before being used by the  
BRG.  
The BRG provides a divide-by-16 option (BRGCx[DIV16]) and a 12-bit prescaler  
(BRGCx[CD]) to divide the source clock frequency. The combined source-clock divide  
factor can be changed on-the-ßy; however, two changes should not occur within two source  
clock periods.  
The prescaler output is sent internally to the bank of clocks and can also be output  
externally on BRGOn through the parallel I/O ports. If the BRG divides the clock by an  
even value, the transitions of BRGOn always occur on the falling edge of the source clock.  
If the divide factor is odd, the transitions alternate between the falling and rising edges of  
the source clock. Additionally, the output of the BRG can be sent to the autobaud control  
block.  
16.1 BRG ConÞguration Registers 1Ð8 (BRGCx)  
The BRG conÞguration registers (BRGCx) are shown in Figure 16-2. A reset disables the  
BRG and drives the BRGO output clock high. The BRGC can be written at any time with  
no need to disable the SCCs or external devices that are connected to BRGO. ConÞguration  
changes occur at the end of the next BRG clock cycle (no spikes occur on the BRGO output  
clock). BRGC can be changed on-the-ßy; however, two changes should not occur within a  
time equal to two source clock periods.  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field  
Reset  
R/W  
Ñ
RST EN  
0000_0000_0000_0000  
R/W  
Addr  
0x119F0 (BRGC1), 0x119F4 (BRGC2), 0x119F8 (BRGC3), 0x119FC (BRGC4),  
0x115F0 (BRGC5), 0x115F4 (BRGC6), 0x115F8 (BRGC7), 0x115FC (BRGC8)  
Bit  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
EXTC  
ATB  
CD  
DIV16  
0000_0000_0000_0000  
R/W  
Addr  
0x119F22 (BRGC1), 0x119F6 (BRGC2), 0x119FA (BRGC3), 0x119FE (BRGC4),  
0x115F2 (BRGC5), 0x115F6 (BRGC6), 0x115FA (BRGC7), 0x115FE (BRGC8)  
Figure 16-2. Baud-Rate Generator Configuration Registers (BRGCx)  
16-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part IV. Communications Processor Module  
Table 16-1 describes the BRGCx Þelds.  
Table 16-1. BRGCx Field Descriptions  
Bits Name  
Description  
0Ð13  
14  
Ñ
Reserved, should be cleared.  
RST  
Reset BRG. Performs a software reset of the BRG identical to that of an external reset. A reset  
disables the BRG and drives BRGO high. This is externally visible only if BRGO is connected to the  
corresponding parallel I/O pin.  
0 Enable the BRG.  
1 Reset the BRG (software reset).  
15  
EN  
Enable BRG count. Used to dynamically stop the BRG from countingÑuseful for low-power modes.  
0 Stop all clocks to the BRG.  
1 Enable clocks to the BRG.  
16Ð17 EXTC External clock source. Selects the BRG input clock. See Table 16-2.  
00 The BRG input clock comes from the BRGCLK (internal clock generated from the CPM clock); see  
Section 9.8, ÒSystem Clock Control Register (SCCR).Ó  
01 If BRG1, 2, 5, 6: The BRG input clock comes from the CLK3 pin.  
If BRG3, 4, 7, 8: The BRG input clock comes from the CLK9 pin  
10 If BRG1, 2, 5, 6: The BRG input clock comes from the CLK5 pin.  
If BRG3, 4, 7, 8: The BRG input clock comes from the CLK15 pin  
11 Reserved.  
18  
ATB  
Autobaud. Selects autobaud operation of the BRG on the corresponding RXD. ATB must remain zero  
until the SCC receives the three Rx clocks.Then the user must set ATB to obtain the correct baud rate.  
After the baud rate is obtained and locked, it is indicated by setting AB in the UART event register.  
0 Normal operation of the BRG.  
1 When RXD goes low, the BRG determines the length of the start bit and synchronizes the BRG to  
the actual baud rate.  
19Ð30 CD  
Clock divider. CD presets an internal 12-bit counter that is decremented at the DIV16 output rate.  
When the counter reaches zero, it is reloaded with CD. CD = 0xFFF produces the minimum clock rate  
for BGRO (divide by 4,096); CD = 0x000 produces the maximum rate (divide by 1). When dividing by  
an odd number, the counter ensures a 50% duty cycle by asserting the terminal count once on clock  
low and next on clock high. The terminal count signals counter expiration and toggles the clock. See  
Section 16.3, ÒUART Baud Rate Examples.Ó  
31  
DIV16 Divide-by-16. Selects a divide-by-1 or divide-by-16 prescaler before reaching the clock divider. See  
Section 16.3, ÒUART Baud Rate Examples.Ó  
0 Divide by 1.  
1 Divide by 16.  
Table 16-2 shows the possible external clock sources for the BRGs.  
MOTOROLA  
Chapter 16. Baud-Rate Generators (BRGs)  
16-3  
 
Part IV. Communications Processor Module  
Table 16-2. BRG External Clock Source Options  
CLK  
BRG  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20  
BRG1  
BRG2  
BRG3  
BRG4  
BRG5  
BRG6  
BRG7  
BRG8  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
16.2 Autobaud Operation on a UART  
During the autobaud process, a UART deduces the baud rate of its received character stream  
by examining the received pattern and its timing. A built-in autobaud control function  
automatically measures the length of a start bit and modiÞes the baud rate accordingly.  
If the autobaud bit BRGCx[ATB] is set, the autobaud control function starts searching for  
a low level on the corresponding RXDn input, which it assumes marks the beginning of a  
start bit, and begins counting the start bit length. During this time, the BRG output clock  
toggles for 16 BRG clock cycles at the BRG source clock rate and then stops with BRGOn  
in the low state.  
When RXDn goes high again, the autobaud control block rewrites BRGCx[CD, DIV16] to  
the divide ratio found, which at high baud rates may not be exactly the Þnal rate desired (for  
example, 56,600 may result rather than 57,600). An interrupt can be enabled in the UART  
SCC event register to report that the autobaud controller rewrote BRGCx. The interrupt  
handler can then adjust BRGCx[CD, DIV16] (see Table 16-3) for accuracy before the Þrst  
character is fully received, ensuring that the UART recognizes all characters.  
After a full character is received, the software can verify that the character matches a  
predeÞned value (such as ÔaÕ or ÔAÕ). Software should then check for other characters (such  
as ÔtÕ or ÔTÕ) and program the preferred parity mode in the UARTÕs protocol-speciÞc mode  
register (PSMR).  
Note that the SCC associated with this BRG must be programmed to UART mode and  
select the 16´ option for TDCR and RDCR in the general SCC mode register low. Input  
frequencies such as 1.8432, 3.68, 7.36, and 14.72 MHz should be used. The SCC  
performing the autobaud function must be connected to that SCCÕs BRG; that is, SCC2  
must be clocked by BRG2, and so on.  
Also, to detect an autobaud lock and generate an interrupt, the SCC must receive three full  
Rx clocks from the BRG before the autobaud process begins. To do this, Þrst clear  
BRGCx[ATB] and enable the BRG Rx clock to the highest frequency. Then, immediately  
before the autobaud process starts (after device initialization), set BRGCx[ATB].  
16-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
16.3 UART Baud Rate Examples  
For synchronous communication using the internal BRG, the BRGO output clock must not  
exceed the system frequency divided by 2. So, with a 66-MHz system frequency, the  
maximum BRGO rate is 33 MHz. Program the UART to 16´ oversampling when using the  
SCC as a UART. Rates of 8´ and 32´ are also available. Assuming 16´ oversampling is  
chosen in the UART, the maximum data rate is 66 MHz Ö 16 = 4.125 Mbps. Keeping the  
above in mind, use the following formula to calculate the bit rate based on a particular BRG  
conÞguration for a UART:  
BRGCLK or External Clock Source  
Async Baud Rate = ------------------------------------------------------------------------------------------------------------------------------------------------  
(Prescale Divider) · (Clock Divider + 1) · (Sampling Rate)  
BRGCx[EXTC]  
= --------------------------------------------------------------------------------------------------------------------------------------------------------  
(BRGCx[DIV16]) · (BRGCx[CD] + 1) · (GSMRx_L[xDCR])  
Table 16-3 lists typical bit rates of asynchronous communication. Note that here the  
internal clock rate is assumed to be 16´ the baud rate; that is, GSMRx_L[TDCR] =  
GSMRx_L[RDCR] = 0b10.  
Table 16-3. Typical Baud Rates for Asynchronous Communication  
Using 66-MHz System Clock  
Baud Rate  
BRGCx[DIV16]  
BRGCx[CD]  
Actual Frequency (Hz)  
75  
150  
1
1
1
1
0
0
0
0
0
0
0
0
0
3436  
1718  
858  
429  
3436  
1718  
858  
429  
214  
106  
71  
75.01  
149.98  
300.13  
599.56  
1200.2  
2399.7  
4802.1  
9593.0  
19,186  
38,551  
57,292  
114,583  
458,333  
300  
600  
1200  
2400  
4800  
9600  
19,200  
38,400  
57,600  
115,200  
460,000  
35  
8
MOTOROLA  
Chapter 16. Baud-Rate Generators (BRGs)  
16-5  
   
Part IV. Communications Processor Module  
For synchronous communication, the internal clock is identical to the baud-rate output. To  
get the preferred rate, select the system clock according to the following:  
BRGCLK or External Clock Source  
Sync Baud Rate = --------------------------------------------------------------------------------------------------  
(Prescale Divider) · (Clock Divider + 1)  
BRGCx[EXTC]  
= ------------------------------------------------------------------------------------------------  
(BRGCx[DIV16]) · (BRGCx[CD] + 1)  
For example, to get a rate of 64 kbps, the system clock can be 24.96 MHz,  
BRGCx[DIV16] = 0, and BRGCx[CD] = 389.  
16-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Chapter 17  
Timers  
170  
1T70 he CPM includes four identical 16-bit general-purpose timers or two 32-bit timers. Each  
general-purpose timer consists of a timer mode register (TMR), a timer capture register  
(TCR), a timer counter (TCN), a timer reference register (TRR), a timer event register  
(TER), and a timer global conÞguration register (TGCR). The TMRs contain the prescaler  
values programmed by the user.  
Figure 17-1 shows the timer block diagram.  
General  
System Clock  
TGCR  
Global Configuration Register  
TGATE1  
TGATE2  
TER1  
TMR1  
Timer Event Register  
Mode Register  
Timer  
Clock  
Generator  
TIN1  
TIN2  
Prescaler  
Mode Bits  
TIN3  
TIN4  
Clock  
Divider  
TCN1  
TRR1  
TCR1  
Timer Counter (TCN)  
Capture  
Detection  
Reference Register  
Capture Register  
TOUT1  
TOUT2  
TOUT3  
TOUT4  
Timer1  
Timer2  
Timer3  
Timer4  
Figure 17-1. Timer Block Diagram  
Pin assignments for TINx, TGATEx, and TOUTx are described in Section 35.5, ÒPorts  
Tables.Ó  
MOTOROLA  
Chapter 17. Timers  
17-1  
         
Part IV. Communications Processor Module  
17.1 Features  
The key features of the timer include the following:  
¥
¥
¥
¥
¥
¥
¥
¥
¥
The maximum input clock is the bus clock  
Maximum period of 4 seconds (at 66 MHz)  
16-nanosecond resolution (at 66 MHz)  
Programmable sources for the clock input  
Input capture capability  
Output compare with programmable mode for the output pin  
Two timers cascade internally or externally to form a 32-bit timer  
Free run and restart modes  
Functional compatibility with timers on the MC68360 and MPC860  
17.2 General-Purpose Timer Units  
The clock input to the prescaler can be selected from three sources:  
¥
¥
¥
The bus clock (CLKIN)  
The bus clock divided by 16 (CLKIN/16)  
The corresponding TINx, programmed in the parallel port registers  
The general system clock is generated in the clock synthesizer and defaults to the system  
frequency. However, the general system clock has the option to be divided before it leaves  
the clock synthesizer. This mode, called slow go, is used to save power. Whatever the  
resulting frequency of the general system clock, the user can either choose that frequency  
or the frequency divided by 16 as the input to the prescaler of each timer. Alternatively, the  
user may prefer TINx to be the clock source. TINx is internally synchronized to the internal  
clock. If the user has chosen to internally cascade two 16-bit timers to a 32-bit timer, then  
a timer can use the clock generated by the output of another timer.  
The clock input source is selected by the corresponding TMR[ICLK] bits. The prescaler is  
programmed to divide the clock input by values from 1 to 256 and the output of the  
prescaler is used as an input to the 16-bit counter. The best resolution of the timer is one  
clock cycle (16 ns at 66 MHz). The maximum period (when the reference value is all ones)  
is 268,435,456 cycles (4 seconds at 66 MHz).  
Each timer can be conÞgured to count until a reference is reached and then either begin a  
new time count immediately or continue to run. The FRR bit of the corresponding TMR  
selects each mode. Upon reaching the reference value, the corresponding TER bit is set and  
an interrupt is issued if TMR[ORI] = 1. The timers can output a signal on the timer outputs  
(TOUT1ÐTOUT4) when the reference value is reached (selected by the corresponding  
TMR[OM]). This signal can be an active-low pulse or a toggle of the current output. The  
17-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
           
Part IV. Communications Processor Module  
output can also be connected internally to the input of another timer, resulting in a 32-bit  
timer.  
In addition, each timer has a 16-bit TCR used to latch the value of the counter when a  
deÞned transition of TIN1, TIN2, TIN3, or TIN4 is sensed by the corresponding input  
capture edge detector. The type of transition triggering the capture is selected by the  
corresponding TMR[CE] bits. Upon a capture or reference event, the corresponding TER  
bit is set and a maskable interrupt request is issued to the interrupt controller. The timers  
may be gated/restarted by an external gate signal. There are two gate signalsÑTGATE1  
controls timer 1 and/or 2 and TGATE2 controls timer 3 and/or 4. Normal gate mode enables  
the count on a falling edge of TGATEx and disables the count on the rising edge of  
TGATEx. This mode allows the timer to count conditionally, based on the state of TGATEx.  
The restart gate mode performs the same function as normal mode, except it also resets the  
counter on the falling edge of TGATEx. This mode has applications in pulse interval  
measurement and bus monitoring as follows:  
¥
Pulse measurementÑThe restart gate mode can measure a low TGATEx. The rising  
edge of TGATEx completes the measurement and if TGATEx is connected  
externally to TINx, it causes the timer to capture the count value and generate a  
rising-edge interrupt.  
¥
Bus monitoringÑThe restart gate mode can detect a signal that is abnormally stuck  
low. The bus signal should be connected to TGATEx. The timer count is reset on the  
falling edge of the bus signal and if the bus signal does not go high again within the  
number of user-deÞned clocks, an interrupt can be generated.  
The gate function is enabled in the TMR; the gate operating mode is selected in the TGCR.  
NOTE  
TGATEx is internally synchronized to the system clock. If  
TGATEx meets the asynchronous input setup time, the counter  
begins counting after one system clock when working with the  
internal clock.  
17.2.1 Cascaded Mode  
In this mode, two 16-bit timers can be internally cascaded to form a 32-bit counter. Timer  
1 may be internally cascaded to timer 2, and timer 3 can be internally cascaded to timer 4.  
Because the decision to cascade timers is made independently, the user can select two 16-  
bit timers or one 32-bit timer. TGCR is used to put the timers into cascaded mode, as shown  
in Figure 17-2.  
MOTOROLA  
Chapter 17. Timers  
17-3  
       
Part IV. Communications Processor Module  
Timer1  
Timer2  
Clock  
Clock  
TRR, TCR, TCN connected to D[0Ð15]  
TRR, TCR, TCN connected to D[16Ð31]  
Capture  
Timer3  
TRR, TCR, TCN connected to D[0Ð15]  
Capture  
Timer4  
TRR, TCR, TCN connected to D[16Ð31]  
Figure 17-2. Timer Cascaded Mode Block Diagram  
If TGCR[CAS] = 1, the two timers function as a 32-bit timer with a 32-bit TRR, TCR, and  
TCN. In this case, TMR1 and/or TMR3 are ignored, and the modes are deÞned using TMR2  
and/or TMR4. The capture is controlled from TIN2 or TIN4 and the interrupts are generated  
from TER2 or TER4. In cascaded mode, the combined TRR, TCR, and TCN must be  
referenced with 32-bit bus cycles.  
17.2.2 Timer Global ConÞguration Registers (TGCR1 and TGCR2)  
The timer global conÞguration registers (TGCR1 and TGCR2), shown in Figure 17-3 and  
Figure 17-4, contain conÞguration parameters used by the timers. These registers allow  
simultaneous starting and stopping of a pair of timers (1 and 2 or 3 and 4) if one bus cycle  
is used.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
CAS2  
Ñ
STP2  
RST2  
GM1  
Ñ
STP1  
RST1  
0000_0000  
R/W  
Addr  
0x10D80  
Figure 17-3. Timer Global Configuration Register 1 (TGCR1)  
Table 17-1 describes TGCR1 Þelds.  
Table 17-1. TGCR1 Field Descriptions  
Bits  
Name  
Description  
0
CAS2 Cascade timers.  
0 Normal operation.  
1 Timers 1 and 2 cascade to form a 32-bit timer.  
1
2
Ñ
Reserved, should be cleared.  
STP 2 Stop timer.  
0 Normal operation.  
1 Reduce power consumption of the timer. This bit stops all clocks to the timer, except the clock  
from the internal bus interface, which allows the user to read and write timer registers.The clocks  
to the timer remain stopped until the user clears this bit or a hardware reset occurs.  
17-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
             
Part IV. Communications Processor Module  
Table 17-1. TGCR1 Field Descriptions (Continued)  
Bits  
Name  
Description  
3
RST2 Reset timer.  
0 Reset the corresponding timer (a software reset is identical to an external reset).  
1 Enable the corresponding timer if the STP bit is cleared.  
4
GM1 Gate mode for TGATE1. This bit is valid only if the gate function is enabled in TMR1 or TMR2.  
0 Restart gate mode. TGATE1 is used to enable/disable count. A falling TGATE1 enables and  
restarts the count and a rising edge of TGATE1 disables the count.  
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE1 does not  
restart the count value in TCN.  
5
6
Ñ
Reserved, should be cleared.  
STP1 Stop timer.  
0 Normal operation.  
1 Reduce power consumption of the timer. This bit stops all clocks to the timer, except the clock  
from the internal bus interface, which allows the user to read and write timer registers.The clocks  
to the timer remain stopped until the user clears this bit or a hardware reset occurs.  
7
RST1 Reset timer.  
0 Reset the corresponding timer (a software reset is identical to an external reset).  
1 Enable the corresponding timer if STP = 0.  
The TGCR2 register is shown in Figure 17-4.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
CAS4  
Ñ
STP4  
RST4  
GM2  
Ñ
STP3  
RST3  
0000_0000  
R/W  
Addr  
0x10D84  
Figure 17-4. Timer Global Configuration Register 2 (TGCR2)  
Table 17-2 describes TGCR2 Þelds.  
Table 17-2. TGCR2 Field Descriptions  
Bit  
Name  
Description  
0
CAS4 Cascade timers.  
0 Normal operation.  
1 Timers 3 and 4 cascades to form a 32-bit timer.  
1
2
Ñ
Reserved, should be cleared.  
STP 4 Stop timer.  
0 Normal operation.  
1 Reduce power consumption of the timer. This bit stops all clocks to the timer, except the clock  
from the internal bus interface, which allows the user to read and write timer registers.The clocks  
to the timer remain stopped until the user clears this bit or a hardware reset occurs.  
3
RST4 Reset timer.  
0 Reset the corresponding timer (a software reset is identical to an external reset).  
1 Enable the corresponding timer if the STP bit is cleared.  
MOTOROLA  
Chapter 17. Timers  
17-5  
   
Part IV. Communications Processor Module  
Table 17-2. TGCR2 Field Descriptions (Continued)  
Bit  
Name  
Description  
4
GM2 Gate mode for TGATE2. This bit is valid only if the gate function is enabled in TMR3 or TMR4.  
0 Restart gate mode. TGATE2 is used to enable/disable the count. The falling edge of TGATE2  
enables and restarts the count and the rising edge of TGATE2 disables the count.  
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE2 does not  
restart the count value in TCN.  
5
6
Ñ
Reserved, should be cleared.  
STP3 Stop timer.  
0 Normal operation.  
1 Reduce power consumption of the timer. This bit stops all clocks to the timer, however it is  
possible to read the values while the clock is stopped. The clocks to the timer remain stopped  
until the user clears this bit or a hardware reset occurs.  
7
RST3 Reset timer.  
0 Reset the corresponding timer (a software reset is identical to an external reset).  
1 Enable the corresponding timer if STP = 0.  
17.2.3 Timer Mode Registers (TMR1ÐTMR4)  
The four timer mode registers (TMR1ÐTMR4) are shown in Figure 17-5.  
Erratic behavior may occur if TGCR1 and TGCR2 are not initialized before the TMRs.  
Only TGCR[RST] can be modiÞed at any time.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
PS  
CE  
OM ORI FRR  
ICLK  
GE  
0000_0000_0000_0000  
R/W  
Addr  
0x10D90 (TMR1); 0x10D92 (TMR2); 0x10DA0 (TMR3); 0x10DA2 (TMR4)  
Figure 17-5. Timer Mode Registers (TMR1ÐTMR4)  
Table 17-3 describes TMR1ÐTMR4 register Þelds.  
Table 17-3. TMRIÐTMR4 Field Descriptions  
Bits Name  
Description  
0Ð7  
8Ð9  
PS  
CE  
Prescaler value. The prescaler is programmed to divide the clock input by values from 1 to 256. The  
value 00000000 divides the clock by 1 and 11111111 divides the clock by 256.  
Capture edge and enable interrupt.  
00 Disable interrupt on capture event; capture function is disabled.  
01 Capture on rising TINx edge only and enable interrupt on capture event.  
10 Capture on falling TINx edge only and enable interrupt on capture event.  
11 Capture on any TINx edge and enable interrupt on capture event.  
17-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part IV. Communications Processor Module  
Table 17-3. TMRIÐTMR4 Field Descriptions (Continued)  
Bits Name  
Description  
10  
OM Output mode  
0 Active-low pulse on TOUTx for one timer input clock cycle as deÞned by the ICLK bits. Thus,  
TOUTx may be low for one general system clock period, one general system clock/16 period, or  
one TINx clock cycle period. TOUTx changes occur on the rising edge of the system clock.  
1 Toggle TOUTx. TOUTx changes occur on the rising edge of the system clock.  
11  
12  
ORI Output reference interrupt enable.  
0 Disable interrupt for reference reached (does not affect interrupt on capture function).  
1 Enable interrupt upon reaching the reference value.  
FRR Free run/restart.  
0 Free run. The timer count continues to increment after the reference value is reached.  
1 Restart. The timer count is reset immediately after the reference value is reached.  
13Ð14 ICLK Input clock source for the timer.  
00 Internally cascaded input. For TMR1, the timer 1 input is the output of timer 2. For TMR3, the  
timer 3 input is the output of timer 4. For TMR2 and TMR4, this selection means no input clock is  
provided to the timer.  
01 Internal general system clock.  
10 Internal general system clock divided by 16.  
11 Corresponding TINx: TIN1, TIN2, TIN3, or TIN4 (falling edge).  
15  
GE  
Gate enable.  
0 TGATEx is ignored.  
1 TGATEx is used to control the timer.  
17.2.4 Timer Reference Registers (TRR1ÐTRR4)  
Each timer reference register (TRR1ÐTRR4), shown in Figure 17-6, contains the timeoutÕs  
reference value. The reference value is not reached until TCNx increments to equal the  
timeout reference value.  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field  
Reset  
R/W  
Timeout reference value  
0xFFFF  
R/W  
Addr  
0x10D94 (TRR1), 0x10D96 (TRR2), 0x10DA4 (TRR3), 0x10DA6 (TRR4)  
Figure 17-6. Timer Reference Registers (TRR1ÐTRR4)  
MOTOROLA  
Chapter 17. Timers  
17-7  
       
Part IV. Communications Processor Module  
17.2.5 Timer Capture Registers (TCR1ÐTCR4)  
Each timer capture register (TCR1ÐTCR4), shown in Figure 17-7, is used to latch the value  
of the counter according to TMRx[CE].  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field  
Reset  
R/W  
Latched counter value  
0x0000  
R/W  
Addr  
0x10D98 (TCR1), 0x10D9A (TCR2), 0x10DA8 (TCR3), 0x10DAA (TCR4)  
Figure 17-7. Timer Capture Registers (TCR1ÐTCR4)  
17.2.6 Timer Counters (TCN1ÐTCN4)  
Each timer counter register (TCN1ÐTCN4), shown in Figure 17-8, is an up-counter. A read  
cycle to TCNx yields the current value of the timer but does not affect the counting  
operation. A write cycle to TCNx sets the register to the written value, thus causing its  
corresponding prescaler, TMRx[PS], to be reset.  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field  
Reset  
R/W  
Up counter  
0x0000  
R/W  
Addr  
0x10D9C (TCN1), 0x10D9E (TCN2), 0x10DAC (TCN3), 0x10DAE (TCN4)  
Figure 17-8. Timer Counter Registers (TCN1ÐTCN4)  
Note that the counter registers may not be updated correctly if a write is made while the  
timer is not running. Use TRRx to deÞne the preferred count value.  
17.2.7 Timer Event Registers (TER1ÐTER4)  
Each timer event register (TERx), shown in Figure 17-9, reports events recognized by the  
timers. When an output reference event is recognized, the timer sets TERx[REF] regardless  
of the corresponding TMRx[ORI]. The capture event is set only if it is enabled by  
TMRx[CE]. TER1ÐTER4 can be read at any time.  
Writing ones clears event bits; writing zeros has no effect. Both event bits must be cleared  
before the timer negates the interrupt.  
Bits  
Field  
Reset  
Addr  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Ñ
REF CAP  
0x0000  
0x10DB0 (TER1); 0x10DB2 (TER2); 0x10DB4 (TER3); 0x10DB6 (TER4)  
Figure 17-9. Timer Event Registers (TER1ÐTER4)  
17-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
                       
Part IV. Communications Processor Module  
Table 17-4 describes TER Þelds.  
Table 17-4. TER Field Descriptions  
Bits  
Name  
Description  
0Ð13  
14  
Ð
Reserved, should be cleared.  
REF Output reference event. The counter has reached the TRR value. TMR[ORI] is used to enable the  
interrupt request caused by this event.  
15  
CAP Capture event. The counter value has been latched into the TCR. TMR[CE] is used to enable  
generation of this event.  
MOTOROLA  
Chapter 17. Timers  
17-9  
 
Part IV. Communications Processor Module  
17-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Chapter 18  
SDMA Channels and IDMA Emulation  
180  
1T80 he MPC8260 has two physical serial DMA (SDMA) channels. The CP implements two  
dedicated virtual SDMA channels for each FCC, MCC, SCC, SMC, SPI, and I2CÑone for  
each transmitter and receiver. An additional four virtual SDMA channels are assigned to the  
programmable independent DMA (IDMA) channels.  
Figure 18-1 shows data ßow paths. Data from the peripheral controllers can be routed to  
external RAM using the 60x bus (path 1) or the local bus (path 2).  
External  
RAM  
1
60x  
Internal 60x Bus  
Core  
Dual-Port  
RAM  
External  
ROM  
CP  
SDMA  
2
Local  
External  
RAM  
2
2 MCCs  
3 FCCs  
4 SCCs  
2 SMCs  
SPI  
I C  
Figure 18-1. SDMA Data Paths  
MOTOROLA  
Chapter 18. SDMA Channels and IDMA Emulation  
18-1  
       
Part IV. Communications Processor Module  
On a path 1 access, the SDMA channel must acquire the external system bus. On a path 2  
access, the local bus is acquired and the access is not seen on the external system bus. Thus,  
the local bus transfer occurs at the same time as other operations on the external 60x system  
bus.  
The SDMA channel can be assigned abig-endian (Motorola) or little-endian format for  
accessing buffer data. These features are programmed in the receive and transmit registers  
associated with the FCCs, MCCs, SCCs, SMCs, SPI, and I2C.  
If a 60x or local bus error occurs on a CP-related access by the SDMA, the CP generates a  
unique interrupt in the SDMA status register (SDSR). The interrupt service routine then  
reads the appropriate DMA transfer error address register (PDTEA for the 60x bus or  
LDTEA for the local bus) to determine the address the bus error occurred on. The channel  
that caused the bus error is determined by reading the channel number from PDTEM or  
LDTEM. If an SDMA bus error occurs on a CP-related transaction, all CPM activity stops  
and the entire CPM must be reset in the CP command register (CPCR). See Section 18.2,  
ÒSDMA Registers.Ó  
18.1 SDMA Bus Arbitration and Bus Transfers  
On the MPC8260, the core and SDMA can become external bus masters. (The relative  
priority of these masters is programmed by the user; see Section 4.3.2, ÒSystem  
ConÞguration and Protection RegistersÓ for programming bus arbitration.) Therefore, any  
SDMA channel can arbitrate for the bus against the other internal devices and any external  
devices present. Once an SDMA channel becomes system bus master, it remains bus master  
for one transaction (which can be a byte, half-word, word, burst, or extended special burst)  
before releasing the bus. This feature, in combination with the zero-clock arbitration  
overhead provided by the 60x bus, increases bus efÞciency and lowers bus latency.  
To minimize the latency associated with slower, character-oriented protocols, an SDMA  
writes each character to memory as it arrives without waiting for the next character, and  
always reads using 16-bit half-word transfers.  
The SDMA can access the 60x bus either at the regular 60x transactions (single-beat  
accesses, four-beat bursts) or special two- and three-beat burst accesses. For a further  
description of this feature see Section 8.4.3.8, ÒExtended Transfer Mode.Ó  
A transfer may take multiple bus transactions if the memory provides a less than 64-bit 60x  
port size or less than 32-bit local bus port size. An SDMA uses back-to-back bus  
transactions for the entire transferÑ4-word bursts, 64-bit reads, and 8-, 16-, 32-, or 64-bit  
writesÑbefore relinquishing the bus. For example, a 64-bit word 60x-bus read from a 32-  
bit memory takes two consecutive SDMA bus transactions.  
An SDMA can steal transactions with no arbitration overhead when the MPC8260 is bus  
master. Figure 18-2 shows an SDMA stealing a transaction from an internal bus master.  
18-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
Other Transaction  
SDMA Transaction  
Other Transaction  
CLK  
TS  
TA  
SDMA Internally  
Requests the Bus  
Figure 18-2. SDMA Bus Arbitration (Transaction Steal)  
18.2 SDMA Registers  
The only user-accessible registers associated with the SDMA are the SDMA address  
registers, read-only register used for diagnostics in case of an SDMA bus error, the SDMA  
status register and the SDMA mask register.  
18.2.1 SDMA Status Register (SDSR)  
The SDMA status register (SDSR) reports bus error events recognized by the SDMA  
controller for all 26 SDMA channels and 4 IDMA channels. On recognition of a bus error  
on the local or 60x buses, the SDMA sets its corresponding SDSR bit. The SDSR is a  
memory-mapped register that can be read at any time. Bits are cleared by writing ones to  
them; writing zeros has no effect.  
Bits  
Field  
Reset  
Addr  
0
1
2
3
4
5
6
7
SBER_P  
SBER_L  
Ñ
0000_0000  
0x11018  
Figure 18-3. SDMA Status Register (SDSR)  
Table 18-1 describes SDSR Þelds.  
Table 18-1. SDSR Field Descriptions  
Bits  
Name  
Description  
0
SBER_P SDMA channel 60x bus error. Indicates that the SDMA channel on the 60x bus had terminated with  
an error during a read or write transaction. This bit is cleared writing a 1; writing a zero has no effect.  
The SDMA transfer error address is read from PDTEA. The channel number is read from PDTEM.  
1
SBER_L SDMA channel local bus error. Indicates that the SDMA channel on the local bus had terminated with  
an error during a read or write transaction. This bit is cleared writing a 1; writing a zero has no effect.  
The SDMA transfer error address can be read from LDTEA, and the channel number from LDTEM.  
2Ð7  
Ñ
Reserved, should be cleared.  
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18.2.2 SDMA Mask Register (SDMR)  
The SDMA mask register (SDMR) is an 8-bit read/write register with the same bit format  
as the SDMA status register. If an SDMR bit is 1, the corresponding interrupt in SDSR is  
enabled. If the bit is zero, the corresponding interrupt in the status register is masked.  
SDMR is cleared at reset. SDMR can be accessed at 0x1101C.  
18.2.3 SDMA Transfer Error Address Registers (PDTEA and LDTEA)  
There are two 32-bit, read-only SDMA address registers. The PDTEA holds the system  
address accessed during an SDMA transfer error on the 60x bus. The LDTEA holds the  
system address accessed during an SDMA transfer error on the local bus. Both registers are  
undeÞned at reset. PDTEA can be accessed at 0x10050; LDTEA can be accessed at  
0x10058.  
18.2.4 SDMA Transfer Error MSNUM Registers (PDTEM and LDTEM)  
There are two SDMA transfer error MSNUM registers (PDTEM and LDTEM).  
MSNUM[0Ð4] contains the sub-block code (SBC) used to identify the current peripheral  
controller accessing the bus. MSNUM[5] identiÞes which half of the controller is  
transferring (transmitter or receiver). The MSNUM of each transaction is held in these  
registers until the transaction is complete.  
PDTEM is for SDMA transfer errors on the 60x bus, and LDTEM is for errors on the local  
bus. Both registers are undeÞned at reset. See Figure 18-4.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
MSNUM  
Ñ
Ñ
R
Addr  
0x10054 (PDTEM); 0x1005C (LDTEM)  
Figure 18-4. SDMA Transfer Error MSNUM Registers (PDTEM/LDTEM)  
Table 18-2 describes PDTEM and LDTEM Þelds.  
Table 18-2. PDTEM and LDTEM Field Descriptions  
Bits  
Name  
Description  
0Ð4 MSNUM Bits 0Ð4 of MSNUM is the sub-block code of the current peripheral controller accessing the bus. See  
[0Ð4] the SBC Þeld description of the CPCR in Section 13.4.1, ÒCP Command Register (CPCR).Ó  
5
MSNUM Bit 5 of MSNUM indicates which section of the peripheral controller is accessing the bus.  
[5]  
Ñ
0 Transmit section  
1 Receive section  
6Ð7  
Reserved, should be cleared.  
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18.3 IDMA Emulation  
The CPM can be conÞgured to provide general-purpose DMA functionality through the  
SDMA channel. Four general-purpose independent DMA (IDMA) channels are supported.  
In this special emulation mode, the user can specify any memory-to-memory or  
peripheral-to/from-memory transfers as if using dedicated DMA hardware.  
The general-purpose IDMA channels can operate in different user-programmable data  
transfer modes. The IDMA can transfer data between any combination of memory and I/O.  
In addition, data may be transferred in either byte, half-word, word, double-word or burst  
quantities and the source and destination addresses may be odd or even. The most efÞcient  
packing algorithms are used in the IDMA transfers. The single-address mode (ßy-by mode)  
gives the highest performance, allowing data to be transferred between memory and a  
peripheral in a single bus transaction. The chip-select and wait-state generation logic on the  
MPC8260 can be used with the IDMA.  
The bus bandwidth occupied by the IDMA can be programmed in the IDMA parameter  
RAM to achieve maximum system performance.  
The IDMA supports two buffer handling modesÑauto buffer and buffer chaining. The auto  
buffer mode allows blocks of data to be repeatedly moved from one location to another  
without user intervention. The buffer chaining mode allows a chain of blocks to be moved.  
The user speciÞes the data movement using BD tables like those used by other peripheral  
controllers. The BD tables reside in the dual-port RAM.  
Each IDMA has three signals (DREQx, DACKx and DONEx) for peripheral handshaking.  
18.4 IDMA Features  
The main IDMA features are as follows:  
¥
¥
¥
¥
¥
¥
¥
Four independent, fully programmable DMA channels  
Dual- or single-address transfers with 32-bit address and 64-bit data capability  
Memory-to-memory, memory-to-peripheral, and peripheral-to-memory modes  
4-Gbyte maximum block length for each buffer  
32-bit address pointers that can be optionally incremented  
Two buffer handling modesÑauto buffer and buffer chaining  
Interrupts are optionally generated for BD transfer completion, external DONE  
assertion, and STOP_IDMA command completion.  
¥
¥
¥
Any channel is independently conÞgurable for data transfer from any 60x, local bus  
source to any 60x, local bus destination  
Programmable byte-order conversion is supported independently for each DMA  
channel  
Supports programmable 60x-bus bandwidth usage for system performance  
optimization  
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Peripheral to/from memory features include the following:  
¥
External DREQ, DACK, and DONE signals for each channel simpliÞes the  
peripheral interface for memory-to/from-peripheral transfers  
¥
¥
Supports 1-, 2-, 4-, and 8-byte peripheral port sizes  
Supports standard 60x burst accesses (four consecutive 64-bit data phases) to/from  
peripherals  
18.5 IDMA Transfers  
The IDMA channel transfers data from a source to a destination using an intermediate  
transfer buffer (of programmable size) in the dual-port RAM. An efÞcient data-packing  
algorithm bursts data through the IDMA transfer buffer to minimize the bus cycles needed  
for the transfer. In single-address peripheral transfers, however, data is transferred directly  
between memory and a peripheral device without using the IDMA transfer buffer.  
Unaligned data is transferred in single accesses until alignment is achieved. Then, burst  
transactions are used (if allowed by the user) to transfer the bulk of the data buffer. Single  
accesses are used again for any remaining non-burstable data at the end of the transfer.  
18.5.1 Memory-to-Memory Transfers  
For memory-to-memory transfers, the IDMA Þrst Þlls the IDMA transfer buffer in the dual-  
port RAM by initiating read accesses on the source bus. It then empties the data from the  
internal transfer buffer to the destination bus by initiating write accesses. The transfer sizes  
for the source and destination buses are programmed in the IDMA parameter RAM.  
For the DMA to generate bursts on the 60x bus, the address boundaries of each burst  
transfer must be 32-byte aligned. If the transfer does not start on a burst boundary, the  
IDMA controller transfers the end-of-burst (EOB) data (1Ð31 bytes) in non-burst  
transactions on the source bus and on the destination bus until reaching the next boundary.  
When alignment is achieved, subsequent data is bursted until the remainder of the data in  
the buffer is less than a burst size (32 bytes). The remaining data is transferred using non-  
burst transactions.  
Data transfers use the parameters described in Table 18-3.  
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Table 18-3. IDMA Transfer Parameters  
Parameter  
Description  
DMA_WRAP Determines the size of the dedicated IDMA transfer buffer in dual-port RAM. The buffer size is a  
multiple of a 60x burst size (k*32 bytes).  
SS_MAX  
Initialized to (IDMA_transfer_buffer_size - 32) bytes, which is the steady-state maximum transfer size of  
IDMA transfer. This condition ensures that the transfer buffer is either Þlled by one SS_MAX bytes  
transfer and emptied in one or several transfers, or Þlled by one or several transfers to be emptied in  
one SS_MAX bytes transfer. In terms of bursts, if the transfer buffer contains k bursts (each is 32 bytes  
long), then SS_MAX equals to k-1 bursts which is (k-1)*32 bytes.  
STS/DTS  
Source/destination transfer size. These parameters determine the access sizes in which the source/  
destination is accessed in steady state of work. At least one of these values (DTS/STS) must be  
initialized to the value of SS_MAX.  
Figure 18-5 shows the IDMA transfer buffer.  
DMA_WRAP determines IDMA transfer buffer size  
(32 * k) bytes  
EOB[0–31]  
SS_MAX  
(k-1)*32  
128  
96  
64  
32  
Base Address (aligned to buffer size)  
0
Figure 18-5. IDMA Transfer Buffer in the Dual-Port RAM  
Each bufferÕs contents are transferred in three phases:  
¥
First phase. The internal transfer buffer is Þlled with [EOB(alignment to source address) +  
SS_MAX] bytes, read from the source bus. Then, if EOB(alignment to destination address) £  
EOB(alignment to source address), [EOB(destination) + SS_MAX] bytes are written from the  
transfer buffer to the destination bus; or if EOB(destination) > EOB(source),  
[EOB(destination) + (k-2)*32] bytes are written bytes are written. This write transfer  
size leaves a remainder of 0Ð31 bytes in the transfer buffer after the last write burst  
of the steady-state phase. After the Þrst phase, burst alignment is ensured.  
¥
Steady-state phase. The transfer buffer is Þlled with SS_MAX bytes (k-1 bursts),  
read from the source bus in STS units. Then, SS_MAX bytes are written to the  
destination bus, in DTS units, from the transfer buffer. Because alignment is ensured  
from Þrst phase, all bus transfers are bursts. This sequence is repeated until there are  
no more than SS_MAX bytes to be transferred. A remainder of 0Ð31 bytes is left in  
the transfer buffer after the last burst write.  
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¥
Last phase. The remaining data is read into the transfer buffer in bursts, with the last  
1Ð31 bytes read in single accesses. All data in the transfer buffer is written to the  
destination bus in bursts, with the last 1Ð31 bytes written in single accesses. The last  
transfers, read/write or both can be accompanied with DONE assertion, if  
programmed.  
Figure 18-6 shows an example of the three IDMA transfer stages.  
First Phase  
128  
EOB (source)  
EOB (destination)  
96  
Read size = EOB(source) + SS_MAX  
64  
32  
0
Write size = EOB(destination) + SS_MAX  
Note: After phase 1, less than 32 bytes (a burst) will  
remain in the internal buffer.  
after first read  
after first write  
Steady-State Phase (2 transfers in this case)  
Read size = SS_MAX  
Write size = SS_MAX  
Read size = SS_MAX  
Write size = SS_MAX  
after second read  
after second write  
after third read  
after third write  
Last Phase  
Read size = remainder data of BD  
Write size = all data left  
after last read  
after last write  
Figure 18-6. Example IDMA Transfer Buffer States for a Memory-to-Memory  
Transfer (Size = 128 Bytes)  
18.5.1.1 External Request Mode  
Memory-to-memory transfers can be conÞgured to operate in external request mode  
(DCM[ERM] = 1). In external request mode, every read transfer is triggered by the  
assertion of DREQ. When the transfer buffer is full, the Þrst write transfer is done  
automatically. Additional write transfers, if needed, are triggered by DREQ assertions.  
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Because at least one of the transfer sizes (STS or DTS) equals SS_MAX, every DREQ  
assertion causes one transfer to the smaller (in STS/DTS terms) bus. If STS = DTS,  
asserting DREQ triggers one read transfer automatically followed by one write transfer.  
NOTE  
External request mode does not support external DONE  
signaling from a device and DACK signaling from an IDMA  
channel.  
18.5.1.2 Normal Mode  
When external request mode is not selected (DCM[ERM] = 0), the IDMA channel operates  
automatically, ignoring DREQ.  
18.5.2 Memory to/from Peripheral Transfers  
Working with peripheral devices requires the external signals DONE, DREQ, DACK to  
control the data transfer using the following rules:  
¥
The peripheral sets a request for data to be read-from/write-to by asserting DREQ  
as conÞgured, falling or rising edge sensitive.  
¥
¥
¥
The peripheral transfers/samples the data when DACK is asserted.  
The peripheral asserts DONE to stop the current transfer.  
The peripheral terminates the current transfer when DONE is asserted, combined  
with DACK, by the IDMA.  
Peripherals are usually accessed with Þxed port-size transfers. The transfer sizes (STS/  
DTS) related to the peripheral must be programmed to its port size; thus, every access to a  
peripheral yields a single bus transaction. The maximum peripheral port size is (bus_width  
- 8) bytes and also should evenly divide the buffer length, BD[Data Length].  
A peripheral can also be conÞgured to accept a burst per DREQ assertion. In this case, the  
transfer size parameter should be initialized to 32, and the accesses are made in bursts. See  
Table 18-8.  
A peripheral can be accessed at a Þxed address location or at incremental addresses. Setting  
DCM[SINC, DINC] in the DMA channel mode register causes the address to be  
incremented before the next transfer; see Section 18.8.2.1, ÒDMA Channel Mode (DCM).Ó  
This allows the IDMA to access a FIFO buffer the same way it does peripherals.  
DCM[S/D] determines whether the peripheral is the source or destination.  
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Data can be transferred between a peripheral and memory in single- or dual-address  
accesses:  
¥
For dual-address accesses, the data is read from the source, temporarily stored in the  
IDMA transfer buffer in the dual-port RAM, and then written to the destination.  
¥
For single-address accesses (ßy-by mode), the data is transferred directly between  
memory and the peripheral. Memory responds to the address phase, while the  
peripheral ignores it and responds to DACK assertions.  
Any IDMA access to a peripheral uses the highest arbitration priority allowed for the DMA,  
providing faster bus access by bypassing other pending DMA requests.  
18.5.2.1 Dual-Address Transfers  
The following sections discuss various dual-address transfers.  
18.5.2.1.1 Peripheral to Memory  
Dual-address peripheral-to-memory data transfers are similar to memory-to-memory  
transfers using the three-phase algorithm; see Section 18.5.1, ÒMemory-to-Memory  
Transfers.Ó When a peripheral asserts DREQ, data is loaded from the peripheral in port-size  
units to the internal transfer buffer. When the transfer buffer reaches the steady-state level,  
it is automatically written to the memory destination in one transfer. The source transfer  
size (STS) is initialized to the peripheral port size, and the destination transfer size (DTS)  
is initialized to SS_MAX.  
External requests must be enabled (DCM[ERM] = 1) for dual-address peripheral-to-  
memory transfers. If DONE is asserted externally by the peripheral or if a STOP_IDMA  
command is issued, the current transfer stops. All data in the internal transfer buffer is  
written to memory in one transfer before its BD is closed, and the IDSR[EDN] or  
IDSR[SC] event bits are set; see Section 18.8.4, ÒIDMA Event Register (IDSR) and Mask  
Register (IDMR).Ó  
When the peripheral controls a transfer of unknown length, initialize a large enough buffer  
so that the peripheral will most likely assert DONE before overßowing the buffer. When  
DONE is asserted, the BD is closed and interrupts are generated (if enabled). The next  
DREQ assertion opens the next BD if DCM[DT] is set; see Section 18.8.2.1, ÒDMA  
Channel Mode (DCM).Ó  
18.5.2.1.2 Memory to Peripheral  
Dual-address memory-to-peripheral data transfers are similar to memory-to-memory  
transfers using the three-phase algorithm; see Section 18.5.1, ÒMemory-to-Memory  
Transfers.Ó STS is initialized to SS_MAX and DTS is initialized to the peripheral port size.  
The Þrst DREQ peripheral assertion triggers a read of SS_MAX (or more in the Þrst phase)  
bytes from the memory into the internal transfer buffer, automatically followed by a write  
of DTS bytes to the peripheral. Subsequent DREQ assertions trigger writes to the  
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peripheral. When the transfer buffer has fewer than DTS bytes left, the next DREQ  
assertion triggers a read of SS_MAX bytes from memory, automatically followed by a  
write to the peripheral, and the sequence begins again.  
External requests must be enabled (DCM[ERM] = 1) for dual-address peripheral-to-  
memory transfers. If DONE is asserted externally by the peripheral or if a STOP_IDMA  
command is issued, the current transfer is stopped, its BD is closed, and the IDSR[EDN]  
or IDSR[SC] event bits are set; see Section 18.8.4, ÒIDMA Event Register (IDSR) and  
Mask Register (IDMR).Ó  
18.5.2.2 Single Address (Fly-By) Transfers  
When DCM[FB] = 1, both peripheral-to-memory and memory-to-peripheral transfers  
occur in ßy-by mode; see Section 18.8.2.1, ÒDMA Channel Mode (DCM).Ó In fly-by mode,  
an internal transfer buffer is not needed because the data is transferred directly between  
memory and the peripheral. Also, parameters related to the dual-port RAM bus are not  
relevant in ßy-by mode. Each DREQ assertion triggers a transfer the size of the peripheral  
port. All transfers are made in single memory accesses accompanied by DACK assertion.  
When DONE is asserted externally or a STOP_IDMA command is issued, the current transfer  
is stopped, its BD is closed, and the IDSR[EDN] or IDSR[SC] event bits are set; see  
Section 18.8.4, ÒIDMA Event Register (IDSR) and Mask Register (IDMR).Ó  
In ßy-by mode, a peripheral can be conÞgured to handle a burst per DREQ assertion if STS  
is programmed to 32. The Þrst phase of the transfer aligns the data to the burst boundary so  
that subsequent accesses can be performed in bursts.  
18.5.2.2.1 Peripheral-to-Memory Fly-By Transfers  
During peripheral-to-memory ßy-by transfers, the IDMA controller writes to memory  
while simultaneously asserting DACK. The constant assertion of DACK enables the  
controller to write to memory as soon as the peripheral outputs data to the bus. Thus, data  
is transferred from a peripheral to memory in one data phase instead of two, increasing  
throughput.  
For proper operation, STS must equal the peripheral port size.  
18.5.2.2.2 Memory-to-Peripheral Fly-By Transfers  
During memory-to-peripheral ßy-by transfers, the IDMA controller reads from memory  
while simultaneously asserting DACK.  
The constant assertion of DACK enables the controller to read from memory as soon as the  
peripheral samples the data bus. Thus, data is transferred from memory to a peripheral in  
one data phase instead of two, increasing throughput.  
For proper operation, DTS must equal the peripheral port size.  
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18.5.3 Controlling 60x Bus Bandwidth  
STS, DTS, and SS_MAX can be used to control the 60x bus bandwidth occupied by the  
IDMA channel. In every mode except ßy-by mode, at least one transfer size parameter  
(STS/DTS) must be initialized to the SS_MAX value. For memory-to-memory transfers,  
the other transfer size parameter can be initialized to a smaller value used to control the 60x  
bus bandwidth. For example, if the transfer size is N*32 bytes, each time the DMA  
controller wins arbitration, it transfers N bursts before releasing the bus. When SS_MAX  
bytes have been transferred, the controller reverts to single transactions (double-word,  
word, half-word, or byte).  
Memory-to-memory transfer sizes must evenly divide into SS_MAX and also be a multiple  
of 32 (for bursting); see Table 18-7.  
The size of the IDMA transfer buffer in the dual-port RAM should be determined by the  
largest transfer (usually SS_MAX + 32 bytes) needed by one of the buses, while the other  
transfer size can be programmed to control the bandwidth of the other bus.  
Summarizing the above, a larger DMA transfer size provides for greater microcode  
efÞciency and lower DMA bus latency, because the DMA controller does not release the  
60x bus until the transfer is completed. If the DMA priority on the 60x bus is high, however,  
other 60x masters may experience a high bus latency. Conversely, if the transfer size is  
small, the DMA requests the 60x bus more often, DMA latency increases and microcode  
efÞciency decreases.  
The IDMA transfer size parameters give high ßexibility, but it is recommended to check  
overall system performance with different IDMA parameter settings for maximum  
throughput.  
Note that the memory priority parameter DCM[LP] should be considered when dealing  
with bus bandwidth usage.  
18.6 IDMA Priorities  
Each IDMA channel can be programmed to have a higher or lower priority relative to the  
serial controllers or to have the lowest overall priority when requesting service from the CP.  
The IDMA priorities are programmed in RCCR[DRxQP]; see Section 13.3.6, ÒRISC  
Controller ConÞguration Register (RCCR).Ó Take care to avoid overrun or underrun errors  
in the serial controllers when selecting high priorities for IDMA.  
Additional priority over all serial controllers can be selected by setting DCM[LP]; see  
Section 18.8.2.1, ÒDMA Channel Mode (DCM).Ó  
18.7 IDMA Interface Signals  
Each IDMA has three dedicated handshake control signals for transfers involving an  
external peripheral device: DMA request (DREQ[1Ð4]), DMA acknowledge (DACK[1Ð4])  
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and DMA done (DONE[1Ð4]). DREQx may also be used to control the transfer pace of  
memory-to-memory transfers.  
¥
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DREQx is the external DMA request signal.  
DACKx is the DMA acknowledge.  
DONEx marks the end of an IDMA transfer.  
The IDMA signals are multiplexed with other internal controller signals at the parallel I/O  
ports. To enable the IDMA signals, the corresponding bits in the parallel I/O registers  
should be set. See Chapter 35, ÒParallel I/O Ports.Ó  
18.7.1 DREQx and DACKx  
When the peripheral requires IDMA service, it asserts DREQx and the MPC8260 begins  
the IDMA process. When the IDMA service is in progress, DACKx is asserted during  
accesses to the peripheral. A peripheral must validate the transfer by asserting TA or signal  
an error by asserting TEA.  
DREQx may be conÞgured as either edge- or level-sensitive by programming the  
RCCR[DRxM]. When DREQx is conÞgured as edge-sensitive, RCCR[EDMx] controls  
whether the request is generated on the rising or falling edge; see Section 13.3.6, ÒRISC  
Controller ConÞguration Register (RCCR).Ó  
DREQx is sampled at each rising edge of the clock to determine when a valid request is  
asserted by the device.  
18.7.1.1 Level-Sensitive Mode  
For external devices requiring very high data transfer rates, level-sensitive mode allows the  
IDMA to use a maximum bandwidth to service the device. The device requests service by  
asserting DREQx and leaving it asserted as long as it needs service. This mode is selected  
by setting the corresponding RCCR[DRxM].  
The IDMA asserts DACK each time it issues a bus transaction to either read or write the  
peripheral. The peripheral must use TA and TEA for data validation. DACK is the  
acknowledgment of the original burst request given on DREQx. DREQx should be negated  
during the DACK active period to ensure that no further transactions are performed.  
18.7.1.2 Edge-Sensitive Mode  
For external devices that generate a pulsed signal for each operand to be transferred, edge-  
sensitive mode should be used. In edge-sensitive mode, the IDMA controller moves one  
operand for each falling/rising (as conÞgured by RCCR[EDMx]) edge of DREQx. This  
mode is selected by clearing the corresponding RCCR[DRxM] and programming the  
corresponding RCCR[EDMx] to the proper edge.  
When the IDMA controller detects a valid edge on DREQx, a request becomes pending and  
remains pending until it is serviced by the IDMA. Subsequent changes on DREQx are  
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ignored until the request begins to be serviced. The servicing of the request results in one  
operand being transferred. Each time the IDMA issues a bus transaction to either read or  
write the device, the IDMA asserts DACK. The device must use TA and TEA for data  
validation. Thus, DACK is the acknowledgment of the original transaction request given on  
DREQx.  
18.7.2 DONEx  
This bidirectional open-drain signal is used to indicate the last IDMA transfer. DONE can  
be an output of the IDMA in the source or destination bus transaction if the transfer count  
is exhausted. This function is controlled by BD[SDN, DDN].  
DONE can also operate as an input. When operating in external request modes, DONE may  
be used as an input to the IDMA controller to indicate that the device being serviced  
requires no more transfers. In that case, the transfer is terminated, the current BD is closed,  
and an interrupt is generated (if enabled).  
NOTE  
DONE is ignored if it is asserted externally during internal  
request mode (DCM[ERM] = 0).  
DONE must not be asserted externally during memory-to-  
memory transfers if external request mode is enabled  
(DCM[ERM] = 1).  
18.8 IDMA Operation  
Every IDMA operation involves the following stepsÑIDMA channel initialization, data  
transfer, and block termination.  
¥
During initialization, the core initializes the IDMA_BASE register in the internal  
parameter RAM to point to the IDMA-speciÞc table in RAM. This table contains  
control information for the IDMA operation. In addition the core initializes the  
parallel I/O registers to enable IDMA external signals, if needed, and other registers  
related to the channel priority and operation modes; see Section 18.11,  
ÒProgramming the Parallel I/O Registers.Ó The core initiates the IDMA BDs to point  
to the data for the transfer and/or a free space for data to be transferred to, and starts  
the transfer by issuing the START_IDMA command.  
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During data transfer, the IDMA accepts requests for data transfers and provides  
addressing and bus control for the transfers.  
Termination occurs when the IDMA operation completes or the peripheral asserts  
DONE externally. The core can initiate termination by using the STOP_IDMA  
command. The IDMA can interrupt the core if interrupts are enabled to signal for  
operation termination and other events related to the data transfer.  
The IDMA uses a data structure, which, as with serial controller BDs, allows ßexible data  
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Part IV. Communications Processor Module  
allocation and eliminates the need for core intervention between transfers. BDs contain  
information describing the data block and special control options for the DMA operation  
while transferring the data block.  
18.8.1 Auto Buffer and Buffer Chaining  
The core processor should initialize the IDMA BD table with the appropriate buffer  
handling mode, source address, destination address, and block length. See Figure 18-7.  
IDMAx BD Base  
Address (IBASE)  
BD 0  
Source Device or  
Buffer 0  
Destination Device or  
Buffer 0  
BD 1  
BD 2  
Source Device or  
Buffer 1  
Destination Device or  
Buffer 1  
•
•
•
Source Device or  
Buffer 2  
Destination Device or  
Buffer 2  
•
•
•
•
•
•
BD n  
Source Device or  
Buffer n  
Destination Device or  
Buffer n  
Figure 18-7. IDMAx ChannelÕs BD Table  
Data associated with each IDMA channel is stored in buffers and each buffer is referenced  
by a BD that uses a circular table structure in the dual-port RAM. Control options such as  
interrupt and DONE assertion are also programmed on a per-buffer basis in each BD.  
Data may be transferred in the two following modes:  
¥
Auto buffer mode. The IDMA continuously transfers data to/from the location  
programmed in the BD until a STOP_IDMA command is issued or DONE is asserted  
externally.  
¥
Buffer chaining mode. Data is transferred according to the Þrst BD parameters, then  
the second BD and so forth. The Þrst BD is reused (if ready) until the BD with the  
last bit set is reached. IDMA transfers stop and restarts when the BD table is  
reinitialized and a START_IDMA command is issued.  
MOTOROLA  
Chapter 18. SDMA Channels and IDMA Emulation  
18-15  
     
Part IV. Communications Processor Module  
18.8.2 IDMAx Parameter RAM  
When an IDMAx channel is conÞgured to auto buffer or buffer chaining mode, the  
MPC8260 uses the IDMAx parameters listed in the Table 18-4. Parameters should be  
modiÞed only while the channel is disabled, that is, before the Þrst START_IDMA command  
or when the event registerÕs stop-completed bit (IDSR[SC]) is set following a STOP_IDMA  
command.  
Each IDMAx channel parameter table can be placed at any 64-byte aligned address in the  
dual-port RAMÕs general-purpose area (banks 1Ð8). The CP accesses each IDMAx channel  
parameter table using a user-programmed pointer (IDMAx_BASE) located in the  
parameter RAM; see Section 13.5.2, ÒParameter RAM.Ó For example, if the IDMA1  
channel parameter table is to be placed at address offset 0x2000 in the dual-port RAM,  
write 0x2000 to IDMA1_BASE.  
Table 18-4. IDMAx Parameter RAM  
1
Offset  
Name  
IBASE  
Width  
Description  
0x00  
Hword IDMA BD table base address. DeÞnes the starting location in the dual-port RAM  
for the set of IDMA BDs. It is an offset from the beginning of the dual-port RAM.  
The user must initialize IBASE before enabling the IDMA channel and should  
not overlap BD tables of two enabled serial controllers or IDMA channels or  
erratic operation results. The IBASE value should be 16-bit aligned.  
0x02  
0x04  
DCM  
Hword DMA channel mode. See Section 18.8.2.1, ÒDMA Channel Mode (DCM).Ó  
IBDPTR  
Hword IDMA BD pointer. Points to the current BD during transfer processing. Points to  
the next BD to be processed when an idle channel is restarted. Initialize to  
IBASE before the Þrst START_IDMA command. If BD[W] = 1, the CP initializes  
IBPTR to IBASE When the end of an IDMA BD table is reached. After a  
STOP_IDMA command is issued, IBDPTR points to the next BD to be processed.  
It can be modiÞed after SC interrupt is set and before a START_IDMA command is  
reissued.  
0x06  
DPR_BUF  
Hword IDMA transfer buffer base address. The base address should be aligned  
according to the buffer size determined by DCM[DMA_WRAP]. The transfer  
buffer size should be consistent with DCM[DMA_WRAP]; that is, DPR_BUF =  
DMA_WRAP  
(64 X 2  
) - 32. See Section 18.8.2.1, ÒDMA Channel Mode (DCM).Ó  
0x08  
0x0A  
BUF_INV  
Hword Internal buffer inventory. Indicates the quantity of data inside the internal buffer.  
Hword Steady-state maximum transfer size in bytes. User-deÞned parameter to  
SS_MAX  
increase microcode efÞciency. Initialize to internal_buffer_size - 32, that is,  
DMA_WRAP  
SS_MAX = (64 X 2  
) - 32. If possible, SS_MAX is used as the transfer  
size on transfers to/from memory in memory-to-peripheral mode or in  
peripheral-to-memory mode. For memory-to-memory mode, SS_MAX is used  
as the transfer size for at least one of the devices. SS_MAX should be  
consistent with STS, DTS, and DCM[S/D]. See Table 18-7 and Table 18-8.  
0x0C  
DPR_IN_PTR  
Hword Write pointer inside the internal buffer.  
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Part IV. Communications Processor Module  
Table 18-4. IDMAx Parameter RAM (Continued)  
1
Offset  
Name  
Width  
Description  
0x0E  
STS  
Hword Source transfer size in bytes. All transfers from the source (except the start  
alignment and the end) are written to the bus using this parameter.  
In memory-to-peripheral mode, STS should be initialized to SS_MAX.  
In peripheral-to-memory mode, STS should be initialized to the peripheral port  
size or peripheral transfer size (if the peripheral accepts bursts). See Table 18-8  
for valid STS values for peripherals.  
In ßy-by mode, STS is initialized to the peripheral port size.  
In memory-to-memory mode:  
¥
¥
STS should be initialized to SS_MAX.  
DTS value should be initialized to SS_MAX. STS can be initialized to values  
other than SS_MAX in the following conditions:  
ÐSTS must divide SS_MAX.  
ÐSTS must be divided by 32 to enable bursts during the steady-state phase.  
See Table 18-7 for memory-to-memory valid STS values.  
0x10  
0x12  
0x14  
0x16  
DPR_OUT_PTR Hword Read pointer inside the internal buffer.  
SEOB  
DEOB  
DTS  
Hword Source end of burst. Used for alignment of the Þrst read burst.  
Hword Destination end of burst. Used for alignment of the Þrst write burst.  
Hword Destination transfer size in bytes. All transfers to destination (except the start  
alignment and the tail) are written to the bus using this parameter.  
In peripheral-to-memory mode, DTS should equal SS_MAX.  
In memory-to-peripheral modes, initialize DTS to the peripheral port size if  
transferÕs destination is a peripheral.Valid sizes for peripheral destination is 1, 2,  
4, and 8 bytes, or peripheral transfer size (if the peripheral accepts bursts). See  
Table 18-8 for valid STS values for peripherals.  
In ßy-by mode, DTS is initialized to the peripheral port size.  
In memory-to-memory mode:  
¥
¥
DTS value is initialized to SS_MAX.  
STS value is initialized to SS_MAX. DTS can be initialized to values other  
than SS_MAX in the following conditions:  
ÐDTS must divide SS_MAX.  
ÐDTS must be divided by 32, to enable bursts in steady-state phase.  
See Table 18-8 for valid memory-to-memory DTS values.  
Hword Used to save return address when working in ERM = 1 mode.  
Hword Reserved, should be cleared.  
0x18  
0x1A  
0x1C  
0x20  
0x24  
0x28  
RET_ADD  
Ñ
BD_CNT  
S_PTR  
D_PTR  
ISTATE  
Word Internal byte count.  
Word Source internal data pointer.  
Word Destination internal data pointer.  
Word Internal. Should be cleared before every START_IDMA command.  
1
From the pointer value programmed in IDMAx_BASE: IDMA1_BASE at 0x87FE, IDMA2_BASE at 0x88FE,  
IDMA3_BASE at 0x89FE, and IDMA4_BASE at 0x8AFE; see Section 13.5.2, ÒParameter RAM.Ó  
MOTOROLA  
Chapter 18. SDMA Channels and IDMA Emulation  
18-17  
Part IV. Communications Processor Module  
18.8.2.1 DMA Channel Mode (DCM)  
The IDMA channel mode (DCM) is a 16-bit Þeld within the IDMA parameter RAM, that  
controls the operation modes of the IDMA channel. As are all other IDMA parameters, the  
DCM is undeÞned at reset.  
bits  
Þeld  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
FB  
LP  
Ñ
TC2  
Ñ
DMA_WRAP  
SINC DINC ERM DT  
S/D  
Reset  
R/W  
Ñ
R/W  
Figure 18-8. DCM Parameters  
Table 18-5 describes DCM bits.  
Table 18-5. DCM Field Descriptions  
Bits  
Name  
Description  
0
FB  
Fly-by mode. See Table 18-6.  
0 Dual-address mode.  
1 Fly-by (single-address) mode. The internal IDMA transfer buffer is not used. Valid only in  
peripheral-to-memory (S/D=10) or memory-to-peripheral (S/D=01) modes.  
1
LP  
Low priority. Applies to memory-to-memory accesses only. See Section 4.3.2, ÒSystem  
ConÞguration and Protection Registers.Ó  
0 The IDMA transaction to memory is in middle CPM request priority.  
1 The IDMA transaction to memory is in low CPM request priority.  
Note that IDMA single-address (ßy-by) transfers with external peripherals are always high  
priority, ignoring this bit and bypassing other pending SDMA requests.  
2Ð4  
5
Ñ
Reserved, should be cleared.  
TC2  
Driven on TC[2] during IDMA transactions. The TC[0Ð1] signals are always driven to 0b11  
during IDMA transactions.  
6
Ñ
Reserved, should be cleared.  
7Ð9 DMA_WRAP DMA wrap. DeÞnes the size of the IDMA transfer buffer. The IDMA pointer wraps to the  
beginning of the buffer whenever DMA_WRAP bytes have been transferred to/from the buffer.  
000 64 byte  
001 128 byte  
010 256 byte  
011 512 byte  
100 1024 byte  
101 2048 byte  
11x Reserved  
Table 18-7 and Table 18-8 describes the relations between the parameterÕs initial value and  
SS_MAX, STS, DTD and DCM[S/D] parameters.  
The IDMA transfer buffer (DPR_BUF) size should be consistent with DCM[DMA_WRAP]; that  
(DMA_WRAP)  
is DPR_BUF = 64 X 2  
- 32  
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Part IV. Communications Processor Module  
Table 18-5. DCM Field Descriptions (Continued)  
Bits  
Name  
Description  
10  
SINC  
Source increment address.  
0 Source address pointer (S_PTR) is not incremented in the source read transaction. Should  
be cleared for peripheral-to-memory transfers if the peripheral has a Þxed address.  
1 CP increments the source address pointer (S_PTR) with the number of bytes transferred in  
the source read transaction. Used for memory-to-memory and memory-to-peripheral  
transfers.  
In ßy-by mode, SINC controls the memory address increment and should equal DINC.  
11  
DINC  
Destination increment address.  
0 Destination address pointer (D_PTR) is not changed in the destination write transaction.  
Used for memory-to-peripheral transfers if the peripheral has a Þxed address.  
1 CP increments the destination pointer (D_PTR) with the number of bytes transferred in the  
destination write transaction. Used for memory-to-memory and memory-to-peripheral  
transfers.  
In ßy-by mode, DINC should equal SINC.  
12  
ERM  
External request mode.  
0 The CP transfers continuously, as if an external level request is asserted, regardless of the  
DREQ signal assertion. The CP stops the transfer when there are no more valid BDs or  
after a STOP_IDMA command is issued. DONE assertion by a external device is ignored.  
1 The CP responds to DREQ as conÞgured (edge/level) by performing single- or dual-address  
transfers. The CP also responds to DONE assertions.  
Note: Memory-to-memory transfers (S/D=00) with external request (ERM=1) is allowed, but  
DONE assertion is not supported in this mode (DONE should be disabled).  
13  
DT  
DONE treatment:  
0 After external DONE assertion, the IDMA ignores further DREQ assertions. The CP closes  
the current BD and IDMA stops. START_IDMA command should be issued before assertion of  
another DREQ.  
1 After external DONE assertion, the CP closes the current BD. The IDMA continues to the  
next BD when DREQ is asserted.  
14Ð15  
S/D  
Source/destination is a peripheral device or memory. See Table 18-6.  
00 Read from memory, write to memory.  
10 Read from peripheral, write to memory.  
01 Read from memory, write to peripheral.  
11 Reserved  
When a device is a peripheral:  
¥
¥
¥
¥
DACK is asserted during transfers to/from it.  
It may assert DONE to terminate all accesses to/from it.  
It can be operated in ßy-by modeÑrespond to DACK ignoring the address.  
It gets highest DMA priority on the bus arbiter and the lowest DMA latency available.  
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Part IV. Communications Processor Module  
18.8.2.2 Data Transfer Types as Programmed in DCM  
Table 18-6 summarizes the types of data transfers according to the DCM programming.  
Table 18-6. IDMA Channel Data Transfer Operation  
S/D FB  
Read From  
Write To  
Description (Steady-State Operation)  
01  
10  
0
0
Memory  
Peripheral  
Read from memory: Filling internal buffer in one DMA transfer.  
(STS = SS_MAX) (DTS = port size On the bus: one burst or more, depends on STS  
or 32)  
Write to peripheral: In smaller transfers until internal buffer empties.  
On the bus: singles or burst, depends on DTS  
Peripheral  
(STS = port size or (DTS =  
Memory  
Read from peripheral: Filling internal buffer in several DMA  
transfers.  
32)  
SS_MAX)  
On the bus: singles or burst, depends on STS  
Write to memory: in one DMA transfer, internal buffer empties.  
On the bus: one burst or more, depends on DTS  
00  
00  
0
0
Memory  
Memory  
Read from memory: Filling internal buffer in one DMA transfer.  
On the bus: one burst or more, depends on STS  
(STS = SS_MAX) (DTS =  
SS_MAX or  
less)  
Write to memory: in one transfer or more until internal buffer  
empties.  
On the bus: singles or bursts, depends on DTS  
Memory  
(STS = SS_MAX  
or less)  
Memory  
(DTS =  
SS_MAX)  
Read from memory: Filling internal buffer in one or more DMA  
transfers.  
On the bus: singles or bursts, depends on STS  
Write to memory: in one DMA transfer, internal buffer empties.  
On the bus: one burst or more, depends on DTS  
01  
10  
1
1
Memory to  
peripheral  
(DTS = port size or  
32)  
Ñ
Read transaction from memory while asserting DACK to  
peripheral. Peripheral samples the data read from memory.  
On the bus: singles or bursts, depends on DTS  
Ñ
Peripheral to  
memory  
Write transaction to memory while asserting DACK to peripheral.  
Peripheral provides the data that is written to the memory.  
(STS = port size On the bus: singles or bursts, depends on STS  
or 32)  
18.8.2.3 Programming DTS and STS  
The options for setting STS and DTS depend on (DCM[DMA_WRAP]) and are described  
in the following tables for memory/memory and memory/peripheral transfers.  
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Part IV. Communications Processor Module  
Table 18-7 describes valid STS/DTS values for memory-to-memory operations.  
Table 18-7. Valid Memory-to-Memory STS/DTS Values  
Number of Transfers to  
Fill Internal Buffer  
Internal  
DMA_WRAP Buffer SS_MAX  
Size  
STS (in Bytes)  
DTS (in Bytes)  
STS Size  
DTS Size  
1 * 32  
32  
32  
1 * 32  
1
1
000  
001  
010  
011  
100  
101  
64  
1 * 32  
3 * 32  
1
1
3 * 32  
3 * 32, 32  
1
1, 3  
128  
3 * 32, 32  
3 * 32  
1, 3  
1
7 * 32  
7 * 32, 32  
1
1, 7  
256  
7 * 32  
7 * 32, 32  
7 * 32  
1, 7  
1
15 * 32  
15 * 32, 3 * 32, 5 * 32, 32  
15 * 32  
1
1, 5, 3, 15  
1
1, 5, 3, 15  
512  
15 * 32  
31 * 32  
63 * 32  
15 * 32, 3 * 32, 5 * 32, 32  
31 * 32  
1
31 * 32, 32  
31 * 32  
1, 31  
1024  
2048  
31 * 32, 32  
63 * 32  
1, 31  
1
1, 7, 9, 63  
1
63 * 32, 9 * 32, 7 * 32, 32  
63 * 32  
1
63 * 32, 9 * 32, 7 * 32, 32  
1, 7, 9, 63  
Table 18-8 describes valid STS/DTS values for memory/peripheral operations.  
Table 18-8. Valid STS/DTS Values for Peripherals  
DMA_WRAP Internal Buffer Size SS_MAX  
S/D Mode  
STS (in Bytes)  
DTS (in Bytes)  
1
000  
001  
010  
64  
1 * 32  
3 * 32  
7 * 32  
01  
1 * 32  
1, 2, 4, 8 (single) ; 32  
2
(burst)  
10  
01  
10  
01  
10  
1, 2, 4, 8 (single); 32  
(burst)  
1 * 32  
128  
256  
3 * 32  
1, 2, 4, 8 (single); 32  
(burst)  
1, 2, 4, 8 (single); 32  
(burst)  
3 * 32  
7 * 32  
1, 2, 4, 8 (single); 32  
(burst)  
1, 2, 4, 8 (single); 32  
(burst)  
7 * 32  
MOTOROLA  
Chapter 18. SDMA Channels and IDMA Emulation  
18-21  
   
Part IV. Communications Processor Module  
Table 18-8. Valid STS/DTS Values for Peripherals (Continued)  
DMA_WRAP Internal Buffer Size SS_MAX  
S/D Mode  
STS (in Bytes)  
DTS (in Bytes)  
011  
100  
101  
512  
1024  
2048  
15 * 32  
31 * 32  
63 * 32  
01  
15 * 32  
1, 2, 4, 8 (single); 32  
(burst)  
10  
01  
10  
01  
10  
1, 2, 4, 8 (single); 32  
(burst)  
15 * 32  
31 * 32  
1, 2, 4, 8 (single); 32  
(burst)  
1, 2, 4, 8 (single); 32  
(burst)  
31 * 32  
63 * 32  
1, 2, 4, 8 (single); 32  
(burst)  
1, 2, 4, 8 (single); 32  
(burst)  
63 * 32  
1
2
These values come out as a single transaction on the bus.  
Peripherals that can accept bursts of 32 bytes are supported.  
18.8.3 IDMA Performance  
The transfer parameters STS, DTS, SS_MAX, and DMA_WRAP determine the amount of  
data transferred for each START_IDMA command issued. Using large internal IDMA  
transfer buffers and the maximum transfer sizes allows longer transfers to memory devices,  
optimizes bus usage and thus reduces the overall load on the CP.  
For example, 2,016 bytes can be transferred by issuing one START_IDMA command using a  
2-Kbyte internal transfer buffer, or by issuing 63 START_IDMA commands using a 64-byte  
buffer. The load on the CP in the second case is about 63 times more than the Þrst.  
18.8.4 IDMA Event Register (IDSR) and Mask Register (IDMR)  
The IDMA event (status) register (IDSR) is used to report events recognized by the IDMA  
controller. On recognition of an event, the controller sets the corresponding IDSR bit. Each  
IDMA event bit can generate a maskable interrupt to the core. Even bits are cleared by  
writing ones; writing zeros has no effect.  
The IDMA mask register (IDMR) has the same format as IDSR. Setting IDMR bits enables,  
and clearing IDMR bits disables, the corresponding interrupts in the event register.  
Figure 18-9 shows the bit format for IDSR and IDMR.  
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Part IV. Communications Processor Module  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
Ñ
R
SC  
OB  
EDN  
BC  
0000_0000  
R/W  
Addr  
0x11020 (IDSR1), 0x11028 (IDSR2), 0x11030 (IDSR3), 0x11038 (IDSR4)/  
0x11024 (IDMR1), 0x1102C (IDMR2), 0x11034 (IDMR3), 0x1103C (IDMR4)  
Figure 18-9. IDMA Event/Mask Registers (IDSR/IDMR)  
Table 18-9 describes IDSR/IDMR Þelds.  
Table 18-9. IDSR/IDMR Field Descriptions  
Bits Name  
Description  
0Ð3  
4
Ñ
Reserved, should be cleared.  
SC Stop completed. Set after the IDMA channel completes processing the STOP_IDMA command. Do not  
change channel parameters until SC is set.  
5
6
OB Out of buffers. Set to indicate that the IDMA channel encountered no valid BDs for the transfer.  
EDN External DONE was asserted by device. Set to indicate that the IDMA channel terminated a transfer  
because DONE was asserted by an external device, on the former SDMA transaction.  
7
BC BD completed. Set only after all data of a BD whose I (interrupt) bit is set has completed transfer to the  
destination.  
18.8.5 IDMA BDs  
Source addresses, destination addresses, and byte counts are presented to the CP using the  
special IDMA BDs. The CP reads the BDs, programs the SDMA channel, and notiÞes the  
core about the completion of a buffer transfer using the IDMA BDs. This concept is similar  
to the one used for the serial controllers on the MPC8260 except that the BD is larger  
because it contains additional information.  
0
1
2
W
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
Ñ
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
Offset + 8  
Offset + A  
Offset + C  
Offset + E  
V
Ñ
I
L
Ñ
Ñ
CM  
Ñ
SDN DDN DGBL  
DBO  
DDTB  
Ñ
SGBL  
SBO  
SDTB  
Ñ
Data Length  
Source Data Buffer Pointer  
Destination Data Buffer Pointer  
Figure 18-10. IDMA BD Structure  
18-23  
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Part IV. Communications Processor Module  
Table 18-10 describes IDMA BD Þelds.  
Table 18-10. IDMA BD Field Descriptions  
Offset Bits  
Name  
V
Description  
0x00  
0
Valid  
0 This BD does not contain valid data for transfer.  
1 This BD contain valid data for transfer.  
The CP checks this bit before starting a BD service. If this bit is cleared when the CP  
accesses the BD, an interrupt IDSR[OB] is issued to the core, the IDMA channel is  
stopped until a START_IDMA command is issued. After the BD is serviced this bit is  
cleared by CP unless CM = 1.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (Þnal BD in table)  
0 This is not the last BD in the BD table.  
1 Last BD in the table. After the associated buffer has been used, the CP transfers data  
from the Þrst BD in the table, which is pointed by IBASE. The number of BDs in this  
table is programmable and determined by W bit and the overall space constraints of the  
dual-port RAM.  
3
4
I
Interrupt  
0 No interrupt is generated after this buffer is serviced.  
1 When the CP services all the bufferÕs data, IDSR[BC] is set, which generates a  
maskable interrupt.  
L
Last  
0 Not the last buffer of a chain to be transferred in buffer chaining mode. The I bit can be  
used to generate an interrupt when this buffer service is complete.  
1 Last buffer of a chain to be transferred in buffer chaining mode.When this BD service is  
complete the channel is stopped by CP until START_IDMA command is issued.  
This bit should be set only in buffer chaining mode (CM bit 6 = 0).  
5
6
Ñ
Reserved, should be cleared.  
CM  
Continuous mode  
0 Buffer chaining mode. The CP clears V after this BD is serviced. Buffer chaining mode  
is used to transfer large quantities of data into non-contiguous buffer areas. The user  
can initialize BDs ahead of time, if needed. The CP automatically loads the IDMA  
registers from the next BD values when the transfer is terminated.  
1 Auto buffer mode (continuous mode).The CP does not clear V after this BD is serviced.  
This is the only difference between auto buffer mode and buffer chaining mode. Auto  
buffer mode transfers multiple groups of data to/from a buffer table and does not  
require BD reprogramming. The CP automatically reloads the IDMA registers from the  
next BD values when the transfer is terminated. Either a single BD or multiple BDs can  
be used to create an inÞnite loop of repeated data moves.  
Note that the I bit can still be used to generate an interrupt in this mode.  
7-8  
9
Ñ
Reserved, should be cleared.  
SDN  
Source done  
0 DONE is inactive during this BD.  
1 The IDMA asserts DONE at the last read data phase of the BD.  
In ßy-by mode (DCM[FB] = 1), SDN should be same as DDN.  
10  
DDN  
Destination done  
0 DONE is inactive during this BD.  
1 The IDMA asserts DONE at the last write data phase of the BD.  
In ßy-by mode (DCM[FB] = 1), DDN should be same as SDN.  
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Part IV. Communications Processor Module  
Table 18-10. IDMA BD Field Descriptions (Continued)  
Offset Bits  
Name  
DGBL  
Description  
11  
Destination global  
0 Snooping is not activated.  
1 Snooping is activated for write transactions to the destination.  
In ßy-by mode, should be the same as SGBL.  
12-13  
DBO  
Destination byte ordering:  
01 PowerPC little Endian.  
1x Big endian (Motorola).  
00 Reserved  
In ßy-by mode, should be the same as SBO.  
14  
15  
Ñ
Reserved, should be cleared.  
DDTB  
Destination data bus.  
0 The destination address lies within the 60x bus.  
1 The destination address lies within the local bus.  
In ßy-by mode, should be the same as SDTB.  
0x02  
0-1  
2
Ñ
Reserved, should be cleared.  
SGBL  
Source global  
0 Snooping is not activated.  
1 Snooping is activated for read transactions from the source.  
In ßy-by mode, should be the same as DGBL.  
3-4  
SBO  
Source byte ordering:  
01 PowerPC little endian  
1x Big endian (Motorola)  
00 Reserved  
In ßy-by mode, should be the same as DBO.  
5
6
Ñ
Reserved, should be cleared.  
SDTB  
Source data bus.  
0 The source address lies within the 60x bus.  
1 The source address lies within the local bus.  
In ßy-by mode, should be the same as DDTB.  
7-15  
Ñ
Reserved, should be cleared.  
0x04 0Ð31  
Data  
Length  
Number of bytes the IDMA transfers. Should be programmed to a value greater than  
zero.  
Notes: When operating with a peripheral that accepts only single bus transactions  
(transfer size < 32), data length should be a multiple of the peripheral transfer size (STS  
for S/D = 10, or DTS for S/D = 01). Also, there is no error notiÞcation if the data length  
does not match the buffer sizes.  
0x08 0Ð31  
Source  
Buffer  
Pointer  
Holds the address of the associated buffer. Buffers may reside in internal or external  
memory. Note that if the source/destination is a device, the pointer should contain the  
device address.  
In ßy-by mode, the pointers should contain the memory address.  
0x0C 0Ð31 Destination  
Buffer  
Pointer  
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Part IV. Communications Processor Module  
18.9 IDMA Commands  
The user has two commands to control each IDMA channel. These commands are executed  
through the CP command register (CPCR); see Section 13.4, ÒCommand Set.Ó  
18.9.1 START_IDMA Command  
The START_IDMA command is used to start a transfer on an IDMA channel. The user must  
initialize all parameters relevant for the correct operation of the channel (IDMAx_BASE  
and IDMA channel parameter table) before issuing this command.  
To restart the channel operation, the START_IDMA command can be reissued after every  
pause in channel activity. The user must ensure that parameters are correct for the channel  
to continue operation correctly.  
The parameter ISTATE of the IDMA parameter RAM should be cleared before every issue  
of a START_IDMA command.  
An IDMA pause may occur for one of the following reasons:  
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The channel is out of buffersÑIDSR[OB] event is set and an interrupt is generated  
to the core, if enabled.  
DONE was asserted externally and DCM[DT] = 0 (see Table 18-5).An IDSR[EDN]  
event is set and an interrupt is generated to the core, if enabled.  
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STOP_IDMA command was issued.  
The channel has Þnished a transfer of a BD with the last bit (L) set.  
If the START_IDMA command is reissued and channel has more buffers to transfer, it restarts  
transferring data according to the next BD in the buffer table.  
In external request mode (ERM=1), the START_IDMA command initializes the channel, but  
the Þrst data transfer is performed after external DREQx assertion.  
In internal request mode (ERM=0), the START_IDMA command starts the data transfer  
almost immediately, with a delay which depends on the CP load.  
18.9.2 STOP_IDMA Command  
The STOP_IDMA command is issued to stop the transfer of an IDMA channel.  
When a STOP_IDMA command is issued, the CP terminates current IDMA transfers and the  
current BD is closed (if it was open). If memory is the destination, all data in the IDMA  
internal buffer is transferred to memory before termination.  
At the end of the stop process, the stop-completed event (SC) is set and a maskable interrupt  
is generated to the core. The user should not modify channel parameters until SC = 1. When  
the channel is stopped, it does not respond to external requests. If a START_IDMA command  
is reissued, the next BD in the BD table is processed (if it is valid).  
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Part IV. Communications Processor Module  
In external request mode (ERM = 1), STOP_IDMA command processing has priority over a  
peripheral asserting DONE.  
Note: In memory-to-peripheral, peripheral-to-memory, and ßy-by modes, if a STOP_IDMA  
command is issued with no data in the internal buffer, the BD is immediately closed and the  
channel is stopped. In this case, a peripheral expecting DONE to be asserted is not notiÞed  
because the last transfer of the buffer (with BD[DDN or SDN] set) is not performed.  
18.10 IDMA Bus Exceptions  
Bus exceptions can occur while the IDMA has the bus and is transferring operands. In any  
computer system, a hardware failure can cause an error during a bus transaction due to  
random noise or an illegal access. When a synchronous bus structure (like those supported  
by the MPC8260) is used, it is easy to make provisions for a bus master to detect and  
respond to errors during a bus transaction. The IDMA recognizes the same bus exceptions  
as the core, reset and transfer error, as described in Table 18-11.  
Table 18-11. IDMA Bus Exceptions  
Exception  
Description  
Reset  
On an external reset, the IDMA immediately aborts the channel operation, returns to the idle state, and  
clears IDSR. If reset is detected when a bus transaction is in progress, the transaction is terminated, the  
control and address/data pins are three-stated, and bus mastership is released.  
Transfer  
Error  
When a fatal error occurs during a bus transaction, a bus error exception is used to abort the transaction  
and systematically terminate channel operation. The IDMA terminates the current bus transaction,  
signals an error in the SDSR, and signals an interrupt if the corresponding bit in the SDMR is set. The  
CPM must be reset before IDMA operation is restarted. Any data previously read from the source into the  
internal storage is lost, however, issuing a START_IDMA command transfers the last BD again.  
Note: Any source or destination device for an operand under IDMA handshake control for single-address  
transfers may need to monitor TEA to detect a bus exception for the current bus transaction. TEA  
terminates the transaction immediately and negates DACK, which is used to control the transfer to/from  
the device.  
18.10.1 Externally Recognizing IDMA Operand Transfers  
The following ways can be used determine externally that the IDMA is executing a bus  
transaction:  
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The TC[2] signal (programmed in DCM[TC2]) or SDMA channels can be  
programmed to a unique code that identiÞes an IDMA transfer.  
The DACK signal shows accesses to the peripheral device. DACK activates on either  
the source or destination bus transactions, depending on DCM[S/D].  
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Part IV. Communications Processor Module  
18.11 Programming the Parallel I/O Registers  
The parallel I/O registers control the use of the external pins of the chip. Each pin can be  
used for different purposes. See Table 18-12, Table 18-13 and Table 18-14 (optional) for  
the proper parallel I/O register programming dedicating the proper external ports to the four  
IDMA channelsÕ external I/O signals.  
Each port is controlled by Þve I/O registers: PPAR, PSOR, PDIR, PODR, and PDAT. Each  
bit in these registers controls the external pin of the same location.  
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PPARC selects the pins general purpose(0)/dedicated(1) mode for port C.  
PDIRC select the pins input or inout (0)/output(1) mode for port C.  
PODRC selects the open drain pins for port C.  
PSORC selects the pins dedicated1(0)/dedicated2(1) mode for port C.  
PPARA, PDIRA, PODRA, and PSORA control port A in the same way.  
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PPARD, PDIRD, PODRD, and PSORD control port D in the same way.  
The default is the value that is seen by the IDMA channel on the pin (input or inout  
mode onlyÑPDIR[PN] = 0) if a PSORx register bit is set to the complement value  
of the value in Table 18-12, Table 18-13 and Table 18-14. See Section 35.2, ÒPort  
Registers.Ó  
Table 18-12. Parallel I/O Register ProgrammingÑPort C  
Channel  
Signal  
Pin  
PPARC  
PDIRC  
PODRC  
PSORC  
Default  
IDMA1  
DREQ1 (I)  
DACK1 (O)  
DONE1 (I/O)  
DREQ2 (I)  
PC[0]  
PC[23]  
PC[22]  
PC[1]  
PC[3]  
PC[2]  
1
1
1
1
1
1
0
1
0
0
1
0
0
0
1
0
0
1
0
1
1
0
1
1
GND  
Ñ
VDD  
GND  
Ñ
IDMA2  
DACK2 (O)  
DONE2 (I/O)  
VDD  
Table 18-13 describes parallel I/O register programming for port A.  
Table 18-13. Parallel I/O Register ProgrammingÑPort A  
Channel  
Signal  
Pin  
PPARA  
PDIRA  
PODRA  
PSORA  
Default  
IDMA3  
DREQ3 (I)  
DACK3 (O)  
DONE3 (I/O)  
DREQ4 (I)  
PA[0]  
PA[2]  
PA[1]  
PA[5]  
PA[3]  
PA[4]  
1
1
1
1
1
1
0
1
0
0
1
0
0
0
1
0
0
1
1
1
1
1
1
1
GND  
Ñ
VDD  
GND  
Ñ
IDMA4  
DACK4 (O)  
DONE4 (I/O)  
VDD  
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Part IV. Communications Processor Module  
Table 18-14 describes parallel I/O register programming for port D (optional).  
Table 18-14. Parallel I/O Register ProgrammingÑPort D  
Channel  
Signal  
Pin  
PPARD  
PDIRD  
PODRD  
PSORD  
Default  
IDMA1  
DACK1 (O)  
PD[6]  
PD[5]  
1
1
1
0
0
1
1
1
Ñ
DONE1 (I/O)  
VDD  
18.12 IDMA Programming Examples  
These programming examples demonstrate the use of most of the different modes and  
conÞgurations of the IDMA channels.  
18.12.1 Peripheral-to-Memory Mode (60x Bus to Local Bus)ÑIDMA2  
In the example in Table 18-15, the IDMA2 channel reads 8 bytes per DREQ assertion from  
a Þxed address peripheral located on the 60x bus into the internal buffer. When there is  
enough data in the internal buffer, it writes one burst to the memory located on the local  
bus. The internal buffer size is set to 64 bytes to handle maximum transfer of a single burst.  
The IDMA2 channel asserts DONE on the last read transfer of the last BD to notify the  
peripheral that there is no data left to transfer.  
Table 18-15. Example: Peripheral-to-Memory ModeÑIDMA2  
Important Init Values  
Description  
DCM(FB) = 0  
DCM(LP) = 0  
Not in ßy-by mode.  
Transfers to memory have middle CPM request priority. The destination bus is not overloaded.  
DCM(DMA_WRAP) =  
000  
The internal buffer is 64 bytes long to support 32-byte transfers to memory on the destination  
bus (one 60x burst) on steady-state of work.  
DCM(ERM) = 1  
DCM(DT) = 0  
Transfers from peripheral are initiated by DREQ. DONE assertion is supported.  
Assertion of DONE by the peripheral causes the transfer to be terminated, after writing all the  
data in the internal buffer to memory, interrupt EDN is set to the core, IDMA channel is  
stopped. additional DREQ assertions are ignored, until START_IDMA command is issued.  
DCM(S/D) = 10  
Peripheral-to-memory mode. DONE DREQ and DACK are connected to the peripheral.  
The peripheral address are not incremented after transfers, Þxed location.  
The memory address is incremented after every transfer.  
DCM(SINC) = 0  
DCM(DINC) = 1  
DPR_BUF = 0x0DC0  
Initiated to address aligned to 64 (bit[5Ð0]= 00000).  
IBASE = IBDPTR =  
0x0030  
The current BD pointer is set to the BD table base address (aligned 16 -bits[3Ð0] = 0).  
STS = 8 (0x0008)  
Transfers from peripheral are always single 8-byte accesses.  
Transfers to memory are 32 bytes long (60x bursts) on steady-state of work.  
Peripheral is on the 60x bus.  
DTS = 32 (0x0020)  
Every BD(SDTB) = 1  
Every BD(DDTB) = 0  
Memory is on the local bus.  
MOTOROLA  
Chapter 18. SDMA Channels and IDMA Emulation  
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Part IV. Communications Processor Module  
Table 18-15. Example: Peripheral-to-Memory ModeÑIDMA2 (Continued)  
Important Init Values  
Description  
Last BD(SDN) = 1  
DONE is asserted on the last transfer from peripheral.  
Last BD(DDN) = 0  
DONE is not asserted on the last transfer to memory.  
Every BD(DL) = k*STS  
IDMR2 = 0x0300_0000  
Data length must be STS modular (divided by STS without residue).  
IDMA2 Mask register is programmed to enable EDN and BC interrupts only.  
SIMR_L = 0x0000_0200 Interrupt controller is programmed to enable interrupts from IDMA2.  
PDIRC = 0x1000_0000 Parallel I/O registers are programmed to enable:PC[1] = DREQ2; PC[3] = DACK2; PC[2] =  
PPARC = 0x7000_0000 DONE2.  
PSORC = 0x3000_0000 The peripheral signals are to be connected to these lines accordingly.  
PODRC = 0x2000_0000  
RCCR = 0x0000_0000  
IDMA2 conÞguration: DREQ is edge low-to-high. DONE is high-to-low. Request priority is  
higher than the SCCs.  
88FE = 0x0300  
IDMA2_BASE points to 0x0300 where the parameter table base address is located for IDMA2.  
CPCR = 0x22A1_0009  
START_IDMA command. IDMA2 page-01000 SBC-10101 op-1001 FLG=1.This write starts the  
channel operation.  
DMA operation description:  
START_IDMA: Initialize all parameter RAM values, wait for DREQ to open the Þrst BD. The four Þrst DREQs trigger single, 8-  
byte read transactions from the peripheral until data in the internal buffer is 32 bytes long. Then, a write transaction to  
memory is done with the size needed for alignment.  
Steady state: Every DREQ assertion triggers a read transaction of 8 bytes from the peripheral. If the data in the internal  
buffer is more than 31 bytes a write transaction to memory of 32 bytes (one local burst) follows immediately. Memory  
address is incremented constantly. Last read transaction of the last BD from the peripheral is combined with DONE  
assertion.  
STOP_IDMA: After all data in internal buffer is written to memory in one transfer, SC bit is set in IDSR (SC interrupt to the  
core is not enabled) and BD is closed. Channel is stopped until START_IDMA command is reissued.  
DONE assertion by the peripheral: All data in internal buffer is written to memory in one transfer. At the end of the transfer,  
EDN interrupt is set to hos. Additional DREQ assertions are ignored. IDMA2 channel is stopped until START_IDMA  
command is issued.  
18.12.2 Memory-to-Peripheral Fly-By Mode (Both on 60x Bus)Ñ  
IDMA3  
In the example in Table 18-16, IDMA3 transfers data from a memory device to a 4-byte  
wide peripheral, both on the 60x bus. The transfers are made by issuing 4-byte read  
transactions to the memory and asserting DACK so the peripheral samples the data from  
the bus directly. No address is dedicated for the peripheral, and no internal buffer is deÞned  
in this mode. The IDMA3 channel asserts DONE on the last read transfer of the last BD to  
notify the peripheral that there is no data left to transfer.  
Table 18-16. Example: Memory-to-Peripheral Fly-By Mode (on 60x)ÐIDMA3  
Important Init Values  
Description  
DCM[FB] = 1  
DCM[LP] = x  
Fly-by mode.  
DonÕt care. Transfer from memory to peripheral on the 60x bus is high priority.  
DCM[DMA_WRAP] = DC DonÕt care. No internal buffer is used.  
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Part IV. Communications Processor Module  
Table 18-16. Example: Memory-to-Peripheral Fly-By Mode (on 60x)ÐIDMA3 (Continued)  
Important Init Values  
Description  
Transfers from peripheral are initiated by DREQ.  
DCM[ERM] = 1  
DCM[DT] = 1  
Assertion of DONE by the peripheral terminates the transfer, interrupt EDN is set to the core,  
Current BD is closed and the next BD if valid is opened. Additional DREQ assertions cause the  
new BD to be transferred.  
DCM[S/D] = 01  
DCM[SINC] = 1.  
DCM[DINC] = 1  
DPR_BUF  
Memory-to-peripheral mode. DONE, DREQ, and DACK are connected to the peripheral.  
The memory address is incremented after every transfer.  
The memory address is incremented after every transfer.  
The IDMA transfer buffer is not used.  
IBASE = IBDPTR =  
0x0030  
The current BD pointer is set to the BD table base address (aligned 16 -bits[3Ð0]=0000).  
STS = 0x0004  
Transfers from memory to peripheral are always 4 bytes long (60x singles).  
Transfers from memory to peripheral are always 4 bytes long (60x singles).  
Memory and peripheral are on the 60x bus.  
DTS = 0x0004  
Every BD[SDTB] = 1  
Every BD[DDTB] = 1  
Last BD[SDN] = 1  
Last BD[DDN] = 1  
IDMR3 = 0x0400_0000  
Memory and peripheral are on the 60x bus.  
DONE is asserted on the last transfer.  
DONE is asserted on the last transfer.  
The IDMA3 mask register is programmed to enable the IDSR[OB] interrupt only.  
SIMR_L = 0x0000_0100 The interrupt controller is programmed to enable interrupts from IDMA3.  
PDIRA = 0x2000_0000 Parallel I/O registers are programmed to enable:PA[0] = DREQ3; PA[2] = DACK3; PA[1] =  
PPARA = 0xE000_0000 DONE3.  
PSORA = 0xE000_0000 The peripheral signals are to be connected to these lines accordingly.  
PODRA = 0x4000_0000  
RCCR = 0x0000_0080  
IDMA3 conÞguration: DREQ is level high. DONE is high to low. request priority is higher than  
the SCCs.  
89FE = 0x0300  
IDMA3_BASE points to 0x0300 where the parameter table base address is located for IDMA3.  
CPCR = 0x26C1_0009  
START_IDMA command. IDMA3 page-01001 SBC-10110 op-1001 FLG=1.This write starts the  
channel operation.  
DMA operation description:  
START_IDMA: Initialize all parameter RAM values, wait for DREQ to open the Þrst BD.  
Steady state: Every DREQ triggers a 4-byte transfer in single address transaction. DMA performs a memory read  
transaction combined with DACK assertion. Memory address is incremented constantly. Last transaction of the last BD is  
combined with DONE assertion.Another DREQ assertion after last BD complete will issue IDSR[OB] interrupt to the core.  
STOP_IDMA: BD is closed. SC bit is set in IDSR (SC interrupt to the core is not enabled).Channel is stopped until  
START_IDMA command is issued.  
DONE assertion by the peripheral: current BD is closed. IDSR[EDN] is set (but the interrupt to the core is not  
enabled).The next BD is open with the next DREQ assertion (or IDSR[OB] interrupt is set to the core if there is no other  
valid BDs).  
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Part IV. Communications Processor Module  
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Chapter 19  
Serial Communications Controllers  
(SCCs)  
190  
1T90 he MPC8260 has four serial communications controllers (SCCs), which can be  
conÞgured independently to implement different protocols for bridging functions, routers,  
and gateways, and to interface with a wide variety of standard WANs, LANs, and  
proprietary networks. An SCC has many physical interface options such as interfacing to  
TDM buses, ISDN buses, and standard modem interfaces.  
The SCCs are independent from the physical interface, but SCC logic formats and  
manipulates data from the physical interface. Furthermore, the choice of protocol is  
independent from the choice of interface. An SCC is described in terms of the protocol it  
runs. When an SCC is programmed to a certain protocol or mode, it implements  
functionality that corresponds to parts of the protocolÕs link layer (layer 2 of the OSI  
reference model). Many SCC functions are common to protocols of the following  
controllers:  
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UART, described in Chapter 20, ÒSCC UART Mode.Ó  
HDLC and HDLC bus, described in Chapter 21, ÒSCC HDLC Mode.Ó  
AppleTalk/LocalTalk, described in Chapter 25, ÒSCC AppleTalk Mode.Ó  
BISYNC, described in Chapter 22, ÒSCC BISYNC Mode.Ó  
Transparent, described in Chapter 23, ÒSCC Transparent Mode.Ó  
Ethernet, described in Chapter 24, ÒSCC Ethernet Mode.Ó  
Although the selected protocol usually applies both to the SCC transmitter and receiver, one  
half of an SCC can run transparent operations while the other runs a standard protocol  
(except Ethernet).  
Each Rx and Tx internal clock can be programmed with either an external or internal  
source. Internal clocks originate from one of eight baud rate generators (BRGs) or an  
external clock pin; see Section 15.3, ÒNMSI ConÞguration,Ó for each SCCÕs available clock  
sources. These clocks can be as fast as a 1:2 ratio of the system clock. (For example, an SCC  
internal clock can run at 12.5 MHz in a 25-MHz system.) However, an SCCÕs ability to  
support a sustained bit stream depends on the protocol as well as other factors.  
MOTOROLA  
Chapter 19. Serial Communications Controllers (SCCs)  
19-1  
   
Part IV. Communications Processor Module  
Associated with each SCC is a digital phase-locked loop (DPLL) for external clock  
recovery, which supports NRZ, NRZI, FM0, FM1, Manchester, and Differential  
Manchester. If the clock recovery function is not required (that is, synchronous  
communication), then the DPLL can be disabled, in which case only NRZ and NRZI are  
supported.  
An SCC can be connected to its own set of pins on the MPC8260. This conÞguration is  
called the non-multiplexed serial interface (NMSI) and is described in Chapter 14, ÒSerial  
Interface with Time-Slot Assigner.Ó Using NMSI, an SCC can support standard modem  
interface signals, RTS, CTS, and CD. If required, software and additional parallel I/O lines  
can be used to support additional handshake signals. Figure 19-1 shows the SCC block  
diagram.  
60x Bus  
DPLL  
and Clock  
Recovery  
TCLK  
RCLK  
Control  
Registers  
Clock  
Generator  
Peripheral Bus  
Internal Clocks  
Rx  
Data  
FIFO  
Tx  
Data  
FIFO  
Rx  
Control  
Unit  
Tx  
Control  
Unit  
Modem Lines  
Decoder  
Modem Lines  
Encoder  
RXD  
Delimiter  
Shifter  
Shifter  
Delimiter  
TXD  
Figure 19-1. SCC Block Diagram  
19.1 Features  
The following is a list of the main SCC features. (Performance Þgures assume a 25-MHz  
system clock.)  
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Implements HDLC/SDLC, HDLC bus, synchronous start/stop, asynchronous start/  
stop (UART), AppleTalk/LocalTalk, and totally transparent protocols  
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Supports 10-Mbps Ethernet/IEEE 802.3 (half- or full-duplex) on all SCCs  
Additional protocols supported through Motorola-supplied RAM microcodes:  
ProÞbus, Signaling System#7 (SS7), ATM over T1/E1 (ATOM1)  
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Additional protocols can be added in the future through the use of RAM microcodes.  
19-2  
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Part IV. Communications Processor Module  
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DPLL circuitry for clock recovery with NRZ, NRZI, FM0, FM1, Manchester, and  
Differential Manchester (also known as Differential Bi-phase-L)  
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Clocks can be derived from a baud rate generator, an external pin, or DPLL  
Data rate for asynchronous communication can be as high as 16.62 Mbps at  
133 MHz  
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Supports automatic control of the RTS, CTS, and CD modem signals  
Multi-buffer data structure for receive and send (the number of buffer descriptors  
(BDs) is limited only by the size of the internal dual-port RAMÑ8 bytes per BD)  
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Deep FIFOs (SCC send and receive FIFOs are 32 bytes each.)  
Transmit-on-demand feature decreases time to frame transmission (transmit  
latency)  
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Low FIFO latency option for send and receive in character-oriented and totally  
transparent protocols  
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¥
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Frame preamble options  
Full-duplex operation  
Fully transparent option for one half of an SCC (Rx/Tx) while another protocol  
executes on the other half (Tx/Rx)  
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Echo and local loopback modes for testing  
19.1.1 The General SCC Mode Registers (GSMR1ÐGSMR4)  
Each SCC contains a general SCC mode register (GSMR) that deÞnes options common to  
each SCC regardless of the protocol. GSMR_L contains the low-order 32 bits; GSMR_H,  
shown in Figure 19-2, contains the high-order 32 bits. Some GSMR operations are  
described in later sections.  
Bit  
Field  
Reset  
R/W  
Addr  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12 13  
14  
15  
Ñ
GDE  
0000_0000_0000_0000  
R/W  
0x11A04 (GSMR1); 0x11A24 (GSMR2); 0x11A44 (GSMR3); 0x11A64 (GSMR4)  
16 17  
TCRC  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28 29  
SYNL  
30  
31  
Field  
Reset  
R/W  
Addr  
REVD TRX TTX CDP CTSP CDS CTSS TFL RFW TXSY  
RTSM RSYN  
0000_0000_0000_0000  
R/W  
0x11A06 (GSMR1); 0x11A26 (GSMR2); 0x11A46 (GSMR3); 0x11A66 (GSMR4)  
Figure 19-2. GSMR_HÑGeneral SCC Mode Register (High Order)  
MOTOROLA  
Chapter 19. Serial Communications Controllers (SCCs)  
19-3  
       
Part IV. Communications Processor Module  
Table 19-1 describes GSMR_H Þelds.  
Table 19-1. GSMR_H Field Descriptions  
Bit  
Name  
Description  
0Ð14  
15  
Ñ
Reserved, should be cleared.  
GDE Glitch detect enable. Determines whether the SCC searches for glitches on the external Rx and Tx  
serial clock lines. Regardless of the GDE setting, a Schmitt trigger on the input lines is used to  
reduce signal noise.  
0 No glitch detection. Clear GDE if the external serial clock exceeds the limits of glitch detection logic  
(6.25 MHz assuming a 25-MHz system clock), if an internal BRG supplies the SCC clock, or if  
external clocks are used and glitch detection matters less than power consumption.  
1 Glitches can be detected and reported as maskable interrupts in the SCC event register (SCCE).  
16Ð17 TCRC Transparent CRC (valid for totally transparent channel only). Selects the frame checking provided on  
transparent channels of the SCC (either the receiver, transmitter, or both, as deÞned by TTX and  
TRX). Although this conÞguration selects a frame check type, the decision to send the frame check is  
made in the TxBD. Thus, frame checks are not needed in transparent mode and frame check errors  
generated on the receiver can be ignored.  
00 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1).  
01 CRC16 (BISYNC). (X16 + X15 + X2 + 1).  
10 32-bit CCITT CRC (Ethernet and HDLC).  
(X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 + 1).  
11 Reserved.  
18  
REVD Reverse data (valid for a totally transparent channel only)  
0 Normal operation.  
1 Reverses the bit order for totally transparent channels on this SCC (either the receiver, transmitter,  
or both) and sends the msb of each byte Þrst. Section 22.11, ÒBISYNC Mode Register (PSMR),Ó  
describes reversing bit order in a BISYNC protocol.  
19Ð20 TRX, Transparent receiver/transmitter. The receiver, transmitter, or both can use totally transparent  
TTX  
operation, regardless of GSMR_L[MODE]. For example, to conÞgure the transmitter as a UART and  
the receiver for totally transparent operations, set MODE = 0b0100 (UART), TTX = 0, and TRX = 1.  
0 Normal operation.  
1 The channel uses totally transparent mode, regardless of the protocol chosen in GSMR_L[MODE].  
For full-duplex totally transparent operation, set both TTX and TRX.  
Note that an SCC cannot operate with half in Ethernet mode and half in transparent mode. That is, if  
MODE = 0b1100 (Ethernet), erratic operation occurs unless TTX = TRX.  
21, 22 CDP, CD/CTS pulse. If this SCC is used in the TSA and is programmed in transparent mode, set CTSP  
CTSP and refer to Section 23.4.2, ÒSynchronization and the TSA,Ó for options on programming CDP.  
0 Normal operation (envelope mode). CD/CTS should envelope the frame. Negating CD/CTS during  
reception causes a CD/CTS lost error.  
1 Pulse mode. Synchronization occurs when CD/CTS is asserted; further CD/CTS transitions do not  
affect reception.  
23, 24 CDS, CD/CTS sampling. Determine synchronization characteristics of CD and CTS. If the SCC is in  
CTSS transparent mode and is used in the TSA, CDS and CTSS must be set. Also, CDS and CTSS must  
be set for loopback testing in transparent mode.  
0 CD/CTS is assumed to be asynchronous with data. It is internally synchronized by the SCC, then  
data is received (CD) or sent (CTS) after several clock delays.  
1 CD/CTS is assumed to be synchronous with data, which speeds up operation. CD or CTS must  
transition while the Rx/Tx clock is low, at which time, the transfer begins. Useful for connecting  
MPC8260 in transparent mode since the RTS of one MPC8260 can connect directly to the CD/  
CTS of another.  
19-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part IV. Communications Processor Module  
Table 19-1. GSMR_H Field Descriptions (Continued)  
Bit  
25  
Name  
Description  
TFL  
Transmit FIFO length.  
0 Normal operation. The transmit FIFO is 32 bytes.  
1 The Tx FIFO is 1 byte. This option is used with character-oriented protocols, such as UART, to  
ensure a minimum FIFO latency at the expense of performance.  
26  
RFW Rx FIFO width.  
0 Receive FIFO is 32 bits wide for maximum performance; the Rx FIFO is 32 bytes. Data is not  
normally written to receive buffers until at least 32 bits are received. This conÞguration is required  
for HDLC-type protocols and Ethernet and is recommended for high-performance transparent  
protocols.  
1 Low-latency operation. The receive FIFO is 8 bits wide, reducing the Rx FIFO to a quarter its  
normal size. This allows data to be written to the buffer as soon as a character is received, instead  
of waiting to receive 32 bits. This conÞguration must be chosen for character-oriented protocols,  
such as UART. It can also be used for low-performance, low-latency, transparent operation.  
However, it must not be used with HDLC, HDLC Bus, AppleTalk, or Ethernet because it causes  
erratic behavior.  
27  
TXSY Transmitter synchronized to the receiver. Intended for X.21 applications where the transmitted data  
must begin an exact multiple of 8-bit periods after the received data arrives.  
0 No synchronization between receiver and transmitter (default).  
1 The transmit bit stream is synchronized to the receiver. Additionally, if RSYN = 1, transmission in  
totally transparent mode does not occur until the receiver synchronizes with the bit stream and  
CTS is asserted to the SCC. Assuming CTS is asserted, transmission begins 8 clocks after the  
receiver starts receiving data.  
28Ð29 SYNL Sync length (BISYNC and transparent mode only). See the data synchronization register (DSR)  
deÞnition in Section 22.9, ÒSending and Receiving the Synchronization Sequence,Ó (BISYNC) and  
Section 23.4.1.1, ÒIn-Line Synchronization Pattern,Ó (transparent).  
00 An external sync (CD) is used instead of the sync pattern in the DSR.  
01 4-bit sync. The receiver synchronizes on a 4-bit sync pattern stored in the DSR. This sync and  
additional syncs can be stripped by programming the SCCÕs parameter RAM for character  
recognition.  
10 8-bit sync. Should be chosen along with the BISYNC protocol to implement mono-sync. The  
receiver synchronizes on an 8-bit sync pattern in the DSR.  
11 16-bit sync. Also called BISYNC.The receiver synchronizes on a 16-bit sync pattern stored in the  
DSR.  
30  
31  
RTSM RTS mode. Determines whether ßags or idles are to be sent. Can be changed on-the-ßy.  
0 Send idles between frames as deÞned by the protocol and the TEND bit. RTS is negated between  
frames (default).  
1 Send ßags/syncs between frames according to the protocol. RTS is always asserted whenever the  
SCC is enabled.  
RSYN Receive synchronization timing (totally transparent mode only).  
0 Normal operation.  
1 If CDS = 1, CD should be asserted on the second bit of the Rx frame rather than on the Þrst.  
MOTOROLA  
Chapter 19. Serial Communications Controllers (SCCs)  
19-5  
Part IV. Communications Processor Module  
Figure 19-3 shows GSMR_L.  
Bit  
Field  
Reset  
R/W  
Addr  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Ñ
EDGE  
TCI  
TSNC  
RINV TINV  
TPL  
TPP  
TEND  
TDCR  
0000_0000_0000_0000  
R/W  
0x11A00 (SCC1); 0x11A20 (SCC2); 0x11A40 (SCC3); 0x11A60 (SCC4)  
16  
17 18  
19  
20 21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
Addr  
RDCR  
RENC  
TENC  
DIAG  
ENR ENT  
MODE  
0000_0000_0000_0000  
R/W  
0x11A02 (SCC1); 0x11A22 (SCC2); 0x11A42 (SCC3); 0x11A62 (SCC4)  
Figure 19-3. GSMR_LÑGeneral SCC Mode Register (Low Order)  
Table 19-2 describes GSMR_L Þelds.  
Table 19-2. GSMR_L Field Descriptions  
Bit  
Name  
Description  
0
Ñ
Reserved, should be cleared.  
1Ð2  
EDGE Clock edge. Determines the clock edge the DPLL uses to adjust the receive sample point due to jitter  
in the received signal. Ignored in UART protocol or if the 1x clock mode is selected in RDCR.  
00 Both the positive and negative edges are used for changing the sample point (default).  
01 Positive edge. Only the positive edge of the received signal is used to change the sample point.  
10 Negative edge. Only the negative edge of the received signal is used to change the sample point.  
11 No adjustment is made to the sample point.  
3
TCI  
Transmit clock invert.  
0 Normal operation.  
1 Before it is used, the internal Tx clock (TCLK) is inverted by the SCC so it can clock data out one-  
half clock earlier (on the rising rather than the falling edge). In this case, the SCC offers a minimum  
and maximum rising clock edge-to-data speciÞcation. Data output by the SCC after the rising edge  
of an external Tx clock can be latched by the external receiver one clock cycle later on the next  
rising edge of the same Tx clock. Recommended for Ethernet, HDLC, and transparent operation  
when clock rates exceed 8 MHz to improve data setup time for the external transceiver.  
4Ð5  
TSNC Transmit sense. Determines the amount of time the internal carrier sense signal stays active after the  
last transition on RXD, indicating that the line is free. For instance, AppleTalk can use TSNC to avoid  
a spurious CS-changed (SCCE[DCC]) interrupt that would otherwise occur during the frame sync  
sequence before the opening ßags. If RDCR is conÞgured to 1´ clock mode, the delay is the greater  
of the two numbers listed. If RDCR is conÞgured to 8´, 16´, or 32´ mode, the delay is the smaller  
number.  
00 InÞnite. Carrier sense is always active (default).  
01 14- or 6.5-bit times as determined by RDCR.  
10 4- or 1.5-bit times as determined by RDCR (normally for AppleTalk).  
11 3- or 1-bit times as determined by RDCR.  
6
RINV DPLL Rx input invert data. Must be zero in HDLC bus mode or asynchronous UART mode.  
0 Do not invert.  
1 Invert data before sending it to the DPLL for reception. Used to produce FM1 from FM0 and NRZI  
space from NRZI mark or to invert the data stream in regular NRZ mode.  
19-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
Table 19-2. GSMR_L Field Descriptions (Continued)  
Bit  
Name  
Description  
7
TINV DPLL Tx input invert data. Must be zero in HDLC bus mode.  
0 Do not invert.  
1 Invert data before sending it to the DPLL for transmission. Used to produce FM1 from FM0 and  
NRZI space from NRZI mark and to invert the data stream in regular NRZ mode. In T1 applications,  
setting TINV and TEND creates a continuously inverted HDLC data stream.  
8Ð10 TPL  
Tx preamble length. Determines the length of the preamble conÞgured by the TPP bits.  
000 No preamble (default).  
001 8 bits (1 byte).  
010 16 bits (2 bytes).  
011 32 bits (4 bytes).  
100 48 bits (6 bytes). Select this setting for Ethernet operation.  
101 64 bits (8 bytes).  
110 128 bits (16 bytes).  
111 Reserved.  
11Ð12 TPP  
Tx preamble pattern. Determines what, if any, bit pattern should precede each Tx frame. The  
preamble pattern is sent before the Þrst ßag/sync of the frame. TPP is ignored in UART mode. The  
preamble length is programmed in TPL; the preamble pattern is typically sent to a receiving station  
that uses a DPLL for clock recovery. The receiving DPLL uses the regular preamble pattern to help it  
lock onto the received signal in a short, predictable time period.  
00 All zeros.  
01 Repetitive 10s. Select this setting for Ethernet operation.  
10 Repetitive 01s.  
11 All ones. Select this setting for LocalTalk operation.  
13  
TEND Transmitter frame ending. Intended for NMSI transmitter encoding of the DPLL. TEND determines  
whether TXD should idle in a high state or in an encoded ones state (high or low). It can, however, be  
used with other encodings besides NMSI.  
0 Default operation.TXD is encoded only when data is sent, including the preamble and opening and  
closing ßags/syncs. When no data is available to send, the signal is driven high.  
1 TXD is always encoded, even when idles are sent.  
14Ð15 TDCR Transmitter/receiver DPLL clock rate. If the DPLL is not used, choose 1´ mode except in  
asynchronous UART mode where 8´, 16´, or 32´ must be chosen. TDCR should match RDCR in  
16Ð17 RDCR  
most applications to allow the transmitter and receiver to use the same clock source. If an application  
uses the DPLL, the selection of TDCR/RDCR depends on the encoding/decoding. If communication  
is synchronous, select 1´. FM0/FM1, Manchester, and Differential Manchester require 8´, 16´, or  
32´. If NRZ- or NRZI-encoded communication is asynchronous (that is, clock recovery required),  
select 8´, 16´, or 32´. The 8´ option allows highest speed, whereas the 32´ option provides the  
greatest resolution.  
00 1´ clock mode. Only NRZ or NRZI encodings/decodings are allowed.  
01 8´ clock mode.  
10 16´ clock mode. Normally chosen for UART and AppleTalk.  
11 32´ clock mode.  
18Ð20 RENC Receiver decoding/transmitter encoding method. Select NRZ if DPLL is not used. RENC should equal  
TENC in most applications. However, do not use this internal DPLL for Ethernet.  
21Ð23 TENC  
000 NRZ (default setting if DPLL is not used). Required for UART (synchronous or asynchronous).  
001 NRZI Mark (set RINV/TINV also for NRZI space).  
010 FM0 (set RINV/TINV also for FM1).  
011 Reserved.  
100 Manchester.  
101 Reserved.  
110 Differential Manchester (Differential Bi-phase-L).  
111 Reserved.  
MOTOROLA  
Chapter 19. Serial Communications Controllers (SCCs)  
19-7  
Part IV. Communications Processor Module  
Table 19-2. GSMR_L Field Descriptions (Continued)  
Bit  
Name  
Description  
24Ð25 DIAG Diagnostic mode.  
00 Normal operation, CTS and CD are under automatic control. Data is received through RXD and  
transmitted through TXD. The SCC uses modem signals to enable or disable transmission and  
reception. These timings are shown in Section 19.3.5, ÒControlling SCC Timing with RTS, CTS,  
and CD.Ó  
01 Local loopback mode. Transmitter output is connected internally to the receiver input, while the  
receiver and the transmitter operate normally. The value on RXD is ignored. If enabled, data  
appears on TXD, or the parallel I/O registers can be programmed to make TXD high. RTS can also  
be programmed to be disabled in the appropriate parallel I/O register.The transmitter and receiver  
must share the same clock source, but separate CLKx pins can be used if connected to the same  
external clock source.  
If external loopback is preferred, program DIAG for normal operation and externally connect TXD  
and RXD.Then, physically connect the control signals (RTS connected to CD, and CTS grounded)  
or set the parallel I/O registers so CD and CTS are permanently asserted to the SCC by  
conÞguring the associated CTS and CD pins as general-purpose I/O.  
10 Automatic echo mode. The transmitter automatically resends received data bit-by-bit using the Rx  
clock provided. The receiver operates normally and receives data if CD is asserted. CTS is  
ignored.  
11 Loopback and echo mode. Loopback and echo operation occur simultaneously. CD and CTS are  
ignored. See the loopback bit description above for clocking requirements.  
For TDM operation, the diagnostic mode is selected by SIxMR[SDMx]; see Section 14.5.2, ÒSI Mode  
Registers (SIxMR).Ó  
26  
ENR  
Enable receive. Enables the receiver hardware state machine for this SCC.  
0 The receiver is disabled and data in the Rx FIFO is lost. If ENR is cleared during reception, the  
receiver aborts the current character.  
1 The receiver is enabled.  
ENR can be set or cleared, regardless of whether serial clocks are present. Section 19.3.8,  
ÒReconÞguring the SCCs,Ó describes how to disable/enable an SCC. Note that other tools, including  
the ENTER HUNT MODE and CLOSE RXBD commands and the E bit of the Rx BD, data provide the  
capability to control the receiver.  
27  
ENT  
Enable transmit. Enables the transmitter hardware state machine for this SCC.  
0 The transmitter is disabled. If ENT is cleared during transmission, the current character is aborted  
and TXD returns to the idle state. Data already in the Tx shift register is not sent.  
1 The transmitter is enabled.  
ENT can be set or cleared, regardless of whether serial clocks are present. Section 19.3.8,  
ÒReconÞguring the SCCs,Ó describes how to disable/enable an SCC. Note that other tools, such as  
the STOP TRANSMIT, GRACEFUL STOP TRANSMIT, and RESTART TRANSMIT commands, the freeze option  
and CTS ßow control option in UART mode, and the R bit of the TxBD, also provide the capability to  
control the transmitter.  
28Ð31 MODE Channel protocol mode. See also GSMR_H[TTX, TRX].  
0000 HDLC  
0001 Reserved  
0010 AppleTalk/LocalTalk  
0011 SS7Ñreserved for RAM microcode  
0100 UART  
0101 ProÞbusÑreserved for RAM microcode  
0110 Reserved  
0111 Reserved  
1000 BISYNC  
1001 Reserved  
101x Reserved  
1100 Ethernet  
11xx Reserved  
19-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part IV. Communications Processor Module  
19.1.2 Protocol-SpeciÞc Mode Register (PSMR)  
The protocol implemented by an SCC is selected by its GSMR_L[MODE]. Each SCC has  
an additional protocol-speciÞc mode register (PSMR) that conÞgures it speciÞcally for the  
chosen protocol. The PSMR Þelds are described in the speciÞc chapters that describe each  
protocol. PSMRs are cleared at reset. PSMRs reside at the following addresses: 0x11A08  
(PSMR1), 0x11A28 (PSMR2), 0x11A48 (PSMR3), and 0x11A68 (PSMR4).  
19.1.3 Data Synchronization Register (DSR)  
Each SCC has a data synchronization register (DSR) that speciÞes the pattern used for  
frame synchronization. The programmed value for DSR depends on the protocol:  
¥
¥
¥
¥
UARTÑDSR is used to conÞgure fractional stop bit transmission.  
BISYNC and transparentÑDSR should be programmed with the sync pattern.  
EthernetÑDSR should be programmed with 0xD555.  
HDLCÑAt reset, DSR defaults to 0x7E7E (two HDLC ßags), so it does not need to  
be written.  
Figure 19-4 shows the sync Þelds.  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
SYN1  
0111_1110  
12  
13  
14  
15  
Field  
Reset  
R/W  
SYN2  
0111_1110  
R/W  
0x11A0E (DSR1); 0x11A2E (DSR2); 0x11A4E (DSR3); 0x11A6E (DSR4)  
Addr  
Figure 19-4. Data Synchronization Register (DSR)  
19.1.4 Transmit-on-Demand Register (TODR)  
In normal operation, if no frame is being sent by an SCC, the CP periodically polls the R  
bit of the next TxBD to see if a new frame/buffer is requested. Depending on the SCC  
conÞguration, this polling occurs every 8Ð32 serial Tx clocks. The transmit-on-demand  
option, selected in the transmit-on-demand register (TODR) shown in Figure 19-5,  
shortens the latency of the Tx buffer/frame and is useful in LAN-type protocols where  
maximum inter-frame gap times are limited by the protocol speciÞcation.  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field  
Reset  
R/W  
TOD  
Ñ
0000_0000_0000_0000  
R/W  
Addr  
0x11A0C (TODR1); 0x11A2C (TODR2); 0x11A4C (TODR3); 0x11A6C (TODR4)  
Figure 19-5. Transmit-on-Demand Register (TODR)  
MOTOROLA  
Chapter 19. Serial Communications Controllers (SCCs)  
19-9  
                     
Part IV. Communications Processor Module  
The CP can be conÞgured to begin processing a new frame/buffer without waiting the  
normal polling time by setting TODR[TOD] after TxBD[R] is set. Because this feature  
favors the speciÞed TxBD, it may affect servicing of other SCC FIFOs. Therefore,  
transmitting on demand should only be used when a high-priority TxBD has been prepared  
and enough time has passed since the last g transmission. Table 19-3 describes TODR  
Þelds.  
Table 19-3. TODR Field Descriptions  
Bits Name  
Description  
0
TOD Transmit on demand.  
0 Normal operation.  
1 The CP gives high priority to the current TxBD and begins sending the frame without waiting the  
normal polling time to check the TxBDÕs R bit.TOD is cleared automatically after one serial clock, but  
transmitting on demand continues until an unprepared (R = 0) BD is reached.TOD does not need to  
be set again if new TxBDs are added to the BD table as long as older TxBDs are still being  
processed. New TxBDs are processed in order. The Þrst bit of the frame is typically clocked out 5-6  
bit times after TOD is set.  
1Ð15  
Ñ
Reserved, should be cleared.  
19.2 SCC Buffer Descriptors (BDs)  
Data associated with each SCC channel is stored in buffers and each buffer is referenced by  
a buffer descriptor (BD) that can reside anywhere in dual-port RAM. The total number of  
8-byte BDs is limited only by the size of the dual-port RAM (128 BDs/1 Kbyte). These BDs  
are shared among all serial controllersÑSCCs, SMCs, SPI, and I2C. The user deÞnes how  
the BDs are allocated among the controllers.  
Each 64-bit BD has the following structure:  
¥
The half word at offset + 0x0 contains status and control bits that control and report  
on the data transfer. These bits vary from protocol to protocol. The CPM updates the  
status bits after the buffer is sent or received.  
¥
The half word at offset + 0x2 (data length) holds the number of bytes sent or  
received.  
Ñ For an RxBD, this is the number of bytes the controller writes into the buffer. The  
CPM writes the length after received data is placed into the associated buffer and  
the buffer closed. In frame-based protocols (but not including SCC transparent  
operation), this Þeld contains the total frame length, including CRC bytes. Also,  
if a received frameÕs length, including CRC, is an exact multiple of MRBLR, the  
last BD holds no actual data but does contain the total frame length.  
Ñ For a TxBD, this is the number of bytes the controller should send from its buffer.  
Normally, this value should be greater than zero. The CPM never modiÞes this  
Þeld.  
19-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part IV. Communications Processor Module  
¥
The word at offset + 0x4 (buffer pointer) points to the beginning of the buffer in  
memory (internal or external).  
Ñ For an RxBD, the value must be a multiple of four. (word-aligned)  
Ñ For a TxBD, this pointer can be even or odd.  
Shown in Figure 19-6, the format of Tx and Rx BDs is the same in each SCC mode. Only  
the status and control bits differ for each protocol.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
Status and Control  
Data Length  
High-Order Buffer Pointer  
Low-Order Buffer Pointer  
Figure 19-6. SCC Buffer Descriptors (BDs)  
For frame-oriented protocols, a message can reside in as many buffers as necessary. Each  
buffer has a maximum length of 65,535 bytes. The CPM does not assume that all buffers of  
a single frame are currently linked to the BD table. The CPM does assume, however, that  
the unlinked buffers are provided by the core in time to be sent or received; otherwise, an  
error condition is reportedÑan underrun error when sending and a busy error when  
receiving. Figure 19-7 shows the SCC BD table and buffer structure.  
MOTOROLA  
Chapter 19. Serial Communications Controllers (SCCs)  
19-11  
 
Part IV. Communications Processor Module  
Dual-Port RAM  
External Memory  
Tx Buffer Descriptors  
Status and Control  
Buffer Length  
Buffer Pointer  
SCCx TxBD  
Table  
Tx Buffer  
Rx Buffer Descriptors  
SCCx RxBD  
Table  
Status and Control  
Buffer Length  
SCCx RxBD  
Table Pointer  
Buffer Pointer  
SCCx TxBD  
Table Pointer  
Rx Buffer  
Figure 19-7. SCC BD and Buffer Memory Structure  
In all protocols, BDs can point to buffers in the internal dual-port RAM. However, because  
dual-port RAM is used for descriptors, buffers are usually put in external RAM, especially  
if they are large.  
The CPM processes TxBDs straightforwardly; when the transmit side of an SCC is enabled,  
the CPM starts with the Þrst BD in that SCC TxBD table. Once the CPM detects that the R  
bit is set in the TxBD, it starts processing the buffer. The CPM detects that the BD is ready  
when it polls the R bit or when the user writes to the TODR. After data from the BD is put  
in the Tx FIFO, if necessary the CPM waits for the next descriptorÕs R bit to be set before  
proceeding. Thus, the CPM does no look-ahead descriptor processing and does not skip  
BDs that are not ready. When the CPM sees a BDÕs W bit (wrap) set, it returns to the start  
of the BD table after this last BD of the table is processed. The CPM clears R (not ready)  
after using a TxBD, which keeps it from being retransmitted before it is conÞrmed by the  
core. However, some protocols support a continuous mode (CM), for which R is not cleared  
(always ready).  
The CPM uses RxBDs similarly. When data arrives, the CPM performs required processing  
on the data and moves resultant data to the buffer pointed to by the Þrst BD; it continues  
until the buffer is full or an event, such as an error or end-of-frame detection, occurs. The  
buffer is then closed; subsequent data uses the next BD. If E = 0, the current buffer is not  
empty and it reports a busy error. The CPM does not move from the current BD until E is  
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Part IV. Communications Processor Module  
set by the core (the buffer is empty). After using a descriptor, the CPM clears E (not empty)  
and does not reuse a BD until it has been processed by the core. However, in continuous  
mode (CM), E remains set. When the CPM discovers a descriptorÕs W bit set (indicating it  
is the last BD in the circular BD table), it returns to the beginning of the table when it is  
time to move to the next buffer.  
19.3 SCC Parameter RAM  
Each SCC parameter RAM area begins at the same offset from each SCC base area.  
Section 19.3.1, ÒSCC Base Addresses,Ó describes the SCCÕs base addresses. The protocol-  
speciÞc portions of the SCC parameter RAM are discussed in the speciÞc protocol  
descriptions and the part that is common to all SCC protocols is shown in Table 19-4.  
Some parameter RAM values must be initialized before the SCC can be enabled. Other  
values are initialized or written by the CPM. Once initialized, most parameter RAM values  
do not need to be accessed because most activity centers around the descriptors rather than  
the parameter RAM. However, if the parameter RAM is accessed, note the following:  
¥
¥
Parameter RAM can be read at any time.  
Tx parameter RAM can be written only when the transmitter is disabledÑafter a  
STOP TRANSMIT command and before a RESTART TRANSMIT command or after the  
buffer/frame Þnishes transmitting after a GRACEFUL STOP TRANSMIT command and  
before a RESTART TRANSMIT command.  
¥
¥
Rx parameter RAM can be written only when the receiver is disabled. Note the  
CLOSE RXBD command does not stop reception, but it does allow the user to extract  
data from a partially full Rx buffer.  
See Section 19.3.8, ÒReconÞguring the SCCs.Ó  
Table 19-4 shows the parameter RAM map for all SCC protocols. Boldfaced entries must  
be initialized by the user.  
Table 19-4. SCC Parameter RAM Map for All Protocols  
1
Offset  
Name  
Width  
Description  
0x00  
0x02  
RBASE Hword Rx/TxBD table base addressÑoffset from the beginning of dual-port RAM. The BD  
tables can be placed in any unused portion of the dual-port RAM. The CPM starts BD  
TBASE Hword  
processing at the top of the table. (The user deÞnes the end of the BD table by setting  
the W bit in the last BD to be processed.) Initialize these entries before enabling the  
corresponding channel. Erratic operations occur if BD tables of active SCCs overlap.  
Values in RBASE and TBASE should be multiples of eight.  
0x04  
0x05  
RFCR  
TFCR  
Byte  
Byte  
Rx function code. See Section 19.3.2, ÒFunction Code Registers (RFCR and TFCR).Ó  
Tx function code. See Section 19.3.2, ÒFunction Code Registers (RFCR and TFCR).Ó  
MOTOROLA  
Chapter 19. Serial Communications Controllers (SCCs)  
19-13  
       
Part IV. Communications Processor Module  
Table 19-4. SCC Parameter RAM Map for All Protocols (Continued)  
0x06  
MRBLR Hword Maximum receive buffer length. DeÞnes the maximum number of bytes the MPC8260  
writes to a receive buffer before it goes to the next buffer. The MPC8260 can write fewer  
bytes than MRBLR if a condition such as an error or end-of-frame occurs. It never writes  
more bytes than the MRBLR value. Therefore, user-supplied buffers should be no  
smaller than MRBLR. MRBLR should be greater than zero for all modes. It should be a  
multiple of 4 for Ethernet and HDLC modes, and in totally transparent mode unless the  
Rx FIFO is 8-bits wide (GSMR_H[RFW] = 1).  
Note that although MRBLR is not intended to be changed while the SCC is operating, it  
can be changed dynamically in a single-cycle, 16-bit move (not two 8-bit cycles).  
Changing MRBLR has no immediate effect. To guarantee the exact Rx BD on which the  
change occurs, change MRBLR only while the receiver is disabled.  
Transmit buffer length is programmed in TxBD[Data Length] and is not affected by  
MRBLR.  
3
0x08  
0x0C  
RSTATE Word Rx internal state  
2
Word Rx internal buffer pointer . The Rx and Tx internal buffer pointers are updated by the  
SDMA channels to show the next address in the buffer to be accessed.  
0x10  
RBPTR Hword Current RxBD pointer. Points to the current BD being processed or to the next BD the  
receiver uses when it is idling. After reset or when the end of the BD table is reached,  
the CPM initializes RBPTR to the value in the RBASE. Although most applications do  
not need to write RBPTR, it can be modiÞed when the receiver is disabled or when no  
Rx buffer is in use.  
2
0x12  
Hword Rx internal byte count .The Rx internal byte count is a down-count value initialized with  
MRBLR and decremented with each byte written by the supporting SDMA channel.  
3
0x14  
0x18  
0x1C  
Word Rx temp  
3
TSTATE Word Tx internal state  
2
Word Tx internal buffer pointer . The Rx and Tx internal buffer pointers are updated by the  
SDMA channels to show the next address in the buffer to be accessed.  
0x20  
TBPTR Hword Current TxBD pointer. Points to the current BD being processed or to the next BD the  
transmitter uses when it is idling. After reset or when the end of the BD table is reached,  
the CPM initializes TBPTR to the value in the TBASE. Although most applications do not  
need to write TBPTR, it can be modiÞed when the transmitter is disabled or when no Tx  
buffer is in use (after a STOP TRANSMIT or GRACEFUL STOP TRANSMIT command is issued  
and the frame completes its transmission).  
2
0x22  
Hword Tx internal byte count . A down-count value initialized with TxBD[Data Length] and  
decremented with each byte read by the supporting SDMA channel.  
3
0x24  
0x28  
0x2C  
0x30  
Word Tx temp  
2
RCRC  
TCRC  
Word Temp receive CRC  
2
Word Temp transmit CRC  
Protocol-speciÞc area. (The size of this area depends on the protocol chosen.)  
1
From SCC base. See Section 19.3.1, ÒSCC Base Addresses.Ó  
These parameters need not be accessed for normal operation but may be helpful for debugging.  
For CP use only  
2
3
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Part IV. Communications Processor Module  
19.3.1 SCC Base Addresses  
The CPM maintains a section of RAM called the parameter RAM, which contains many  
parameters for the operation of the FCCs, SCCs, SMCs, SPI, I2C, and IDMA channels.  
SCC base addresses are described in Table 19-5.  
The exact deÞnition of the parameter RAM is contained in each protocol subsection  
describing a device that uses a parameter RAM. For example, the Ethernet parameter RAM  
is deÞned differently in some locations from the HDLC-speciÞc parameter RAM.  
Table 19-5. Parameter RAMÑSCC Base Addresses  
1
Page  
Address  
Peripheral  
Size (Bytes)  
1
0x8000  
0x8100  
0x8200  
0x8300  
SCC1  
SCC2  
SCC3  
SCC4  
256  
256  
256  
256  
2
3
4
1
Offset from RAM_Base  
19.3.2 Function Code Registers (RFCR and TFCR)  
There are eight separate function code registers for the four SCC channels, four for Rx  
buffers (RFCR1ÐRFCR4) and four for Tx buffers (TFCR1ÐTFCR4). The function code  
registers contain the transaction speciÞcation associated with SDMA channel accesses to  
external memory. Figure 19-8 shows the register format.  
Bit  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
Ñ
GBL  
BO  
TC2  
DTB  
Ñ
0000_0000_0000_0000  
R/W  
Addr  
SCCx base + 0x04 (RFCRx); SCCx base + 0x05 (TFCRx)  
Figure 19-8. Function Code Registers (RFCR and TFCR)  
MOTOROLA  
Chapter 19. Serial Communications Controllers (SCCs)  
19-15  
             
Part IV. Communications Processor Module  
Table 19-6 describes RFCRx/TFCRx Þelds.  
Table 19-6. RFCRx /TFCRx Field Descriptions  
Bits  
Name  
Description  
0Ð1  
2
Ñ
Reserved, should be cleared.  
GBL  
Global  
0 Snooping disabled.  
1 Snooping enabled.  
3Ð4  
BO  
Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-ßy,  
it takes effect at the beginning of the next frame (Ethernet, HDLC, and transparent) or at the  
beginning of the next BD.  
00 Reserved  
01 PowerPC little-endian.  
1x Big-endian or true little-endian.  
5
6
TC2  
DTB  
Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory  
access. TC[0Ð1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.  
Data bus indicator  
0 Use 60x bus for SDMA operation  
1 Use local bus for SDMA operation  
7
Ñ
Reserved, should be cleared.  
19.3.3 Handling SCC Interrupts  
To allow interrupt handling for SCC-speciÞc events, event, mask, and status registers are  
provided within each SCCÕs internal memory map area; see Table 19-7. Because interrupt  
events are protocol-dependent, event descriptions are found in the speciÞc protocol  
chapters.  
Table 19-7. SCCx Event, Mask, and Status Registers  
Register &  
Description  
IMMR Offset  
SCCEx  
SCC event register.This 16-bit register reports events recognized by any of the SCCs.When an event  
0x11A10 (SCCE1); is recognized, the SCC sets its corresponding bit in SCCE, regardless of the corresponding mask bit.  
0x11A30 (SCCE2); When the corresponding event occurs, an interrupt is signaled to the SIVEC register. Bits are cleared  
0x11A50 (SCCE3); by writing ones (writing zeros has no effect). SCCE is cleared at reset and can be read at any time.  
0x11A70 (SCCE4)  
SCCMx  
SCC mask register. The 16-bit, read/write register allows interrupts to be enabled or disabled using  
0x11A14 (SCCM1); the CPM for speciÞc events in each SCC channel. An interrupt is generated only if SCC interrupts in  
0x11A34 (SCCM2); this channel are enabled in the SIU interrupt mask register (SIMR). If an SCCM bit is zero, the CPM  
0x11A54 (SCCM3); does not proceed with interrupt handling when that event occurs. The SCCM and SCCE bit positions  
0x11A74 (SCCM4) are identical.  
SCCSx  
SCC status register. This 8-bit, read-only register allows monitoring of the real-time status of RXD.  
0x11A17 (SCCS1);  
0x11A37 (SCCS2);  
0x11A57 (SCCS3);  
0x11A77 (SCCS4)  
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Part IV. Communications Processor Module  
Follow these steps to handle an SCC interrupt:  
1. When an interrupt occurs, read SCCE to determine the interrupt sources and clear  
those SCCE bits (in most cases).  
2. Process the TxBDs to reuse them if SCCE[TX] or SCCE[TXE] = 1. If the transmit  
speed is fast or the interrupt delay is long, the SCC may have sent more than one Tx  
buffer. Thus, it is important to check more than one TxBD during interrupt handling.  
A common practice is to process all TxBDs in the handler until one is found with its  
R bit set.  
3. Extract data from the RxBD if SCCE[RX], SCCE[RXB], or SCCE[RXF] is set. As  
with transmit buffers, if the receive speed is fast or the interrupt delay is long, the  
SCC may have received more than one buffer and the handler should check more  
than one RxBD. A common practice is to process all RxBDs in the interrupt handler  
until one is found with RxBD[E] set.  
4. Execute the rÞ instruction.  
Additional information about interrupt handling can be found in Section 4.2, ÒInterrupt  
Controller.Ó  
19.3.4 Initializing the SCCs  
The SCCs require that a number of registers and parameters be conÞgured after a power-on  
reset. Regardless of the protocol used, follow these steps to initialize SCCs:  
1. Write the parallel I/O ports to conÞgure and connect the I/O pins to the SCCs.  
2. ConÞgure the parallel I/O registers to enable RTS, CTS, and CD if these signals are  
required.  
3. If the time-slot assigner (TSA) is used, the serial interface (SIx) must be conÞgured.  
If the SCC is used in NMSI mode, CMXSCR must still be initialized.  
4. Write all GSMR bits except ENT or ENR.  
5. Write the PSMR.  
6. Write the DSR.  
7. Initialize the required values for this SCCÕs parameter RAM.  
8. Initialize the transmit/receive parameters via the CP command register (CPCR).  
9. Clear out any current events in SCCE (optional).  
10.Write ones to SCCM register to enable interrupts.  
11.Set GSMR_L[ENT] and GSMR_L[ENR].  
Descriptors can have their R or E bits set at any time. Notice that the CPCR does not need  
to be accessed after a hardware reset. An SCC should be disabled and reenabled after any  
dynamic change to its parallel I/O ports or serial channel physical interface conÞguration.  
A full reset can also be implemented using CPCR[RST].  
MOTOROLA  
Chapter 19. Serial Communications Controllers (SCCs)  
19-17  
   
Part IV. Communications Processor Module  
19.3.5 Controlling SCC Timing with RTS, CTS, and CD  
When GSMR_L[DIAG] is programmed to normal operation, CD and CTS are controlled  
by the SCC. In the following subsections, it is assumed that GSMR_L[TCI] is zero,  
implying normal transmit clock operation.  
19.3.5.1 Synchronous Protocols  
RTS is asserted when the SCC data is loaded into the Tx FIFO and a falling Tx clock occurs.  
At this point, the SCC starts sending data once appropriate conditions occur on CTS. In all  
cases, the Þrst data bit is the start of the opening ßag, sync pattern, or preamble.  
Figure 19-9 shows that the delay between RTS and data is 0 bit times, regardless of  
GSMR_H[CTSS]. This operation assumes that CTS is already asserted to the SCC or that  
CTS is reprogrammed to be a parallel I/O line, in which case CTS to the SCC is always  
asserted. RTS is negated one clock after the last bit in the frame.  
TCLK  
TXD  
(Output)  
First Bit of Frame Data  
Last Bit of Frame Data  
RTS  
(Output)  
CTS  
(Input)  
NOTE:  
1. A frame includes opening and closing flags and syncs, if present in the protocol.  
Figure 19-9. Output Delay from RTS Asserted for Synchronous Protocols  
When RTS is asserted, if CTS is not already asserted, delays to the Þrst data bit depend on  
when CTS is asserted. Figure 19-10 shows that the delay between CTS and the data can be  
approximately 0.5 to 1 bit times or 0 bit times, depending on GSMR_H[CTSS].  
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Part IV. Communications Processor Module  
TCLK  
TXD  
(Output)  
First Bit of Frame Data  
Last Bit of Frame Data  
RTS  
(Output)  
CTS  
(Input)  
CTS Sampled Low Here  
NOTE:  
1. GSMR_H[CTSS] = 0. CTSP is a donÕt care.  
TCLK  
TXD  
(Output)  
First Bit of Frame Data  
Last Bit of Frame Data  
RTS  
(Output)  
CTS  
(Input)  
NOTE:  
1. GSMR_H[CTSS] = 1. CTSP is a donÕt care.  
Figure 19-10. Output Delay from CTS Asserted for Synchronous Protocols  
If CTS is programmed to envelope data, negating it during frame transmission causes a  
CTS lost error. Negating CTS forces RTS high and Tx data to become idle. If  
GSMR_H[CTSS] is zero, the SCC must sample CTS before a CTS lost is recognized;  
otherwise, the negation of CTS immediately causes the CTS lost condition. See  
Figure 19-11.  
MOTOROLA  
Chapter 19. Serial Communications Controllers (SCCs)  
19-19  
 
Part IV. Communications Processor Module  
TCLK  
TXD  
(Output)  
Data Forced High  
RTS Forced High  
First Bit of Frame Data  
RTS  
(Output)  
CTS  
(Input)  
CTS Sampled Low Here  
CTS Sampled High Here  
CTS Lost Signaled in Frame BD  
NOTE:  
1. GSMR_H[CTSS] = 0. CTSP=0 or no CTS lost can occur.  
TCLK  
TXD  
(Output)  
Data Forced High  
RTS Forced High  
First Bit of Frame Data  
RTS  
(Output)  
CTS  
(Input)  
CTS Lost Signaled in Frame BD  
NOTE:  
1. GSMR_H[CTSS] = 1. CTSP=0 or no CTS lost can occur.  
Figure 19-11. CTS Lost in Synchronous Protocols  
Note that if GSMR_H[CTSS] = 1, CTS transitions must occur while the Tx clock is low.  
Reception delays are determined by CD as shown in Figure 19-12. If GSMR_H[CDS] is  
zero, CD is sampled on the rising Rx clock edge before data is received. If GSMR_H[CDS]  
is 1, CD transitions cause data to be immediately gated into the receiver.  
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Part IV. Communications Processor Module  
RCLK  
RXD  
(Input)  
First Bit of Frame Data  
Last Bit of Frame Data  
CD Sampled High Here  
CD  
(Input)  
CD Sampled Low Here  
NOTE:  
1. GSMR_H[CDS] = 0. CDP=0.  
2. If CD is negated prior to the last bit of the receive frame, CD lost is signaled in the frame BD.  
3. If CDP=1, CD lost cannot occur and CD negation has no effect on reception.  
RCLK  
RXD  
(Input)  
First Bit of Frame Data  
Last Bit of Frame Data  
CD  
(Input)  
CD Assertion Immediately  
Gates Reception  
CD Negation Immediately  
Halts Reception  
NOTE:  
1. GSMR_H[CDS] = 1. CDP=0.  
2. If CD is negated prior to the last bit of the receive frame, CD lost is signaled in the frame BD.  
3. If CDP=1, CD lost cannot occur and CD negation has no effect on reception.  
Figure 19-12. Using CD to Control Synchronous Protocol Reception  
If CD is programmed to envelope the data, it must remain asserted during frame  
transmission or a CD lost error occurs. Negation of CD terminates reception. If  
GSMR_H[CDS] is zero, CD must be sampled by the SCC before a CD lost error is  
recognized; otherwise, the negation of CD immediately causes the CD lost condition.  
If GSMR_H[CDS] is set, all CD transitions must occur while the Rx clock is low.  
19.3.5.2 Asynchronous Protocols  
In asynchronous protocols, RTS is asserted when SCC data is loaded into the Tx FIFO and  
a falling Tx clock occurs. CD and CTS can be used to control reception and transmission  
in the same manner as the synchronous protocols. The Þrst bit sent in an asynchronous  
protocol is the start bit of the Þrst character. In addition, the UART protocol has an option  
for CTS ßow control as described in Chapter 20, ÒSCC UART Mode.Ó  
¥
¥
¥
If CTS is already asserted when RTS is asserted, transmission begins in two  
additional bit times.  
If CTS is not already asserted when RTS is asserted and GSMR_H[CTSS] = 0,  
transmission begins in three additional bit times.  
If CTS is not already asserted when RTS is asserted and GSMR_H[CTSS] = 1,  
transmission begins in two additional bit times.  
MOTOROLA  
Chapter 19. Serial Communications Controllers (SCCs)  
19-21  
   
Part IV. Communications Processor Module  
19.3.6 Digital Phase-Locked Loop (DPLL) Operation  
Each SCC channel includes a digital phase-locked loop (DPLL) for recovering clock  
information from a received data stream. For applications that provide a direct clock source  
to the SCC, the DPLL can be bypassed by selecting 1x mode for GSMR_L[RDCR, TDCR].  
If the DPLL is bypassed, only NRZ or NRZI encodings are available. The DPLL must not  
be used when an SCC is programmed to Ethernet and is optional for other protocols.  
Figure 19-13 shows the DPLL receiver block; Figure 19-14 shows the transmitter block  
diagram.  
RENC  
RDCR  
Recovered Clock  
HSRCLK  
0
1
RCLK  
Carrier SNC  
Noise  
EDGE  
TSNC  
DPLL  
Receiver  
S
Hunting  
RINV  
1x Mode  
Decoded Data  
RXD  
HSRCLK  
RINV  
0
1
SCCR Data  
RXD  
S
RENC  
¹
NRZI  
1x Mode  
D
Q
HSRCLK  
CLK  
Figure 19-13. DPLL Receiver Block Diagram  
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MPC8260 PowerQUICC II UserÕs Manual  
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Part IV. Communications Processor Module  
TENC  
TDCR  
Recovered Clock  
0
HSTCLK  
TCLK  
TXEN  
1
TEND  
DPLL  
Transmitter  
S
HSTCLK  
1x Mode  
D
Q
HSTCLK  
CLK  
Encoded Data  
SCCT Data  
TINV  
0
TXD  
1
0
1
D
Q
S
HSTCLK  
CLK  
S
1x Mode  
TENC = NRZI  
Figure 19-14. DPLL Transmitter Block Diagram  
The DPLL can be driven by one of the baud rate generator outputs or an external clock,  
CLKx. In the block diagrams, this clock is labeled HSRCLK/HSTCLK. The HSRCLK/  
HSTCLK should be approximately 8x, 16x, or 32x the data rate, depending on the coding  
chosen. The DPLL uses this clock, along with the data stream, to construct a data clock that  
can be used as the SCC Rx and/or Tx clock. In all modes, the DPLL uses the input clock to  
determine the nominal bit time. If the DPLL is bypassed, HSRCLK/HSTCLK is used  
directly as RCLK/TCLK.  
At the beginning of operation, the DPLL is in search mode, whereas the Þrst transition  
resets the internal DPLL counter and begins DPLL operation. While the counter is  
counting, the DPLL watches the incoming data stream for transitions; when one is detected,  
the DPLL adjusts the count to produce an output clock that tracks incoming bits.  
The DPLL has a carrier-sense signal that indicates when data transfers are on RXD. The  
carrier-sense signal asserts as soon as a transition is detected on RXD; it negates after the  
programmed number of clocks in GSMR_L[TSNC] when no transitions are detected.  
To prevent itself from locking on the wrong edges and to provide fast synchronization, the  
DPLL should receive a preamble pattern before it receives the data. In some protocols, the  
preceding ßags or syncs can function as a preamble; others use the patterns in Table 19-8.  
When transmission occurs, the SCC can generate preamble patterns, as programmed in  
GSMR_L[TPP, TPL].  
MOTOROLA  
Chapter 19. Serial Communications Controllers (SCCs)  
19-23  
 
Part IV. Communications Processor Module  
Table 19-8. Preamble Requirements  
Decoding Method  
NRZI Mark  
Preamble Pattern  
All zeros  
Minimum Preamble Length Required  
8-bit  
8-bit  
8-bit  
8-bit  
8-bit  
8-bit  
NRZI Space  
FM0  
All ones  
All ones  
FM1  
All zeros  
101010...10  
All ones  
Manchester  
Differential Manchester  
The DPLL can also be used to invert the data stream of a transfer. This feature is available  
in all encodings, including standard NRZ format. Also, when the transmitter is idling, the  
DPLL can either force TXD high or continue encoding the data supplied to it.  
The DPLL is used for UART encoding/decoding, which gives the option of selecting the  
divide ratio in the UART decoding process (8´, 16´, or 32´). Typically, 16´ is used.  
Note the 1:2 system clock/serial clock ratio does not apply when the DPLL is used to  
recover the clock in the 8´, 16´, or 32´ modes. Synchronization occurs internally after the  
DPLL generates the Rx clock. Therefore, even the fastest DPLL clock generation (the 8´  
option) easily meets the required 1:2 ratio clocking limit.  
19.3.6.1 Encoding Data with a DPLL  
Each SCC contains a DPLL unit that can be programmed to encode and decode the SCC  
data as NRZ, NRZI Mark, NRZI Space, FM0, FM1, Manchester, and Differential  
Manchester. Figure 19-15 shows the different encoding methods.  
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Part IV. Communications Processor Module  
Data  
NRZ  
0
1
1
0
0
1
NRZI Mark  
NRZI Space  
FM0  
FM1  
Manchester  
Differential  
Manchester  
Figure 19-15. DPLL Encoding Examples  
If the DPLL is not needed, NRZ or NRZI codings can be selected in GSMR_L[RENC,  
TENC]. Coding deÞnitions are shown in Table 19-9.  
Table 19-9. DPLL Codings  
Coding  
NRZ  
Description  
A one is represented by a high level for the duration of the bit and a zero is represented by a low level.  
NRZI Mark A one is represented by no transition at all. A zero is represented by a transition at the beginning of the  
bit (the level present in the preceding bit is reversed).  
NRZI Space A one is represented by a transition at the beginning of the bit (the level present in the preceding bit is  
reversed). A zero is represented by no transition at all.  
FM0  
A one is represented by a transition only at the beginning of the bit. A zero is represented by a transition  
at the beginning of the bit and another transition at the center of the bit.  
FM1  
A one is represented by a transition at the beginning of the bit and another transition at the center of the  
bit. A zero is represented by a transition only at the beginning of the bit.  
Manchester A one is represented by a high-to-low transition at the center of the bit. A zero is represented by a low to  
high transition at the center of the bit. In both cases there may be a transition at the beginning of the bit  
to set up the level required to make the correct center transition.  
Differential A one is represented by a transition at the center of the bit with the opposite direction from the transition  
Manchester at the center of the preceding bit. A zero is represented by a transition at the center of the bit with the  
same polarity from the transition at the center of the preceding bit.  
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Chapter 19. Serial Communications Controllers (SCCs)  
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Part IV. Communications Processor Module  
19.3.7 Clock Glitch Detection  
Clock glitches cause problems for many communications systems, and they may go  
undetected by the system. Systems that supply an external clock to a serial channel are often  
susceptible to glitches from noise, connecting or disconnecting the physical cable from the  
application board, or excessive ringing on a clock line. A clock glitch occurs when more  
than one edge occurs in a time period that violates the minimum high or low time  
speciÞcation of the input clock.  
The SCCs on the MPC8260 have a special circuit designed to detect glitches and alert the  
system of a problem at the physical layer. The glitch-detect circuit is not a speciÞcation test;  
if a circuit does not meet the SCCÕs input clocking speciÞcations, erroneous data may not  
be detected or false glitch indications can occur. Regardless of whether the DPLL is used,  
the received clock is passed through a noise Þlter that eliminates any noise spikes that affect  
a single sample. This sampling is enabled using GSMR_H[GDE].  
If a spike is detected, a maskable Rx or Tx glitched clock interrupt is generated in  
SCCEx[GLR,GLT]. Although the receiver or transmitter can be reset or allowed to continue  
operation, statistics on clock glitches should be kept for evaluation to help in debugging,  
especially during prototype testing.  
19.3.8 ReconÞguring the SCCs  
The proper reconÞguration sequence must be followed for SCC parameters that cannot be  
changed dynamically. For instance, the internal baud rate generators allow on-the-ßy  
changes, but the DPLL-related GSMR does not. The steps in the following sections show  
how to disable, reconÞgure and re-enable an SCC to ensure that buffers currently in use are  
properly closed before reconÞguring the SCC and that subsequent data goes to or from new  
buffers according to the new conÞguration.  
Modifying parameter RAM does not require the SCC to be fully disabled. See the  
parameter RAM description for when values can be changed. To disable all peripheral  
controllers, set CPCR[RST] to reset the entire CPM.  
19.3.8.1 General ReconÞguration Sequence for an SCC Transmitter  
An SCC transmitter can be reconÞgured by following these general steps:  
1. If the SCC is sending data, issue a STOP TRANSMIT command. Transmission should  
stop smoothly. If the SCC is not transmitting (no TxBDs are ready or the GRACEFUL  
STOP TRANSMIT command has been issued and completed) or the INIT TX  
PARAMETERS command is issued, the STOP TRANSMIT command is not required.  
2. Clear GSMR_L[ENT] to disable the SCC transmitter and put it in reset state.  
3. Modify SCC Tx parameters or parameter RAM. To switch protocols or restore the  
initial Tx parameters, issue an INIT TX PARAMETERS command.  
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Part IV. Communications Processor Module  
4. If an INIT TX PARAMETERS command was not issued in step 3, issue a RESTART  
TRANSMIT command.  
5. Set GSMR_L[ENT]. Transmission begins using the TxBD pointed to by TBPTR,  
assuming the R bit is set.  
19.3.8.2 Reset Sequence for an SCC Transmitter  
The following steps reinitialize an SCC transmit parameters to the reset state:  
1. Clear GSMR_L[ENT].  
2. Make any modiÞcations then issue the INIT TX PARAMETERS command.  
3. Set GSMR_L[ENT].  
19.3.8.3 General ReconÞguration Sequence for an SCC Receiver  
An SCC receiver can be reconÞgured by following these steps:  
1. Clear GSMR_L[ENR]. The SCC receiver is now disabled and put in a reset state.  
2. Modify SCC Rx parameters or parameter RAM. To switch protocols or restore Rx  
parameters to their initial state, issue an INIT RX PARAMETERS command.  
3. If the INIT RX PARAMETERS command was not issued in step 2, issue an ENTER HUNT  
MODE command.  
4. Set GSMR_L[ENR]. Reception begins using the RxBD pointed to by RBPTR,  
assuming the E bit is set.  
19.3.8.4 Reset Sequence for an SCC Receiver  
To reinitialize the SCC receiver to the state it was in after reset, follow these steps:  
1. Clear GSMR_L[ENR].  
2. Make any modiÞcations then issue the INIT RX PARAMETERS command.  
3. Set GSMR_L[ENR].  
19.3.8.5 Switching Protocols  
To switch an SCCÕs protocol without resetting the board or affecting other SCCs, follow  
these steps:  
1. Clear GSMR_L[ENT, ENR].  
2. Make protocol changes in the GSMR and additional parameters then issue the INIT  
TX and RX PARAMETERS command to initialize both Tx and Rx parameters.  
3. Set GSMR_L[ENT, ENR] to enable the SCC with the new protocol.  
19.3.9 Saving Power  
To save power when not in use, an SCC can be disabled by clearing GSMR_L[ENT, ENR].  
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Chapter 19. Serial Communications Controllers (SCCs)  
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MPC8260 PowerQUICC II UserÕs Manual  
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Chapter 20  
SCC UART Mode  
200  
2T00 he universal asynchronous receiver transmitter (UART) protocol is commonly used to  
send low-speed data between devices. The term asynchronous is used because it is not  
necessary to send clocking information along with the data being sent. UART links are  
typically 38400 baud or less and are character-based. Asynchronous links are used to  
connect terminals with other devices. Even where synchronous communications are  
required, the UART is often used as a local port to run board debugger software. The  
character format of the UART protocol is shown in Figure 20-1.  
UART TCLK  
8x, 16x, or 32x  
(Not to scale)  
UART TXD  
Start  
Bit  
5, 6, 7, or 8 data bits with the  
least significant bit first  
Addr Parity  
Bit Bit  
9/16 to 2  
stop bits  
(Optional)  
Figure 20-1. UART Character Format  
Because the transmitter and receiver operate asynchronously, there is no need to connect  
the transmit and receive clocks. Instead, the receiver oversamples the incoming data stream  
(usually by a factor of 16) and uses some of these samples to determine the bit value.  
Traditionally, the middle 3 of the 16 samples are used. Two UARTs can communicate using  
this system if the transmitter and receiver use the same parameters, such as the parity  
scheme and character length.  
When data is not sent, a continuous stream of ones is sent (idle condition). Because the start  
bit is always a zero, the receiver can detect when real data is once again on the line. UART  
speciÞes an all-zeros break character, which ends a character transfer sequence.  
The most popular protocol that uses asynchronous characters is the RS-232 standard, which  
speciÞes baud rates, handshaking protocols, and mechanical/electrical details. Another  
popular format is RS-485, which deÞnes a balanced line system allowing longer cables than  
RS-232 links. Even synchronous protocols like HDLC are sometimes deÞned to run over  
asynchronous links. The ProÞbus standard extends UART protocol to include LAN-  
oriented features such as token passing.  
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Chapter 20. SCC UART Mode  
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Part IV. Communications Processor Module  
All standards provide handshaking signals, but some systems require only three physical  
linesÑTx data, Rx data, and ground. Many proprietary standards have been built around  
the UARTÕs asynchronous character frame, some of which implement a multidrop  
conÞguration where multiple stations, each with a speciÞc address, can be present on a  
network. In multidrop mode, frames of characters are broadcast with the Þrst character  
acting as a destination address. To accommodate this, the UART frame is extended one bit  
to distinguish address characters from normal data characters.  
In synchronous UART (isochronous operation), a separate clock signal is explicitly  
provided with the data. Start and stop bits are present in synchronous UART, but  
oversampling is not required because the clock is provided with each bit.  
The general SCC mode register (GSMR) is used to conÞgure an SCC channel to function  
in UART mode, which provides standard serial I/O using asynchronous character-based  
(start-stop) protocols with RS-232C-type lines. Using standard asynchronous bit rates and  
protocols, an SCC UART controller can communicate with any existing RS-232-type  
device and provides a serial communications port to other microprocessors and terminals  
(either locally or via modems). The independent transmit and receive sections, whose  
operations are asynchronous with the core, send data from memory (either internal or  
external) to TXD and receive data from RXD. The UART controller supports a multidrop  
mode for master/slave operations with wake-up capability on both the idle signal and  
address bit. It also supports synchronous operation where a clock (internal or external) must  
be provided with each bit received.  
20.1 Features  
The following list summarizes main features of an SCC UART controller:  
¥
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Flexible message-based data structure  
Implements synchronous and asynchronous UART  
Multidrop operation  
Receiver wake-up on idle line or address bit  
Receive entire messages into buffers as indicated by receiver idle timeout or by  
control character reception  
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¥
¥
¥
¥
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Eight control character comparison  
Two address comparison in multidrop conÞgurations  
Maintenance of four 16-bit error counters  
Received break character length indication  
Programmable data length (5Ð8 bits)  
Programmable fractional stop bit lengths (from 9/16 to 2 bits) in transmission  
Capable of reception without a stop bit  
Even/odd/force/no parity generation and check  
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Frame error, noise error, break, and idle detection  
Transmit preamble and break sequences  
Freeze transmission option with low-latency stop  
20.2 Normal Asynchronous Mode  
In normal asynchronous mode, the receive shift register receives incoming data on RXDx.  
Control bits in the UART mode register (PSMR) deÞne the length and format of the UART  
character. Bits are received in the following order:  
1. Start bit  
2. 5Ð8 data bits (lsb Þrst)  
3. Address/data bit (optional)  
4. Parity bit (optional)  
5. Stop bits  
The receiver uses a clock 8´, 16´, or 32´ faster than the baud rate and samples each bit of  
the incoming data three times around its center. The value of the bit is determined by the  
majority of those samples; if all do not agree, the noise indication counter (NOSEC) in  
parameter RAM is incremented. When a complete character has been clocked in, the  
contents of the receive shift register are transferred to the receive FIFO before proceeding  
to the receive buffer. The CPM ßags UART events, including reception errors, in SCCE and  
the RxBD status and control Þelds.  
The SCC can receive fractional stop bits. The next characterÕs start bit can begin any time  
after the three middle samples are taken. The UART transmit shift register sends outgoing  
data on TXDx. Data is then clocked synchronously with the transmit clock, which may have  
either an internal or external source. Characters are sent lsb Þrst. Only the data portion of  
the UART frame is stored in the buffers because start and stop bits are generated and  
stripped by the SCC. A parity bit can be generated in transmission and checked during  
reception; although it is not stored in the buffer, its value can be inferred from the bufferÕs  
reporting mechanism. Similarly, the optional address bit is not stored in the transmit or  
receive buffer, but is supplied in the BD itself. Parity generation and checking includes the  
optional address bit. GSMR_H[RFW] must be set for an 8-bit receive FIFO in the UART  
receiver.  
20.3 Synchronous Mode  
In synchronous mode, the controller uses a 1´ data clock for timing. The receive shift  
register receives incoming data on RXDx synchronous with the clock. The bit length and  
format of the serial character are deÞned by the control bits in the PSMR in the same way  
as in asynchronous mode. When a complete byte has been clocked in, the contents of the  
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Chapter 20. SCC UART Mode  
20-3  
       
Part IV. Communications Processor Module  
receive shift register are transferred to the receive FIFO before proceeding to the receive  
buffer. The CPM ßags UART events, including reception errors, in SCCE and the RxBD  
status and control Þelds. GSMR_H[RFW] must be set for an 8-bit receive FIFO.  
The synchronous UART transmit shift register sends outgoing data on TXDx. Data is then  
clocked synchronously with the transmit clock, which can have an internal or external  
source.  
20.4 SCC UART Parameter RAM  
For UART mode, the protocol-speciÞc area of the SCC parameter RAM is mapped as in  
Table 20-1.  
Table 20-1. UART-Specific SCC Parameter RAM Memory Map  
1
Offset  
Name  
Width  
Description  
0x30  
0x38  
Ñ
DWord Reserved  
MAX_IDL  
Hword Maximum idle characters. When a character is received, the receiver begins  
counting idle characters. If MAX_IDL idle characters are received before the next  
data character, an idle timeout occurs and the buffer is closed, generating a  
maskable interrupt request to the core to receive the data from the buffer. Thus,  
MAX_IDL offers a way to demarcate frames. To disable the feature, clear  
MAX_IDL. The bit length of an idle character is calculated as follows: 1 + data  
length (5Ð9) + 1 (if parity is used) + number of stop bits (1Ð2). For 8 data bits, no  
parity, and 1 stop bit, the character length is 10 bits.  
0x3A  
0x3C  
IDLC  
Hword Temporary idle counter. Holds the current idle count for the idle timeout process.  
IDLC is a down-counter and does not need to be initialized or accessed.  
BRKCR  
Hword Break count register (transmit). Determines the number of break characters the  
transmitter sends.The transmitter sends a break character sequence when a STOP  
TRANSMIT command is issued. For 8 data bits, no parity, 1 stop bit, and 1 start bit,  
each break character consists of 10 zero bits.  
16  
Hword User-initialized,16-bit (moduloÐ2 ) counters incremented by the CP.  
0x3E  
0x40  
0x42  
0x44  
0x46  
PAREC  
FRMEC  
NOSEC  
BRKEC  
BRKLN  
PAREC counts received parity errors.  
FRMEC counts received characters with framing errors.  
Hword  
NOSEC counts received characters with noise errors.  
BRKEC counts break conditions on the signal. A break condition can last for  
hundreds of bit times, yet BRKEC is incremented only once during that period.  
Hword  
Hword  
Hword Last received break length. Holds the length of the last received break character  
sequence measured in character units. For example, if RXDx is low for 20 bit times  
and the deÞned character length is 10 bits, BRKLN = 0x002, indicating that the  
break sequence is at least 2 characters long. BRKLN is accurate to within one  
character length.  
0x48  
0x4A  
UADDR1  
UADDR2  
Hword UART address character 1/2. In multidrop mode, the receiver provides automatic  
address recognition for two addresses. In this case, program the lower order bytes  
Hword  
of UADDR1 and UADDR2 with the two preferred addresses.  
0x4C  
RTEMP  
Hword Temp storage  
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Part IV. Communications Processor Module  
Table 20-1. UART-Specific SCC Parameter RAM Memory Map (Continued)  
0x4E  
TOSEQ  
Hword Transmit out-of-sequence character. Inserts out-of-sequence characters, such as  
XOFF and XON, into the transmit stream. The TOSEQ character is put in the Tx  
FIFO without affecting a Tx buffer in progress. See Section 20.11, ÒInserting  
Control Characters into the Transmit Data Stream.Ó  
0x50  
0x52  
0x54  
0x56  
0x58  
0x5A  
0x5C  
0x5E  
0x60  
CHARACTER1 Hword Control character 1Ð8.These characters deÞne the Rx control characters on which  
interrupts can be generated.  
CHARACTER2 Hword  
CHARACTER3 Hword  
CHARACTER4 Hword  
CHARACTER5 Hword  
CHARACTER6 Hword  
CHARACTER7 Hword  
CHARACTER8 Hword  
RCCM  
Hword Receive control character mask. Used to mask comparison of CHARACTER1Ð8  
so classes of control characters can be deÞned. A one enables the comparison,  
and a zero masks it.  
0x62  
0x64  
RCCR  
Hword Receive control character register. Used to hold the last rejected control character  
(not written to the Rx buffer). Generates a maskable interrupt. If the core does not  
process the interrupt and read RCCR before a new control character arrives, the  
previous control character is overwritten.  
RLBC  
Hword Receive last break character. Used in synchronous UART when PSMR[RZS] = 1;  
holds the last break character pattern. By counting zeros in RLBC, the core can  
measure break length to a one-bit resolution. Read RLBC by counting the zeros  
written from bit 0 to where the Þrst one was written. RLBC = 0b001xxxxxxxxxxxxx  
indicates two zeros; 0b1xxxxxxxxxxxxxxx indicates no zeros.  
Note that RLBC can be used in combination with BRKLN above to calculate the  
number of bits in the break sequence: (BRKLN * character length) + (number of  
zeros in RLBC).  
1
From SCC base. See Section 19.3.1, ÒSCC Base Addresses.Ó  
20.5 Data-Handling Methods: Character- or Message-  
Based  
An SCC UART controller uses the same BD table and buffer structures as the other  
protocols and supports both multibuffer, message-based and single-buffer, character-based  
operation.  
For character-based transfers, each character is sent with stop bits and parity and received  
into separate 1-byte buffers.A maskable interrupt is generated when each buffer is received.  
In a message-based environment, transfers can be made on entire messages rather than on  
individual characters. To simplify programming and save processor overhead, a message is  
transferred as a linked list of buffers without core intervention. For example, before  
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Chapter 20. SCC UART Mode  
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Part IV. Communications Processor Module  
handling input data, a terminal driver may wait for an end-of-line character or an idle  
timeout rather than be interrupted when each character is received. Conversely, ASCII Þles  
can be sent as messages ending with an end-of-line character.  
When receiving messages, up to eight control characters can be conÞgured to mark the end  
of a message or generate a maskable interrupt without being stored in the buffer. This option  
is useful when ßow control characters such as XON or XOFF are needed but are not part  
of the received message. See Section 20.9, ÒReceiving Control Characters.Ó  
20.6 Error and Status Reporting  
Overrun, parity, noise, and framing errors are reported via the BDs and/or error counters in  
the UART parameter RAM. Signal status is indicated in the status register; a maskable  
interrupt is generated when status changes.  
20.7 SCC UART Commands  
The transmit commands in Table 20-2 are issued to the CP command register (CPCR).  
Table 20-2. Transmit Commands  
Command  
Description  
STOP  
After a hardware or software reset and a channel is enabled in the GSMR, the transmitter starts polling  
the Þrst BD in the TxBD table every 8 Tx clocks. STOP TRANSMIT disables character transmission. If the  
SCC receives STOP TRANSMIT as a message is being sent, the message is aborted. The transmitter  
Þnishes sending data transferred to its FIFO and stops. The TBPTR is not advanced. The UART  
transmitter sends a programmable break sequence and starts sending idles. The number of break  
characters in the sequence (which can be zero) should be written to BRKCR in the parameter RAM  
before issuing this command.  
TRANSMIT  
GRACEFUL  
STOP  
Used to stop transmitting smoothly. The transmitter stops after the current buffer has been completely  
sent or immediately if no buffer is being sent. SCCE[GRA] is set once transmission stops, then the  
UART Tx parameters, including the TxBD, can be modiÞed.TBPTR points to the next TxBD in the table.  
Transmission begins once the R bit of the next BD is set and a RESTART TRANSMIT command is issued.  
TRANSMIT  
RESTART  
TRANSMIT  
Enables transmission. The controller expects this command after it disables the channel in its PSMR,  
after a STOP TRANSMIT command, after a GRACEFUL STOP TRANSMIT command, or after a transmitter  
error. Transmission resumes from the current BD.  
INIT TX Resets the transmit parameters in the parameter RAM. Issue only when the transmitter is disabled.  
PARAMETERS Note that INIT TX AND RX PARAMETERS resets both Tx and Rx parameters.  
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Part IV. Communications Processor Module  
Receive commands are described in Table 20-3.  
Table 20-3. Receive Commands  
Command  
Description  
ENTER HUNT Forces the receiver to close the RxBD in use and enter hunt mode. After a hardware or software reset,  
MODE  
once an SCC is enabled in the GSMR, the receiver is automatically enabled and uses the Þrst BD in the  
RxBD table. If a message is in progress, the receiver continues receiving in the next BD. In multidrop  
hunt mode, the receiver continually scans the input data stream for the address character.When it is not  
in multidrop mode, it waits for the idle sequence (one character of idle). Data present in the Rx FIFO is  
not lost when this command is executed.  
CLOSE RXBD Forces the SCC to close the RxBD in use and use the next BD for subsequent received data. If the SCC  
is not in the process of receiving data, no action is taken.  
Note that in an SCC UART controller, CLOSE RXBD functions like ENTER HUNT MODE but does not need to  
receive an idle character to continue receiving.  
INIT RX Resets the receive parameters in the parameter RAM. Should be issued when the receiver is disabled.  
PARAMETERS Note that INIT TX AND RX PARAMETERS resets both Tx and Rx parameters.  
20.8 Multidrop Systems and Address Recognition  
In multidrop systems, more than two stations can be on a network, each with a speciÞc  
address. Figure 20-2 shows two examples of this conÞguration. Frames made up of many  
characters can be broadcast as long as the Þrst character is the destination address. The  
UART frame is extended by one bit to distinguish an address character from standard data  
characters. Programmed in PSMR[UM], the controller supports the following two  
multidrop modes:  
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Automatic multidrop modeÑThe controller checks the incoming address character  
and accepts subsequent data only if the address matches one of two user-deÞned  
values. The two 16-bit address registers, UADDR1 and UADDR2, support address  
recognition. Only the lower 8 bits are used so the upper 8 bits should be cleared; for  
addresses less than 8 bits, unused high-order bits should also be cleared. The  
incoming address is checked against UADDR1 and UADDR2. When a match  
occurs, RxBD[AM] indicates whether UADDR1 or UADDR2 matched.  
Manual multidrop modeÑThe controller receives all characters. An address  
character is always written to a new buffer and can be followed by data characters.  
User software performs the address comparison.  
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Chapter 20. SCC UART Mode  
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1
2
3
4
+ V  
Tx  
Rx  
Tx  
Rx  
Tx  
Rx  
Tx  
Rx  
R
Master  
Slave 1  
Slave 2  
Slave 3  
+ V  
Tx  
Rx  
Tx  
Rx  
Tx  
Rx  
Tx  
Rx  
R
UADDR1  
UADDR2  
PAODR  
Choose wired-or operation in the port A  
open-drain register to allow multiple transmit  
pins to be directly connected  
Two 8-bit addresses can be automatically  
recognized in either configuration  
Figure 20-2. Two UART Multidrop Configurations  
20.9 Receiving Control Characters  
The UART receiver can recognize special control characters used in a message-based  
environment. Eight control characters can be deÞned in a control character table in the  
UART parameter RAM. Each incoming character is compared to the table entries using a  
mask (the received control character mask, RCCM) to strip donÕt cares. If a match occurs,  
the received control character can either be written to the receive buffer or rejected.  
If the received control character is not rejected, it is written to the receive buffer. The receive  
buffer is then automatically closed to allow software to handle end-of-message characters.  
Control characters that are not part of the actual message, such as XOFF, can be rejected.  
Rejected characters bypass the receive buffer and are written directly to the received control  
character register (RCCR), which triggers maskable interrupt.  
The 16-bit entries in the control character table support control character recognition. Each  
entry consists of the control character, a valid bit (end of table), and a reject bit. See  
Figure 20-3.  
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1
Offset  
0x50  
0x52  
0
E
E
1
R
R
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Ñ
Ñ
CHARACTER1  
CHARACTER2  
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
0x5E  
0x60  
0x62  
E
1
R
1
Ñ
Ñ
CHARACTER8  
RCCM  
Ñ
RCCR  
1
From SCCx base address  
Figure 20-3. Control Character Table  
Table 20-4 describes the data structure used in control character recognition.  
Table 20-4. Control Character Table, RCCM, and RCCR Descriptions  
Offset Bits  
Name  
Description  
0x50Ð  
0x5E  
0
1
E
R
End of table. In tables with eight control characters, E is always 0.  
0 This entry is valid.  
1 The entry is not valid and is not used.  
Reject character.  
0 A matching character is not rejected but is written into the Rx buffer, which is  
then closed. If RxBD[I] is set, the buffer closing generates a maskable interrupt  
through SCCE[RX]. A new buffer is opened if more data is in the message.  
1 A matching character is written to RCCR and not to the Rx buffer. A maskable  
interrupt is generated through SCCE[CCR]. The current Rx buffer is not closed.  
2Ð7  
Ñ
Reserved  
8Ð15 CHARACTERn Control character values 1Ð8. DeÞnes control characters to be compared to the  
incoming character. For characters smaller than 8 bits, the most signiÞcant bits  
should be zero.  
0x60  
0Ð1  
0b11  
Must be set. Used to mark the end of the control character table in case eight  
characters are used. Setting these bits ensures correct operation during control  
character recognition.  
2Ð7  
Ñ
Reserved  
8Ð15 RCCM  
Received control character mask. Used to mask the comparison of  
CHARACTERn. Each RCCM bit corresponds to the respective bit of  
CHARACTERn and decodes as follows.  
0 Ignore this bit when comparing the incoming character to CHARACTERn.  
1 Use this bit when comparing the incoming character to CHARACTERn.  
0x62  
0Ð7  
Ñ
Reserved  
8Ð15 RCCR  
Received control character register. If the newly arrived character matches and is  
rejected from the buffer (R = 1), the PIP controller writes the character into the  
RCCR and generates a maskable interrupt. If the core does not process the  
interrupt and read RCCR before a new control character arrives, the previous  
control character is overwritten.  
MOTOROLA  
Chapter 20. SCC UART Mode  
20-9  
   
Part IV. Communications Processor Module  
20.10 Hunt Mode (Receiver)  
A UART receiver in hunt mode remains deactivated until an idle or address character is  
recognized, depending on PSMR[UM]. A receiver is forced into hunt mode by issuing an  
ENTER HUNT MODE command.  
The receiver aborts any message in progress when ENTER HUNT MODE is issued. When the  
message is Þnished, the receiver is reenabled by detecting the idle line (one idle character)  
or by the address bit of the next message, depending on PSMR[UM]. When a receiver in  
hunt mode receives a break sequence, it increments BRKEC and generates a BRK interrupt  
condition.  
20.11 Inserting Control Characters into the Transmit  
Data Stream  
The SCC UART transmitter can send out-of-sequence, ßow-control characters like XON  
and XOFF. The controller polls the transmit out-of-sequence register (TOSEQ), shown in  
Figure 20-4, whenever the transmitter is enabled for UART operation, including during a  
UART freeze operation, UART buffer transmission, and when no buffer is ready for  
transmission. The TOSEQ character (in CHARSEND) is sent at a higher priority than the  
other characters in the transmit buffer, but does not preempt characters already in the  
transmit FIFO. This means that the XON or XOFF character may not be sent for eight or  
four (SCC) character times. To reduce this latency, set GSMR_H[TFL] to decrease the  
FIFO size to one character before enabling the transmitter.  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field  
Reset  
R/W  
Ñ
REA  
I
CT  
Ñ
A
CHARSEND  
0000_0000_0000_0000  
R/W  
Addr  
SCC base + 0x4E  
Figure 20-4. Transmit Out-of-Sequence Register (TOSEQ)  
Table 20-5 describes TOSEQ Þelds.  
Table 20-5. TOSEQ Field Descriptions  
Bit  
Name  
Description  
0Ð1  
2
Ñ
Reserved, should be cleared.  
REA  
Ready. Set when the character is ready for transmission. Remains 1 while the character is  
being sent. The CP clears this bit after transmission.  
3
4
I
Interrupt. If this bit is set, transmission completion is ßagged in the event register (SCCE[TX] is  
set), triggering a maskable interrupt to the core.  
CT  
Clear-to-send lost. Operates only if the SCC monitors CTS (GSMR_L[DIAG]). The CP sets this  
bit if CTS negates when the TOSEQ character is sent. If CTS negates and the TOSEQ  
character is sent during a buffer transmission, the TxBD[CT] status bit is also set.  
20-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
             
Part IV. Communications Processor Module  
Table 20-5. TOSEQ Field Descriptions (Continued)  
Bit  
Name  
Description  
5Ð6  
7
Ñ
Reserved, should be cleared.  
Address. Setting this bit indicates an address character for multidrop mode.  
A
8Ð15 CHARSEND Character send. Contains the character to be sent. Any 5- to 8-bit character value can be sent  
in accordance with the UART conÞguration. The character should be placed in the lsbs of  
CHARSEND. This value can be changed only while REA = 0.  
20.12 Sending a Break (Transmitter)  
A break is an all-zeros character with no stop bit that is sent by issuing a STOP TRANSMIT  
command. The SCC Þnishes transmitting outstanding data, sends a programmable number  
of break characters (determined by BRKCR), and reverts to idle or sends data if a RESTART  
TRANSMIT command is given before completion. When the break code is complete, the  
transmitter sends at least one high bit before sending more data, to guarantee recognition  
of a valid start bit. Because break characters do not preempt characters in the transmit FIFO,  
they may not be sent for eight (SCC) or four (SCC) character times. To reduce this latency,  
set GSMR_H[TFL] to decrease the FIFO size to one character before enabling the  
transmitter.  
20.13 Sending a Preamble (Transmitter)  
Sending a preamble sequence of consecutive ones ensures that a line is idle before sending  
a message. If the preamble bit TxBD[P] is set, the SCC sends a preamble sequence (idle  
character) before sending the buffer. For example, for 8 data bits, no parity, 1 stop bit, and  
1 start bit, a preamble of 10 ones is sent before the Þrst character in the buffer.  
20.14 Fractional Stop Bits (Transmitter)  
The asynchronous UART transmitter, shown in Figure 20-5, can be programmed to send  
fractional stop bits. The FSB Þeld in the data synchronization register (DSR) determines  
the fractional length of the last stop bit to be sent. FSB can be modiÞed at any time. If two  
stop bits are sent, only the second is affected. Idle characters are always sent as full-length  
characters.  
Bit  
0
Ñ
0
1
2
3
4
5
Ñ
1
6
Ñ
1
7
Ñ
0
8
Ñ
0
9
Ñ
1
10  
Ñ
1
11  
Ñ
1
12  
Ñ
1
13  
Ñ
1
14  
Ñ
1
15  
Ñ
0
Field  
Reset  
R/W  
FSB  
1111  
R/W  
Addr  
Figure 20-5. Asynchronous UART Transmitter  
MOTOROLA  
Chapter 20. SCC UART Mode  
20-11  
         
Part IV. Communications Processor Module  
Table 20-6 describes DSR Þelds.  
Table 20-6. DSR Fields Descriptions  
Bit  
Name  
Description  
0
Ñ
0b0  
1Ð4  
FSB  
Fractional stop bits. For 16´ oversampling:  
1111 Last transmitted stop bit 16/16. Default value after reset.  
1110 Last transmitted stop bit 15/16.  
É
1000 Last transmitted stop bit 9/16.  
0xxx Invalid. Do not use.  
For 32´ oversampling:  
1111 Last transmitted stop bit 32/32. Default value after reset.  
1110 Last transmitted stop bit 31/32.  
É
0000 Last transmitted stop bit 17/32.  
For 8´ oversampling:  
1111 Last transmitted stop bit 8/8. Default value after reset.  
1110 Last transmitted stop bit 7/8.  
1101 Last transmitted stop bit 6/8.  
1100 Last transmitted stop bit 5/8.  
10xx Invalid. Do not use.  
0xxx Invalid. Do not use.  
The UART receiver can always receive fractional stop bits. The next characterÕs start bit can begin  
any time after the three middle samples have been taken.  
5Ð6  
7Ð8  
9Ð14  
15  
Ñ
Ñ
Ñ
Ñ
0b11  
0b00  
0b111111  
0b0  
20.15 Handling Errors in the SCC UART Controller  
The UART controller reports character reception and transmission error conditions via the  
BDs, the error counters, and the SCCE. Modem interface lines can be monitored by the port  
C pins. Transmission errors are described in Table 20-7.  
Table 20-7. Transmission Errors  
Error  
Description  
CTS Lost  
during  
Character  
When CTS negates during transmission, the channel stops after Þnishing the current character. The  
CP sets TxBD[CT] and generates the TX interrupt if it is not masked. The channel resumes  
transmission after the RESTART TRANSMIT command is issued and CTS is asserted.  
Transmission Note that if CTS is used, the UART also offers an asynchronous ßow control option that does not  
generate an error. See the description of PSMR[FLC] in Table 20-9.  
20-12  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part IV. Communications Processor Module  
Reception errors are described in Table 20-8.  
Table 20-8. Reception Errors  
Error  
Description  
Overrun  
Occurs when the channel overwrites the previous character in the Rx FIFO with a new character, losing  
the previous character.The channel then writes the new character to the buffer, closes it, sets RxBD[OV],  
and generates an RX interrupt if not masked. In automatic multidrop mode, the receiver enters hunt mode  
immediately.  
CD Lost  
during  
If this error occurs and the channel is using this pin to automatically control reception, the channel  
terminates character reception, closes the buffer, sets RxBD[CD], and generates the RX interrupt if not  
Character masked. This error has the highest priority. The last character in the buffer is lost and other errors are not  
Reception checked. In automatic multidrop mode, the receiver enters the hunt mode immediately.  
Parity  
Noise  
Idle  
When a parity error occurs, the channel writes the received character to the buffer, closes the buffer, sets  
RxBD[PR], and generates the RX interrupt if not masked. The channel also increments the parity error  
counter PAREC. In automatic multidrop mode, the receiver enters hunt mode immediately.  
A noise error occurs when the three samples of a bit are not identical.When this error occurs, the channel  
writes the received character to the buffer, proceeds normally, but increments the noise error counter  
NOSEC. Note that this error does not occur in synchronous mode.  
If the UART is receiving data and gets an idle character (all ones), the channel begins counting  
Sequence consecutive idle characters received. If MAX_IDL is reached, the buffer is closed and an RX interrupt is  
Receive  
generated if not masked. If no buffer is open, this event does not generate an interrupt or any status  
information.The internal idle counter (IDLC) is reset every time a character is received.To disable the idle  
sequence function, clear MAX_IDL.  
Framing  
The UART reports a framing errors when it receives a character with no stop bit, regardless of the mode.  
The channel writes the received character to the buffer, closes it, sets RxBD[FR], generates the RX  
interrupt if not masked, increments FRMEC, but does not check parity for this character. In automatic  
multidrop mode, the receiver immediately enters hunt mode. If the UART allows data with no stop bits  
(PSMR[RZS] = 1) when in synchronous mode (PSMR[SYN] = 1), framing errors are reported but  
reception continues assuming the unexpected zero is the start bit of the next character; in this case, the  
user may ignore a reported framing error until multiple framing errors occur within a short period.  
Break  
When the Þrst break sequence is received, the UART increments the break error counter BRKEC. It  
Sequence updates BRKLN when the sequence completes. After the Þrst 1 is received, the UART sets SCCE[BRKE],  
which generates an interrupt if not masked. If the UART is receiving characters when it receives a break,  
it closes the Rx buffer, sets RxBD[BR], and sets SCCE[RX], which can generate an interrupt if not  
masked. If PSMR[RZS] = 1 when the UART is in synchronous mode, a break sequence is detected after  
two successive break characters are received.  
20.16 UART Mode Register (PSMR)  
For UART mode, the SCC protocol-speciÞc mode register (PSMR) is called the UART  
mode register. Many bits can be modiÞed while the receiver and transmitter are enabled.  
Figure 20-6 shows the PSMR in UART mode.  
MOTOROLA  
Chapter 20. SCC UART Mode  
20-13  
       
Part IV. Communications Processor Module  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
Ñ
11  
12  
13  
14  
15  
Field  
Reset  
R/W  
FLC SL  
CL  
UM  
FRZ RZS SYN DRT  
PEN  
RPM  
TPM  
0
R/W  
Addr  
0x11A08 (PSMR1); 0x11A28 (PSMR2); 0x11A48 (PSMR3); 0x11A68 (PSMR4)  
Figure 20-6. Protocol-Specific Mode Register for UART (PSMR)  
Table 20-9 describes PSMR UART Þelds.  
Table 20-9. PSMR UART Field Descriptions  
Bit  
Name  
Description  
0
FLC  
Flow control.  
0 Normal operation. The GSMR and port C registers determine the mode of CTS.  
1 Asynchronous ßow control. When CTS is negated, the transmitter stops at the end of the current  
character. If CTS is negated past the middle of the current character, the next full character is sent  
before transmission stops. When CTS is asserted again, transmission continues where it left off  
and no CTS lost error is reported. Only idle characters are sent while CTS is negated.  
1
SL  
CL  
Stop length. Selects the number of stop bits the SCC sends. SL can be modiÞed on-the-ßy. The  
receiver is always enabled for one stop bit unless the SCC UART is in synchronous mode and  
PSMR[RZS] is set. Fractional stop bits are conÞgured in the DSR.  
0 One stop bit.  
1 Two stop bits.  
2Ð3  
Character length. Determines the number of data bits in the character, not including optional parity or  
multidrop address bits. If a character is less than 8 bits, most-signiÞcant bits are received as zeros  
and are ignored when the character is sent. CL can be modiÞed on-the-ßy.  
00 5 data bits  
01 6 data bits  
10 7 data bits  
11 8 data bits  
4Ð5  
UM  
UART mode. Selects the asynchronous channel protocol. UM can be modiÞed on-the-ßy.  
00 Normal UART operation. Multidrop mode is disabled and idle-line wake-up mode is selected.The  
UART receiver leaves hunt mode by receiving an idle character (all ones).  
01 Manual multidrop mode. An additional address/data bit is sent with each character. Multidrop  
asynchronous modes are compatible with the MC68681 DUART, MC68HC11 SCI, DSP56000  
SCI, and Intel 8051 serial interface. The receiver leaves hunt mode when the address/data bit is  
a one, indicating the received character is an address that all inactive processors must process.  
The controller receives the address character and writes it to a new buffer. The core then  
compares the written address with its own address and decides whether to ignore or process  
subsequent characters.  
10 Reserved.  
11 Automatic multidrop mode. The CPM compares the address of an incoming address character  
with UADDRx parameter RAM values; subsequent data is accepted only if a match occurs.  
6
FRZ  
Freeze transmission. Allows the UART transmitter to pause and later continue from that point.  
0 Normal operation. If the buffer was previously frozen, it resumes transmission from the next  
character in the same buffer that was frozen.  
1 The SCC completes transmission of any data already transferred to the Tx FIFO (the number of  
characters depends on GSMR_H[TFL]) and then freezes. After FRZ is cleared, transmission  
resumes from the next character.  
20-14  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
Table 20-9. PSMR UART Field Descriptions (Continued)  
Bit  
Name  
Description  
7
RZS  
Receive zero stop bits.  
0 The receiver operates normally, but at least one stop bit is needed between characters. A framing  
error is issued if a stop bit is missing. Break status is set if an all-zero character is received with a  
zero stop bit.  
1 ConÞgures the receiver to receive data without stop bits. Useful in V.14 applications where SCC  
UART controller data is supplied synchronously and all stop bits of a particular character can be  
omitted for cross-network rate adaptation. RZS should be set only if SYN is set. The receiver  
continues if a stop bit is missing. If the stop bit is a zero, the next bit is considered the Þrst data bit  
of the next character. A framing error is issued if a stop bit is missing, but a break status is reported  
only after two consecutive break characters have no stop bits.  
8
9
SYN  
DRT  
Synchronous mode.  
0 Normal asynchronous operation. GSMR_L[TENC,RENC] must select NRZ and GSMR_L[TDCR,  
RDCR] select either 8´, 16´, or 32´. 16´ is recommended for most applications.  
1 Synchronous SCC UART controller using 1´ clock (isochronous UART operation).  
GSMR_L[TENC, RENC] must select NRZ and GSMR_L[RDCR, TDCR] select 1´ mode. A bit is  
transferred with each clock and is synchronous to the clock, which can be internal or external.  
Disable receiver while transmitting.  
0 Normal operation.  
1 While the SCC is sending data, the internal RTS disables and gates the receiver. Useful for a  
multidrop conÞguration in which the user does not want to receive its own transmission. For  
multidrop UART mode, set the BDsÕ preamble bit, TxBD[P].  
10  
11  
Ñ
Reserved, should be cleared.  
PEN  
Parity enable.  
0 No parity.  
1 Parity is enabled and determined by the parity mode bits.  
12Ð13, RPM, Receiver/transmitter parity mode. Selects the type of parity check the receiver/transmitter performs;  
14Ð15 TPM  
can be modiÞed on-the-ßy. Receive parity errors can be ignored but not disabled.  
00 Odd parity. If a transmitter counts an even number of ones in the data word, it sets the parity bit  
so an odd number is sent. If a receiver receives an even number, a parity error is reported.  
01 Low parity (space parity). A transmitter sends a zero in the parity bit position. If a receiver does  
not read a 0 in the parity bit, a parity error is reported.  
10 Even parity. Like odd parity, the transmitter adjusts the parity bit, as necessary, to ensure that the  
receiver receives an even number of one bits; otherwise, a parity error is reported.  
11 High parity (mark parity). The transmitter sends a one in the parity bit position. If the receiver  
does not read a 1 in the parity bit, a parity error is reported.  
20.17 SCC UART Receive Buffer Descriptor (RxBD)  
The CPM uses RxBDs to report on each buffer received. The CPM closes the current buffer,  
generates a maskable interrupt, and starts receiving data into the next buffer after one of the  
following occurs:  
¥
¥
¥
¥
A user-deÞned control character is received.  
An error occurs during message processing.  
A full receive buffer is detected.  
A MAX_IDL number of consecutive idle characters is received.  
MOTOROLA  
Chapter 20. SCC UART Mode  
20-15  
   
Part IV. Communications Processor Module  
¥
¥
An ENTER HUNT MODE or CLOSE RXBD command is issued.  
An address character is received in multidrop mode. The address character is written  
to the next buffer for a software comparison.  
Figure 20-7 shows an example of how RxBDs are used in receiving.  
MRBLR = 8 Bytes for this SCC  
Rx BD 0  
ID  
Buffer  
Byte 1  
Byte 2  
E
0
Status  
Length  
0
0008  
Buffer Full  
Pointer  
32-Bit Buffer Pointer  
8 Bytes  
etc.  
Byte 8  
Rx BD 1  
ID  
Buffer  
Byte 9  
Byte 10  
E
0
Status  
Length  
1
0002  
8 Bytes  
Idle Time-Out  
Occurred  
Pointer  
32-Bit Buffer Pointer  
Empty  
Rx BD 2  
ID  
Buffer  
Byte 1  
E
0
FR  
1
Status  
Length  
0
0004  
Byte 2  
Byte 4 has  
Framing Error  
Pointer  
32-Bit Buffer Pointer  
Byte 3  
8 Bytes  
Byte 4 Error!  
Empty  
Rx BD 3  
Buffer  
Byte 5  
E
1
Status  
Length  
XXXX  
Additional Bytes  
will be Stored Unless  
Idle Count Expires  
(MAX_IDL)  
8 Bytes  
Pointer  
32-Bit Buffer Pointer  
Reception  
Still in Progress  
with this Buffer  
10 Characters  
5 Characters  
Long Idle Period  
Characters  
Received by UART  
Fourth Character  
has Framing Error!  
Present  
Time  
Time  
Figure 20-7. SCC UART Receiving using RxBDs  
20-16  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part IV. Communications Processor Module  
Figure 20-8 shows the SCC UART RxBD.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
Ñ
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
E
Ñ
W
I
C
A
CM  
ID  
AM  
Ñ
BR  
FR  
PR  
OV  
CD  
Data Length  
Rx Buffer Pointer  
Figure 20-8. SCC UART Receive Buffer Descriptor (RxBD)  
Table 20-10 describes RxBD status and control Þelds.  
Table 20-10. SCC UART RxBD Status and Control Field Descriptions  
Bits Name  
Description  
0
E
Empty.  
0 The buffer is full or reception was aborted due to an error. The core can read or write to any Þelds of  
this BD. The CPM does not reuse this BD while E = 0.  
1 The buffer is not full. The CPM controls this BD and buffer. The core should not modify this BD.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (last buffer descriptor in the BD table).  
0 Not the last descriptor in the table.  
1 Last descriptor in the table. After this buffer is used, the CPM receives incoming data using the BD  
pointed to by RBASE. The number of BDs in this table is programable and determined only by the W  
bit and overall space constraints of the dual-port RAM.  
3
I
Interrupt.  
0 No interrupt is generated after this buffer is Þlled.  
1 The CP sets SCCE[RX] when this buffer is completely Þlled by the CPM, indicating the need for the  
core to process the buffer. Setting SCCE[RX] causes an interrupt if not masked.  
4
5
C
A
Control character.  
0 This buffer does not contain a control character.  
1 The last byte in this buffer matches a user-deÞned control character.  
Address.  
0 The buffer contains only data.  
1 For manual multidrop mode, A indicates the Þrst byte of this buffer is an address byte. Software should  
perform address comparison. In automatic multidrop mode, A indicates the buffer contains a message  
received immediately after an address matched UADDR1 or UADDR2.The address itself is not written  
to the buffer but is indicated by the AM bit.  
6
CM  
Continuous mode.  
0 Normal operation. The CPM clears E after this BD is closed.  
1 The CPM does not clear E after this BD is closed, allowing the buffer to be overwritten when the CPM  
accesses this BD again. E is cleared if an error occurs during reception, regardless of CM.  
7
8
ID  
Buffer closed on reception of idles.The buffer is closed because a programmable number of consecutive  
idle sequences (MAX_IDL) was received.  
AM  
Address match. SigniÞcant only if the address bit is set and automatic multidrop mode is selected in  
PSMR[UM]. After an address match, AM identiÞes which user-deÞned address character was matched.  
0 The address matched the value in UADDR2.  
1 The address matched the value in UADDR1.  
9
Ñ
Reserved, should be cleared.  
MOTOROLA  
Chapter 20. SCC UART Mode  
20-17  
   
Part IV. Communications Processor Module  
Table 20-10. SCC UART RxBD Status and Control Field Descriptions (Continued)  
Bits Name  
Description  
10  
11  
BR  
FR  
Break received. Set when a break sequence is received as data is being received into this buffer.  
Framing error. Set when a character with a framing error (a character without a stop bit) is received and  
located in the last byte of this buffer. A new Rx buffer is used to receive subsequent data.  
12  
PR  
Parity error. Set when a character with a parity error is received and located in the last byte of this buffer.  
A new Rx buffer is used to receive subsequent data.  
13  
14  
15  
Ñ
Reserved, should be cleared.  
OV  
CD  
Overrun. Set when a receiver overrun occurs during reception.  
Carrier detect lost. Set when the carrier detect signal is negated during reception.  
Section 19.2, ÒSCC Buffer Descriptors (BDs),Ó describes the data length and buffer pointer  
Þelds.  
20.18 SCC UART Transmit Buffer Descriptor (TxBD)  
The CPM uses BDs to conÞrm transmission and indicate error conditions so the core knows  
that buffers have been serviced. Figure 20-9 shows the SCC UART TxBD.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
R
Ñ
W
I
CR  
A
CM  
P
NS  
Ñ
CT  
Data Length  
Tx Buffer Pointer  
Figure 20-9. SCC UART Transmit Buffer Descriptor (TxBD)  
Table 20-11 describes TxBD status and control Þelds.  
Table 20-11. SCC UART TxBD Status and Control Field Descriptions  
Bit Name  
Description  
0
R
Ready.  
0 The buffer is not ready. This BD and buffer can be modiÞed. The CPM automatically clears R after  
the buffer is sent or an error occurs.  
1 The user-prepared buffer is waiting to begin transmission or is being transmitted. Do not modify the  
BD once R is set.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (last buffer descriptor in TxBD table).  
0 Not the last BD in the table.  
1 Last BD in the table. After this buffer is used, the CPM sends data using the BD pointed to by  
TBASE.The number of TxBDs in this table is determined only by the W bit and space constraints of  
the dual-port RAM.  
20-18  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part IV. Communications Processor Module  
Table 20-11. SCC UART TxBD Status and Control Field Descriptions (Continued)  
Bit Name  
Description  
3
I
Interrupt.  
0 No interrupt is generated after this buffer is processed.  
1 SCCE[TX] is set after this buffer is processed by the CPM, which can cause an interrupt.  
4
CR  
Clear-to-send report.  
0 The next buffer is sent with no delay (assuming it is ready), but if a CTS lost condition occurs,  
TxBD[CT] may not be set in the correct TxBD or may not be set at all. Asynchronous ßow control,  
however, continues to function normally.  
1 Normal CTS lost error reporting and three bits of idle are sent between consecutive buffers.  
5
6
A
Address. Valid only in multidrop modeÑautomatic or manual.  
0 This buffer contains only data.  
1 This buffer contains address characters. All data in this buffer is sent as address characters.  
CM  
Continuous mode.  
0 Normal operation. The CPM clears R after this BD is closed.  
1 The CPM does not clear R after this BD is closed, allowing the buffer to be resent next time the  
CPM accesses this BD. However, R is cleared by transmission errors, regardless of CM.  
7
8
P
Preamble.  
0 No preamble sequence is sent.  
1 Before sending data, the controller sends an idle character consisting of all ones. If the data length  
of this BD is zero, only a preamble is sent.  
NS  
No stop bit or shaved stop bit sent.  
0 Normal operation. Stop bits are sent with all characters in this buffer.  
1 If PSMR[SYN] = 1, data in this buffer is sent without stop bits. If SYN = 0, the stop bit is shaved,  
depending on the DSR setting; see Section 20.14, ÒFractional Stop Bits (Transmitter).Ó  
9Ð14  
15  
Ñ
Reserved, should be cleared.  
CT  
CTS lost. The CPM writes this status bit after sending the associated buffer.  
0 CTS remained asserted during transmission.  
1 CTS negated during transmission.  
The data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer  
Descriptors (BDs).Ó  
20.19 SCC UART Event Register (SCCE) and Mask  
Register (SCCM)  
The SCC event register (SCCE) is used to report events recognized by the UART channel  
and to generate interrupts. When an event is recognized, the controller sets the  
corresponding SCCE bit. Interrupts can be masked in the UART mask register (SCCM),  
which has the same format as SCCE. Setting a mask bit enables the corresponding SCCE  
interrupt; clearing a bit masks it. Figure 20-10 shows example interrupts that can be  
generated by the SCC UART controller.  
MOTOROLA  
Chapter 20. SCC UART Mode  
20-19  
     
Part IV. Communications Processor Module  
Characters  
Received by UART  
10 Characters  
Time  
Line Idle  
RXD  
CD  
Line Idle  
Break  
UART SCCE  
Events  
CD  
IDL  
RX  
CCR  
IDL  
RX  
IDL BRKS  
BRKE IDL CD  
Notes:  
1. The first RX event assumes Rx buffers are 6 bytes each.  
2. The second IDL event occurs after an all-ones character is received.  
3. The second RX event position is programmable based on the MAX_IDL value.  
4. The BRKS event occurs after the first break character is received.  
5. The CD event must be programmed in the port C parallel I/O, not in the SCC itself.  
Legend:  
A receive control character defined not to be stored in the Rx buffer.  
Characters  
Transmitted by UART  
7 Characters  
TXD  
Line Idle  
Line Idle  
RTS  
CTS  
UART SCCE  
Events  
CTS  
TX  
CTS  
Notes:  
1. TX event assumes all seven characters were put into a single buffer and TxBD[CR]=1.  
2. The CTS event must be programmed in the port C parallel I/O, not in the SCC itself.  
Figure 20-10. SCC UART Interrupt Event Example  
SCCE bits are cleared by writing ones; writing zeros has no effect. Unmasked bits must be  
cleared before the CPM clears an internal interrupt request. Figure 20-11 shows SCCE/  
SCCM for UART operation.  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
Ñ
12  
13  
14  
15  
Field  
Reset  
R/W  
Ñ
GLR GLT  
Ñ
AB  
IDL GRA BRKE BRKS  
CCR BSY TX  
RX  
0000_0000_0000_0000  
R/W  
Addr  
0x11A10 (SCCE1); 0x11A30 (SCCE2); 0x11A50 (SCCE3); 0x11A70 (SCCE4)  
0x11A14 (SCCM1); 0x11A34 (SCCM2); 0x11A54 (SCCM3); 0x11A74 (SCCM4)  
Figure 20-11. SCC UART Event Register (SCCE) and Mask Register (SCCM)  
20-20  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
Table 20-12 describes SCCE Þelds for UART mode.  
Table 20-12. SCCE/SCCM Field Descriptions for UART Mode  
Bit Name  
Description  
0Ð2  
3
Ñ
Reserved, should be cleared.  
GLR  
GLT  
Ñ
Glitch on receive. Set when the SCC encounters an Rx clock glitch.  
Glitch on transmit. Set when the SCC encounters a Tx clock glitch.  
Reserved, should be cleared.  
4
5
6
AB  
Autobaud. Set when an autobaud lock is detected.The core should rewrite the baud rate generator with  
the precise divider value. See Chapter 16, ÒBaud-Rate Generators (BRGs).Ó  
7
8
IDL  
Idle sequence status changed. Set when the channel detects a change in the serial line. The lineÕs real-  
time status can be read in SCCS[ID]. Idle is entered when a character of all ones is received; it is exited  
when a zero is received.  
GRA  
Graceful stop complete. Set as soon as the transmitter Þnishes any buffer in progress after a GRACEFUL  
STOP TRANSMIT command is issued. It is set immediately if no buffer is in progress.  
9
BRKE Break end. Set when an idle bit is received after a break sequence.  
10  
BRKS Break start. Set when the Þrst character of a break sequence is received. Multiple BRKS events are not  
received if a long break sequence is received.  
11  
12  
Ñ
Reserved, should be cleared.  
CCR  
Control character received and rejected. Set when a control character is recognized and stored in the  
receive control character register RCCR.  
13  
BSY  
Busy. Set when a character is received and discarded due to a lack of buffers. In multidrop mode, the  
receiver automatically enters hunt mode; otherwise, reception continues when a buffer is available.The  
latest point that an RxBD can be changed to empty and guarantee avoiding the busy condition is the  
middle of the stop bit of the Þrst character to be stored in that buffer.  
14  
15  
TX  
RX  
Tx event. Set when a buffer is sent. If TxBD[CR] = 1, TX is set no sooner than when the last stop bit of  
the last character in the buffer begins transmission. If TxBD[CR] = 0, TX is set after the last character is  
written to the Tx FIFO. TX also represents a CTS lost error; check TxBD[CT].  
Rx event. Set when a buffer is received, which is no sooner than the middle of the Þrst stop bit of the  
character that caused the buffer to close. Also represents a general receiver error (overrun, CD lost,  
parity, idle sequence, and framing errors); the RxBD status and control Þelds indicate the speciÞc error.  
20.20 SCC UART Status Register (SCCS)  
The SCC UART status register (SCCS), shown in Figure 20-12, monitors the real-time  
status of RXD.  
Bit  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
Ñ
ID  
0000_0000_0000_0000  
R
Addr  
0x11A17 (SCCS1); 0x11A37 (SCCS2); 0x11A57 (SCCS3); 0x11A77 (SCCS4)  
Figure 20-12. SCC Status Register for UART Mode (SCCS)  
MOTOROLA  
Chapter 20. SCC UART Mode  
20-21  
         
Part IV. Communications Processor Module  
Table 20-13 describes UART SCCS Þelds.  
Table 20-13. UART SCCS Field Descriptions  
Bits  
Name  
Description  
0Ð6  
7
Ñ
ID  
Reserved, should be cleared.  
Idle status. Set when RXD has been a logic one for at least a full character time.  
0 The line is not idle.  
1 The line is idle.  
20.21 SCC UART Programming Example  
The following initialization sequence is for the 9,600 baud, 8 data bits, no parity, and stop  
bit of an SCC in UART mode assuming a 66-MHz system frequency. BRG1 and SCC2 are  
used. The controller is conÞgured with RTS2, CTS2, and CD2 active; CTS2 acts as an  
automatic ßow-control signal.  
1. ConÞgure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and  
PDIRD[27] and clear PDIRD[28] and PSORD[27,28].  
2. ConÞgure ports C and D pins to enable RTS2, CTS2 and CD2. Set PPARD[26],  
PPARC[12,13] and PDIRD[26] and clear PDIRC[12,13], PSORC[12,13] and  
PSORD[26].  
3. ConÞgure BRG1. Write BRGC1 with 0x0001_035A. The DIV16 bit is not used and  
the divider is 429 (decimal). The resulting BRG1 clock is 16´ the preferred bit rate.  
4. Connect BRG1 to SCC2 using the CPM mux. Clear CMXSCR[RS2CS,TS2CS].  
5. Connect the SCC2 to the NMSI. Clear CMXSCR[SC2].  
6. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and  
TxBD tables in dual-port RAM. Assuming one RxBD at the start of dual-port RAM  
followed by one TxBD, write RBASE with 0x0000 and TBASE with 0x0008.  
7. Write 0x04A1_0000 to CPCR to execute the INIT RX AND TX PARAMS command for  
SCC2. This command updates RBPTR and TBPTR of the serial channel with the  
new values of RBASE and TBASE.  
8. Write RFCR with 0x10 and TFCR with 0x10 for normal operation.  
9. Write MRBLR with the maximum number of bytes per Rx buffer. For this case,  
assume 16 bytes, so MRBLR = 0x0010.  
10.Write MAX_IDL with 0x0000 in the parameter RAM to disable the maximum idle  
functionality for this example.  
11.Set BRKCR to 0x0001 so STOP TRANSMIT commands send only one break character.  
12.Clear PAREC, FRMEC, NOSEC, and BRKEC in parameter RAM.  
13.Clear UADDR1 and UADDR2. They are not used.  
14.Clear TOSEQ. It is not used.  
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Part IV. Communications Processor Module  
15.Write CHARACTER1Ð8 with 0x8000. They are not used.  
16.Write RCCM with 0xC0FF. It is not used.  
17.Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory.  
Write 0xB000 to the RxBD[Status and Control], 0x0000 to RxBD[Data Length]  
(optional), and 0x0000_1000 to RxBD[Buffer Pointer].  
18.Initialize the TxBD. Assume the buffer is at 0x0000_2000 in main memory and  
contains sixteen 8-bit characters. Write 0xB000 to the TxBD[Status and Control],  
0x0010 to TxBD[Data Length], and 0x00002000 to TxBD[Buffer Pointer].  
19.Write 0xFFFF to SCCE2 to clear any previous events.  
20.Write 0x0003 to SCCM2 to allow the TX and RX interrupts.  
21.Write 0x0040_0000 to the SIMR_L so SMC1 can generate a system interrupt.  
Initialize SIPNR_L by writing 0xFFFF_FFFF to it.  
22.Write 0x0000_0020 to GSMR_H2 to conÞgure a small Rx FIFO width.  
23.Write 0x0002_8004 to GSMR_L2 to conÞgure 16´ sampling for transmit and  
receive, CTS and CD to automatically control transmission and reception (DIAG  
bits), and the SCC for UART mode. Notice that the transmitter (ENT) and receiver  
(ENR) have not been enabled yet.  
24.Set PSMR2 to 0xB000 to conÞgure automatic ßow control using CTS, 8-bit  
characters, no parity, 1 stop bit, and asynchronous SCC UART operation.  
25.Write 0x0002_8034 to GSMR_L2 to enable the transmitter and receiver. This  
ensures that ENT and ENR are enabled last.  
Note that after 16 bytes are sent, the transmit buffer is closed. Additionally, the receive  
buffer is closed after 16 bytes are received. Data received after 16 bytes causes a busy  
(out-of-buffers) condition because only one RxBD is prepared.  
20.22 S-Records Loader Application  
This section describes a downloading application that uses an SCC UART controller. The  
application performs S-record downloads and uploads between a host computer and an  
intelligent peripheral through a serial asynchronous line. S-records are strings of ASCII  
characters that begin with ÔSÕand end in an end-of-line character. This characteristic is used  
to impose a message structure on the communication between the devices. For ßow control,  
each device can transmit XON and XOFF characters, which are not part of the program  
being uploaded or downloaded.  
For simplicity, assume that the line is not multidrop (no addresses are sent) and that each  
S-record Þts into a single buffer. Follow the basic UART initialization sequence above in  
Section 20.21, ÒSCC UART Programming Example,Ó except allow for more and larger  
buffers and create the control character table as described in Table 20-14.  
MOTOROLA  
Chapter 20. SCC UART Mode  
20-23  
   
Part IV. Communications Processor Module  
Table 20-14. UART Control Characters for S-Records Example  
Character  
Description  
Line Feed Both the E and R bits should be cleared. When an end-of-line character is received, the current buffer is  
closed and made available to the core for processing. This buffer contains an entire S record that the  
processor can now check and copy to memory or disk as required.  
XOFF  
E should be cleared; R should be set. Whenever the core receives a control-character-received (CCR)  
interrupt and the RCCR contains XOFF, the software should immediately stop transmitting by setting  
PSMR[FRZ]. This keeps the other station from losing data when it runs out of Rx buffers.  
XON  
XON should be received after XOFF. E should be cleared and R should be set. PSMR[FRZ] on the  
transmitter should now be cleared. The CPM automatically resumes transmission of the serial line at the  
point at which it was previously stopped. Like XOFF, the XON character is not stored in the receive buffer.  
To receive S-records, the core must wait for an RX interrupt, indicating that a complete S-  
record buffer was received. Transmission requires assembling S-records into buffers and  
linking them to the TxBD table; transmission can be paused when an XOFF character is  
received. This scheme minimizes the number of interrupts the core receives (one per S-  
record) and relieves it from continually scanning for control characters.  
20-24  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Chapter 21  
SCC HDLC Mode  
210  
2H10 igh-level data link control (HDLC) is one of the most common protocols in the data link  
layer, layer 2 of the OSI model. Many other common layer 2 protocols, such as SDLC,  
SS#7, AppleTalk, LAPB, and LAPD, are based on HDLC and its framing structure in  
particular. Figure 21-1 shows the HDLC framing structure.  
HDLC uses a zero insertion/deletion process (bit-stufÞng) to ensure that a data bit pattern  
matching the delimiter ßag does not occur in a Þeld between ßags. The HDLC frame is  
synchronous and relies on the physical layer for clocking and synchronization of the  
transmitter/receiver.  
An address Þeld is needed to carry the frame's destination address because the layer 2 frame  
can be sent over point-to-point links, broadcast networks, packet-switched or circuit-  
switched systems. An address Þeld is commonly 0, 8, or 16 bits, depending on the data link  
layer protocol. SDLC and LAPB use an 8-bit address. SS#7 has no address Þeld because it  
is always used in point-to-point signaling links. LAPD divides its 16-bit address into  
different Þelds to specify various access points within one device. LAPD also deÞnes a  
broadcast address. Some HDLC-type protocols permit addressing beyond 16 bits.  
The 8- or 16-bit control Þeld provides a ßow control number and deÞnes the frame type  
(control or data). The exact use and structure of this Þeld depends on the protocol using the  
frame. The length of the data in the data Þeld depends on the frame protocol. Layer 3 frames  
are carried in this data Þeld. Error control is implemented by appending a cyclic redundancy  
check (CRC) to the frame, which in most protocols is 16 bits long but can be as long as 32  
bits. In HDLC, the lsb of each octet is sent Þrst; the msb of the CRC is sent Þrst.  
HDLC mode is selected for an SCC by writing GSMR_L[MODE] = 0b0000. In a  
nonmultiplexed modem interface, SCC outputs connect directly to external pins. Modem  
signals can be supported through port C. The Rx and Tx clocks can be supplied from either  
the bank of baud rate generators, by the DPLL, or externally. An SCC can also be connected  
through the TDM channels of the serial interface (SI). In HDLC mode, an SCC becomes  
an HDLC controller, and consists of separate transmit and receive sections whose  
operations are asynchronous with the core and can either be synchronous or asynchronous  
with respect to other SCCs.  
MOTOROLA  
Chapter 21. SCC HDLC Mode  
21-1  
     
Part IV. Communications Processor Module  
21.1 SCC HDLC Features  
The main features of an SCC in HDLC mode are follows:  
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
Flexible buffers with multiple buffers per frame  
Separate interrupts for frames and buffers (Rx and Tx)  
Received-frames threshold to reduce interrupt overhead  
Can be used with the SCC DPLL  
Four address comparison registers with mask  
Maintenance of Þve 16-bit error counters  
Flag/abort/idle generation and detection  
Zero insertion/deletion  
16- or 32-bit CRC-CCITT generation and checking  
Detection of nonoctet aligned frames  
Detection of frames that are too long  
Programmable ßags (0Ð15) between successive frames  
Automatic retransmission in case of collision  
21.2 SCC HDLC Channel Frame Transmission  
The HDLC transmitter is designed to work with little or no core intervention. Once enabled  
by the core, a transmitter starts sending ßags or idles as programmed in the HDLC mode  
register (PSMR). The HDLC polls the Þrst BD in the TxBD table. When there is a frame to  
transmit, the SCC fetches the data (address, control, and information) from the Þrst buffer  
and starts sending the frame after inserting the minimum number of ßags speciÞed between  
frames. When the end of the current buffer is reached and TxBD[L] (last buffer in frame)  
is set, the SCC appends the CRC and closing ßag. In HDLC mode, the lsb of each octet and  
the msb of the CRC are sent Þrst. Figure 21-1 shows a typical HDLC frame.  
Opening Flag  
8 bits  
Address  
16 bits  
Control  
8 bits  
Information (Optional)  
CRC  
Closing Flag  
8 bits  
8n bits  
16 bits  
Figure 21-1. HDLC Framing Structure  
After a closing ßag is sent, the SCC updates the frame status bits of the BD and clears  
TxBD[R] (buffer ready). At the end of the current buffer, if TxBD[L] is not set (multiple  
buffers per frame), only TxBD[R] is cleared. Before the SCC proceeds to the next TxBD in  
the table, an interrupt can be issued if TxBD[I] is set. This interrupt programmability allows  
the core to intervene after each buffer, after a speciÞc buffer, or after each frame.  
The STOP TRANSMIT command can be used to expedite critical data ahead of previously  
linked buffers or to support efÞcient error handling. When the SCC receives a STOP  
TRANSMIT command, it sends idles or ßags instead of the current frame until it receives a  
RESTART TRANSMIT command. The GRACEFUL STOP TRANSMIT command can be used to  
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MOTOROLA  
       
Part IV. Communications Processor Module  
insert a high-priority frame without aborting the current oneÑa graceful-stop-complete  
event is generated in SCCE[GRA] when the current frame is Þnished. See Section 21.6,  
ÒSCC HDLC Commands.Ó  
21.3 SCC HDLC Channel Frame Reception  
The HDLC receiver is designed to work with little or no core intervention to perform  
address recognition, CRC checking, and maximum frame length checking. Received  
frames can be used to implement any HDLC-based protocol.  
Once enabled by the core, the receiver waits for an opening ßag character. When it detects  
the Þrst byte of the frame, the SCC compares the frame address with four user-  
programmable, 16-bit address registers and an address mask. The SCC compares the  
received address Þeld with the user-deÞned values after masking with the address mask. To  
detect broadcast (all ones) address frames, one address register must be written with all  
ones.  
If an address match is detected, the SCC fetches the next BD and SCC starts transferring  
the incoming frame to the buffer if it is empty. When the buffer is full, the SCC clears  
RxBD[E] and generates a maskable interrupt if RxBD[I] is set. If the incoming frame is  
larger than the current buffer, the SCC continues receiving using the next BD in the table.  
During reception, the SCC checks for frames that are too long (using MFLR). When the  
frame ends, the CRC Þeld is checked against the recalculated value and written to the  
buffer. RxBD[Data Length] of the last BD in the HDLC frame contains the entire frame  
length. This also enables software to identify the frames in which the maximum frame  
length violations occur. The SCC sets RxBD[L] (last buffer in frame), writes the frame  
status bits, and clears RxBD[E]. It then generates a maskable event (SCCE[RXF]) to  
indicate a frame was received. The SCC then waits for a new frame. Back-to-back frames  
can be received with only one shared ßag between frames.  
The received frames threshold parameter (RFTHR) can be used to postpone interrupts until  
a speciÞed number of frames is received. This function can be combined with a timer to  
implement a timeout if fewer than the speciÞed number of threshold frames is received.  
Note that SCCs in HDLC mode, or any other synchronous mode, must receive a minimum  
of eight clocks after the last bit arrives to account for Rx FIFO delay.  
21.4 SCC HDLC Parameter RAM  
For HDLC mode, the protocol-speciÞc area of the SCC parameter RAM is mapped as in  
Table 21-1.  
MOTOROLA  
Chapter 21. SCC HDLC Mode  
21-3  
     
Part IV. Communications Processor Module  
Table 21-1. HDLC-Specific SCC Parameter RAM Memory Map  
1
Offset  
Name  
Width  
Description  
0x30  
0x34  
Ñ
Word  
Word  
Reserved  
C_MASK  
CRC mask. For the 16-bit CRC-CCITT, initialize with 0x0000_F0B8. For 32-bit CRC-  
CCITT, initialize with 0xDEBB_20E3.  
0x38  
C_PRES  
Word  
CRC preset. For the 16-bit CRC-CCITT, initialize with 0x0000_FFFF. For 32-bit CRC-  
CCITT, initialize with 0xFFFF_FFFF.  
16  
Modulo 2 counters maintained by the CP. Initialize them while the channel is  
disabled.  
DISFC (Discarded frame counter) Counts error-free frames discarded due to lack of  
free buffers.  
CRCEC (CRC error counter) Includes frames not addressed to the user or frames  
received in the BSY condition, but does not include overrun errors.  
ABTSC (Abort sequence counter)  
NMARC (Nonmatching address received counter) Includes error-free frames only.  
RETRC (Frame retransmission counter) Counts number of frames resent due to  
collision.  
0x3C  
0x3E  
0x40  
0x42  
0x44  
DISFC  
Hword  
Hword  
Hword  
Hword  
Hword  
CRCEC  
ABTSC  
NMARC  
RETRC  
0x46  
MFLR  
Hword  
Max frame length register. The HDLC compares the incoming HDLC frameÕs length  
with the user-deÞned limit in MFLR. If the limit is exceeded, the rest of the frame is  
discarded and RxBD[LG] is set in the last BD of that frame. At the end of the frame  
the SCC reports frame status and frame length in the last RxBD. The MFLR is  
deÞned as all in-frame bytes between the opening and closing ßags.  
0x48  
0x4A  
MAX_CNT Hword  
Maximum length counter. A temporary down-counter used to track frame length.  
RFTHR  
Hword  
Received frames threshold. Used to reduce potential interrupt overhead when each  
in a series of short HDLC frames causes an SCCE[RXF] event. Setting RFTHR  
determines the frequency of RXF interrupts, which occur only when the RFTHR limit  
is reached. Provide enough empty RxBDs for the number of frames speciÞed in  
RFTHR.  
0x4C  
0x4E  
0x50  
0x52  
0x54  
0x56  
RFCNT  
Hword  
Hword  
Hword  
Hword  
Hword  
Hword  
Received frames count. RFCNT is a down-counter used to implement RFTHR.  
HMASK  
HADDR1  
HADDR2  
HADDR3  
HADDR4  
Mask register (HMASK) and four address registers (HADDRn) for address  
recognition. The SCC reads the frame address from the HDLC receiver, compares it  
with the HADDRs, and masks the result with HMASK. Setting an HMASK bit enables  
the corresponding comparison bit, clearing a bit masks it. When a match occurs, the  
frame address and data are written to the buffers. When no match occurs and a  
frame is error-free, the nonmatching address received counter (NMARC) is  
incremented.  
The eight low-order bits of HADDRn should contain the Þrst address byte after the  
opening ßag. For example, to recognize a frame that begins 0x7E (ßag), 0x68, 0xAA,  
using 16-bit address recognition, HADDRn should contain 0xAA68 and HMASK  
should contain 0xFFFF. For 8-bit addresses, clear the eight high-order HMASK bits.  
See Figure 21-2.  
0x58  
0x5A  
TMP  
Hword  
Hword  
Temporary storage.  
Temporary storage.  
TMP_MB  
1
From SCC base. See Section 19.3.1, ÒSCC Base Addresses.Ó  
21-4  
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MOTOROLA  
   
Part IV. Communications Processor Module  
Figure 21-2 shows 16- and 8-bit address recognition.  
16-Bit Address Recognition  
8-Bit Address Recognition  
Address Control  
Flag  
0x7E  
Address  
0x68  
Address  
0xAA  
Control  
0x44  
Flag  
0x7E  
etc.  
etc.  
0x55  
0x44  
HMASK  
0xFFFF  
0xAA68  
0xFFFF  
0xAA68  
0xAA68  
HMASK  
0x00FF  
0xXX55  
0xXX55  
0xXX55  
0xXX55  
HADDR1  
HADDR2  
HADDR3  
HADDR4  
HADDR1  
HADDR2  
HADDR3  
HADDR4  
Recognizes one 16-bit address (HADDR1) and  
the 16-bit broadcast address (HADDR2)  
Recognizes a single 8-bit address (HADDR1)  
Figure 21-2. HDLC Address Recognition  
21.5 Programming the SCC in HDLC Mode  
HDLC mode is selected for an SCC by writing GSMR_L[MODE] = 0b0000. The HDLC  
controller uses the same buffer and BD data structure as other modes and supports  
multibuffer operation and address comparisons. Receive errors are reported through the  
RxBD; transmit errors are reported through the TxBD.  
21.6 SCC HDLC Commands  
The transmit and receive commands are issued to the CP command register (CPCR).  
Transmit commands are described in Table 21-2.  
Table 21-2. Transmit Commands  
Command  
Description  
STOP  
After a hardware or software reset and a channel is enabled in the GSMR, the transmitter starts polling  
the Þrst BD in the TxBD table every 64 Tx clocks, or immediately if TODR[TOD] = 1, and begins sending  
data if TxBD[R] is set. If the SCC receives the STOP TRANSMIT command while not transmitting, the  
transmitter stops polling the BDs. If the SCC receives the command during transmission, transmission is  
aborted after a maximum of 64 additional bits, the Tx FIFO is ßushed, and the current BD pointer TBPTR  
is not advanced (no new BD is accessed). The transmitter then sends an abort sequence (0x7F) and  
stops polling the BDs.  
TRANSMIT  
When not transmitting, the channel sends ßags or idles as programmed in the GSMR.  
Note that if PSMR[MFF] = 1, multiple small frames could be ßushed from the Tx FIFO; a GRACEFUL STOP  
TRANSMIT command prevents this.  
GRACEFUL  
STOP  
Stops transmission smoothly. Unlike a STOP TRANSMIT command, it stops transmission after the current  
frame is Þnished or immediately if no frame is being sent. SCCE[GRA] is set when transmission stops.  
HDLC Tx parameters and Tx BDs can then be updated. TBPTR points to the next TxBD. Transmission  
begins once TxBD[R] of the next BD is set and a RESTART TRANSMIT command is issued.  
TRANSMIT  
RESTART  
TRANSMIT  
Enables frames to be sent on the transmit channel. The HDLC controller expects this command after a  
STOP TRANSMIT is issued and the channel in its GSMR is disabled, after a GRACEFUL STOP TRANSMIT  
command, or after a transmitter error. The transmitter resumes from the current BD.  
INIT TX  
Resets the Tx parameters in the parameter RAM. Issue only when the transmitter is disabled. INIT TX AND  
PARAMETERS RX PARAMETERS resets both Tx and Rx parameters.  
MOTOROLA  
Chapter 21. SCC HDLC Mode  
21-5  
           
Part IV. Communications Processor Module  
Receive commands are described in Table 21-3.  
Table 21-3. Receive Commands  
Command  
Description  
ENTER HUNT After a hardware or software reset, once an SCC is enabled in the GSMR, the receiver is  
MODE  
automatically enabled and uses the Þrst BD in the RxBD table. While the SCC is looking for the  
beginning of a frame, that SCC is in hunt mode. The ENTER HUNT MODE command is used to force the  
HDLC receiver to stop receiving the current frame and enter hunt mode, in which the HDLC  
continually scans the input data stream for a ßag sequence. After receiving the command, the buffer is  
closed and the CRC is reset. Further frame reception uses the next BD.  
CLOSE RXBD Should not be used in the HDLC protocol.  
INIT RX Resets the Rx parameters in the parameter RAM.; issue only when the receiver is disabled. Note that  
PARAMETERS INIT TX AND RX PARAMETERS resets both Tx and Rx parameters.  
21.7 Handling Errors in the SCC HDLC Controller  
The SCC HDLC controller reports frame reception and transmission errors using BDs,  
error counters, and the SCCE. Transmission errors are described in Table 21-4.  
Table 21-4. Transmit Errors  
Error  
Description  
Transmitter  
Underrun  
The channel stops transmitting, closes the buffer, sets TxBD[UN], and generates a TXE interrupt if not  
masked. Transmission resumes when a RESTART TRANSMIT command is issued. The SCC send and  
receive FIFOs are 32 bytes each.  
CTS Lost  
The channel stops transmitting, closes the buffer, sets TxBD[CT], and generates the TXE interrupt if  
duringFrame not masked.Transmission resumes after a RESTART TRANSMIT command. If this error occurs on the Þrst  
Transmission or second buffer of the frame and PSMR[RTE] = 1, the channel resends the frame when CTS is  
reasserted and no error is reported. If collisions are possible, to ensure proper retransmission of multi-  
buffer frames, the Þrst two buffers of each frame should in total contain more than 36 bytes for SCC or  
20 bytes for SCC. The channel also increments the retransmission counter RETRC in the parameter  
RAM.  
Reception errors are described in Table 21-5.  
Table 21-5. Receive Errors  
Error  
Description  
Overrun  
Each SCC maintains an internal FIFO for receiving data. The CP begins programming the SDMA  
channel (if the buffer is in external memory) and updating the CRC when a full or partial FIFOÕs worth  
of data (according to GSMR_H[RFW]) is received in the Rx FIFO. When an Rx FIFO overrun occurs,  
the previous byte is overwritten by the next byte. The previous data byte and the frame status are lost.  
The channel closes the buffer with RxBD[OV] set and generates an RXF interrupt if not masked. The  
receiver then enters hunt mode. Even if an overrun occurs during a frame whose address is not  
recognized, an RxBD with data length two is opened to report the overrun and the interrupt is  
generated.  
CD Lost Highest priority error. The channel stops frame reception, closes the buffer, sets RxBD[CD], and  
during Frame generates the RXF interrupt if not masked. The rest of the frame is lost and other errors are not  
Reception  
checked in that frame. At this point, the receiver enters hunt mode.  
21-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part IV. Communications Processor Module  
Table 21-5. Receive Errors (Continued)  
Error  
Abort  
Sequence  
Description  
Occurs when seven or more consecutive ones are received.When this occurs while receiving a frame,  
the channel closes the buffer, sets RxBD[AB] and generates a maskable RXF interrupt. The channel  
also increments the abort sequence counter ABTSC. The CRC and nonoctet error status conditions  
are not checked on aborted frames. The receiver then enters hunt mode.  
Nonoctet  
Aligned  
Frame  
The channel writes the received data to the buffer, closes the buffer, sets RxBD[NO], and generates a  
maskable RXF interrupt. CRC error status should be disregarded on nonoctet frames. After a nonoctet  
aligned frame is received, the receiver enters hunt mode. An immediate back-to-back frame is still  
received. The nonoctet data may be derived from the last word in the buffer as follows:  
msb  
lsb  
1
0
0
Valid Data  
Nonvalid Data  
Note that if buffer swapping is used (RFCR[BO] = 0b0x), the Þgure above refers to the last byte, rather  
than the last word, of the buffer.The lsb of each octet is sent Þrst while the msb of the CRC is sent Þrst.  
CRC  
The channel writes the received CRC to the buffer, closes the buffer, sets RxBD[CR], generates a  
maskable RXF interrupt, and increments the CRC error counter CRCEC. After receiving a frame with  
a CRC error, the receiver enters hunt mode. An immediate back-to-back frame is still received. CRC  
checking cannot be disabled, but the CRC error can be ignored if checking is not required.  
21.8 HDLC Mode Register (PSMR)  
The protocol-speciÞc mode register (PSMR), shown in Figure 21-3, functions as the HDLC  
mode register.  
Bit  
Field  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
Ñ
15  
NOF  
CRC  
RTE  
Ñ
FSE DRT BUS BRM MFF  
Reset  
R/W  
0
R/W  
Address  
0x11A08 (PSMR1); 0x11A28 (PSMR2); 0x11A48 (PSMR3); 0x11A68 (PSMR4)  
Figure 21-3. HDLC Mode Register (PSMR)  
Table 21-6 describes PSMR HDLC Þelds.  
Table 21-6. PSMR HDLC Field Descriptions  
Bits Name  
Description  
0-3  
NOF Number of ßags. Minimum number of ßags between or before frames. If NOF = 0b0000, no ßags are  
inserted between frames and the closing ßag of one frame is followed by the opening ßag of the next  
frame in the case of back-to-back frames. NOF can be modiÞed on-the-ßy.  
4Ð5  
CRC CRC selection.  
00 16-bit CCITT-CRC (HDLC). X16 + X12 + X5 + 1.  
x1 Reserved.  
10 32-bit CCITT-CRC (Ethernet and HDLC). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8  
+ X7 + X5 + X4 + X2 + X1 +1.  
MOTOROLA  
Chapter 21. SCC HDLC Mode  
21-7  
         
Part IV. Communications Processor Module  
Table 21-6. PSMR HDLC Field Descriptions (Continued)  
Bits Name  
Description  
6
RTE  
Retransmit enable.  
0 No retransmission.  
1 Automatic frame retransmission is enabled. Particularly useful in the HDLC bus protocol and ISDN  
applications where multiple HDLC controllers can collide. Note that retransmission occurs only if a  
lost CTS occurs on the Þrst or second buffer of the frame.  
7
8
Ñ
Reserved, should be cleared.  
FSE  
Flag sharing enable. Valid only if GSMR_H[RTSM] = 1. Can be modiÞed on-the-ßy.  
0 Normal operation.  
1 If NOF[0Ð3] = 0b0000, a single shared ßag is sent between back-to-back frames. Other values of  
NOF[0Ð3] are decremented by 1. Useful in signaling system #7 applications.  
9
DRT Disable receiver while transmitting.  
0 Normal operation.  
1 As the SCC sends data, the receiver is disabled and gated by the internal RTS. This helps if the  
HDLC channel is on a multidrop line and the SCC does not need to receive its own transmission.  
10  
11  
BUS HDLC bus mode.  
0 Normal HDLC operation.  
1 HDLC bus operation is selected. See Section 21.14, ÒHDLC Bus Mode with Collision Detection.Ó  
BRM HDLC bus RTS mode. Valid only if BUS = 1. Otherwise, it is ignored.  
0 Normal RTS operation during HDLC bus mode. RTS is asserted on the Þrst bit of the Tx frame and  
negated after the Þrst collision bit is received.  
1 Special RTS operation during HDLC bus mode. RTS is delayed by one bit with respect to the  
normal case, which helps when the HDLC bus protocol is being run locally and sent over a long-  
distance line at the same time. The one-bit delay allows RTS to be used to enable the transmission  
line buffers so that the electrical effects of collisions are not sent over the transmission line.  
12  
MFF Multiple frames in Tx FIFO. The receiver is not affected.  
0 Normal operation. The Tx FIFO must never contain more than one HDLC frame. The CTS lost  
status is reported accurately on a per-frame basis.  
1 The Tx FIFO can hold multiple frames, but lost CTS may not be reported on the buffer/frame it  
occurred on.This can improve performance of HDLC transmissions of small back-to-back frames or  
when the number of ßags between frames should be limited.  
13Ð15  
Ñ
Reserved, should be cleared.  
21.9 SCC HDLC Receive Buffer Descriptor (RxBD)  
The CP uses the RxBD, shown in Figure 21-4, to report on data received for each buffer.  
0
1
2
3
4
L
5
F
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
E
Ñ
W
I
CM  
Ñ
DE  
Ñ
LG  
NO  
AB  
CR  
OV  
CD  
Data Length  
Rx Buffer Pointer  
Figure 21-4. SCC HDLC Receive Buffer Descriptor (RxBD)  
21-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part IV. Communications Processor Module  
Table 21-7 describes HDLC RxBD status and control Þelds.  
Table 21-7. SCC HDLC RxBD Status and Control Field Descriptions  
Bits Name  
Description  
0
E
Empty.  
0 The buffer is full or reception stopped because of an error. The core can read or write to any Þelds of  
this RxBD. The CP does not use this BD while E = 0.  
1 The buffer is not full. The CP controls the BD and buffer. The core should not update the BD.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (last BD in the RxBD table).  
0 Not the last BD in the table.  
1 Last BD in the table. After this buffer is used, the CP receives incoming data using the BD pointed to  
by RBASE.The number of BDs in this table are programmable and determined only by RxBD[W] and  
overall space constraints of the dual-port RAM.  
3
4
I
Interrupt.  
0 SCCE[RXB] is not set after this buffer is used; SCCE[RXF] is unaffected.  
1 SCCE[RXB] or SCCE[RXF] is set when the SCC uses this buffer.  
L
Last buffer in frame.  
0 Not the last buffer in frame.  
1 Last buffer in frame. Indicates reception of a closing ßag or an error, in which case one or more of the  
CD, OV, AB, and LG bits are set. The SCC writes the number of frame octets to the data length Þeld.  
5
6
F
First in frame.  
0 Not the Þrst buffer in a frame.  
1 First buffer in a frame.  
CM  
Continuous mode. Note that RxBD[E] is cleared if an error occurs during reception, regardless of CM.  
0 Normal operation.  
1 RxBD[E] is not cleared by the CP after this BD is closed, allowing the associated buffer to be  
overwritten next time the CP accesses it.  
7
8
Ñ
Reserved, should be cleared.  
DE  
DPLL error. Set when a DPLL error occurs while this buffer is being received. DE is also set due to a  
missing transition when using decoding modes in which a transition is required for every bit. Note that  
when a DPLL error occurs, the frame closes and error checking halts.  
9
Ñ
Reserved, should be cleared.  
10  
LG  
Rx frame length violation. Set when a frame larger than the maximum deÞned for this channel is  
recognized. Only the maximum-allowed number of bytes (MFLR) is written to the buffer. This event is  
not reported until the buffer is closed, SCCE[RXF] is set, and the closing ßag is received. The total  
number of bytes received between ßags is still written to the data length Þeld.  
11  
12  
13  
NO  
AB  
CR  
Rx nonoctet aligned frame. Set when a received frame contains a number of bits not divisible by eight.  
Rx abort sequence. Set when at least seven consecutive ones are received during frame reception.  
Rx CRC error. Set when a frame contains a CRC error. CRC bytes received are always written to the  
Rx buffer.  
14  
15  
OV  
CD  
Overrun. Set when a receiver overrun occurs during frame reception.  
Carrier detect lost (NMSI mode only). Set when CD is negated during frame reception.  
Data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer  
Descriptors (BDs).Ó Because HDLC is a frame-based protocol, RxBD[Data Length] of the  
MOTOROLA  
Chapter 21. SCC HDLC Mode  
21-9  
 
Part IV. Communications Processor Module  
last buffer of a frame contains the total number of frame bytes, including the 2 or 4 bytes  
for CRC. Figure 21-5 shows an example of how RxBDs are used in receiving.  
MRBLR = 8 Bytes for this SCC  
Receive BD 0  
Buffer  
E
0
L
0
F
1
Status  
Length  
Address 1  
Address 2  
0x0008  
Buffer full  
Pointer  
32-Bit Buffer Pointer  
8 Bytes  
Control Byte  
5
Information  
(I-Field) Bytes  
Receive BD 1  
Buffer  
E
0
L
1
F
0
Status  
Length  
Last I-Field Byte  
CRC Byte 1  
CRC Byte 2  
0x000B  
Buffer closed  
when closing flag  
Received  
Pointer  
32-Bit Buffer Pointer  
8 Bytes  
Empty  
Receive BD 2  
Buffer  
E
0
L
1
F
1
AB  
1
Status  
Length  
Address 1  
Address 2  
Control Byte  
0x0003  
8 Bytes  
Abort was  
received after  
control byte  
Pointer  
32-Bit Buffer Pointer  
Empty  
Buffer  
Receive BD 3  
E
1
Status  
Length  
XXXX  
8 Bytes  
Empty  
Buffer  
still empty  
Pointer  
32-Bit Buffer Pointer  
Stored in Rx Buffer  
Stored in Rx Buffer  
F
A
A
C
I
I
I
I
I
I
CR CR  
F
Line Idle  
F
A
A
C
Abort/Idle  
Two Frames  
Received in HDLC  
Unexpected abort  
occurs before  
closing flag  
Present  
time  
Time  
Legend:  
F = Flag  
A = Address byte  
C = Control byte  
I = Information byte  
CR = CRC Byte  
Figure 21-5. SCC HDLC Receiving Using RxBDs  
21-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part IV. Communications Processor Module  
21.10 SCC HDLC Transmit Buffer Descriptor (TxBD)  
The CP uses the TxBD, shown in Figure 21-6, to conÞrm transmissions and indicate error  
conditions.  
0
1
2
3
4
5
6
7
8
9
10  
Ñ
11  
12  
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
R
Ñ
W
I
L
TC CM  
UN  
CT  
Data Length  
Tx Buffer Pointer  
Figure 21-6. SCC HDLC Transmit Buffer Descriptor (TxBD)  
Table 21-8 describes HDLC TxBD status and control Þelds.  
Table 21-8. SCC HDLC TxBD Status and Control Field Descriptions  
Bits Name  
Description  
0
R
Ready.  
0 The buffer is not ready for transmission. Both the buffer and the BD can be updated. The CP clears  
R after the buffer is sent or an error is encountered.  
1 The buffer has not been sent or is being sent and the BD cannot be updated.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (last BD in TxBD table).  
0 Not the last BD in the table.  
1 Last BD in the BD table. After this buffer is used, the CP sends data using the BD pointed to by  
TBASE. The number of TxBDs in this table is determined by TxBD[W] and the space constraints of  
the dual-port RAM.  
3
4
5
I
Interrupt.  
0 No interrupt is generated after this buffer is processed.  
1 SCCE[TXB] or SCCE[TXE] is set when this buffer is processed, causing interrupts if not masked.  
L
Last.  
0 Not the last buffer in the frame.  
1 Last buffer in the frame.  
TC  
Tx CRC. Valid only when TxBD[L] = 1. Otherwise, it is ignored.  
0 Transmit the closing ßag after the last data byte. This setting can be used to send a bad CRC after  
the data for testing purposes.  
1 Transmit the CRC sequence after the last data byte.  
6
CM  
Continuous mode.  
0 Normal operation.  
1 The CP does not clear TxBD[R] after this BD is closed allowing the buffer to be resent the next time  
the CP accesses this BD. However, TxBD[R] is cleared if an error occurs during transmission,  
regardless of CM.  
7Ð13  
14  
Ñ
Reserved, should be cleared.  
UN  
CT  
Underrun. Set after the SCC sends a buffer and a transmitter underrun occurred.  
15  
CTS lost. Indicates when CTS in NMSI mode or layer 1 grant is lost in GCI or IDL mode during frame  
transmission. If data from more than one buffer is currently in the FIFO when this error occurs, the  
HDLC writes CT in the current BD after sending the buffer.  
MOTOROLA  
Chapter 21. SCC HDLC Mode  
21-11  
       
Part IV. Communications Processor Module  
The data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer  
Descriptors (BDs).Ó  
21.11 HDLC Event Register (SCCE)/HDLC Mask  
Register (SCCM)  
The SCC event register (SCCE) is used as the HDLC event register to report events  
recognized by the HDLC channel and to generate interrupts. When an event is recognized,  
the SCC sets the corresponding SCCE bit. Interrupts generated through SCCE can be  
masked in the SCC mask register (SCCM) which has the same bit format as the SCCE.  
Setting an SCCM bit enables the corresponding interrupt; clearing a bit masks it. SCCE bits  
are cleared by writing ones; writing zeros has no effect. All unmasked bits must be cleared  
before the CP clears the internal interrupt request. Figure 21-7 shows SCCE/SCCM for  
HDLC operation.  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field  
Reset  
R/W  
Ñ
GLR GLT DCC FLG IDL GRA  
Ñ
TXE RXF BSY TXB RXB  
0000_0000_0000_0000  
R/W  
Addr  
0x11A10 (SCCE1); 0x11A30 (SCCE2); 0x11A50 (SCCE3); 0x11A70 (SCCE4)  
0x11A14 (SCCM1); 0x11A34 (SCCM2); 0x11A54 (SCCM3); 0x11A74 (SCCM4)  
Figure 21-7. HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)  
Table 21-9 describes SCCE/SCCM Þelds.  
Table 21-9. SCCE/SCCM Field Descriptions  
Bits  
0Ð2  
Name  
Description  
Ñ
Reserved, should be cleared.  
3, 4  
GLR/  
GLT  
Glitch on Rx/Tx. Set when the SCC detects a clock glitch on the receive/transmit clock. See  
Section 19.3.7, ÒClock Glitch Detection.Ó  
5
DCC  
DPLL carrier sense changed. Set when the carrier sense status generated by the DPLL changes.  
Real-time status can be read in SCCS[CS]. This is not the CD status reported in port C. Valid only  
when the DPLL is used.  
6
7
8
FLG  
IDL  
Flag status. Set when the SCC stops or starts receiving HDLC ßags. Real-time status can be read in  
SCCS[FG].  
Idle sequence status changed. Set when HDLC line status changes. Real-time status of the line can  
be read in SCCS[ID].  
GRA  
Graceful stop complete. A GRACEFUL STOP TRANSMIT command completed execution. Set as soon as  
the transmitter has sent a frame in progress when the command was issued. Set immediately if no  
frame was in progress when the command was issued.  
9Ð10  
11  
Ñ
Reserved, should be cleared.  
TXE  
Tx error. Indicates an error (CTS lost or underrun) has occurred on the transmitter channel.  
21-12  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part IV. Communications Processor Module  
Table 21-9. SCCE/SCCM Field Descriptions (Continued)  
Bits  
12  
Name  
Description  
RXF  
Rx frame. Set when the number of receive frames speciÞed in RFTHR are received on the HDLC  
channel. It is set no sooner than two clocks after the last bit of the closing ßag is received.This event is  
not maskable via the RxBD[I] bit.  
13  
14  
BSY  
TXB  
Busy condition. Indicates a frame arrived but was discarded due to a lack of buffers.  
Transmit buffer. Enabled by setting TxBD[I].TXB is set when a buffer is sent on the HDLC channel. For  
the last buffer in the frame, TXB is not set before the last bit of the closing ßag begins its transmission;  
otherwise, it is set after the last byte of the buffer is written to the Tx FIFO.  
15  
RXB  
Receive buffer. Enabled by setting RxBD[I]. RXB is set when the HDLC channel receives a buffer that  
is not the last in a frame.  
Figure 21-8 shows interrupts that can be generated using the HDLC protocol.  
Frame  
Received by HDLC  
Stored in Rx Buffer  
Time  
F
F
A
A
C
I
I
I
CR CR  
F
RXD  
Line Idle  
Line Idle  
CD  
HDLC SCCE  
Events  
CD  
IDL FLG  
FLG  
RXB  
RXF FLG IDL  
FLG  
CD  
NOTES:  
1. RXB event assumes receive buffers are 6 bytes each.  
2. The second IDL event occurs after 15 ones are received in a row.  
3. The FLG interrupts show the beginning and end of flag reception.  
4. The FLG interrupt at the end of the frame may precede the RXF interrupt due to receive FIFO latency.  
5. The CD event must be programmed in the port C parallel I/O, not in the SCC itself.  
6. F = flag, A = address byte, C = control byte, I = information byte, and CR = CRC byte  
Stored in Tx Buffer  
Frame  
Transmitted by HDLC  
TXD  
RTS  
CTS  
Line Idle  
F
F
A
A
C
CR CR  
F
Line Idle  
HDLC SCCE  
Events  
CTS  
TXB  
CTS  
NOTES:  
1. TXB event shown assumes all three bytes were put into a single buffer.  
2. Example shows one additional opening flag. This is programmable.  
3. The CTS event must be programmed in the port C parallel I/O, not in the SCC itself.  
Figure 21-8. SCC HDLC Interrupt Event Example  
MOTOROLA  
Chapter 21. SCC HDLC Mode  
21-13  
   
Part IV. Communications Processor Module  
21.12 SCC HDLC Status Register (SCCS)  
The SCC status register (SCCS), shown in Figure 21-9, permits monitoring of real-time  
status conditions on RXD. The real-time status of CTS and CD are part of the port C  
parallel I/O.  
Bit  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
Ñ
FG  
CS  
ID  
0000_0000  
R
Addr  
0x11A17 (SCCS1); 0x11A37 (SCCS2); 0x11A57 (SCCS3); 0x11A77 (SCCS4)  
Figure 21-9. SCC HDLC Status Register (SCCS)  
Table 21-10 describes HDLC SCCS Þelds.  
Table 21-10. HDLC SCCS Field Descriptions  
Bits Name  
Description  
0Ð4  
5
Ñ
Reserved, should be cleared.  
Flags. The line is checked after the data has been decoded by the DPLL.  
FG  
0 HDLC ßags are not being received. The most recently received 8 bits are examined every bit time to  
see if a ßag is present.  
1 HDLC ßags are being received. FG is set as soon as an HDLC ßag (0x7E) is received on the line.  
Once it is set, it remains set at least 8 bit times and the next eight received bits are examined. If  
another ßag occurs, FG stays set for at least another eight bits. If not, it is cleared and the search  
begins again.  
6
7
CS  
ID  
Carrier sense (DPLL). Shows the real-time carrier sense of the line as determined by the DPLL.  
0 The DPLL does not sense a carrier.  
1 The DPLL senses a carrier.  
Idle status.  
0 The line is busy.  
1 Set when RXD is a logic 1 (idle) for 15 or more consecutive bit times. It is cleared after a single logic  
0 is received.  
21.13 SCC HDLC Programming Examples  
The following sections show examples for programming SCCs in HDLC mode. The Þrst  
example uses an external clock. The second example implements Manchester encoding.  
21-14  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
           
Part IV. Communications Processor Module  
21.13.1 SCC HDLC Programming Example #1  
The following initialization sequence is for an SCC HDLC channel with an external clock.  
SCC2 is used with RTS2, CTS2, and CD2 active; CLK3 is used for both the HDLC receiver  
and transmitter.  
1. ConÞgure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and  
PDIRD[27] and clear PDIRD[28] and PSORD[27,28].  
2. ConÞgure ports C and D pins to enable RTS2, CTS2 and CD2. Set PPARD[26],  
PPARC[12,13] and PDIRD[26] and clear PDIRC[12,13], PSORC[12,13] and  
PSORD[26].  
3. ConÞgure port C pin 29 to enable the CLK3 pin. Set PPARC[29] and clear  
PDIRC[29] and PSORC[29].  
4. Connect CLK3 to SCC2 using the CPM mux. Write 0b110 to CMXSCR[R2CS] and  
CMXSCR[T2CS].  
5. Connect the SCC2 to the NMSI (its own set of pins). clear CMXSCR[SC2].  
6. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and  
TxBD tables in dual-port RAM. Assuming one RxBD at the start of dual-port RAM  
and one TxBD following it, write RBASE with 0x0000 and TBASE with 0x0008.  
7. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and  
TxBD tables in dual-port RAM. Assuming one RxBD at the start of dual-port RAM  
and one TxBD following it, write RBASE with 0x0000 and TBASE with 0x0008.  
8. Write 0x04A1_0000 to CPCR to execute the INIT RX AND TX PARAMS command for  
SCC2. This command updates RBPTR and TBPTR of the serial channel with the  
new values of RBASE and TBASE.  
9. Write RFCR with 0x10 and TFCR with 0x10 for normal operation.  
10.Write MRBLR with the maximum number of bytes per Rx buffer. Choose 256 bytes  
(MRBLR = 0x0100) so an entire Rx frame can Þt in one buffer.  
11.Write C_MASK with 0x0000F0B8 to comply with 16-bit CCITT-CRC.  
12.Write C_PRES with 0x0000FFFF to comply with 16-bit CCITT-CRC.  
13.Clear DISFC, CRCEC, ABTSC, NMARC, and RETRC for clarity.  
14.Write MFLR with 0x0100 so the maximum frame size is 256 bytes.  
15.Write RFTHR with 0x0001 to allow interrupts after each frame.  
16.Write HMASK with 0x0000 to allow all addresses to be recognized.  
17.Clear HADDR1ÐHADDR4 for clarity.  
18.Initialize the RxBD. Assume the buffer is at 0x0000_1000 in main memory.  
RxBD[Status and Control]= 0xB000, RxBD[Data Length] = 0x0000 (not required),  
and RxBD[Buffer Pointer] = 0x0000_1000.  
MOTOROLA  
Chapter 21. SCC HDLC Mode  
21-15  
   
Part IV. Communications Processor Module  
19.Initialize the TxBD. Assume the Tx data frame is at 0x0000_2000 in main memory  
and contains Þve 8-bit characters. TxBD[Status and Control] = 0xBC00,  
TxBD[Data Length] = 0x0005, and TxBD[Buffer Pointer] = 0x0000_2000.  
20.Write 0xFFFF to SCCE to clear any previous events.  
21.Write 0x001A to SCCM to enable TXE, RXF, and TXB interrupts.  
22.Write 0x0040_0000 to the SIU interrupt mask register low (SIMR_L) so the SMC1  
can generate a system interrupt. Initialize SIU interrupt pending register low  
(SIPNR_L) by writing 0xFFFF_FFFF to it.  
23.Write 0x0000_0000 to GSMR_H2 to enable normal CTS and CD behavior with  
idles (not ßags) between frames.  
24.Write 0x0000_0000 to GSMR_L2 to conÞgure CTS and CD to control transmission  
and reception in HDLC mode. Normal Tx clock operation is used. Notice that the  
transmitter (ENT) and receiver (ENR) have not been enabled. If inverted HDLC  
operation is preferred, set RINV and TINV.  
25.Write 0x0000 to PSMR2 to conÞgure one opening and one closing ßag, 16-bit  
CCITT-CRC, and prevent multiple frames in the FIFO.  
26.Write 0x00000030 to GSMR_L2 to enable the SCC2 transmitter and receiver. This  
additional write ensures that ENT and ENR are enabled last.  
Note that after 5 bytes and CRC have been sent, the Tx buffer is closed; the Rx buffer is  
closed after a frame is received. Frames larger than 256 bytes cause a busy (out-of-buffers)  
condition because only one RxBD is prepared.  
21.13.2 SCC HDLC Programming Example #2  
The following sequence initializes an HDLC channel that uses the DPLL in a Manchester  
encoding. Provide a clock which is 16´ the chosen bit rate of CLK3. Then connect CLK3  
to the HDLC transmitter and receiver. (A baud rate generator could be used instead.)  
ConÞgure SCC2 to use RTS2, CTS2, and CD2.  
1. Follow steps 1Ð22 in example #1 above.  
2. Write 0x004A_A400 to GSMR_L2 to make carrier sense always active, a 16-bit  
preamble of Ô01Õpatterns, 16´ operation of the DPLL and Manchester encoding for  
the receiver and transmitter, and HDLC mode. CTS and CD should be conÞgured to  
control transmission and reception. Do not set GSMR[ENT, ENR].  
3. Write 0x0000 to PSMR2 to use one opening and one closing ßag and 16-bit CCITT-  
CRC and to reject multiple frames in the FIFO.  
4. Write 0x004A_A430 to GSMR_L2 to enable the SCC2 transmitter and receiver.  
This additional write to GSMR_L2 ensures that ENT and ENR are enabled last.  
21-16  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
21.14 HDLC Bus Mode with Collision Detection  
The HDLC controller includes an option for hardware collision detection and  
retransmission on an open-drain connected HDLC bus, referred to as HDLC bus mode.  
Most HDLC-based controllers provide only point-to-point communications; however, the  
HDLC bus enhancement allows implementation of an HDLC-based LAN and other point-  
to-multipoint conÞgurations. The HDLC bus is based on techniques used in the CCITT  
ISDN I.430 and ANSI T1.605 standards for D-channel point-to-multipoint operation over  
the S/T interface. However, the HDLC bus does not fully comply with I.430 or T1.605 and  
cannot replace devices that implement these protocols. Instead, it is more suited to non-  
ISDN LAN and point-to-multipoint conÞgurations.  
Review the basic features of the I.430 and T1.605 before learning about the HDLC bus. The  
I.430 and T1.605 deÞne a way to connect eight terminals over the D-channel of the S/T  
ISDN bus. The layer 2 protocol is a variant of HDLC, called LAPD. However, at layer 1, a  
method is provided to allow the eight terminals to send frames to the switch through the  
physical S/T bus.  
To determine whether a channel is clear, the S/T interface device looks at an echo bit on the  
line designed to echo the last bit sent on the D channel. Depending on the class of terminal  
and the context, an S/T interface device waits for 7Ð10 ones on the echo bit before letting  
the LAPD frame begin transmission, after which the S/T interface monitors transmitted  
data. As long as the echo bit matches the sent data, transmission continues. If the echo bit  
is ever 0 when the transmit bit is 1, a collision occurs between terminals; the station(s) that  
sent a zero stops transmitting. The station that sent a 1 continues as normal.  
The I.430 and T1.605 standards provide a physical layer protocol that allows multiple  
terminals to share one physical connection. These protocols handle collisions efÞciently  
because one station can always complete its transmission, at which point, it lowers its own  
priority to give other devices fair access to the physical connection.  
The HDLC bus differs from the I.430 and T1.605 standards as follows:  
¥
The HDLC bus uses a separate input signal rather than the echo bit to monitor data;  
the transmitted data is simply connected to the CTS input.  
¥
The HDLC bus is a synchronous, digital open-drain connection for short-distance  
conÞgurations, rather than the more complex S/T interface.  
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¥
Any HDLC-based frame protocol can be used at layer 2, not just LAPD.  
HDLC bus devices wait 8Ð10 rather than 7Ð10 bit times before transmitting. (HDLC  
bus has only one class.)  
The collision-detection mechanism supports only:  
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NRZ-encoded data  
A common synchronous clock for all receivers and transmitters  
Non-inverted data (GSMR[RINV, TINV] = 0)  
Open-drain connection with no external transceivers  
MOTOROLA  
Chapter 21. SCC HDLC Mode  
21-17  
   
Part IV. Communications Processor Module  
Figure 21-10 shows the most common HDLC bus LAN conÞguration, a multimaster  
conÞguration. A station can transfer data to or from any other LAN station. Transmissions  
are half-duplex, which is typical in LANs.  
+ 5 V  
R
HDLC Bus LAN  
RXD TXD CTS  
RXD TXD CTS  
RXD TXD CTS  
HDLC Bus  
Controller  
A
HDLC Bus  
Controller  
B
HDLC Bus  
Controller  
C
RCLK/TCLK  
RCLK/TCLK  
RCLK/TCLK  
Clock  
Master  
Master  
Master  
NOTES:  
1. Transceivers may be used to extend the LAN size.  
2. The TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port.  
3. Clock is a common RCLK/TCLK for all stations.  
Figure 21-10. Typical HDLC Bus Multimaster Configuration  
In single-master conÞguration, a master station transmits to any slave station without  
collisions. Slaves communicate only with the master, but can experience collisions in their  
access over the bus. In this conÞguration, a slave that communicates with another slave  
must Þrst transmit its data to the master, where the data is buffered in RAM and then resent  
to the other slave. The beneÞt of this conÞguration, however, is that full-duplex operation  
can be obtained. In a point-to-multipoint environment, this is the preferred conÞguration.  
Figure 21-11 shows the single-master conÞguration.  
21-18  
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MOTOROLA  
   
Part IV. Communications Processor Module  
+ 5 V  
R
HDLC Bus LAN  
RXD  
TXD  
RXD TXD CTS  
RXD TXD CTS  
HDLC  
Controller  
A
HDLC Bus  
Controller  
B
HDLC Bus  
Controller  
C
RCLK  
TCLK  
RCLK  
TCLK  
RCLK  
TCLK  
Clock1  
Clock2  
Master  
Slave  
Slave  
NOTES:  
1. Transceivers may be used to extend the LAN size.  
2. The TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port.  
3. Clock1 is the master RCLK and the slave TCLK.  
4. Clock2 is the master TCLK and the slave RCLK.  
Figure 21-11. Typical HDLC Bus Single-Master Configuration  
21.14.1 HDLC Bus Features  
The main features of the HDLC bus are as follows:  
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Superset of the HDLC controller features  
Automatic HDLC bus access  
Automatic retransmission in case of collision  
May be used with the NMSI or a TDM bus  
Delayed RTS mode  
21.14.2 Accessing the HDLC Bus  
The HDLC bus protocol ensures orderly bus control when multiple transmitters attempt  
simultaneous access. The transmitter sending a zero bit at the time of collision completes  
the transmission. If a station sends out an opening ßag (0x7E) while another station is  
already sending, the collision is always detected within the Þrst byte, because the  
transmission in progress is using zero bit insertion to prevent ßag imitation.  
While in the active condition (ready to transmit), the HDLC bus controller monitors the bus  
using CTS. It counts the one bits on CTS. When eight consecutive ones are counted, the  
HDLC bus controller starts transmitting on the line; if a zero is detected, the internal  
counter is cleared. During transmission, data is continuously compared with the external  
bus using CTS. CTS is sampled halfway through the bit time using the rising edge of the  
Tx clock. If the transmitted bit matches the received CTS bus sample, transmission  
continues. However, if the received CTS sample is 0 and the transmitted bit is 1,  
MOTOROLA  
Chapter 21. SCC HDLC Mode  
21-19  
           
Part IV. Communications Processor Module  
transmission stops after that bit and waits for an idle line before attempting retransmission.  
Since the HDLC bus uses a wired-OR scheme, a transmitted zero has priority over a  
transmitted 1. Figure 21-12 shows how CTS is used to detect collisions.  
TCLK  
TXD  
(Output)  
CTS  
(Input)  
CTS sampled at halfway point.  
Collision detected when  
TXD=1, but CTS=0.  
Figure 21-12. Detecting an HDLC Bus Collision  
If both the destination address and source address are included in the HDLC frame, then a  
predeÞned priority of stations results; if two stations begin to transmit simultaneously, they  
necessarily detect a collision no later than the end of the source address.  
The HDLC bus priority mechanism ensures that stations share the bus equally. To minimize  
idle time between messages, a station normally waits for eight one bits on the line before  
attempting transmission. After successfully sending a frame, a station waits for 10 rather  
than eight consecutive one bits before attempting another transmission. This mechanism  
ensures that another station waiting to transmit acquires the bus before a station can  
transmit twice. When a low priority station detects 10 consecutive ones, it tries to transmit;  
if it fails, it reinstates the high priority of waiting for only eight ones.  
21.14.3 Increasing Performance  
Because it uses a wired-OR conÞguration, HDLC bus performance is limited by the rise  
time of the one bit. To increase performance, give the one bit more rise time by using a  
clock that is low longer than it is high, as shown in Figure 21-13.  
21-20  
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MOTOROLA  
       
Part IV. Communications Processor Module  
TCLK  
TXD  
(Output)  
CTS  
(Input)  
CTS sampled at three quarter point.  
Collision detected when  
TXD=1, but CTS=0.  
Figure 21-13. Nonsymmetrical Tx Clock Duty Cycle for Increased Performance  
21.14.4 Delayed RTS Mode  
Figure 21-14 shows local HDLC bus controllers using a standard transmission line and a  
local bus. The controllers do not communicate with each other but with a station on the  
transmission line; yet the HDLC bus protocol controls access to the transmission line.  
+ 5 V  
Local HDLC Bus  
Rx  
R
Line Driver  
Tx  
(1-Bit Delay)  
RXD TXD CTS  
RXD TXD CTS  
HDLC Bus  
Controller  
A
HDLC Bus  
Controller  
B
EN  
RTS  
RTS  
NOTES:  
1. The TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port.  
2. The RTS pins of each HDLC bus controller are configured to delayed RTS mode.  
Figure 21-14. HDLC Bus Transmission Line Configuration  
Normally, RTS goes active at the beginning of the opening ßagÕs Þrst bit. Setting  
PSMR[BRM] delays RTS by one bit, which is useful when the HDLC bus connects  
multiple local stations to a transmission line. If the transmission line driver has a one-bit  
delay, the delayed RTS can be used to enable the output of the line driver. As a result, the  
electrical effects of collisions are isolated locally. Figure 21-15 shows RTS timing.  
MOTOROLA  
Chapter 21. SCC HDLC Mode  
21-21  
       
Part IV. Communications Processor Module  
Collision  
3rd Bit  
TCLK  
TXD  
CTS  
RTS  
1st Bit  
2nd Bit  
RTS active for  
only 2 bit times  
Figure 21-15. Delayed RTS Mode  
21.14.5 Using the Time-Slot Assigner (TSA)  
HDLC bus controllers can be used with a time-division multiplexed transmission line and  
a local bus, as shown in Figure 21-16. Local stations use time slots to communicate over  
the TDM transmission line; stations that share a time slot use the HDLC bus protocol to  
control access to the local bus.  
+ 5 V  
Local HDLC Bus  
Rx  
R
Tx  
Line Driver  
L1RXD L1TXD CTS  
L1RXD L1TXD CTS  
L1RXD L1TXD CTS  
L1RXD L1TXD CTS  
HDLC Bus  
Controller  
A
HDLC Bus  
Controller  
B
HDLC Bus  
Controller  
C
HDLC Bus  
Controller  
D
Stations share time-slot n  
Stations share time-slot m  
NOTES:  
1. All TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port.  
2. The TSA in the SI of each station is used to configure the preferred time slot.  
3. The choice of the number of stations to share a time slot is user-defined. It is two in this example.  
Figure 21-16. HDLC Bus TDM Transmission Line Configuration  
The local SCCs in HDLC bus mode communicate only with the transmission line and not  
with each other. The SCCs use the TSA of the serial interface, receiving and sending data  
over L1TXDx and L1RXDx. Because collisions are still detected from the individual SCC  
CTS pin, it must be conÞgured to connect to the chosen SCC. Because the SCC only  
receives clocks during its time slot, CTS is sampled only during the Tx clock edges of the  
particular SCC time slot.  
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MOTOROLA  
       
Part IV. Communications Processor Module  
21.14.6 HDLC Bus Protocol Programming  
The HDLC bus on the MPC8260 is implemented using the SCC in HDLC mode with bus-  
speciÞc options selected in the PSMR and GSMR, as outlined below. See also Section 21.5,  
ÒProgramming the SCC in HDLC Mode.Ó  
21.14.6.1 Programming GSMR and PSMR for the HDLC Bus Protocol  
To program the protocol-speciÞc mode register (PSMR), set the bits as described below:  
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ConÞgure NOF as preferred  
Set RTE and BUS to 1  
Set BRM to 1 if delayed RTS is desired  
ConÞgure CRC to 16-bit CRC CCITT (0b00).  
ConÞgure other bits to zero or default.  
To program the general SCC mode register (GSMR), set the bits as described below:  
¥
¥
¥
¥
¥
¥
¥
Set MODE to HDLC mode (0b0000).  
ConÞgure CTSS to 1 and all other bits to zero or default.  
ConÞgure the DIAG bits for normal operation (0b00).  
ConÞgure RDCR and TDCR for 1´ clock (0b00).  
ConÞgure TENC and RENC for NRZ (0b000).  
Clear RTSM to send idles between frames.  
Set GSMR_L[ENT, ENR] as the last step to begin operation.  
21.14.6.2 HDLC Bus Controller Programming Example  
Except for the above discussion in Section 21.14.6.1, ÒProgramming GSMR and PSMR for  
the HDLC Bus Protocol,Ó use the example in Section 21.13.1, ÒSCC HDLC Programming  
Example #1.Ó  
MOTOROLA  
Chapter 21. SCC HDLC Mode  
21-23  
             
Part IV. Communications Processor Module  
21-24  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Chapter 22  
SCC BISYNC Mode  
220  
2T20 he byte-oriented BISYNC protocol was developed by IBM for use in networking  
products. There are three classes of BISYNC framesÑtransparent, nontransparent with  
header, and nontransparent without header, shown in Figure 22-1. The transparent frame  
type in BISYNC is not related to transparent mode, discussed in Chapter 23, ÒSCC  
Transparent Mode.Ó Transparent BISYNC mode allows full binary data to be sent with any  
possible character pattern. Each class of frame starts with a standard two-octet  
synchronization pattern and ends with a block check code (BCC). The end-of-text character  
(ETX) is used to separate the text and BCC Þelds.  
Nontransparent with Header  
SYN1  
SYN1  
SYN1  
SYN2  
SYN2  
SYN2  
SOH  
STX  
DLE  
Header  
STX  
Text  
ETX  
ETX  
ETX  
BCC  
BCC  
BCC  
Nontransparent without Header  
Text  
Transparent  
STX  
Transparent  
Text  
DLE  
Figure 22-1. Classes of BISYNC Frames  
The bulk of a frame is divided into Þelds whose meaning depends on the frame type. The  
BCC is a 16-bit CRC format if 8-bit characters are used; it is a combination longitudinal  
(sum check) and vertical (parity) redundancy check if 7-bit characters are used. In  
transparent operation, a special character (DLE) is deÞned that tells the receiver that the  
next character is text, allowing BISYNC control characters to be valid text data in a frame.  
A DLE sent as data must be preceded by a DLE character. This is sometimes called byte-  
stufÞng. The physical layer of the BISYNC communications link must synchronize the  
receiver and transmitter, usually by sending at least one pair of synchronization characters  
before each frame.  
BISYNC protocol is unusual in that a transmit underrun need not be an error. If an underrun  
occurs, a synchronization pattern is sent until data is again ready. In nontransparent  
operation, the receiver discards additional synchronization characters (SYNCs) as they are  
received. In transparent mode, DLE-SYNC pairs are discarded. Normally, for proper  
MOTOROLA  
Chapter 22. SCC BISYNC Mode  
22-1  
           
Part IV. Communications Processor Module  
transmission, an underrun must not occur between the DLE and its following character.  
This failure mode cannot occur with the MPC8260.  
An SCC can be conÞgured as a BISYNC controller to handle basic BISYNC protocol in  
normal and transparent modes. The controller can work with the time-slot assigner (TSA)  
or nonmultiplexed serial interface (NMSI). The controller has separate transmit and receive  
sections whose operations are asynchronous with the core and either synchronous or  
asynchronous with other SCCs.  
22.1 Features  
The following list summarizes features of the SCC in BISYNC mode:  
¥
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¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
Flexible data buffers  
Eight control character recognition registers  
Automatic SYNC1ÐSYNC2 detection  
16-bit pattern (bisync)  
8-bit pattern (monosync)  
4-bit pattern (nibblesync)  
External SYNC pin support  
SYNC/DLE stripping and insertion  
CRC16 and LRC (sum check) generation/checking  
VRC (parity) generation/checking  
Supports BISYNC transparent operation  
Maintains parity error counter  
Reverse data mode capability  
22.2 SCC BISYNC Channel Frame Transmission  
The BISYNC transmitter is designed to work with almost no core intervention. When the  
transmitter is enabled, it starts sending SYN1ÐSYN2 pairs in the data synchronization  
register (DSR) or idles as programmed in the PSMR. The BISYNC controller polls the Þrst  
BD in the channelÕs TxBD table. If there is a message to send, the controller fetches the  
message from memory and starts sending it after the SYN1ÐSYN2 pair. The entire pair is  
always sent, regardless of GSMR[SYNL].  
After a buffer is sent, if the last (TxBD[L]) and the Tx block check sequence (TxBD[TB])  
bits are set, the BISYNC controller appends the CRC16/LRC and then writes the message  
status bits in TxBD status and control Þelds and clears the ready bit, TxBD[R]. It then starts  
sending the SYN1ÐSYN2 pairs or idles, according to GSMR[RTSM]. If the end of the  
current BD is reached and TxBD[L] is not set, only TxBD[R] is cleared. In both cases, an  
interrupt is issued according to TxBD[I]. TxBD[I] controls whether interrupts are generated  
after transmission of each buffer, a speciÞc buffer, or each block. The controller then  
proceeds to the next BD.  
22-2  
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Part IV. Communications Processor Module  
If no additional buffers have been sent to the controller for transmission, an in-frame  
underrun is detected and the controller starts sending syncs or idles. If the controller is in  
transparent mode, it sends DLE-sync pairs. Characters are included in the block check  
sequence (BCS) calculation on a per-buffer basis. Each buffer can be programmed  
independently to be included or excluded from the BCS calculation; thus, excluded  
characters must reside in a separate buffer. The controller can reset the BCS generator  
before sending a speciÞc buffer. In transparent mode, the controller inserts a DLE before  
sending a DLE character, so that only one DLE is used in the calculation.  
22.3 SCC BISYNC Channel Frame Reception  
Although the receiver is designed to work with almost no core intervention, the user can  
intervene on a per-byte basis if necessary. The receiver performs CRC16, longitudinal  
(LRC) or vertical redundancy (VRC) checking, sync stripping in normal mode, DLE-sync  
stripping, stripping of the Þrst DLE in DLE-DLE pairs in transparent mode, and control  
character recognition. Control characters are discussed in Section 22.6, ÒSCC BISYNC  
Control Character Recognition.Ó  
When enabled, the receiver enters hunt mode where the data is shifted into the receiver shift  
register one bit at a time and the contents of the shift register are compared to the contents  
of DSR[SYN1, SYN2]. If the two are unequal, the next bit is shifted in and the comparison  
is repeated. When registers match, hunt mode is terminated and character assembly begins.  
The controller is character-synchronized and performs SYNC stripping and message  
reception. It reverts to hunt mode when it receives an ENTER HUNT MODE command, an error  
condition, or an appropriate control character.  
When receiving data, the controller updates the BCS bit in the BD for each byte transferred.  
When the buffer is full, the controller clears the E bit in the BD and generates an interrupt  
if the I bit in the BD is set. If incoming data exceeds the buffer length, the controller fetches  
the next BD; if E is zero, reception continues to its buffer.  
When a BCS is received, it is checked and written to the buffer. The BISYNC controller  
sets the last bit, writes the message status bits into the BD, clears the E bit, and then  
generates a maskable interrupt, indicating that a block of data was received and is in  
memory. The BCS calculations do not include SYNCs (in nontransparent mode) or DLE-  
SYNC pairs (in transparent mode).  
Note that GSMR_H[RFW] should be set for an 8-bit-wide receive FIFO for the BISYNC  
receiver. See Section 19.1.1, ÒThe General SCC Mode Registers (GSMR1ÐGSMR4).Ó  
22.4 SCC BISYNC Parameter RAM  
For BISYNC mode, the protocol-speciÞc area of the SCC parameter RAM is mapped as in  
Table 22-1.  
MOTOROLA  
Chapter 22. SCC BISYNC Mode  
22-3  
       
Part IV. Communications Processor Module  
Table 22-1. SCC BISYNC Parameter RAM Memory Map  
1
Offset  
Name  
Width  
Description  
0x30  
0x34  
0x38  
0x3A  
0x3C  
Ñ
Word  
Word  
Reserved  
CRCC  
CRC constant temp value.  
PRCRC  
PTCRC  
PAREC  
Hword Preset receiver/transmitter CRC16/LRC. These values should be preset to all  
ones or zeros, depending on the BCS used.  
Hword  
16  
Hword Receive parity error counter. This 16-bit (modulo 2 ) counter maintained by the  
CP counts parity errors on receive if the parity feature of BISYNC is enabled.  
Initialize PAREC while the channel is disabled.  
0x3E  
0x40  
BSYNC  
BDLE  
Hword BISYNC SYNC register. Contains the value of the SYNC to be sent as the second  
byte of a DLEÐSYNC pair in an underrun condition and stripped from incoming  
data on receive once the receiver synchronizes to the data using the DSR and  
SYN1ÐSYN2 pair. See Section 22.7, ÒBISYNC SYNC Register (BSYNC).Ó  
Hword BISYNC DLE register. Contains the value to be sent as the Þrst byte of a DLEÐ  
SYNC pair and stripped on receive. See Section 22.8, ÒSCC BISYNC DLE  
Register (BDLE).Ó  
0x42  
0x44  
0x46  
0x48  
0x4A  
0x4C  
0x4E  
0x50  
0x52  
CHARACTER1 Hword Control character 1Ð8. These values represent control characters that the  
BISYNC controller recognizes. See Section 22.6, ÒSCC BISYNC Control  
CHARACTER2 Hword  
Character Recognition.Ó  
CHARACTER3 Hword  
CHARACTER4 Hword  
CHARACTER5 Hword  
CHARACTER6 Hword  
CHARACTER7 Hword  
CHARACTER8 Hword  
RCCM  
Hword Receive control character mask. Masks CHARACTERn comparison so control  
character classes can be deÞned. Setting a bit enables and clearing a bit masks  
comparison. See Section 22.6, ÒSCC BISYNC Control Character Recognition.Ó  
1
From SCCx base address. See Section 19.3.1, ÒSCC Base Addresses.Ó  
GSMR[MODE] determines the protocol for each SCC. The SYN1ÐSYN2 synchronization  
characters are programmed in the DSR (see Section 19.1.3, ÒData Synchronization  
Register (DSR).Ó) The BISYNC controller uses the same basic data structure as other  
modes; receive and transmit errors are reported through their respective BDs. There are two  
basic ways to handle BISYNC channels:  
¥
¥
The controller can inspect data on a per-byte basis and interrupt the core each time  
a byte is received.  
The controller can be programmed so software handles the Þrst two or three bytes.  
The controller directly handles subsequent data without interrupting the core.  
22-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
22.5 SCC BISYNC Commands  
Transmit and receive commands are issued to the CP command register (CPCR). Transmit  
commands are described in Table 22-2.  
Table 22-2. Transmit Commands  
Command  
Description  
STOP  
After hardware or software is reset and the channel is enabled in the GSMR, the channel is in transmit  
enable mode and starts polling the Þrst BD every 64 transmit clocks.This command stops transmission  
after a maximum of 64 additional bits without waiting for the end of the buffer and the transmit FIFO to  
be ßushed. TBPTR is not advanced, no new BD is accessed, and no new buffers are sent for this  
channel. SYNCÐSYNC or DLEÐSYNC pairs are sent continually until a RESTART TRANSMIT is issued. A  
STOP TRANSMIT can be used when an EOT sequence should be sent and transmission should stop.  
After transmission resumes, the EOT sequence should be the Þrst buffer sent to the controller.  
Note that the controller remains in transparent or normal mode after it receives a STOP TRANSMIT or  
RESTART TRANSMIT command.  
TRANSMIT  
GRACEFUL  
STOP  
Stops transmission after the current frame Þnishes sending or immediately if there is no frame being  
sent. SCCE[GRA] is set once transmission stops. Then BISYNC transmit parameters and TxBDs can  
be modiÞed. The TBPTR points to the next TxBD. Transmission resumes when the R bit of the next BD  
is set and a RESTART TRANSMIT is issued.  
TRANSMIT  
RESTART  
TRANSMIT  
Lets characters be sent on the transmit channel. The BISYNC controller expects it after a STOP  
TRANSMIT or a GRACEFUL STOP TRANSMIT command is issued, after a transmitter error occurs, or after a  
STOP TRANSMIT is issued and the channel is disabled in its SCCM.The controller resumes transmission  
from the current TBPTR in the channelÕs TxBD table.  
INIT TX Initializes all transmit parameters in the serial channelÕs parameter RAM to their reset state. Issue only  
PARAMETERS when the transmitter is disabled. INIT TX AND RX PARAMETERS resets transmit and receive parameters.  
Receive commands are described in Table 22-2.  
Table 22-3. Receive Commands  
Command  
Description  
RESET BCS Immediately resets the receive BCS accumulator. It can be used to reset the BCS after recognizing a  
CALCULATION control character, thus signifying that a new block is beginning.  
ENTER HUNT After hardware or software is reset and the channel is enabled in SCCM, the channel is in receive  
MODE  
enable mode and uses the Þrst BD. This command forces the controller to stop receiving and enter  
hunt mode, during which the controller continually scans the data stream for an SYN1ÐSYN2  
sequence as programmed in the DSR. After receiving the command, the current receive buffer is  
closed and the BCS is reset. Message reception continues using the next BD.  
CLOSE RXBD Used to force the SCC to close the current RxBD if it is in use and to use the next BD for subsequent  
data. If data is not being received, no action is taken.  
INIT RX Initializes receive parameters in this serial channelÕs parameter RAM to reset state. Issue only when  
PARAMETERS the receiver is disabled. An INIT TX AND RX PARAMETERS resets transmit and receive parameters.  
MOTOROLA  
Chapter 22. SCC BISYNC Mode  
22-5  
       
Part IV. Communications Processor Module  
22.6 SCC BISYNC Control Character Recognition  
The BISYNC controller recognizes special control characters that customize the protocol  
implemented by the BISYNC controller and aid its operation in a DMA-oriented  
environment. They are used for receive buffers longer than one byte. In single-byte buffers,  
each byte can be easily inspected so control character recognition should be disabled.  
The control character table lets the BISYNC controller recognize the end of the current  
block. Because the controller imposes no restrictions on the format of BISYNC blocks,  
software must respond to received characters and inform the controller of mode changes  
and of certain protocol events, such as resetting the BCS. Using the control character table  
correctly allows the remainder of the block to be received without interrupting software.  
Up to eight control characters can be deÞned to inform the BISYNC controller that the end  
of the current block is reached and whether a BCS is expected after the character. For  
example, the end-of-text character (ETX) implies an end-of-block (ETB) with a subsequent  
BCS. An enquiry (ENQ) character designates an end of block without a subsequent BCS.  
All the control characters are written into the data buffer. The BISYNC controller uses a  
table of 16-bit entries to support control character recognition. Each entry consists of the  
control character, an end-of-table bit (E), a BCS expected bit (B), and a hunt mode bit (H).  
The RCCM entry deÞnes classes of control characters that support masking option.  
Offset from  
SCCx Base  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
0x42  
0x44  
0x46  
0x48  
0x4A  
0x4D  
0x4E  
0x50  
0x52  
E
E
E
E
E
E
E
E
1
B
B
B
B
B
B
B
B
1
H
H
H
H
H
H
H
H
1
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
CHARACTER1  
CHARACTER2  
CHARACTER3  
CHARACTER4  
CHARACTER5  
CHARACTER6  
CHARACTER7  
CHARACTER8  
MASK VALUE(RCCM)  
Figure 22-2. Control Character Table and RCCM  
22-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part IV. Communications Processor Module  
Table 22-4 describes control character table and RCCM Þelds.  
Table 22-4. Control Character Table and RCCM Field Descriptions  
Offset Bit  
Name  
Description  
0x42Ð  
0x50  
0
E
B
End of table.  
0 This entry is valid. The lower eight bits are checked against the incoming character.  
In tables with eight control characters, E should be zero in all eight positions.  
1 The entry is not valid. No other valid entries exist beyond this entry.  
1
BCS expected. A maskable interrupt is generated after the buffer is closed.  
0 The character is written into the receive buffer and the buffer is closed.  
1 The character is written into the receive buffer. The receiver waits for one LRC or  
two CRC bytes of BCS and then closes the buffer. This should be used for ETB,  
ETX, and ITB.  
2
H
Hunt mode. Enables hunt mode when the current buffer is closed.  
0 The BISYNC controller maintains character synchronization after closing this buffer.  
1 The BISYNC controller enters hunt mode after closing the buffer. When the B bit is  
set, the controller enters hunt mode after receiving the BCS.  
3Ð7  
Ñ
Reserved  
8Ð15 CHARACTERn Control character 1Ð8.When using 7-bit characters with parity, include the parity bit in  
the character value.  
0x52 0Ð2  
3Ð7  
Ñ
Ñ
All ones.  
Reserved  
8Ð15 RCCM  
Received control character mask. Masks comparison of CHARACTERn. Each bit of  
RCCM masks the corresponding bit of CHARACTERn.  
0 Mask this bit in the comparison of the incoming character and CHARACTERn.  
1 The address comparison on this bit proceeds normally and no masking occurs. If  
RCCM is not set, erratic operation can occur during control character recognition.  
22.7 BISYNC SYNC Register (BSYNC)  
The BSYNC register deÞnes BISYNC stripping and SYNC character insertion. When an  
underrun occurs, the BISYNC controller inserts SYNC characters until the next buffer is  
available for transmission. If the receiver is not in hunt mode when a SYNC character is  
received, it discards this character if the valid bit (BSYNC[V]) is set.When using 7-bit  
characters with parity, the parity bit should be included in the SYNC register value.  
Bit  
Field  
0
1
2
0
3
0
4
0
5
0
6
0
7
0
8
9
10  
11  
12  
13  
14  
15  
V
DIS  
SYNC  
Reset  
R/W  
UndeÞned  
R/W  
Address  
SCC Base + 0x3E  
Figure 22-3. BISYNC SYNC (BSYNC)  
MOTOROLA  
Chapter 22. SCC BISYNC Mode  
22-7  
       
Part IV. Communications Processor Module  
Table 22-5 describes BSYNC Þelds.  
Table 22-5. BSYNC Field Descriptions  
Bits  
Name  
Description  
0
1
V
Valid. If V = 1 and the receiver is not in hunt mode when a SYNC character is received, this  
character is discarded.  
DIS  
Disable BSYNC stripping  
0 Normal mode.  
1 BSYNC stripping disabled (BISYNC transparent mode only).  
2Ð7  
Ñ
All zeroes  
8Ð15  
SYNC  
SYNC character  
22.8 SCC BISYNC DLE Register (BDLE)  
The BDLE register is used to deÞne the BISYNC stripping and insertion of DLE characters.  
When an underrun occurs while a message is being sent in transparent mode, the BISYNC  
controller inserts DLE-SYNC pairs until the next buffer is available for transmission.  
In transparent mode, the receiver discards any DLE character received and excludes it from  
the BCS if the valid bit (BDLE[V]) is set. If the second character is SYNC, the controller  
discards it and excludes it from the BCS. If it is a DLE, the controller writes it to the buffer  
and includes it in the BCS. If it is not a DLE or SYNC, the controller examines the control  
character table and acts accordingly. If the character is not in the table, the buffer is closed  
with the DLE follow character error bit set. If the valid bit is not set, the receiver treats the  
character as a normal character. When using 7-bit characters with parity, the parity bit  
should be included in the DLE register value.  
Bit  
Field  
0
1
2
0
3
0
4
0
5
0
6
0
7
0
8
9
10  
11  
12  
13  
14  
15  
V
DIS  
DLE  
Reset  
R/W  
UndeÞned  
R/W  
Address  
SCC Base + 0x40  
Figure 22-4. BISYNC DLE (BDLE)  
22-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part IV. Communications Processor Module  
Table 22-6 describes BDLE Þelds.  
Table 22-6. BDLE Field Descriptions  
Bits  
Name  
Description  
0
1
V
Valid. If V = 1 and the receiver is not in hunt mode when a SYNC character is received, this  
character is discarded.  
DIS  
Disable DLE stripping  
0 Normal mode.  
1 DLE stripping disabled. When DIS is enabled in BDLE and on BSYNC the following cases  
occur:  
DLE-DLE sequence. Both characters are written to the memory.The BCS is calculated only on  
the second DLE.  
DLE-SYNC sequence. Both characters are written to the memory, but neither are included in  
the BCS calculation.  
DLE-ETX, DLE-ITB, DLE-ETB sequence, both characters are written to memory. The BCS is  
calculated only on the second character.  
2Ð7  
Ñ
All zeroes  
8Ð15  
SYNC  
SYNC character  
22.9 Sending and Receiving the Synchronization  
Sequence  
The BISYNC channel can be programmed to send and receive a synchronization pattern  
deÞned in the DSR. GSMR_H[SYNL] deÞnes pattern length, as shown in Table 22-7. The  
receiver synchronizes on this pattern. Unless SYNL is zero (external sync), the transmitter  
always sends the entire DSR contents, lsb Þrst, before each frameÑthe chosen 4- or 8-bit  
pattern can be repeated in the lower-order bits.  
Table 22-7. Receiver SYNC Pattern Lengths of the DSR  
Bit Assignments  
GSMR_H[SYNL]  
Setting  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
00  
01  
10  
11  
An external SYNC signal is used instead of the SYNC pattern in the DSR.  
4-Bit  
8-Bit  
16-Bit  
22.10 Handling Errors in the SCC BISYNC  
The controller reports message transmit and receive errors using the channel BDs, error  
counters, and the SCCE. Modem lines can be directly monitored via the parallel port pins.  
MOTOROLA  
Chapter 22. SCC BISYNC Mode  
22-9  
             
Part IV. Communications Processor Module  
Table 22-8 describes transmit errors.  
Table 22-8. Transmit Errors  
Error  
Description  
Transmitter  
Underrun  
The channel stops sending the buffer, closes it, sets TxBD[UN], and generates aTXE interrupt if it  
is enabled. The channel resumes transmission after a RESTART TRANSMIT command is received.  
Underrun cannot occur between frames or during a DLEÐXXX pair in transparent mode.  
CTS Lost during The channel stops sending the buffer, closes it, sets TxBD[CT], and generates a TXE interrupt if  
Message  
Transmission  
not masked. Transmission resumes when a RESTART TRANSMIT command is received.  
Table 22-9 describes receive errors.  
Table 22-9. Receive Errors  
Error  
Overrun  
Description  
The controller maintains a receiver FIFO for receiving data. The CP begins programming the SDMA  
channel (if the buffer is in external memory) and updating the CRC when the Þrst byte is received in  
the Rx FIFO. If an Rx FIFO overrun occurs, the controller writes the received byte over the  
previously received byte.The previous character and its status bits are lost.The channel then closes  
the buffer, sets RxBD[OV], and generates the RXB interrupt if it is enabled. Finally, the receiver  
enters hunt mode.  
CD Lost during The channel stops receiving, closes the buffer, sets RxBD[CD], and generates the RXB interrupt if  
Message  
Reception  
not masked. This error has the highest priority. If the rest of the message is lost, no other errors are  
checked in the message. The receiver immediately enters hunt mode.  
Parity  
CRC  
The channel writes the received character to the buffer and sets RxBD[PR]. The channel stops  
receiving, closes the buffer, sets RxBD[PR], and generates the RXB interrupt if it is enabled. The  
channel also increments PAREC and the receiver immediately enters hunt mode.  
The channel updates the CR bit in the BD every time a character is received with a byte delay of  
eight serial clocks between the status update and the CRC calculation. When control character  
recognition is used to detect the end of the block and cause CRC checking, the channel closes the  
buffer, sets the CR bit in the BD, and generates the RXB interrupt if it is enabled.  
22.11 BISYNC Mode Register (PSMR)  
The PSMR is used as the BISYNC mode register, shown in Figure 22-5. PSMR[RBCS,  
RTR, RPM, TPM] can be modiÞed on-the-ßy.  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field  
Reset  
R/W  
NOS  
CRC  
RBCS RTR RVD DRT  
Ñ
RPM  
TPM  
0
R/W  
Addr  
0x11A08 (PSMR1); 0x11A28 (PSMR2); 0x11A48 (PSMR3); 0x11A68 (PSMR4)  
Figure 22-5. Protocol-Specific Mode Register for BISYNC (PSMR)  
22-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
           
Part IV. Communications Processor Module  
Table 22-10 describes PSMR Þelds.  
Table 22-10. PSMR Field Descriptions  
Bits Name  
Description  
0Ð3  
4Ð5  
NOS Minimum number of SYN1ÐSYN2 pairs (deÞned in DSR) sent between or before messages.If NOS =  
0000, one pair is sent. If NOS = 1111, 16 pairs are sent. The entire pair is always sent, regardless of  
how GSMR[SYNL) is set. NOS can be modiÞed on-the-ßy.  
CRC CRC selection.  
x0 Reserved.  
01 CRC16 (BISYNC). X16 + X15 + X2 + 1. PRCRC and PTCRC should be initialized to all zeros or  
all ones before the channel is enabled. In either case, the transmitter sends the calculated CRC  
noninverted and the receiver checks the CRC against zero. Eight-bit data characters (without  
parity) are conÞgured when CRC16 is chosen.  
11 LRC (sum check). (BISYNC). For even LRC, initialize PRCRC and PTCRC to zeroes before the  
channel is enabled; for odd LRC, they should be initialized to ones.  
Note that the receiver checks character parity when BCS is programmed to LRC and the receiver  
is not in transparent mode. The transmitter sends character parity when BCS is programmed to  
LRC and the transmitter is not in transparent mode. Use of parity in BISYNC assumes that 7-bit  
data characters are being used.  
6
7
RBCS Receive BCS. The receiver internally stores two BCS calculations separated by an eight serial clock  
delay to allow examination of a received byte to determine whether it should used in BCS calculation.  
0 Disable receive BCS.  
1 Enable receive BCS. Should be set (or reset) within the time taken to receive the following data  
byte. When RBCS is reset, BCS calculations exclude the latest fully received data byte. When  
RBCS is set, BCS calculations continue as normal.  
RTR Receiver transparent mode.  
0 Normal receiver mode with SYNC stripping and control character recognition.  
1 Transparent receiver mode. SYNCs, DLEs, and control characters are recognized only after a  
leading DLE character. The receiver calculates the CRC16 sequence even if it is programmed to  
LRC while in transparent mode. Initialize PRCRC to the CRC16 preset value before setting RTR.  
8
9
RVD Reverse data.  
0 Normal operation.  
1 Any portion of this SCC deÞned to operate in BISYNC mode operates by reversing the character bit  
order and sending the msb Þrst.  
DRT Disable receiver while sending. DRT should not be set for typical BISYNC operation.  
0 Normal operation.  
1 As the SCC sends data, the receiver is disabled and gated by the internal RTS signal. This helps if  
the BISYNC channel is being conÞgured onto a multidrop line and the user does not want to receive  
its own transmission. Although BISYNC usually uses a half-duplex protocol, the receiver is not  
actually disabled during transmission.  
10Ð11 Ñ  
Reserved, should be cleared.  
MOTOROLA  
Chapter 22. SCC BISYNC Mode  
22-11  
 
Part IV. Communications Processor Module  
Table 22-10. PSMR Field Descriptions (Continued)  
Bits Name  
Description  
12Ð13 RPM Receiver parity mode. Selects the type of parity check that the receiver performs. RPM can be  
modiÞed on-the-ßy and is ignored unless CRC = 11 (LRC). Receive parity errors cannot be disabled  
but can be ignored.  
00 Odd parity. The transmitter counts ones in the data word. If the sum is not odd, the parity bit is set  
to ensure an odd number. An even sum indicates a transmission error.  
01 Low parity. If the parity bit is not low, a parity error is reported.  
10 Even parity. An even number must result from the calculation performed at both ends of the line.  
11 High parity. If the parity bit is not high, a parity error is reported.  
14Ð15 TPM Transmitter parity mode. Selects the type of parity the transmitter performs and can be modiÞed  
on-the-ßy. TPM is ignored unless CRC = 11 (LRC).  
00 Odd parity.  
01 Force low parity (always send a zero in the parity bit position).  
10 Even parity.  
11 Force high parity (always send a one in the parity bit position).  
22.12 SCC BISYNC Receive BD (RxBD)  
The CP uses BDs to report on each buffer received. It closes the buffer, generates a  
maskable interrupt, and starts receiving data into the next buffer after any of the following:  
¥
¥
¥
¥
¥
A user-deÞned control character is received.  
An error is detected.  
A full receive buffer is detected.  
The ENTER HUNT MODE command is issued.  
The CLOSE RX BD command is issued.  
Figure 22-6 shows the SCC BISYNC RxBD.  
0
1
2
3
4
L
5
F
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
E
Ñ
W
I
CM  
Ñ
DE  
Ñ
NO PR  
CR  
OV  
CD  
Data Length  
Rx Data Buffer Pointer  
Figure 22-6. SCC BISYNC RxBD  
Table 22-11 describes SCC BISYNC RxBD status and control Þelds.  
Table 22-11. SCC BISYNC RxBD Status and Control Field Descriptions  
Bits Name  
Description  
0
E
Empty.  
0 The buffer is full or stopped receiving because of an error.The core can read or write any Þelds of this  
RxBD. The CP does not use this BD as long as the E bit is zero.  
1 The buffer is not full. The CP controls this BD and buffer. The core should not update this BD.  
22-12  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part IV. Communications Processor Module  
Table 22-11. SCC BISYNC RxBD Status and Control Field Descriptions (Continued)  
Bits Name  
Description  
1
Ñ
Reserved, should be cleared.  
2
W
Wrap (last BD in table).  
0 Not the last BD in the table.  
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the Þrst BD that  
RBASE points to. The number of BDs in this table is determined by the W bit and by overall space  
constraints of the dual-port RAM.  
3
4
I
Interrupt.  
0 No interrupt is generated after this buffer is used.  
1 SCCE[RXB] is set when the controller closes this buffer, which can cause an interrupt if it is enabled.  
L
Last in frame. Set when this buffer is the last in a frame. If CD is negated in envelope mode or an error  
is received, one or more of the OV, CD, and DE bits are set. The controller writes the number of frame  
octets to the data length Þeld.  
0 Not the Þrst buffer in the frame.  
1 The Þrst buffer in the frame.  
5
6
F
First in frame. Set when this is the Þrst buffer in a frame.  
0 Not the Þrst buffer in a frame.  
1 First buffer in a frame  
CM  
Continuous mode.  
0 Normal operation.  
1 The CP does not clear E after this BD is closed; the buffer is overwritten when the CP accesses this  
BD next. However, E is cleared if an error occurs during reception, regardless of how CM is set.  
7
8
Ñ
Reserved, should be cleared.  
DE  
DPLL error. Set when a DPLL error occurs during reception. In decoding modes where a transition is  
should occur every bit, the DPLL error is set when a transition is missing.  
9Ð10 Ñ  
Reserved, should be cleared.  
11  
12  
13  
NO  
Rx non-octet-aligned frame. Set when a frame is received containing a number of bits not evenly  
divisible by eight.  
PR  
CR  
Parity error. Set when a character with parity error is received. Upon a parity error, the buffer is closed;  
thus, the corrupted character is the last byte of the buffer. A new Rx buffer receives subsequent data.  
Rx CRC error. Set when this frame contains a CRC error. Received CRC bytes are always written to  
the receive buffer.  
14  
15  
OV  
CD  
Overrun. Set when a receiver overrun occurs during frame reception.  
Carrier detect lost. Indicates when the carrier detect signal, CD, is negated during frame reception.  
Data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer  
Descriptors (BDs).Ó Data length represents the number of octets the CP writes into this  
buffer, including the BCS. For BISYNC mode, clear these bits. It is incremented each time  
a received character is written to the buffer.  
MOTOROLA  
Chapter 22. SCC BISYNC Mode  
22-13  
Part IV. Communications Processor Module  
22.13 SCC BISYNC Transmit BD (TxBD)  
The CP arranges data to be sent on an SCC channel in buffers referenced by the channel  
TxBD table. The CP uses BDs to conÞrm transmission or indicate errors so the core knows  
buffers have been serviced. The user conÞgures status and control bits before transmission,  
but the CP sets them after the buffer is sent.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
Ñ
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
R
Ñ
W
I
L
TB CM BR  
TD  
TR  
B
UN  
CT  
Data Length  
Tx Data Buffer Pointer  
Figure 22-7. SCC BISYNC Transmit BD (TxBD)  
Table 22-12 describes SCC BISYNC TxBD status and control Þelds.  
Table 22-12. SCC BISYNC TxBD Status and Control Field Descriptions  
Bits Name  
Description  
0
R
Ready.  
0 The buffer is not ready for transmission.The current BD and buffer can be updated.The CP clears R  
after the buffer is sent or after an error condition.  
1 The user-prepared buffer has not been sent or is being sent.This BD cannot be updated while R = 1.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (last BD in table).  
0 Not the last BD in the table.  
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the Þrst BD that  
TBASE points to. The number of TxBDs in this table is determined only by the W bit and overall  
space constraints of the dual-ported RAM.  
3
4
I
Interrupt.  
0 No interrupt is generated after this buffer is serviced.  
1 SCCE[TXB] or SCCE[TXE] is set after the CP services this buffer, which can cause an interrupt.  
L
Last in message.  
0 The last character in the buffer is not the last character in the current block.  
1 The last character in the buffer is the last character in the current block. The transmitter enters and  
stays in normal mode after sending the last character in the buffer and the BCS, if enabled.  
5
TB  
Transmit BCS. Valid only when the L bit is set.  
0 Send an SYN1ÐSYN2 or idle sequence (speciÞed in GSMR[RTSM]) after the last character in the  
buffer.  
1 Send the BCS sequence after the last character. The controller also resets the BCS generator after  
sending the BCS.  
6
7
CM  
BR  
Continuous mode.  
0 Normal operation.  
1 The CP does not clear R after this BD is closed, so the buffer is resent when the CP next accesses  
this BD. However, R is cleared if an error occurs during transmission, regardless of how CM is set.  
BCS reset. Determines whether transmitter BCS accumulation is reset before sending the data buffer.  
0 BCS accumulation is not reset.  
1 BCS accumulation is reset before sending the data buffer.  
22-14  
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MOTOROLA  
       
Part IV. Communications Processor Module  
Table 22-12. SCC BISYNC TxBD Status and Control Field Descriptions (Continued)  
Bits Name  
Description  
8
TD  
Transmit DLE.  
0 No automatic DLE transmission can occur before the data buffer.  
1 The transmitter sends a DLE character before sending the buffer, which saves writing the Þrst DLE to  
a separate buffer in transparent mode. See TR for information on control characters.  
9
TR  
Transparent mode.  
0 The transmitter enters and stays in normal mode after sending the buffer. The transmitter  
automatically inserts SYNCs if an underrun condition occurs.  
1 The transmitter enters or stays in transparent mode after sending the buffer. It automatically inserts  
DLEÐSYNC pairs if an underrun occurs (the controller Þnishes a buffer with L = 0 and the next BD is  
not available). It also checks all characters before sending them. If a DLE is detected, another DLE is  
sent automatically. Insert a DLE or program the controller to insert one before each control  
character. The transmitter calculates the CRC16 BCS even if PSMR[BCS] is programmed to LRC.  
Initialize PTCRC to CRC16 before setting TR.  
10  
B
BCS enable.  
0 The buffer consists of characters that are excluded from BCS accumulation.  
1 The buffer consists of characters that are included in BCS accumulation.  
11Ð13 Ñ  
Reserved, should be cleared.  
14  
UN  
Underrun. Set when the BISYNC controller encounters a transmitter underrun error while sending the  
associated data buffer. The CPM writes UN after it sends the associated buffer.  
15  
CT  
CTS lost.The CP sets CT when CTS is lost during message transmission after it sends the data buffer.  
Data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer  
Descriptors (BDs).Ó Although it is never modiÞed by the CP, data length should be greater  
than zero. The CPM writes these Þelds after it Þnishes sending the buffer.  
22.14 BISYNC Event Register (SCCE)/BISYNC Mask  
Register (SCCM)  
The BISYNC controller uses the SCC event register (SCCE) to report events recognized by  
the BISYNC channel and to generate interrupts. When an event is recognized, the controller  
sets the corresponding SCCE bit. Interrupts are enabled by setting, and masked by clearing,  
the equivalent bits in the BISYNC mask register (SCCM). SCCE bits are reset by writing  
ones; writing zeros has no effect. Unmasked bits must be reset before the CP negates the  
internal interrupt request signal.  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field  
Reset  
R/W  
Ñ
GLR GLT DCC  
Ñ
GRA  
Ñ
TXE RCH BSY TXB RXB  
0000_0000_0000_0000  
R/W  
Addr  
0x11A10 (SCCE1); 0x11A30 (SCCE2); 0x11A50 (SCCE3); 0x11A70 (SCCE4)  
0x11A14 (SCCM1); 0x11A34 (SCCM2); 0x11A54 (SCCM3); 0x11A74 (SCCM4)  
Figure 22-8. BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)  
MOTOROLA  
Chapter 22. SCC BISYNC Mode  
22-15  
       
Part IV. Communications Processor Module  
Table 22-13 describes SCCE and SCCM Þelds.  
Table 22-13. SCCE/SCCM Field Descriptions  
Bits Name  
Description  
0Ð2  
3
Ñ
Reserved, should be cleared.  
GLR  
GLT  
Glitch on receive. Set when the SCC Þnds an Rx clock glitch.  
Glitch on transmit. Set when the SCC Þnds a Tx clock glitch.  
4
5
DCC DPLL CS changed. Set when carrier sense status generated by the DPLL changes. Real-time status  
can be found in SCCS. This is not the CD status discussed elsewhere. Valid only when DPLL is used.  
6Ð7  
8
Ñ
Reserved, should be cleared.  
GRA Graceful stop complete. Set as soon the transmitter Þnishes any message in progress when a  
GRACEFUL STOP TRANSMIT is issued (immediately if no message is in progress).  
9Ð10 Ñ  
Reserved, should be cleared.  
11  
12  
13  
TXE  
Tx Error. Set when an error occurs on the transmitter channel.  
RCH Receive character. Set when a character is received and written to the buffer.  
BSY  
Busy. Set when a character is received and discarded due to a lack of buffers. The receiver resumes  
reception after an ENTER HUNT MODE command.  
14  
15  
TXB  
RXB  
Tx buffer. Set when a buffer is sent. TXB is set as the last bit of data or the BCS begins transmission.  
Rx buffer. Set when the CPM closes the receive buffer on the BISYNC channel.  
22.15 SCC Status Registers (SCCS)  
The SCC status (SCCS) register allows real-time monitoring of RXD. The real-time status  
of CTS and CD are part of the parallel I/O.  
Bit  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
Ñ
CS  
Ñ
0000_0000  
R
Addr  
0x11A17 (SCCS1); 0x11A37 (SCCS2); 0x11A57 (SCCS3); 0x11A77 (SCCS4)  
Figure 22-9. SCC Status Registers (SCCS)  
22-16  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part IV. Communications Processor Module  
Table 22-14 describes SCCS Þelds.  
Table 22-14. SCCS Field Descriptions  
Bit  
0Ð5  
Name  
Description  
Ñ
Reserved, should be cleared.  
6
CS  
Carrier sense (DPLL). Shows the real-time carrier sense of the line as determined by the DPLL.  
0 The DPLL does not sense a carrier.  
1 The DPLL senses a carrier.  
7
Ñ
Reserved, should be cleared.  
22.16 Programming the SCC BISYNC Controller  
Software has two ways to handle data received by the BISYNC controller. The simplest is  
to allocate single-byte receive buffers, request an interrupt on reception of each buffer, and  
implement BISYNC protocol entirely in software on a byte-by-byte basis. This ßexible  
approach can be adapted to any BISYNC implementation. The obvious penalty is the  
overhead caused by interrupts on each received character.  
A more efÞcient method is to prepare and link multi-byte buffers in the RxBD table and use  
software to analyze the Þrst two to three bytes of the buffer to determine the type of block  
received. When this is determined, reception continues without further software  
intervention until it encounters a control character, which signiÞes the end of the block and  
causes software to revert to byte-by-byte reception.  
To accomplish this, set SCCM[RCH] to enable an interrupt on every received byte so  
software can analyze each byte. After analyzing the initial characters of a block, either set  
PSMR[RTR] or issue a RESET BCS CALCULATION command. For example, if a DLE-STX is  
received, enter transparent mode. By setting the appropriate PSMR bit, the controller strips  
the leading DLE from DLE-character sequences. Thus, control characters are recognized  
only when they follow a DLE character. PSMR[RTR] should be cleared after a DLE-ETX  
is received.  
Alternatively, after an SOH is received, a RESET BCS CALCULATION should be issued to  
exclude SOH from BCS accumulation and reset the BCS. Notice that PSMR[RBCS] is not  
needed because the controller automatically excludes SYNCs and leading DLEs.  
After the type of block is recognized, SCCE[RCH] should be masked. The core does not  
interrupt data reception until the end of the current block, which is indicated by the  
reception of a control character matching the one in the receive control character table.  
Using Table 22-15, the control character table should be set to recognize the end of the  
block.  
MOTOROLA  
Chapter 22. SCC BISYNC Mode  
22-17  
     
Part IV. Communications Processor Module  
Table 22-15. Control Characters  
Control Characters  
E
B
H
ETX  
0
0
0
0
0
1
1
1
0
X
1
0
1
0
X
ITB  
ETB  
ENQ  
Next entry  
After ETX, a BCS is expected; then the buffer should be closed. Hunt mode should be  
entered when a line turnaround occurs. ENQ characters are used to stop sending a block  
and to designate the end of the block for a receiver, but no CRC is expected. After control  
character reception, set SCCM[RCH] to reenable interrupts for each byte of data received.  
22.17 SCC BISYNC Programming Example  
This BISYNC controller initialization example for SCC2 uses an external clock. The  
controller is conÞgured with RTS2, CTS2, and CD2 active. Both the receiver and  
transmitter use CLK3.  
1. ConÞgure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and  
PDIRD[27] and clear PDIRD[28] and PSORD[27,28].  
2. ConÞgure ports C and D pins to enable RTS2, CTS2 and CD2. Set PPARD[26],  
PPARC[12,13] and PDIRD[26] and clear PDIRC[12,13], PSORC[12,13], and  
PSORD[26].  
3. ConÞgure port C pin 29 to enable the CLK3 pin. Set PPARC[29] and clear  
PDIRC[29] and PSORC[29].  
4. Connect CLK3 to SCC2 using the CPM mux. Write 0b110 to CMXSCR[R2CS] and  
CMXSCR[T2CS].  
5. Connect the SCC2 to the NMSI (its own set of pins). Clear CMXSCR[SC2].  
6. Assuming one RxBD at the beginning of dual-port RAM followed by one TxBD,  
write RBASE with 0x0000 and TBASE with 0x0008.  
7. Write 0x04a1_0000 to CPCR to execute INIT RX AND TX PARAMETERS. This updates  
RBPTR and TBPTR to the new values of RBASE and TBASE.  
8. Write RFCR and TFCR with 0x10 for normal operation.  
9. Write MRBLR with the maximum number of bytes per receive buffer. For this case,  
assume 16 bytes, so MRBLR = 0x0010.  
10.Write PRCRC with 0x0000 to comply with CRC16.  
11.Write PTCRC with 0x0000 to comply with CRC16.  
12.Clear PAREC for clarity.  
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Part IV. Communications Processor Module  
13.Write BSYNC with 0x8033, assuming a SYNC value of 0x33.  
14.Write DSR with 0x3333.  
15.Write BDLE with 0x8055, assuming a DLE value of 0x55.  
16.Write CHARACTER1 with 0x6077, assuming ETX = 0x77.  
17.Write CHARACTER2Ð8 with 0x8000. They are not used.  
18.Write RCCM with 0xE0FF. It is not used.  
19.Initialize the RxBD and assume the data buffer is at 0x00001000 in main memory.  
Then write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length]  
(optional), and 0x00001000 to RxBD[Buffer Pointer].  
20.Initialize the TxBD and assume the Tx data buffer is at 0x00002000 in main memory  
and contains Þve 8-bit characters. Then write 0xBD20 to TxBD[Status and Control]  
0x0005 to TxBD[Data Length], and 0x00002000 to TxBD[Buffer Pointer]. Note  
that ETX character should be written at the end of userÕs data.  
21.Write 0xFFFF to SCCE to clear any previous events.  
22.Write 0x0013 to SCCM to enable the TXE, TXB, and RXB interrupts.  
23.Write 0x0040_0000 to the SIU interrupt mask register low (SIMR_L) so the SMC1  
can generate a system interrupt. Initialize SIU interrupt pending register low  
(SIPNR_L) by writing 0xFFFF_FFFF to it.  
24.Write 0x0000002C to GSMR_H2 to conÞgure a small receive FIFO width.  
25.Write 0x00000008 to GSMR_L2 to conÞgure CTS and CD to automatically control  
transmission and reception (DIAG bits) and the BISYNC mode. Notice that the  
transmitter (ENT) and receiver (ENR) are not yet enabled.  
26.Set PSMR to 0x0600 to conÞgure CRC16, CRC checking on receive, and normal  
operation (not transparent).  
27.Write 0x00000038 to GSMR_L2 to enable the SCC2 transmitter and receiver. This  
additional write ensures that ENT and ENR are enabled last.  
Write 0x00000038 to GSMR_L2 to enable the SCC2 transmitter and receiver. This  
additional write ensures that ENT and ENR are enabled last. After 5 bytes are sent, the  
TxBD is closed. The buffer is closed after 16 bytes are received. Any received data beyond  
16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared.  
MOTOROLA  
Chapter 22. SCC BISYNC Mode  
22-19  
Part IV. Communications Processor Module  
22-20  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Chapter 23  
SCC Transparent Mode  
230  
2T30 ransparent mode (also called totally transparent or promiscuous mode) provides a clear  
channel on which the SCC can send or receive serial data without bit-level manipulation.  
Software implements protocols run over transparent mode. An SCC in transparent mode  
functions as a high-speed serial-to-parallel and parallel-to-serial converter.  
Transparent mode can be used for serially moving data that requires no superimposed  
protocol, for applications that require serial-to-parallel and parallel-to-serial conversion for  
communication among chips on the same board, and for applications that require data to be  
switched without interfering with the protocol encoding itself, such as when data from a  
high-speed time-multiplexed serial stream is multiplexed into low-speed data streams. The  
concept is to switch the data path without altering the protocol encoded on that data path.  
Transparent mode is conÞgured in the GSMR; see Section 19.1.1, ÒThe General SCC Mode  
Registers (GSMR1ÐGSMR4).Ó Transparent mode is selected in GSMR_H[TTX, TRX] for  
the transmitter and receiver, respectively. Setting both bits enables full-duplex transparent  
operation. If only one is set, the other half of the SCC uses the protocol speciÞed in  
GSMR_L[MODE]. This allows loop-back modes to DMA data from one memory location  
to another while data is converted to a speciÞc serial format.  
The SCC operations are asynchronous with the core and can be synchronous or  
asynchronous with other SCCs. Each clock can be supplied from the internal baud rate  
generator bank, DPLL output, or external pins.  
The SCC can work with the time-slot assigner (TSA) or nonmultiplexed serial interface  
(NMSI) and supports modem lines with the general-purpose I/O pins. Data can be  
transferred either the msb or lsb Þrst in each octet.  
23.1 Features  
The following list summarizes the main features of the SCC in transparent mode:  
¥
¥
¥
¥
Flexible buffers  
Automatic SYNC detection on receive  
CRCs can be sent and received  
Reverse data mode  
MOTOROLA  
Chapter 23. SCCTransparent Mode  
23-1  
           
Part IV. Communications Processor Module  
¥
¥
Another protocol can be performed on the other half of the SCC  
MC68360-compatible SYNC options  
23.2 SCC Transparent Channel Frame Transmission  
Process  
The transparent transmitter is designed to work almost no intervention from the core. When  
the core enables the SCC transmitter in transparent mode, it starts sending idles, which are  
logic high or encoded ones, as programmed in GSMR_L[TEND]. The SCC polls the Þrst  
BD in the TxBD table. When there is a message to send, the SCC fetches data from  
memory, loads the transmit FIFO, and waits for transmitter synchronization, which is  
achieved with CTS or by waiting for the receiver to achieve synchronization, depending on  
GSMR_H[TXSY]. Transmission begins when transmitter synchronization is achieved.  
When all BD data has been sent, if TxBD[L] is set, the SCC writes the message status bits  
into the BD, clears TxBD[R], and sends idles until the next BD is ready. If it is ready, some  
idles are still sent. The transmitter resumes sending only after it achieves synchronization.  
If TxBD[L] is cleared when the end of the BD is reached, only TxBD[R] is cleared and the  
transmitter moves immediately to the next buffer to begin transmission with no gap on the  
serial line between buffers. Failure to provide the next buffer in time causes a transmit  
underrun which sets SCCE[TXE].  
In both cases, an interrupt is issued according to TxBD[I]. By appropriately setting  
TxBD[I] in each BD, interrupts are generated after each buffer or group of buffers is sent.  
The SCC then proceeds to the next BD in the table and any whole number of bytes can be  
sent. If GSMR_H[REVD] is set, the bit order of each byte is reversed before being sent; the  
msb of each octet is sent Þrst.  
Setting GSMR_H[TFL] makes the transmit FIFO smaller and reduces transmitter latency,  
but it can cause transmitter underruns at higher transmission speeds. An optional CRC,  
selected in GSMR_H[TCRC], can be appended to each transparent frame if it is enabled in  
the TxBD.  
When the time-slot assigner (TSA) is used with a transparent-mode channel,  
synchronization is provided by the TSA. There is a start-up delay for the transmitter, but  
delays will always be some whole number of complete TSA frames. This means that n-byte  
transmit buffers can be mapped directly into n-byte time slots in the TSA frames.  
23.3 SCC Transparent Channel Frame Reception  
Process  
When the core enables the SCC receiver in transparent mode, it waits to achieve  
synchronization before data is received. The receiver can be synchronized to the data by a  
synchronization pulse or SYNC pattern.  
23-2  
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MOTOROLA  
       
Part IV. Communications Processor Module  
After a buffer is full, the SCC clears RxBD[E] and generates a maskable interrupt if  
RxBD[I] is set. It moves to the next RxBD in the table and begins moving data to its buffer.  
If the next buffer is not available, SCCE[BSY] signiÞes a busy signal that can generate a  
maskable interrupt. The receiver reverts to hunt mode when an ENTER HUNT MODE  
command or an error is received. If GSMR_H[REVD] is set, the bit order of each byte is  
reversed before it is written to memory.  
Setting GSMR_H[RFW] reduces receiver latency by making the receive FIFO smaller,  
which may cause receiver overruns at higher transmission speeds. The receiver always  
checks the CRC of the received frame, according to GSMR_H[TCRC]. If a CRC is not  
required, resulting errors can be ignored.  
23.4 Achieving Synchronization in Transparent Mode  
Once the SCC transmitter is enabled for transparent operation, the TxBD is prepared and  
the transmit FIFO is preloaded by the SDMA channel, another process must occur before  
data can be sent. It is called transmit synchronization. Similarly, once the SCC receiver is  
enabled for transparent operation in the GSMR and the RxBD is made empty for the SCC,  
receive synchronization must occur before data can be received. An in-line synchronization  
pattern or an external synchronization signal can provide bit-level control of the  
synchronization process when sending or receiving.  
23.4.1 Synchronization in NMSI Mode  
This section describes synchronization in NMSI mode.  
23.4.1.1 In-Line Synchronization Pattern  
The transparent channel can be programmed to receive a synchronization pattern. This  
pattern is deÞned in the data synchronization register, DSR; see Section 19.1.3, ÒData  
Synchronization Register (DSR).Ó Pattern length is speciÞed in GSMR_H[SYNL], as  
shown in Table 23-1. See also Section 19.1.1, ÒThe General SCC Mode Registers  
(GSMR1ÐGSMR4).Ó  
Table 23-1. Receiver SYNC Pattern Lengths of the DSR  
Bit Assignments  
GSMR_H[SYNL]  
Setting  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
00  
01  
10  
11  
An external SYNC signal is used instead of the SYNC pattern in the DSR.  
4-bit  
8-bit  
16-bit  
If a 4-bit SYNC is selected, reception begins as soon as these four bits are received,  
beginning with the Þrst bit following the 4-bit SYNC. The transmitter synchronizes on the  
receiver pattern if GSMR_H[RSYN] = 1.  
MOTOROLA  
Chapter 23. SCCTransparent Mode  
23-3  
               
Part IV. Communications Processor Module  
Note that the transparent controller does not automatically send the synchronization  
pattern; therefore, the synchronization pattern must be included in the transmit buffer.  
23.4.1.2 External Synchronization Signals  
If GSMR_H[SYNL] is 0b00, the transmitter uses CTS and the receiver uses CD to begin  
the sequence. These signals share two optionsÑpulsing and sampling.  
GSMR_H[CDP] and GSMR_H[CTSP] determine whether CD or CTS need to be asserted  
only once to begin reception/transmission or whether they must remain asserted for the  
duration of the transparent frame. Pulse operation allows an uninterrupted stream of data.  
However, use envelope mode to identify frames of transparent data.  
The sampling option determines the delay between CD and CTS being asserted and the  
resulting action by the SCC. Assume either that these signals are asynchronous to the data  
and internally synchronized by the SCC or that they are synchronous to the data with faster  
operation. This option allows RTS of one SCC to be connected to CD of another SCC and  
to have the data synchronized and bit aligned. It is also an option to link the transmitter  
synchronization to the receiver synchronization. Diagrams for the pulse/envelope and  
sampling options are shown in Section 23.4, ÒAchieving Synchronization in Transparent  
Mode.Ó  
23.4.1.2.1 External Synchronization Example  
Figure shows synchronization using external signals.  
23-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part IV. Communications Processor Module  
MPC8260 (B)  
MPC8260 (A)  
TXD  
RXD  
CD  
RTS  
BRGOx  
RXD  
CLKx  
TXD  
CD  
RTS  
CLKx  
BRGOx  
BRGOx  
(Output is CLKx Input)  
TXD  
(Output is RXD Input)  
Last Bit of Frame Data  
or CRC  
First Bit of Frame Data  
RTS  
(Output is CD Input)  
TxBD[L] = 1 Causes Negation of RTS  
CD Lost Condition Terminates Reception of Frame  
Notes:  
1. Each MPC8260 generates its own transmit clocks. If the transmit and receive clocks are the same, one MPC8260  
can generate transmit and receive clocks for the other MPC8260. For example, CLKx on MPC8260 (B) could be  
used to clock the transmitter and receiver.  
2. CTS should be configured as always asserted in the parallel I/O or connected to ground externally.  
3. The required GSMR conÞgurations are DIAG= 00, CTSS=1, CTSP is a ÒdonÕt careÓ, CDS=1, CDP=0, TTX=1, and  
TRX=1. REVD and TCRC are application-dependent.  
4. The transparent frame contains a CRC if TxBD[TC] is set.  
Figure 23-1. Sending Transparent Frames between MPC8260s  
MPC8260(A) and MPC8260(B) exchange transparent frames and synchronize each other  
using RTS and CD. However, CTS is not required because transmission begins at any time.  
Thus, RTS is connected directly to the other MPC8260 CD pin. GSMR_H[RSYN] is not  
used and transmission and reception from each MPC8260 are independent.  
23.4.1.3 Transparent Mode without Explicit Synchronization  
If there is no need to synchronize the transparent controller at a speciÞc point, the user can  
ÔfakeÕ synchronization in one of the following ways:  
¥
¥
Tie a parallel I/O pin to the CTS and CD lines. Then, after enabling the receiver and  
transmitter, provide a falling edge by manipulating the I/O pin in software.  
Enable the receiver and transmitter for the SCC in loopback mode and then change  
GSMR_L[DIAG] to 0b00 while the transmitter and receiver and enabled.  
23.4.2 Synchronization and the TSA  
A transparent-mode SCC using the time-slot assigner can synchronize either on a user-  
deÞned inline pattern or by inherent synchronization.  
MOTOROLA  
Chapter 23. SCCTransparent Mode  
23-5  
           
Part IV. Communications Processor Module  
Note that when using the TSA, a newly-enabled transmitter sends from 10 to 15 frames of  
idles before sending the actual transparent data due to startup requirements of the TDM.  
Therefore, when loopback testing through the TDM, expect to receive several bytes of 0xFF  
before the actual data.  
23.4.2.1 Inline Synchronization Pattern  
The receiver can be programmed to begin receiving data into the receive buffers only after  
a speciÞed data pattern arrives. To synchronize on an inline pattern:  
¥
¥
¥
¥
Set GSMR_H[SYNL].  
Program the DSR with the desired pattern.  
Clear GSMR_H[CDP].  
Set GSMR_H[CTSP, CTSS, CDS].  
If GSMR_H[TXSY] is also used, the transmitter begins transmission eight clocks after the  
receiver achieves synchronization.  
23.4.2.2 Inherent Synchronization  
Inherent synchronization assumes synchronization by default when the channel is enabled;  
all data sent from the TDM to the SCC is received. To implement inherent synchronization:  
¥
Set GSMR_H[CDP, CDS, CTSP, CTSS].  
If these bits are not set, the received bit stream will be bit-shifted. The SCC loses the Þrst  
received bit because CD and CTS are treated as asynchronous signals.  
23.4.3 End of Frame Detection  
An end of frame cannot be detected in the transparent data stream since there is no deÞned  
closing ßag in transparent mode. Therefore, if framing is needed, the user must use the CD  
line to alert the transparent controller of an end of frame.  
23.5 CRC Calculation in Transparent Mode  
The CRC calculations follow the ITU/IEEE standard. The CRC is calculated on the  
transmitted data stream; that is, from lsb to msb for non-bit-reversed (GSMR_H[REVD] =  
0) and from msb to lsb for bit-reversed (GSMR_H[REVD] = 1) transmission. The  
appended CRC is sent msb to lsb. When receiving, the CRC is calculated as the incoming  
bits arrive. The optional reversal of data (GSMR_H[REVD] = 1) is done just before data is  
stored in memory (after the CRC calculation).  
23.6 SCC Transparent Parameter RAM  
For transparent mode, the protocol-speciÞc area of the SCC parameter RAM is mapped as  
in Table 23-2.  
23-6  
MPC8260 PowerQUICC II UserÕs Manual  
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Part IV. Communications Processor Module  
Table 23-2. SCC Transparent Parameter RAM Memory Map  
1
Offset  
Name Width  
Description  
0x 30 CRC_P Long CRC preset for totally transparent. For the 16-bit CRC-CCITT, initialize with 0x0000_FFFF.  
For the 32-bit CRC-CCITT, initialize with 0xFFFF_FFFF and for the CRC-16, initialize with  
ones (0x0000_FFFF) or zeros (0x0000_0000).  
0x 34 CRC_C Long CRC constant for totally transparent receiver. For the 16-bit CRC-CCITT, initialize with  
0x0000_F0B8. For the 32-bit CRC-CCITT, CRC_C initialize with 0xDEBB_20E3 and for  
the CRC-16, which is normally used with BISYNC, initialize with 0x0000_0000.  
1
From SCC base address. See Section 19.3.1, ÒSCC Base Addresses.Ó  
CRC_P and CRC_C overlap with the CRC parameters for the HDLC-based protocols.  
However, this overlap is not detrimental since the CRC constant is used only for the receiver  
and the CRC preset is used only for the transmitter, so only one entry is required for each.  
Thus, the user can choose an HDLC transmitter with a transparent receiver or a transparent  
transmitter with an HDLC receiver.  
23.7 SCC Transparent Commands  
The following transmit and receive commands are issued to the CP command register.  
Table 23-3 describes transmit commands.  
Table 23-3. Transmit Commands  
Command  
Description  
STOP  
After hardware or software is reset and the channel is enabled in the GSMR, the channel is in transmit  
enable mode and starts polling the Þrst BD every 64 clocks (or immediately if TODR[TOD] = 1). STOP  
TRANSMIT disables frame transmission on the transmit channel. If the transparent controller receives the  
command during frame transmission, transmission is aborted after a maximum of 64 additional bits  
and the transmit FIFO is ßushed. The current TxBD pointer (TBPTR) is not advanced, no new BD is  
accessed and no new buffers are sent for this channel. The transmitter will send idles.  
TRANSMIT  
GRACEFUL  
STOP  
Stops transmission smoothly, rather than abruptly, in much the same way that the regular STOP  
TRANSMIT command stops. It stops transmission after the current frame Þnishes or immediately if no  
frame is being sent. A transparent frame is not complete until a BD with TxBD[L] set has its buffer  
completely sent. SCCE[GRA] is set once transmission stops; transmit parameters and their BDs can  
then be modiÞed. The current TxBD pointer (TBPTR) advances to the next TxBD in the table.  
Transmission resumes once TxBD[R] is set and a RESTART TRANSMIT command is issued.  
TRANSMIT  
RESTART  
TRANSMIT  
Reenables transmission of characters on the transmit channel. The transparent controller expects it  
after a STOP TRANSMIT command is issued (at which point the channel is disabled in SCCM), after a  
GRACEFUL STOP TRANSMIT command is issued, or after a transmitter error. The transparent controller  
resumes transmission from the current TBPTR in the channel TxBD table.  
INIT TX Initializes all transmit parameters in the serial channel parameter RAM to reset state. Issue only when  
PARAMETERS the transmitter is disabled. INIT TX AND RX PARAMETERS resets receive and transmit parameters.  
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Chapter 23. SCCTransparent Mode  
23-7  
       
Part IV. Communications Processor Module  
Table 23-4 describes receive commands.  
Table 23-4. Receive Commands  
Command  
Description  
ENTER HUNT  
MODE  
After hardware or software is reset and the channel is enabled, the channel is in receive enable mode  
and uses the Þrst BD in the table. ENTER HUNT MODE forces the transparent receiver to the current  
frame and enter hunt mode where the transparent controller waits for the synchronization sequence.  
After receiving the command, the current buffer is closed. Further data reception uses the next BD.  
CLOSE RXBD  
INIT RX  
Forces the SCC to close the RxBD if it is being used and to use the next BD for any subsequently  
received data. If the SCC is not receiving data, no action is taken by this command.  
Initializes all receive parameters in this serial channel parameter RAM to reset state. Issue only when  
PARAMETERS the receiver is disabled. INIT TX AND RX PARAMETERS resets receive and transmit parameters.  
23.8 Handling Errors in the Transparent Controller  
The SCC reports message reception and transmission errors using the channel buffer  
descriptors, the error counters, and SCCE. Table 23-5 describes transmit errors.  
Table 23-5. Transmit Errors  
Error  
Description  
Transmitter  
Underrun  
When this occurs, the channel stops sending the buffer, closes it, sets TxBD[UN], and generates a  
TXE interrupt if it is enabled. Transmission resumes after a RESTART TRANSMIT command is  
received. Underrun occurs after a transmit frame for which TxBD[L] was not set. In this case, only  
SCCE[TXE] is set. Underrun cannot occur between transparent frames.  
CTS Lost During When this occurs, the channel stops sending the buffer, closes it, sets TxBD[CT], and generates  
Message  
Transmission  
the TXE interrupt if it is enabled. The channel resumes sending after RESTART TRANSMIT is received.  
Table 23-6 describes receive errors.  
Table 23-6. Receive Errors  
Error  
Overrun  
Description  
The SCC maintains a receive FIFO.The CPM starts programming the SDMA channel if the buffer is  
in external memory and updating the CRC when 8 or 32 bits are received in the FIFO as determined  
by GSMR_H[RFW]. If a FIFO overrun occurs, the SCC writes the received byte over the previously  
received byte.The previous character and its status bits are lost. Afterwards, the channel closes the  
buffer, sets OV in the BD, and generates the RXB interrupt if it is enabled. The receiver immediately  
enters hunt mode.  
CD Lost During When this occurs, the channel stops receiving messages, closes the buffer, sets RxBD[CD], and  
Message  
Reception  
generates the RXB interrupt if it is enabled. This error has highest priority. The rest of the message  
is lost, and no other errors are checked in the message. The receiver immediately enters hunt  
mode.  
23-8  
MPC8260 PowerQUICC II UserÕs Manual  
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Part IV. Communications Processor Module  
23.9 Transparent Mode and the PSMR  
The protocol-speciÞc mode register (PSMR) is not used by the transparent controller  
because all transparent mode selections are made in the GSMR. If only half of an SCC  
(transmitter or receiver) is running the transparent protocol, the other half (receiver or  
transmitter) can support another protocol. In such a case, use the PSMR for the non-  
transparent protocol.  
23.10 SCC Transparent Receive Buffer Descriptor  
(RxBD)  
The CPM reports information about the received data for each buffer using an RxBD,  
closes the current buffer, generates a maskable interrupt, and starts receiving data into the  
next buffer after one of the following occurs:  
¥
¥
¥
¥
An error is detected.  
A full receive buffer is detected.  
An ENTER HUNT MODE command is Issued.  
A CLOSE RXBD command is issued.  
0
1
2
3
4
L
5
F
6
7
8
9
10  
11  
12  
Ñ
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
E
Ñ
W
I
CM  
Ñ
DE  
Ñ
NO  
CR  
OV  
CD  
Data Length  
Rx Buffer Pointer  
Figure 23-2. SCC Transparent Receive Buffer Descriptor (RxBD)  
Table 23-7 describes RxBD status and control Þelds.  
Table 23-7. SCC Transparent RxBD Status and Control Field  
Descriptions  
Bits Name  
Description  
0
E
Empty.  
0 The buffer is full or stopped receiving data because an error occurred. The core can read or write to  
any Þelds of this RxBD. The CPM does not use this BD when RxBD[E] is zero.  
1 The buffer is not full. This RxBD and buffer are owned by the CPM. Once E is set, the core should  
not write any Þelds of this RxBD.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (Þnal BD in table).  
0 Not the last BD in the table.  
1 Last BD in the table. After this buffer is used, the CPM receives data into the Þrst BD that RBASE  
points to. The number of BDs in this table is determined only by RxBD[W] and overall space  
constraints of the dual-port RAM.  
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Chapter 23. SCCTransparent Mode  
23-9  
             
Part IV. Communications Processor Module  
Table 23-7. SCC Transparent RxBD Status and Control Field  
Descriptions (Continued)  
Bits Name  
Description  
3
I
Interrupt.  
0 No interrupt is generated after this buffer is used.  
1 When this buffer is closed by the transparent controller, the SCCE[RXB] is set. SCCE[RXB] can  
cause an interrupt if it is enabled.  
4
L
Last in frame. Set by the transparent controller when this buffer is the last in a frame, which occurs  
when CD is negated (if GSMR_H[CDP] = 0) or an error is received. If an error is received, one or more  
of RxBD[OV, CD, DE] are set. Note that the SCC transparent controller writes the number of buffer (not  
frame) octets to the last BDÕs data length Þeld.  
0 Not the last buffer in a frame.  
1 Last buffer in a frame.  
5
6
F
First in frame. The transparent controller sets F when this buffer is the Þrst in the frame:  
0 Not the Þrst buffer in a frame.  
1 First buffer in a frame.  
CM  
Continuous mode.  
0 Normal operation.  
1 The CPM does not clear RxBD[E] after this BD is closed, letting the buffer be overwritten when the  
CPM next accesses this BD. However, RxBD[E] is cleared if an error occurs during reception,  
regardless of how CM is set.  
7
8
Ñ
Reserved, should be cleared.  
DE  
DPLL error. Set by the transparent controller when a DPLL error occurs as this buffer is received. In  
decoding modes, where a transition is promised every bit, DE is set when a missing transition occurs.  
If a DPLL error occurs, no other error checking is performed.  
9Ð10  
11  
Ñ
Reserved, should be cleared.  
NO  
Ñ
Rx non-octet. Set when a frame containing a number of bits not exactly divisible by eight is received.  
Reserved, should be cleared.  
12  
13  
CR  
CRC error indication bits. Indicates that this frame contains a CRC error. The received CRC bytes are  
always written to the receive buffer. CRC checking cannot be disabled, but it can be ignored.  
14  
15  
OV  
CD  
Overrun. Indicates that a receiver overrun occurred during buffer reception.  
Carrier detect lost. Indicates when CD is negated during buffer reception.  
Data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer  
Descriptors (BDs).Ó The Rx buffer pointer must be divisible by four, unless  
GSMR_H[RFW] is set to 8 bits wide, in which case the pointer can be even or odd. The  
buffer can reside in internal or external memory.  
23.11 SCC Transparent Transmit Buffer Descriptor  
(TxBD)  
Data is sent to the CPM for transmission on an SCC channel by arranging it in buffers  
referenced by the TxBD table. The CPM uses BDs to conÞrm transmission or indicate error  
conditions so the processor knows buffers have been serviced. Prepare status and control  
bits before transmission; they are set by the CPM after the buffer is sent.  
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Part IV. Communications Processor Module  
0
1
2
3
4
5
6
7
8
9
10  
Ñ
11  
12  
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
R
Ñ
W
I
L
TC CM  
UN  
CT  
Data Length  
Tx Buffer Pointer  
Figure 23-3. SCC Transparent Transmit Buffer Descriptor (TxBD)  
Table 23-8 describes SCC Transparent TxBD status and control Þelds.  
Table 23-8. SCC Transparent TxBD Status and Control Field Descriptions  
Bit Name  
Description  
0
R
Ready.  
0 The buffer is not ready for transmission.The BD and buffer can be updated.The CPM clears R after  
the buffer is sent or after an error is encountered.  
1 The user-prepared buffer is not sent yet or is being sent. This BD cannot be updated while R = 1.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (Þnal BD in table).  
0 Not the last BD in the table.  
1 Last BD in the table. After this buffer is used, the CPM receives incoming data into the Þrst BD that  
TBASE points to. The number of TxBDs in this table is determined only by TxBD[W] and overall  
space constraints of the dual-port RAM.  
3
4
I
Interrupt. Note that clearing this bit does not disable all SCCE[TXE] events.  
0 No interrupt is generated after this buffer is serviced.  
1 When the CPM services this buffer, SCCE[TXB] or SCCE[TXE] is set. These bits can cause  
interrupts if they are enabled.  
L
Last in message.  
0 The last byte in the buffer is not the last byte in the transmitted transparent frame. Data from the  
next transmit buffer is sent immediately after the last byte of this buffer.  
1 The last byte in the buffer is the last byte in the transmitted transparent frame. After this buffer is  
sent, the transmitter requires synchronization before the next buffer is sent.  
5
6
TC  
Transmit CRC.  
0 No CRC sequence is sent after this buffer.  
1 A frame check sequence deÞned by GSMR_H[TCRC] is sent after the last byte of this buffer.  
CM  
Continuous mode.  
0 Normal operation.  
1 The CPM does not clear TxBD[R] after this BD is closed, so the buffer is automatically resent when  
the CPM accesses this BD next. However, TxBD[R] is cleared if an error occurs during  
transmission, regardless of how CM is set.  
7Ð13  
14  
Ñ
Reserved, should be cleared.  
UN  
CT  
Underrun. Set when the SCC encounters a transmitter underrun condition while sending the buffer.  
CTS lost. Indicates the CTS was lost during frame transmission.  
15  
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Chapter 23. SCCTransparent Mode  
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Part IV. Communications Processor Module  
Data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer  
Descriptors (BDs).Ó Although it is never modiÞed by the CP, data length should be greater  
than zero. The buffer pointer can be even or odd and can reside in internal or external  
memory.  
23.12 SCC Transparent Event Register (SCCE)/Mask  
Register (SCCM)  
When the SCC is in transparent mode, the SCC event register (SCCE) functions as the  
transparent event register to report events recognized by the transparent channel and to  
generate interrupts. When an event is recognized, the transparent controller sets the  
corresponding SCCE bit. Interrupts are enabled by setting, and masked by clearing, the  
equivalent bits in the transparent mask register (SCCM).  
Event bits are reset by writing ones; writing zeros has no effect. All unmasked bits must be  
reset before the CP clears the internal interrupt request to the SIU interrupt controller.  
Figure 23-4 shows the event and mask registers.  
Bit  
Field  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
Ñ
13  
14  
15  
Ñ
GLR GLT DCC  
Ñ
GRA  
Ñ
TXE  
BSY TXB RXB  
Reset  
R/W  
0000_0000_0000_0000  
R/W  
Address  
0x11A10 (SCCE1); 0x11A30 (SCCE2); 0x11A50 (SCCE3); 0x11A70 (SCCE4)  
0x11A14 (SCCM1); 0x11A34 (SCCM2); 0x11A54 (SCCM3); 0x11A74 (SCCM4)  
Figure 23-4. SCC Transparent Event Register (SCCE)/Mask Register (SCCM)  
Table 23-9 describes SCCE/SCCM Þelds.  
Table 23-9. SCCE/SCCM Field Descriptions  
Bit Name  
Description  
0Ð2  
Ñ
Reserved, should be cleared.  
3
4
5
GLR  
GLT  
DCC  
Glitch on Rx. Set when the SCC Þnds a glitch on the receive clock.  
Glitch on Tx. Set when the SCC Þnds a glitch on the transmit clock.  
DPLL CS changed. Set when the DPLL-generated carrier sense status changes (valid only when the  
DPLL is used). Real-time status can be read in SCCS.This is not the CD status mentioned elsewhere.  
6Ð7  
8
Ñ
Reserved, should be cleared.  
GRA  
Graceful stop complete. Set when a graceful stop initiated by completes as soon as the transmitter  
Þnishes any frame in progress when the GRACEFUL STOP TRANSMIT command was issued. Immediately  
if no frame was in progress when the command was issued.  
9Ð10  
11  
Ñ
Reserved, should be cleared.  
TXE  
Ñ
Tx error. Set when an error occurs on the transmitter channel.  
Reserved, should be cleared.  
12  
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MPC8260 PowerQUICC II UserÕs Manual  
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Part IV. Communications Processor Module  
Table 23-9. SCCE/SCCM Field Descriptions (Continued)  
Bit Name  
Description  
13  
BSY  
TXB  
RXB  
Busy condition. Set when a byte or word is received and discarded due to a lack of buffers. The  
receiver resumes reception after it gets an ENTER HUNT MODE command.  
14  
15  
Tx buffer. Set no sooner than when the last bit of the last byte of the buffer begins transmission,  
assuming L is set in the TxBD. If it is not, TXB is set when the last byte is written to the transmit FIFO.  
Rx buffer. Set when a complete buffer was received on the SCC channel, no sooner than two serial  
clocks after the last bit of the last byte in which the buffer is received on RXD.  
23.13 SCC Status Register in Transparent Mode  
(SCCS)  
The SCC status register (SCCS) allows monitoring of real-time status conditions on the  
RXD line. The real-time status of CTS and CD are part of the parallel I/O.  
Bit  
Field  
0
1
2
3
4
5
6
7
Ñ
CS  
Ñ
Reset  
R/W  
0000_0000  
R
Address  
0x11A17 (SCCS1); 0x11A37 (SCCS2); 0x11A57 (SCCS3); 0x11A77 (SCCS4)  
Figure 23-5. SCC Status Register in Transparent Mode (SCCS)  
Table 23-10 describes SCCS Þelds.  
Table 23-10. SCCS Field Descriptions  
Bit Name  
Description  
0Ð5  
Ñ
Reserved, should be cleared.  
6
7
CS  
Carrier sense (DPLL). Shows the real-time carrier sense of the line as determined by the DPLL.  
0 The DPLL does not sense a carrier.  
1 The DPLL senses a carrier.  
Ñ
Reserved, should be cleared.  
23.14 SCC2 Transparent Programming Example  
The following initialization sequence enables the transmitter and receiver, which operate  
independently of each other. They implement the connection shown on MPC8260(B) in  
Figure 23-1.  
The transmit and receive clocks are externally provided to MPC8260(B) using CLK3.  
SCC2 is used. The transparent controller is conÞgured with the RTS2 and CD2 pins active  
and CTS2 is conÞgured to be grounded internally. A 16-bit CRC-CCITT is sent with each  
transparent frame. The FIFOs are conÞgured for fast operation.  
MOTOROLA  
Chapter 23. SCCTransparent Mode  
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Part IV. Communications Processor Module  
1. ConÞgure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and  
PDIRD[27] and clear PDIRD[28] and PSORD[27,28].  
2. ConÞgure ports C and D pins to enable RTS2, CTS2 and CD2. Set PPARD[26],  
PPARC[12,13] and PDIRD[26] and clear PDIRC[12,13], PSORC[12,13] and  
PSORD[26].  
3. ConÞgure port C pin 29 to enable the CLK3 pin. Set PPARC[29] and clear  
PDIRC[29] and PSORC[29].  
4. Connect CLK3 to SCC2 using the CPM mux. Program CMXSCR[R2CS] and  
CMXSCR[T2CS] to 0b110.  
5. Connect the SCC2 to the NMSI and clear CMXSCR[SC2].  
6. Write RBASE with 0x0000 and TBASE with 0x0008 in the SCC2 parameter RAM  
to point to one RxBD at the beginning of dual-port RAM followed by one TxBD.  
7. Write 0x04A1_0000 to the CPCR to execute INIT RX AND TX PARAMETERS for  
SCC2.  
8. Write 0x0041 to the CPCR to execute INIT RX AND TX PARAMETERS for SCC2.  
9. Write RFCR and TFCR with 0x10 for normal operation.  
10.Write MRBLR with the maximum number of bytes per receive buffer and assume  
16-bytes, so MRBLR = 0x0010.  
11.Write CRC_P with 0x0000_FFFF to comply with the 16-bit CRC-CCITT.  
12.Write CRC_C with 0x0000_F0B8 to comply with the 16-bit CRC-CCITT.  
13.Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory.  
Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length]  
(optional), and 0x0000_1000 to RxBD[Buffer Pointer].  
14.Initialize the TxBD. Assume the Tx buffer is at 0x0000_2000 in main memory and  
contains Þve 8-bit characters. Write 0xBC00 to TxBD[Status and Control], 0x0005  
to TxBD[Data Length], and 0x0000_2000 to TxBD[Buffer Pointer].  
15.Write 0xFFFF to SCCE to clear any previous events.  
16.Write 0x0013 to SCCM to enable the TXE, TXB, and RXB interrupts.  
17.Write 0x0040_0000 to the SIU interrupt mask register low (SIMR_L) so SMC1 can  
generate a system interrupt. Initialize SIU interrupt pending register low (SIPNR_L)  
by writing 0xFFFF_FFFF to it.  
18.Write 0x0000_1980 to GSMR_H2 to conÞgure the transparent channel.  
19.Write 0x0000_0000 to GSMR_L2 to conÞgure CTS and CD to automatically  
control transmission and reception (DIAG bits). Normal operation of the transmit  
clock is used. Note that the transmitter (ENT) and receiver (ENR) are not enabled  
yet.  
20.Write 0x0000_0030 to GSMR_L2 to enable the SCC2 transmitter and receiver. This  
additional write ensures that the ENT and ENR bits are enabled last.  
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Part IV. Communications Processor Module  
Note that after 5 bytes are sent, the Tx buffer is closed and after 16 bytes are received the  
Rx buffer is closed. Any data received after 16 bytes causes a busy (out-of-buffers)  
condition since only one RxBD is prepared.  
MOTOROLA  
Chapter 23. SCCTransparent Mode  
23-15  
Part IV. Communications Processor Module  
23-16  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Chapter 24  
SCC Ethernet Mode  
240  
2T40 he Ethernet IEEE 802.3 protocol is a widely used LAN protocol based on the carrier sense  
multiple access/collision detect (CSMA/CD) approach. Because Ethernet and IEEE 802.3  
protocols are similar and can coexist on the same LAN, both are referred to as Ethernet in  
this manual, unless otherwise noted. Figure 24-1 shows Ethernet and IEEE 802.3 frame  
structure.  
Frame Length is 64–1518 Bytes  
Start Frame  
Delimiter  
Destination  
Address  
Source  
Address  
Type/  
Length  
Frame Check  
Sequence  
Preamble  
7 Bytes  
Data  
1 Byte  
6 Bytes  
6 Bytes  
2 Bytes  
46–1500 Bytes  
4 Bytes  
NOTE: The lsb of each octet is transmitted first.  
Figure 24-1. Ethernet Frame Structure  
The frame begins with a 7-byte preamble of alternating ones and zeros. Because the frame  
is Manchester encoded, the preamble gives receiving stations a known pattern on which to  
lock. The start frame delimiter follows the preamble, signifying the beginning of the frame.  
The 48-bit destination address is next, followed by the 48-bit source address. Original  
versions of the IEEE 802.3 speciÞcation allowed 16-bit addressing, but this addressing has  
never been widely used and is not supported.  
The next Þeld is the Ethernet type Þeld/IEEE 802.3 length Þeld. The type Þeld signiÞes the  
protocol used in the rest of the frame and the length Þeld speciÞes the length of the data  
portion of the frame. For Ethernet and IEEE 802.3 frames to coexist on the same LAN, the  
length Þeld of the frame must always be different from any type Þelds used in Ethernet. This  
limits the length of the data portion of the frame to 1,500 bytes and total frame length to  
1,518 bytes. The last 4 bytes of the frame are the frame check sequence (FCS), a standard  
32-bit CCITT-CRC polynomial used in many protocols.  
When a station needs to transmit, it checks for LAN activity. When the LAN is silent for a  
speciÞed period, the station starts sending. At that time, the station continually checks for  
collisions on the LAN; if one is found, the station forces a jam pattern (all ones) on its frame  
and stops sending. Most collisions occur close to the beginning of a frame. The station waits  
MOTOROLA  
Chapter 24. SCC Ethernet Mode  
24-1  
       
Part IV. Communications Processor Module  
a random period of time, called a backoff, before trying to retransmit. Once the backoff time  
expires, the station waits for silence on the LAN before retransmitting, which is called a  
retry. If the frame cannot be sent within 15 retries, an error occurs  
10-Mbps Ethernet transmits at 0.8 µs per byte. The preamble plus start frame delimiter is  
sent in 6.4 µs. The minimum 10-Mbps Ethernet interframe gap is 9.6 µs and the slot time  
is 52 µs.  
24.1 Ethernet on the MPC8260  
Setting GSMR[MODE] to 0b1100 selects Ethernet. The SCC performs the full set of IEEE  
802.3/Ethernet CSMA/CD media access control and channel interface functions.  
60x Bus  
Slot Time  
and Defer  
Counter  
Control  
Registers  
RCLK  
TCLK  
Clock  
Generator  
Peripheral Bus  
Internal Clocks  
REJECT  
RSTRT  
RTS = TENA  
Rx  
Data  
FIFO  
Tx  
Data  
FIFO  
Receiver  
Control  
Unit  
Transmitter  
Control  
Unit  
CD = RENA  
CTS = CLSN  
CD = RENA  
CTS = CLSN  
TXD  
RXD  
Shifter  
Shifter  
Figure 24-2. Ethernet Block Diagram  
The MPC8260 Ethernet controller requires an external serial interface adaptor (SIA) and  
transceiver function to complete the interface to the media.  
Although the MPC8260 contains DPLLs that allow Manchester encoding and decoding,  
these DPLLs were not designed for Ethernet rates. Therefore, the MPC8260 Ethernet  
controller bypasses the on-chip DPLLs and uses the external system interface adaptor on  
the EEST instead. The on-chip DPLL cannot be used for low-speed (1-Mbps) Ethernet  
either because it cannot properly detect start-of-frame or end-of-frame.  
Note that the CPM of the MPC8260 requires a minimum system clock frequency of 24  
MHz to support Ethernet.  
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Part IV. Communications Processor Module  
24.2 Features  
The following list summarizes the main features of the SCC in Ethernet mode:  
¥
¥
Performs MAC layer functions of Ethernet and IEEE 802.3  
Performs framing functions  
Ñ Preamble generation and stripping  
Ñ Destination address checking  
Ñ CRC generation and checking  
Ñ Automatically pads short frames on transmit  
Ñ Framing error (dribbling bits) handling  
¥
Full collision support  
Ñ Enforces the collision (jamming)  
Ñ Truncated binary exponential backoff algorithm for random wait  
Ñ Two nonaggressive backoff modes  
Ñ Automatic frame retransmission (until the attempt limit is reached)  
Ñ Automatic discard of incoming collided frames  
Ñ Delay transmission of new frames for speciÞed interframe gap  
¥
¥
¥
¥
¥
¥
Maximum 10 Mbps bit rate  
Optional full-duplex support  
Back-to-back frame reception  
Detection of receive frames that are too long  
Multibuffer data structure  
Supports 48-bit addresses in three modes  
Ñ PhysicalÐOne 48-bit address recognized or 64-bin hash table for physical  
addresses  
Ñ LogicalÐ64-bin group address hash table plus broadcast address checking  
Ñ PromiscuousÐReceives all addresses, but discards frame if REJECT is asserted  
External content-addressable memory (CAM) support on serial bus interfaces  
Up to eight parallel I/O pins can be sampled and appended to any frame  
Optional heartbeat indication  
¥
¥
¥
¥
Transmitter network management and diagnostics  
Ñ Lost carrier sense  
Ñ Underrun  
Ñ Number of collisions exceeded the maximum allowed  
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Chapter 24. SCC Ethernet Mode  
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Part IV. Communications Processor Module  
Ñ Number of retries per frame  
Ñ Deferred frame indication  
Ñ Late collision  
¥
Receiver network management and diagnostics  
Ñ CRC error indication  
Ñ Nonoctet alignment error  
Ñ Frame too short  
Ñ Frame too long  
Ñ Overrun  
Ñ Busy (out of buffers)  
Error counters  
¥
¥
Ñ Discarded frames (out of buffers or overrun occurred)  
Ñ CRC errors  
Ñ Alignment errors  
Internal and external loopback mode  
24.3 Connecting the MPC8260 to Ethernet  
The basic interface to the external SIA chip consists of the following Ethernet signals:  
¥
¥
Receive clock (RCLK)Ña CLKx signal routed through the bank of clocks on the  
MPC8260.  
Transmit clock (TCLK)Ña CLKx signal routed through the bank of clocks on the  
MPC8260. Note that RCLK and TCLK should not be connected to the same CLKx  
since the SIA provides separate transmit and receive clock signals.  
¥
¥
Transmit data (TXD)Ñthe MPC8260 TXD signal.  
Receive data (RXD)Ñthe MPC8260 RXD signal.  
The following signals take on different functionality when the SCC is in Ethernet mode:  
¥
Transmit enable (TENA)ÑRTS becomes TENA. The polarity of TENA is active  
high, whereas the polarity of RTS is active low.  
¥
¥
Receive enable (RENA)ÑCD becomes RENA.  
Collision (CLSN)ÑCTS becomes CLSN. The carrier sense signal is referenced in  
Ethernet descriptions because it indicates when the LAN is in use. Carrier sense is  
deÞned as the logical OR of RENA and CLSN.  
Figure 24-3 shows the basic components and signals required to make an Ethernet  
connection between the MPC8260 and EEST.  
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Part IV. Communications Processor Module  
MPC8260  
SCC  
EEST  
MC68160  
TXD  
Tx  
RJ-45  
TENA (RTS)  
TCLK (CLKx)  
RXD  
TENA  
TCLK  
Rx  
Twisted  
Pair  
Passive  
RENA (CD)  
RCLK (CLKx)  
CLSN (CTS)  
RENA  
RCLK  
CLSN  
D-15  
Passive  
AUI  
Parallel I/O  
Loop  
Stored in Receive Buffer  
Stored in Transmit Buffer  
Start Frame  
Delimiter  
Destination  
Address  
Source  
Address  
Type/  
Length  
Frame Check  
(Pads)  
Sequence  
Preamble  
7 Bytes  
Data  
46–1500 Bytes  
1 Byte  
6 Bytes  
6 Bytes  
2 Bytes  
4 Bytes  
NOTE: Short Tx frames are padded automatically by the MPC8260.  
Figure 24-3. Connecting the MPC8260 to Ethernet  
The EEST has similar names for its connection to the above seven MPC8260 signals. The  
EEST also provides a loopback input so the MPC8260 can perform external loopback  
testing, which can be controlled by any available MPC8260 parallel I/O signal. The passive  
components needed to connect to AUI or twisted-pair media are external to the EEST. The  
MC68160 documentation describes EEST connection circuits.  
The MPC8260 uses SDMA channels to store bytes received after the start frame delimiter  
in system memory. When sending, provide the destination address, source address, type/  
length Þeld, and the transmit data. To meet minimum frame requirements, the MPC8260  
pads frames with fewer than 46 bytes in the data Þeld and appends the FCS to the frame.  
24.4 SCC Ethernet Channel Frame Transmission  
The Ethernet transmitter works with almost no core intervention. When the core enables the  
transmitter, the SCC polls the Þrst TxBD in the table every 128 serial clocks. Setting  
TODR[TOD] lets the next frame be sent without waiting for the next poll.  
To begin transmission, the SCC in Ethernet mode (called the Ethernet controller) fetches  
data from the buffer, asserts TENA to the EEST, and starts sending the preamble sequence,  
the start frame delimiter, and frame information. If the line is busy, it waits for carrier sense  
to remain inactive for 6.0 µs, at which point it waits an additional 3.6 µs before it starts  
sending (9.6 µs after carrier sense originally became inactive).  
If a collision occurs during frame transmission, the Ethernet controller follows a speciÞed  
backoff procedure and tries to retransmit the frame until the retry limit threshold is reached.  
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Chapter 24. SCC Ethernet Mode  
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Part IV. Communications Processor Module  
The Ethernet controller stores the Þrst 5 to 8 bytes of the transmit frame in dual-port RAM  
so they need not be retrieved from system memory in case of a collision. This improves bus  
usage and latency when the backoff timer output requires an immediate retransmission. If  
a collision occurs during frame transmission, the controller returns to the Þrst buffer for a  
retransmission. The only restriction is that the Þrst buffer must contain at least 9 bytes.  
Note that if an Ethernet frame consists of multiple buffers, do not reuse the Þrst BD until  
the CPM clears the R bit of the last BD.  
When the end of the current BD is reached and TxBD[L] is set, the FCS bytes are appended  
(if the TC bit is set in the TxBD), and TENA is negated. This notiÞes the EEST of the need  
to generate the illegal Manchester encoding that marks the end of an Ethernet frame. After  
CRC transmission, the Ethernet controller writes the frame status bits into the BD and  
clears the R bit. When the end of the current BD is reached and the L bit is not set, only the  
R bit is cleared.  
In either mode, whether an interrupt is issued depends on how the I bit is set in the TxBD.  
The Ethernet controller proceeds to the next TxBD. Transmission can be interrupted after  
each frame, after each buffer, or after a speciÞc buffer is sent. The Ethernet controller can  
pad characters to short frames. If TxBD[PAD] is set, the frame is padded up to the value of  
the minimum frame length register (MINFLR).  
To send expedited data before previously linked buffers or for error situations, the  
GRACEFUL STOP TRANSMIT command can be used to rearrange transmit queue before the  
CPM sends all the frames; the Ethernet controller stops immediately if no transmission is  
in progress or it will keep sending until the current frame either Þnishes or terminates with  
a collision. When the Ethernet controller receives a RESTART TRANSMIT command, it  
resumes transmission. The Ethernet controller sends bytes least-signiÞcant bit Þrst.  
24.5 SCC Ethernet Channel Frame Reception  
The Ethernet receiver handles address recognition and performs CRC, short frame,  
maximum DMA transfer, and maximum frame length checking with almost no core  
intervention. When the core enables the Ethernet receiver, it enters hunt mode as soon as  
RENA is asserted while CLSN is negated. In hunt mode, as data is shifted into the receive  
shift register one bit at a time, the register contents are compared to the contents of the  
SYN1 Þeld in the data synchronization register (DSR). This compare function becomes  
valid a certain number of clocks after the start of the frame (depending on PSMR[NIB]). If  
the two are not equal, the next bit is shifted in and the comparison is repeated. If a double-  
zero or double-one fault is detected between bits 14 to 21 from the Þrst received preamble  
bit, the frame is rejected. If a double-zero fault is detected after 21 bits from the Þrst  
received preamble bit and before detection of the start frame delimiter (SFD), the frame is  
also rejected. When the incoming pattern is not rejected and matches the DSR, the SFD has  
been detected; hunt mode is terminated and character assembly begins.  
When the receiver detects the Þrst bytes of the frame, the Ethernet controller performs  
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Part IV. Communications Processor Module  
address recognition on the frame. The receiver can receive physical (individual), group  
(multicast), and broadcast addresses. Ethernet receive frame data is not written to memory  
until the internal address recognition process completes, which improves bus usage with  
frames not addressed to this station.  
If a match is found, the Ethernet controller fetches the next RxBD and, if it is empty, starts  
transferring the incoming frame to the RxBD associated data buffer. If a collision is  
detected during the frame, the RxBDs associated with this frame are reused. Thus, there  
will be no collision frames presented to you except late collisions, which indicate serious  
LAN problems. When the data buffer has been Þlled, the Ethernet controller clears the E  
bit in the RxBD and generates an interrupt if the I bit is set. If the incoming frame exceeds  
the length of the data buffer, the Ethernet controller fetches the next RxBD in the table and,  
if it is empty, continues transferring the rest of the frame to this buffer. The RxBD length is  
determined by MRBLR in the SCC general-purpose parameter RAM, which should be at  
least 64 bytes.  
During reception, the Ethernet controller checks for a frame that is either too short or too  
long. When the frame ends, the receive CRC Þeld is checked and written to the buffer. The  
data length written to the last BD in the Ethernet frame is the length of the entire frame and  
it enables the software to correctly recognize the frame-too-long condition.  
The Ethernet controller then sets the L bit in the RxBD, writes the other frame status bits  
into the RxBD, and clears the E bit. Then it generates a maskable interrupt, which indicates  
that a frame has been received and is in memory. The Ethernet controller then waits for a  
new frame. It receives serial data least-signiÞcant bit Þrst.  
24.6 The Content-Addressable Memory (CAM)  
Interface  
The Ethernet controller has one option for connecting to an external CAMÑa serial  
interface. The reject signal (REJECT) is used to signify that the current frame should be  
discarded. The MPC8260Õs internal address recognition logic can be used in combination  
with an external CAM. See Section 24.10, ÒSCC Ethernet Address Recognition.Ó  
The MPC8260 outputs a receive start (RSTRT) signal when the start frame delimiter is  
recognized. This signal is asserted for one bit time on the second destination address bit.  
The CAM control logic uses RSTRT (in combination with the RXD and RCLK signals) to  
store the destination or source address and generate writes to the CAM for address  
recognition. In addition, the RENA signal supplied from the SIA can be used to abort the  
comparison if a collision occurs on the receive frame.  
After the comparison, the CAM control logic asserts the receive reject signal (REJECT), if  
the current receive frame is rejected. The MPC8260Õs Ethernet controller then immediately  
stops writing data to system memory and reuses the buffer(s) for the next frame. If the CAM  
accepts the frame, the CAM control logic does nothing (REJECT is not asserted). However,  
if REJECT is asserted, it must be done prior to the end of the receive frame.  
MOTOROLA  
Chapter 24. SCC Ethernet Mode  
24-7  
 
Part IV. Communications Processor Module  
24.7 SCC Ethernet Parameter RAM  
For Ethernet mode, the protocol-speciÞc area of the SCC parameter RAM is mapped as in  
Table 24-1.  
Table 24-1. SCC Ethernet Parameter RAM Memory Map  
1
Offset  
Name  
Width  
Description  
0x30 C_PRES  
0x34 C_MASK  
0x38 CRCEC  
0x3C ALEC  
Word Preset CRC. For the 32-bit CRC-CCITT, initialize to 0xFFFFFFFF.  
Word Constant mask for CRC. For the 32-bit CRC-CCITT, initialized to 0xDEBB20E3.  
Word CRC error, alignment error, and discard frame counters. The CPM maintains these  
32  
32-bit (modulo 2 ) counters that can be initialized while the channel is disabled.  
CRCEC is incremented for each received frame with a CRC error, not including  
frames not addressed to the controller, frames received in the out-of-buffers  
condition, frames with overrun errors, or frames with alignment errors. ALEC is  
incremented for frames received with dribbling bits, but does not include frames  
not addressed to the controller, frames received in the out-of-buffers condition, or  
frames with overrun errors. DISFC is incremented for frames discarded because of  
the out-of-buffers condition or an overrun error. The CRC does not have to be  
correct for DISFC to be incremented.  
0x40 DISFC  
0x44 PADS  
Hword Short frame PAD character. Write the pad character pattern to be sent when short  
frame padding is implemented into PADS. The pattern may be of any value, but  
both the high and low bytes should be the same.  
0x46 RET_LIM  
Hword Retry limit. Number of retries (typically 15 decimal) that can be made to send a  
frame. An interrupt can be generated if the limit is reached.  
0x48 RET_CNT  
Hword Retry limit counter. Temporary down-counter for counting retries.  
0x4A MFLR  
Hword Maximum frame length register (Typically 1518 decimal). The Ethernet controller  
checks the length of an incoming Ethernet frame against this limit. If it is exceeded,  
the rest of the frame is discarded and LG is set in the last BD of that frame. The  
controller reports frame status and length in the last BD. MFLR is defined as all in-  
frame bytes between the start frame delimiter and the end of the frame.  
0x4C MINFLR  
Hword Minimum frame length register. The Ethernet controller checks the incoming  
frameÕs length against MINFLR (typically 64 decimal). If the received frame is  
smaller than MINFLR, it is discarded unless PSMR[RSH] is set, in which case, SH  
is set in the last BD for the frame. For transmitting a frame that is too short, the  
Ethernet controller pads the frame to make it MINFLR bytes long, depending on  
how PAD is set in the TxBD and on the PAD value in the parameter RAM.  
0x4E MAXD1  
Hword Max DMAn length register. Gives the option to stop system bus writes after a  
frame exceeds a certain size. However, this value is valid only if an address match  
Hword  
is found. The Ethernet controller checks the length of an incoming Ethernet frame  
0x50 MAXD2  
against this user-defined value (usually 1520 decimal). If this limit is exceeded, the  
rest of the incoming frame is discarded. The Ethernet controller waits until the end  
of the frame or until MFLR bytes are received and reports the frame status and the  
frame length in the last RxBD.  
MAXD1 is used when an address matches an individual or group address. MAXD2  
is used in promiscuous mode when no address match is detected. In a monitor  
station, MAXD2 can be much less than MAXD1 to receive entire frames  
addressed to this station, but only the headers of the other frames are received.  
0x52 MAXD  
Hword Rx max DMA.  
0x54 DMA_CNT  
Hword Rx DMA counter. A temporary down-counter used to track frame length.  
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Part IV. Communications Processor Module  
Table 24-1. SCC Ethernet Parameter RAM Memory Map (Continued)  
1
Offset  
Name  
Width  
Description  
0x54 MAX_B  
0x58 GADDR1  
0x5A GADDR2  
0x5C GADDR3  
0x5E GADDR4  
Hword Maximum BD byte count.  
Hword Group address Þlter 1Ð4. Used in the hash table function of the group addressing  
mode. Write zeros to these values after reset and before the Ethernet channel is  
enabled to disable all group hash address recognition functions. The SET GROUP  
ADDRESS command is used to enable the hash table.  
0x60 TBUF0_DATA0 Word Save area 0Ñcurrent frame.  
0x64 TBUF0_DATA1 Word Save area 1Ñcurrent frame.  
0x68 TBUF0_RBA0 Word  
0x6C TBUF0_CRC Word  
0x70 TBUF0_BCNT Hword  
0x72 PADDR1_H  
0x74 PADDR1_M  
0x76 PADDR1_L  
0x78 P_PER  
Hword The 48-bit individual address of this station into this location. PADDR1_L is the  
lowest order hword and PADDR1_H is the highest order hword.  
Hword Persistence. Lets the Ethernet controller be less aggressive after a collision.  
Normally, 0x0000. It can be a value between 1 and 9 (1 is most aggressive). The  
value is added to the retry count in the backoff algorithm to reduce the chance of  
transmission on the next time slot.  
Note: Using P_PER is fully allowed in the Ethernet/802.3 specifications. A less  
aggressive backoff algorithm used by multiple stations on a congested Ethernet  
LAN increases overall throughput by reducing the chance of collision. PSMR[SBT]  
offers another way to reduce the aggressiveness of the Ethernet controller.  
0x7A RFBD_PTR  
0x7C TFBD_PTR  
0x7E TLBD_PTR  
Hword Rx Þrst BD pointer.  
Hword Tx Þrst BD pointer.  
Hword Tx last BD pointer.  
0x80 TBUF1_DATA0 Word Save area 0Ñnext frame.  
0x84 TBUF1_DATA1 Word Save area 1Ñnext frame.  
0x88 TBUF1_RBA0 Word  
0x8C TBUF1_CRC Word  
0x90 TBUF1_BCNT Hword  
0x92 TX_LEN  
0x94 IADDR1  
0x96 IADDR2  
0x98 IADDR3  
0x9A IADDR4  
0x9C BOFF_CNT  
Hword Tx frame length counter.  
Hword Individual address Þlter 1Ð4. Used in the hash table function of the individual  
addressing mode. Zeros can be written to these values after reset and before the  
Ethernet channel is enabled to disable all individual hash address recognition  
functions. The SET GROUP ADDRESS command is used to enable the hash table.  
Hword Backoff counter.  
MOTOROLA  
Chapter 24. SCC Ethernet Mode  
24-9  
Part IV. Communications Processor Module  
Table 24-1. SCC Ethernet Parameter RAM Memory Map (Continued)  
1
Offset  
Name  
Width  
Description  
0x9E TADDR_H  
0x A0 TADDR_M  
0x A2 TADDR_L  
Hword Allows addition and deletion of addresses from individual and group hash tables.  
After placing an address in TADDR, issue a SET GROUP ADDRESS command.  
TADDR_L (temp address low) is the least-signiÞcant half word and TADDR_H  
(temp address high) is the most-signiÞcant half word.  
1
From SCC base address. See Section 19.3.1, ÒSCC Base Addresses.Ó  
24.8 Programming the Ethernet Controller  
The core conÞgures the SCC to operate as an Ethernet controller by setting GSMR[MODE]  
to 0b1100. Receive and transmit errors are reported through RxBD and TxBD. Several  
GSMR Þelds must be programmed to special values for Ethernet. Set DSR[SYN1] to 0x55  
and DSR[SYN2] to 0xDE. The 6 bytes of preamble programmed in the GSMR, in  
combination with the DSR programming, causes 8 bytes of preamble on transmit  
(including the 1-byte start delimiter with the value 0xD5).  
24.9 SCC Ethernet Commands  
Transmit and receive commands are issued to the CP command register (CPCR).  
Table 24-2 describes transmit commands.  
Table 24-2. Transmit Commands  
Command  
Description  
STOP  
When used with the Ethernet controller, this command violates a speciÞc behavior of an Ethernet/IEEE  
802.3 station. It should not be used.  
TRANSMIT  
GRACEFUL  
STOP  
Used to ensure that transmission stops smoothly after the current frame Þnishes or has a collision.  
SCCE[GRA] is set once transmission stops, at which point Ethernet transmit parameters and their BDs  
can be updated. TBPTR points to the next TxBD. Transmission begins once the R bit of the next BD is  
set and a RESTART TRANSMIT command is issued.  
TRANSMIT  
Note that if GRACEFUL STOP TRANSMIT is issued and the current frame ends in a collision, TBPTR points  
to the start of the collided frame with the R bit still set in the BD. The frame looks as if it was never sent.  
RESTART  
TRANSMIT  
Enables transmission of characters on the transmit channel. The Ethernet controller expects it after a  
GRACEFUL STOP TRANSMIT command is issued or a transmitter error. The Ethernet controller resumes  
transmission from the current TBPTR in the channel TxBD table.  
INIT TX Initializes transmit parameters in this serial channel parameter RAM to reset state. Issue only when the  
PARAMETERS transmitter is disabled. INIT TX and RX PARAMETERS resets both transmit and receive parameters.  
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Part IV. Communications Processor Module  
Table 24-3 describes receive commands.  
Table 24-3. Receive Commands  
Command  
Description  
ENTER HUNT After hardware or software is reset and the channel is enabled in GSMR_L, the channel is in receive  
MODE  
enable mode and uses the Þrst BD in the table. The receiver then enters hunt mode, waiting for an  
incoming frame. The ENTER HUNT MODE command is generally used to force the Ethernet receiver to  
stop receiving the current frame and enter hunt mode, in which the Ethernet controller continually  
scans the input data stream for a transition of carrier sense from inactive to active and then a preamble  
sequence followed by the start frame delimiter. After receiving the command, the buffer is closed and  
the CRC calculation is reset. The next RxBD is used to receive more frames.  
CLOSE RXBD Should not be used with the Ethernet controller.  
INIT RX Initializes receive parameters in this serial channel parameter RAM to their reset state. Issue it only  
PARAMETERS when the receiver is disabled. INIT TX and RX PARAMETERS resets receive and transmit parameters.  
SET GROUP  
ADDRESS  
Used to set one of the 64 bits of the four individual/group address hash Þlter registers. The address to  
be added to the hash table should be written to TADDR_L, TADDR_M, and TADDR_H in the parameter  
RAM before executing this command. The CP uses an individual address if the I/G bit in the address  
stored in TADDR is 0; otherwise, it uses a group address. This command can be executed at any time,  
regardless of whether the Ethernet channel is enabled.  
To delete an address from the hash table, disable the Ethernet channel, clear the hash table registers,  
and execute this command for the remaining addresses. Do not simply clear the channelÕs associated  
hash table bit because the hash table may have multiple addresses mapped to the same hash table bit.  
Note that after a CPM reset via CPCR[RST], the Ethernet transmit enable (TENA) signal  
defaults to its RTS, active-low functionality. To prevent false TENA assertions to an  
external transceiver, conÞgure TENA as an input before issuing a CPM reset. See step 3 in  
Section 24.21, ÒSCC Ethernet Programming Example.Ó  
24.10 SCC Ethernet Address Recognition  
The Ethernet controller can Þlter received frames based on different addressing typesÑ  
physical (individual), group (multicast), broadcast (all-ones group address), and  
promiscuous. The difference between an individual address and a group address is  
determined by the I/G bit in the destination address Þeld. A ßowchart for address  
recognition on received frames is shown in Figure 24-4.  
In the physical type of address recognition, the Ethernet controller compares the destination  
address Þeld of the received frame with the user-programmed physical address in PADDR1.  
Address recognition can be performed on multiple individual addresses using the  
IADDR1Ð4 hash table.  
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Part IV. Communications Processor Module  
Check Address  
G
I
I/G Address  
?
Broadcast  
Address  
?
True  
False  
True  
Multiple IND  
?
Multiple Individual  
Addresses  
False  
Hash_Search  
Use Indicated  
Table  
Hash Search  
Use Group  
Table  
Broadcast  
Enabled  
?
True  
False  
Single  
Address  
True True  
Match  
?
Match  
?
False  
False  
Receive Frame  
Ignore REJECT  
Receive Frame  
Ignore REJECT  
False  
Match  
?
True  
Receive Frame  
Ignore REJECT  
False  
True  
PROMISC  
?
Start Receive  
Discard Frame if REJECT  
is Asserted  
Discard Frame  
Figure 24-4. Ethernet Address Recognition Flowchart  
In group address recognition, the controller determines whether the group address is a  
broadcast address. If broadcast addresses are enabled, the frame is accepted, but if the  
group address is not a broadcast address, address recognition can be performed on multiple  
group addresses using the GADDRn hash table. In promiscuous mode, the controller  
receives all incoming frames regardless of their address, unless REJECT is asserted.  
If an external CAM is used for address recognition, select promiscuous mode; the frame  
can be rejected by asserting REJECT while the frame is being received. The on-chip  
address recognition functions can be used in addition to the external CAM address  
recognition functions.  
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Part IV. Communications Processor Module  
If the external CAM stores addresses that should be rejected rather than accepted, the use  
of REJECT by the CAM should be logically inverted.  
24.11 Hash Table Algorithm  
Individual and group hash Þltering operate using certain processes. The Ethernet controller  
maps any 48-bit address into one of 64 bins, each represented by a bit stored in GADDRx  
or IADDRx. When a SET GROUP ADDRESS command is executed, the Ethernet controller  
maps the selected 48-bit address into one of the 64 bits by passing the 48-bit address  
through the on-chip 32-bit CRC generator and selecting 6 bits of the CRC-encoded result  
to generate a number between 1 and 64. Bits 31Ð30 of the CRC result select one of the  
GADDRs or IADDRs; bits 29Ð26 of the CRC result indicate the bit in that register.  
When the Ethernet controller receives a frame, the same process is used. If the CRC  
generator selects a bit that is set in the group/individual hash table, the frame is accepted.  
Otherwise, it is rejected. So, if eight group addresses are stored in the hash table and  
random group addresses are received, the hash table prevents roughly 56/64 (87.5%) of the  
group address frames from reaching memory. Frames that reach memory must be further  
Þltered by the processor to determine if they contain one of the eight preferred addresses.  
Better performance is achieved by using the group and individual hash tables  
simultaneously. For instance, if eight group and eight physical addresses are stored in their  
respective hash tables, 87.5% of all frames are prevented from reaching memory. The  
effectiveness of the hash table declines as the number of addresses increases. For instance,  
with 128 addresses stored in a 64-bin hash table, the vast majority of the hash table bits are  
set, thus preventing a small fraction of the frames from reaching memory.  
Hash tables cannot be used to reject frames that match a set of entered addresses because  
unintended addresses are mapped to the same bit in the hash table.  
24.12 Interpacket Gap Time  
The receiver receives back-to-back frames with a minimum interpacket spacing of 9.6 µs.  
In addition, after the backoff algorithm, the transmitter waits for carrier sense to be negated  
before resending the frame. Retransmission begins 9.6 µs after carrier sense is negated if it  
stays negated for at least 6.4 µs.  
24.13 Handling Collisions  
If a collision occurs as a frame is being sent, the Ethernet controller continues sending for  
at least 32 bit times, thus sending a JAM pattern of 32 ones. If a collision occurs during the  
preamble sequence, the JAM pattern is sent at the end of the sequence.  
If a collision occurs within 64 byte times, the retry process is initiated. The transmitter waits  
a random number of slot times (512 bit times or 52 µs). If a collision occurs after 64 byte  
times, no retransmission is performed and the buffer is closed with an LC error indication.  
MOTOROLA  
Chapter 24. SCC Ethernet Mode  
24-13  
         
Part IV. Communications Processor Module  
If a collision occurs while a frame is being received, reception stops. This error is reported  
only in the BD if the length of the frame exceeds MINFLR or if PSMR[RSH] = 1.  
24.14 Internal and External Loopback  
Both internal and external loopback are supported by the Ethernet controller. In loopback  
mode, both of the SCC FIFOs are used and the channel actually operates in a full-duplex  
fashion. Both internal and external loopback are conÞgured using combinations of  
PSMR[LPB] and GSMR[DIAG]. Because of the full-duplex nature of the loopback  
operation, the performance of other SCCs is degraded.  
Internal loopback disconnects the SCC from the serial interface. Receive data is connected  
to the transmit data and the receive clock is connected to the transmit clock. Both FIFOs  
are used. Data from the transmit FIFO is received immediately into the receive FIFO. There  
is no heartbeat check in this mode; conÞgure TENA as a general-purpose output.  
In external loopback operation, the Ethernet controller listens for data being received from  
the EEST at the same time that it is sending.  
24.15 Full-Duplex Ethernet Support  
To run full-duplex Ethernet, select loopback and full-duplex Ethernet modes in the SCCÕs  
protocol-speciÞc mode register, (PSMR[LPB, FDE] = 1). The loopback mode tells the  
Ethernet controller to accept received frames without signaling a collision. Setting  
PSMR[FDE] tells the controller that it can send while receiving without waiting for a clear  
line (carrier sense).  
24.16 Handling Errors in the Ethernet Controller  
The Ethernet controller reports frame reception and transmission error conditions using  
channel BDs, error counters, and SCCE. Table 24-4 describes transmission errors.  
Table 24-4. Transmission Errors  
Error  
Description  
Transmitter underrun If this error occurs, the channel sends 32 bits that ensures a CRC error, stops sending the  
buffer, closes it, sets the UN bit in the TxBD and SCCE[TXE]. The channel resumes  
transmission after it receives a RESTART TRANSMIT command.  
Carrier sense lost  
during frame  
transmission  
When this error occurs and no collision is found in the frame, the channel sets the CSL bit in  
the TxBD, sets SCCE[TXE], and continues sending the buffer normally. No retries are  
performed after this error occurs. Carrier sense is the logical OR of RENA and CLSN.  
Retransmission  
The channel stops sending the buffer, closes it, sets the RL bit in the TxBD and SCCE[TXE].  
attempts limit expired The channel resumes transmission after it receives a RESTART TRANSMIT command.  
Late collision  
When this error occurs, the channel stops sending the buffer, closes it, sets SCCE[TXE] and  
the LC bit in the TxBD. The channel resumes transmission after it receives the RESTART  
TRANSMIT command. This error is discussed further in the deÞnition of PSMR[LCW].  
24-14  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
           
Part IV. Communications Processor Module  
Table 24-4. Transmission Errors (Continued)  
Error  
Heartbeat  
Description  
Some transceivers have a heartbeat (signal-quality error) self-test.To signify a good self-test,  
the transceiver indicates a collision to the MPC8260 within 20 clocks after the Ethernet  
controller sends a frame.This heartbeat condition does not imply a collision error, but that the  
transceiver seems to be functioning properly. If SCCE[HBC] = 1 and the MPC8260 does not  
detect a heartbeat condition after sending a frame, a heartbeat error occurs; the channel  
closes the buffer, sets the HB bit in the TxBD, and generates the TXE interrupt if it is enabled.  
Table 24-4 describes reception errors.  
Table 24-5. Reception Errors  
Error  
Description  
Overrun  
The Ethernet controller maintains an internal FIFO for receiving data. When it overruns, the channel  
writes the received byte over the previously received byte. The previous byte and frame status are lost.  
The channel closes the buffer, sets RxBD[OV] and SCCE[RXF], and increments the discarded frame  
counter (DISFC). The receiver then enters hunt mode.  
Busy  
A frame was received and discarded because of a lack of buffers. The channel sets SCCE[BSY] and  
increments DISFC. The receiver then enters hunt mode.  
Non-Octet The Ethernet controller handles up to seven dribbling bits when the receive frame terminates nonoctet  
Error aligned. It checks the CRC of the frame on the last octet boundary. If there is a CRC error, a frame  
(Dribbling nonoctet aligned error is reported, SCCE[RXF] is set, and the alignment error counter is incremented. If  
Bits)  
there is no CRC error, no error is reported. The receiver then enters hunt mode.  
CRC  
When a CRC error occurs, the channel closes the buffer, sets SCCE[RXF] and CR in the RxBD, and  
increments the CRC error counter (CRCEC). After receiving a frame with a CRC error, the receiver enters  
hunt mode. CRC checking cannot be disabled, but CRC errors can be ignored if checking is not required.  
24.17 Ethernet Mode Register (PSMR)  
In Ethernet mode, the protocol-speciÞc mode register (PSMR), shown in Figure 24-5, is  
used as the Ethernet mode register.  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
Ñ
11  
12  
13  
14  
15  
Field HBC FC RSH IAM  
CRC  
PRO BRO SBT LPB  
0000_0000_0000_0000  
R/W  
LCW  
NIB  
FDE  
Reset  
R/W  
Addr  
0x11A08 (PSMR1); 0x11A28 (PSMR2); 0x11A48 (PSMR3); 0x11A68 (PSMR4)  
Figure 24-5. Ethernet Mode Register (PSMR)  
MOTOROLA  
Chapter 24. SCC Ethernet Mode  
24-15  
         
Part IV. Communications Processor Module  
Table 24-6 describes PSMR Þelds.  
Table 24-6. PSMR Field Descriptions  
Bits Name  
Description  
0
HBC Heartbeat checking.  
0 No heartbeat checking is performed. Do not wait for a collision after transmission.  
1 Wait 20 transmit clocks or 2 µs for a collision asserted by the transceiver after transmission.The HB  
bit in the TxBD is set if the heartbeat is not heard within 20 transmit clocks.  
1
FC  
Force collision.  
0 Normal operation.  
1 The channel forces a collision when each frame is sent.To test collision logic conÞgure the MPC8260  
in loopback operation. In the end, the retry limit for each transmit frame is exceeded.  
2
3
RSH Receive short frames.  
0 Discard short frames that are not as long as MINFLR.  
1 Receive short frames.  
IAM  
Individual address mode.  
0 Normal operation. A single 48-bit physical address in PADDR1 is checked when it is received.  
1 The individual hash table is used to check all individual addresses that are received.  
4Ð5  
6
CRC CRC selection. Only CRC = 10 is valid. Complies with Ethernet speciÞcations. 32-bit CCITT-CRC.  
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 +1.  
PRO Promiscuous.  
0 Check the destination address of incoming frames.  
1 Receive the frame regardless of its address unless REJECT is asserted as it is being received.  
7
8
BRO Broadcast address.  
0 Receive all frames containing the broadcast address.  
1 Reject all frames containing the broadcast address, unless PRO = 1.  
SBT  
LPB  
Ñ
Stop backoff timer.  
0 The backoff timer is functioning normally.  
1 The backoff timer for the random wait after a collision is stopped when carrier sense is active.  
Retransmission is less aggressive than the maximum allowed in IEEE 802.3. The persistence  
(P_PER) feature in the parameter RAM can be used in combination with or in place of SBT.  
9
Local protect bit  
0
1
Receiver is blocked when transmitter sends (default).  
Receiver is not blocked when transmitter sends. Must be set for full-duplex operation. For loopback  
operation, GSMR[DIAG] must be programmed also; see Section 19.1.1, ÒThe General SCC Mode  
Registers (GSMR1ÐGSMR4).Ó  
10  
11  
Reserved. Should be cleared.  
LCW Late collision window.  
0 A late collision is any collision that occurs at least 64 bytes from the preamble.  
1 A late collision is any collision that occurs at least 56 bytes from the preamble.  
24-16  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part IV. Communications Processor Module  
Table 24-6. PSMR Field Descriptions  
Bits Name  
Description  
12Ð14 NIB  
Number of ignored bits. Determines how soon after RENA assertion the Ethernet controller should  
begin looking for the start frame delimiter. Typically NIB = 101 (22 bits).  
000 Begin searching 13 bits after the assertion of RENA.  
001 Begin searching 14 bits after the assertion of RENA.  
...  
111 Begin searching 24 bits after the assertion of RENA.  
15  
FDE Full duplex Ethernet.  
0 Disable full-duplex Ethernet mode.  
1 Enable full-duplex Ethernet mode.  
Note: When FDE = 1, PSMR[LPB] must be set also.  
24.18 SCC Ethernet Receive BD  
The Ethernet controller uses the RxBD to report on the received data for each buffer.  
0
1
2
3
4
L
5
F
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
E
Ñ
W
I
Ñ
M
Ñ
LG  
NO SH  
CR  
OV  
CL  
Data Length  
Rx Data Buffer Pointer  
Figure 24-6. SCC Ethernet Receive RxBD  
Table 24-7 describes RxBD status and control Þelds.  
Table 24-7. SCC Ethernet Receive RxBD Status and Control  
Field Descriptions  
Bits Name  
Description  
0
E
Empty.  
0 The buffer is full or stopped receiving data because an error occurred.The core can read or write any  
Þelds of this RxBD. The CPM does not use this BD as long as the E bit is zero.  
1 The buffer is not full. The CPM controls this BD and its buffer; do not modify this BD.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (Þnal BD in table).  
0 Not the last BD in the table.  
1 Last BD in the table. After this buffer is used, the CPM receives incoming data into the Þrst BD that  
RBASE points to.The number of BDs is determined only by the W bit and overall space constraints of  
the dual-port RAM.  
3
I
Interrupt. Note that this bit does not mask SCCE[RXF] interrupts.  
0 No SCCE[RXB] interrupt is generated after this buffer is used.  
1 SCCE[RXB] or SCCE[RXF] is set when this buffer is used by the Ethernet controller. These two bits  
can cause interrupts if they are enabled.  
MOTOROLA  
Chapter 24. SCC Ethernet Mode  
24-17  
       
Part IV. Communications Processor Module  
Table 24-7. SCC Ethernet Receive RxBD Status and Control  
Field Descriptions (Continued)  
Bits Name  
Description  
4
L
Last in frame. The Ethernet controller sets this bit when this buffer is the last one in a frame, which  
occurs when the end of a frame is reached or an error is received. In the case of error, one or more of  
the CL, OV, CR, SH, NO, and LG bits are set.The Ethernet controller writes the number of frame octets  
to the data length Þeld.  
0 The buffer is not the last one in a frame.  
1 The buffer is the last one in a frame.  
5
F
First in frame. The Ethernet controller sets this bit when this buffer is the Þrst one in a frame.  
0 The buffer is not the Þrst one in a frame.  
1 The buffer is the Þrst one in a frame.  
6
7
Ñ
M
Reserved, should be cleared.  
Miss. (valid only if L = 1) The Ethernet controller sets M for frames that are accepted in promiscuous  
mode, but are ßagged as a miss by internal address recognition. Thus, in promiscuous mode, M  
determines whether a frame is destined for this station.  
0 The frame is received because of an address recognition hit.  
1 The frame is received because of promiscuous mode.  
8Ð9  
10  
Ñ
Reserved, should be cleared.  
LG  
Rx frame length violation. Set when a frame length greater than the maximum deÞned for this channel  
has been recognized. Only the maximum number of bytes allowed is written to the buffer.  
11  
12  
NO  
SH  
Rx nonoctet-aligned frame. Set when a frame containing a number of bits not divisible by eight is  
received. Also, the CRC check that occurs at the preceding byte boundary generated an error.  
Short frame. Set if a frame smaller than the minimum deÞned for this channel was recognized. Occurs  
if PSMR[RSH] = 1.  
13  
14  
15  
CR  
OV  
CL  
Rx CRC error. set when a frame contains a CRC error.  
Overrun. Set when a receiver overrun occurs during frame reception.  
Collision. This frame is closed because a collision occurred during frame reception. CL is set only if a  
late collision occurs or if PSMR[RSH] is enabled. Late collisions are better deÞned in PSMR[LCW].  
Data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer  
Descriptors (BDs).Ó Data length includes the total number of frame octets (including four  
bytes for CRC).  
Figure 24-7 shows an example of how RxBDs are used in receiving.  
24-18  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part IV. Communications Processor Module  
MRBLR = 64 Bytes for this SCC  
Buffer  
Receive BD 0  
E
0
L
0
F
1
Status  
Length  
Destination Address (6)  
Source Address (6)  
0x0040  
Buffer Full  
Pointer  
32-Bit Buffer Pointer  
64 Bytes  
Type/Length (2)  
Data Bytes (50)  
Receive BD 1  
Buffer  
CRC Bytes (4)  
Tag Byte (1)  
Empty  
E
0
L
1
F
0
Status  
Length  
0x0045  
Buffer Closed  
after CRC Received.  
Optional Tag Byte  
Appended  
Pointer  
32-Bit Buffer Pointer  
64 Bytes  
Receive BD 2  
Buffer  
E
1
Status  
Length  
Old Data from  
Collided Frame Will  
be Overwritten  
XXXX  
64 Bytes  
Collision  
Causes Buffer  
to be Reused  
Pointer  
32-Bit Buffer Pointer  
Empty  
Buffer  
Receive BD 3  
E
1
Status  
Length  
XXXX  
64 Bytes  
Empty  
Buffer  
Still Empty  
Pointer  
32-Bit Buffer Pointer  
Non-Collided Ethernet Frame 1  
Line Idle  
Frame 2  
Two Frames  
Received in Ethernet  
Collision  
Present  
Time  
Time  
Figure 24-7. Ethernet Receiving using RxBDs  
24.19 SCC Ethernet Transmit Buffer Descriptor  
Data is sent to the Ethernet controller for transmission on an SCC channel by arranging it  
in buffers referenced by the channel TxBD table. The Ethernet controller uses TxBDs to  
MOTOROLA  
Chapter 24. SCC Ethernet Mode  
24-19  
     
Part IV. Communications Processor Module  
conÞrm transmission or indicate errors so the core knows buffers have been serviced.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
R
PAD  
W
I
L
TC DEF HB  
LC  
RL  
RC  
UN CSL  
Data Length  
Tx Data Buffer Pointer  
Figure 24-8. SCC Ethernet TxBD  
Table 24-8 describes TxBD status and control Þelds.  
Table 24-8. SCC Ethernet Transmit TxBD Status and Control  
Field Descriptions  
Bits Name  
Description  
0
1
2
R
Ready.  
0 The buffer is not ready for transmission. The user can update this BD or its data buffer. The CPM  
clears R after the buffer has been sent or after an error occurs.  
1 The user-prepared buffer has not been sent or is currently being sent. Do not modify this BD.  
PAD Short frame padding. Valid only when L is set. Otherwise, it is ignored.  
0 Do not add PADs to short frames.  
1 Add PADs to short frames. Pad bytes are inserted until the length of the sent frame equals the  
MINFLR and they are stored in PADs in the parameter RAM.  
W
Wrap (Þnal BD in table).  
0 Not the last BD in the table.  
1 Last BD in the table. After this buffer is used, the CPM receives incoming data into the Þrst BD that  
TBASE points to in the table.The number of TxBDs in this table is determined only by the W bit and  
overall space constraints of the dual-port RAM.  
Note: The TxBD table must contain more than one BD in Ethernet mode.  
3
I
Interrupt.  
0 No interrupt is generated after this buffer is serviced.  
1 SCCE[TXB] or SCCE[TXE] is set after this buffer is serviced.These bits can cause interrupts if they  
are enabled.  
4
5
6
L
Last.  
0 Not the last buffer in the transmit frame.  
1 Last buffer in the transmit frame.  
TC Tx CRC. Valid only when L = 1. Otherwise, it is ignored.  
0 End transmission immediately after the last data byte.  
1 Transmit the CRC sequence after the last data byte.  
DEF Defer indication.The frame was deferred before being sent successfully, that is, the transmitter had to  
wait for carrier sense before sending because the line was busy. This is not a collision indication;  
collisions are indicated in RC.  
7
8
HB Heartbeat. Set when the collision input was not asserted within 20 transmit clocks after transmission.  
HB cannot be set unless PSMR[HBC] = 1. The SCC writes HB after it Þnishes sending the buffer.  
LC Late collision. Set when a collision occurred after the number of bytes deÞned for PSMR[LCW] are  
sent. The Ethernet controller stops sending and writes this bit after it Þnishes sending the buffer.  
24-20  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
Table 24-8. SCC Ethernet Transmit TxBD Status and Control  
Field Descriptions (Continued)  
Bits Name  
Description  
9
RL Retransmission limit. Set when the transmitter fails (Retry Limit + 1) attempts to successfully transmit  
a message because of repeated collisions on the medium.The Ethernet controller writes this bit after  
it Þnishes attempting to send the buffer.  
10Ð13 RC Retry count. Indicates the number of retries required before the frame was sent successfully. If RC =  
0, the frame was sent correctly the Þrst time. If RC = 15 and RET_LIM = 15 in the parameter RAM, 15  
retries were required. Because the counter saturates at 15, if RC = 15 and RET_LIM > 15, then 15 or  
more retries were required. The controller writes this Þeld after it successfully sends the buffer.  
14  
UN Underrun. Set when the Ethernet controller encounters a transmitter underrun while sending the  
buffer. The Ethernet controller writes UN after it Þnishes sending the buffer.  
15  
CSL Carrier sense lost. Set when carrier sense is lost during frame transmission. The Ethernet controller  
writes CSL after it Þnishes sending the buffer.  
Data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer  
Descriptors (BDs).Ó  
24.20 SCC Ethernet Event Register (SCCE)/Mask  
Register (SCCM)  
The SCC event register (SCCE) is used as the Ethernet event register to generate interrupts  
and report events recognized by the Ethernet channel. When an event is recognized, the  
Ethernet controller sets the corresponding SCCE bit. Interrupts are enabled by setting, and  
masked by clearing, the equivalent bits in the Ethernet mask register (SCCM). SCCE bits  
are cleared by writing ones; writing zeros has no effect. All unmasked bits must be cleared  
before the CPM clears the internal interrupt request.  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field  
Reset  
R/W  
Ñ
GRA  
Ñ
TXE RXF BSY TXB RXB  
0000_0000_0000_0000  
R/W  
Addr  
0x11A10 (SCCE1); 0x11A30 (SCCE2); 0x11A50 (SCCE3); 0x11A70 (SCCE4)  
0x11A14 (SCCM1); 0x11A34 (SCCM2); 0x11A54 (SCCM3); 0x11A74 (SCCM4)  
Figure 24-9. SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)  
Table 24-9 describes SCCE and SCCM Þelds.  
Table 24-9. SCCE/SCCM Field Descriptions  
Bits Name  
Description  
0Ð7  
8
Ñ
Reserved, should be cleared.  
GRA Graceful stop complete. Set as soon the transmitter Þnishes any frame that was in progress when a  
GRACEFUL STOP TRANSMIT command was issued. It is set immediately if no frame was in progress.  
MOTOROLA  
Chapter 24. SCC Ethernet Mode  
24-21  
         
Part IV. Communications Processor Module  
Table 24-9. SCCE/SCCM Field Descriptions (Continued)  
Bits Name  
Description  
9Ð10  
11  
Ñ
Reserved, should be cleared.  
TXE Set when an error occurs on the transmitter channel.  
12  
RXF Rx frame. Set when a complete frame has been received on the Ethernet channel.  
BSY Busy condition. Set when a frame is received and discarded due to a lack of buffers.  
TXB Tx buffer. Set when a buffer has been sent on the Ethernet channel.  
13  
14  
15  
RXB Rx buffer. Set when a buffer that was not a complete frame was received on the Ethernet channel.  
Figure 24-10 shows an example of interrupts that can be generated in Ethernet protocol.  
Frame  
Received in Ethernet  
Stored in Rx Buffer  
Time  
P
SFD DA SA T/L  
D
CR  
RXD  
Line Idle  
Line Idle  
RENA  
Ethernet SCCE  
Events  
RXB  
RXF  
NOTES  
:
1. RXB event assumes receive buffers are 64 bytes each.  
2. The RENA events, if required, must be programmed in the parallel I/O ports, not in the SCC itself.  
3. The RxF interrupt may occur later than RENA due to receive FIFO latency.  
Frame  
Transmitted by Ethernet  
Stored in Tx Buffer  
P
SFD DA SA T/L  
D
CR  
TXD  
Line Idle  
Line Idle  
TENA  
CLSN  
Ethernet SCCE  
Events  
TXB  
TXB, GRA  
NOTES:  
1. TXB events assume the frame required two transmit buffers.  
2. The GRA event assumes a GRACEFUL STOP TRANSMIT command was issued during frame transmission.  
3. The TENA or CLSN events, if required, must be programmed in the parallel I/O ports, not in the SCC itself.  
LEGEND:  
P = Preamble, SFD = Start frame delimiter, DA and SA = Source/Destination address,  
T/L = Type/Length, D = Data, CR = CRC bytes  
Figure 24-10. Ethernet Interrupt Events Example  
24-22  
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MOTOROLA  
 
Part IV. Communications Processor Module  
Note that the SCC status register (SCCS) cannot be used with the Ethernet protocol. The  
current state of the RENA and CLSN signals can be found in the parallel I/O ports.  
24.21 SCC Ethernet Programming Example  
The following is an initialization sequence for the SCC2 in Ethernet mode. The CLK3 pin  
is used for the Ethernet receiver and CLK4 is used for the transmitter.  
1. ConÞgure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and  
PDIRD[27] and clear PDIRD[28] and PSORD[27,28].  
2. ConÞgure ports C and D pins to enable TENA2 (RTS2), CLSN2 (CTS2) and  
RENA2 (CD2). Set PPARD[26], PPARC[12,13] and PDIRD[26] and clear  
PDIRC[12,13], PSORC[12,13] and PSORD[26].  
3. ConÞgure port C pins to enable CLK3 and CLK4. Set PPARC[28,29] and clear  
PDIRC[28,29] and PSORC[28,29].  
4. Connect CLK3 to the SCC2 receiver and CLK4 to the transmitter using the CPM  
mux. Program CMXSCR[R2CS] to 0b110 and CMXSCR[T2CS] to 0b111.  
5. Connect the SCC2 to the NMSI and clear CMXSCR[SC2].  
6. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and  
TxBD in the dual-port RAM. Assuming one RxBD at the beginning of the dual-port  
RAM and one TxBD following that RxBD, write RBASE with 0x0000 and TBASE  
with 0x0008.  
7. Write 0x04A1_0000 to the CPCR to execute an INIT RX AND TX PARAMETERS  
command for this channel.  
8. Clear CRCEC, ALEC, and DISFC for clarity.  
9. Write PAD with 0x8888 for the PAD value.  
10.Write RET_LIM with 0x000F.  
11.Write MFLR with 0x05EE to make the maximum frame size 1518 bytes.  
12.Write MINFLR with 0x0040 to make the minimum frame size 64 bytes.  
13.Write MAXD1 and MAXD2 with 0x05F0 to make the maximum DMA count 1520  
bytes.  
14.Clear GADDR1ÐGADDR4. The group hash table is not used.  
15.Write PADDR1_H with 0x0000, PADDR1_M with 0x0000, and PADDR1_L with  
0x0040 to conÞgure the physical address.  
16.Clear P_PER. It is not used.  
17.Clear IADDR1ÐIADDR4. The individual hash table is not used.  
18.Clear TADDR_H, TADDR_M, and TADDR_L for clarity.  
19.Initialize the RxBD and assume the Rx data buffer is at 0x0000_1000 in main  
memory. Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data  
Length] (optional), and 0x0000_1000 to RxBD[Buffer Pointer].  
MOTOROLA  
Chapter 24. SCC Ethernet Mode  
24-23  
   
Part IV. Communications Processor Module  
20.Initialize the TxBD and assume the Tx data frame is at 0x0000_2000 in main  
memory and contains fourteen 8-bit characters (destination and source addresses  
plus the type Þeld). Write 0xFC00 to TxBD[Status and Control], add PAD to the  
frame and generate a CRC. Then write 0x000D to TxBD[Data Length] and  
0x0000_2000 to TxBD[Buffer Pointer].  
21.Write 0xFFFF to the SCCE register to clear any previous events.  
22.Write 0x001A to the SCCM register to enable the TXE, RXF, and TXB interrupts.  
23.Write 0x0040_0000 to the SIU interrupt mask register low (SIMR_L) so the SMC1  
can generate a system interrupt. Initialize SIU interrupt pending register low  
(SIPNR_L) by writing 0xFFFF_FFFF to it.  
24.Write 0x0000_0000 to GSMR_H2 to enable normal operation of all modes.  
25.Write 0x1088_000C to the GSMR_L2 register to conÞgure CTS (CLSN) and CD  
(RENA) to automatically control transmission and reception (DIAG bits) and the  
Ethernet mode. TCI is set to allow more setup time for the EEST to receive the  
MPC8260 transmit data. TPL and TPP are set for Ethernet requirements. The DPLL  
is not used with Ethernet. Note that the ENT and ENR are not enabled yet.  
26.Write 0xD555 to the DSR.  
27.Set the PSMR2 to 0x0A0A to conÞgure 32-bit CRC, promiscuous mode, and begin  
searching for the start frame delimiter 22 bits after RENA2 (CD2).  
28.Write 0x1088_003C to GSMR_L2 to enable the SCC2 transmitter and receiver. This  
additional write ensures that ENT and ENR are enabled last.  
After 14 bytes and the 46 bytes of automatic pad (plus the 4 bytes of CRC) are sent, the  
TxBD is closed. Additionally, the receive buffer is closed after a frame is received. Any data  
received after 1520 bytes or a single frame causes a busy (out-of-buffers) condition because  
only one RxBD is prepared.  
24-24  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Chapter 25  
SCC AppleTalk Mode  
250  
2A50 ppleTalk is a set of protocols developed by Apple Computer, Inc. to provide a LAN  
service between Macintosh computers and printers. Although AppleTalk can be  
implemented over a variety of physical and link layers, including Ethernet, AppleTalk  
protocols have been most closely associated with the LocalTalk physical and link-layer  
protocol, an HDLC-based protocol that runs at 230.4 kbps. In this manual, the term  
ÔAppleTalk controllerÕ refers to the support that the MPC8260 provides for LocalTalk  
protocol. The AppleTalk controller provides required frame synchronization, bit sequence,  
preamble, and postamble onto standard HDLC frames. These capabilities, with the use of  
the HDLC controller in conjunction with DPLL operation in FM0 mode, provide the proper  
connection formats to the LocalTalk bus.  
25.1 Operating the LocalTalk Bus  
A LocalTalk frame, shown in Figure , is basically a modiÞed HDLC frame.  
Sync  
Sequence  
HDLC  
Flags  
Destination  
Address  
Source  
Address  
Control  
Byte  
Data  
(Optional)  
Closing  
Flag  
Abort  
Sequence  
CRC-16  
2 bytes  
> 3 bits  
2 or more  
bytes  
1 byte  
1 byte  
1 byte  
0-600 bytes  
1 byte  
12–18 ones  
Figure 25-1. LocalTalk Frame Format  
First, a synchronization sequence of more than three bits is sent. This sequence consists of  
at least one logical one bit (FM0 encoded) followed by two bit times or more of line idle  
with no particular maximum time speciÞed. The idle time allows LocalTalk equipment to  
sense a carrier by detecting a missing clock on the line. The remainder of the frame is a  
typical half-duplex HDLC frame. Two or more ßags are sent, allowing bit, byte, and frame  
delineation or detection. Two bytes of address, destination, and source are sent next,  
followed by a byte of control and 0Ð600 data bytes. Next, two bytes of CRC (the common  
16-bit CRC-CCITT polynomial referenced in the HDLC standard protocol) are sent. The  
LocalTalk frame is then terminated by a ßag and a restricted HDLC abort sequence. Then  
the transmitterÕs driver is disabled.  
MOTOROLA  
Chapter 25. SCC AppleTalk Mode  
25-1  
           
Part IV. Communications Processor Module  
The control byte within the LocalTalk frame indicates the type of frame. Control byte  
values from 0x01Ð0x7F are data frames; control byte values from 0x80Ð0xFF are control  
frames. Four control frames are deÞned:  
¥
¥
¥
¥
ENQÑEnquiry  
ACKÑEnquiry acknowledgment  
RTSÑRequest to send a data frame  
CTSÑClear to send a data frame  
Frames are sent in groups known as dialogs, which are handled by the software. For  
instance, to transfer a data frame, three frames are sent over the network. An RTS frame  
(not to be confused with the RS-232 RTS pin) is sent to request the network, a CTS frame  
is sent by the destination node, and the data frame is sent by the requesting node. These  
three frames comprise one possible type of dialog.After a dialog begins, other nodes cannot  
start sending until the dialog is complete. Frames within a dialog are sent with a maximum  
interframe gap (IFG) of 200 µs. Although the LocalTalk speciÞcation does not state it, there  
is also a minimum recommended IFG of 50 µs. Dialogs must be separated by a minimum  
interdialog gap (IDG) of 400 µs. In general, these gaps are implemented by the software.  
Depending on the protocol, collisions should be encountered only during RTS and ENQ  
frames. Once frame transmission begins, it is fully sent, regardless of whether it collides  
with another frame. ENQ frames are infrequent and are sent only when a node powers up  
and enters the network. A higher-level protocol controls the uniqueness and transmission  
of ENQ frames.  
In addition to the frame Þelds, LocalTalk requires that the frame be FM0 (differential  
Manchester space) encoded, which requires one level transition on every bit boundary. If  
the value to be encoded is a logical zero, FM0 requires a second transition in the middle of  
the bit time. The purpose of FM0 encoding is to avoid having to transmit clocking  
information on a separate wire. With FM0, the clocking information is present whenever  
valid data is present.  
25.2 Features  
The following list summarizes the features of the SCC in AppleTalk mode:  
¥
¥
¥
¥
¥
¥
¥
¥
Superset of the HDLC controller features  
FM0 encoding/decoding  
Programmable transmission of sync sequence  
Automatic postamble transmission  
Reception of sync sequence does not cause extra SCCE[DCC] interrupts  
Reception is automatically disabled while sending a frame  
Transmit-on-demand feature expedites frames  
Connects directly to an RS-422 transceiver  
25-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
25.3 Connecting to AppleTalk  
As shown in Figure , the MPC8260 connects to LocalTalk, and, using TXD, RTS, and  
RXD, is an interface for the RS-422 transceiver. The RS-422, in turn, is an interface for the  
LocalTalk connector. Although it is not shown, a passive RC circuit is recommended  
between the transceiver and connector.  
MPC8260  
RS-422  
MINI-DIN 8  
Connection  
Tx Data  
Tx Enable  
Rx Data  
SCC  
TXD  
RTS  
RXD  
Stored in Receive Buffer  
Stored in Transmit Buffer  
6-Bit Sync Two HDLC Destination Source  
Sequence Flags Address Address  
Control  
Byte  
Closing  
Flag  
16 Ones  
(Abort)  
TXD  
RTS  
Data  
CRC-16  
Standard HDLC frame handling  
Figure 25-2. Connecting the MPC8260 to LocalTalk  
The 16´ overspeed of a 3.686-MHz clock can be generated from an external frequency  
source or from one of the baud rate generators if the resulting output frequency is close to  
a multiple of the 3.686 MHz frequency. The MPC8260 asserts RTS throughout the duration  
of the frame so that RTS can be used to enable the RS-422 transmit driver.  
25.4 Programming the SCC in AppleTalk Mode  
The AppleTalk controller is implemented by setting certain bits in the HDLC controller.  
Otherwise, Chapter 21, ÒSCC HDLC Mode,Ó describes how to program the HDLC  
controller. Use GSMR, PSMR, or TODR to program the AppleTalk controller.  
25.4.1 Programming the GSMR  
Program the GSMR as described below:  
1. Set MODE to 0b0010 (AppleTalk).  
2. Set DIAG to 0b00 for normal operation, with CD and CTS grounded or conÞgured  
for parallel I/O. This causes CD and CTS to be internally asserted to the SCC.  
3. Set RDCR and TDCR to (0b10) a 16´ clock.  
4. Set the TENC and RENC bits to 0b010 (FM0).  
MOTOROLA  
Chapter 25. SCC AppleTalk Mode  
25-3  
             
Part IV. Communications Processor Module  
5. Clear TEND for default operation.  
6. Set TPP to 0b11 for a preamble pattern of all ones.  
7. Set TPL to 0b000 to transmit the next frame with no synchronization sequence and  
to 001 to transmit the next frame with the LocalTalk synchronization sequence. For  
example, data frames do not require a preceding synchronization sequence. These  
bits may be modiÞed on-the-ßy if the AppleTalk protocol is selected.  
8. Clear TINV and RINV so data will not be inverted.  
9. Set TSNC to 1.5 bit times (0b10).  
10.Clear EDGE. Both the positive and negative edges are used to change the sample  
point (default).  
11.Clear RTSM (default).  
12.Set all other bits to zero or default.  
13.Set ENT and ENR as the last step to begin operation.  
25.4.2 Programming the PSMR  
Follow these steps to program the protocol-speciÞc mode register:  
1. Set NOF to 0b0001 giving two ßags before frames (one opening ßag, plus one  
additional ßag).  
2. Set CRC 16-bit CRC-CCITT.  
3. Set DRT.  
4. Set all other bits to zero or default.  
For the PSMR deÞnition, see Section 21.8, ÒHDLC Mode Register (PSMR).Ó  
25.4.3 Programming the TODR  
Use the transmit-on-demand (TODR) register to expedite a transmit frame. See  
Section 19.1.4, ÒTransmit-on-Demand Register (TODR).Ó  
25.4.4 SCC AppleTalk Programming Example  
Except for the previously discussed register programming, use the example in  
Section 21.14.6, ÒHDLC Bus Protocol Programming.Ó  
25-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
           
Chapter 26  
Serial Management Controllers (SMCs)  
260  
2T60 he two serial management controllers (SMCs) are full-duplex ports that can be conÞgured  
independently to support one of three protocols or modesÑUART, transparent, or general-  
circuit interface (GCI). Simple UART operation is used to provide a debug/monitor port in  
an application, which allows the SCCs to be free for other purposes. The SMC in UART  
mode is not as complex as that of the SCC in UART mode. The SMC clock can be derived  
from one of the internal baud rate generators or from an external clock signal. However, the  
clock should be a 16´ clock.  
In totally transparent mode, the SMC can be connected to a TDM channel (such as a T1  
line) or directly to its own set of signals. The receive and transmit clocks are derived from  
the TDM channel, the internal baud rate generators, or from an external 1´ clock. The  
transparent protocol allows the transmitter and receiver to use the external synchronization  
signal. The SMC in transparent mode is not as complex as that of the SCC in transparent  
mode.  
Each SMC supports the C/I and monitor channels of the GCI bus, for which the SMC  
connects to a time-division multiplex (TDM) channel in a serial interface (SIx). SMCs  
support loopback and echo modes for testing. The SMC receiver and transmitter are  
double-buffered, corresponding to an effective FIFO size (latency) of two characters.  
Chapter 14, ÒSerial Interface with Time-Slot Assigner,Ó describes GCI interface  
conÞguration.  
MOTOROLA  
Chapter 26. Serial Management Controllers (SMCs)  
26-1  
     
Part IV. Communications Processor Module  
60x Bus  
SYNC  
CLK  
Control  
Registers  
Control  
Logic  
Peripheral Bus  
Rx  
Data  
Tx  
Data  
Register  
Register  
TXD  
RXD  
Shifter  
Shifter  
Figure 26-1. SMC Block Diagram  
The receive data source can be L1RXD if the SMC is connected to a TDM channel of an  
SIx, or SMRXD if it is connected to the NMSI. The transmit data source can be L1TXD if  
the SMC is connected to a TDM or SMTXD if it is connected to the NMSI.  
If the SMC is connected to a TDM, the SMC receive and transmit clocks can be  
independent from each other, as deÞned in Chapter 14, ÒSerial Interface with Time-Slot  
Assigner.Ó However, if the SMC is connected to the NMSI, receive and transmit clocks  
must be connected to a single clock source (SMCLK), an internal signal name for a clock  
generated from the bank of clocks. SMCLK originates from an external signal or one of the  
four internal baud rate generators.  
An SMC connected to a TDM derives a synchronization pulse from the TSA. An SMC  
connected to the NMSI using transparent protocol can use SMSYN for synchronization to  
determine when to start a transfer. SMSYN is not used when the SMC is in UART mode.  
26.1 Features  
The following is a list of the SMCÕs main features:  
¥
¥
Each SMC can implement the UART protocol on its own signals  
Each SMC can implement a totally transparent protocol on a multiplexed or  
nonmultiplexed line. This mode can also be used for a fast connection between  
MPC8260s.  
¥
¥
Each SMC channel fully supports the C/I and monitor channels of the GCI (IOM-2)  
in ISDN applications  
Two SMCs support the two sets of C/I and monitor channels in the SCIT channels 0  
and 1  
26-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part IV. Communications Processor Module  
¥
¥
Full-duplex operation  
Local loopback and echo capability for testing  
26.2 Common SMC Settings and ConÞgurations  
The following sections describe settings and conÞgurations that are common to the SMCs.  
26.2.1 SMC Mode Registers (SMCMR1/SMCMR2)  
The SMC mode registers (SMCMR1 and SMCMR2), shown in Figure 26-2, selects the  
SMC mode as well as mode-speciÞc parameters. The functions of SMCMR[8Ð15] are the  
same for each protocol. Bits 0Ð7 vary according to protocol selected by the SM bits.  
Bit  
Field: UART  
Transparent  
GCI  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Ñ
CLEN  
SL PEN  
PM  
Ñ
SM  
DM  
TEN REN  
Ñ
BS REVD  
C#  
ME  
Ñ
Reset  
0000_0000_0000_0000  
R/W  
R/W  
Address  
0x11A82 (SMCMR1), 0x11A92 (SMCMR2)  
Figure 26-2. SMC Mode Registers (SMCMR1/SMCMR2)  
MOTOROLA  
Chapter 26. Serial Management Controllers (SMCs)  
26-3  
         
Part IV. Communications Processor Module  
Table 26-1 describes SMCMR Þelds.  
Table 26-1. SMCMR1/SMCMR2 Field Descriptions  
Bits Name  
Description  
0
Ñ
Reserved, should be cleared.  
1Ð4  
CLEN Character length (UART). Number of bits in the character minus one. The total is the sum of 1 (start  
bit always present) + number of data bits (5Ð14) + number of parity bits (0 or 1) + number of stop bits  
(1 or 2). For example, for 8 data bits, no parity, and 1 stop bit, the total number of bits in the character  
is 1 + 8 + 0 + 1 = 10. So, CLEN should be programmed to 9.  
Characters range from 5Ð14 bits. If the data bit length is less than 8, the msbs of each byte in  
memory are not used on transmit and are written with zeros on receive. If the length is more than 8,  
the msbs of each 16-bit word are not used on transmit and are written with zeros on receive.  
The character must not exceed 16 bits. For a 14-bit data length, set SL to one stop bit and disable  
parity. For a 13-bit data length with parity enabled, set SL to one stop bit. Writing values 0 to 3 to  
CLEN causes erratic behavior.  
Character length (transparent). The values 3Ð15 specify 4Ð16 bits per character. If a character is less  
than 8 bits, the most-signiÞcant bits of the byte in buffer memory are not used on transmit and are  
written with zeros on receive. If character length is more than 8 bits but less than 16, the most-  
signiÞcant bits of the half-word in buffer memory are not used on transmit and are written with zeros  
on receive.  
Note: Using values 0Ð2 causes erratic behavior. Larger character lengths increase an SMC channelÕs  
potential performance and lowers the performance impact of other channels. For instance, using 16-  
rather than 8-bit characters is encouraged if 16-bit characters are acceptable in the end application.  
Character length (GCI). Number of bits in the C/I and monitor channels of the SCIT channels 0 or 1.  
(values 0Ð15 correspond to 1Ð16 bits) CLEN should be 13 for SCIT channel 0 or GCI (8 data bits,  
plus A and E bits, plus 4 C/I bits = 14 bits). It should be 15 for the SCIT channel 1 (8 data, bits, plus A  
and E bits, plus 6 C/I bits = 16 bits).  
5
SL  
Stop length. (UART)  
0 One stop bit.  
1 Two stop bits.  
Ñ
Reserved, should be cleared. (transparent)  
ME  
Monitor enable. (GCI)  
0 The SMC does not support the monitor channel.  
1 The SMC supports the monitor channel.  
6
PEN Parity enable. (UART)  
0 No parity.  
1 Parity is enabled for the transmitter and receiver as determined by the PM bit.  
BS  
Byte sequence(transparent). Controls the byte transmission sequence if REVD is set for a character  
length greater than 8 bits. Clear BS to maintain behavior compatibility with MC68360 QUICC.  
0 Normal mode. This should be selected if the character length is not larger than 8 bits.  
1 Transmit lower address byte Þrst.  
Ñ
Reserved, should be cleared. (GCI)  
7
PM  
Parity mode. (UART)  
0 Odd parity.  
1 Even parity.  
REVD Reverse data. (transparent)  
0 Normal mode.  
1 Reverse the character bit order. The msb is sent Þrst.  
C#  
Ñ
SCIT channel number. (GCI)  
0 SCIT channel 0  
1 SCIT channel 1. Required for Siemens ARCOFI and SGS S/T chips.  
8Ð9  
Reserved, should be cleared.  
26-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part IV. Communications Processor Module  
Table 26-1. SMCMR1/SMCMR2 Field Descriptions (Continued)  
Bits Name  
Description  
10Ð11 SM  
SMC mode.  
00 GCI or SCIT support.  
01 Reserved.  
10 UART (must be selected for SMC UART operation).  
11 Totally transparent operation.  
12Ð13 DM  
Diagnostic mode.  
00 Normal operation.  
01 Local loopback mode.  
10 Echo mode.  
11 Reserved.  
14  
15  
TEN  
SMC transmit enable.  
0 SMC transmitter disabled.  
1 SMC transmitter enabled.  
REN SMC receive enable.  
0 SMC receiver disabled.  
1 SMC receiver enabled.  
26.2.2 SMC Buffer Descriptor Operation  
In UART and transparent modes, the SMCÕs memory structure is like the SCCÕs, except that  
SMC-associated data is stored in buffers. Each buffer is referenced by a BD and organized  
in a BD table located in the dual-port RAM. See Figure 26-3.  
Dual-Port RAM  
External Memory  
TxBD Table  
Status and Control  
Data Length  
SMC TxBD  
Table  
Buffer Pointer  
Tx Data Buffer  
RxBD Table  
Status and Control  
Data Length  
SMC RxBD  
Table  
Buffer Pointer  
Rx Data Buffer  
Pointer to SMCx  
RxBD Table  
Pointer to SMCx  
TxBD Table  
Figure 26-3. SMC Memory Structure  
MOTOROLA  
Chapter 26. Serial Management Controllers (SMCs)  
26-5  
       
Part IV. Communications Processor Module  
The BD table allows buffers to be deÞned for transmission and reception. Each table forms  
a circular queue. The CP uses BDs to conÞrm reception and transmission so that the  
processor knows buffers have been serviced. The data resides in external or internal buffers.  
When SMCs are conÞgured to operate in GCI mode, their memory structure is predeÞned  
to be one half-word long for transmit and one half-word long for receive. For more  
information on these half-word structures, see Section 26.5, ÒThe SMC in GCI Mode.Ó  
26.2.3 SMC Parameter RAM  
The CP accesses each SMCÕs parameter table using a user-programmed pointer  
(SMCx_BASE) located in the parameter RAM; see Section 13.5.2, ÒParameter RAM.Ó  
Each SMC parameter RAM table can be placed at any 64-byte aligned address in the dual-  
port RAMÕs general-purpose area (banks #1Ð#8). The protocol-speciÞc portions of the  
SMC parameter RAM are discussed in the sections that follow. The SMC parameter RAM  
shared by the UART and transparent protocols is shown in Table 26-2. Parameter RAM for  
GCI protocol is described in Table 26-17.  
Table 26-2. SMC UART and Transparent Parameter RAM Memory Map  
1
Offset  
Name  
Width  
Description  
0x00  
0x02  
RBASE  
TBASE  
Hword RxBDs and TxBDs base address. (BD table pointer) DeÞne starting points in the dual-  
port RAM of the set of BDs for the SMC send and receive functions. They allow ßexible  
partitioning of the BDs. By selecting RBASE and TBASE entries for all SMCs and by  
Hword  
setting W in the last BD in each list, BDs are allocated for the send and receive side of  
every SMC. Initialize these entries before enabling the corresponding channel.  
ConÞguring BD tables of two enabled SMCs to overlap causes erratic operation. RBASE  
and TBASE should be a multiple of eight.  
0x04  
0x05  
RFCR  
TFCR  
Byte  
Byte  
Rx/Tx function code. The two SMC channels have four RFCRs for receive data buffers  
and four TFCRs for transmit data buffers. See Section 26.2.3.1, ÒSMC Function Code  
Registers (RFCR/TFCR).Ó  
0x06  
MRBLR  
Hword Maximum receive buffer length. The most bytes the MPC8260 writes to a receive buffer  
before moving to the next buffer. It can write fewer bytes than MRBLR if a condition like  
an error or end-of-frame occurs, but it cannot exceed MRBLR. MPC8260 buffers should  
not be smaller than MRBLR. SMC transmit buffers are unaffected by MRBLR.  
Transmit buffers can be individually given varying lengths through the data length Þeld.  
MRBLR can be changed while an SMC is operating only if it is done in a single bus cycle  
with one 16-bit move (not two 8-bit bus cycles back-to-back). This occurs when the CP  
shifts control to the next RxBD, so the change does not take effect immediately. To  
guarantee the exact RxBD on which the change occurs, change MRBLR only while the  
SMC receiver is disabled. MRBLR should be greater than zero and should be even if  
character length exceeds 8 bits.  
2
0x08  
0x0C  
RSTATE  
Ñ
Word  
Word  
Rx internal state. Can be used only by the CP.  
2
Rx internal data pointer. Updated by the SDMA channels to show the next address in  
the buffer to be accessed.  
0x10  
RBPTR  
Hword RxBD pointer. Points to the next BD for each SMC channel that the receiver transfers  
data to when it is in idle state, or to the current BD during frame processing. After a reset  
or when the end of the BD table is reached, the CP initializes RBPTR to the value in  
RBASE. Most applications never need to write RBPTR, but it can be written when the  
receiver is disabled or when no receive buffer is in use.  
26-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part IV. Communications Processor Module  
Table 26-2. SMC UART and Transparent Parameter RAM Memory Map (Continued)  
1
Offset  
Name  
Width  
Description  
2
0x12  
Ñ
Hword Rx internal byte count. A down-count value initialized with the MRBLR value and  
decremented with every byte the SDMA channels write.  
2
0x14  
0x18  
0x1C  
Ñ
Word  
Word  
Word  
Rx temp Can be used only by the CP.  
2
TSTATE  
Ñ
Tx internal state. Can be used only by the CP.  
2
Tx internal data pointer. Updated by the SDMA channels to show the next address in  
the buffer to be accessed.  
0x20  
TBPTR  
Hword TxBD pointer. Points to the next BD for each SMC channel the transmitter transfers data  
from when it is in idle state or to the current BD during frame transmission. After reset or  
when the end of the table is reached, the CP initializes TBPTR to the TBASE value. Most  
applications never need to write TBPTR, but it can be written when the transmitter is  
disabled or when no transmit buffer is in use. For instance, after a STOP TRANSMIT or  
GRACEFUL STOP TRANSMIT command is issued and the frame completes its transmission.  
2
0x22  
Ñ
Ñ
Hword Tx internal byte count. A down-count value initialized with the TxBD data length and  
decremented with every byte the SDMA channels read.  
2
0x24  
0x28  
Word  
Tx temp. Can be used only by the CP.  
MAX_IDL Hword Maximum idle characters. (UART protocol-speciÞc parameter) When a character is  
received on the line, the SMC starts counting idle characters received. If MAX_IDL idle  
characters arrive before the next character, an idle time-out occurs and the buffer closes,  
which sends an interrupt request to the core to receive data from the buffer. MAX_IDL  
demarcates frames in UART mode. Clearing MAX_IDL disables the function so the  
buffer never closes, regardless of how many idle characters are received. An idle  
character is calculated as follows: 1 + data length (5 to 14) + 1 (if parity bit is used) +  
number of stop bits (1 or 2). For example, for 8 data bits, no parity, and 1 stop bit,  
character length is 10 bits.  
0x2A IDLC  
Hword Temporary idle counter. (UART protocol-speciÞc parameter) Down-counter in which the  
CP stores the current idle counter value in the MAX_IDL time-out process.  
0x2C BRKLN  
Hword Last received break length. (UART protocol-speciÞc parameter) Holds the length of the  
last received break character sequence measured in character units. For example, if the  
receive signal is low for 20 bit times and the deÞned character length is 10 bits, BRKLN =  
0x002, indicating that the break sequence is at least 2 characters long. BRKLN is  
accurate to within one character length.  
0x2E BRKEC  
Hword Receive break condition counter. (UART protocol-speciÞc parameter) Counts break  
conditions on the line. A break condition may last for hundreds of bit times, yet BRKEC  
increments only once during that period.  
0x30  
BRKCR  
Hword Break count register (transmit). (UART protocol-speciÞc parameter) Determines the  
number of break characters the UART controller sends. Set when the SMC sends a  
break character sequence after a STOP TRANSMIT command. For 8 data bits, no parity, 1  
stop bit, and 1 start bit, each break character is 10 zeros.  
0x32  
0x34  
R_MASK Hword Temporary bit mask. (UART protocol-speciÞc parameter)  
Word SDMA Temp  
Ñ
1
2
From the pointer value programmed in SMCx_BASE: SMC1_BASE at 0x87FC, SMC2_BASE at IMMR + 0x88FC.  
Not accessed for normal operation. May hold helpful information for experienced users and for debugging.  
To extract data from a partially full receive buffer, issue a CLOSE RXBD command.  
MOTOROLA  
Chapter 26. Serial Management Controllers (SMCs)  
26-7  
 
Part IV. Communications Processor Module  
Certain parameter RAM values must be initialized before the SMC is enabled. Other values  
are initialized or written by the CP. Once values are initialized, software typically does not  
need to update them because activity centers mostly around transmit and receive BDs rather  
than parameter RAM. However, note the following:  
¥
¥
Parameter RAM can be read at any time.  
Values that pertain to the SMC transmitter can be written only if SMCMR[TEN] is  
zero or between the STOP TRANSMIT and RESTART TRANSMIT commands.  
¥
Values for the SMC receiver can be written only when SMCMR[REN] is zero, or, if  
the receiver is previously enabled, after an ENTER HUNT MODE command is issued  
but before the CLOSE RXBD command is issued and REN is set.  
26.2.3.1 SMC Function Code Registers (RFCR/TFCR)  
Each SMC channel has four receive buffers (RFCRn) and four transmit buffers (TFCRn).  
The function code registers contain the transaction speciÞcation associated with SDMA  
channel accesses to external memory. Figure 26-4 shows the register format.  
Bit  
Field  
0
1
2
3
4
5
6
7
GBL  
BO  
TC2  
DTB  
Ñ
R/W  
R/W  
Address  
SMC base + 0x04 (RFCR)/SMC base + 0x05 (TFCR)  
Figure 26-4. SMC Function Code Registers (RFCR/TFCR)  
Table 26-3 describes FCR Þelds.  
Table 26-3. RFCR/TFCR Field Descriptions  
Bit Name  
Description  
0Ð1  
2
Ñ
Reserved, should be cleared.  
GBL  
Global access bit  
0 Disable memory snooping  
1 Enable memory snooping  
3Ð4 BO  
Byte ordering. Selects byte ordering of the data buffer.  
00 The DEC/Intel convention (swapped operation or little-endian). The transmission order of bytes  
within a buffer word is opposite of Motorola mode. (32-bit port size memory only).  
01 PowerPC little-endian. As data is sent onto the serial line from the buffer, the LSB of the buffer  
double word contains data to be sent earlier than the MSB of the same double word.  
1x Motorola (big-endian) byte ordering (normal operation). As data is sent onto the serial line from the  
buffer, the MSB of the buffer word contains data to be sent earlier than the LSB of the same word.  
5
6
TC2  
DTB  
Transfer code 2. Contains the transfer code value of TC[2], used during this SDMA channel memory  
access. TC[0Ð1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.  
Data bus indicator.  
0 Use 60x bus for SDMA operation.  
1 Use local bus for SDMA operation.  
7
Ñ
Reserved, should be cleared.  
26-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part IV. Communications Processor Module  
26.2.4 Disabling SMCs On-the-Fly  
An SMC can be disabled and reenabled later by ensuring that buffers are closed properly  
and new data is transferred to or from a new buffer. Such a sequence is required if the  
parameters to be changed are not dynamic. If the register or bit description states that  
dynamic changes are allowed, the sequences need not be followed and the register or bits  
may be changed immediately.  
Note that the SMC does not have to be fully disabled for parameter RAM to be modiÞed.  
Table 26-2 describes when parameter RAM values can be modiÞed. To disable all SCCs,  
2
SMCs, the SPI, and the I C, use the CPCR to reset the CPM with a single command.  
26.2.4.1 SMC Transmitter Full Sequence  
Follow these steps to fully enable or disable the SMC transmitter:  
1. If the SMC is sending data, issue a STOP TRANSMIT command to stop transmission  
smoothly. If the SMC is not sending, if TBPTR is overwritten, or if an INIT TX  
PARAMETERS command is executed, this command is not required.  
2. Clear SMCMR[TEN] to disable the SMC transmitter and put it in reset state.  
3. Update SMC transmit parameters, including the parameter RAM. To switch  
protocols or reinitialize parameters, issue an INIT TX PARAMETERS command.  
4. Issue a RESTART TRANSMIT if an INIT TX PARAMETERS was issued in step 3.  
5. Set SMCMR[TEN]. Transmission now begins using the TxBD that the TBPTR  
value pointed to as soon as the R bit is set in the TxBD.  
26.2.4.2 SMC Transmitter Shortcut Sequence  
This shorter sequence reinitializes transmit parameters to the state they had after reset.  
1. Clear SMCMR[TEN].  
2. Issue an INIT TX PARAMETERS command and make any additional changes.  
3. Set SMCMR[TEN].  
26.2.4.3 SMC Receiver Full Sequence  
Follow these steps to fully enable or disable the receiver:  
1. Clear SMCMR[REN]. Reception is aborted immediately, which disables the SMC  
receiver and puts it in a reset state.  
2. Modify SMC receive parameters, including parameter RAM. To switch protocols or  
reinitialize SMC receive parameters, issue an INIT RX PARAMETERS command.  
3. Issue a CLOSE RXBD command if INIT RX PARAMETERS was not issued in step 2.  
4. Set SMCMR[REN]. Reception immediately uses the RxBD that RBPTR pointed to  
if E is set in the RxBD.  
MOTOROLA  
Chapter 26. Serial Management Controllers (SMCs)  
26-9  
               
Part IV. Communications Processor Module  
26.2.4.4 SMC Receiver Shortcut Sequence  
This shorter sequence reinitializes receive parameters to their state after reset.  
1. Clear SMCMR[REN].  
2. Issue an INIT RX PARAMETERS command and make any additional changes.  
3. Set SMCMR[REN].  
26.2.4.5 Switching Protocols  
To switch the protocol that the SMC is executing without resetting the board or affecting  
any other SMC, use one command and follow these steps:  
1. Clear SMCMR[REN] and SMCMR[TEN].  
2. Issue an INIT TX AND RX PARAMETERS COMMAND to initialize transmit and receive  
parameters. Make any additional SMCMR changes.  
3. Set SMCMR[REN, TEN]. The SMC is now enabled with the new protocol.  
26.2.5 Saving Power  
When SMCMR[TEN, REN] are cleared, the SMC consumes little power.  
26.2.6 Handling Interrupts in the SMC  
Follow these steps to handle an interrupt in the SMC:  
1. Once an interrupt occurs, read SMCE to identify the interrupt source. The SMCE  
bits are usually cleared at this time.  
2. Process the TxBD to reuse it if SMCE[TXB] is set. Extract data from the RxBD if  
SMCE[RXB] is set. To send another buffer, set TxBD[R].  
3. Execute the rÞ instruction.  
26.3 SMC in UART Mode  
SMCs generally offer less functionality and performance in UART mode than do SCCs,  
which makes them more suitable for simpler debug/monitor ports instead of full-featured  
UARTs. SMCs do not support the following features in UART mode.  
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
RTS, CTS, and CD signals  
Receive and transmit sections clocked at different rates  
Fractional stop bits  
Built-in multidrop modes  
Freeze mode for implementing flow control  
Isochronous operation (1´ clock)  
Interrupts on special control character reception  
Ability to transmit data on demand using the TODR  
SCCS register to determine idle status of the receive signal  
Other features for the SCCs as described in the GSMR  
26-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
                   
Part IV. Communications Processor Module  
However, SMCs allow a data length of up to 14 bits; SCCs support up to 8 bits.  
SMCLK  
16x  
(not to scale)  
SMTXD  
Start  
Bit  
5 to 14 Data Bits with the  
Least Significant Bit First  
Parity  
Bit  
1 or 2  
Stop Bits  
(Optional)  
Figure 26-5. SMC UART Frame Format  
26.3.1 Features  
The following list summarizes the main features of the SMC in UART mode:  
¥
¥
¥
¥
¥
¥
¥
¥
Flexible message-oriented data structure  
Programmable data length (5Ð14 bits)  
Programmable 1 or 2 stop bits  
Even/odd/no parity generation and checking  
Frame error, break, and idle detection  
Transmit preamble and break sequences  
Received break character length indication  
Continuous receive and transmit modes  
26.3.2 SMC UART Channel Transmission Process  
The UART transmitter is designed to work with almost no intervention from the core. When  
the core enables the SMC transmitter, it starts sending idles. The SMC immediately polls  
the Þrst BD in the transmit channel BD table and once every character time after that,  
depending on character length. When there is a message to transmit, the SMC fetches data  
from memory and starts sending the message.  
When a BD data is completely written to the transmit FIFO, the SMC writes the message  
status bits into the BD and clears R. An interrupt is issued if the I bit in the BD is set. If the  
next TxBD is ready, the data from its buffer is appended to the previous data and sent over  
the transmit signal without any gaps between buffers. If the next TxBD is not ready, the  
SMC starts sending idles and waits for the next TxBD to be ready.  
By appropriately setting the I bit in each BD, interrupts can be generated after each buffer,  
a speciÞc buffer, or each block is sent. The SMC then proceeds to the next BD. If the CM  
bit is set in the TxBD, the R bit is not cleared, allowing a buffer to be automatically resent  
next time the CP accesses this buffer. For instance, if a single TxBD is initialized with the  
CM and W bits set, the buffer is sent continuously until R is cleared in the BD.  
MOTOROLA  
Chapter 26. Serial Management Controllers (SMCs)  
26-11  
           
Part IV. Communications Processor Module  
26.3.3 SMC UART Channel Reception Process  
When the core enables the SMC receiver, it enters hunt mode and waits for the Þrst  
character. The CP then checks the Þrst RxBD to see if it is empty and starts storing  
characters in the buffer. When the buffer is full or the MAX_IDL timer expires (if enabled),  
the SMC clears the E bit in the BD and generates an interrupt if the I bit in the BD is set. If  
incoming data exceeds the bufferÕs length, the SMC fetches the next BD, and, if it is empty,  
continues transferring data to this BDÕs buffer. If CM is set in the RxBD, the E bit is not  
cleared, so the CP can overwrite this buffer on its next access.  
26.3.4 Programming the SMC UART Controller  
UART mode is selected by setting SMCMR[SM] to 0b10. See Section 26.2.1, ÒSMC Mode  
Registers (SMCMR1/SMCMR2).Ó UART mode uses the same data structure as other  
modes. This structure supports multibuffer operation and allows break and preamble  
sequences to be sent. Overrun, parity, and framing errors are reported via the BDs. At its  
simplest, the SMC UART controller functions in a character-oriented environment,  
whereas each character is sent with the selected stop bits and parity. They are received into  
separate 1-byte buffers. A maskable interrupt can be generated when each buffer is  
received.  
Many applications can take advantage of the message-oriented capabilities that the SMC  
UART supports through linked buffers for sending or receiving. Data is handled in a  
message-oriented environment, so entire messages can be handled instead of individual  
characters. A message can span several linked buffers; each one can be sent and received as  
a linked list of buffers without core intervention, which simpliÞes programming and saves  
processor overhead. In a message-oriented environment, an idle sequence is used as the  
message delimiter. The transmitter can generate an idle sequence before starting a new  
message and the receiver can close a buffer when an idle sequence is found.  
26.3.5 SMC UART Transmit and Receive Commands  
Table 26-4 describes transmit commands issued to the CPCR.  
Table 26-4. Transmit Commands  
Command  
Description  
STOP  
Disables transmission of characters on the transmit channel. If the SMC UART controller receives this  
command while sending a message, it stops sending. The SMC UART controller Þnishes sending any  
data that has already been sent to its FIFO and shift register and then stops sending data.The TBPTR  
is not advanced when this command is issued. The SMC UART controller sends a programmable  
number of break sequences and then sends idles. The number of break sequences, which can be  
zero, should be written to the BRKCR before this command is issued to the SMC UART controller.  
TRANSMIT  
RESTART  
TRANSMIT  
Enables characters to be sent on the transmit channel. The SMC UART controller expects it after  
disabling the channel in its SMCMR and after issuing the STOP TRANSMIT command. The SMC UART  
controller resumes transmission from the current TBPTR in the channelÕs TxBD table.  
INIT TX  
Initializes transmit parameters in this serial channelÕs parameter RAM to their reset state and should  
PARAMETERS only be issued when the transmitter is disabled.The INIT TX and RX PARAMETERS command can also be  
used to reset the transmit and receive parameters.  
26-12  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
             
Part IV. Communications Processor Module  
Table 26-5 describes receive commands issued to the CPCR.  
Table 26-5. Receive Commands  
Command  
Description  
ENTER HUNT MODE Use the CLOSE RXBD command instead ENTER HUNT MODE for an SMC UART channel.  
CLOSE RXBD  
Forces the SMC to close the current receive BD if it is currently being used and to use the next BD  
in the list for any subsequently received data. If the SMC is not receiving data, no action is taken.  
INIT RX  
Initializes receive parameters in this serial channel parameter RAM to reset state. Issue it only if  
the receiver is disabled. INIT TX AND RX PARAMETERS resets both receive and transmit parameters.  
PARAMETERS  
26.3.6 Sending a Break  
A break is an all-zeros character without stop bits. It is sent by issuing a STOP TRANSMIT  
command. After sending any outstanding data, the SMC sends a character of consecutive  
zeros, the number of which is the sum of the character length, plus the number of start,  
parity, and stop bits. The SMC sends a programmable number of break characters  
according to BRKCR and then reverts to idle or sends data if a RESTART TRANSMIT is issued  
before completion. When the break completes, the transmitter sends at least one idle  
character before sending any data to guarantee recognition of a valid start bit.  
26.3.7 Sending a Preamble  
A preamble sequence provides a way to ensure that the line is idle before a new message  
transfer begins. The length of the preamble sequence is constructed of consecutive ones that  
are one-character long. If the preamble bit in a BD is set, the SMC sends a preamble  
sequence before sending that buffer. For 8 data bits, no parity, 1 stop bit, and 1 start bit, a  
preamble of 10 ones would be sent before the Þrst character in the buffer. If no preamble  
sequence is sent, data from two ready transmit buffers can be sent on the transmit signal  
with no delay between them.  
26.3.8 Handling Errors in the SMC UART Controller  
The SMC UART controller reports character reception error conditions via the channel  
BDs and the SMCE. The SMC UART controller has no transmission errors.  
Table 26-6. SMC UART Errors  
Error  
Description  
Overrun  
The SMC maintains a two-character length FIFO for receiving data. Data is moved to the buffer after the  
Þrst character is received into the FIFO; if a receiver FIFO overrun occurs, the channel writes the  
received character into the internal FIFO. It then writes the character to the buffer, closes it, sets the OV  
bit in the BD, and generates the RXB interrupt if it is enabled. Reception then resumes as normal.  
Overrun errors that occasionally occur when the line is idle can be ignored.  
Parity  
Idle  
The channel writes the received character to the buffer, closes it, sets the PR bit in the BD, and  
generates the RXB interrupt if it is enabled. Reception then resumes as normal.  
An idle is found when a character of all ones is received, at which point the channel counts consecutive  
Sequence idle characters. If the count reaches MAX_IDL, the buffer is closed and an RXB interrupt is generated. If  
Receive  
no receive buffer is open, this does not generate an interrupt or any status information. The idle counter  
is reset each time a character is received.  
MOTOROLA  
Chapter 26. Serial Management Controllers (SMCs)  
26-13  
               
Part IV. Communications Processor Module  
Table 26-6. SMC UART Errors (Continued)  
Error  
Description  
Framing  
The SMC received a character with no stop bit. When it occurs, the channel writes the received  
character to the buffer, closes the buffer, sets FR in the BD, and generates the RXB interrupt if it is  
enabled. When this error occurs, parity is not checked for the character.  
Break  
The SMC receiver received an all-zero character with a framing error. The channel increments BRKEC,  
Sequence generates a maskable BRK interrupt in SMCE, measures the length of the break sequence, and stores  
this value in BRKLN. If the channel was processing a buffer when the break was received, the buffer is  
closed with the BR bit in the RxBD set. The RXB interrupt is generated if it is enabled.  
26.3.9 SMC UART RxBD  
Using the BDs, the CP reports information about the received data on a per-buffer basis.  
Then it closes the current buffer, generates a maskable interrupt, and starts receiving data  
into the next buffer after one of the following occurs:  
¥
¥
¥
An error is received during message processing  
A full receive buffer is detected  
A programmable number of consecutive idle characters are received  
Figure 26-6 shows the format of the SMC UART RxBD.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
Ñ
14  
15  
Ñ
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
E
Ñ
W
I
Ñ
CM  
ID  
Ñ
BR  
FR  
PR  
OV  
Data Length  
Rx Data Buffer Pointer  
Figure 26-6. SMC UART RxBD  
Table 26-7 describes RxBD Þelds.  
Table 26-7. SMC UART RxBD Field Descriptions  
Bit Name  
Description  
0
E
Empty.  
0 The buffer is full or data reception stopped due to an error. The core can read or write any Þelds of  
this RxBD. The CP does not use this BD while E is zero.  
1 The buffer is empty or reception is in progress. This RxBD and its buffer are owned by the CP. Once  
E is set, the core should not write any Þelds of this RxBD.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (last BD in RxBD table).  
0 Not the last BD in the table.  
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the Þrst BD that  
RBASE points to in the table.The number of RxBDs in this table is determined only by the W bit and  
overall space constraints of the dual-port RAM.  
3
I
Interrupt.  
0 No interrupt is generated after this buffer is Þlled.  
1 The SMCE[RXB] is set when this buffer is completely Þlled by the CP, indicating the need for the  
core to process the buffer. RXB can cause an interrupt if it is enabled.  
26-14  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part IV. Communications Processor Module  
Table 26-7. SMC UART RxBD Field Descriptions (Continued)  
Bit Name  
Description  
4Ð5  
6
Ñ
Reserved, should be cleared.  
CM  
Continuous mode.  
0 Normal operation.  
1 The CP does not clear the E bit after this BD is closed, allowing the CP to automatically overwrite  
the buffer when it next accesses the BD. However, E is cleared if an error occurs during reception,  
regardless of how CM is set.  
7
ID  
Buffer closed on reception of idles. Set when the buffer has closed because a programmable number  
of consecutive idle sequences is received. The CP writes ID after received data is in the buffer.  
8Ð9  
10  
Ñ
Reserved, should be cleared.  
BR  
Buffer closed on reception of break. Set when the buffer closes because a break sequence was  
received. The CP writes BR after the received data is in the buffer.  
11  
12  
FR  
PR  
Framing error. Set when a character with a framing error is received and located in the last byte of this  
buffer. A framing error is a character with no stop bit. A new receive buffer is used to receive additional  
data. The CP writes FR after the received data is in the buffer.  
Parity error. Set when a character with a parity error is received in the last byte of the buffer. A new  
buffer is used for additional data. The CP writes PR after received data is in the buffer.  
13  
14  
Ñ
Reserved, should be cleared.  
OV  
Overrun. Set when a receiver overrun occurs during reception. The CP writes OV after the received  
data is in the buffer.  
15  
Ñ
Reserved, should be cleared.  
Data length represents the number of octets the CP writes into the buffer. After data is  
received in buffer, the CP only writes them once as the BD closes. Note that the memory  
allocated for this buffer should be no smaller than MRBLR. The Rx data buffer pointer  
points to the Þrst location of the buffer and must be even. The buffer can be in internal or  
external memory. Figure 26-7 shows the UART RxBD process, showing RxBDs after they  
receive 10 characters, an idle period, and Þve characters (one with a framing error). The  
example assumes that MRBLR = 8.  
MOTOROLA  
Chapter 26. Serial Management Controllers (SMCs)  
26-15  
Part IV. Communications Processor Module  
MRBLR = 8 Bytes for this SMC  
Buffer  
Receive BD 0  
E
0
ID  
0
Status  
Length  
Byte 1  
Byte 2  
0008  
Buffer Full  
Pointer  
32-Bit Buffer Pointer  
8 Bytes  
etc.  
Byte 8  
Receive BD 1  
ID  
Buffer  
Byte 9  
Byte 10  
E
0
Status  
Length  
1
0002  
8 Bytes  
Idle Time-Out  
Occurred  
Pointer  
32-Bit Buffer Pointer  
Empty  
Receive BD 2  
ID  
Buffer  
Byte 1  
E
0
FR  
1
Status  
Length  
0
0004  
Byte 2  
Byte 4 has  
Framing Error  
Pointer  
32-Bit Buffer Pointer  
Byte 3  
8 Bytes  
Byte 4 Error!  
Empty  
Receive BD 3  
Buffer  
Byte 5  
E
1
Status  
Length  
XXXX  
Additional Bytes  
are Stored Unless  
Idle Count Expires  
(MAX_IDL)  
8 Bytes  
Pointer  
32-Bit Buffer Pointer  
Reception  
Still in Progress  
with this Buffer  
10 Characters  
5 Characters  
Long Idle Period  
Characters  
Received by UART  
Fourth Character  
has Framing Error!  
Present  
Time  
Time  
Figure 26-7. RxBD Example  
26.3.10 SMC UART TxBD  
Data is sent to the CP for transmission on an SMC channel by arranging it in buffers  
referenced by the channel TxBD table. Using the BDs, the CP confirms transmission or  
indicates error conditions so that the processor knows the buffers have been serviced.  
26-16  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part IV. Communications Processor Module  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
R
Ñ
W
I
Ñ
CM  
P
Ñ
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
Data Length  
Tx Data Buffer Pointer  
Figure 26-8. SMC UART TxBD  
Table 26-8 describes SMC UART TxBD Þelds.  
Table 26-8. SMC UART TxBD Field Descriptions  
Bits Name  
Description  
0
R
Ready  
0 The buffer is not ready for transmission; BD and its buffer can be altered. The CP clears R after the  
buffer has been sent or an error occurs.  
1 The buffer has not been completely sent. This BD cannot updated while R is set.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (Þnal BD in the TxBD table)  
0 Not the last BD in the table.  
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the Þrst BD that  
TBASE points to. The number of TxBDs in this table is determined only by the W bit and overall  
space constraints of the dual-port RAM.  
3
I
Interrupt  
0 No interrupt is generated after this buffer is serviced.  
1 The SMCE[TXB] is set when this buffer is serviced. TXB can cause an interrupt if it is enabled.  
4Ð5  
6
Ñ
Reserved, should be cleared.  
CM  
Continuous mode  
0 Normal operation.  
1 The CP does not clear R after this BD is closed and automatically retransmits the buffer when it  
accesses this BD next.  
7
P
Preamble  
0 No preamble sequence is sent.  
1 The UART sends one all-ones character before it sends the data so that the other end detects an  
idle line before the data is received. If this bit is set and the data length of this BD is zero, only a  
preamble is sent.  
8Ð15  
Ñ
Reserved, should be cleared.  
Data length represents the number of octets that the CP should transmit from this BD data  
buffer. However, it is never modiÞed by the CP and normally is greater than zero. It can be  
zero if P is set and only a preamble is sent. If there are more than 8 bits in the UART  
character, data length should be even. For example, to transmit three UART characters of  
8-bit data, 1 start, and 1 stop, initialize the data length Þeld to 3. To send three UART  
characters of 9-bit data, 1 start, and 1 stop, the data length Þeld should 6, because the three  
9-bit data Þelds occupy three half words in memory (the 9 least-signiÞcant bits of each half  
word).  
Tx data buffer pointer points to the Þrst location of the buffer. It can be even or odd, unless  
the number of data bits in the UART character is greater than 8 bits. Then the buffer pointer  
MOTOROLA  
Chapter 26. Serial Management Controllers (SMCs)  
26-17  
   
Part IV. Communications Processor Module  
must be even. For instance, the pointer to 8-bit data, 1 start, and 1 stop characters can be  
even or odd, but the pointer to 9-bit data, 1 start, and 1 stop characters must be even. The  
buffer can reside in internal or external memory.  
26.3.11 SMC UART Event Register (SMCE)/Mask Register (SMCM)  
The SMC event register (SMCE) generates interrupts and report events recognized by the  
SMC UART channel. When an event is recognized, the SMC UART controller sets the  
corresponding SMCE bit. Bits are cleared by writing a 1; writing 0 has no effect. The SMC  
mask register (SMCM) has the same bit format as SMCE. Setting an SMCM bit enables,  
and clearing it disables, the corresponding interrupt. All unmasked bits must be cleared  
before the CP clears the internal interrupt request.  
Bit  
Field  
0
1
2
3
4
5
6
7
Ñ
BRKE  
Ñ
BRK  
Ñ
BSY  
TXB  
RXB  
Reset  
R/W  
0
R/W  
Address  
0x11A86 (SMCE1), 0x11A96 (SMCE2)/ 0x11A8A (SMCM1), 0x11A9A (SMCM2)  
Figure 26-9. SMC UART Event Register (SMCE)/Mask Register (SMCM)  
Table 26-9 describes SMCE/SMCM Þelds.  
Table 26-9. SMCE/SMCM Field Descriptions  
Bits Name  
Description  
0
1
2
3
Ñ
Reserved, should be cleared.  
BRKE Break end. Set no sooner than after one idle bit is received after the break sequence.  
Reserved, should be cleared.  
Ñ
BRK Break character received. Set when a break character is received. If a very long break sequence  
occurs, this interrupt occurs only once after the Þrst all-zeros character is received.  
4
5
Ñ
Reserved, should be cleared.  
BSY Busy condition. Set when a character is received and discarded due to a lack of buffers. Set no  
sooner than the middle of the last stop bit of the Þrst receive character for which there is no available  
buffer. Reception resumes when an empty buffer is provided.  
6
7
TXB Tx buffer. Set when the transmit data of the last character in the buffer is written to the transmit FIFO.  
Wait two character times to ensure that data is completely sent over the transmit signal.  
RXB Rx buffer. Set when a buffer is received and its associated RxBD is closed. Set no sooner than the  
middle of the last stop bit of the last character that is written to the receive buffer.  
Figure 26-10 shows an example of the timing of various events in the SMCE.  
26-18  
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MOTOROLA  
         
Part IV. Communications Processor Module  
Characters  
Received by SMC UART  
10 Characters  
Time  
Line Idle  
Break  
RXD  
Line Idle  
SMC UART SMCE  
Events  
RX  
RX  
BRK  
BRKE  
NOTES:  
1. The first RX event assumes receive buffers are 6 bytes each.  
2. The second RX event position is programmable based on the MAX_IDL value.  
3. The BRK event occurs after the first break character is received.  
Characters  
Transmitted by SMC UART  
7 Characters  
TXD  
Line Idle  
Line Idle  
SMC UART SMCE  
Events  
TX  
NOTES:  
1. The TX event assumes all seven characters were put into a single buffer, and the TX event occurred when the seventh  
character was written to the SMC transmit FIFO.  
Figure 26-10. SMC UART Interrupts Example  
26.3.12 SMC UART Controller Programming Example  
The following initialization sequence assumes 9,600 baud, 8 data bits, no parity, and 1 stop  
bit in a 66-MHz system. BRG1 and SMC1 are used. (The SMC transparent programming  
example uses an external clock conÞguration; see Section 26.4.11, ÒSMC Transparent  
NMSI Programming Example.Ó)  
1. ConÞgure the port D pins to enable SMTXD1 and SMRXD1. Set PPARD[8,9] and  
PDIRD[9]. Clear PDIRD[8] and PSORD[8,9].  
2. ConÞgure the BRG1. Write BRGC1 with 0x0001_035A. The DIV16 bit is not used  
and the divider is 429 (decimal). The resulting BRG1 clock is 16´ the preferred bit  
rate.  
3. Connect BRG1 to SMC1 using the CPM mux by clearing CMXSMR[SMC1,  
SMC1CS].  
4. In address 0x87FC, assign a pointer to the SMC1 parameter RAM.  
5. Assuming one RxBD at the beginning of dual-port RAM followed by one TxBD,  
write RBASE with 0x0000 and TBASE with 0x0008.  
6. Write 0x1D01_0000 to CPCR to execute the INIT RX AND TX PARAMETERS  
command.  
7. Write RFCR and TFCR with 0x10 for normal operation.  
8. Write MRBLR with the maximum number of bytes per receive buffer. Assume 16  
bytes, so MRBLR = 0x0010.  
MOTOROLA  
Chapter 26. Serial Management Controllers (SMCs)  
26-19  
     
Part IV. Communications Processor Module  
9. Write MAX_IDL with 0x0000 in the SMC UART-speciÞc parameter RAM to  
disable the MAX_IDL functionality for this example.  
10.Clear BRKLN and BRKEC in the SMC UART-speciÞc parameter RAM.  
11.Set BRKCR to 0x0001; if a STOP TRANSMIT COMMAND is issued, one break  
character is sent.  
12.Initialize the RxBD. Assume the Rx data buffer is at 0x0000_1000 in main memory.  
Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (not  
required), and 0x0000_1000 to RxBD[Buffer Pointer].  
13.Assuming the Tx data buffer is at 0x0000_2000 in main memory and contains Þve  
8-bit characters, write 0xB000 to TxBD[Status and Control], 0x0005 to TxBD[Data  
Length], and 0x0000_2000 to TxBD[Buffer Pointer].  
14.Write 0xFF to the SMCE1 register to clear any previous events.  
15.Write 0x57 to the SMCM1 register to enable all possible SMC1 interrupts.  
16.Write 0x0000_1000 to the SIU interrupt mask register low (SIMR_L) so the SMC1  
can generate a system interrupt. Write 0xFFFF_FFFF to the SIU interrupt pending  
register low (SIPNR_L) to clear events.  
17.Write 0x4820 to SMCMR to conÞgure normal operation (not loopback), 8-bit  
characters, no parity, 1 stop bit. The transmitter and receiver are not yet enabled.  
18.Write 0x4823 to SMCMR to enable the SMC transmitter and receiver. This  
additional write ensures that the TEN and REN bits are enabled last.  
After 5 bytes are sent, the TxBD is closed. The receive buffer closes after receiving 16  
bytes. Subsequent data causes a busy (out-of-buffers) condition since only one RxBD is  
ready.  
26.4 SMC in Transparent Mode  
Compared to the SCC in transparent mode, the SMCs generally offer less functionality,  
which helps them provide simpler functions and slower speeds. Transparent mode is  
selected by programming SMCMR[SM] to 0b10. Section 26.2.1, ÒSMC Mode Registers  
(SMCMR1/SMCMR2)Ó describes other protocol-speciÞc bits in the SMCMR. The SMC in  
transparent mode does not support the following features:  
¥
Independent transmit and receive clocks, unless connected to a TDM channel of an  
SIx  
¥
¥
¥
¥
¥
¥
CRC generation and checking  
Full RTS, CTS, and CD signals (supports only one SMSYN signal)  
Ability to transmit data on demand using the TODR  
Receiver/transmitter in transparent mode while executing another protocol  
4-, 8-, or 16-bit SYNC recognition  
Internal DPLL support  
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Part IV. Communications Processor Module  
However, the SMC in transparent mode provides a data character length option of 4 to 16  
bits, whereas the SCCs provide 8 or 32 bits, depending on GSMR[RFW]. The SMC in  
transparent mode is also referred to as the SMC transparent controller.  
26.4.1 Features  
The following list summarizes the features of the SMC in transparent mode:  
¥
¥
¥
Flexible data buffers  
Connects to a TDM bus using the TSA in an SIx  
Transmits and receives transparently on its own set of signals using a sync signal to  
synchronize the beginning of transmission and reception to an external event  
¥
¥
¥
¥
Programmable character length (4Ð16)  
Reverse data mode  
Continuous transmission and reception modes  
Four commands  
26.4.2 SMC Transparent Channel Transmission Process  
The transparent transmitter is designed to work with almost no core intervention. When the  
core enables the SMC transmitter in transparent mode, it starts sending idles. The SMC  
immediately polls the Þrst BD in the transmit channel BD table and once every character  
time, depending on the character length (every 4 to 16 serial clocks). When there is a  
message to transmit, the SMC fetches the data from memory and starts sending the message  
when synchronization is achieved.  
Synchronization can be achieved in two ways. First, when the transmitter is connected to a  
TDM channel, it can be synchronized to a time slot. Once the frame sync is received, the  
transmitter waits for the Þrst bit of its time slot before it starts transmitting. Data is sent only  
during the time slots deÞned by the TSA. Secondly, when working with its own set of  
signals, the transmitter starts sending when SMSYNx is asserted.  
When a BD data is completely written to the transmit FIFO, the L bit is checked and if it is  
set, the SMC writes the message status bits into the BD and clears the R bit. It then starts  
transmitting idles. When the end of the current BD is reached and the L bit is not set, only  
R is cleared. In both cases, an interrupt is issued according to the I bit in the BD. By  
appropriately setting the I bit in each BD, interrupts can be generated after each buffer, a  
speciÞc buffer, or each block is sent. The SMC then proceeds to the next BD. If no  
additional buffers have been presented to the SMC for transmission and the L bit was  
cleared, an underrun is detected and the SMC begins sending idles.  
If the CM bit is set in the TxBD, the R bit is not cleared, so the CP can overwrite the buffer  
on its next access. For instance, if a single TxBD is initialized with the CM and W bits set,  
the buffer is sent continuously until R is cleared in the BD.  
MOTOROLA  
Chapter 26. Serial Management Controllers (SMCs)  
26-21  
       
Part IV. Communications Processor Module  
26.4.3 SMC Transparent Channel Reception Process  
When the core enables the SMC receiver in transparent mode, it waits for synchronization  
before receiving data. Once synchronization is achieved, the receiver transfers the incoming  
data into memory according to the Þrst RxBD in the table. Synchronization can be achieved  
in two ways. First, when the receiver is connected to a TDM channel, it can be synchronized  
to a time slot. Once the frame sync is received, the receiver waits for the Þrst bit of its time  
slot to occur before reception begins. Data is received only during the time slots deÞned by  
the TSA. Secondly, when working with its own set of signals, the receiver starts reception  
when SMSYNx is asserted.  
When the buffer full, the SMC clears the E bit in the BD and generates an interrupt if the I  
bit in the BD is set. If incoming data exceeds the data buffer length, the SMC fetches the  
next BD; if it is empty, the SMC continues transferring data to this BDÕs buffer. If the CM  
bit is set in the RxBD, the E bit is not cleared, so the CP can automatically overwrite the  
buffer on its next access.  
26.4.4 Using SMSYN for Synchronization  
The SMSYN signal offers a way to externally synchronize the SMC channel. This method  
differs somewhat from the synchronization options available in the SCCs and should be  
studied carefully. See Figure 26-11 for an example.  
Once SMCMR[REN] is set, the Þrst rising edge of SMCLK that Þnds SMSYN low causes  
the SMC receiver to achieve synchronization. Data starts being received or latched on the  
same rising edge of SMCLK that latched SMSYN. This is the Þrst bit of data received. The  
receiver does not lose synchronization again, regardless of the state of SMSYN, until REN  
is cleared.  
Once SMCMR[TEN] is set, the Þrst rising edge of SMCLK that Þnds SMSYN low  
synchronizes the SMC transmitter which begins sending ones asynchronously from the  
falling edge of SMSYN. After one character of ones is sent, if the transmit FIFO is loaded  
(the TxBD is ready with data), data starts being send on the next falling edge of SMCLK  
after one character of ones is sent. If the transmit FIFO is loaded later, data starts being sent  
after some multiple number of all-ones characters is sent.  
Note that regardless of whether the transmitter or receiver uses SMSYN, it must make  
glitch-free transitions from high-to-low or low-to-high. Glitches on SMSYN can cause  
errant behavior of the SMC.  
The transmitter never loses synchronization again, regardless of the state of SMSYN, until  
the TEN bit is cleared or an ENTER HUNT MODE command is issued.  
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Part IV. Communications Processor Module  
SMCLK  
SMSYN  
SMTXD  
1s are sent  
Five 1s are sent  
SMC1 Transmit Data  
TEN set  
here  
SMSYN  
detected  
Tx FIFO  
loaded  
Five 1s  
assume  
First bit of  
first 5-bit  
transmit  
character  
(lsb)  
Transmission  
could begin  
here if Tx FIFO  
not loaded  
in time  
low here approximately character  
here  
length  
equals 5  
SMCLK  
SMSYN  
SMRXD  
SMC1 Receive Data  
REN set  
here or  
ENTER HUNT  
SMSYN  
detected  
low here  
First bit  
of receive  
data  
NOTES:  
1. SMCLK is an internal clock derived from an external  
CLKx or a baud rate generator.  
2. This example shows the SMC receiver and transmitter  
enabled separately. If the REN and TEN bits were set at  
the same time, a single falling edge of SMSYN would  
synchronize both.  
MODE  
(lsb)  
command  
issued  
Figure 26-11. Synchronization with SMSYNx  
If both SMCMR[REN] and SMCMR[TEN] are set, the Þrst falling edge of SMSYN causes  
both the transmitter and receiver to achieve synchronization. The SMC transmitter can be  
disabled and reenabled and SMSYN can be used again to resynchronize the transmitter  
itself. Section 26.2.4, ÒDisabling SMCs On-the-Fly,Ó describes how to safely disable and  
reenable the SMC. Simply clearing and setting TEN may be insufÞcient. The receiver can  
also be resynchronized this way.  
26.4.5 Using the Time-Slot Assigner (TSA) for Synchronization  
The TSA offers an alternative to using SMSYN to internally synchronize the SMC channel.  
This method is similar, except that the synchronization event is the Þrst time-slot for this  
SMC receiver/transmitter after the frame sync indication rather than the falling edge of  
SMSYN. Chapter 14, ÒSerial Interface with Time-Slot Assigner,Ó describes how to  
conÞgure time slots. The TSA allows the SMC receiver and transmitter to be enabled  
simultaneously and synchronized separately; SMSYN does not provide this capability.  
Figure 26-12 shows synchronization using the TSA.  
MOTOROLA  
Chapter 26. Serial Management Controllers (SMCs)  
26-23  
   
Part IV. Communications Processor Module  
TDM Tx CLK  
TDM Tx SYNC  
SMC1  
SMC1  
TDM Tx  
After TEN  
is set,  
transmission  
begins here.  
If SMC runs out of Tx buffers and new ones  
are provided later, transmission begins at  
the beginning of either time slot.  
TDM Rx CLK  
TDM Rx SYNC  
TDM Rx  
SMC1  
SMC1  
After REN is set or after  
ENTER HUNT MODE command,  
reception begins here.  
Figure 26-12. Synchronization with the TSA  
Once SMCMR[REN] is set, the Þrst time-slot after the frame sync causes the SMC receiver  
to achieve synchronization. Data is received immediately, but only during deÞned receive  
time slots. The receiver continues receiving data during its deÞned time slots until REN is  
cleared. If an ENTER HUNT MODE command is issued, the receiver loses synchronization,  
closes the buffer, and resynchronizes to the Þrst time slot after the frame sync.  
Once SMCMR[TEN] is set, the SMC waits for the transmit FIFO to be loaded before trying  
to achieve synchronization. When the transmit FIFO is loaded, synchronization and  
transmission begins depending on the following:  
¥
¥
¥
If a buffer is made ready when the SMC2 is enabled, the Þrst byte is placed in time  
slot 1 if CLSN is 8 and to slot 2 if CLSN is 16.  
If a buffer has its SMC enabled, then the Þrst byte in the next buffer can appear in  
any time slot associated with this channel.  
If a buffer is ended with the L bit set, then the next buffer can appear in any time slot  
associated with this channel.  
If the SMC runs out of transmit buffers and a new buffer is provided later, idles are sent in  
the gap between buffers. Data transmission from the later buffer begins at the start of an  
SMC time slot, but not necessarily the Þrst time slot after the frame sync. So, to maintain a  
certain bit alignment beginning with the Þrst time slot, make sure that at least one TxBD is  
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MOTOROLA  
 
Part IV. Communications Processor Module  
always ready and that underruns do not occur. Otherwise, the SMC transmitter should be  
disabled and reenabled. Section 26.2.4, ÒDisabling SMCs On-the-Fly,Ó describes how to  
safely disable and reenable the SMC. Simply clearing and setting TEN may not be enough.  
26.4.6 SMC Transparent Commands  
Table 26-10 describes transmit commands issued to the CPCR.  
Table 26-10. SMC Transparent Transmit Commands  
Command  
Description  
STOP  
After hardware or software is reset and the channel is enabled in the SMCM, the channel is in transmit  
enable mode and polls the Þrst BD. This command disables transmission of frames on the transmit  
channel. If the transparent controller receives this command while sending a frame, it stops after the  
contents of the FIFO are sent (up to 2 characters). The TBPTR is not advanced to the next BD, no new  
BD is accessed, and no new buffers are sent for this channel. The transmitter sends idles until a  
RESTART TRANSMIT command is issued.  
TRANSMIT  
RESTART  
TRANSMIT  
Starts or resumes transmission from the current TBPTR in the channel TxBD table. When the channel  
receives this command, it polls the R bit in this BD. The SMC expects this command after a STOP  
TRANSMIT is issued. The channel in its mode register is disabled or after a transmitter error occurs.  
INIT TX Initializes transmit parameters in this serial channel to reset state. Use only if the transmitter is  
PARAMETERS disabled. The INIT TX AND RX PARAMETERS command resets transmit and receive parameters.  
Table 26-11 describes receive commands issued to the CPCR.  
Table 26-11. SMC Transparent Receive Commands  
Command  
Description  
ENTER HUNT Forces the SMC to close the current receive BD if it is in use and to use the next BD for subsequent  
MODE  
data. If the SMC is not receiving data, the buffer is not closed. Additionally, this command causes the  
receiver to wait for a resynchronization before reception resumes.  
CLOSE RXBD Forces the SMC to close the current receive BD if it in use and to use the next BD in the list for  
subsequent received data. If the SMC is not in the process of receiving data, no action is taken.  
iNIT RX  
Initializes receive parameters in this serial channel to reset state. Use only if the receiver is disabled.  
PARAMETERS The INIT TX AND RX PARAMETERS command resets receive and transmit parameters.  
26.4.7 Handling Errors in the SMC Transparent Controller  
The SMC uses BDs and the SMCE to report message send and receive errors.  
Table 26-12. SMC Transparent Error Conditions  
Error  
Descriptions  
Underrun The channel stops sending the buffer, closes it, sets UN in the BD, and generates a TXE interrupt if it is  
enabled. The channel resumes sending after a RESTART TRANSMIT command. Underrun cannot occur  
between frames.  
Overrun The SMC maintains an internal FIFO for receiving data. If the buffer is in external memory, the CP begins  
programming the SDMA channel when the Þrst character is received into the FIFO. If a FIFO overrun  
occurs, the SMC writes the received data character over the previously received character. The previous  
character and its status bits are lost. Then the channel closes the buffer, sets OV in the BD, and generates  
the RXB interrupt if it is enabled. Reception continues as normal.  
MOTOROLA  
Chapter 26. Serial Management Controllers (SMCs)  
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Part IV. Communications Processor Module  
26.4.8 SMC Transparent RxBD  
Using BDs, the CP reports information about the received data for each buffer and closes  
the current buffer, generates a maskable interrupt, and starts to receive data into the next  
buffer after one of the following events:  
¥
¥
¥
An overrun error occurs.  
A full receive buffer is detected.  
The ENTER HUNT MODE command is issued.  
0
1
2
3
4
5
6
7
8
9
10  
Ñ
11  
12  
13  
14  
15  
Ñ
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
E
Ñ
W
I
Ñ
CM  
OV  
Data Length  
Rx Data Buffer Pointer  
Figure 26-13. SMC Transparent RxBD  
Table 26-13 describes SMC transparent RxBD Þelds.  
Table 26-13. SMC Transparent RxBD Field Descriptions  
Bits Name  
Description  
0
E
Empty.  
0 The buffer is full or reception was aborted due to an error. The core can read or write any Þelds of  
this RxBD. The CP does not use this BD while E = 0.  
1 The buffer is empty or is receiving data. The CP owns this RxBD and its buffer. Once E is set, the  
core should not write any Þelds of this RxBD.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (last BD in RxBD table).  
0 Not the last BD in the table.  
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the Þrst BD that  
RBASE points to. The number of RxBDs is determined only by the W bit and overall space  
constraints of the dual-port RAM.  
3
I
Interrupt.  
0 No interrupt is generated after this buffer is Þlled.  
1 SMCE[RXB] is set when the CP completely Þlls this buffer indicating that the core must process the  
buffer. The RXB bit can cause an interrupt if it is enabled.  
4Ð5  
6
Ñ
Reserved, should be cleared.  
CM  
Continuous mode.  
0 Normal operation.  
1 The CP does not clear E after this BD is closed, allowing the buffer to be overwritten when the CP  
next accesses this BD. However, E is cleared if an error occurs during reception, regardless of how  
CM is set.  
7Ð13  
14  
Ñ
Reserved, should be cleared.  
OV  
Overrun. Set when a receiver overrun occurs during reception. The CP writes OV after the received  
data is placed into the buffer.  
15  
Ñ
Reserved, should be cleared.  
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MPC8260 PowerQUICC II UserÕs Manual  
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Part IV. Communications Processor Module  
Data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer  
Descriptors (BDs).Ó  
26.4.9 SMC Transparent TxBD  
Data is sent to the CP for transmission on an SMC channel by arranging it in buffers  
referenced by the channel TxBD table. The CP uses BDs to conÞrm transmission or  
indicate error conditions so the processor knows buffers have been serviced.  
0
1
2
3
4
5
6
7
8
9
10  
Ñ
11  
12  
13  
14  
15  
Ñ
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
R
Ñ
W
I
L
Ñ
CM  
UN  
Data Length  
Tx Data Buffer Pointer  
Table 26-14. SMC Transparent TxBD  
Table 26-15 describes SMC transparent TxBD Þelds.  
Table 26-15. SMC Transparent TxBD Field Descriptions  
Bits Name  
Description  
0
R
Ready.  
0 The buffer is not ready for transmission. The BD and buffer can be updated. The CP clears R after  
the buffer is sent or after an error occurs.  
1 The user-prepared data buffer is not sent or is being sent. BD Þelds cannot be updated if R is set.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (Þnal BD in table).  
0 Not the last BD in the table.  
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the Þrst BD that  
TBASE points to. The number of TxBDs in this table is programmable and determined by theW bit  
and overall space constraints of the dual-port RAM.  
3
4
I
Interrupt.  
0 No interrupt is generated after this buffer is serviced.  
1 SMCE[TXB] or SMCE[TXE] are set when the buffer is serviced.They can cause interrupts if they are  
enabled.  
L
Last in message.  
0 The last byte in the buffer is not the last byte in the transmitted transparent frame. Data from the next  
transmit buffer (if ready) is sent immediately after the last byte of this buffer.  
1 The last byte in this buffer is the last byte in the transmitted transparent frame. After this buffer is  
sent, the transmitter requires synchronization before the next buffer is sent.  
5
6
Ñ
Reserved, should be cleared.  
CM Continuous mode.  
0 Normal operation.  
1 The CP does not clear R after this BD is closed, allowing the buffer to be automatically resent when  
the CP accesses this BD again. However, the R bit is cleared if an error occurs during transmission,  
regardless of how CM is set.  
7Ð13  
14  
Ñ
Reserved, should be cleared.  
UM Underrun. Set when the SMC encounters a transmitter underrun condition while sending the buffer.  
Reserved, should be cleared.  
15  
Ñ
MOTOROLA  
Chapter 26. Serial Management Controllers (SMCs)  
26-27  
       
Part IV. Communications Processor Module  
Data length represents the number of octets the CP should transmit from this buffer. It is  
never modiÞed by the CP. The data length can be even or odd, but if the number of bits in  
the transparent character is greater than 8, the data length should be even. For example, to  
transmit three transparent 8-bit characters, the data length Þeld should be initialized to 3.  
However, to transmit three transparent 9-bit characters, the data length Þeld should be  
initialized to 6 because the three 9-bit characters occupy three half words in memory.  
The data buffer pointer points to the Þrst byte of the buffer. They can be even or odd, unless  
character length is greater than 8 bits, in which case the transmit buffer pointer must be  
even. For instance, the pointer to 8-bit transparent characters can be even or odd, but the  
pointer to 9-bit transparent characters must be even. The buffer can reside in internal or  
external memory.  
26.4.10 SMC Transparent Event Register (SMCE)/Mask Register  
(SMCM)  
The SMC event register (SMCE) generates interrupts and reports events recognized by the  
SMC channel. When an event is recognized, the SMC sets the corresponding SMCE bit.  
Interrupts are masked in the SMCM, which has the same format as the SMCE. SMCE bits  
are cleared by writing a 1 (writing 0 has no effect). Unmasked bits must be cleared before  
the CP clears the internal interrupt request.  
Bit  
Field  
0
1
2
3
4
5
6
7
Ñ
TXE  
Ñ
BSY  
TXB  
RXB  
Reset  
R/W  
0
R/W  
Address  
0x11A86 (SMCE1), 0x11A96 (SMCE2)/ 0x11A8A (SMCM1), 0x11A9A (SMCM2)  
Figure 26-14. SMC Transparent Event Register (SMCE)/Mask Register (SMCM)  
Table 26-16 describes SMCE/SMCM Þelds.  
Table 26-16. SMCE/SMCM Field Descriptions  
Bits Name  
Description  
0Ð2  
3
Ñ
Reserved, should be cleared.  
TXE  
Ñ
Tx error. Set when an underrun error occurs on the transmitter channel.  
Reserved, should be cleared.  
4
5
BSY  
Busy condition. Set when a character is received and discarded due to a lack of buffers. Reception  
begins after a new buffer is provided. Executing an ENTER HUNT MODE command makes the receiver  
wait for resynchronization.  
6
7
TXB  
RXB  
Tx buffer. Set after a buffer is sent. If the L bit of the TxBD is set, TXB is set when the last character  
starts being sent. A one character-time delay is required to ensure that data is completely sent over the  
transmit signal. If the L bit of the TxBD is cleared, TXB is set when the last character is written to the  
transmit FIFO. A two character-time delay is required to ensure that data is completely sent.  
Rx buffer. Set when a buffer is received (after the last character is written) on the SMC channel and its  
associated RxBD is now closed.  
26-28  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part IV. Communications Processor Module  
26.4.11 SMC Transparent NMSI Programming Example  
The following example initializes the SMC1 transparent channel over its own set of signals.  
The CLK9 signal supplies the transmit and receive clocks; the SMSYNx signal is used for  
synchronization. (The SMC UART programming example uses a BRG conÞguration; see  
Section 26.3.12, ÒSMC UART Controller Programming Example.Ó)  
1. ConÞgure the port D pins to enable SMTXD1, SMRXD1, and SMSYN1. Set  
PPARD[7,8,9] and PDIRD[9]. Clear PDIRD[7,8] and PSORD[7,8,9].  
2. ConÞgure the port C pins to enable CLK9. Set PPARC[23]. Clear PDIRC[23] and  
PSORC[23].  
3. Connect CLK9 to SMC1 using the CPM mux. Clear CMXSMR[SMC1] and  
program CMXSMR[SMC1CS] to 0b11.  
4. In address 0x87FC, assign a pointer to the SMC1 parameter RAM.  
5. Write RBASE and TBASE in the SMC parameter RAM to point to the RxBD and  
TxBD in the dual-port RAM. Assuming one RxBD at the beginning of the dual-port  
RAM followed by one TxBD, write RBASE with 0x0000 and TBASE with 0x0008.  
6. Write 0x1D01_0000 to CPCR to execute the INIT RX AND TX PARAMETERS  
command.  
7. Write RFCR and TFCR with 0x10 for normal operation.  
8. Write MRBLR with the maximum bytes per receive buffer. Assuming 16 bytes  
MRBLR = 0x0010.  
9. Initialize the RxBD assuming the buffer is at 0x0000_1000 in main memory. Write  
0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional),  
and 0x0000_1000 to RxBD[Buffer Pointer].  
10.Initialize the TxBD assuming the Tx buffer is at 0x0000_2000 in main memory and  
contains Þve 8-bit characters. Write 0xB800 to TxBD[Status and Control], 0x0005  
to TxBD[Data Length], and 0x0000_2000 to TxBD[Buffer Pointer].  
11.Write 0xFF to SMCE1 to clear any previous events.  
12.Write 0x13 to SMCM1 to enable all possible SMC1 interrupts.  
13.Write 0x0000_1000 to the SIU interrupt mask register low (SIMR_L) so the SMC1  
can generate a system interrupt. Write 0xFFFF_FFFF to the SIU interrupt pending  
register low (SIPNR_L) to clear events.  
14.Write 0x3830 to the SMCMR to conÞgure 8-bit characters, unreversed data, and  
normal operation (not loopback). The transmitter and receiver are not enabled yet.  
15.Write 0x3833 to the SMCMR to enable the SMC transmitter and receiver. This  
additional write ensures that TEN and REN are enabled last.  
After 5 bytes are sent, the TxBD is closed; after 16 bytes are received the receive buffer is  
closed. Any data received after 16 bytes causes a busy (out-of-buffers) condition since only  
one RxBD is prepared.  
MOTOROLA  
Chapter 26. Serial Management Controllers (SMCs)  
26-29  
   
Part IV. Communications Processor Module  
26.5 The SMC in GCI Mode  
The SMC can control the C/I and monitor channels of the GCI frame. When using the SCIT  
conÞguration of a GCI, one SMC can handle SCIT channel 0 and the other can handle SCIT  
channel 1. The main features of the SMC in GCI mode are as follows:  
¥
Each SMC channel supports the C/I and monitor channels of the GCI (IOM-2) in  
ISDN applications  
¥
¥
¥
Two SMCs support both sets of C/I and monitor channels in SCIT channels 0 and 1  
Full-duplex operation  
Local loopback and echo capability for testing  
To use the SMC GCI channels properly, the TSA must be conÞgured to route the monitor  
and C/I channels to the preferred SMC. Chapter 14, ÒSerial Interface with Time-Slot  
Assigner,Ó describes how to program this conÞguration. GCI mode is selected by setting  
SMCMR[SM] to 0b10. Section 26.2.1, ÒSMC Mode Registers (SMCMR1/SMCMR2)Ó  
describes other protocol-speciÞc SMCMR bits.  
26.5.1 SMC GCI Parameter RAM  
The GCI parameter RAM differs from that for UART and transparent mode. The CP  
accesses each SMCÕs GCI parameter table using a user-programmed pointer  
(SMCx_BASE) located in the parameter RAM; see Section 13.5.2, ÒParameter RAM.Ó  
Each SMC GCI parameter RAM table can be placed at any 64-byte aligned address in the  
dual-port RAMÕs general-purpose area (banks #1Ð#8). In GCI mode, parameter RAM  
contains the BDs instead of pointers to them. Compare Table 26-17 with Table 26-2 to see  
the differences. (In GCI mode, the SMC has no extra protocol-speciÞc parameter RAM.)  
Table 26-17. SMC GCI Parameter RAM Memory Map  
1
Offset  
Name  
Width  
Description  
0x00  
0x02  
0x04  
0x06  
0x08  
0x0C  
0x0E  
0x10  
0x12  
M_RxBD  
M_TxBD  
CI_RxBD  
CI_TxBD  
Half word Monitor channel RxBD. See Section 26.5.5, ÒSMC GCI Monitor Channel RxBD.Ó  
Half word Monitor channel TxBD. See Section 26.5.6, ÒSMC GCI Monitor Channel TxBD.Ó  
Half word C/I channel RxBD. See Section 26.5.7, ÒSMC GCI C/I Channel RxBD.Ó  
Half word C/I channel TxBD. See Section 26.5.8, ÒSMC GCI C/I Channel TxBD.Ó  
2
RSTATE  
Word  
Rx/Tx Internal State  
2
M_RxD  
Half word Monitor Rx Data  
Half word Monitor Tx Data  
Half word C/I Rx Data  
Half word C/I Tx Data  
2
M_TxD  
2
CI_RxD  
2
CI_TxD  
1
2
From the pointer value programmed in SMCx_BASE: SMC1_BASE at 0x87FC, SMC2_BASE at 0x88FC.  
RSTATE, M_RxD, M_TxD, CI_RxD, and CI_TxD do not need to be accessed by the user in normal operation,  
and are reserved for RISC use only.  
26-30  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
             
Part IV. Communications Processor Module  
26.5.2 Handling the GCI Monitor Channel  
The following sections describe how the GCI monitor channel is handled.  
26.5.2.1 SMC GCI Monitor Channel Transmission Process  
Monitor channel 0 is used to exchange data with a layer 1 device (reading and writing  
internal registers and transferring of the S and Q bits). Monitor channel 1 is used for  
programming and controlling voice/data modules such as CODECs. The core writes the  
byte into the TxBD. The SMC sends the data on the monitor channel and handles the A and  
E control bits according to the GCI monitor channel protocol. The TIMEOUT command  
resolves deadlocks when errors in the A and E bit states occur on the data line.  
26.5.2.2 SMC GCI Monitor Channel Reception Process  
The SMC receives data and handles the A and E control bits according to the GCI monitor  
channel protocol. When the CP stores a received data byte in the SMC RxBD, a maskable  
interrupt is generated. A TRANSMIT ABORT REQUEST command causes the MPC8260 to  
send an abort request on the E bit.  
26.5.3 Handling the GCI C/I Channel  
The C/I channel is used to control the layer 1 device. The layer 2 device in the TE sends  
commands and receives indication to or from the upstream layer 1 device through C/I  
channel 0. In the SCIT conÞguration, C/I channel 1 is used to convey real-time status  
information between the layer 2 device and nonlayer 1 peripheral devices (CODECs).  
26.5.3.1 SMC GCI C/I Channel Transmission Process  
The core writes the data byte into the C/I TxBD and the SMC transmits the data  
continuously on the C/I channel to the physical layer device.  
26.5.3.2 SMC GCI C/I Channel Reception Process  
The SMC receiver continuously monitors the C/I channel. When it recognizes a change in  
the data and this value is received in two successive frames, it is interpreted as valid data.  
This is called the double last-look method. The CP stores the received data byte in the C/I  
RxBD and a maskable interrupt is generated. If the SMC is conÞgured to support SCIT  
channel 1, the double last-look method is not used.  
MOTOROLA  
Chapter 26. Serial Management Controllers (SMCs)  
26-31  
                   
Part IV. Communications Processor Module  
26.5.4 SMC GCI Commands  
The commands in Table 26-18 are issued to the CPCR.  
Table 26-18. SMC GCI Commands  
Command  
Description  
INIT TX AND RX  
PARAMETERS  
Initializes transmit and receive parameters in the parameter RAM to their reset state. It is  
especially useful when switching protocols on a given serial channel.  
TRANSMIT This receiver command can be issued when the MPC8260 implements the monitor channel  
ABORT REQUEST protocol. When it is issued, the MPC8260 sends an abort request on the A bit.  
TIMEOUT  
This transmitter command can be issued when the MPC8260 implements the monitor channel  
protocol. It is usually issued because the device is not responding or A bit errors are detected.The  
MPC8260 sends an abort request on the E bit at the time this command is issued.  
26.5.5 SMC GCI Monitor Channel RxBD  
This BD is used by the CP to report information about the monitor channel receive byte.  
0
1
l
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0  
E
ER MS  
Ñ
DATA  
Figure 26-15. SMC Monitor Channel RxBD  
Table 26-19 describes SMC monitor channel RxBD Þelds.  
Table 26-19. SMC Monitor Channel RxBD Field Descriptions  
Bits Name  
Description  
0
E
Empty.  
0 The CP clears E when the byte associated with this BD is available to the core.  
1 The core sets E when the byte associated with this BD has been read.  
1
2
3
L
Last (EOM). Valid only for monitor channel protocol and is set when the EOM indication is received on  
the E bit. Note that when this bit is set, the data byte is invalid.  
ER Error condition. Valid only for monitor channel protocol. Set when an error occurs on the monitor  
channel protocol. A new byte is sent before the SMC acknowledges the previous byte.  
MS Data mismatch. Valid only for monitor channel protocol. Set when two different consecutive bytes are  
received; cleared when the last two consecutive bytes match. The SMC waits for the reception of two  
identical consecutive bytes before writing new data to the RxBD.  
4Ð7  
Ñ
Reserved, should be cleared.  
8Ð15 DATA Data Þeld. Contains the monitor channel data byte that the SMC received.  
26.5.6 SMC GCI Monitor Channel TxBD  
The CP uses this BD to report about the monitor channel transmit byte.  
0
1
L
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0  
R
AR  
Ñ
DATA  
Figure 26-16. SMC Monitor Channel TxBD  
26-32  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
                   
Part IV. Communications Processor Module  
Table 26-20 describes SMC monitor channel TxBD Þelds.  
Table 26-20. SMC Monitor Channel TxBD Field Descriptions  
Bits Name  
Description  
0
R
Ready.  
0 Cleared by the CP after transmission. The TxBD is now available to the core.  
1 Set by the core when the data byte associated with this BD is ready for transmission.  
1
L
Last (EOM). Valid only for monitor channel protocol. When L = 1, the SMC Þrst transmits the buffer  
data and then transmits the EOM indication on the E bit.  
2
AR  
Ñ
Abort request. Valid only for monitor channel protocol. Set by the SMC when an abort request is  
received on the A bit. The transmitter sends the EOM on the E bit after receiving an abort request.  
3Ð7  
Reserved, should be cleared.  
8Ð15 DATA Data Þeld. Contains the data to be sent by the SMC on the monitor channel.  
26.5.7 SMC GCI C/I Channel RxBD  
The CP uses this BD to report information about the C/I channel receive byte.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0  
E
Ñ
C/I DATA  
Ñ
Figure 26-17. SMC C/I Channel RxBD  
Table 26-21 describes SMC C/I channel RxBD Þelds  
Table 26-21. SMC C/I Channel RxBD Field Descriptions  
Bits  
Name  
Description  
0
E
Empty.  
0 Cleared by the CP to indicate that the byte associated with this BD is available to the core.  
1 The core sets E to indicate that the byte associated with this BD has been read.  
Note that additional data received is discarded until E bit is set.  
1Ð7  
Ñ
Reserved, should be cleared.  
8Ð13 C/I DATA Command/indication data bits. For C/I channel 0, bits 10Ð13 contain the 4-bit data Þeld and bits 8Ð  
9 are always written with zeros. For C/I channel 1, bits 8Ð13 contain the 6-bit data Þeld.  
14Ð15  
Ñ
Reserved, should be cleared.  
26.5.8 SMC GCI C/I Channel TxBD  
The CP uses this BD to report about the C/I channel transmit byte.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0  
R
Ñ
C/I DATA  
Ñ
Figure 26-18. SMC C/I Channel TxBD  
MOTOROLA  
Chapter 26. Serial Management Controllers (SMCs)  
26-33  
               
Part IV. Communications Processor Module  
Table 26-22 describes SMC C/I channel TxBD Þelds.  
Table 26-22. SMC C/I Channel TxBD Field Descriptions  
Bits  
Name  
Description  
0
R
Ready.  
0 Cleared by the CP after transmission to indicate that the BD is available to the core.  
1 Set by the core when data associated with this BD is ready for transmission.  
1Ð7  
Ñ
Reserved, should be cleared.  
8Ð13 C/I DATA Command/indication data bits. For C/I channel 0, bits 10Ð13 hold the 4-bit data Þeld (bits 8 and 9  
are always written with zeros). For C/I channel 1, bits 8Ð13 contain the 6-bit data Þeld.  
14Ð15  
Ñ
Reserved, should be cleared.  
26.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM)  
The SMCE generates interrupts and report events recognized by the SMC channel. When  
an event is recognized, the SMC sets its corresponding SMCE bit. SMCE bits are cleared  
by writing ones; writing zeros has no effect. SMCM has the same bit format as SMCE.  
Setting an SMCM bit enables, and clearing an SMCM bit disables, the corresponding  
interrupt. Unmasked bits must be cleared before the CP clears the internal interrupt request  
to the SIU interrupt controller.  
Bit  
Field  
0
1
2
3
4
5
6
7
Ñ
CTXB  
CRXB  
MTXB  
MRXB  
Reset  
R/W  
0000_0000  
R/W  
Address  
0x11A86 (SMCE1), 0x11A96 (SMCE2)/ 0x11A8A (SMCM1), 0x11A9A (SMCM2)  
Figure 26-19. SMC GCI Event Register (SMCE)/Mask Register (SMCM)  
Table 26-23 describes SMCE/SMCM Þelds.  
Table 26-23. SMCE/SMCM Field Descriptions  
Bits Name  
Description  
0Ð3  
4
Ñ
Reserved, should be cleared.  
CTXB C/I channel buffer transmitted. Set when the C/I transmit buffer is now empty.  
CRXB C/I channel buffer received. Set when the C/I receive buffer is full.  
5
6
MTXB Monitor channel buffer transmitted. Set when the monitor transmit buffer is now empty.  
MRXB Monitor channel buffer received. Set when the monitor receive buffer is full.  
7
26-34  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
           
Chapter 27  
Multi-Channel Controllers (MCCs)  
270  
2T70 he MPC8260Õs two multi-channel controllers (MCC1 and MCC2) each handle up to 128  
serial, full-duplex data channels. The 128 channels are divided into four subgroups (of 32  
channels each). One or more subgroups can be multiplexed through corresponding SIx  
TDM channels; MCC1 connects through SI1, and MCC2 uses SI2.  
Each channel can be programmed separately either to perform HDLC formatting/  
deformatting or to act as a transparent channel.  
27.1 Features  
Each MCC has the following features:  
¥
¥
¥
¥
¥
Up to 128 independent communication channels.  
Independent mapping for receive/transmit.  
Supports either transparent or HDLC protocols for each channel.  
Up to 256 DMA channels with independent buffer descriptor (BD) tables.  
Five interrupt circular tables with programmable size and overßow identiÞcation.  
One for transmit and four for receive.  
¥
¥
¥
Global loop mode.  
Individual channel loop mode.  
EfÞcient bus usage (no bus usage for inactive channel or for active channels with  
nothing to transmit).  
¥
¥
¥
¥
¥
¥
¥
¥
EfÞcient control of the interrupts to the core.  
Supports external BD tables.  
Uses on-chip dual-port RAM (DPR) for parameter storage.  
Uses 64-bit data transactions for reading and writing data in BDs.  
Supports automatic routing in transparent mode using negative empty polarity.  
Supports inverted data per channel.  
Supports super channel synchronization in transparent mode (slot synchronization).  
Supports in-line synchronization in transparent mode (synchronization on a pattern  
of 2 bytes).  
MOTOROLA  
Chapter 27. Multi-Channel Controllers (MCCs)  
27-1  
       
Part IV. Communications Processor Module  
27.2 MCC Data Structure Organization  
Each MCC uses the following data structures:  
¥
¥
Global MCC parameters (common to all the 128 channels) placed in the DPR from  
the offset (relative to the DPR base address) deÞned in Table 13-10.  
Channel-speciÞc parameters. Each channel use 64 bytes of speciÞc parameters  
placed in the DPR at offset 64*CH_NUM (relative to the DPR base address).  
CH_NUM is the channel number (0Ð127 for MCC1 and 128Ð255 for MCC2).  
Channel-speciÞc parameters are described in Section 27.6, ÒChannel-SpeciÞc  
HDLC Parameters,Ó and Section 27.7, ÒChannel-SpeciÞc Transparent Parameters.Ó  
Note that the DPR memory corresponding to the inactive channels can be used for  
other purposes.  
¥
Channel extra parameters. Each channel use 8 bytes of extra parameters placed in  
the DPR at offset XTRABASE + 8*CH_NUM (relative to the DPR base address).  
XTRABASE is one of the global MCC parameters.  
Channel extra parameters are described in Section 27.4, ÒChannel Extra  
Parameters.Ó Note that the DPR memory corresponding to the inactive channels can  
be used for other purposes.  
¥
¥
Super channel table (used only if super channels are deÞned). This table is placed in  
the DPR from the offset SCTPBASE (relative to the DPR base address).  
SCTPBASE is one of the global MCC parameters. The super channel tale is  
described in Section 27.5, ÒSuper-Channel Table.Ó  
BD tables placed in the external memory. All the BD tables associated with one  
MCC must reside in a 512-KByte segment. The absolute base addresses of a channel  
BD table is MCCBASE + 8*RBASE (for the receiver) and MCCBASE + 8*TBASE  
(for the transmitter). MCCBASE is one of the global MCC parameters and RBASE/  
TBASE are channel extra parameters. Each BD table is a circular queue. One BD  
includes status bits, start address and length of a data buffer. Figure 27-1 shows the  
BD structure for one MCC.  
¥
¥
Circular interrupt tables placed in the external memory. There is one table for the  
transmitter interrupts (base address TINTBASE) and between one and four tables  
for receiver interrupts (base address RINTBASE0ÐRINTBASE4). TINTBASE and  
RINTBASE0ÐRINTBASE4 are global MCC parameters.  
Three registers (MCCE, MCCM, and MCCF) at described in Section 27.10.1,  
ÒMCC Event Register (MCCE)/Mask Register (MCCM),Ó and Section 27.8, ÒMCC  
ConÞguration Registers (MCCFx).Ó  
27-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
Buffer Descriptor  
Table Base Address  
External Memory  
DPR  
DPR_base  
Channel 0 Parameter  
Channel 1 Parameter  
x8  
Channel j Extra  
Parameter  
RBASE  
TBASE  
+
Channel j RxBD  
Table  
512 Kbytes  
Global MCC  
Parameters  
MCCBASE  
x8  
+
Channel j TxBD  
Table  
Figure 27-1. BD Structure for One MCC  
27.3 Global MCC Parameters  
The global MCC parameters are described in Table 27-1.  
Table 27-1. Global Multiple-Channel Parameters  
1
Offset  
Name  
Width  
Description  
0x00  
MCCBASE Word Multi-channel controller base pointer. User-initialized parameter points to the starting  
address of a 512-Kbyte BD segment in external memory.  
0x04  
0x06  
MCCSTATE Hword Multi-channel controller state, used by the CP for global state deÞnition (reserved for  
the user)  
MRBLR  
Hword Maximum receive buffer length (user-initialized). DeÞnes the maximum number of  
bytes written to a receive buffer before moving to the next buffer for this channel.  
This value must be a multiple of 8.  
0x08  
GRFTHR  
Hword Global receive frame threshold. Used to reduce interrupt overhead that can occur  
when many short HDLC frames arrive that each cause an RXF interrupt. Setting all  
bits enables every interrupt event. Setting a GRFTHR value can limit the frequency  
of RXF interrupts. Note that an RXF event is written to the interrupt queue on each  
received frame but GINT is set only when the number of RXF events (by all  
channels) reaches the GRFTHR value. This parameter does not need to be reset  
after an interrupt.  
0x0A  
GRFCNT  
Hword Global receive frame count. A decrementor counter used to implement the GRFTHR  
feature. It should be initialized to the GRFTHR value. Setting all bits enables every  
interrupt event. The CP writes an entry in a circular interrupt table and decrements  
GRFCNT each time a frame is received. When GRFCNT underßows the CP  
generates an interrupt and copy GRFTHR to GRFCNT. This parameter does not  
need to be reset after an interrupt.  
MOTOROLA  
Chapter 27. Multi-Channel Controllers (MCCs)  
27-3  
       
Part IV. Communications Processor Module  
Table 27-1. Global Multiple-Channel Parameters (Continued)  
1
Offset  
Name  
Width  
Description  
0x0C  
RINTTMP  
Word Temporary location for holding the receive interrupt queue entry, used by the CP  
(reserved for the user)  
0x10  
0x14  
0x18  
DATA0  
DATA1  
Word Temporary location for holding data, used by the CP (reserved for the user)  
Word Temporary location for holding data, used by the CP (reserved for the user)  
TINTBASE Word Multi-channel transmitter circular interrupt table base address. The interrupt circular  
table is a cyclic table (FIFO-like). Each table entry contains information about an  
interrupt request generated by the MCC to the host.  
0x1C  
0x20  
TINTPTR  
Word Pointer to the transmitter circular interrupt table. The CP writes the next interrupt  
information to this entry when an exception occurs. The user must copy the  
TINTBASE value to TINTPTR before enabling interrupts. Further updates of the  
TINTPTR are done by the CP.  
TINTTMP  
Word Temporary location for holding the transmit interrupt queue entry, used by the CP.  
The 60x initializes this Þeld before initializing the MCC. The user must clear it before  
enabling interrupts.  
0x24  
0x26  
0x28  
SCTPBASE Hword Internal pointer for the super channel transmit table, offset from the DPRAM address  
Hword  
Ñ
C_MASK32 Word CRC constant (user initialized to 0xDEBB20E3). Used for 32-bit CRC-CCITT  
calculation if HDLC mode is chosen for a selected channel. (This option is  
programmable. For each HDLC channel, one of two CRC-CCITT can be selected  
through the CHAMR.)  
0x2C  
0x2E  
XTRABASE Hword Pointer the beginning of the extra parameters information, offset from the DPRAM  
address  
C_MASK16 Hword CRC constant (user initialized to 0xF0B8). Used for 16-bit CRC-CCITT calculation if  
HDLC mode is chosen for a selected channel. This option is programmable. For  
each HDLC channel, one of two CRC-CCITT can be selected through the CHAMR.  
0x30  
0x34  
0x38  
0x3C  
0x40  
0x44  
0x48  
0x4C  
0x50  
0x54  
0x58  
0x5C  
0x60  
RINTTMP0 Word RINTTMPx.Temporary location for holding a receive circular interrupt table entry (for  
tables 0Ð4), used by the CP. The user must clear it before enabling interrupts.See  
RINTTMP1 Word  
Section 27.10, ÒMCC Exceptions.Ó  
RINTTMP2 Word  
RINTTMP3 Word  
RINTBASE0 Word RINTBASExÑMulti-channel receiver circular interrupt table base address. The  
interrupt circular table is a cyclic table (FIFO-like). Each table entry contains  
RINTPTR0 Word  
information about an interrupt request generated by the MCC to the host.  
RINTPTRxÑPointer to the receiver circular interrupt table. The CP writes the next  
RINTBASE1 Word  
interrupt information to this entry when an exception occurs. The user must copy the  
RINTBASEx value to RINTPTRx before enabling interrupts. Further updates of the  
RINTPTRx are done by the CP.  
RINTPTR1 Word  
RINTBASE2 Word  
RINTPTR2 Word  
RINTBASE3 Word  
RINTPTR3 Word  
TS_TMP  
Offset to MCC Base  
Word Temporary place for time stamp  
1
27-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part IV. Communications Processor Module  
27.4 Channel Extra Parameters  
Table 27-2 describes extra parameters. This table is indexed by logical channel number.  
Table 27-2. Channel Extra Parameters  
1
Offset  
Name Width  
Description  
0x00  
TBASE Hword TxBD base address. Offset of the channelÕs TxBD table relative to the MCCBASE (The  
base address of the BD table for this channel MCCBASE+8*TBASE)  
0x02  
TBPTR Hword TxBD pointer. Offset of the current BD relative to the MCCBASE.TBPTR is user-initialized  
to TBASE before enabling the channel or after a fatal error before reinitializing the  
channel. (The address of the BD in use for this channel MCCBASE+8*TBPTR)  
0x04  
0x06  
RBASE Hword RxBD base address. Offset of the channelÕs RxBD table relative to the MCCBASE. (The  
base address of the BD table for this channel MCCBASE+8*RBASE)  
RBPTR Hword RxBD pointer. Offset of the current BD relative to the MCCBASE. RBPTR is user-  
initialized to RBASE before enabling the channel or after a fatal error before reinitializing  
the channel. (The address of the BD in use for this channel MCCBASE+8*RTBPTR)  
1
The offset relative to dual-port RAM base address + XTRABASE + 8*CH_NUM  
27.5 Super-Channel Table  
The super channel t able entry redirects an MCC slot to a different channel number. For this  
reason, the transmitter super channel uses more FIFO (2 bytesÑhalf of a single channel  
transmitter FIFOÑmultiplied by the number of the channels in the super channel) in the  
MCC hardware.  
On the transmitter side, super channels must be deÞned in the SI RAM (see Section 14.4.3,  
ÒProgramming SIx RAM Entries,Ó for details) and a super-channel table must be created.  
On the receiver side, the transparent super channels that require slot synchronization must  
be programmed in the SI RAM as super channels (the slot synchronization ensures that the  
data is aligned in the receiver buffer starting from the Þrst time slot after a sync pulse). In  
this case, 1 byte of FIFO is allocated for each super channel. Transparent super channels  
that do not require slot synchronization and HDLC super channels can be programmed in  
the SI RAM as regular channels pointing to the same MCC channel. In this case the FIFO  
allocated for each super channel is 2 bytes (and the CP load will be lower).  
Bits  
Field  
0
0
1
0
2
3
4
5
6
7
8
9
10  
0
11  
0
12  
0
13  
0
14  
0
15  
0
Channel Number  
Address  
DPR_base_address+SCTPBASE+2*Virtual_Channel_Number  
(Virtual_channel_number is the number written in the MCSEL Þeld of the corresponding SI RAM entry)  
Figure 27-2. Super Channel Table Entry  
The example in Figure 27-3 shows the SI RAM programming and the super-channel table  
for two transmitter super channels, one including slots 1, 6, and 7 and the second 2, 3, and  
4. Figure 27-4 shows the SI RAM programming for the same transparent receiver super  
MOTOROLA  
Chapter 27. Multi-Channel Controllers (MCCs)  
27-5  
             
Part IV. Communications Processor Module  
channels which uses the slot synchronization. Figure 27-5 shows the SI RAM  
programming for the same transparent or HDLC receiver super channels that do not use slot  
synchronization.  
SI RAM  
3Ð10  
Super Channel Table  
0
1
2
11Ð13  
CNT  
14  
15  
0Ð1  
2Ð9  
10Ð15  
MCC LOOP SUPER MCSEL  
SI RAM Address  
BYT LST  
CHANNEL NO  
DPR_Base + SCTPBASE +  
Ñ
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0x0  
0x1  
0x2  
0x3  
0x4  
0x5  
0x6  
0x7  
0x8  
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
0x1  
0x0  
0x2  
0x4  
0x6  
0x8  
0xA  
0xC  
0xE  
0x10  
1
0x1  
0x2  
0x2  
0x2  
Ñ
0x0  
2
0x0  
2
0x7  
2
0x7  
0x1  
2
0x1  
0x1  
Ñ
0x7  
2
0x7  
0x1  
1
2
First slot of the super channel  
Regular (not Þrst) slot of the super channel  
.
The super channel BD tables are associated with channels 1 and 2 (no BD tables are necessary for  
channels 3, 4, 6, and 7)  
Figure 27-3. Transmitter Super Channel Example  
The example in Figure 27-5 shows a receiver super channel with slot synchronization.  
27-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
SI RAM  
3Ð10  
0
1
2
11Ð13  
CNT  
14  
15  
MCC LOOP SUPER MCSEL  
SI RAM Address  
BYT LST  
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0x0  
0x1  
0x2  
0x2  
0x2  
0x3  
0x1  
0x1  
0x1  
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
Regular Channel  
Super Channel 1  
Super Channel 2  
Super Channel 2  
Super Channel 2  
Regular Channel  
Super Channel 1  
Super Channel 1  
Regular Channel  
0x1  
1
0x0  
1
0x0  
2
0x7  
2
0x7  
0x1  
2
0x7  
2
0x7  
0x1  
1
2
First slot of the super channel  
Regular (not Þrst) slot of the super channel  
The super channel BD tables are associated with channels 1 and 2  
Figure 27-4. Receiver Super Channel with Slot Synchronization Example  
The example in Figure 27-5 shows a receiver super channel without slot synchronization.  
SI RAM  
0
1
2
3Ð10  
11Ð13  
CNT  
14  
15  
MCC LOOP SUPER MCSEL  
SI RAM Address  
BYT LST  
1
0
0
0x0  
1
0
Regular Channel  
0x1  
0x1  
0x1  
0x1  
0x1  
0x1  
0x1  
0x1  
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x1  
0x2  
0x2  
0x2  
0x3  
0x1  
0x1  
0x4  
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
Super Channel 1  
Super Channel 2  
Super Channel 2  
Super Channel 2  
Regular Channel  
Super Channel 1  
Super Channel 1  
Regular Channel  
0x1  
The super channel BD tables are associated with channels 1 and 2  
Figure 27-5. Receiver Super Channel without Slot Synchronization Example  
MOTOROLA  
Chapter 27. Multi-Channel Controllers (MCCs)  
27-7  
       
Part IV. Communications Processor Module  
27.6 Channel-SpeciÞc HDLC Parameters  
Table 27-3 describes channel-speciÞc parameters for HDLC.  
Table 27-3. Channel-Specific Parameters for HDLC  
1
Offset  
Name  
Width  
Description  
0x00  
TSTATE  
Word Tx internal state. To start a transmitter channel the user must write to TSTATE  
0xHH80_0000. HH is the TSTATE high byte described in Section 27.6.1, ÒInternal  
Transmitter State (TSTATE).Ó  
0x04  
ZISTATE Word Zero-insertion machine state.(User-initialized to 0x10000207 for regular channel, and  
0x30000207 for inverted channel)  
0x08  
0x0C  
0x10  
0x12  
ZIDATA0 Word Zero-insertion high word data buffer (User-initialized to 0xFFFFFFFF)  
ZIDATA1 Word Zero-insertion low word data buffer (User-initialized to 0xFFFFFFFF)  
TBDFlags Hword TxDB ßags, used by the CP (read-only for the user)  
TBDCNT Hword Tx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only  
for the user)  
0x14  
TBDPTR Word Tx internal data pointer. Points to current absolute data address of channel, used by the  
CP (read-only for the user)  
0x18  
0x1A  
0x1C  
INTMSK  
CHAMR  
TCRC  
Hword ChannelÕs interrupt mask ßag. See Section 27.6.2, ÒInterrupt Mask (INTMSK).Ó  
Hword Channel mode register. See Section 27.6.3, ÒChannel Mode Register (CHAMR).Ó  
Word Temp transmit CRC.Temp value of CRC calculation result, used by the CP (read-only for  
the user)  
0x20  
0x24  
RSTATE  
Word Rx internal state. To start a receiver channel the user must write to RSTATE  
0xHH80_0000. HH is the RSTATE high byte described in Section 27.6.4, ÒInternal  
Receiver State (RSTATE).Ó  
ZDSTATE Word Zero-deletion machine state (User-initialized to 0x00FFFFE0 for regular channel and  
0x20FFFFE0 for inverted channel)  
0x28  
0x2C  
0x30  
0x32  
ZDDATA0 Word Zero-deletion high word data buffer (User-initialized to 0xFFFFFFFF)  
ZDDATA1 Word Zero-deletion low word data buffer (User-initialized to 0xFFFFFFFF)  
RBDFlags Hword RxBD ßags, used by the CP (read-only for the user)  
RBDCNT Hword Rx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only  
for the user)  
0x34  
0x38  
RBDPTR Word Rx internal data pointer. Points to current absolute data address of channel, used by the  
CP (read-only for the user)  
MFLR  
Hword Maximum frame length register. DeÞnes the longest expectable frame for this channel.  
(64-Kbyte maximum). The remainder of a frame that is larger than MFLR is discarded  
and the LG ßag is set in the last frameÕs BD. An interrupt request might be generated  
(RXF and RXB) depending on the interrupt mask. A frameÕs length is considered to be  
everything between ßags, including CRC. No more data is written into the current buffer  
when the MFLR violation is detected.  
0x3A  
0x3C  
MAX_CNT Hword Max_length counter, used by the CP (read-only for the user)  
RCRC Word Temp receive CRC, used by the CP (read-only for the user)  
1
The offset is relative to dual-port RAM base address + 64*CH_NUM  
27-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part IV. Communications Processor Module  
27.6.1 Internal Transmitter State (TSTATE)  
Internal transmitter state (TSTATE) is a 4-byte register provides transaction parameters  
associated with SDMA channel accesses (like function code registers) and starts the  
transmitter channel.  
To start the channel, write 0xHH800000 to TSTATE, where HH is the TSTATE high byte  
(see Figure 27-6). When the channel is active, the CP changes the value of the three LSBs,  
hence these 3 bytes must be masked if the user reads back the TSTATE.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
Ñ
GBL  
BO  
Ñ
TC2  
DTB  
BDB  
R/W  
Figure 27-6. TSTATE High Byte  
TSTATE high-byte Þelds are described in Table 27-4.  
Table 27-4. TSTATE High-Byte Field Descriptions  
Bits  
Name  
Description  
0Ð1  
2
Ñ
Reserved, should be cleared.  
GBL  
Global. Setting GLB activates snooping (only the 60X bus can be snooped, this parameter is  
ignored for local bus transactions).  
3Ð4 BO  
Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-ßy,  
it takes effect at the beginning of the next frame or at the beginning of the next BD.  
00 Reserved  
01 PowerPC little-endian.  
1x Big-endian  
5
6
TC2  
DTB  
Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory  
access.TC[0Ð1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.  
Data bus indicator. Selects the bus that handles transfers to and from data buffers.  
0 60x bus SDMA  
1 Local bus SDMA  
7
BDB  
BD bus. Seects the bus that handles transfers to/from BD and interrupt circular tables.  
0 60x bus SDMA used for accessing BDs  
1 Local bus SDMA used for accessing BDs  
27.6.2 Interrupt Mask (INTMSK)  
The interrupt mask (INTMSK) provides in bits for enabling/disabling each event deÞned in  
the interrupt circular table entry.  
MOTOROLA  
Chapter 27. Multi-Channel Controllers (MCCs)  
27-9  
           
Part IV. Communications Processor Module  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Interrupt Entry  
INTMSK  
Ñ
Ñ
UN  
TXB  
Ñ
Ñ
NID IDL MRF RXF BSY RXB  
Mask Bits  
Mask Bits  
Figure 27-7. INTMSK Mask Bits  
To enable an interrupt, set the corresponding bit. If a bit is cleared, no interrupt request is  
generated and no new entry is written in the circular interrupt table. The user must initialize  
INTMSK prior to operation. Reserved bits are cleared.  
27.6.3 Channel Mode Register (CHAMR)  
The channel mode register (CHAMR) is a user-initialized register, shown in Figure 27-8.  
This is a generalized representation of CHAMR. Section 27.7.1, ÒChannel Mode Register  
(CHAMR)ÑTransparent Mode,Ó describes the CHAMR for transparent mode.  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field MODE POL  
1
IDLM  
Ñ
CRC  
Ñ
TS  
RQN  
NOF  
Reset  
R/W  
Ñ
R/W  
Offset  
0x1A  
Figure 27-8. Channel Mode Register (CHAMR)  
CHAMR Þelds are described in Table 27-5.  
Table 27-5. CHAMR Field Descriptions  
Bits  
Name  
Description  
0
MODE This mode bit determines whether the HDLC or transparent mode is used. It also determines how  
other CHAMR bits are interpreted.  
0 Transparent mode. See Section 27.7.1, ÒChannel Mode Register (CHAMR)ÑTransparent Mode.Ó  
1 HDLC mode  
1
POL  
Enable polling. POL enables the transmitter to poll the TxBDs.  
0 Polling is disabled (The CPM does not access the external bus to check the R bit in the TxBD).  
1 Polling is enabled.  
POL can be used to optimize the use of the external bus. Software should always set POL at the  
beginning of a transmit sequence of one or more frames. The CP clears POL when no more buffers  
are ready in the transmit queue, i.e. when it Þnds a BD with R = 0 (for example, at the end of a frame  
or at the end of a multi-frame transmission). To minimize useless transactions on the external bus,  
software should always prepare the new BD, or multiple BDs, and set BD[R] before enabling polling.  
2
1
Must be set.  
27-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part IV. Communications Processor Module  
Table 27-5. CHAMR Field Descriptions (Continued)  
Bits  
Name  
IDLM  
Description  
3
Idle mode.  
0 No idle patterns are sent between frames. After sending NOF+1 ßags, the transmitter starts  
sending the data of the frame. If the transmission is between frames and the frame buffers are not  
ready, the transmitter sends ßags until it can start transmitting the data.  
1 At least one idle pattern is sent between adjacent frames.The NOF value shall be no smaller than  
the PAD setting, see TxBD. If NOF = 0, this is identical to ßag sharing in HDLC. Mode ßags  
precede the actual data. When IDLM = 1, at least one idle pattern is sent between adjacent  
frames. If the transmission is between frames and the frame buffer is not ready, the transmitter  
sends idle characters. When data is ready, the NOF+1 ßags are sent followed by the data frame.  
If IDLE mode is selected and NOF = 1, the following sequence is sent:  
......init value, FF, FF, ßag, ßag, data, ........  
The init value before the idle will be ones.  
4Ð7  
8
Ñ
These bits must be cleared.  
CRC  
Selects the type of CRC when HDLC channel mode is used.  
0 16-bit CCITT-CRC  
1 32-bit CCITT-CRC  
9
Ñ
This bit must be cleared.  
10  
TS  
Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data  
buffer that the BD points to.If this bit is set the data buffer must start from an address equal to 8*n-4  
(n is any integer larger than 0).  
11Ð12 RQN  
Receive queue number. SpeciÞes the receive interrupt queue number.  
00 Queue number 0.  
01 Queue number 1.  
10 Queue number 2.  
11 Queue number 3.  
13Ð15 NOF  
Number of ßags. NOF deÞnes the minimum number of ßags before frames:  
000 At least 1 ßag  
001 At least 2 ßags  
....  
111 At least 8 ßags  
27.6.4 Internal Receiver State (RSTATE)  
Internal receiver state (RSTATE) is a 4-byte register that provides transaction parameters  
associated with SDMA channel accesses (like function code registers) and starts the  
receiver channel.  
To start the channel the user must write 0xHH800000 to RSTATE, where HH is the  
RSTATE high byte (see Figure 27-9). When the channel is active the CP changes the value  
of the 3 LSBs, hence these 3 bytes must be masked if the user reads back the RSTATE.  
MOTOROLA  
Chapter 27. Multi-Channel Controllers (MCCs)  
27-11  
   
Part IV. Communications Processor Module  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
Ñ
GBL  
BO  
Ñ
TC2  
DTB  
BDB  
R/W  
0x20  
Addr  
Figure 27-9. Rx Internal State (RSTATE) High Byte  
RSTATE high-byte Þelds are described in Table 27-6.  
Table 27-6. RSTATE High-Byte Field Descriptions  
Bits Name  
Description  
0Ð1  
2
Ñ
Reserved, should be cleared.  
GBL  
Global. Setting GLB activates snooping (only the 60X bus can be snooped, this parameter is ignored  
for local bus transactions).  
3Ð4 BO  
Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-ßy,  
it takes effect at the beginning of the next frame or at the beginning of the next BD.  
00 Reserved  
01 PowerPC little-endian.  
1x Big-endian  
5
6
TC2  
DTB  
Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory  
access. TC[0Ð1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.  
Data bus indicator.  
The transfers to data buffers are handled by the:  
0 60x bus SDMA  
1 Local bus SDMA  
7
BDB  
BD and interrupt circular tables bus indicator.  
The transfers to/from BD and interrupt circular tables are handled by the:  
0 60x bus SDMA  
1 Local bus SDMA  
Note that the following restrictions result from the fact that there is a common bus selection bit for  
BDs and interrupt circular tables:  
¥
The RxBDs of all the channels that use a particular interrupt table must reside on the same bus  
(60x or local).  
All TxBDs must reside on the same bus (60x or local).  
¥
27.7 Channel-SpeciÞc Transparent Parameters  
Table 27-7 describes channel-speciÞc parameters for transparent operation.  
Table 27-7. Channel-Specific Parameters for Transparent Operation  
1
Offset  
Name  
Width  
Description  
0x00  
TSTATE  
Word Tx internal state. To start a transmitter channel the user must write to TSTATE  
0xHH80_0000. HH is the TSTATE high byte described in Section 27.6.1, ÒInternal  
Transmitter State (TSTATE).Ó  
27-12  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part IV. Communications Processor Module  
Table 27-7. Channel-Specific Parameters for Transparent Operation (Continued)  
1
Offset  
Name  
Width  
Description  
0x04  
ZISTATE  
Word Zero-insertion machine state.(User-initialized to 0x10000207 for regular channel, and  
0x30000207 for inverted channel)  
0x08  
0x0C  
0x10  
0x12  
ZIDATA0  
ZIDATA1  
Word Zero-insertion high word data buffer (User-initialized to 0xFFFFFFFF)  
Word Zero-insertion low word data buffer (User-initialized to 0xFFFFFFFF)  
TBDFlags Hword TxDB ßags, used by the CP (read-only for the user)  
TBDCNT  
Hword Tx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only  
for the user)  
0x14  
TBDPTR  
Word Tx internal data pointer. Points to current absolute data address of channel, used by  
the CP (read-only for the user)  
0x18  
0x1A  
INTMSK  
CHAMR  
Hword ChannelÕs interrupt mask ßag. See Section 27.6.2, ÒInterrupt Mask (INTMSK).Ó  
Hword Channel mode register. See Section 27.7.1, ÒChannel Mode Register (CHAMR)Ñ  
Transparent Mode.Ó  
0x1C  
0x20  
Ñ
Word Reserved  
RSTATE  
Word Rx internal state. To start a receiver channel the user must write to RSTATE  
0xHH80_0000. HH is the RSTATE high byte described in Section 27.6.4, ÒInternal  
Receiver State (RSTATE).Ó  
0x24  
ZDSTATE Word Zero-deletion machine state (User-initialized to 0x00FFFFE0 for regular channel and  
0x20FFFFE0 for inverted channel)  
0x28  
0x2C  
0x30  
0x32  
ZDDATA0 Word Zero-deletion high word data buffer (User-initialized to 0xFFFFFFFF)  
ZDDATA1 Word Zero-deletion low word data buffer (User-initialized to 0xFFFFFFFF)  
RBDFlags Hword RxBD ßags, used by the CP (read-only for the user)  
RBDCNT  
Hword Rx internal byte count. Number of remaining bytes in buffer, used by the CP (read-  
only for the user)  
0x34  
0x38  
RBDPTR  
Word Rx internal data pointer. Points to current absolute data address of channel, used by  
the CP (read-only for the user)  
TMRBLR Hword Transparent maximum receive buffer length. DeÞnes the maximum number of bytes  
written to a receiver buffer before moving to the next buffer for the respective channel.  
This value must be 8 byte aligned.  
0x3A  
RCVSYNC Hword Receive synchronization pattern. DeÞnes the synchronization pattern when  
CHAMR[SYNC] is 0b1x. The two bytes are checked in reverse order (byte from  
address 0x3B Þrst and byte from address 0x3A last). Non-inverted data is used for  
synchronization even if the channel is programmed to invert the data.  
0x3C  
Ñ
Word Reserved  
1
The offset is relative to dual-port RAM address 64*CH_NUM  
27.7.1 Channel Mode Register (CHAMR)ÑTransparent Mode  
Figure 27-10 shows the user-initialized channel mode register, CHAMR, for transparent  
mode.  
MOTOROLA  
Chapter 27. Multi-Channel Controllers (MCCs)  
27-13  
     
Part IV. Communications Processor Module  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
MODE POL  
1
1
EP  
RD  
SYNC  
Ñ
TS  
RQN  
Ñ
Ñ
R/W  
0x1A  
Offset  
Figure 27-10. Channel Mode Register (CHAMR)ÑTransparent Mode  
CHAMR Þelds are described in Table 27-5,  
Table 27-8. CHAMR Field DescriptionsÑTransparent Mode  
Bits Name  
Description  
0
1
MODE Channel mode. Selects either HDLC or transparent mode.  
0 Transparent mode.  
1 HDLC mode  
POL  
Enable polling. POL enables the transmitter to poll the TxBDs.  
0 Polling is disabled (The CPM does not access the external bus to check the R bit in the TxBD).  
1 Polling is enabled.  
POL can be used to optimize the use of the external bus. Software should always set POL at the  
beginning of a transmit sequence of one or more frames. The CP clears POL when no more buffers  
are ready in the transmit queue, i.e. when it Þnds a BD with R = 0 (for example, at the end of a frame  
or at the end of a multi-frame transmission). To prevent a signiÞcant number of useless transactions  
on the external bus, software should always prepare the new BD, or multiple BDs, and set BD[R]  
before enabling polling.  
2Ð3 0b11  
Must be set.  
4
EP  
Empty polarity and enable polling.  
0
The E bit in the RxBD is handled in positive logic (1 = empty; 0 = not empty). Polling occurs only if  
POL is set.  
1
The E bit in the RxBD is handled in negative logic (0 = empty, 1 = not empty). Polling occurs  
disregarding the value of POL.  
5
RD  
0 Normal bit order (transmit/receive the lsb of each octet Þrst)  
1 Reversed bit order to be reversed (transmit/receive the msb of each octet Þrst).  
6Ð7 SYNC Synchronization. SYNC controls synchronization of multi-channel operation in transparent mode.  
SYNC Receive Transmit  
Description  
00  
01  
None  
Slot  
None  
Slot  
Transmitter and receiver operate with no synchronization algorithm  
The Þrst data is sent/received in the slot deÞned in the slot  
assignment table (for super channels only)  
10  
11  
8-bit  
None  
None  
Receive data synchronization uses an 8-bit pattern speciÞed by the 8  
MSB of RCVSYNC. The sync bytes will not be written to the receive  
buffer  
16-bit  
Receive data synchronization uses a 16-bit pattern speciÞed by  
RCVSYNC. The Þrst byte of the sync pattern will not be written to the  
receive buffer. The second byte of the sync pattern will be written to  
the receive buffer (Þrst and second represent the order in which the  
two bytes of the sync pattern are received on the serial channel).  
8Ð9  
Ñ
Reserved, must be cleared.  
27-14  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
Table 27-8. CHAMR Field DescriptionsÑTransparent Mode (Continued)  
Bits Name  
10 TS  
Description  
Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data  
buffer that the BD points to.If this bit is set the data buffer must start from an address equal to 8*N-4  
(N is any number larger than 0).  
11Ð12 RQN  
Receive queue number. SpeciÞes the receive interrupt queue number.  
00 Queue number 0.  
01 Queue number 1.  
10 Queue number 2.  
11 Queue number 3.  
13Ð15  
Ñ
Reserved, must be cleared.  
27.8 MCC ConÞguration Registers (MCCFx)  
The MCC conÞguration register (MCCF), shown in Figure 27-11, deÞnes the mapping of  
the MCC channels to the TDM channels. MCC1 can be connected to SI1 and MCC2 can  
be connected to SI2. For each MCCx-SIx pair, each of the four 32 channels subgroups can  
be connected to one of the four TDM highways (TDMA, TDMB, TDMC, and TDMD).  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
Group 1  
Group 2  
Group 3  
Group 4  
0000_0000  
R/W  
Addr  
0x11B38 (MCCF1), 0x11B58 (MCCF2)  
Figure 27-11. SI MCC Configuration Register (MCCF)  
Table 27-9 describes MCCF Þelds.  
Table 27-9. MCCF Field Descriptions  
Bits  
Name  
Description  
0Ð1, 2Ð3, 4Ð5, 6Ð7  
GROUP x Group x of channels is used by TDM y as shown in Table 27-10.  
00 Group x is used by TDM A.  
01 Group x is used by TDM B.  
10 Group x is used by TDM C.  
11 Group x is used by TDM D.  
Table 27-10 describes group assignments.  
MOTOROLA  
Chapter 27. Multi-Channel Controllers (MCCs)  
27-15  
         
Part IV. Communications Processor Module  
Table 27-10. Group Channel Assignments  
Group  
Channels  
0Ð31  
Group1 in MCCF1  
Group2 in MCCF1  
Group3 in MCCF1  
Group4 in MCCF1  
Group1 in MCCF2  
Group2 in MCCF2  
Group3 in MCCF2  
Group4 in MCCF2  
32Ð63  
64Ð95  
96Ð127  
128Ð159  
160Ð191  
192Ð223  
224Ð255  
Note that the TDM group channel assignments made in MCCF must be coherent with the  
SI register programming and SI RAM programming; see Section 14.5, ÒSerial Interface  
Registers,Ó and Section 14.4.3, ÒProgramming SIx RAM Entries.Ó The user must also  
program MCCF before enabling the TDM channel in the SIGMR; see Section 14.5.1, ÒSI  
Global Mode Registers (SIxGMR).Ó  
27.9 MCC Commands  
The user starts channels by writing to the TSTATE/RSTATE registers as described in  
Section 27.6.4, ÒInternal Receiver State (RSTATE),Ó and Section 27.6.1, ÒInternal  
Transmitter State (TSTATE).Ó  
The following commands, used to stop and initialize channels, are issued to the MCC by  
writing to CPCR as described in Section 13.4.1, ÒCP Command Register (CPCR).Ó  
Table 27-11 describes transmit commands.  
Table 27-11. Transmit Commands  
Command  
Description  
STOP  
Disables the transmission on the selected channel and clears CHAMR[POL]. When this command is  
issued in the middle of a frame, the CP sends an ABORT indication and then idles/ßags on the  
selected channel. If this command is issued between frames, the CP sends only idles or ßags  
(depending on CHAMR[IDLM]). TBPTR points for the buffer that the CP was using when the STOP  
TRANSMIT command was issued.  
TRANSMIT  
INIT TX  
Initializes transmit parameters in this MCC parameter RAM to their reset state. This command should  
PARAMETERS only be issued when the transmitter is disabled. Note that the MCC initialize commands initialize only  
the 32 consecutive channels starting with the channel number speciÞed in CPCR[MCN]. To initialize  
more than 32 channels, reissue the command with the appropriate channel numbers. Note also the INIT  
TX AND RX PARAMETERS command can be used to reset both the receive and transmit parameters.  
27-16  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part IV. Communications Processor Module  
Table 27-12 describes receive commands.  
Table 27-12. Receive Commands  
Command  
Description  
STOP  
Forces the receiver of the selected channel to terminate reception. After this command is executed, the  
CP does not change the receive parameters in the dual-port RAM. The user must initialize the channel  
receive parameters in order to restart reception.  
RECEIVE  
INIT RX  
Initializes all receive parameters in this MCC parameter RAM to their reset state. Should be issued only  
PARAMETERS when the receiver is disabled. Note that the MCC initialize commands initialize only the 32 consecutive  
channels starting with the channel number speciÞed in CPCR[MCN]. To initialize more than 32  
channels, reissue the command with the appropriate channel numbers. Note also the INIT TX AND RX  
PARAMETERS command can be used to reset both the receive and transmit parameters.  
27.10 MCC Exceptions  
MCC interrupt handling involves two main data structures, the MCC event register  
(described in Section 27.10.1, ÒMCC Event Register (MCCE)/Mask Register (MCCM))  
and the interrupt circular tables, shown in Figure 27-12.  
Interrupt Table Entry  
0
1
2Ð17  
18Ð25  
26Ð31  
Interrupt Flags  
Interrupt Flags  
Interrupt Flags  
Interrupt Flags  
Interrupt Flags  
Interrupt Flags  
Interrupt Flags  
Interrupt Flags  
Interrupt Flags  
Channel Number  
Channel Number  
Channel Number  
Channel Number  
Channel Number  
Channel Number  
Channel Number  
Channel Number  
Channel Number  
T/RINTBASE  
V=0  
V=0  
V=0  
V=0  
V=1  
V=1  
V=0  
V=0  
V=0  
W=0  
W=0  
W=0  
W=0  
W=0  
W=0  
W=0  
W=0  
W=1  
Software Pointer  
T/RINTPTR  
Figure 27-12. Interrupt Circular Table  
There is one table for transmitter interrupts and from one to four tables for receiver  
interrupts. Each channel is programmed to report receiver interrupts in one of the receiver  
tables. This way receiver interrupts can be sorted, for example, by priority. Each interrupt  
circular table must be least two entries long.  
T/RINTBASE and T/RINTPTR, which are user-initialized global MCC parameters (See  
Section 27.3, ÒGlobal MCC ParametersÓ), point to the starting location of the table (in  
external memory) and the current empty position (initialized at the top of the table)  
available to the CP. All the entries in the table must be user-initialized with 0x00000000,  
except for the last one which must be initialized with 0x40000000 (W = 1, thus deÞning the  
MOTOROLA  
Chapter 27. Multi-Channel Controllers (MCCs)  
27-17  
         
Part IV. Communications Processor Module  
end of the table). When an MCC channel generates an interrupt request, the CP writes a new  
entry to the table (with V = 1) and increments T/RINTPTR (if W = 1 for the current entry,  
T/RINTPTR is loaded with T/RINTBASE).  
An interrupt is issued to the core whenever an entry is added to an interrupt circular table,  
except for the RXF events (received complete HDLC frame), in which case an interrupt is  
issued after a total of GRFTHR entries were added to one or more of the receive interrupt  
circular tables. See Table 27-1 for the description of the GRFTHR.  
In addition to the channelÕs number, this entry contains a description of the exception (see  
Section 27.10.1.1, ÒInterrupt Table EntryÓ).  
After an MCC interrupt, the user reads MCCE. MCCE[GINT] can be used to indicate that  
at least one new entry was added to one of the tables. After clearing GINT, the user starts  
processing the table(s) which contain pending events, as indicated by the bits  
MCCE[RINTx] and MCCE[TINT]. The user then clears this entryÕs valid bit (V) (see  
Section 27.10.1.1, ÒInterrupt Table EntryÓ). The user follows this procedure until it reaches  
an entry with V = 0.  
27.10.1 MCC Event Register (MCCE)/Mask Register (MCCM)  
The MCC event register (MCCE) is used to report events and generate interrupt requests.  
For each of its ßags, a programmable mask/enable bit in MCCM determines whether an  
interrupt request is generated. The MCC mask register (MCCM) is used to enable/disable  
interrupt requests. For each ßag in the MCCE there is a programmable mask/enable bit in  
MCCM which determines whether an interrupt request is generated. Setting an MCCM bit  
enables and clearing an MCCM bit disables the corresponding interrupt.  
MCCE bits are cleared by writing ones to them; writing zeros has no effect.  
Figure 27-13 shows MCCE and MCCM bits,  
Bits  
0
1
2
3
4
5
6
7
8
9
10 11  
12  
13  
14  
15  
Field QOV0 RINT0 QOV1 RINT1 QOV2 RINT2 QOV3 RINT3  
Ñ
TQOV TINT GUN GOV  
Reset  
R/W  
0000_0000_0000_0000  
R/W  
Addr  
0x11B30 (MCCE1), 0x11B50 (MCCE2)/0x11B34 (MCCM1), 0x11B54 (MCCM2)  
Figure 27-13. MCC Event Register (MCCE)/Mask Register (MCCM)  
27-18  
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MOTOROLA  
       
Part IV. Communications Processor Module  
Table 27-13 describes MCCE Þelds.  
Table 27-13. MCCE/MCCM Register Field Descriptions  
Bits  
Name  
Description  
0
1
QOV0  
RINT0  
QOV1  
RINT1  
QOV2  
RINT2  
QOV3  
RINT3  
Ñ
QOVxÑReceive interrupt queue overßow. IQOV is set (and an interrupt request generated) by the  
CP whenever an overßow occurs in the transmit circular interrupt table. This occurs if the CP tries to  
update an interrupt entry that was not handled by the user (such an entry is identiÞed by V = 1).  
RINTxÑReceive interrupt.When RINT = 1, the MCC generated at least one new entry in the receive  
interrupt circular table. After clearing it, the user reads the next entry from the receive interrupt  
circular table and starts processing a speciÞc channelÕs exception. The user returns from the  
interrupt handler when it reaches a table entry with V = 0.  
2
3
4
5
6
7
8Ð11  
12  
Reserved, should be cleared.  
TQOV  
Transmit interrupt queue overßow. TQOV is set (and interrupt request generated) by the CP  
whenever an overßow occurs in the transmit circular interrupt table. This condition occurs if the CP  
attempts to write a new interrupt entry into an entry that was not handled by the user. Such an entry  
is identiÞed by V = 1.  
13  
14  
TINT  
GUN  
Transmit interrupt. When TINT = 1, at least one new entry in the transmit interrupt circular table was  
generated by MCC. After clearing it, the user reads the next entry from the transmit interrupt circular  
table and starts processing a speciÞc channelÕs exception. The user returns from the interrupt  
handler when it reaches a table entry with V = 0.  
Global transmitter underrun. When set, this ßag indicates that an underrun occured in the MCCÕs  
transmitter FIFO buffer. This error is fatal, since it is unknown which channels were affected.  
Following the assertion of GUN in the MCCE the MCC stops transmitting data in all channels. The  
TDM Tx line becomes idle. The MCC transmitters must be reinitialized after this error. If enabled in  
MCCM, an interrupt request is generated when GUN is set. The user must clear GUN.  
15  
GOV  
Global receiver overrun. When GOV = 1, an overrun occured in the MCCÕs receiver FIFO buffer.This  
error is fatal, since it is unknown which channels were affected. When GOV = 1, the MCC stops  
receiving data in all channels. No more data is transferred to memory. The MCC receivers must be  
re-initialized after this error. If enabled in MCCM, an interrupt request is generated when GOV is set.  
The user must clear GOV bit.  
27.10.1.1 Interrupt Table Entry  
Each interrupt table entry, shown in Figure 27-14, contains information about channel-  
speciÞc events. The transmit circular table shows only events caused by transmission; the  
receive circular tables shows only events caused by reception.  
MOTOROLA  
Chapter 27. Multi-Channel Controllers (MCCs)  
27-19  
   
Part IV. Communications Processor Module  
Bits  
Field  
R/W  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
V
W
Ñ
UN TXB  
Ñ
NID IDL MRF RXF BSY RXB  
R/W  
23  
16  
17  
18  
19  
20  
21  
22  
24  
25  
26  
0
27  
0
28  
0
29  
0
30  
0
31  
0
Field  
R/W  
Ñ
Channel Number  
R/W  
Figure 27-14. Interrupt Circular Table Entry  
Table 27-14 describes interrupt circular table Þelds.  
Table 27-14. Interrupt Circular Table Entry Field Descriptions  
Bits  
Name  
Description  
0
V
Valid bit. V = 1 indicates that this entry contains valid interrupt information. Upon generating a new  
entry, the CP sets V = 1. The user clears V immediately after it reads the interrupt ßags of the entry  
(before processing the interrupt). The V bits in the table are user-initialized. During initialization, the  
user must clear those bits in all table entries.  
1
W
Wrap bit. W = 1 indicates the last interrupt circular table entry. The next eventÕs entry is written/read  
(by CP/user) from the address contained in INTBASE (see Table 27-1). During initialization, the user  
must clear all W bits in the table except for the last one which must be set.  
2Ð5  
6
Ñ
Reserved, should be cleared.  
UN  
Tx no data. The CP sets this ßag if there is no data available to be sent to the transmitter. The  
transmitter sends an ABORT indication and then sends idles.  
7
TXB  
Tx buffer. A buffer has been completely transmitted. TXB is set (and an interrupt request is  
generated) as soon as the programmed number of PAD characters (or the closing ßag, for PAD = 0)  
is written to MCC transmit FIFO. This controls when the TXB interrupt is given in relation to the  
closing ßag sent out at TXD. Section 27.11.2, ÒTransmit Buffer Descriptor (TxBD)Ó describes how  
PAD characters are used.  
8Ð9  
10  
Ñ
Reserved, should be cleared.  
MRF  
Maximum receive frame length violation. This interrupt occurs in HDLC mode when more bytes are  
received than the value speciÞed in MFLR.This interrupt is generated as soon as the MFLR value is  
exceeded; the remainder of the frame is discarded  
11  
12  
NID  
IDL  
Set whenever a pattern that is not an idle pattern is identiÞed.  
Idle. Set when the channelÕs receiver identiÞes the Þrst occurrence of HDLC idle (0xFFFE) after any  
non-idle pattern.  
13  
14  
15  
RXF  
BSY  
RXB  
Rx frame. A complete HDLC frame has been received.  
Busy. A frame was received but was discarded due to lack of buffers.  
Rx buffer. A buffer has been received on this channel that was not the last buffer in frame. This  
interrupt is also given for different error types that can happen during reception. Error conditions are  
reported in the RxBD.  
16Ð18  
Ñ
Reserved, should be cleared.  
19Ð26 CN  
Channel number. IdentiÞes the requests channel index (0Ð255).  
Reserved, should be cleared.  
27Ð31  
Ñ
27-20  
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MOTOROLA  
   
Part IV. Communications Processor Module  
27.11 MCC Buffer Descriptors  
Each MCC channel requires two BD tables (one for transmit and one for receive). Each BD  
contains key information about the buffer it deÞnes. The BDs are accessed by the MCC as  
needed; BDs can be added dynamically to the BDs chain. The RxBDs chain must include  
at least two BDs; the TxBD chain must include at least one BDs.  
The MCC BDs are located in the external memory.  
27.11.1 Receive Buffer Descriptor (RxBD)  
Figure 27-15 shows the RxBD.  
0
1
2
3
4
L
5
F
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
E
Ñ
W
I
CM  
Ñ
UB  
Ñ
LG  
NO  
AB  
CR  
Ñ
Data Length  
Rx Data Buffer Pointer  
Figure 27-15. MCC Receive Buffer Descriptor (RxBD)  
RxBD Þelds are described in Table 27-15.  
Table 27-15. RxBD Field Descriptions  
Bits Name  
Description  
0
E
Empty  
0
The data buffer associated with this BD has been Þlled with received data, or data reception has  
been aborted due to an error condition. The user is free to examine or write to any Þelds of this  
RxBD. The CP does not use this BD again while the empty bit remains zero.  
The data buffer associated with this BD is empty, or reception is in progress. This RxBD and its  
associated receive buffer are in use by the CP.When E = 1, the user should not write any Þelds of  
this RxBD.  
1
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (Þnal BD in table)  
0
1
This is not the last BD in the RxBD table.  
This is the last BD in the RxBD table. After this buffer has been used, the CP receives incoming  
data into the Þrst BD in the table (the BD pointed to by RBASE). The number of RxBDs in this  
table is programmable and is determined by the wrap bit.  
3
4
I
Interrupt  
0
1
The RXB bit is not set after this buffer has been used, but RXF operation remains unaffected.  
The RXB or RXF bit in the HDLC interrupt circular table entry is set when this buffer has been  
used by the HDLC controller. These two bits may cause interrupts (if enabled).  
L
Last in frame (only for HDLC mode of operation).The HDLC controller sets L = 1, when this buffer is  
the last in a frame.This implies the reception either of a closing ßag or of an error, in which case one  
or more of the CD, OV, AB, and LG bits are set. The HDLC controller writes the number of frame  
octets to the data length Þeld.  
0
1
This buffer is not the last in a frame.  
This buffer is the last in a frame.  
MOTOROLA  
Chapter 27. Multi-Channel Controllers (MCCs)  
27-21  
         
Part IV. Communications Processor Module  
Table 27-15. RxBD Field Descriptions (Continued)  
Bits Name  
Description  
5
F
First in frame. The HDLC controller sets F = 1 for the Þrst buffer in a frame. In transparent mode, F  
indicates that there was a synchronization before receiving data in this BD.  
0
1
This is not the Þrst buffer in a frame.  
This is the Þrst buffer in a frame.  
6
CM  
Continuous mode  
0
1
Normal operation (The empty bit (bit 0) is cleared by the CP after this BD is closed).  
The empty bit (bit 0) is not cleared by the CP after this BD is closed, allowing the associated data  
buffer to be overwritten automatically when the CP next accesses this BD. However, if an error  
occurs during reception, the empty bit is cleared regardless of the CM bit setting.  
7
8
Ñ
Reserved, should be cleared.  
UB  
User bit. UB is a user-deÞned bit that the CPM never sets nor clears. The user determines how this  
bit is used.  
9
Ñ
Reserved, should be cleared.  
10  
LG  
Rx frame length violation (HDLC mode only). Indicates that a frame length greater than the  
maximum value was received in this channel. Only the maximum-allowed number of bytes, MFLR  
rounded to the nearest higher word alignment, are written to the data buffer.This event is recognized  
as soon as the MFLR value is exceeded when data is word-aligned. When data is not word-aligned,  
this interrupt occurs when the SDMA writes 64 bits to memory. The worst-case latency from MFLR  
violation until detected is 7 bytes timing for this channel. When MFLR violation is detected, the  
receiver is still receiving even though the data is discarded. The buffer is closed upon detecting a  
ßag, and this is considered to be the closing ßag for this buffer. At this point, LG is set (1) and an  
interrupt may be generated. The length Þeld for this buffer is everything between the opening ßag  
and this last identifying ßag.  
11  
NO  
Rx nonoctet-aligned frame. A frame of bits not divisible exactly by eight was received. NO = 1 for any  
type of nonalignment regardless of frame length. The shortest frame that can be detected is of type  
FLAG-BIT-FLAG, which causes the buffer to be closed with NO error indicated.  
The following shows how the nonoctet alignment is reported and where data can be found.  
msb  
xxx .................................... xx  
Valid data  
lsb  
000...... 0  
1
Invalid data  
To accommodate the extra word of data that may be written at the end of the frame, it is  
recommended to reserve MFLR + 8 bytes for each buffer data.  
12  
AB  
Rx abort sequence. A minimum of seven consecutive 1s was received during frame reception. Abort  
is not detected between frames. The sequence  
Closing-Flag, data, CRC, AB, data, opening-ßag...  
does not cause an abort error. If the abort is long enough to be an idle, an idle line interrupt may be  
generated. An abort within the frame is not reported by a unique interrupt but rather with a RXF  
interrupt and the user has to examine the BD.  
13  
CR  
Ñ
Rx CRC error. This frame contains a CRC error. The received CRC bytes are always written to the  
receive buffer.  
14Ð15  
Reserved, should be cleared.  
27-22  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part IV. Communications Processor Module  
The data length and buffer pointer are described as follows:  
¥
Data length. Data length is the number of octets written by the CP into this BDÕs data  
buffer. It is written by the CP when the BD is closed. When this is the last BD in the  
frame (L = 1), the data length contains the total number of frame octets (including  
two or four bytes for CRC). Note that memory allocated for buffers should be not  
smaller than the contents of the maximum receive buffer length register (MRBLR).  
The data length does not include the time stamp.  
¥
Rx buffer pointer. The receive buffer pointer points to the Þrst location of the  
associated data buffer. This value must be equal to 8*n if CHAMR[TS] = 0 and equal  
to 8*n - 4 if CHAMR[TS] = 1 (where n is any integer larger than 0).  
27.11.2 Transmit Buffer Descriptor (TxBD)  
Figure 27-16 shows the TxBD.  
0
1
2
3
4
5
6
7
8
9
10  
Ñ
11  
12  
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
R
Ñ
W
I
L
TC  
CM  
Ñ
UB  
PAD  
Data Length  
Tx Data Buffer Pointer  
Figure 27-16. MCC Transmit Buffer Descriptor (TxBD)  
Table 27-16 describes TxBD Þelds.  
Table 27-16. TxBD Field Descriptions  
Bits Name  
Description  
0
R
Ready  
0
The buffer associated with this BD is not ready for transmission. The user is free to manipulate this  
BD or its associated data buffer. The CP clears this bit after the buffer has been transmitted or after  
an error condition is encountered.  
1
The data buffer is ready to be transmitted. The transmission may have begun, but it has not  
completed. The user cannot modify this BD once this bit is set.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (Þnal BD in table)  
0
1
This is not the last BD in the TxBD table.  
This is the last BD in the TxBD table. After this buffer is used, the CP receives incoming data into the  
Þrst BD in the table (the BD pointed to by TBASE). The number of TxBDs in this table is  
programmable and is determined the wrap bit.  
3
4
I
Interrupt  
0
1
No interrupt is generated after this buffer has been serviced.  
TXB in the circular interrupt table entry is set when this buffer has been serviced by the MCC. This  
bit can cause an interrupt (if enabled).  
L
Last  
0
1
This is not the last buffer in the frame.  
This is the last buffer in the current frame.  
MOTOROLA  
Chapter 27. Multi-Channel Controllers (MCCs)  
27-23  
       
Part IV. Communications Processor Module  
Table 27-16. TxBD Field Descriptions (Continued)  
Bits Name  
Description  
5
F
Tx CRC. Valid only when L = 1. Otherwise it must be ignored.  
0
Transmit the closing ßag after the last data byte. This setting can be used for testing purposes to  
send an erroneous CRC after the data.  
Transmit the CRC sequence after the last data byte.  
1
6
CM  
Continuous mode  
0
1
Normal operation.  
The CP does not clear the ready bit after this BD is closed, allowing the associated data buffer to be  
retransmitted automatically when the CP next accesses this BD. However, the R bit is cleared if an  
error occurs during transmission, regardless of the CM bit setting.  
7
8
Ñ
Reserved, should be cleared.  
UB  
User bit. UB is a user-deÞned bit that the CPM never sets nor clears. The user determines how this bit  
is used.  
9Ð11  
Ñ
Reserved, should be cleared.  
12Ð15 PAD  
Pad characters.These four bits indicate the number of PAD characters (0x7E or 0xFF depending on the  
IDLM mode selected in the CHAMR register) that the transmitter sends after the closing ßag. The  
transmitter issues a TXB interrupt only after sending the programmed number of pads to the Tx FIFO  
buffer. The user can use the PAD value to guarantee that the TXB interrupt occurs after the closing ßag  
has been sent out on the TXD line. PAD = 0, means that the TXB interrupt is issued immediately after  
the closing ßag is sent to the Tx FIFO buffer. The number of PAD characters depends on the FIFO size  
assigned to the channel in the MCC hardware. If the channel is not part of a super channel then the  
MCC hardware assigns to this channel a Þfo of 4 bytes. So in this case a pad of 4 bytes ensure that the  
TXB interrupt is not given before the closing ßag has been transmitted over the TXD line. For a super  
channel, FIFO length equals the number of channels included in the super channel multiplied by four.  
The data length and buffer pointer are described below:  
¥
Data length. The data length is the number of bytes the MCC should transmit from  
this BDÕs data buffer. It is never modiÞed by the CP. The value of this Þeld should  
be greater than zero.  
¥
Tx buffer pointer. The transmit buffer pointer, which contains the address of the  
associated data buffer, may be even or odd. The buffer may reside in either internal  
or external memory. This value is never modiÞed by the CP.  
27.12 MCC Initialization and Start/Stop Sequence  
The MCC must be initialized and started/stopped in relation with the corresponding TDMs.  
The following two sections present the initialization and start/stop sequences which must  
be followed for single and super channels.  
27-24  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
27.12.1 Single-Channel Initialization  
The following sequence must be followed to initialize and start a single channel (after reset  
or after a fatal error):  
1. Program the SI. The entries the MCC channels uses must point to the null channel  
(set in the SI RAM entry MCC = 0, CSEL = 0 and the correct size - 1 byte); entries  
used by other controllers (not MCC) can be activated at this time.  
2. Initialize the MCC parameters (in DPR and external memory).  
3. Enable the MCC channel as described in Section 27.6.1, ÒInternal Transmitter State  
(TSTATE),Ó and Section 27.6.4, ÒInternal Receiver State (RSTATE).Ó  
4. Reprogram the SI RAM to point to the enabled channel(s).  
The following sequence must be followed to stop a single channel in order to change the SI  
without using the shadow SI:  
1. Issue a STOP command for the respective channel as described in Section 27.9,  
ÒMCC Commands.Ó  
2. Change the SI.  
3. Enable the MCC channel(s) as described in Section 27.6.1, ÒInternal Transmitter  
State (TSTATE),Ó and Section 27.6.4, ÒInternal Receiver State (RSTATE).Ó  
It is possible to change the SI using the SI shadow while the channel is active. Both the  
primary and the shadow conÞguration of the SI RAM must observe the conÞguration  
deÞned in MCCF (see Section 27.8, ÒMCC ConÞguration Registers (MCCFx)Ó). The  
MCCF cannot be changed while there are active channels.  
The following sequence must be followed to stop a single channel in order to change the  
MCC parameters of the respective channel:  
1. Issue a STOP command for the respective channel as described in Section 27.9,  
ÒMCC Commands,Ó or change the associated SI RAM entry to point to a channel  
which is not active and wait for two frame periods in order to clear the internal  
FIFOs.  
2. Change the channel parameters.  
3. Enable the MCC channel(s) as described in Section 27.6.1, ÒInternal Transmitter  
State (TSTATE),Ó and Section 27.6.4, ÒInternal Receiver State (RSTATE),Ó or  
change the associated SI RAM entry to point to the respective channel.  
MOTOROLA  
Chapter 27. Multi-Channel Controllers (MCCs)  
27-25  
 
Part IV. Communications Processor Module  
27.12.2 Super Channel Initialization  
The following steps initialize and start a super channel (after reset of after a fatal error):  
1. Program the SI as required for a super channel but do not enable the TDM.  
2. Issue a STOP command as described in Section 27.9, ÒMCC Commands.Ó  
3. Enable the TDM.  
4. Initialize the MCC parameters (in DPR and external memory).  
5. Enable the MCC channel(s) as described in Section 27.6.1, ÒInternal Transmitter  
State (TSTATE),Ó and Section 27.6.4, ÒInternal Receiver State (RSTATE).Ó  
The following sequence must be followed to stop a super channel in order to change the SI:  
1. Issue a STOP command for the respective channel as described in Section 27.9,  
ÒMCC Commands.Ó  
2. Disable the TDM.  
3. Change the SI.  
4. Enable the TDM.  
5. If necessary, change the MCC parameters (in DPR and external memory).  
6. Enable the MCC channel(s) as described in Section 27.6.1, ÒInternal Transmitter  
State (TSTATE),Ó and Section 27.6.4, ÒInternal Receiver State (RSTATE).Ó  
Under the following restrictions, the SI can be changed using the SI shadow while the  
channel is active:  
¥
Both the primary and the shadow conÞguration of the SI RAM must observe the  
conÞguration of the super channel. Note that the super-channel table and MCCF  
register cannot be changed dynamically.  
¥
¥
It is not possible to add dynamically to a super channel a time slot previously used  
by a single-channel and had a width different from 8 bits.  
A time slot that was previously used by a single channel and had a width different  
from 8 bits cannot be added dynamically to a super channel.  
27.13 MCC Latency and Performance  
The MCC transfers data to/from the memory 8 bytes at a time. Considering this and the  
internal receiver FIFO (of 2 bytes/channel), the receiver latency (time since data on a  
channel is serialized until the respective data is written to memory) can be from 8Ð10 frame  
periods.  
If no super channels are active, the MCC can handle aggregate data rates of up to 16 Mbps  
on each of the four channel subgroups. If super channels are used this performance is  
limited to 8 Mbps.  
27-26  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part IV. Communications Processor Module  
If multiple synchronized channels are used (as an example 8 T1 with common clock/sync)  
it is recommended to start the channels out of phase in order to load uniformly the bus. This  
avoids bus activity peaks when all the channels have to transfer data to/from the memory  
simultaneously.  
MOTOROLA  
Chapter 27. Multi-Channel Controllers (MCCs)  
27-27  
Part IV. Communications Processor Module  
27-28  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Chapter 28  
Fast Communications Controllers  
(FCCs)  
280  
2T80 he MPC8260Õs fast communications controllers (FCCs) are serial communications  
controllers (SCCs) optimized for synchronous high-rate protocols. FCC key features  
include the following:  
¥
¥
¥
¥
¥
Supports HDLC/SDLC and totally transparent protocols  
FCC clocks can be derived from a baud-rate generator or an external signal.  
Supports RTS, CTS, and CD modem control signals  
Use of bursts to improve bus usage  
Multibuffer data structure for receive and transmit, external buffer descriptors (BDs)  
anywhere in system memory  
¥
¥
¥
192-byte FIFO buffers  
Full-duplex operation  
Fully transparent option for one half of an FCC (receiver/transmitter) while HDLC/  
SDLC protocol executes on the other half (transmitter/receiver)  
¥
¥
Echo and local loopback modes for testing  
Assuming a 100-MHz CPM clock, the FCCs support the following:  
Ñ Full 10/100-Mbps Ethernet/IEEE 802.3x through an MII  
Ñ Full 155-Mbps ATM segmentation and reassembly (SAR) through UTOPIA (on  
FCC1 and FCC2 only)  
Ñ 45-Mbps (DS-3/E3 rates) HDLC and/or transparent data rates supported on each  
FCC  
FCCs differ from SCCs as follows:  
¥
¥
¥
¥
No DPLL support.  
No BISYNC, UART, or AppleTalk/LocalTalk support.  
No HDLC bus.  
Ethernet support only through an MII.  
MOTOROLA  
Chapter 28. Fast Communications Controllers (FCCs)  
28-1  
   
Part IV. Communications Processor Module  
28.1 Overview  
MPC8260 FCCs can be conÞgured independently to implement different protocols.  
Together, they can be used to implement bridging functions, routers, and gateways, and to  
interface with a wide variety of standard WANs, LANs, and proprietary networks. FCCs  
have many physical interface options such as interfacing to TDM buses, ISDN buses,  
standard modem interfaces, fast Ethernet interface (MII), and ATM interfaces (UTOPIA);  
see Chapter 14, ÒSerial Interface with Time-Slot Assigner,Ó Chapter 30, ÒFast Ethernet  
Controller,Ó and Chapter 29, ÒATM Controller.Ó The FCCs are independent from the  
physical interface, but FCC logic formats and manipulates data from the physical interface.  
That is why the interfaces are described separately.  
The FCC is described in terms of the protocol that it is chosen to run. When an FCC is  
programmed to a certain protocol, it implements a certain level of functionality associated  
with that protocol. For most protocols, this corresponds to portions of the link layer (layer  
2 of the seven-layer OSI model). Many functions of the FCC are common to all of the  
protocols. These functions are described in the FCC description. Following that, the  
implementation details that differentiate protocols from one another are discussed,  
beginning with the transparent protocol. Thus, the reader should read from this point to the  
transparent protocol and then skip to the appropriate protocol. Since the FCCs use similar  
data structures across all protocols, the reader's learning time decreases dramatically after  
understanding the Þrst protocol.  
Each FCC supports a number of protocolsÑEthernet, HDLC/SDLC, ATM, and totally  
transparent operation. Although the selected protocol usually applies to both the FCC  
transmitter and receiver, half of one FCC can run transparent operation while the other runs  
HDLC/SDLC protocol. The internal clocks (RCLK, TCLK) for each FCC can be  
programmed with either an external or internal source. The internal clocks originate from  
one of the baud-rate generators or one of the external clock signals. These clocks can be as  
fast as one-third the CPM clock frequency. See Chapter 14, ÒSerial Interface with Time-  
Slot Assigner.Ó However, the FCCÕs ability to support a sustained bit stream depends on the  
protocol as well as on other factors.Each FCC can be connected to its own set of pins on  
the MPC8260. This conÞguration, the nonmultiplexed serial interface, or NMSI, is  
described in Chapter 14, ÒSerial Interface with Time-Slot Assigner.Ó In this conÞguration,  
each FCC can support the standard modem interface signals (RTS, CTS, and CD) through  
the appropriate port pins and the interrupt controller. Additional handshake signals can be  
supported with additional parallel I/O lines. The FCC block diagram is shown in  
Figure 28-1.  
28-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
60x Bus  
Control  
Registers  
TCLK  
Clock  
Generator  
RCLK  
Peripheral Bus  
Internal Clocks  
Receive  
Data  
FIFO  
Transmit  
Data  
FIFO  
Receive  
Control  
Unit  
Transmit  
Control  
Unit  
Modem Lines  
Modem Lines  
Decoder  
TXD  
RXD  
Delimiter  
Shifter  
Shifter  
Delimiter  
Encoder  
Figure 28-1. FCC Block Diagram  
28.2 General FCC Mode Registers (GFMRx)  
Each FCC contains a general FCC mode register (GFMRx) that deÞnes all options common  
to every FCC, regardless of the protocol. Some GFMR operations are described in later  
sections. The GFMRx are read/write registers cleared at reset. Figure 28-2 shows the  
GFMR format.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
Ñ
13  
14  
15  
DIAG  
TCI  
TRX TTX CDP CTSP CDS CTSS  
0000_0000_0000_0000  
R/W  
Addr  
Bits  
0x11300 (GFMR1), 0x11320 (GFMR2), 0x11340 (GFMR3)  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
SYNL  
RTSM  
RENC  
REVD  
TENC  
TCRC  
ENR ENT  
MODE  
0000_0000_0000_0000  
R/W  
Addr  
0x11302 (GFMR1), 0x11322 (GFMR2), 0x11342 (GFMR3)  
Figure 28-2. General FCC Mode Register (GFMR)  
MOTOROLA  
Chapter 28. Fast Communications Controllers (FCCs)  
28-3  
             
Part IV. Communications Processor Module  
Table 28-1 describes GFMR Þelds.  
Table 28-1. GFMR Register Field Descriptions  
Field Name  
Description  
0Ð1 DIAG  
Diagnostic mode.  
00 Normal operationÑReceive data enters through RXD, and transmit data is shifted out through  
TXD. The FCC uses the modem signals (CD and CTS) to automatically enable and disable  
transmission and reception. Timings are shown in Section 28.11, ÒFCC Timing Control.Ó  
01 Local loopback modeÑTransmitter output is connected internally to the receiver input, while the  
receiver and the transmitter operate normally. RXD is ignored. Data can be programmed to  
appear on TXD, or TXD can remain high by programming the appropriate parallel port register.  
RTS can be disabled in the appropriate parallel I/O register. The transmitter and receiver must  
use the same clock source, but separate CLKx pins can be used if connected to the same  
external clock source.  
If external loopback is preferred, program DIAG for normal operation and externally connect  
TXD and RXD. Then, physically connect the control signals (RTS connected to CD, and CTS  
grounded) or set the parallel I/O registers so CD and CTS are permanently asserted to the FCC  
by conÞguring the associated CTS and CD pins as general-purpose I/O.; see Chapter 35,  
ÒParallel I/O Ports.Ó  
10 Automatic echo modeÑThe channel automatically retransmits received data, using the receive  
clock provided. The receiver operates normally and receives data if CD is asserted. The  
transmitter simply transmits received data. In this mode, CTS is ignored. The echo function can  
also be accomplished in software by receiving buffers from an FCC, linking them to TxBDs, and  
transmitting them back out of that FCC.  
11 Loopback and echo modeÑLoopback and echo operation occur simultaneously. CD and CTS  
are ignored. Refer to the loopback bit description for clocking requirements.  
For TDM operation, the diagnostic mode is selected by SIxMR[SDMx]; see Section 14.5.2, ÒSI  
Mode Registers (SIxMR).Ó  
2
3
TCI  
Transmit clock invert  
0
1
Normal operation.  
The FCC inverts the internal transmit clock.  
TRX  
Transparent receiver. The MPC8260 FCCs offer totally transparent operation. However, to increase  
ßexibility, totally transparent operation is conÞgured with the TTX and TRX bits instead of the  
MODE bits. This lets the user implement unique applications such as an FCC transmitter  
conÞgured to HDLC and a receiver conÞgured to totally transparent operation. To do this, program  
MODE = HDLC, TTX = 0, and TRX = 1.  
0
1
Normal operation  
The receiver operates in totally transparent mode, regardless of the protocol selected for the  
transmitter in the MODE bits.  
Note that full-duplex, totally transparent operation for an FCC is obtained by setting both TTX and  
TRX. Attempting to operate an FCC with Ethernet or ATM on its transmitter and transparent  
operation on its receiver causes erratic behavior. In other words, if the MODE = Ethernet or ATM,  
TTX must equal TRX.  
4
TTX  
Transparent transmitter. The MPC8260 FCCs offer totally transparent operation. However, to  
increase ßexibility, totally transparent operation is conÞgured with the TTX and TRX bits instead of  
the MODE bits. This lets the user implement unique applications, such as conÞguring an FCC  
receiver to HDLC and a transmitter to totally transparent operation. To do this, program MODE =  
HDLC, TTX = 1, and TRX = 0.  
0 Normal operation.  
1 The transmitter operates in totally transparent mode, regardless of the receiver protocol selected  
in the MODE bits.  
Note that full-duplex totally transparent operation for an FCC is obtained by setting both TTX and  
TRX. Attempting to operate an FCC with Ethernet or ATM on its receiver and transparent operation  
on its transmitter causes erratic behavior. In other words, if the GFMR MODE = Ethernet or ATM,  
TTX must equal TRX.  
28-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part IV. Communications Processor Module  
Table 28-1. GFMR Register Field Descriptions (Continued)  
Field Name  
Description  
5
CDP  
CD pulse (transparent mode only)  
0 Normal operation (envelope mode). CD should envelope the frame; to negate CD while receiving  
causes a CD lost error.  
1 Pulse mode. Once CD is asserted (high to low transition), synchronization has been achieved,  
and further transitions of CD do not affect reception.  
This bit must be set if this FCC is used in the TSA.  
6
7
CTSP  
CDS  
CTS pulse  
0 Normal operation (envelope mode). CTS should envelope the frame; to negate CTS while  
transmitting causes a CTS lost error. See Section 28.11, ÒFCC Timing Control.Ó  
1 Pulse mode. CTS is asserted when synchronization is achieved; further transitions of CTS do not  
affect transmission.  
CD sampling  
0 The CD input is assumed to be asynchronous with the data. The FCC synchronizes it internally  
before data is received. (This mode is illegal in transparent mode when SYNL = 0b00.)  
1 The CD input is assumed to be synchronous with the data, giving faster operation. In this mode,  
CD must transition while the receive clock is in the low state. When CD goes low, data is  
received.This is useful when connecting MPC8260s in transparent mode since it allows the RTS  
signal of one MPC8260 to be connected directly to the CD signal of another MPC8260.  
8
CTSS  
CTS sampling  
0 The CTS input is assumed to be asynchronous with the data. When it is internally synchronized  
by the FCC, data is sent after a delay of no more than two serial clocks.  
1 The CTS input is assumed to be synchronous with the data, giving faster operation. In this mode,  
CTS must transition while the transmit clock is in the low state. As soon as CTS is low, data  
transmission begins. This mode is useful when connecting MPC8260 in transparent mode  
because it allows the RTS signal of one MPC8260 to be connected directly to the CTS signal of  
another MPC8260.  
9--15  
Ñ
Reserved, should be 0.  
16Ð17 SYNL  
Sync length (transparent mode only). Determines the operation of an FCC receiver conÞgured for  
totally transparent operation only. See Section 32.3.1, ÒIn-Line Synchronization Pattern.Ó  
00 The sync pattern in the FDSR is not used. An external sync signal is used instead (CD signal  
asserted: high to low transition).  
01 Automatic sync (assumes always synchronized, ignores CD signal).  
10 8-bit sync. The receiver synchronizes on an 8-bit sync pattern stored in the FDSR. Negation of  
CD causes CD lost error.  
11 16-bit sync.The receiver synchronizes on a 16-bit sync pattern stored in the FDSR. Negation of  
CD causes CD lost error.  
18  
RTSM RTS mode  
0 Send idles between frames as deÞned by the protocol. RTS is negated between frames (default).  
1 Send ßags/syncs between frames according to the protocol. RTS is asserted whenever the FCC  
is enabled.  
19Ð20 RENC Receiver decoding method. The user should set RENC = TENC in most applications.  
00 NRZ  
01 NRZI (one bit mode HDLC or transparent only)  
1x Reserved  
21  
REVD Reverse data (valid for a totally transparent channel only)  
0 Normal operation  
1 The totally transparent channels on this FCC (either the receiver, transmitter, or both, as deÞned  
by TTX and TRX) reverse bit order, transmitting the MSB of each octet Þrst.  
MOTOROLA  
Chapter 28. Fast Communications Controllers (FCCs)  
28-5  
Part IV. Communications Processor Module  
Table 28-1. GFMR Register Field Descriptions (Continued)  
Field Name  
Description  
22Ð23 TENC Transmitter encoding method. The user should set TENC = RENC in most applications.  
00 NRZ  
01 NRZI (one bit mode HDLC or transparent only)  
1x Reserved  
24-25 TCRC Transparent CRC (totally transparent channel only). Selects the type of frame checking provided on  
the transparent channels of the FCC (either the receiver, transmitter, or both, as deÞned by TTX  
and TRX). This conÞguration selects a frame check type; the decision to send the frame check is  
made in the TxBD. Thus, it is not required to send a frame check in transparent mode. If a frame  
check is not used, the user can ignore any frame check errors generated on the receiver.  
00 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1)  
01 Reserved  
10 32-bit CCITT CRC (Ethernet and HDLC) (X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +  
X8 + X7 + X5 + X4 + X2 + X1 +1)  
11 Reserved  
26  
ENR  
Enable receive. Enables the receiver hardware state machine for this FCC.  
0 The receiver is disabled and any data in the receive FIFO buffer is lost. If ENR is cleared during  
reception, the receiver aborts the current character.  
1 The receiver is enabled.  
ENR may be set or cleared regardless of whether serial clocks are present. Describes how to  
disable and reenable an FCC. Note that the FCC provides other tools for controlling receptionÑthe  
ENTER HUNT MODE command, CLOSE RXBD command, and RxBD[E].  
27  
ENT  
Enable transmit. Enables the transmitter hardware state machine for this FCC.  
0 The transmitter is disabled. If ENT is cleared during transmission, the transmitter aborts the  
current character and TXD returns to idle state. Data in the transmit shift register is not sent.  
1 The transmitter is enabled.  
ENT can be set or cleared, regardless of whether serial clocks are present. See Section 28.12,  
ÒDisabling the FCCs On-the-Fly,Ó for a description of the proper methods to disable and reenable an  
FCC. Note that the FCC provides other tools for controlling transmission besides the ENT bitÑthe  
STOP TRANSMIT, GRACEFUL STOP TRANSMIT, and RESTART TRANSMIT commands, CTS ßow control,  
and TxBD[R].  
28Ð31 MODE Channel protocol mode  
0000 HDLC  
0001 Reserved for RAM microcode  
0010 Reserved  
0011 Reserved for RAM microcode  
0100 Reserved  
0101 Reserved for RAM microcode  
0110 Reserved  
0111 Reserved for RAM microcode  
1000 Reserved  
1001 Reserved for RAM microcode  
1010 ATM  
1011 Reserved for RAM microcode  
1100 Ethernet  
11xx Reserved  
28-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part IV. Communications Processor Module  
28.3 FCC Protocol-SpeciÞc Mode Registers  
(FPSMRx)  
The functionality of the FCC varies according to the protocol selected by GFMR[MODE].  
Each FCC has an additional 32-bit, memory-mapped, read/write protocol-speciÞc mode  
register (FPSMR) that conÞgures them speciÞcally for a chosen mode. The section for each  
speciÞc protocol describes the FPSMR bits.  
28.4 FCC Data Synchronization Registers (FDSRx)  
Each FCC has a 16-bit, memory-mapped, read/write data synchronization register (FDSR)  
that speciÞes the pattern used in the frame synchronization procedure of the synchronous  
protocols. In the totally transparent protocol, the FDSR should be programmed with the  
preferred SYNC pattern. For Ethernet protocol, it should be programmed with 0xD555. At  
reset, it defaults to 0x7E7E (two HDLC ßags), so it does not need to be written for HDLC  
mode. The FDSR contents are always sent lsb Þrst.  
Bits  
Field  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
SYN2  
SYN1  
Reset  
R/W  
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
R/W  
0x1130C (FDSR1), 0x1132C (FDSR2), 0x1132C (FDSR3)  
Address  
Table 28-2. FCC Data Synchronization Register (FDSR)  
28.5 FCC Transmit-on-Demand Registers (FTODRx)  
If no frame is being sent by the FCC, the CP periodically polls the R bit of the next TxBD  
to see if the user has requested a new frame/buffer to be sent. The polling algorithm depends  
on the FCC conÞguration, but occurs every 256 serial transmit clocks. The user, however,  
can request that the CP begin processing the new frame/buffer without waiting the normal  
polling time. For immediate processing, set the transmit-on-demand (TOD) bit in the  
transmit-on-demand register (TODR) after setting TxBD[R].  
This feature, which decreases the transmission latency of the transmit buffer/frame, is  
particularly useful in LAN-type protocols where maximum interframe GAP times are  
limited by the protocol speciÞcation. Since the transmit-on-demand feature gives a high  
priority to the speciÞed TxBD, it can conceivably affect the servicing of the other FCC  
FIFO buffers. Therefore, it is recommended that the transmit-on-demand feature be used  
only for a high-priority TxBD and when transmission on this FCC has not occurred for a  
given time period, which is protocol-dependent.  
If a new TxBD is added to the BD table while preceding TxBDs have not completed  
transmission, the new TxBD is processed immediately after the older TxBDs are sent.  
MOTOROLA  
Chapter 28. Fast Communications Controllers (FCCs)  
28-7  
                 
Part IV. Communications Processor Module  
Bits  
Field  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
TOD  
Ñ
Reset  
R/W  
0000_0000_0000_0000  
R/W  
Address  
0x11308 (FTODR1), 0x11328 (FTODR2), 0x11328 (FTODR3)  
Table 28-3. FCC Transmit-on-Demand Register (TODR)  
Fields in the TODR are described in Table 28-4  
Table 28-4. TODR Field Descriptions  
Field Name  
Description  
0
TOD Transmit on demand  
0
1
Normal polling.  
The CP gives high priority to the current TxBD and begins sending the frame does without waiting  
for the normal polling time to check TxBD[R]. TOD is cleared automatically.  
1Ð15  
Ñ
Reserved, should be cleared.  
28.6 FCC Buffer Descriptors  
Data associated with each FCC channel is stored in buffers. Each buffer is referenced by a  
buffer descriptor (BD) that can be anywhere in external memory.  
The BD table forms a circular queue with a programmable length. The user can program  
the start address of each channel BD table anywhere in memory. See Figure 28-3.  
28-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part IV. Communications Processor Module  
Dual-Port RAM  
External Memory  
Tx Buffer Descriptors  
Status and Control  
Data Length  
FCCx TxBD  
Table  
Buffer Pointer  
Tx Buffer  
Rx Buffer Descriptors  
FCCx RxBD  
Table  
Status and Control  
Data Length  
FCCx RxBD Table Pointer  
(RBASE)  
Buffer Pointer  
FCCx TxBD Table Pointer  
(TBASE)  
Rx Buffer  
Figure 28-3. FCC Memory Structure  
The format of transmit and receive BDs, shown in Figure 28-4, is the same for every FCC  
mode of operation except ATM mode; see Section 29.10.5, ÒATM Controller Buffer  
Descriptors (BDs).Ó The Þrst 16 bits in each BD contain status and control information,  
which differs for each protocol. The second 16 bits indicate the BD table length. The  
remaining 32-bits contain the 32-bit address pointer to the actual buffer in memory.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
offset + 0  
offset + 2  
offset + 4  
offset + 6  
Status and Control  
Data Length  
High-Order Data Buffer Pointer  
Low-Order Data Buffer Pointer  
Figure 28-4. Buffer Descriptor Format  
For frame-based protocols, a message can reside in as many buffers as necessary (transmit  
or receive). Each buffer has a maximum length of (64KÐ1) bytes. The CP does not assume  
that all buffers of a single frame are currently linked to the BD table. It does assume,  
however, that unlinked buffers are provided by the core soon enough to be sent or received.  
Failure to do so causes an error condition being reported by the CP. An underrun error is  
reported in the case of transmit; a busy error is reported in the case of receive. Because BDs  
are prefetched, the receive BD table must always contain at least one empty BD to avoid a  
busy error; therefore, RxBD tables must always have at least two BDs.  
MOTOROLA  
Chapter 28. Fast Communications Controllers (FCCs)  
28-9  
     
Part IV. Communications Processor Module  
The BDs and data buffers can be anywhere in the system memory.  
The CP processes the TxBDs in a straightforward fashion. Once the transmit side of an FCC  
is enabled, it starts with the Þrst BD in that FCCÕs TxBD table. When the CP detects that  
TxBD[R] is set, it begins processing the buffer. The CP detects that the BD is ready either  
by polling the R bit periodically or by the user writing to the TODR. When the data from  
the BD has been placed in the transmit FIFO buffer, the CP moves on to the next BD, again  
waiting for the R bit to be set. Thus, the CP does no look-ahead BD processing, nor does it  
skip over BDs that are not ready. When the CP sees the wrap (W) bit set in a BD, it goes  
back to the beginning of the BD table after processing of the BD is complete.  
After using a BD, the CP normally clears R (not-ready); thus, the CP does not use a BD  
again until the BD has been prepared by the core. Some protocols support continuous  
mode, which allows repeated transmission and for which the R bit remains set (always  
ready).  
The CP uses RxBDs in a similar fashion. Once the receive side of an FCC is enabled, it  
starts with the Þrst BD in the FCCÕs RxBD table. Once data arrives from the serial line into  
the FCC, the CP performs the required protocol processing on the data and moves the  
resultant data to the buffer pointed to by the Þrst BD. Use of a BD is complete when no  
room is left in the buffer or when certain events occur, such as the detection of an error or  
end-of-frame. Regardless of the reason, the buffer is then said to be closed and additional  
data is stored using the next BD. Whenever the CP needs to begin using a BD because new  
data is arriving, it checks the E bit of that BD. This check is made on a prefetched copy of  
the current BD. If the current BD is not empty, it reports a busy error. However, it does not  
move from the current BD until it is empty. Because there is a periodic prefetch of the  
RxBD, the busy error may recur if the BD is not prepared soon enough.  
When the CP sees the W bit set in a BD, it returns to the beginning of the BD table after  
processing of the BD is complete. After using a BD, the CP clears the E bit (not empty) and  
does not use a BD again until the BD has been processed by the core. However, in  
continuous mode, available to some protocols, the E bit remains set (always empty).  
28.7 FCC Parameter RAM  
Each FCC parameter RAM area begins at the same offset from each FCC base area. The  
protocol-speciÞc portions of the FCC parameter RAM are discussed in the speciÞc protocol  
descriptions. Table 28-5 shows portions common to all FCC protocols.  
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Part IV. Communications Processor Module  
Some parameter RAM values must be initialized before the FCC is enabled; other values  
are initialized/written by the CP. Once initialized, most parameter RAM values do not need  
to be accessed by user software because most activity centers around the TxBDs and  
RxBDs rather than the parameter RAM. However, if the parameter RAM is accessed, note  
the following:  
¥
¥
Parameter RAM can be read at any time.  
Tx parameter RAM can be written only when the transmitter is disabledÑafter a  
STOP TRANSMIT command and before a RESTART TRANSMIT command or after the  
buffer/frame Þnishes transmitting after a GRACEFUL STOP TRANSMIT command and  
before a RESTART TRANSMIT command.  
¥
¥
Rx parameter RAM can be written only when the receiver is disabled. Note the  
CLOSE RXBD command does not stop reception, but it does allow the user to extract  
data from a partially full Rx buffer.  
See Section 28.12, ÒDisabling the FCCs On-the-Fly.Ó  
Some parameters in Table 28-5 are not described and are listed only to provide information  
for experienced users and for debugging. The user need not access these parameters in  
normal operation.  
Table 28-5. FCC Parameter RAM Common to All Protocols  
1
Offset  
Name  
Width  
Description  
0x00  
RIPTR  
Hword Receive internal temporary data pointer. Used by microcode as a temporary buffer for  
data. Must be 32-byte aligned and the size of the internal buffer must be 32 bytes unless  
it is stated otherwise in the protocol speciÞcation. For best performance, it should be  
located in the following address ranges: 0x3000Ð0x4000 or 0xB000Ð0xC000.  
0x02  
TIPTR  
Hword Transmit internal temporary data pointer. Used by microcode as a temporary buffer for  
data. Must be 32-byte aligned and the size of the internal buffer must be 32 bytes unless  
it is stated otherwise in the protocol speciÞcation. For best performance it should be  
located in the following address ranges: 0x3000Ð0x4000 or 0xB000Ð0xC000.  
0x04  
0x06  
Ñ
Hword Reserved, should be cleared.  
MRBLR Hword Maximum receive buffer length (a multiple of 32 for all modes). The number of bytes that  
the FCC receiver writes to a receive buffer before moving to the next buffer. The receiver  
can write fewer bytes to the buffer than MRBLR if a condition such as an error or end-of-  
frame occurs, but it never exceeds the MRBLR value. Therefore, user-supplied buffers  
should be at least as large as the MRBLR.  
Note that FCC transmit buffers can have varying lengths by programming TxBD[Data  
Length], as needed, and are not affected by the value in MRBLR.  
MRBLR is not intended to be changed dynamically while an FCC is operating. Change  
MRBLR only when the FCC receiver is disabled.  
0x08  
RSTATE Word Receive internal state. The high byte, RSTATE[0Ð7], contains the function code register;  
see Section 28.7.1, ÒFCC Function Code Registers (FCRx).Ó RSTATE[8Ð31] is used by  
the CP and must be cleared initially.  
MOTOROLA  
Chapter 28. Fast Communications Controllers (FCCs)  
28-11  
 
Part IV. Communications Processor Module  
Table 28-5. FCC Parameter RAM Common to All Protocols (Continued)  
1
Offset  
Name  
Width  
Description  
0x0C  
RBASE  
Word RxBD base address (must be divisible by eight). DeÞnes the starting location in the  
memory map for the FCC RxBDs. This provides great ßexibility in how FCC RxBDs are  
partitioned. By selecting RBASE entries for all FCCs and by setting the W bit in the last  
BD in each BD table, the user can select how many BDs to allocate for the receive side  
of every FCC. The user must initialize RBASE before enabling the corresponding  
channel. Furthermore, the user should not conÞgure BD tables of two enabled FCCs to  
overlap or erratic operation occurs.  
0x10 RBDSTAT Hword RxBD status and control. Reserved for CP use only.  
0x12  
0x14  
0x18  
RBDLEN Hword RxBD data length. A down-count value initialized by the CP with MRBLR and  
decremented with every byte written by the SDMA channels.  
RDPTR  
Word RxBD data pointer. Updated by the SDMA channels to show the next address in the  
buffer to be accessed.  
TSTATE Word Tx internal state. The high byte, TSTATE[0Ð7], contains the function code register; see  
Section 28.7.1, ÒFCC Function Code Registers (FCRx).Ó TSTATE[8Ð31] is used by the  
CP and must be cleared initially.  
0x1C  
TBASE  
Word TxBD base address (must be divisible by eight). DeÞnes the starting location in the  
memory map for the FCC TxBDs. This provides great ßexibility in how FCC TxBDs are  
partitioned. By selecting TBASE entries for all FCCs and by setting the W bit in the last  
BD in each BD table, the user can select how many BDs to allocate for the transmit side  
of every FCC. The user must initialize TBASE before enabling the corresponding  
channel. Furthermore, the user should not conÞgure BD tables of two enabled FCCs to  
overlap or erratic operation occurs.  
0x20 TBDSTAT Hword TxBD status and control. Reserved for CP use only.  
0x22  
0x24  
0x28  
TBDLEN Hword TxBD data length. A down-count value initialized with the TxBD data length and  
decremented with every byte read by the SDMA channels.  
TDPTR  
Word TxBD data pointer. Updated by the SDMA channels to show the next address in the  
buffer to be accessed.  
RBPTR  
Word RxBD pointer. Points to the next BD that the receiver transfers data to when it is in idle  
state or to the current BD during frame processing. After a reset or when the end of the  
BD table is reached, the CP sets RBPTR = RBASE. Although the user need never write  
to RBPTR in most applications, the user can modify it when the receiver is disabled or  
when no receive buffer is in use.  
0x2C  
TBPTR  
Word TxBD pointer. Points either to the next BD that the transmitter transfers data from when it  
is in idle state or to the current BD during frame transmission. After a reset or when the  
end of the BD table is reached, the CP sets TBPTR = TBASE. Although the user need  
never write to TBPTR in most applications, the user can modify it when the transmitter is  
disabled or when no transmit buffer is in use (after a STOP TRANSMIT or GRACEFUL STOP  
TRANSMIT command is issued and the frame completes transmission).  
0x30  
0x34  
0x38  
RCRC  
TCRC  
Word Temporary receive CRC  
Word Temporary transmit CRC  
First word of protocol-speciÞc area  
1
Offset from FCC base: 0x8400 (FCC1), 0x8500 (FCC2) and 0x8600 (FCC3); see Section 13.5.2, ÒParameter RAM.Ó  
28-12  
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Part IV. Communications Processor Module  
28.7.1 FCC Function Code Registers (FCRx)  
The function code registers contain the transaction speciÞcation associated with SDMA  
channel accesses to external memory. Figure 28-5 shows the format of the transmit and  
receive function code registers, which reside at TSTATE[0Ð7] and RSTATE[0Ð7] in the  
FCC parameter RAM (see Table 28-5).  
Bits  
0
1
2
3
4
5
6
7
Field  
Ñ
GBL  
BO  
TC2  
DTB  
BDB  
Figure 28-5. Function Code Register (FCRx)  
FCRx Þelds are described in Table 28-6.  
Table 28-6. FCRx Field Descriptions  
Bits Name  
Description  
0Ð1  
2
Ñ
Reserved, should be cleared.  
GBL Global. Indicates whether the memory operation should be snooped.  
0 Snooping disabled.  
1 Snooping enabled.  
3Ð4 BO Byte ordering. Used to select the byte ordering of the buffer. If BO is modiÞed on-the-ßy, it takes effect  
at the start of the next frame (Ethernet, HDLC, and transparent) or at the beginning of the next BD.  
01 PowerPC little-endian byte ordering. As data is sent onto the serial line from the data buffer, the  
LSB of the buffer double-word contains data to be sent earlier than the MSB of the same buffer  
double-word.  
10 Motorola byte ordering (normal operation). It is also called big-endian byte ordering. As data is sent  
onto the serial line from the data buffer, the MSB of the buffer word contains data to be sent earlier  
than the LSB of the same buffer word.  
5
6
TC2 Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory  
access. TC[0Ð1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.  
DTB Indicates on what bus the data is located.  
0 On the 60x bus.  
1 On the local.  
7
BDB Indicates on what bus the BDs are located.  
0 On the 60x bus.  
1 On the local bus.  
28.8 Interrupts from the FCCs  
Interrupt handling for each of the FCC channels is conÞgured on a global (per channel)  
basis in the interrupt pending register (SIPNR_L) and interrupt mask register (SIMR_L).  
One bit in each register is used to either mask, enable, or report an interrupt in an FCC  
channel. The interrupt priority between the FCCs is programmable in the CPM interrupt  
priority register (SCPRR_H). The interrupt vector register (SIVEC) indicates which  
pending channel has highest priority. Registers within the FCCs manage interrupt handling  
for FCC-speciÞc events.  
MOTOROLA  
Chapter 28. Fast Communications Controllers (FCCs)  
28-13  
           
Part IV. Communications Processor Module  
Events that can cause the FCC to interrupt the processor vary slightly among protocols and  
are described with each protocol. These events are handled independently for each channel  
by the FCC event and mask registers (FCCE and FCCM).  
28.8.1 FCC Event Registers (FCCEx)  
Each FCC has a 24-bit FCC event register (FCCE) used to report events. On recognition of  
an event, the FCC sets its corresponding FCCE bit regardless of the corresponding mask  
bit. To the user it appears as a memory-mapped register that can be read at any time. Bits  
are cleared by writing ones; writing zeros has no effect on bit values. FCCE is cleared at  
reset. Fields of this register are protocol-dependent and are described in the respective  
protocol sections.  
28.8.2 FCC Mask Registers (FCCMx)  
Each FCC has a 24-bit, read/write FCC mask register (FCCM) used to enable or disable CP  
interrupts to the core for events reported in an event register (FCCE). Bit positions in  
FCCM are identical to those in FCCE. Note that an interrupt is generated only if the FCC  
interrupts are also enabled in the SIU; see Section 4.3.1.5, ÒSIU Interrupt Mask Registers  
(SIMR_H and SIMR_L).Ó  
If an FCCM bit is zero, the CP does not proceed with its usual interrupt handling whenever  
that event occurs. Any time a bit in the FCCM register is set, a 1 in the corresponding bit in  
the FCCE register sets the FCC event bit in the interrupt pending register; see  
Section 4.3.1.4, ÒSIU Interrupt Pending Registers (SIPNR_H and SIPNR_L).Ó  
28.8.3 FCC Status Registers (FCCSx)  
Each FCC has an 8-bit, read/write FCC status register (FCCS) that lets the user monitor  
real-time status conditions (ßags, idle) on the RXD line. It does not show the status of CTS  
and CD; their real-time status is available in the appropriate parallel I/O port (see  
Chapter 35, ÒParallel I/O PortsÓ).  
28.9 FCC Initialization  
The FCCs require a number of registers and parameters to be conÞgured after a power-on  
reset. The following outline gives the proper sequence for initializing the FCCs, regardless  
of the protocol used.  
1. Write the parallel I/O ports to conÞgure and connect the I/O pins to the FCCs.  
2. Write the appropriate port registers to conÞgure CTS and CD to be parallel I/O with  
interrupt capability or to connect directly to the FCC (if modem support is needed).  
3. If the TSA is used, the SI must be conÞgured. If the FCC is used in the NMSI mode,  
the CPM multiplexing logic (CMX) must still be initialized.  
4. Write the GFMR, but do not write the ENT or ENR bits yet.  
5. Write the FPSMR.  
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Part IV. Communications Processor Module  
6. Write the FDSR.  
7. Initialize the required values for this FCC in its parameter RAM.  
8. Clear out any current events in FCCE, as needed.  
9. Write the FCCM register to enable the interrupts in the FCCE register.  
10.Write the SCPRR_H to conÞgure the FCC interrupt priority.  
11.Clear out any current interrupts in the SIPNR_L, if preferred.  
12.Write the SIMR_L to enable interrupts to the CP interrupt controller.  
13.Issue an INIT TX AND RX PARAMETERS command (with the correct protocol number).  
14.Set GFMR[ENT] and GFMR[ENR].  
The Þrst RxBDÕs empty bit must be set before the INIT RX COMMAND. However TxBDs can  
have their ready bits set at any time. Notice that the CPCR does not need to be accessed  
after a power-on reset until an FCC is to be used. An FCC should be disabled and reenabled  
after any dynamic change in its parallel I/O ports or serial channel physical interface  
conÞguration. A full reset using CPCR[RST] is a comprehensive reset that also can be used.  
28.10 FCC Interrupt Handling  
The following describes what usually occurs within an FCC interrupt handler:  
1. When an interrupt occurs, read FCCE to determine interrupt sources. FCCE bits to  
be handled in this interrupt handler are normally cleared at this time.  
2. Process the TxBDs to reuse them if the FCCE[TX,TXE] were set. If the transmit  
speed is fast or the interrupt delay is long, more than one transmit buffer may have  
been sent by the FCC. Thus, it is important to check more than just one TxBD during  
the interrupt handler. One common practice is to process all TxBDs in the interrupt  
handler until one is found with R set.  
3. Extract data from the RxBD if FCCE[RX, RXB, or RXF] is set. If the receive speed  
is fast or the interrupt delay is long, the FCC may have received more than one  
receive buffer. Thus, it is important to check more than just one RxBD during  
interrupt handling. Typically, all RxBDs in the interrupt handler are processed until  
one is found with E set. Because the FCC prefetches BDs, the BD table must be big  
enough such that always there will be another empty BD to prefetch.  
4. Clear FCCE.  
5. Continue normal execution.  
28.11 FCC Timing Control  
When GFMR[DIAG] is programmed to normal operation, CD and CTS are automatically  
controlled by the FCC. GFMR[TCI] is assumed to be cleared, which implies normal  
transmit clock operation.  
MOTOROLA  
Chapter 28. Fast Communications Controllers (FCCs)  
28-15  
         
Part IV. Communications Processor Module  
RTS is asserted when FCC has data to transmit in the transmit FIFO and a falling transmit  
clock occurs. At this point, the FCC begins sending the data, once the appropriate  
conditions occur on CTS. In all cases, the Þrst bit of data is the start of the opening ßag, or  
sync pattern.  
Figure 28-6 shows that the delay between RTS and data is 0 bit times, regardless of the  
setting of GFMR[CTSS]. This operation assumes that CTS is either already asserted to the  
FCC or is reprogrammed to be a parallel I/O line, in which case the CTS signal to the FCC  
is always asserted. RTS is negated one clock after the last bit in the frame.  
TCLK  
TXD  
(Output)  
RTS  
(Output)  
First Bit of Frame Data  
Last Bit of Frame Data  
CTS  
(Input)  
Note:  
1. A frame includes opening and closing flags and syncs, if present in the protocol.  
Figure 28-6. Output Delay from RTS Asserted  
If CTS is not already asserted when RTS is asserted, the delays to the Þrst bit of data depend  
on when CTS is asserted. Figure shows that the delay between CTS and the data can be  
approximately 0.5- to 1-bit time in asynchronous mode (if GFMR[CTSS] = 0) or 0 bit times  
(if GFMR[CTSS] = 1).  
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Part IV. Communications Processor Module  
TCLK  
TXD  
(Output)  
RTS  
(Output)  
First Bit Of Frame Data  
CTS Sampled Low  
Last Bit of Frame Data  
CTS  
(Input)  
Note:  
1. GFMR_H[CTSS] = 0. CTSP is a donÕt care.  
TCLK  
TXD  
(Output)  
RTS  
(Output)  
First Bit of Frame Data  
Last Bit of Frame Data  
CTS  
(Input)  
Note:  
1. GFMR_H[CTSS] = 1. CTSP is a donÕt care.  
Figure 28-7. Output Delay from CTS Asserted  
If it is programmed to envelope the data, CTS must remain asserted during frame  
transmission or a CTS lost error occurs. The negation of CTS forces RTS high and the  
transmit data to the idle state. If GFMR[CTSS] = 0, the FCC must sample CTS before a  
CTS lost is recognized. Otherwise, the negation of CTS immediately causes the CTS lost  
condition. See Figure 28-8.  
MOTOROLA  
Chapter 28. Fast Communications Controllers (FCCs)  
28-17  
 
Part IV. Communications Processor Module  
TCLK  
TXD  
(Output)  
Data Forced High  
RTS Forced High  
First Bit of Frame Data  
RTS  
(Output)  
CTS  
(Input)  
CTS Sampled Low  
CTS Sampled High  
CTS Lost Signaled in BD  
Note:  
1. GFMR_H[CTSS] = 0. CTSP=0 or no CTS lost can occur.  
TCLK  
TXD  
(Output)  
Data Forced High  
RTS Forced High  
First Bit of Frame Data  
RTS  
(Output)  
CTS  
(Input)  
CTS Lost Signaled in BD  
Note:  
1. GFMR_H[CTSS] = 1. CTSP=0 or no CTS lost can occur.  
Figure 28-8. CTS Lost  
Note that if GFMR[CTSS] = 1, all CTS transitions must occur while the transmit clock is  
low.  
Reception delays are determined by CD as Figure 28-9 shows. If GFMR[CDS] = 0, CD is  
sampled on the rising receive clock edge before data is received. If GFMR[CDS] = 1, CD  
transitions immediately cause data to be gated into the receiver.  
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Part IV. Communications Processor Module  
RCLK  
RXD  
(Input)  
CD  
(Input)  
First Bit of Frame Data  
CD Sampled Low  
Last Bit of Frame Data  
CD Sampled High  
Notes:  
1. GFMR_H[CDS] = 0. CDP=0.  
2. If CD is negated prior to the last bit of the receive frame, CD lost is signaled in the BD.  
3. If CDP=1, CD lost cannot occur and CD negation has no effect on reception.  
RCLK  
RXD  
(Input)  
CD  
(Input)  
First Bit of Frame Data  
Last Bit of Frame Data  
CD Assertion Immediately  
Gates Reception  
CD Negation Immediately  
Halts Reception  
Notes:  
1. GFMR_H[CDS] = 1. CDP=0.  
2. If CD is negated prior to the last bit of the receive frame, CD lost is signaled in the BD.  
3. If CDP=1, CD lost cannot occur and CD negation has no effect on reception.  
Figure 28-9. Using CD to Control Reception  
If it is programmed to envelope data, CD must remain asserted during frame transmission  
or a CD lost error occurs. The negation of CD terminates reception. If [CDS] = 0, CD must  
be sampled by the FCC before a CD lost is recognized. Otherwise, the negation of CD  
immediately causes the CD lost condition.  
Note that if GFMR[CDS] = 1, all CD transitions must occur while the receive clock is low.  
28.12 Disabling the FCCs On-the-Fly  
Unused FCCs can be temporarily disabled. In this case, a operation sequence is followed  
that ensures that any buffers in use are closed properly and that new data is transferred to  
or from a new buffer. Such a sequence is required if the parameters that must be changed  
are not allowed to be changed dynamically. If the register or bit description states that  
dynamic changes are allowed, the following sequences are not required and the register or  
bit may be changed immediately. In all other cases, the sequence should be used.  
Modifying parameter RAM does not require the FCC to be fully disabled. See the  
parameter RAM description for when values can be changed. To disable all peripheral  
controllers, set CPCR[RST] to reset the entire CPM.  
MOTOROLA  
Chapter 28. Fast Communications Controllers (FCCs)  
28-19  
     
Part IV. Communications Processor Module  
28.12.1 FCC Transmitter Full Sequence  
For the FCC transmitter, the full disable and enable sequence is as follows.  
1. Issue the STOP TRANSMIT command. This is recommended if the FCC is currently  
transmitting data because it stops transmission in an orderly way. If the FCC is not  
transmitting (no TxBDs are ready or the GRACEFUL STOP TRANSMIT command has  
been issued and completed), then the STOP TRANSMIT command is not required.  
Furthermore, if the TBPTR is overwritten by the user or the INIT TX PARAMETERS  
command is executed, this command is not required.  
2. Clear GFMR[ENT]. This disables the FCC transmitter and puts it in a reset state.  
3. Make changes. The user can modify FCC transmit parameters, including the  
parameter RAM. To switch protocols or restore the FCC transmit parameters to their  
initial state, the INIT TX PARAMETERS command must be issued.  
4. If an INIT TX PARAMETERS command was not issued in step 3, issue a RESTART  
TRANSMIT command.  
5. Set GFMR[ENT]. Transmission begins using the TxBD that the TBPTR points to as  
soon as TxBD[R] = 1.  
28.12.2 FCC Transmitter Shortcut Sequence  
A shorter sequence is possible if the user prefers to reinitialize the transmit parameters to  
the state they had after reset. This sequence is as follows:  
1. Clear GFMR[ENT].  
2. Issue the INIT TX PARAMETERS command. Any additional changes can be made now.  
3. Set GFMR[ENT].  
28.12.3 FCC Receiver Full Sequence  
The full disable and enable sequence for the receiver is as follows:  
1. Clear GFMR[ENR]. Reception is aborted immediately, which disables the receiver  
of the FCC and puts it in a reset state.  
2. Make changes. The user can modify the FCC receive parameters, including the  
parameter RAM. If the user prefers to switch protocols or restore the FCC receive  
parameters to their initial state, the INIT RX PARAMETERS command must be issued.  
3. Issue the ENTER HUNT MODE command. This command is required if the INIT RX  
PARAMETERS command was not issued in step 2.  
4. Set GFMR[ENR]. Reception begins immediately using the RxBD that the RBPTR  
points to if RxBD[E] = 1.  
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28.12.4 FCC Receiver Shortcut Sequence  
A shorter sequence is possible if the user prefers to reinitialize the receive parameters to the  
state they had after reset. This sequence is as follows:  
1. Clear GFMR[ENR].  
2. Issue the INIT RX PARAMETERS command. Any additional changes can be made now.  
3. Set GFMR[ENR].  
28.12.5 Switching Protocols  
A user can switch the protocol that the FCC is executing (HDLC) without resetting the  
board or affecting any other FCC by taking the following steps:  
1. Clear GFMR[ENT] and GFMR[ENR].  
2. Issue the INIT TX AND RX PARAMETERS command. This command initializes both  
transmit and receive parameters. Additional changes can be made in the GFMR to  
change the protocol.  
3. Set GFMR[ENT] and GFMR[ENR]. The FCC is enabled with the new protocol.  
28.13 Saving Power  
Clearing an FCCÕs ENT and ENR bits minimizes its power consumption.  
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Chapter 28. Fast Communications Controllers (FCCs)  
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Chapter 29  
ATM Controller  
290  
2T90 he ATM controller provides the ATM and AAL layers of the ATM protocol using the  
universal test and operations physical layer (PHY) interface forATM (UTOPIA level II) for  
both master and slave modes. It performs segmentation and reassembly (SAR) functions of  
AAL5, AAL1, and AAL0, and most of the common parts of the convergence sublayer (CP-  
CS) of these protocols.  
For each virtual channel (VC), the controllerÕs ATM pace control (APC) unit generates a  
cell transmission rate to implement constant bit rate (CBR), variable bit rate (VBR),  
available bit rate (ABR), unspeciÞed bit rate (UBR) or UBR+ trafÞc. To regulate VBR  
trafÞc, theAPC unit performs a continuous-state leaky bucket algorithm. TheAPC unit also  
uses up to eight priority levels to prioritize real-time ATM channels, such as CBR and real-  
time VBR, over non-real-time ATM channels such as VBR, ABR and UBR.  
The ATM controller performs the ATM Forum (UNI-4.0) ABR ßow control. To perform  
feedback rate adaptation, it supports forward and backward resource management (RM)  
cell generation and ATM Forum ßoating-point calculation. ABR ßow control is  
implemented in hardware and Þrmware (without software intervention) to prevent potential  
delays during backward RM cell processing and feedback rate adaptation.  
The MPC8260 supports a special mode for ATM/TDM interworking. The CPM performs  
automatic data forwarding between ATM channels and the MCCsÕ TDM channels without  
core intervention.  
The MPC8260 ATM SAR controller applications are as follows:  
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ATM line card controllers  
ATM-to-WAN interworking (frame relay, T1/E1 circuit emulation)  
Residential broadband network interface units (NIU) (ATM-to-Ethernet)  
High-performance ATM network interface cards (NIC)  
Bridges and routers with ATM interface  
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29.1 Features  
The ATM controller has the following features:  
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Full duplex segmentation and reassembly at 155 Mbps  
UTOPIA level II master and slave modes 8/16 bit  
AAL5, AAL1, AAL0 protocols  
Up to 255 active VCs internally, and up to 64K VCs using external memory  
TM 4.0 CBR, VBR, UBR, UBR+ trafÞc types  
VBR type 1 and 2 trafÞc using leaky buckets (GCRA)  
TM 4.0 ABR ßow control (EFCI and ER)  
Idle/unassign cells screening/transmission option  
External and internal rate transmit modes  
Special mode for ATM-to-TDM or ATM-to-ATM data forwarding  
CLP and congestion indication marking  
User-deÞned cells up to 65 bytes  
Separate Tx and RxBD tables for each virtual channel (VC)  
Special mode of global free buffer pools for dynamic and efÞcient memory  
allocation with early packet discard (EPD) support  
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Interrupt report per channel using four priority interrupt queues  
Compliant with ATMF UNI 4.0 and ITU speciÞcation  
AAL5 cell format  
Ñ Reassembly  
Ð Reassemble PDU directly to external memory  
Ð CRC32 check  
Ð CLP and congestion report  
Ð CPCS_UU, CPI, and length check  
Ð Abort message report  
Ñ Segmentation  
Ð Segment PDU directly from external memory  
Ð Performs PDU padding  
Ð CRC32 generation  
Ð Automatic last cell marking  
Ð Automatic CPCS_UU, CPI, and length insertion  
Ð Abort message option  
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AAL1 cell format  
Ñ Reassembly  
Ð Reassemble PDU directly to external memory  
Ð Support for partially Þlled cells (conÞgurable on a per-VC basis)  
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Chapter 29. ATM Controller  
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Ð Sequence number check  
Ð Sequence number protection (CRC-3 and parity) check  
Ñ Segmentation  
Ð Segment PDU directly from external memory  
Ð Partially Þlled cells support (conÞgurable on a per-VC basis)  
Ð Sequence number generation  
Ð Sequence number protection (CRC-3 and even parity) generation  
Ñ Structured AAL1 cell format  
Ð Automatic synchronization using the structured pointer during reassembly  
Ð Structured pointer generation during segmentation  
Ñ Unstructured AAL1 cell format  
Ð Clock recovery using external SRTS (synchronous residual time stamp) logic  
during reassembly  
Ð SRTS generation using external logic during segmentation  
AAL0 format  
¥
Ñ Receive  
Ð Whole cell is put in memory  
Ð CRC10 pass/fail indication  
Ñ Transmit  
Ð Reads a whole cell from memory  
Ð CRC10 insertion option  
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Support for user-deÞned cells  
Ñ Support cells up to 65 bytes  
Ñ Extra header insert/load on a per-frame basis  
Ñ Extra header size has byte resolution  
Ñ Asymmetric cell size for send and receive  
Ñ HEC octet insertion option  
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PHY  
Ñ UTOPIA level II supports 8/16 bits 25/50 MHz  
Ð Supports UTOPIA master and slave modes  
Ð Supports cell-level handshake  
Ð Supports multiple-PHY polling mode  
ATM pace control (APC) unit  
Ñ Peak cell rate pacing on a per-VC basis  
Ñ Peak-and-sustain cell rate pacing using GCRA on a per-VC basis  
Ñ Peak-and-minimum cell rate pacing on a per-VC basis  
Ñ Up to eight priority levels  
Ñ Fully managed by CP with no host intervention  
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Available bit rate (ABR)  
Ñ Performs ATMF UNI 4.0 ABR ßow control on a per-VC basis  
Ñ Automatic forward-RM, backward-RM cells generation  
Ñ Automatic feedback rate adaptation  
Ñ Support for EFCI (explicit forward congestion indication) and ER (explicit rate)  
Ñ RM cell ßoating-point calculations  
Ñ Fully managed by CP with no host intervention  
Receive address look-up mechanism  
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Ñ Two modes of address look-up are supported  
Ð External CAM  
Ð Address compression  
OAM (operations and maintenance) cells  
Ñ OAM Þltering according to PTI Þeld and reserved VCI Þeld  
Ñ Raw cell queues for transmission and reception  
Ñ CRC-10 generation/check  
Ñ Performance monitoring support  
Ð Support up to 64 bidirectional block tests simultaneously  
Ð Automatic FMC and BRC cell generation and termination  
Ð User transmit cell count  
0+1  
Ð User transmit cell count  
0
Ð PM cells time stamp insertion  
Ð Block error detection code (BEDC ) generation/check  
0+1  
Ð Total receive cell count  
0+1  
Ð Total receive cell count  
0
Ñ Specifying channel code for F5 OAM cells  
ATM layer statistic gathering on a per PHY basis.  
Ñ UTOPIA receiver error cells count (Rx parity error or short/long cells error)  
Ñ Misinserted cell count  
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Ñ CRC-10 error cells count (ABR ßow only)  
Memory management  
Ñ RxBD table per VC with option of global free buffer pool for AAL5  
Ñ TxBD table per VC  
29.2 ATM Controller Overview  
The following sections provide an overview of the transmitter and receiver portions of the  
ATM controller.  
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29.2.1 Transmitter Overview  
Before the transmitter is enabled, the host must initialize the MPC8260 and create the  
transmit data structure, described in Section 29.10, ÒATM Memory Structure.Ó When data  
is ready for transmission, the host arranges the BD table and writes the pointer of the Þrst  
BD in the transmit connection table (TCT). The host issues an ATM TRANSMIT command,  
which inserts the current channel to the ATM pace control (APC) unit. The APC unit  
controls the ATM trafÞc of the transmitter. It reads the trafÞc parameters of each channel  
and divides the total bandwidth among them. The APC unit can pace the peak cell rate,  
peak-and-sustain cell rate (GCRA trafÞc) or peak-and-minimum cell rate trafÞc. The APC  
implements up to eight priority levels for servicing real-time channels before non-real-time  
channels.  
The transmitter ATM cell is 53Ð65 bytes and includes 4 bytes of ATM cell header, a 1-byte  
HEC, and 48 bytes of payload. The HEC is a constant taken from FDSRx[0Ð15] when using  
UTOPIA 16 and from FDSRx[8Ð15] when using UTOPIA 8; see Section 28.4, ÒFCC Data  
Synchronization Registers (FDSRx).Ó User-deÞned cells (UDC mode) include an extra  
header of 1Ð12 bytes with an optional HEC octet. Cell transfers use the UTOPIA level II,  
cell-level handshake.  
Transmission starts when the APC schedules a channel. According to the channel code, the  
ATM controller reads the channelÕs entry in the TCT and opens the Þrst BD for  
transmission.  
29.2.1.1 AAL5 Transmitter Overview  
The transmitter reads 48 bytes from the external buffer, adds the cell header, and sends the  
cell through the UTOPIA interface. The transmitter adds any padding needed and appends  
the AAL5 trailer in the last cell of the AAL5 frame. The trailer consists of CPCS-UU+CPI,  
data length, and CRC-32 as deÞned in ITU I.363. The CPCS-UU+CPI (2-byte entry) can  
be speciÞed by the user or optionally cleared by the transmitter; see Section 29.10.2.3,  
ÒTransmit Connection Table (TCT).Ó The transmitter identiÞes the last cell of the AAL5  
message by setting the last (L) indication bit in the PTI Þeld of the cell header. An interrupt  
may be generated to indicate the end of the frame.  
When the transmission of the current frame ends and no additional valid buffers are in the  
BD table, the transmit process ends. The transmitter keeps polling the BD table every time  
this channel is scheduled to transmit. In auto-VC-off mode, the APC automatically  
deactivates the current channel when no buffer is ready to transmit. In this case, a new ATM  
TRANSMIT command is needed for transmission of theVC to resume. Note that a buffer-not-  
ready indication during frame transmission aborts the frame transfer.  
29.2.1.2 AAL1 Transmitter Overview  
The MPC8260 supports both structured and unstructured AAL1 formats. For the  
unstructured format, the transmitter reads 47 bytes from the external buffer and inserts them  
into the AAL1 user data Þeld. The AAL1 PDU header, which consists of the sequence  
number (SN) and the sequence number protection (SNP) (CRC-3 and parity bit), is  
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generated and inserted into the cell. The MPC8260 supports synchronous residual time  
stamp (SRTS) generation using external PLL. If this mode is enabled, the MPC8260 reads  
the SRTS code from the external logic and inserts it into four outgoing cells. See  
Section 29.15, ÒSRTS Generation and Clock Recovery Using External Logic.Ó  
For the structured format, the transmitter reads 47 or 46 bytes from the external buffer and  
inserts them into the AAL1 user data Þeld. The CP generates the AAL1 PDU header and  
inserts it into the cell. The header consists of the SN, SNP, and the structured pointer.  
The MPC8260 supports partially Þlled cells conÞgured on a per-VC basis; only valid octets  
are copied from the TxBD to the ATM cell. The rest of the cell is Þlled with padding octets.  
29.2.1.3 AAL0 Transmitter Overview  
No speciÞc adaptation layer is provided for AAL0. The ATM controller reads a whole cell  
from an external buffer, which always contains exactly one AAL0 cell. The ATM controller  
optionally generates CRC10 on the cell payload and places it at the end of the payload  
(CRC10 Þeld). AAL0 mode can be used to send OAM cells or AAL3/4 raw cells.  
29.2.1.4 Transmit External Rate and Internal Rate Modes  
The ATM controller supports the following two rate modes:  
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External rate modeÑThe total transmission rate is determined by the PHY  
transmission rate. The FCC sends cells to keep the PHY FIFOs full; the FCC inserts  
idle/unassign cells to maintain the transmission rate.  
Internal rate modeÑThe total transmission rate is determined by the FCC internal  
rate timers. In this mode, the FCC does not insert idle/unassign cells. The internal  
rate mechanism is supported for the Þrst four PHY devices (PHY address 00-03).  
Each PHY has its own FTIRR, described in Section 29.13.4, ÒFCC Transmit Internal  
Rate Registers (FTIRRx).Ó The FTIRR includes the initial value of the internal rate  
timer. A cell transmit request is sent when an internal rate timer expires. When using  
internal rate mode, the user assigns one of the baud-rate generators (BRGs) to clock  
the four internal rate timers.  
29.2.2 Receiver Overview  
Before the receiver is enabled, the host must initialize the MPC8260 and create the receive  
data structure described in Section 29.10, ÒATM Memory Structure.Ó The host arranges a  
BD table for each ATM channel. Buffers for each connection can be statically allocated  
(that is, each BD in the BD table is associated with a Þxed buffer location) or in the case of  
AAL5, can be fetched by the CP from a global free buffer pool. See Section 29.10.5, ÒATM  
Controller Buffer Descriptors (BDs).Ó  
The receiver ATM cell size is 53-65 bytes. The cell includes: 4 bytes ATM cell header, 1  
byte HEC, which is ignored, and 48 bytes payload. User-deÞned cells (UDC mode) include  
an extra header of 1Ð12 bytes with an optional HEC octet. Cell transfers use the UTOPIA  
level II, cell-level handshake.  
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Reception starts when the PHY asserts the receive cell available signal (RxCLAV) to  
indicate that the PHY has a complete cell in its receive FIFO. The receiver reads a complete  
cell from the UTOPIA interface and translates the header address (VP/VC) to a channel  
code by performing an address look-up. If no matches are found, the cell is discarded and  
the user-network interface (UNI) statistics tables are updated. The receiver uses the channel  
code to read the channel parameters from the receive connection table (RCT).  
29.2.2.1 AAL5 Receiver Overview  
The receiver copies the 48-byte cell payload to the external buffer and calculates CRC-32  
on the entire CPCS-PDU. When the last AAL5 cell arrives, the receiver checks the length,  
CRC-32, and CPCS-UU+CPI Þelds and sets the corresponding RxBD status bits. An  
interrupt may be generated to one of the four interrupt queues. The receiver copies the last  
cell to memory including the padding and the AAL5 trailer. The CPCS-UU+CPI (16-bit  
entry) may be read directly from the AAL5 trailer.  
The ATM controller monitors the CLP and CNG state of the incoming cells. When the  
message is closed, these events set RxBD[CLP] and RxBD[CNG].  
When no buffer is ready to receive cells (busy state), the receiver switches to hunt state and  
drops all cells associated with the current frame (partial packet discard). The receiver tries  
to open new buffers for cell reception only after the last cell of the discarded AAL5 frame  
arrives.  
29.2.2.2 AAL1 Receiver Overview  
The ATM controller supports both AAL1 structured and unstructured formats. For the  
unstructured format, 47 octets are copied to the current receive buffer. The AAL1 PDU  
header, which consists of the sequence number (SN) and the sequence number protection  
(SNP) (CRC-3 and parity bit), is checked. The MPC8260 supports SRTS clock recovery  
using an external PLL. In this mode, the MPC8260 tracks the SRTS from the four incoming  
cells and writes the SRTS code to external logic. See Section 29.15, ÒSRTS Generation and  
Clock Recovery Using External Logic.Ó  
In the unstructured format, when the receive process begins, the receiver hunts for the Þrst  
cell with a valid sequence number (SN Þeld). When one arrives, the receiver leaves the hunt  
state and starts receiving. If an SN mismatch is detected, the receiver closes the RxBD, sets  
RxBD[SNE], and switches to hunt state, where it stays until a cell with a valid SN Þeld is  
received.  
For the structured format, 47 or 46 octets are copied to the current receive buffer. TheAAL1  
PDU header, which consists of SN and SNP, is checked and the PDU status is written to the  
BD.  
In the structured format, when the receive process begins, the receiver hunts for the Þrst cell  
with a valid structured pointer to gain synchronization. When one arrives, the receiver  
leaves the hunt state and starts receiving. Then the receiver opens a new buffer. The  
structured pointer points to the Þrst octet of the structured block, which then becomes the  
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Þrst byte of the new buffer. If an SN mismatch is detected, the ATM receiver closes the  
current RxBD, sets RxBD[SNE], and returns to the hunt state. The receiver then waits for  
a cell with a valid structured pointer to regain synchronization.  
The MPC8260 supports partially Þlled cells conÞgured on a per-VC basis. In this mode, the  
ATM controller copies only the valid octets from the cell user data Þeld to the buffer.  
29.2.2.3 AAL0 Receiver Overview  
For AAL0, no speciÞc adaptation layer processing is done. The ATM controller copies the  
whole cell to an external buffer. Each buffer contains exactly one AAL0 cell. The ATM  
controller calculates and checks the CRC10 of the cell payload and sets RxBD[CRE] if a  
CRC error occurs.AAL0 mode can be useful for receiving OAM cells orAAL3/4 raw cells.  
29.2.3 Performance Monitoring  
The ATM controller supports performance monitoring testing according to ITU I.610.  
When performance monitoring is enabled, the ATM controller automatically generates and  
terminates FMCs (forward monitoring cells) and BRCs (backward reporting cells). See  
Section 29.6.6, ÒPerformance Monitoring.Ó  
29.2.4 ABR Flow Control  
When AAL5-ABR is enabled, the ATM controller implements the ATM Forum TM 4.0  
available-bit-rate ßow. It automatically inserts forward- and backward-RM cells into the  
user cells stream and adjusts the transmission rate according to the backwards RM cell  
feedback; see Section 29.10.2.2.2, ÒAAL5-ABR Protocol-SpeciÞc RCT.Ó The ABR ßow is  
controlled on a per-VC basis.  
29.3 ATM Pace Control (APC) Unit  
The ATM pace control (APC) unit schedules the ATM channels for transmitting. While  
performing this task, the APC unit uses the following parameters:  
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Frequency (bandwidth) of each ATM channel  
ATM trafÞc pacingÑPeak cell rate (PCR), sustain cell rate (SCR), and minimum  
rate (MCR)  
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Priority levelÑReal-time channels (CBR orVBR-RT) are scheduled at high-priority  
levels; non-real-time channels (VBR-NRT, ABR, UBR) are scheduled at low-  
priority levels. Up to eight priority levels are available.  
29.3.1 APC Modes and ATM Service Types  
The ATM Forum (http://www.atmforum.com) deÞnes the service types described in  
Table 29-1.  
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Table 29-1. ATM Service Types  
Real-Time/  
Non-Real-Time  
Service Type  
Cell Rate Pacing  
Relative Priority  
CBR  
PCR  
RT  
1 (highest)  
VBR-RT  
PCR, SCR (peak-and-sustain)  
PCR, SCR (peak-and-sustain)  
PCR  
RT  
2
VBR-NRT  
NRT  
NRT  
NRT  
NRT  
3
1
ABR  
4
5
UBR+  
UBR  
PCR, MCR (peak-and-minimum)  
PCR  
6 (lowest)  
1
When ABR ßow control is active, the CP automatically adapts the APC parameters PCR,  
PCR_FRACTION. These parameters function as the channelÕs allowed cell rate (ACR).  
For information about cell rate pacing, see Section 29.3.5, ÒATM TrafÞc Type.Ó For  
information about prioritization, see Section 29.3.6, ÒDetermining the Priority of an ATM  
Channel.Ó  
29.3.2 APC Unit Scheduling Mechanism  
The APC unit consists of an APC data structure in the dual-port RAM for each PHY and a  
special scheduling algorithm performed by the CP. Each PHYÕs APC data structure  
includes three elements: an APC parameter table, an APC priority table, and cell  
transmission scheduling tables for each priority level. (See Section 29.10.4, ÒAPC Data  
Structure.Ó)  
Each PHYÕs APC parameter table holds parameters that deÞne the priority table location,  
the number of priority levels, and other APC parameters. The priority table holds pointers  
that deÞne the location and size of each priority levelÕs scheduling table.  
Each scheduling table is divided into time slots, as shown in Figure 29-1. The user  
determines the number of ATM cells to be sent each time slot (cells per slot). After a  
channel is sent, it is removed from the current time slot and advanced to a future time slot  
according to the channelÕs assigned trafÞc rate (speciÞed in time slots). The PCR parameter  
in the TCT, or the SCR or MCR parameters in the TCT extension (TCTE) determine the  
channelÕs actual rate.  
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9
5
1
6
4
3
2
7
8
Number of Slots  
Cell Rescheduling  
Current Slot  
Figure 29-1. APC Scheduling Table Mechanism  
Each 2-byte time-slot entry points to one ATM channel. Additional channels scheduled to  
transmit in the same slot are linked to each other using the APC linked-channel Þeld in the  
TCT. The linked list is not limited; however, if the number of channels for the current slot  
exceeds the cells per slot parameter (CPS), the extra channels are sent in subsequent time  
slots. (The rescheduling of extra channels is based on the original slot to maintain each  
channelÕs pace.)  
Note that a channel can appear only once in the scheduling table at a given time, because  
each channel has only one APC linked-channel Þeld.  
29.3.3 Determining the Scheduling Table Size  
The following sections describe how to determine the number of cells sent per time slot and  
the total number of slots needed in a scheduling table.  
29.3.3.1 Determining the Cells Per Slot (CPS) in a Scheduling Table  
The number of cells sent per time slot is determined by the channel with the maximum bit  
rate; see equation A. The maximum bit rate is achieved when a channel is rescheduled to  
the next slot. For example, if the line rate is 155.52 Mbps and there are eight cells per slot,  
equation A yields a maximum VC rate of 19.44 Mbps.  
line rate  
(A)  
Max bit rate =  
cells per slot  
Note that a channel can appear only once per time slot; thus, 19.44 Mbps = 155.52Mbps/8.  
The cells per slot parameter (CPS) affects the cell delay variation (CDV). Because the APC  
unit does not put cells in a deÞnite order within each time slot (LIFOÑlast-in/Þrst-out  
implementation), as CPS increases, the CDV increases. However as CPS decreases, the size  
of the scheduling table in the dual-port RAM increases and more CPM bandwidth is  
required.  
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29.3.3.2 Determining the Number of Slots in a Scheduling Table  
The number of time slots in a scheduling table is determined by the channel with the  
minimum bit rate; see equation B. The minimum bit rate is achieved when the channel  
reschedules only once in a whole table scan. (The maximum schedule advance allowed is  
equal to number_of_slots-1.) For example, if the line rate is 155.52 Mbps, the minimum bit  
rate is 32 kbps and the CPS is 4, then, according to equation B, the number of slots should  
be 1,216.  
line rate  
Min bit rate =  
(B)  
(number_of_slots - 1) ´ cells per slot  
For the above example, 32 kbps = 155.52 Mbps/((1216-1) ´ 4).  
Use equations (A) and (B) to obtain the maximum and minimum bit rates of a scheduling  
table. For example, given a line rate = 155.52 Mbps, number_of_slots = 1025, and CPS = 8:  
Max bit rate = (155.52 Mbps)/8 = 19.44 Mbps  
Min bit rate = (155.52 Mbps)/(1024 ´ 8) = 18.98 kbps.  
29.3.4 Determining the Time-Slot Scheduling Rate of a Channel  
The time-slot scheduling rate of each ATM channel is deÞned by equation C. The resulting  
number of APC slots is written in either TCT[PCR], TCTE[SCR] or TCTE[MCR],  
depending on the trafÞc type.  
line rate [bps]  
Rate [slots] =  
(C)  
VC rate [bps] ´ cells per slot  
29.3.5 ATM TrafÞc Type  
The APC uses the cell rate pacing parameters (PCR, SCR, and MCR) to generate CBR,  
VBR, ABR, UBR+, and UBR trafÞc. The user determines the kind of trafÞc that is  
generated per VC by writing to TCT[ATT] (ATM trafÞc type); see Section 29.10.2.3,  
ÒTransmit Connection Table (TCT).Ó  
29.3.5.1 Peak Cell Rate TrafÞc Type  
When the peak cell rate trafÞc type is selected, the APC schedules channels to transmit  
according to the PCR and PCR_FRACTION trafÞc parameters. Other trafÞc parameters do  
not apply to this trafÞc type.  
29.3.5.2 Determining the PCR TrafÞc Type Parameters  
Suppose a VC uses 15.66 Mbps of the total 155.52 Mbps and CPS = 8. Equation C yields:  
PCR [slots] = (155.52 Mbps)/(15.66 Mbps ´ 8) = 1.241  
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The resulting number of slots is written into TCT[PCR] and TCT[PCR_FRACTION].  
Because PCR_FRACTION is in units of 1/256 slots, the fraction must be converted as  
follows:  
1.241 = 1+0.241 ´ 256/256 =1+ 61.79/256 ~ 1 + 62/256  
PCR = 1  
PCR_FRACTION = 62  
29.3.5.3 Peak and Sustain TrafÞc Type (VBR)  
Variable bit rate (VBR) trafÞc can burst at the peak cell rate as long as the long-term average  
rate does not exceed the sustainable cell rate. To support VBR channels, the APC  
implements the GCRA (generic cell rate algorithm) using three parametersÑthe peak cell  
rate (PCR), the sustained cell rate (SCR), and burst tolerance (BT), as shown in  
Figure 29-2. (The GCRA is also known as the leaky bucket algorithm.)  
Conforming VBR Traffic  
Incoming cells fill the bucket at the peak cell rate (PCR) or at the SCR if the bucket is full.  
Burst tolerance (BT)  
Sustained cell rate (SCR)  
Figure 29-2. VBR Pacing Using the GCRA (Leaky Bucket Algorithm)  
When a VBR channel is activated, it bursts at the peak cell rate (PCR) until reaching its  
initial burst tolerance (BT), which is the buffer length the network allocated for this VC.  
When the burst limit is reached, the APC reduces the VCÕs scheduling rate to the sustained  
cell rate (SCR). The VC continues sending at SCR as long as TxBDs are ready. However,  
as each SCR time allotment elapses with no TxBD ready to send, the APC grants the VC a  
credit for bursting at the peak cell rate (PCR). (Gaining credit implies that the buffer at the  
switch is not full and can tolerate a burst transmission.) If a TxBD becomes ready, the APC  
schedules the VC to burst at the PCR as long as credit remains. When the burst credit ends  
(the networkÕs UPC leaky bucket reaches its limit), the APC schedules the VC according to  
SCR.  
29.3.5.3.1 Example for Using VBR TrafÞc Parameters  
Suppose the trafÞc parameters of a VBR channel are PCR = 6 Mbps, SCR = 2 Mbps, MBS  
(maximum burst size) = 1000 cells, and CPS = 8.  
Equation C (see Section 29.3.4, ÒDetermining the Time-Slot Scheduling Rate of a  
ChannelÓ) yields the APC parameters, PCR, PCR_FRACTION, SCR, and  
SCR_FRACTION, which the user writes to the channelÕs TCT.  
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PCR [slots] = (155.52 Mbps)/(6 Mbps ´ 8) = 3.24  
3.24 = 3 + 0.24 ´ 256/256 = 3 + 61.44/256 ~ 3 + 62/256  
PCR = 3 PCR_FRACTION = 62  
SCR [slots] = (155.52 Mbps)/(2 Mbps ´ 8) = 9.72  
9.72 = 9 + (0.72 ´ 256/256) = 9 + 184.32/256 ~ 9 + 185/256  
SCR = 9  
SCR_FRACTION = 185  
Equation D yields the number of slots the user writes to the channelÕs TCT[BT].  
BT [slots] = (MBS[cells] - 2) ´ (SCR[slots] - PCR[slots]) + SCR[slots]  
(D)  
= (1000 - 2) ´ ((9+185/256) - (3+62/256)) + (9 +185/256)  
= 6477  
29.3.5.3.2 Handling the Cell Loss Priority (CLP)ÑVBR Type 1 and 2  
The MPC8260 supports two ways to schedule VBR trafÞc based on the cell loss priority  
(CLP). When TCTE[VBR2] is cleared, CLP0+1 cells are scheduled by PCR or SCR  
according to the GCRA state. When TCTE[VBR2] is set, CLP0 cells are still scheduled by  
PCR or SCR according to the GCRA state, but CLP1 cells are always scheduled by PCR.  
See Section 29.10.2.3.4, ÒVBR Protocol-SpeciÞc TCTE.Ó  
29.3.5.4 Peak and Minimum Cell Rate TrafÞc Type (UBR+)  
To support UBR+ channels, the APC schedules transmission according to PCR and MCR.  
For each priority level, the APC maintains a parameter that monitors the trafÞc load  
measured as the time-slot delay between the service pointer (pointing to the current time  
slot waiting transmission) and a real-time slot pointer. If the transmission delay is greater  
than MDA (maximum delay allowed), the APC begins scheduling channels according to  
the MCR parameter. If the delay, however, drops below MDA, the APC again schedules  
channels according to the PCR. Note that in order to guarantee a minimum cell rate for  
UBR+ channels, there must be enough bandwidth to simultaneously send all possible  
channels at the MCR. See Section 29.10.2.3.5, ÒUBR+ Protocol-SpeciÞc TCTE.Ó  
29.3.6 Determining the Priority of an ATM Channel  
The priority mechanism is implemented by adding priority table levels, which point to  
separate scheduling tables; see Section 29.10.4, ÒAPC Data Structure.Ó The APC ßow  
control services the APC_LEVEL1 slots Þrst. If there are no cells to send, the APC goes to  
the next priority level. The APC has up to eight priority levels with APC_LEVEL8 being  
the lowest. The user speciÞes the priority of an ATM channel when issuing the ATM  
TRANSMIT command; see Section 29.14, ÒATM Transmit Command.Ó  
The real-time channels, CBR and VBR-RT, should be inserted in APC_LEVEL1; non-real-  
time channels, VBR-NRT, ABR, and UBR should be inserted in lower priority levels.  
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29.4 VCI/VPI Address Lookup Mechanism  
The MPC8260 supports two ways to look up addresses for incoming cells:  
¥
¥
External CAM lookup  
Address compression  
Writing to GMODE[ALM] (address-lookup-mechanism bit) in the parameter RAM selects  
the mechanism. Both mechanisms are described in the following sections.  
29.4.1 External CAM Lookup  
An external CAM is usually used when the range of VCI/VPI values varies widely or is  
unknown. Clearing GMODE[ALM] selects the external CAM address lookup mechanism.  
If there is no match in the external CAM, the cell is considered a misinserted cell. The  
external CAM can point to internal or external channels (channels whose connection table  
resides in external memory). The CAM input, shown in Figure 29-3, is the 32-bit cell  
address: PHY address, GFC + VPI, and VCI.  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31  
PHY Addr  
(MPHY)  
GFC + VPI VCI  
Figure 29-3. External CAM Data Input Fields  
The output of the CAM, shown in Figure 29-4, is a 32-bit entry (16-bit channel code and a  
match-status bit).  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31  
Channel Code  
MS  
Ñ
Figure 29-4. External CAM Output Fields  
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The external CAM Þelds are described in Table 29-2  
Table 29-2. External CAM Input and Output Field Descriptions  
Field  
Description  
PHY Addr  
In multiple PHY mode, this Þeld contains the 4 least-signiÞcant bits of the current channelÕs physical  
address. Because this CAM comparison Þeld is limited to 4 bits, two CAM devices are needed if using  
more than 16 PHYs.The msb of the PHY address lines (bit 4) selects between the two devices. If the  
msb is zero, the CP accesses the CAM whose address is written in the EXT_CAM_BASE parameter in  
the parameter RAM; if the msb is set, the CP uses EXT_CAM1_BASE. See Section 15.4.1, ÒCMX  
UTOPIA Address Register (CMXUAR).Ó  
In single PHY mode, clear this Þeld.  
GFC+VPI, The GFC, VPI, and VCI of the current channel.  
VCI  
Ch Code  
Ñ
Pointer to internal or external connection table.  
Reserved, should be cleared.  
MS  
Match status.  
0 Match was found.  
1 Match was not found.  
29.4.2 Address Compression  
The address compression mechanism uses two levels of address translation to help  
minimize the memory space needed to cover the available address range. The Þrst level of  
translation (VP-level) uses a look-up table based on the 4-bit PHY address and the 12-bit  
virtual path identiÞer; the second level (VC-level) uses the 16-bit virtual channel identiÞer.  
If there is no match during address compression, the cell is considered a misinserted cell.  
During the VP-level translation, VP_MASK in the ATM parameter RAM compresses an  
incoming cellÕs PHY address and VPI to create an index into the VP-level table. The VP-  
level table entry consists of another mask (VC_MASK) and a pointer to one of theVC-level  
tables (VCOFFSET). Note that the VP table should reside in the dual-port RAM.  
In the VC-level translation, the VCI is compressed with the VC_MASK to generate a  
pointer to theVC-level table entry containing the received cellÕs channel code. TheVC table  
should reside in external memory.  
Figure 29-5 shows an example of address compression.  
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4 bit  
12 bit  
VPI  
VP-level addressing table  
(in dual-port RAM recommended)  
PHY Addr  
31  
0
VPT_BASE  
VP_MASK  
32-bit entries  
0000  
0000 00011111  
0b00011  
16 bit  
16 bit  
VPpointer  
VC_MASK  
VCOFFSET  
VC-level addressing tables  
(in external memory)  
16 bit  
VCI  
32-bit entries  
VCT_BASE  
00000111 11110000  
VCpointer  
15 bit  
Ñ
16 bit  
1 bit  
MS  
0
Ch Code[15Ð0]  
31  
Figure 29-5. Address Compression Mechanism  
Figure 29-5 shows VP_MASK selecting Þve VPI bits to index the VP-level table. The VP-  
level table entry contains the 16-bit mask (VC_MASK) and the VC-level table offset  
(VCOFFSET) for the next level of address mapping. The VC_MASK selects VCI bits 4Ð  
10, which is used with VCT_BASE and VCOFFSET to indicate the received cellÕs channel  
code.  
Table 29-3. Field Descriptions for Address Compression  
Field  
Description  
PHY  
Addr  
In multiple PHY mode, this Þeld contains the 4 least-signiÞcant bits of the current channelÕs physical  
address. Because this comparison Þeld is limited to 4 bits, two sets of look-up tables are needed if using  
more than 16 PHYs.The msb of the PHY address lines (bit 4) selects between the two sets of tables. If the  
msb is zero, the CP accesses the tables at VPT_BASE and VCT_BASE; if the msb is set, the CP uses  
VPT1_BASE and VCT1_BASE. See Section 15.4.1, ÒCMX UTOPIA Address Register (CMXUAR).Ó  
In single PHY mode, clear this Þeld.  
VCI, VPI The VCI and VPI of the current channel.  
Ch Code Pointer to internal or external connection table.  
Ñ
Reserved, should be cleared.  
MS  
Match status.  
0 Match was found.  
1 Match was not found.  
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29.4.2.1 VP-Level Address Compression Table (VPLT)  
The size of the VP-level table depends on the number of mask bits in VP_MASK. For  
example, if only one PHY is available (PHY address = 0) and VPMASK =  
0b11_1111_1111, VP pointer contains ten bits and the table is 4 Kbytes. Because each  
VPLT entry is 4 bytes, the address of an entry is VPT_BASE + VP pointer ´ 4.  
Each VPLT entry has two parameters:  
¥
¥
VC_MASKÑA 16-bit VC-level mask for masking the incoming cellÕs VCI  
VCOFFSETÑA 16-bit VC-level table offset from VC_BASE that points to the  
appropriate VC-level tableÕs (VCLT) starting address. The address of the VCLT is  
VC_BASE + VCOFFSET ´ 4.  
If the VCLTs are to be placed contiguously in memory, each tableÕs VCOFFSET  
depends on the size of preceding tables. Each tableÕs size depends on the number of  
ones in VC_MASK. Figure 29-6 gives the general formula for determining  
VCOFFSET.  
(number of ones in VC_MASKn)  
General formula: VCOFFSET  
= VCOFFSET + 2  
n
(n+1)  
Figure 29-6. General VCOFFSET Formula for Contiguous VCLTs  
Table 29-4 shows example VCOFFSET calculations for a VP-level table with four  
entries.  
Table 29-4. VCOFFSET Calculation Examples for Contiguous VCLTs  
VP-Level  
Table Entry  
Number of Ones  
in VC_MASK  
VC-Level  
Table Size  
VC_MASK  
VCOFFSET  
6
0
1
2
3
0x0237  
0x0230  
0xA007  
x
6
3
5
x
2
= 64 entries  
= 8 entries  
= 32 entries  
x
0
3
2
64  
5
2
64 + 8 = 72  
72 + 32 = 104  
The MPC8260 can check that all unallocated bits of the PHY + VPI are 0 by setting  
GMODE[CUAB] (check unallocated bits) in the parameter RAM. If they are not, the cell  
is considered a misinserted cell.  
Table 29-5 gives an example of VP-level table entry address calculation.  
Table 29-5. VP-Level Table Entry Address Calculation Example  
VPT_BASE VP-Level Table Size VP_MASK  
0x0024_0000 64 entries 0x0237  
Phy+VPI  
VP Pointer  
VP Entry Address  
0x0011  
0x09  
VP Base = 0x240000  
0x09 x 4 = 0x000024  
0x240024  
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Figure 29-7 shows the VP pointer address compression from Table 29-5.  
PHY+VPI  
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
1
1
1
VP_MASK  
VP Pointer  
0
0
1
0
0
1
Figure 29-7. VP Pointer Address Compression  
29.4.2.2 VC-Level Address Compression Tables (VCLTs)  
Each VPLT entry points to a single VCLT. Like the VPLT, the size of each VCLT depends  
on VC_MASK. Because the VCLT contains word entries, if VC_MASK =  
0b11_1111_1111, the table is 4 Kbytes. The address of an entry in this table is VCT_BASE  
+ VCOFFSET ´ 4 + VCpointer ´ 4.  
The MPC8260 can check that all unallocated VCI bits are 0 by setting GMODE[CUAB]  
(check unallocated bits). If they are not, the cell is considered a misinserted cell.  
An example of VC-level table entry address calculation is shown in Table 29-6. Note that  
VCOFFSET is assumed to be 0x100 for this example.  
Table 29-6. VC-Level Table Entry Address Calculation Example  
VCT_BASE  
VCOffset  
VC-Level Table Size VC_MASK  
32 entries 0x0037  
VCI  
VC Pointer  
VC Entry Address  
0x0084_0000  
0x0100  
0x0031  
0x19  
VC Base = 0x840000  
0x100 x 4 = 0x000400  
0x19 x 4 = 0x000064  
0x840464  
Figure 29-8 shows the VC pointer address compression from Table 29-6.  
VCI  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
VC_MASK  
VC Pointer  
1
1
0
0
1
Figure 29-8. VC Pointer Address Compression  
29.4.3 Misinserted Cells  
If the address lookup mechanism cannot find a match (MS=1), the cell is discarded and  
ATM layer statistics are updated, as described in Section 29.8, ÒATM Layer Statistics.Ó  
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29.4.4 Receive Raw Cell Queue  
Channel one in the RCT is reserved as a raw cell queue. The user should program channel  
one to operate in AAL0 protocol. The receive raw cell queue is used for removing  
management cells from the regular cell ßow to the host. When a management cell is sent to  
the receive raw cell queue, the CP sets RxBD[OAM]. The ALL0 BD speciÞes the channel  
code associated with the current OAM cell.  
The following are optionally removed from the regular ßow and sent to the raw cell queue:  
¥
¥
Segment F5 OAM (PTI = 0b100). To enable F5 segment Þltering, set RCT[SEGF].  
End-to-end F5 OAM (PTI = 0b101). To enable F5 end-to-end Þltering, set  
RCT[ENDF].  
¥
RM cells (PTI = 0b110). When ABR ßow is enabled the cells are terminated  
internally; otherwise, they are sent to the raw cell queue.  
¥
¥
Reserved PTI value (PTI = 0b111). Always sent to the raw cell queue.  
VCI value: 3, 4, 6, 7Ð15. To enable VCI Þltering set the associated bit in the VCIF  
entry in the parameter RAM.  
Figure 29-9 shows a ßowchart of the ATM cell ßow.  
Check  
address  
No  
Discard  
cell  
Match  
Yes  
No  
PTI=1xx or  
VCI=3,4,6,7-15  
and filter enable  
Send cell to VC  
queue  
Yes  
Send cell to raw  
cell queue  
Figure 29-9. ATM Address Recognition Flowchart  
Note that even reserved VCI channels should appear in the CAM or address compression  
tables; otherwise, a cell on a reserved channel will be considered misinserted.  
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29.5 Available Bit Rate (ABR) Flow Control  
While CBR service provides a Þxed bandwidth and is useful for real-time applications with  
strictly bounded end-to-end cell transfer delay and cell-delay variation, ABR service is  
intended for data applications that can adapt to time-varying bandwidth and can tolerate  
signiÞcant cell transfer delay and cell delay variation. The MPC8260 implements the two  
following mechanisms deÞned by the ATM Forum TM 4.0 rate-based ßow control.  
¥
Explicit forward congestion indication (EFCI). The network supplies binary  
indication of whether congestion occurred along the connection path. This  
information is carried in the PTI Þeld of the ATM cell header (similar to that used in  
frame relay). The source initially clears each ATM cellÕs EFCI bit, but as the cell  
passes through the connection, any congested node can set it. The MPC8260 detects  
this indication and sets the congestion indication (CI) bit in the next backwards RM  
cell to signal the source end station to reduce its transmission rate.  
¥
Explicit rate (ER) feedback. The network carries explicit bandwidth information, to  
allow the source to adjust its rate. The source sends forward RM cells specifying its  
chosen transmit rate (source ER). A congested switch along the network may  
decrease ER to the exact rate it can support. The destination receives forward RM  
cells and returns them to the source as backward RM cells. The MPC8260  
implements source behavior by adjusting the rate according to each returning  
backward RM cellÕs ER.  
Explicit rate feedback has several advantages over binary feedback (EFCI). Explicit rate  
feedback allows immediate source rate adaptation, eliminating rate oscillation caused by  
incremental rate changes. Using the information in RM cells, the network can allocate  
bandwidth evenly among active ABR channels.  
29.5.1 The ABR Model  
Figure 29-10 shows the MPC8260Õs ABR model.  
Source Behavior  
Destination Behavior  
Nrm Data Cells  
Turn-around  
F-RM Cell  
F-RM Cell  
CCR,ER  
B-RM Cell  
B-RM Cell  
Set CI, NI  
Update Rate  
ER, CI, NI  
Reduce ER  
Figure 29-10. MPC8260Õs ABR Basic Model  
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The MPC8260 ABR ßow control implements both source and destination behavior. The  
MPC8260Õs ABR ßowchart is described in Section 29.5.1.3, ÒABR Flowcharts.Ó  
29.5.1.1 ABR Flow Control Source End-System Behavior  
The MPC8260Õs implementation of ABR ßow control for end-system sources is described  
in the following steps:  
1. An ABR channelÕs allowed cell rate (ACR) lies between the minimum cell rate  
(MCR) and the peak cell rate (PCR).  
2. ACR is initialized to the initial cell rate (ICR).  
3. An F-RM (Forward-RM) cell is sent for every Nrm data cell sent. If more than Mrm  
cells are sent and the time elapsed since the last F-RM exceeds Trm, an F-RM cell  
is sent.  
4. When sending an F-RM cell, the current ACR is written in the CCR (current cell  
rate) Þeld of the RM cell.  
5. When B-RM (backward-RM) cell is received with CI = 1 (congestion indication),  
ACR is reduced by ACR ´ RDF (rate decrease factor). After the reduction, the new  
ACR is determined Þrst by letting ACRtemp be the min of (ACR, ER), and then  
taking the max of (ACRtemp, MCR).  
6. When B-RM is received with CI=0 and NI=0 (no increase),ACR is increased by RIF  
´ PCR (rate increase factor). The new ACR is determined Þrst by letting ACRtemp  
be the min of (ACR, ER), and then taking the max of (ACRtemp, MCR).  
7. Before sending an F-RM cell, if more than ADTF (ACR decrease time factor) has  
elapsed since sending the last F-RM cell, ACR is reduced to ICR. In other words, if  
the source does not fully use its gained bandwidth, it loses it and resumes sending at  
its initial cell rate.  
8. Before sending an F-RM cell and after action 7, if more than Crm F-RM cells were  
sent since the last B-RM cell was received with BN=0 (backward notiÞcation), the  
ACR is reduced by ACR ´ CDF (cutoff decrease factor).  
9. A source whose ACR is less than the tag cell rate (TCR) sends out-of-rate cells at  
the TCR. This behavior is intended for sources whose rates were set to zero by the  
network. These sources should periodically sense the network state by sending out-  
of-rate RM cells. In this case data cells will not be sent.  
10.An RM cell with an incorrect CRC10 is discarded and the UNI statistics tables are  
updated.  
29.5.1.2 ABR Flow Control Destination End-System Behavior  
The MPC8260Õs implementation of ABR ßow control for end-system destinations is  
described in the following steps:  
1. A received F-RM cell is turned around and sent as a B-RM cells.  
2. The DIR Þeld of the received F-RM cell is changed from 0 to 1 (backward DIR).  
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3. The CCR and MCR Þelds are taken from the F-RM and is not changed.  
4. The CI bit of the B-RM cell is set if the previous data cell arrived with EFCI = 1  
(congestion bit in the ATM cell header).  
5. The ER Þeld of the turn around B-RM cells is limited by TCTE[ER-BRM].  
6. If a F-RM cell arrives before the previous F-RM cell was turned around (for the same  
connection), the new RM cell overwrites the old RM cell.  
29.5.1.3 ABR Flowcharts  
The MPC8260Õs ABR transmit and receive flow control is described in the following  
ßowcharts. See Figure 29-11, Figure 29-12, Figure 29-13, and Figure 29-14.  
Start Channel Tx  
No  
ACR < TCR  
Source End-Sys 9  
ACR is low sent only  
out-of-rate cells at TCR  
Yes  
Send RM (DIR = forward, CCR = ACR, ER = PCR, CI = NI = 0, CLP =1)  
Schedule: Time_to_send = now+1/TCR  
EXIT  
ACR>=TCR  
RM/DATA In Rate Cell Tx  
Figure 29-11. ABR Transmit Flow  
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RM/DATA In Rate Cell Tx  
Source End-Sys 3  
Count=Number of data cells from last F-RM.  
Nrm=Number of data cells between every RM cell  
Mrm=Fixed number=2  
Count >= Nrm  
or (Count > Mrm  
and Now ³  
No  
B-RM/DATA In Rate Cell Tx  
Trm=Max time between every F-RM Cells.  
(Last_RM+Trm))  
Yes  
F-RM In Rate Cell Tx  
Checking ÒTime-Out FactorÓ Max time  
allowed between RM Cells before a rate  
Decrease is required.  
Time = Now - Last_RM  
No  
Time >ADTF  
Source End-Sys 7  
ACR is too high  
Idle adjust (Òuse it or loose itÓ)  
Yes  
ACR = ICR  
No  
Source End-Sys 8  
Crm=Max number of F-RM cells without any  
B-RM cell allowed before rate decrease  
is required.  
Unack³Crm  
Unack=Number of F-RM cells sent  
without any B-RM cell received.  
Yes  
ACR = ACR-ACR´CDF  
ACR = max(ACR,MCR)  
Source End-Sys 4  
Send RM (DIR = forward, CCR = ACR, ER = PCR, CI = NI = CLP = 0)  
Count=0  
Last_RM = Now  
First-turn = TRUE  
Unack = Unack+1  
Count = Count+1  
First-turn = Flag indicates first turn of RM cell  
with priority over data cells.  
EXIT  
Figure 29-12. ABR Transmit Flow (Continued)  
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B-RM/DATA In Rate Cell Tx  
Turn-around  
and  
No  
(First-turn or not  
data-in-queue)  
Destination End-Sys 1,2,3,4  
B-RM In Rate Cell Tx  
Yes  
CI-TA = CI-TA || CI-VC  
Send RM cell (DIR = backwards, CCR-TA, ER-TA, MCR-TA,  
CI-TA, NI-TA, CLP=0)  
CI-VC = 0  
Turn-around = first-turn = FALSE  
Count = Count+1  
EXIT  
Data Cell Tx  
Send Data Cell  
CLP = EFCI = 0  
Count = Count+1  
Schedule:Time_to_send = Now+1/ACR  
EXIT  
Figure 29-13. ABR Transmit Flow (Continued)  
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B-RM Cells Rx  
No  
CI = 1  
Yes  
Source End-Sys 5  
ACR = ACR-ACR´RDF  
No  
NI = 0  
Yes  
Source End-Sys 1, 6  
ACR = ACR+RIF´PCR  
ACR = min(ACR,PCR)  
ACR = min(ACR,ER)  
Source End-Sys 5, 6  
ACR = max(ACR,MCR)  
No  
BN = 0  
The source generate this RM  
Yes  
Unack = 0  
Unack = Number of F-RM in absence of B-RM = 0  
EXIT  
Figure 29-14. ABR Receive Flow  
29.5.2 RM Cell Structure  
Table 29-7 describes the structure of the RM cell supported by the MPC8260. For more  
information, see the ABR ßow-control trafÞc management speciÞcation (TM 4.0) on the  
ATM Forum website at http://www.atmforum.com.  
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Table 29-7. Fields and their Positions in RM Cells  
Fields  
Octet Bits  
Description  
Value  
RM-VCC  
PTI=6  
Header  
1Ð5  
All ATM cell header  
ID  
DIR  
BN  
6
7
7
All Protocol ID  
1
0
1
Direction of RM cell (0 = forward, 1 = backward)  
Backward notiÞcation (BN = 0, the cell was generated by the  
source; BN=1, the cell was generated by the network or by the  
destination)  
CI  
NI  
7
7
2
3
4
Congestion indication. (1 = congestion, 0 = otherwise)  
No increase indication. (1 = no increase allowed, 0 = otherwise)  
Not used (ATM Forum ABR)  
RA  
7
0
0
Ñ
7
5-7 Reserved, should be cleared.  
All Explicit rate; see Section 29.5.2.1  
All Current cell rate; see Section 29.5.2.1  
All Min cell rate; see Section 29.5.2.1  
All Not used (ATM Forum ABR)  
All Not used (ATM Forum ABR)  
All Reserved, should be cleared.  
0Ð5 Reserved, should be cleared.  
6Ð7 CRC-10  
ER  
8Ð9  
10Ð11  
12Ð13  
14Ð17  
18Ð21  
22Ð51  
52  
CCR  
MCR  
QL  
0
SN  
0
Ñ
0x6A for each byte  
0
Ñ
CRC-10  
52  
53  
All  
29.5.2.1 RM Cell Rate Representation  
Rates in the RM cells are represented in a binary ßoating-point format using a 5-bit  
exponent (e), a 9-bit mantissa (m), and a 1-bit nonzero ßag (nz), as shown in Figure 29-15.  
0
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
nz  
Exponent  
Mantissa  
Figure 29-15. Rate Format for RM Cells  
The rate (in cells/second) is calculated as in Figure 29-16.  
Rate = 2e  
´
1 + -------- ´ nz  
m
512  
æ
è
ö
ø
Figure 29-16. Rate Formula for RM Cells  
Initialize the trafÞc parameters (ER, MCR, PCR, or ICR) in the ABR protocol-speciÞc  
connection tables using the rate formula in Figure 29-16.  
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29.5.3 ABR Flow Control Setup  
Follow these steps to setup ABR ßow control:  
1. Initialize the ABR data structure: RCT, TCT, RCT-ABR protocol-speciÞc, TCTE-  
ABR protocol-speciÞc.  
2. Initialize ABR global parameters in the parameter RAM. See Section 29.10.1,  
ÒParameter RAM.Ó  
3. Program the AAL-type in the RCT and TCT to AAL5 and set TCT[ABRF]. Note  
that the ABR ßow control is available only with AAL5.  
4. The time stamp timer generates the RM cellÕs time stamp, which the ABR ßow  
control monitors to maintain source behavior in steps #3 and #7 of Section 29.5.1.1,  
ÒABR Flow Control Source End-System Behavior.Ó Enable the time stamp timer by  
writing to the RTSCR; see Section 13.3.7, ÒRISC Time-Stamp Control Register  
(RTSCR).Ó  
5. Initialize the ABR parameters (CPS_ABR and LINE_RATE_ABR) in the APCT;  
see Section 29.10.4.1, ÒAPC Parameter Tables.Ó Note that when usingABR, the CPS  
(cells per slot) parameter in the APCPT should be a power of two.  
6. Finally, send the ATM TRANSMIT command to restart channel transmission.  
29.6 OAM Support  
This section describes the MPC8260Õs support for ATM-layer (F4 out-of-band, and F5 in-  
band) operations and maintenance (OAM) of connections. Alarm surveillance, continuity  
checking, remote defect indication, and loopback cells are supported using OAM receive  
and transmit AAL0 cell queues. Using dedicated support, performance management block  
tests can be performed on up to 64 connections simultaneously. The CP automatically  
inserts forward monitoring cells (FMC) and generates backward-reporting cells (BRC) as  
recommended by ITU I.610.  
29.6.1 ATM-Layer OAM DeÞnitions  
Table 29-8 lists pre-assigned header values at the user-network interface (UNI).  
Table 29-8. Pre-Assigned Header Values at the UNI  
Use  
GFC  
VPI  
VCI  
PTI  
CLP  
Segment OAM F4 ßow cell  
End-to-end OAM F4 ßow cell  
Segment OAM F5 ßow cell  
End-to-end OAM F5 ßow cell  
xxxx  
xxxx  
xxxx  
xxxx  
aaaa_aaaa  
aaaa_aaaa  
aaaa_aaaa  
aaaa_aaaa  
0000_0000_0000_0011  
0000_0000_0000_0100  
aaaa_aaaa_aaaa_aaaa  
aaaa_aaaa_aaaa_aaaa  
0a0  
0a0  
100  
101  
a
a
a
a
a = available for use by the appropriate ATM layer function  
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Table 29-9 lists pre-assigned header values at the network-node interface (NNI).  
Table 29-9. Pre-Assigned Header Values at the NNI  
Use  
VPI  
VCI  
PTI  
CLP  
Segment OAM F4 ßow cell  
End-to-end OAM F4 ßow cell  
Segment OAM F5 ßow cell  
End-to-end OAM F5 ßow cell  
aaaa_aaaa_aaaa  
aaaa_aaaa_aaaa  
aaaa_aaaa_aaaa  
aaaa_aaaa_aaaa  
0000_0000_0000_0011  
0000_0000_0000_0100  
aaaa_aaaa_aaaa_aaaa  
aaaa_aaaa_aaaa_aaaa  
0a0  
0a0  
100  
101  
a
a
a
a
a= available for use by the appropriate ATM layer function  
29.6.2 Virtual Path (F4) Flow Mechanism  
The F4 ßow is designated by pre-assigned virtual channel identiÞers within the virtual path.  
The following two kinds of F4 ßows can exist simultaneously:  
¥
End-to-end (identiÞed as VCI 4)ÑThis ßow is used for end-to-end VPC operations  
communications. Cells inserted into this ßow can be removed only by the endpoints  
of the virtual path.  
¥
Segment (identiÞed as VCI 3)ÑThis ßow is used for communicating operations  
information within one VPC link or among multiple interconnected VPC links. The  
concatenation ofVPC links is called aVPC segment. Cells inserted into this ßow can  
be removed only by the segment endpoints, which must remove these cells to  
prevent confusion in adjacent segments.  
29.6.3 Virtual Channel (F5) Flow Mechanism  
The F5 ßow is designated by pre-assigned payload type identiÞers. The following two kinds  
of F5 ßow can exist simultaneously:  
¥
End-to-end (identiÞed by PTI = 5)ÑThis ßow is used for end-to-end VCC  
operations communications. Cells inserted into this ßow can be removed only byVC  
endpoints.  
¥
Segment (identiÞed by PTI = 4)ÑThis ßow is used for communicating operations  
information with the bound of one VCC link or multiple interconnected VCC links.  
A concatenation of VCC links is called a VCC segment. Segment endpoints must  
remove these cells to prevent confusion in adjacent segments.  
29.6.4 Receiving OAM F4 or F5 Cells  
OAM F4/F5 ßow cells are received using the raw cell queue, described in Section 29.4.4,  
ÒReceive Raw Cell Queue.Ó An F4/F5 OAM cell which does not appear in the CAM or  
address compression tables is considered a misinserted cell.  
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29.6.5 Transmitting OAM F4 or F5 Cells  
OAM F4/F5 ßow cells are sent using the usual AAL0 transmit ßow. For OAM F4/F5 cell  
transmission, program channel one in the TCT to operate in AAL0 mode. Enable the CR10  
(CRC-10 insertion) mode as described in Section 29.10.2.3.3, ÒAAL0 Protocol-SpeciÞc  
TCT.Ó Prepare the OAM F4/F5 ßow cell and insert it in an AAL0 TxBD. Finally, issue a  
ATM TRANSMIT command to send the OAM cell. For multiple PHYs, use several AAL0  
channelsÑeach PHY should have one transmit raw cell queue that is associated with its  
scheduling table.  
A series of OAM cells can be sent using one ATM TRANSMIT command by creating a table  
of AAL0 TxBDs. If the channelÕs TCT[AVCF] (auto VC off) is set, the transmitter  
automatically removes it from the APC (that is, it does not generate periodic transmit  
requests for this channel after all AAL0 BDs are processed).  
29.6.6 Performance Monitoring  
A connectionÕs performance is monitored by inspecting blocks of cells (delimited by  
forward monitoring cells) sent between connection or segment endpoints. Each FMC  
contains statistics about the immediately preceding block of cells. When an endpoint  
receives an FMC, it adds the statistics generated locally across the same block to produce  
a backward reporting cell (BRC), which is then returned to the opposite endpoint.  
The MPC8260 can run up to 64 bidirectional block tests simultaneously. When a  
bidirectional test is run, FMCs are generated for one direction and checked for the opposite.  
Figure 29-17 shows the FMC and BRC cell structure.  
Header = 5 bytes  
Payload = 48 bytes  
4
4
45 x 8  
6
10  
OAM  
Cell  
Type  
Function  
Specific  
Fields  
Function  
Type  
GFC/ VPI VCI PTI CLP HEC  
VPI  
Reserved CRC-10  
0010 = Performance Management  
0000 = Forward Monitoring  
0001 = Backward Reporting  
Monitoring Total User Block Error Total User  
Total  
Received  
Block  
Error  
Result  
Total  
Received  
Cells 0+1  
Time-  
Stamp  
(TSTP)  
Sequence Cell 0+1  
Detection  
Code  
Cell 0  
Count  
Unused  
Number  
(MCSN)  
Count  
(TUC  
Cells 0  
(TRCC )  
1
2
2
2
)
(BEDC  
)
(TUC )  
(BLER) (TRCC  
)
0+1  
0+1  
0
0
0+1  
1 octet  
2 octets  
2 octets  
2 octets  
4 octets  
29 octets 2 octets  
1 octet  
2 octets  
1. BEDC  
appears in FMCs only.  
0+1  
2. TRCC , BLER, and TRCC  
appear in BRCs only.  
0
0+1  
Figure 29-17. Performance Monitoring Cell Structure (FMCs and BRCs)  
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Table 29-10 describes performance monitoring cell Þelds.  
Table 29-10. Performance Monitoring Cell Fields  
Field  
Description  
BRC FMC  
MCSN Monitoring cell sequence number. The sequence number of the performance monitoring  
cell (modulo 256).  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
TUC  
Total user cell 0+1 count. Counts all user cells (modulo 65,536) sent before the FMC was  
inserted.  
0+1  
TUC  
Total user cell 0 count. Counts CLP = 0 user cells (modulo 65,536) sent before the FMC  
was inserted.  
0
TSTP  
BEDC  
Time stamp. Used to indicate when the cell was inserted.  
Yes  
No  
Yes  
Yes  
Block error detection code. Even parity over the payload of the block of user cells sent  
since the last FMC.  
0+1  
TRCC  
Total received cell count 0. Counts CLP=0 user cells (modulo 65,536) received before the  
FMC was received.  
Yes  
No  
0
BLER Block error result. Counts error parity bits detected by the BEDC of the received FMC.  
Yes  
Yes  
No  
No  
TRCC  
Total received cell count 0+1. Counts all user cells (modulo 65,536) received before the  
FMC was received.  
0+1  
29.6.6.1 Running a Performance Block Test  
For bidirectional PM block tests, FMCs are monitored at the receive side and generated at  
the transmit side. The following setup is required to run a bidirectional PM block test on an  
active VCC:  
1. Assign one of the available 64 performance monitoring tables by writing to both  
RCT[PMT] and TCT[PMT] and initializing the one chosen. See Section 29.10.3,  
ÒOAM Performance Monitoring Tables.Ó  
2. For PM F5 segment termination set RCT[SEGF]; for PM F5 end-to-end termination  
set RCT[ENDF].  
3. Finally, set the channelÕs RCT[PM] and TCT[PM] and the receive raw cellÕs  
RCT[PM].  
For unidirectional PM block tests:  
¥
¥
For PM block monitoring only, set only the RCT Þelds above.  
For PM block generation only, set only the TCT Þelds above.  
To run a block test on a VPC, assign all the VCCs of the tested VPC to the same  
performance monitoring table. ConÞgure RCT[PMT] and TCT[PMT] to specify the  
performance monitoring table associated with each F4 channel.  
29.6.6.2 PM Block Monitoring  
PM block monitoring is done by the receiver. After initialization (see Section 29.6.6.1),  
whenever a cell is received for a VCC or VPC, the TRCC counters are incremented and the  
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BEDC is calculated. When an FMC is received, the CP adds the BRC Þelds into the cell  
payload (TRCC0, TRCC0+1, BLER) and transfers the cell to the receive raw cell queue. The  
user can monitor the BRC cell results and transfer the cell to the transmit raw cell queue.  
Before the BRC is transferred to the transmit raw cell queue, the PM function type should  
be changed to backward reporting and additional checking should be done regarding the  
BLER Þeld. If the sequence numbers (MCSN) of the last two FMCs are not sequential or  
the differences between the last two TUCs and the last two TRCCs are not equal, BLER  
should be set to all ones (see the ITU I.610 recommendation).  
Note that the TRCCs are free-running counters (modulo 65,536) that count user cells  
received. The total received cells of a particular block is the difference between TRCC  
values of two consecutive BRC cells. TRCC values are taken from a VCÕs performance  
monitoring table.  
29.6.6.3 PM Block Generation  
The transmitter generates the PM block. Each time the transmitted cell count parameter  
(TCC) in the performance monitoring table reaches zero, the CP inserts an FMC into the  
user cell stream. The CP copies the FMC header, SN-FMC, TUC0+1, TUC0, BEDC0+1-Tx  
from the performance monitoring table and inserts them into the FMC payload. The TSTP  
value (FMC time stamp Þeld) is taken from the MPC8260 time stamp timer; see  
Section 13.3.7, ÒRISC Time-Stamp Control Register (RTSCR).Ó  
The TUCs are free-running counters (modulo 65,536) that count transmitted user cells. The  
total transmitted cells of a particular block is the difference between TUC values of two  
consecutive FMCs. The BEDC (BIP-16, bit interleaved parity) calculation is done on the  
payload of all user cells of the current tested block. The performance monitoring block can  
range from 1 to 2K cells, as speciÞed in the BLCKSIZE parameter in the performance  
monitoring table; see Section 29.10.3, ÒOAM Performance Monitoring Tables.Ó  
In Figure 29-18, the performance monitoring block size is 512 cells. For every 512 user  
cells sent, the ATM controller automatically inserts an FMC into the regular cell stream as  
deÞned in ITU I.610. When an FMC is received, the ATM controller adds the BRC Þelds  
to the cell payload and sends the cell to the raw cell queue. The user can monitor the BRC  
cell results and transfer the cell to the transmit raw cell queue.  
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512 User Cells  
512 User Cells  
1
3
2
Source Cells  
Stream  
FMC Cell Data Cell  
Data Cell FMC Cell  
Data Cell  
Data Cell  
FMC Cell  
TUC0  
TUC0  
TUC0  
TUC0+1  
BEDC  
TSTP  
TUC0+1  
BEDC  
TSTP  
TUC0+1  
BEDC  
TSTP  
3
2
1
BRC Cell  
Destination BRCÕs  
Transmit Stream  
BRC Cell  
BRC Cell  
TUC0  
TUC0  
TUC0  
TUC0+1  
TRCC0  
TRCC0+1  
BLER  
TUC0+1  
TRCC0  
TRCC0+1  
BLER  
TUC0+1  
TRCC0  
TRCC0+1  
BLER  
TSTP  
TSTP  
TSTP  
Figure 29-18. FMC, BRC Insertion  
29.6.6.4 BRC Performance Calculations  
BRC reception uses the regular AAL0 raw cell queue. On receiving two consecutive BRC  
cells, the management layer can calculate the following:  
¥
¥
The difference between two TUCs (Nt)  
The difference between two TRCCs (Nr)  
Information about the connection can be gained by comparing Nt and Nr:  
¥
¥
¥
If Nt > Nr, the difference indicates the number of lost cells of this block test.  
If Nt < Nr, the difference indicates the number of misinserted cells of this block test.  
When Nt = Nr, no cells are lost or misinserted.  
29.7 User-DeÞned Cells (UDC)  
Typical ATM cells are 53 bytes long and consist of a 4-byte header, 1-byte HEC, and 48-  
byte payload. The MPC8260 also supports user-deÞned cells with up to 12 bytes of extra  
header Þelds for internal information for switching applications. This choice is made during  
initialization by writing to the FPSMR; see Section 29.13.2, ÒFCC Protocol-SpeciÞc Mode  
Register (FPSMR).Ó As shown in Figure 29-19, the extra header size can vary between 1 to  
12 bytes (byte resolution) and the HEC octet is optional.  
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Extra Header (1Ð12 Bytes)  
ATM Cell Header (4 Bytes) + HEC (optional)  
Payload (48 Bytes)  
Figure 29-19. Format of User-Defined Cells  
For AAL5 and AAL1 the extra header is taken from the Rx and Tx BDs. The transmitter  
reads the extra header from the UDC TxBD and adds it to each ATM cell associated with  
the current buffer. At the receive side, the extra header of the last cell in the current buffer  
is written to the UDC RxBD.  
For AAL0 the extra header is attached to the regular ATM cell in the buffer. The transmitter  
reads the extra header and theATM cell from the buffer. The receiver writes the extra header  
and the regular ATM cell to the buffer.  
29.7.1 UDC Extended Address Mode (UEAD)  
For external CAM accesses, the UDC extra header can be used to supply extra routing  
information; see Figure 29-20. If GMODE[UEAD] = 1, two bytes of the UDC header are  
used as extensions to the ATM address and the CAM match cycle performs a double-word  
access. UEAD_OFFSET in the parameter RAM determines the offset from the beginning  
of the UDC extra header to the UEAD entry. The offset should be half-word aligned (even  
address). See Section 29.10.1, ÒParameter RAM.Ó  
16-bit  
4-bit  
12-bit  
VPI  
16-bit  
VCI  
CAM data in Þeld:  
UEAD  
PHY addr  
0
15 16  
19 20  
31 32  
47  
Figure 29-20. External CAM Address in UDC Extended Address Mode  
29.8 ATM Layer Statistics  
ATM layer statistics can be used to identify problems, such as the line-bit error rate, that  
affect the UNI performance. Statistics are kept in three 16-bit wrap-around counters:  
¥
¥
¥
UTOPIA error dropped cells countÑCounts cells discarded due to UTOPIA errors:  
Rx parity errors and short or long cells.  
Misinserted dropped cell countÑCounts cells discarded due to address look-up  
failure.  
CRC10 error dropped cell countÑCounts cells discarded due to CRC10 errors.  
(ABR only).  
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Counters are implemented in the dual-port RAM for each PHY device. The counters of  
each PHY are located in the UNI statistics table, described in Section 29.10.7, ÒUNI  
Statistics Table.Ó  
29.9 ATM-to-TDM Interworking  
The MPC8260 supports ATM and TDM interworking. The MCCs and their corresponding  
SIs handle the TDM data processing. (See Chapter 27, ÒMulti-Channel Controllers  
(MCCs),Ó and Chapter 14, ÒSerial Interface with Time-SlotAssigner.Ó) TheATM controller  
processes the ATM data.  
Possible interworking applications include the following:  
¥
¥
¥
Circuit emulation service (CES)  
Carrying voice over ATM  
Multiplexing several low speed services, such as voice and data, onto one ATM  
connection  
Data forwarding between the ATM controller and an MCC can be done in two ways:  
¥
Core intervention. When an MCC receive buffer is full and its RxBD is closed, the  
MCC interrupts the core. The core copies the MCCÕs receive buffer pointer to an  
ATM TxBD and sets the ready bit (TxBD[R]). Similarly, when an ATM receive  
buffer is full and its RxBD is closed, the core services theATM controllerÕs interrupt  
by copying the ATM receive buffer pointer to an MCC TxBD and setting TxBD[R].  
This mode is useful when additional core processing is required.  
¥
Automatic data forwarding. This mode enables automatic data forwarding between  
AAL1/AAL0 and transparent mode over a TDM interface.  
29.9.1 Automatic Data Forwarding  
The basic concept of automatic data forwarding is to program the ATM controller and the  
MCC to process the same BD table, as shown in Figure 29-21.  
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BD Table  
TDM Interface  
MCC  
Buffer 1  
Buffer 2  
Buffer 3  
Buffer 4  
Buffer 5  
Transmitter  
0
BD 1  
BD 2  
BD 3  
BD 4  
BD 5  
MCC Tx ptr  
1
1
0
0
ATM Rx ptr  
UTOPIA Interface  
ATM*  
Receiver  
BD Table  
UTOPIA Interface  
TDM Interface  
Buffer 1  
Buffer 2  
Buffer 3  
Buffer 4  
Buffer 5  
ATM  
Transmitter  
0
BD 1  
BD 2  
BD 3  
BD 4  
BD 5  
ATM Tx ptr  
MCC Rx ptr  
1
1
0
0
MCC*  
Receiver  
* The MCC and ATM receivers should be programmed to operate in opposite polarity E (empty) bit.  
Figure 29-21. ATM-to-TDM Interworking  
When going from TDM to ATM, the MCC receiver routes data from the TDM line to a  
speciÞc BD table. The ATM controller transmitter is programmed to operate on the same  
table. When the MCC Þlls a receive buffer, the ATM controller sends it. The two controllers  
synchronize on the MCCÕs RxBD[E] and the ATM controllerÕs TxBD[R].  
When going from ATM to TDM, the ATM receiver reassembles data received from a  
particular channel to a speciÞc BD table. The MCC transmitter is programmed to operate  
on the same table. When theATM controller Þlls a receive buffer, the MCC controller sends  
it. The controllers synchronize on theATM controllerÕs RxBD[E] and the MCCÕs TxBD[R].  
The MCC and ATM receivers must be programmed to operate in opposite E-bit polarity.  
That is, both receivers receive data into buffers whose RxBD[E] = 0 and set RxBD[E] when  
a buffer is full. For the ATM receiver, set RCT[INVE] of the AAL1- and AAL0-speciÞc  
areas of the receive connection table; see Section 29.10.2.2, ÒReceive Connection Table  
(RCT).Ó For the MCC receiver, set CHAMR[EP]; see Section 27.7.1, ÒChannel Mode  
Register (CHAMR)ÑTransparent Mode.Ó  
29.9.2 Using Interrupts in Automatic Data Forwarding  
The core can program the MCC and ATM interrupt mechanism to trigger interrupts for  
events such as a buffer closing or transfer errors. The interrupt mechanism can be used to  
synchronize the start of the automatic bridging process. For example, to start the MCC  
transmitter after a speciÞc buffer reaches the ATM receiver (the buffering is required to  
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cope with the ATM networkÕs CDV), set ATM RxBD[I]. When the receive buffer is full, the  
RxBD is closed, RxBD[E] is set (because it is operating in opposite E-bit polarity), and the  
core is interrupted. The core then starts the MCC transmitter.  
29.9.3 Timing Issues  
Use of the TDM interface assumes that all communicating entities are synchronized (that  
is, that they are using a synchronized serial clock). If the TDM interfaces are not  
synchronized, a slip can occur in the reassembly buffer. If a buffer-not-ready event occurs  
at the MCC transmitter, the user must restart the MCC transmit channel. If a buffer-not-  
ready event occurs at the ATM transmitter, the user must restart the ATM transmit channel.  
29.9.4 Clock Synchronization (SRTS and Adaptive FIFOs)  
Clock synchronization methods, such as using a time stamp (SRTS) or adaptive FIFOs,  
prevent buffer slipping during reassembly. The SRTS method may be implemented using  
external logic. The MPC8260 can read the SRTS from external logic and insert it into  
AAL1 cells, and can track the SRTS from AAL1 cells and deliver it to external logic. See  
Section 29.15, ÒSRTS Generation and Clock Recovery Using External Logic.Ó  
Alternatively, an adaptive FIFOs method can be implemented using the core to maintain the  
bridging buffer at a mid-level point. The difference between the MCC and ATM data  
pointers is a measure of buffer synchronization. The core calculates the difference between  
pointers at regular intervals and adapts the TDM clock accordingly to hold the difference  
constant.  
29.9.5 Mapping TDM Time Slots to VCs  
Using the MCC and the SI, any TDM time-slot combination can be routed to a speciÞc data  
buffer. (See Chapter 27, ÒMulti-Channel Controllers (MCCs),Ó and Chapter 14, ÒSerial  
Interface with Time-Slot Assigner.Ó) The same data buffers should be used by the ATM  
controller to route receive and transmit data. For information about ATM buffers see  
Section 29.10.5, ÒATM Controller Buffer Descriptors (BDs).Ó  
29.9.6 CAS Support  
For applications requiring channel-associated signaling (CAS), circuit emulation with CAS  
requires additional core processing. External framers perform the CAS manipulation  
through a serial or parallel interface.  
When the MCC receives a multi-frame block, it generates an interrupt to the core. The core  
reads the CAS block from the external framer and places it at the end of theATM data buffer  
after the structured multi-frame block. The core then passes the buffer pointer to the ATM  
controller, and the controller packs the data and CAS block into AAL1 cells. All AAL1  
functions, such as generating PDU-headers and structured pointers, operate normally.  
When theATM controller receives a multi-frame block, it generates an interrupt to the core.  
The core reads the CAS block from the data buffer and writes it to the external framer. The  
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core then moves the buffer pointer to the MCC. The bufferÕs data length should not include  
the CAS octets.  
To optimize the process, the framer may interrupt the core only when the CAS information  
changes. (CAS information changes slowly.) The core can keep the CAS block in memory  
and connect to the framer only when the CAS changes. The core can use regular read and  
write cycles when connecting to the framer through a parallel interface.  
The MCC and ATM controller should be synchronized with the framerÕs multi-frame block  
boundary. At the ATM side, the structured block size should equal the multi-frame block  
size plus the size of the CAS block so that the structured pointer, inserted by the ATM  
controller, points to the start of the structured data block. At the MCC side, the MCC must  
to be synchronized with the super frame sync signal. This synchronization can be achieved  
by external logic that triggers on the super frame sync signal and starts delivering the frame  
sync to the MCC. When loss of super frame synchronization occurs, this logic should reset  
and trigger again on the next super frame indication.  
29.9.7 Trunk Condition  
According to the Bellcore standard, the interworking function (IWF) should be able to  
transmit special payload on both ATM and TDM channels to signal alarm conditions  
(Bellcore TR-NWT-000170). The core can be used to generate the trunk condition payload  
in special buffers (or existing buffers) for the ATM controller or MCC.  
29.9.8 ATM-to-ATM Data Forwarding  
Automatic data forwarding can be used to switch ATM AAL0 cells from one ATM port to  
another without core intervention. The ATM receiver and transmitter should be programed  
to process the same BD table. When the ATM receiver Þlls an AAL0 buffer, the ATM  
transmitter sends it. The ATM receiver and transmitter are synchronized using the same  
mechanism as described for ATM-to-TDM automatic forwarding; see Section 29.9.1,  
ÒAutomatic Data Forwarding.Ó  
29.10 ATM Memory Structure  
The ATM memory structure, described in the following sections, includes the parameter  
RAM, the connection tables, OAM performance monitoring tables, the APC data structure,  
BD tables, the AAL1 sequence number protection table and the UNI statistics table.  
29.10.1 Parameter RAM  
When conÞgured for ATM mode, the FCC parameter RAM is mapped as shown in  
Table 29-11.  
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Table 29-11. ATM Parameter RAM Map  
1
Offset  
Name  
Width  
Description  
0x00Ð  
0x3F  
Ñ
Ñ
Reserved, should be cleared.  
0x40  
RCELL_TMP_  
BASE  
Hword Rx cell temporary base address. Points to a total of 52 bytes reserved dual-  
port RAM area used by the CP. Should be 64 byte aligned. User-deÞned offset  
from dual-port RAM base. (Recommended address space: 0x3000-0x4000 or  
0xB000Ð0xC000)  
0x42 TCELL_TMP_BASE Hword Tx cell temporary base address. Points to total of 52 bytes reserved dual-port  
RAM area used by the CP. Should be 64-byte aligned. User-deÞned offset from  
dual-port RAM base. (Recommended address space: 0x3000Ð0x4000 or  
0xB000Ð0xC000)  
0x44  
UDC_TMP_BASE Hword UDC mode only. Points to a total of 32 bytes reserved dual-port RAM area  
used by the CP. Should be 64-byte aligned. User-deÞned offset from dual-port  
RAM base. (Recommended address space: 0x3000Ð0x4000 or 0xB000Ð  
0xC000)  
0x46  
0x48  
0x4A  
INT_RCT_BASE  
Hword Internal receive connection table base. User-deÞned offset from dual-port  
RAM base.  
INT_TCT_BASE  
Hword Internal transmit connection table base. User-deÞned offset from dual-port  
RAM base.  
INT_TCTE_BASE Hword Internal transmit connection table extension base. User-deÞned offset from  
dual-port RAM base.  
0x4C  
0x50  
0x54  
0x58  
0x5C  
Ñ
Word Reserved, should be cleared.  
EXT_RCT_BASE  
EXT_TCT_BASE  
EXT_TCTE_BASE  
UEAD_OFFSET  
Word External receive connection table base. User-deÞned.  
Word External transmit connection table base. User-deÞned.  
Word External transmit connection table extension base. User-deÞned.  
Hword User-deÞned cells mode only. Offset to the user-deÞned extended address  
(UEAD) in the UDC extra header. Must be an even address. See  
Section 29.10.1.1, ÒDetermining UEAD_OFFSET (UEAD Mode Only).Ó  
If RCT[BO] = 01, UEAD_OFFSET should be in little-endian format. For  
example, if the UEAD entry is the Þrst half word of the extra header in external  
memory, UEAD_OFFSET should be programmed to 2 (second half word entry  
in dual-port RAM).  
0x5E  
0x60  
Ñ
Hword Reserved, should be cleared.  
PMT_BASE  
Hword Performance monitoring table base. User-deÞned offset from dual-port RAM  
base.  
0x62  
0x64  
0x66  
APCP_BASE  
FBT_BASE  
INTT_BASE  
Ñ
Hword APC parameter table base address. User-deÞned offset from dual-port RAM  
base.  
Hword Free buffer pool parameter table base. User-deÞned offset from dual-port RAM  
base.  
Hword Interrupt queue parameter table base. User-deÞned offset from dual-port RAM  
base.  
0x68  
0x6A  
Ñ
Reserved, should be cleared.  
UNI_STATT_BASE Hword UNI statistics table base. User-deÞned offset from dual-port RAM base.  
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Table 29-11. ATM Parameter RAM Map (Continued)  
1
Offset  
Name  
Width  
Description  
0x6C  
BD_BASE_EXT  
Word BD table base address extension. BD_BASE_EXT[0Ð7] holds the 8 most-  
signiÞcant bits of the Rx/Tx BD table base address. BD_BASE_EXT[8Ð31]  
should be zero. User-deÞned.  
0x70  
VPT_BASE /  
EXT_CAM_BASE  
Word Base address of the address compression VP table/external CAM. User-  
deÞned.  
0x74  
0x78  
VCT_BASE  
Word Base address of the address compression VC table. User-deÞned.  
VPT1_BASE /  
EXT_CAM1_BASE  
Word Base address of the address compression VP1 table/EXT CAM1. User-  
deÞned.  
0x7C  
0x80  
0x82  
VCT1_BASE  
VP_MASK  
VCIF  
Word Base address of the address compression VC1 table. User-deÞned.  
Hword VP mask for address compression lookup. User-deÞned.  
Hword VCI Þltering enable bits. When cells with VCI = 3, 4, 6, 7-15 are received and  
the associated VCIF bit = 1 the cell is sent to the raw cell queue. VCIF[0Ð2, 5]  
should be zero. See Section 29.10.1.2, ÒVCI Filtering (VCIF).Ó  
0x84  
GMODE  
Hword Global mode. User-deÞned. See Section 29.10.1.3, ÒGlobal Mode Entry  
(GMODE).Ó  
0x86  
0x88  
0x8A  
0x8C  
0x90  
0x94  
COMM_INFO  
Hword The information Þeld associated with the last host command. User-deÞned.  
See Section 29.14, ÒATM Transmit Command.Ó  
Hword  
Hword  
Ñ
Word Reserved, should be cleared.  
Word Preset for CRC32. Initialize to 0xFFFF_FFFF.  
Word Constant mask for CRC32. Initialize to 0xDEBB_20E3.  
CRC32_PRES  
CRC32_MASK  
0x98 AAL1_SNPT_BASE Hword AAL1 SNP protection look-up table base address. (AAL1 only.) The 32-byte  
table resides in dual-port RAM. AAL1_SNPT_BASE must be halfword-aligned.  
User-deÞned offset from dual-port RAM base. See Section 29.10.6, ÒAAL1  
Sequence Number (SN) Protection Table (AAL1 Only).Ó  
0x9A  
0x9C  
Ñ
Hword Reserved, should be cleared.  
SRTS_BASE  
Word External SRTS logic base address. AAL1 only. Should be 16-byte aligned. The  
four least-signiÞcant bits are taken from SRTS_DEVICE in the AAL1-speciÞc  
area of the connection table entries.  
0xA0  
IDLE/  
UNASSIGN_BASE  
Hword Idle/unassign cell base address. Points to dual-port RAM area contains idle/  
unassign cell template (little-endian format). Should be 64-byte aligned. User-  
deÞned offset from dual-port RAM base. The ATM header should be  
0x0000_0000 or 0x0100_0000 (CLP=1).  
0xA0  
IDLE/  
UNASSIGN_SIZE  
Hword Idle/unassign cell size. 52 in regular mode; 53Ð64 in UDC mode.  
0xA4  
0xA8  
EPAYLOAD  
Trm  
Word Reserved payload. Initialize to 0x6A6A_6A6A.  
Word (ABR only) The upper bound on the time between F-RM cells for an active  
source. TM 4.0 deÞnes the Trm period as 100 msec. The Trm value is deÞned  
by the system clock and the time stamp timer prescaler; see Section 13.3.7,  
ÒRISC Time-Stamp Control Register (RTSCR).Ó For time stamp prescalar of  
1µs, program Trm to be 100 ms/1µs = 100,000.  
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Table 29-11. ATM Parameter RAM Map (Continued)  
1
Offset  
Name  
Width  
Description  
0xAC  
Nrm  
Hword (ABR only) Controls the maximum cells the source may send for each F-RM  
cell. Set to 32 cells.  
0xAE  
0xB0  
Mrm  
TCR  
Hword (ABR only) Controls the bandwidth between F-RM, B-RM and user data cell.  
Set to 2 cells.  
Hword (ABR only) Tag cell rate. The minimum cell rate allowed for all ABR channels.  
An ABR channel whose ACR is less than TCR sends only out-of-rate F-RM  
cells at TCR. Should be set to 10 cells/sec as deÞned in the TM 4.0. Uses the  
ATMF TM 4.0 ßoating-point format. Note that the APC minimum cell rate  
(MCR) should be at least TCR.  
0xB2  
ABR_RX_TCTE  
Hword (ABR only) Points to total of 16 bytes reserved dual-port RAM area used by the  
CP. Should be double-word aligned. User-deÞned offset from dual-port RAM  
base.  
1
Offset from FCC base: 0x8400 (FCC1) and 0x8500 (FCC2); see Section 13.5.2, ÒParameter RAM.Ó  
29.10.1.1 Determining UEAD_OFFSET (UEAD Mode Only)  
The UEAD_OFFSET value is based on the position of the user-deÞned extended address  
(UEAD) in the UDC extra header. Table 29-12 shows how to determine UEAD_OFFSET:  
Þrst determine the halfword-aligned location of the UEAD, and then read the  
corresponding UEAD_OFFSET value.  
Table 29-12. UEAD_OFFSETs for Extended Addresses in the UDC Extra Header  
Bits/  
Header Offset  
0Ð15  
16Ð31  
0x0  
0x4  
0x8  
UEAD_OFFSET = 0x2  
UEAD_OFFSET = 0x6  
UEAD_OFFSET = 0xA  
UEAD_OFFSET = 0x0  
UEAD_OFFSET = 0x4  
UEAD_OFFSET = 0x8  
29.10.1.2 VCI Filtering (VCIF)  
VCI Þltering enable bits are shown in Figure 29-22.  
Bits  
Field  
0
0
1
0
2
0
3
4
5
0
6
7
8
9
10  
11  
12  
13  
14  
15  
VC3 VC4  
VC6 VC7 VC8 VC9 VC10 VC11 VC12 VC13 VC14 VC15  
Figure 29-22. VCI Filtering Enable Bits  
Table 29-13 describes the operation of the VCI Þltering enable bits.  
Table 29-13. VCI Filtering Enable Field Descriptions  
Bits  
Name  
Description  
0Ð2, 5  
Ñ
Clear these bits.  
3, 4, 6,  
7Ð15  
VCx VCI Þltering enable  
0 Do not send cells with this VCI to the raw cell queue.  
1 Send cells with this VCI to the raw cell queue.  
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29.10.1.3 Global Mode Entry (GMODE)  
Figure 29-23 shows the layout of the global mode entry (GMODE).  
Bits  
0
0
1
0
2
0
3
0
4
0
5
0
6
7
8
9
0
10  
0
11  
12  
13  
14  
0
15  
Field  
ALB CTB REM  
UEAD CUAB EVPT  
ALM  
Figure 29-23. Global Mode Entry (GMODE)  
Table 29-14 describes GMODE Þelds.  
Table 29-14. GMODE Field Descriptions  
Bits Name  
Description  
0Ð5  
6
Ñ
Reserved, should be cleared.  
ALB Address look up bus for CAM or address compression tables  
0 Reside on the 60x bus.  
1 Reside on the local bus.  
7
8
CTB External connection tables bus  
0 Reside on the 60x bus.  
1 Reside on the local bus.  
REM Receive emergency mode  
0 Enable REM operation. When the receive FIFO is full, the ATM transmitter stops sending  
data cells until the receiver emergency state is cleared (FIFO not full). The transmitter pace  
is maintained, although a small CDV may be introduced. This mode enables the receiver to  
receive bursts of cells above the steady state performance.  
1 Disable REM operation. Note that to check system performance the user may want to set  
this bit.  
9Ð10  
11  
Ñ
Reserved, should be cleared.  
UEAD User-deÞned cells extended address mode. See Section 29.7.1, ÒUDC Extended Address  
Mode (UEAD).Ó  
0 Disable UEAD mode.  
1 Enable UEAD mode.  
12  
13  
CUAB Check unallocated bits  
0 Do not check unallocated bits during address compression.  
1 Check unallocated bits during address compression.  
EVPT External address compression VP table  
0 VP table resides in dual-port RAM.  
1 VP table reside in external memory.  
14  
15  
Ñ
Reserved, should be cleared.  
ALM Address look-up mechanism. See Section 29.4, ÒVCI/VPI Address Lookup Mechanism.Ó  
0 External CAM lookup.  
1 Address compression.  
29.10.2 Connection Tables (RCT, TCT, and TCTE)  
The receive and transmit connection tables, RCT and TCT, store host-initialized connection  
parameters after connection set-up. These includeAAL type, connection trafÞc parameters,  
BD parameters and temporary parameters used during segmentation and reassembly  
(SAR). The transmit connection table extension (TCTE) supports special connections that  
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use ABR, VBR or UBR+ services. Each connection table entry resides in a 32-byte space.  
Table 29-15 lists sizes for RCT, TCT, and TCTE.  
Table 29-15. Receive and Transmit Connection Table Sizes  
ATM Service Class  
RCT  
TCT  
TCTE  
CBR, UBR service  
32 bytes  
32 bytes  
32 bytes  
32 bytes  
Ñ
ABR, VBR, UBR+ service  
32 bytes  
Note that an ATM channel is considered internal if its tables are in an internal dual-port  
RAM; it is considered external if its tables are in external memory.  
Notes:  
To improve performance, store parameters for fast channels in  
internal dual-port RAM and parameters for slower channels in  
external memory. Connection tables for external channels are  
read and written from external memory each time the CP  
processes a cell. The CP does, however, minimize memory  
access time by burst fetching the 32-byte entry and writing  
back only the Þrst 24 bytes.  
In all connection tables, Þelds which are not used must be  
cleared.  
29.10.2.1 ATM Channel Code  
Each ATM channel has a channel code used as an index to the channelÕs connection table  
entry. The Þrst channel in the table has channel code one, the second has channel code two,  
and so on. Codes of 255 or less indicate internal channels; codes greater than 255 indicate  
external channels. Channel code one is reserved as the raw cell queue and cannot be used  
for another purpose. The channel code is used to specify a VC when sending a ATM  
TRANSMIT command, initiating the external CAM or address compression tables, and when  
the CP sends an interrupt to an interrupt queue.  
Example:  
Suppose a conÞguration supports 1,024 regular ATM channels. To allocate 4 Kbytes of  
dual-port RAM space to the internal connection table, determine that channel codes 0Ð63  
are internal (64 VCs ´ 64 bytes (RCT and TCT) = 4 K). Channels 0Ð1 are reserved. The  
remaining 962 (1024 - 62) external channels are assigned channel codes 256Ð1217. See  
Figure 29-24.  
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Dual-Port RAM  
INT_RCT_BASE  
Reserved  
External Memory  
EXT_RCT_BASE  
RCT256  
RCT257  
RCT258  
RCT259  
Raw Cell (AAL0)  
RCT2  
RCT3  
RCT63  
RCT1217  
Figure 29-24. Example of a 1024-Entry Receive Connection Table  
The general formula for determining the real starting address for all internal and external  
connection table entries is as follows:  
connection table base address + (channel code ´ 32)  
Thus, the real starting address of the RCT entry associated with channel code 3 is as  
follows:  
INT_RCT_BASE+ (3 ´ 32) = INT_RCT_BASE + 96  
Even though it produces a gap in the connection table, the Þrst external channelÕs real  
starting address of the RCT entry (channel code 256) is as follows:  
EXT_RCT_BASE+ (256 ´ 32) = EXT_RCT_BASE + 8192  
See Section 29.10.1, ÒParameter RAM,Ó to Þnd all the connection table base address  
parameters. (The transmit connections table base address parameters are INT_TCT_BASE,  
EXT_TCT_BASE, INT_TCTE_BASE, and EXT_TCTE_BASE.)  
29.10.2.2 Receive Connection Table (RCT)  
Figure 29-25 shows the format of an RCT entry.  
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0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13 14  
INTQ  
AAL  
15  
Offset + 0x00  
Offset + 0x02  
Offset + 0x04  
Offset + 0x06  
Offset + 0x08  
Offset + 0x0A  
Offset + 0x0C  
Offset + 0x0E  
Offset + 0x10  
Offset + 0x12  
Offset + 0x14  
Offset + 0x16  
Offset + 0x18  
Offset + 0x1A  
Offset + 0x1C  
Offset + 0x1E  
Ñ
GBL  
BO  
Ñ
DTB BIB  
Ñ
Ñ
BUFM SEGF ENDF  
Ñ
Ñ
INF  
ABRF  
RX Data Buffer Pointer (RXDBPTR)  
Cell Time Stamp  
RBD_Offset  
Protocol SpeciÞc  
MRBLR  
Ñ
PMT  
RBD_BASE  
RBD_BASE  
Ñ
PM  
Figure 29-25. Receive Connection Table (RCT) Entry  
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Table 29-16 describes RCT Þelds.  
Table 29-16. RCT Field Descriptions  
Offset Bits  
Name  
Description  
0x00  
0Ð1  
2
Ñ
Reserved, should be cleared.  
GBL  
Global. Asserting GBL enables snooping of data buffers, BD, interrupt queues and  
free buffer pool.  
3Ð4  
BO  
Byte orderingÑused for data buffers.  
00 Reserved  
01 PowerPC little endian  
1x Big endian  
5
6
Ñ
Reserved, should be cleared.  
DTB  
Data buffers bus  
0 Data buffers reside on the 60x bus.  
1 Data buffers reside on the local bus.  
7
BIB  
BD, interrupt queues, free buffer pool and external SRTS logic bus  
0 Reside on the 60x bus.  
1 Reside on the local bus.  
Note: When using AAL5, AAL1 in UDC mode, BDs and data should be placed on the  
same bus (RCT[DTB]=RCT[BIB]).  
8
9
Ñ
Reserved, should be cleared.  
BUFM  
Buffer mode. (AAL5 only) See Section 29.10.5.3, ÒATM Controller Buffers.Ó  
0 Static buffer allocation mode. Each BD is associated with a dedicated buffer.  
1 Global buffer allocation mode. Free buffers are fetched from global free buffer  
pools.  
10  
11  
SEGF  
ENDF  
OAM F5 segment Þltering  
0 Do not send cells with PTI=100 to the raw cell queue.  
1 Send cells with PTI=100 to the raw cell queue.  
OAM F5 end-to-end Þltering  
0 Do not send cells with PTI=101 to the raw cell queue.  
1 Send cells with PTI=101 to the raw cell queue.  
12Ð13  
Ñ
INTQ  
Ñ
Reserved, should be cleared.  
14Ð15  
Points to one of four interrupt queues available.  
Internal use only. Initialize to 0.  
0x02  
0
1
INF  
(AAL5 only) Indicates the receiver state. Initialize to 0  
0 In idle state.  
1 In AAL5 frame reception state.  
2Ð11  
12  
Ñ
Internal use only. Initialize to 0.  
ABRF  
(AAL5 only). Controls ABR ßow.  
0 ABR ßow control is disabled.  
1 ABR ßow control is enabled.  
13Ð15  
AAL  
AAL type  
000 AAL0ÑReassembly with no adaptation layer  
001 AAL1ÑATM adaptation layer 1 protocol  
010 AAL5ÑATM adaptation layer 5 protocol  
All others reserved.  
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Part IV. Communications Processor Module  
Table 29-16. RCT Field Descriptions (Continued)  
Offset Bits  
Name  
Description  
0x04  
0x08  
Ñ
Ñ
RxDBPTR Receive data buffer pointer. Holds real address of current position in the Rx buffer.  
Cell Time Used for reassembly time-out. Whenever a cell is received, the MPC8260 time stamp  
Stamp  
timer is sampled and written to this Þeld. See Section 13.3.7, ÒRISC Time-Stamp  
Control Register (RTSCR).Ó  
0x0C  
Ñ
RBD_Offset RxBD offset from RBD_BASE. Points to the channelÕs current BD. User-initialized to  
0; updated by the CP.  
0x0E-  
0x18  
Ñ
Protocol-speciÞc area.  
0x1A  
Ñ
MRBLR  
Ñ
Maximum receive buffer length. Used in both static and dynamic buffer allocation.  
Reserved, should be cleared.  
0x1C 0Ð1  
2Ð7  
PMT  
Performance monitoring table. Points to one of the available 64 performance  
monitoring tables.The starting address of the table is PMT_BASE+PMT ´ 32. Can be  
changed on-the-ßy.  
8Ð15 RBD_BASE RxBD base. Points to the Þrst BD in the channelÕs RxBD table. The 8 most-signiÞcant  
bits of the address are taken from BD_BASE_EXT in the parameter RAM. The four  
0x1E 0Ð11  
least-signiÞcant bits of the address are taken as zeros.  
12Ð14  
15  
Ñ
Reserved, should be cleared.  
PM  
Performance monitoring. Can be changed on-the-ßy.  
0 No performance monitoring for this VC.  
1 Perform performance monitoring for this VC. Whenever a cell is received for this VC  
the performance monitoring table that its code is written in the PMT Þeld is updated.  
29.10.2.2.1 AAL5 Protocol-SpeciÞc RCT  
Figure 29-26 shows the AAL5 protocol-speciÞc area of an RCT entry.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0x0E  
Offset + 0x10  
Offset + 0x12  
Offset + 0x14  
Offset + 0x16  
Offset + 0x18  
TML  
RX CRC  
RBDCNT  
Ñ
Ñ
RXBM RXFM  
Ñ
BPOOL  
Figure 29-26. AAL5 Protocol-Specific RCT  
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Part IV. Communications Processor Module  
Table 29-17 describes AAL5 protocol speciÞc RCT Þelds.  
Table 29-17. RCT Settings (AAL5 Protocol-Specific)  
Offset Bits  
Name  
TML  
Description  
Total message length. This Þeld is used by the CP.  
0x0E  
0x10  
0x14  
Ñ
Ñ
Ñ
RxCRC CRC32 temporary result.  
RBDCNT RxBD count. Indicates how may bytes remain in the current Rx buffer. RBDCNT is  
initialized with MRBLR whenever the CP opens a new buffer.  
0x16  
0x18  
Ñ
0Ð7  
8
Ñ
Ñ
Reserved, should be cleared.  
Reserved, should be cleared.  
RXBM Receive buffer interrupt mask. Determines whether the receive buffer event is disabled.  
Can be changed on-the-ßy.  
0 The event is disabled for this channel. (The RXB event is not sent to the interrupt queue  
when receive buffers are closed.)  
1 The event is enabled for this channel.  
9
RXFM Receive frame interrupt mask. Determines whether the receive frame event is disabled.  
Can be changed on-the-ßy.  
0 The event is disabled for this channel. (RXF event is not sent to the interrupt queue.)  
1 The event is enabled for this channel.  
10Ð13  
Ñ
Reserved, should be cleared.  
14Ð15 BPOOL Buffer pool. Global buffer allocation mode only. Points to one of four free buffer pools. See  
Section 29.10.5.2.4, ÒFree Buffer Pool Parameter Tables.Ó  
29.10.2.2.2 AAL5-ABR Protocol-SpeciÞc RCT  
Figure 29-27 shows the AAL5-ABR protocol-speciÞc area of an RCT entry.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0x0E  
Offset + 0x10  
Offset + 0x12  
Offset + 0x14  
Offset + 0x16  
Offset + 0x18  
AAL5 Protocol-SpeciÞc  
PCR  
RDF  
RIF  
AAL5 Protocol-SpeciÞc  
Figure 29-27. AAL5-ABR Protocol-Specific RCT  
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Part IV. Communications Processor Module  
Table 29-18 describes AAL5-ABR protocol-speciÞc RCT Þelds.  
Table 29-18. ABR Protocol-Specific RCT Field Descriptions  
Offset Bits Name  
Description  
0x0E  
0x16  
Ñ
Ñ
Ñ
AAL5 protocol-speciÞc  
PCR Peak cell rate. The peak number of cells per second of the current ABR channel. The ACR  
(allowed cell rate) never exceeds this value. PCR uses the ATMF TM 4.0 ßoating-point format.  
0x18  
0Ð3  
RDF Rate decrease factor for the current ABR channel. Controls the decrease in cell transmission  
rate upon receipt of a backward RM cell. RDF represents a negative exponent of two, that is, the  
-RDF  
decrease factor = 2  
. The decrease factor ranges from 1/32768 (RDF=0xF) to 1 (RDF=0).  
4Ð7  
RIF Rate increase factor of the current ABR channel. Controls the increase in the cell transmission  
rate upon receipt of a backward RM cell. RIF represents a negative exponent of two, that is, the  
-RIF  
increase factor = 2 . The increase factor ranges from 1/32768 (RIF=0xF) to 1 (RIF=0).  
8Ð15  
Ñ
AAL5 protocol-speciÞc  
29.10.2.2.3 AAL1 Protocol-SpeciÞc RCT  
Figure 29-28 shows the AAL1 protocol-speciÞc area of an RCT entry.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0x0E  
Offset + 0x10  
Offset + 0x12  
Offset + 0x14  
Offset + 0x16  
Offset + 0x18  
Ñ
PFM SRT INVE STF  
Ñ
Ñ
SRTS_TMP  
Ñ
SRTS Device  
Ñ
Valid Octet Size (VOS)  
SPV  
RBDCNT  
Structured Pointer (SP)  
Ñ
SN  
Ñ
SNEM  
Ñ
RXBM  
Ñ
Figure 29-28. AAL1 Protocol-Specific RCT  
Table 29-19 describes AAL1 protocol-speciÞc RCT Þelds.  
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Part IV. Communications Processor Module  
Table 29-19. AAL1 Protocol-Specific RCT Field Descriptions  
Offset Bits  
Name  
Description  
0x0E  
0Ð7  
8
Ñ
Reserved, should be cleared.  
Partially Þlled mode.  
PFM  
0 Partially Þlled cells mode is not used.  
1 Partially Þlled cells mode is used. The receiver copies only valid octets from the  
AAL1 cell to the Rx buffer. The number of the valid octets from the beginning of the  
AAL1 user data Þeld is speciÞed in the VOS (valid octet size) Þeld.  
9
SRT  
Synchronous residual time stamp. Unstructured format only. The MPC8260 supports  
clock recovery using an external SRTS PLL. The MPC8260 tracks the SRTS from the  
incoming four cells with SN = 1, 3, 5, and 7 and writes it to the external SRTS device.  
Every eight cells the CP writes a valid SRTS to external logic. (See Section 29.15,  
ÒSRTS Generation and Clock Recovery Using External Logic.Ó)  
0 SRTS mode is not used.  
1 SRTS mode is used.  
10  
11  
INVE  
STF  
Ñ
Inverted empty.  
0 RxBD[E] is interpreted normally (1 = empty, 0 = not empty).  
1 RxBD[E] is handled in negative logic (0 = empty, 1 = not empty).  
Structured format  
0 Unstructured format is used.  
1 Structured format is used.  
12Ð15  
0Ð3  
Reserved, should be cleared.  
0x10  
0x12  
SRTS_TMP Used by the CP to store the received SRTS code. After a cell with SN = 7 is received,  
the CP writes the SRTS code to the external SRTS device.  
4Ð11  
Ñ
Reserved, should be cleared.  
12Ð15  
SRTS  
Device  
Selects an SRTS device, whose address is SRTS_BASE[0Ð27] + SRTS Device[28Ð  
31]. The 16 byte-aligned SRTS_BASE is taken from the parameter RAM.  
0Ð1  
2Ð7  
Ñ
Reserved, should be cleared.  
VOS  
Valid octet size. SpeciÞes the number of valid octets from the beginning of the AAL1  
user data Þeld. For unstructured, service values 1Ð47 are valid; for structured service,  
values 1-46 are valid. Partially Þlled cell mode only.  
8
SPV  
SP  
Structured pointer valid. Should be user-initialized user to zero. Structured format only.  
9Ð15  
Structured pointer. Used by the CP to calculate the structured pointer.This Þeld should  
be initialized by the user to zero. Used in structured format only.  
0x14  
0x16  
Ñ
RBDCNT RxBD count. Indicates how may bytes remain in the current Rx buffer. Initialized with  
MRBLR whenever the CP opens a new buffer.  
0Ð12  
Ñ
Reserved, should be cleared.  
13Ð15  
SN  
Sequence number. Used by the CP to check incoming cellÕs sequence number.  
29-49  
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Part IV. Communications Processor Module  
Table 29-19. AAL1 Protocol-Specific RCT Field Descriptions (Continued)  
Offset Bits  
Name  
Description  
0x18  
0Ð3  
4
Ñ
Reserved, should be cleared.  
SNEM  
Sequence number error ßag interrupt mask  
0 This mode is disabled.  
1 When an out-of-sequence error occurs, an RXB interrupt is sent to the interrupt  
queue even if RCT[RXBM] is cleared. Note that this mode is the buffer error  
reporting mechanism during automatic data forwarding (ATM-to-TDM bridging)  
when no buffer processing is required (RCT[RXBM]=0).  
5Ð7  
8
Ñ
Reserved, should be cleared.  
RXBM  
Receive buffer interrupt mask  
0 The receive buffer event of this channel is disabled. (The event is not sent to the  
interrupt queue.)  
1 The receive buffer event of this channel is enabled.  
9Ð15  
Ñ
Reserved, should be cleared.  
29.10.2.2.4 AAL0 Protocol-SpeciÞc RCT  
Figure 29-29 shows the layout for the AAL0 protocol-speciÞc RCT.  
0
1
2
3
4
5
6
7
8
0
9
1
10  
11  
12  
13  
Ñ
14  
15  
Offset + 0x0E  
Offset + 0x10  
Offset + 0x12  
Offset + 0x14  
Offset + 0x16  
Offset + 0x18  
Ñ
INVE  
Ñ
Ñ
RXBM  
Ñ
Figure 29-29. AAL0 Protocol-Specific RCT  
Table 29-20 describes AAL0 protocol speciÞc RCT Þelds.  
Table 29-20. AAL0-Specific RCT Field Descriptions  
Offset Bits  
Name  
Description  
0x0E 0-7  
Ñ
Reserved, should be cleared.  
8-9  
10  
0b01  
INVE  
Must be programmed to 0b01 for AAL0.  
Inverted empty.  
0 RxBD[E] is interpreted normally (1 = empty, 0 = not empty).  
1 RxBD[E] is handled in negative logic (0 = empty, 1 = not empty).  
11-15  
Ñ
Ñ
Reserved, should be cleared.  
Reserved, should be cleared.  
0x10  
Ñ
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Part IV. Communications Processor Module  
Table 29-20. AAL0-Specific RCT Field Descriptions (Continued)  
Offset Bits  
Name  
Description  
0x18  
0Ð7  
8
Ñ
Reserved, should be cleared.  
Receive buffer interrupt mask  
RXBM  
0 The receive buffer event of this channel is masked. (The RXB event is not sent to the  
interrupt queue when receive buffers are closed.)  
1 The receive buffer event of this channel is enabled.  
9Ð15  
Ñ
Reserved, should be cleared.  
29.10.2.3 Transmit Connection Table (TCT)  
Figure 29-30 shows the format of an TCT entry.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
INTQ  
AAL  
15  
Offset + 0x00  
Offset + 0x02  
Offset + 0x04  
Offset + 0x06  
Offset + 0x08  
Offset + 0x0A  
Offset + 0x0C  
Offset + 0x0E  
Offset + 0x10  
Offset + 0x12  
Offset + 0x14  
Offset + 0x16  
Offset + 0x18  
Offset + 0x1a  
Offset + 0x1C  
Offset + 0x1E  
Ñ
GBL  
BO  
Ñ
DTB BIB AVCF  
Ñ
Ñ
ATT  
CPUU VCON  
ABRF  
Ñ
INF  
Tx Data Buffer Pointer (TXDBPTR)  
TBDCNT  
TBD_OFFSET  
Rate Remainder  
PCR Fraction  
PCR  
Protocol SpeciÞc  
APC Linked Channel (APCLC)  
ATM Cell Header (VPI,VCI,PTI,CLP)  
Ñ
PMT  
TBD_BASE  
TBD_BASE  
BNM STPT IMK PM  
Figure 29-30. Transmit Connection Table (TCT) Entry  
Table 29-21 describes general TCT Þelds.  
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Part IV. Communications Processor Module  
Table 29-21. TCT Field Descriptions  
Offset Bits  
Name  
Description  
0x00  
0Ð1  
2
Ñ
Reserved, should be cleared.  
GBL  
Global. Asserting GBL enables snooping of data buffers, BDs, interrupt queues and  
free buffer pool.  
3Ð4  
BO  
Byte ordering. This Þeld is used for data buffers.  
00 Reserved  
01 Power PC little endian  
1x Big endian  
5
6
Ñ
Reserved, should be cleared.  
DTB  
Data buffer bus  
0 Reside on the 60x bus.  
1 Reside on the local bus.  
7
8
BIB  
BD, interrupt queue and external SRTS logic bus  
0 Reside on the 60xbus.  
1 Reside on the local bus.  
Note: When using AAL5, AAL1 in UDC mode, BDs and data should be placed on the  
same bus (TCT[DTB]=TCT[BIB]).  
AVCF  
Auto VC off. Determines APC behavior when the last buffer associated with this VC  
has been sent and no more buffers are in the VCÕs TxBD table,  
0 The APC does not remove this VC from the schedule table and continues to  
schedule it to transmit.  
1 The APC removes this VC from the schedule table. To continue transmission after  
the host adds buffers for transmission, a new ATM TRANSMIT command is needed,  
which can be issued only after the CP clears the VCON bit. (Bit 13)  
9
Ñ
Reserved, should be cleared.  
10Ð11  
ATT  
ATM trafÞc type  
00 Peak cell-rate pacing. The host must initialize PCR and the PCR fraction. Other  
trafÞc parameters are not used.  
01 Peak and sustain cell rate pacing (VBR trafÞc). The APC performs a continuous-  
state leaky bucket algorithm (GCRA) to pace the channel-sustain cell rate.The host  
must initialize PCR, PCR fraction, SCR, SCR fraction, and BT (burst tolerance).  
10 Peak and minimum cell rate pacing (UBR+ trafÞc). The host must initialize PCR,  
PCR fraction, MCR, MCR fraction, and MDA.  
11 Reserved  
12  
CPUU  
VCON  
INTQ  
CPCS-UU+CPI insertion (used for AAL5 only).  
0 CPCS-UU+CPI insertion disabled. The transmitter clears the CPCS-UU+CPI Þelds.  
1 CPCS-UU+CPI insertion enabled. The transmitter reads the CPCS-UU+CPI (16-bit  
entry) from external memory. It should be placed after the end of the last buffer (it  
should not be included in the buffer length).  
13  
Virtual channel is on  
Should be set by the host before it issues an ATM TRANSMIT command. When the host  
sets TCT[STPS] (stop transmit), the CP deactivates this channel and clears VCON  
when the channel is next encountered in the APC scheduling table.The host can issue  
another ATM TRANSMIT command only after the CP clears VCON.  
14Ð15  
Points to one of four interrupt queues available.  
29-52  
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Part IV. Communications Processor Module  
Table 29-21. TCT Field Descriptions (Continued)  
Offset Bits  
Name  
Description  
0x02  
0
1
Ñ
Internal use only. Initialize to 0.  
INF  
Used for AAL5 Only. Indicates the transmitter state. Initialize to 0  
0 In idle state.  
1 In AAL5 frame transmission state.  
2Ð11  
12  
Ñ
Internal use only. Initialize to 0.  
ABRF  
Used for AAL5 Only.  
0 ABR Flow control is disabled.  
1 ABR Flow control is enabled.  
13Ð15  
AAL  
AAL type  
000 AAL0ÑSegmentation without any adaptation layer.  
001 AAL1ÑATM adaptation layer 1 protocol.  
010 AAL5ÑATM adaptation layer 5 protocol.  
0x04  
0x08  
Ñ
Ñ
TxDBPTR Tx data buffer pointer. Holds the real address of the current position in the Tx buffer.  
TBDCNT  
Transmit BD count. Counts the remaining data to transmit in the current transmit buffer.  
Its initial value is loaded from the data length Þeld of the TxBD when a new buffer is  
open; its value is subtracted for any transmitted cell associated with this channel.  
0x0A  
0x0C  
Ñ
TBD_OffSet Transmit BD offset. Holds offset from TBD_BASE of the current BD. Initialize to 0.  
0Ð7  
Rate Rate remainder. Used by the APC to hold the rate remainder after adding the pace  
Reminder fraction to the additive channel rate. Initialize to 0.  
8Ð15 PCR Fraction Peak cell rate fraction. Holds the peak cell rate fraction of this channel in units of 1/256  
slot. If this is an ABR channel, this Þeld is automatically updated by the CP.  
0x0E  
Ñ
PCR  
Peak cell rate. Holds the peak cell rate (in units of APC slots) permitted for this channel  
according to the trafÞc contract. Note that for an ABR channel, the CP automatically  
updates PCR to the ACR value.  
0x10  
0x16  
0x18  
Ñ
Ñ
Ñ
Ñ
Protocol-speciÞc  
APCLC  
ATMCH  
APC linked channel. Used by the CP. Initialize to 0 (null pointer).  
ATM cell header. Holds the full (4-byte) ATM cell header of the current channel. The  
transmitter appends ATMCH to the cell payload during transmission.  
0x1C  
0Ð1  
2Ð7  
Ñ
Reserved, should be cleared.  
PMT  
Performance monitoring table. Points to one of the available 64 performance  
monitoring tables. The starting address of the table is PMT_BASE+PMT ´ 32. Can be  
changed on-the-ßy.  
8Ð15  
0Ð11  
TBD_BASE TxBD base. Points to the Þrst BD in the channelÕs TxBD table. The 8 most-signiÞcant  
bits of the address are taken from BD_BASE_EXT in the parameter RAM. The four  
least-signiÞcant bits of the address are taken as zero.  
0x1E  
12  
BNM  
Buffer-not-ready interrupt mask. Can be changed on-the-ßy.  
0 The transmit buffer-not-ready event of this channel is masked. (TBNR event is not  
sent to the interrupt queue.)  
1 The buffer-not-ready event of this channel is enabled.  
13  
STPT  
Stop transmit. Initialize to 0. When the host sets this bit, the CP deactivates this  
channel and clears TCT[VCON] when the channel is next encountered in the APC  
scheduling table. Note that for AAL5 if STPT is set and frame transmission is already  
started (TCT[INF]=1), an abort indication will be sent (last cell with zero length Þeld).  
29-53  
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Part IV. Communications Processor Module  
Table 29-21. TCT Field Descriptions (Continued)  
Offset Bits  
Name  
Description  
0x1E  
14  
IMK  
Interrupt mask. Can be changed on-the-ßy.  
0 The transmit buffer event of this channel is masked. (TXB event is not sent to the  
interrupt queue.)  
1 The transmit buffer event of this channel is enabled.  
15  
PM  
Performance monitoring. Can be changed on-the-ßy.  
0 No performance monitoring for this VC.  
1 Performance is monitored for this VC. When a cell is sent for this VC, the  
performance monitoring table indicated in PMT Þeld is updated.  
29.10.2.3.1 AAL5 Protocol-SpeciÞc TCT  
Figure 29-31 shows the AAL5 protocol-speciÞc TCT.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0x10  
Offset + 0x12  
Offset + 0x14  
Tx CRC  
Total Message Length  
Figure 29-31. AAL5 Protocol-Specific TCT  
Table 29-22 describes AAL5 protocol-speciÞc TCT Þelds.  
Table 29-22. AAL5-Specific TCT Field Descriptions  
Offset  
Name  
Description  
0x10  
0x14  
Tx CRC  
Total Message Length  
CRC32 temporary result.  
This Þeld is used by the CP.  
29.10.2.3.2 AAL1 Protocol-SpeciÞc TCT  
Figure 29-32 shows the AAL1 protocol-speciÞc TCT.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
Ñ
13  
14  
SN  
15  
Offset + 0x10  
Offset + 0x12  
Offset + 0x14  
Ñ
Valid Octet Size (VOS)  
PFM SRT SPF STF  
Block Size  
SRTS Device  
SRTS_TMP  
Structured Pointer (SP)  
Figure 29-32. AAL1 Protocol-Specific TCT  
29-54  
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Part IV. Communications Processor Module  
Table 29-23 describes AAL1 protocol-speciÞc TCT Þelds.  
Table 29-23. AAL1-Specific TCT Field Descriptions  
Offset Bits  
Name  
Description  
0x10  
0-1  
Ñ
Reserved, should be cleared.  
2Ð7  
VOS  
Valid octet size. Partially Þlled cell mode only. SpeciÞes the number of valid octets  
from the beginning of the AAL1 user data Þeld. For unstructured service, values 1-47  
are valid; for structured service, values 1-46 are valid.  
8
9
PFM  
SRT  
Partially Þlled mode.  
0 Partially Þlled cells mode is not used.  
1 Partially Þlled cells mode is used. The transmitter copies only valid octets from the  
buffer to the AAL1 cell. The size of the valid octets from the beginning of the AAL1  
user data Þeld is speciÞed in the VOS (valid octet size) Þeld.  
Synchronous residual time stamp. Unstructured format only. The MPC8260 supports  
SRTS generation using external logic. If this mode is enabled, the MPC8260 reads the  
SRTS from external logic and inserts it into four cells for which SN = 1, 3, 5, or 7. The  
MPC8260 reads the new SRTS from external logic every eight cells. (See  
Section 29.15, ÒSRTS Generation and Clock Recovery Using External Logic.Ó)  
0 SRTS mode is not used.  
1 SRTS mode is used.  
10  
11  
SPF  
STF  
Structured pointer ßag. Indicates that a structured pointer has been inserted in the  
current block. The user should initialize this Þeld to zero. Used by the CP only.  
Structured format  
0 Unstructured format is used.  
1 Structured format is used.  
12  
Ñ
Reserved, should be cleared.  
13Ð15  
0Ð3  
SN  
Sequence number Þeld. Used by the CP to check the incoming cells SN. Initialize to 0.  
0x12  
0x14  
SRTS  
Device  
Used to select a SRTS device. The SRTS device address is SRTS_BASE[0Ð  
27]+SRTS_DEVICE[28:31]. SRTS_BASE is taken from the parameter RAM and is 16-  
byte aligned.  
4Ð15  
0Ð3  
Block Size Used only in structured format. SpeciÞes the structured block size (Block Size  
= 0xFFF = 4 Kbytes maximum).  
SRTS_TMP Before a cell with SN = 1 is sent, the CP reads the SRTS code from external SRTS  
logic, writes it to SRTS_TMP, and then inserts SRTS_TMP into the next four cells with  
an odd SN.  
4Ð15  
SP  
Structured pointer. Used by the CP to calculate the structured pointer. Initialize to 0.  
Structured format only.  
29.10.2.3.3 AAL0 Protocol-SpeciÞc TCT  
Figure 29-33 shows the AAL0 protocol-speciÞc TCT.  
0
1
2
3
4
5
6
7
8
0
9
10  
Ñ
11  
12  
13  
14  
15  
Offset + 0x10  
Offset + 0x12  
Offset + 0x14  
Ñ
CR10  
ACHC  
Ñ
Ñ
Figure 29-33. AAL0 Protocol-Specific TCT  
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Table 29-24 describes AAL0 protocol-speciÞc TCT Þelds.  
Table 29-24. AAL0-Specific TCT Field Descriptions  
Offset Bits  
Name  
Description  
0x10  
0Ð7  
8
Ñ
Reserved, should be cleared.  
Must be 0.  
0
9
CR10 CRC-10  
0 CRC10 insertion is disabled.  
1 CRC10 insertion is enabled.  
10  
11  
Ñ
Reserved, should be cleared.  
ACHC ATM cell header change  
0 Normal operation ATM cell header is taken from AAL0 buffer.  
1 VPI/VCI (28 bits) are taken from TCT.  
12Ð15  
Ñ
Ñ
Ñ
Reserved, should be cleared.  
Reserved, should be cleared.  
0x12Ð  
0x14  
29.10.2.3.4 VBR Protocol-SpeciÞc TCTE  
Figure 29-34 shows the VBR protocol-speciÞc TCTE.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0x00  
Offset + 0x02  
Offset + 0x04  
Offset + 0x06  
Offset + 0x08  
Offset + 0x0A  
Offset + 0x0C  
Offset + 0x0E-1E  
SCR  
Burst Tolerance (BT)  
Out of Buffer Rate (OOBR)  
Sustain Rate Remainder (SRR)  
SCR Fraction (SCRF)  
Sustain Rate (SR)  
VBR2  
Ñ
Ñ
Figure 29-34. Transmit Connection Table Extension (TCTE)ÑVBR Protocol-  
Specific  
Table 29-25 describes VBR protocol-speciÞc TCTE Þelds.  
Table 29-25. VBR-Specific TCTE Field Descriptions  
Offset Bits Name  
Description  
0x00  
0x02  
0x04  
Ñ
Ñ
Ñ
SCR Sustain cell rate. Holds the sustain cell rate (in slots) permitted for this channel according to  
the trafÞc contract. To pace the channelÕs sustain cell rate, the APC performs a continuous-  
state leaky bucket algorithm (GCRA).  
BT  
Burst tolerance. Holds the burst tolerance permitted for this channel according to the trafÞc  
contract.The relationship between the BT and the maximum burst size (MBS) is BT=(MBS-2)  
´ (SCR-PCR) + SCR.  
OOBR Out-of-buffer rate. In out of buffer state (when the transmitter tries to open TxBD whose R bit  
is not set) the APC reschedules the current channel according to OOBR rate.  
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Table 29-25. VBR-Specific TCTE Field Descriptions (Continued)  
Offset Bits Name  
Description  
0x06  
0Ð7  
SRR Sustain rate remainder. Holds the sustain rate remainder after adding the pace fraction Þeld  
to the additive channel sustain rate. Used by the APC to calculate the channel GCRA (leaky  
bucket) state. Initialized to 0.  
8Ð15 SCRF Holds the sustain cell rate fraction of this channel in units of 1/256 slot.  
0x08  
0x0C  
Ñ
SR  
Sustain rate. Used by the APC to hold the sustain rate after adding the pace Þeld to the  
additive channel sustain rate. Used by the APC to calculate the channel GCRA (leaky  
bucket) state.  
0
VBR2 VBR type  
0 Regular VBR. CLP=0+1 cells are rescheduled by PCR or SCR according to the GCRA  
state.  
1 VBR Type 2. CLP=0 cells are rescheduled by PCR or SCR according to the GCRA state.  
CLP=1 cells are rescheduled by PCR.  
1Ð15  
Ñ
Ñ
Ñ
Reserved, should be cleared.  
Reserved, should be cleared.  
0x0EÐ  
0x1E  
29.10.2.3.5 UBR+ Protocol-SpeciÞc TCTE  
Figure 29-35 shows the UBR+ protocol-speciÞc TCTE.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0x00  
Offset + 0x02  
MCR  
Ñ
MCR Fraction (MCRF)  
Offset + 0x04  
Maximum Delay Allowed (MDA)  
Ñ
Offset + 0x06Ð0x1E  
Figure 29-35. UBR+ Protocol-Specific TCTE  
Table 29-26 describes UBR+ protocol-speciÞc TCTE Þelds.  
Table 29-26. UBR+ Protocol-Specific TCTE Field Descriptions  
Offset Bits Name  
Description  
MCR Minimum cell rate for this channel. MCR is in units of APC time slots.  
Reserved, should be cleared.  
0x00  
0x02  
Ñ
0Ð7  
Ñ
8Ð  
15  
MCRF Minimum cell rate fraction. Holds the minimum cell rate fraction of this channel in units of 1/  
256 slot.  
0x04  
Ñ
MDA Maximum delay allowed. The maximum time-slot service delay allowed for this priority level  
before the APC reduces the scheduling rate from PCR to MCR.  
0x06Ð  
0x1E  
Ñ
Ñ
Reserved, should be cleared.  
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29.10.2.3.6 ABR Protocol-SpeciÞc TCTE  
Figure 29-36 shows the ABR protocol-speciÞc TCTE.  
0
1
2
3
4
5
6
7
8
9
10  
11 12 13 14 15  
Offset + 0x00  
Offset + 0x02  
Offset + 0x04  
ER-TA  
CCR-TA  
MCR-TA  
CP-TA  
MCR  
Offset + 0x06 TUAR  
Offset + 0x08  
Ñ
CI-TA NI-TA  
Ñ
Ñ
CI-VC  
Ñ
Offset + 0x0A  
UNACK  
ACR  
Offset + 0x0C  
Offset + 0x0E ACRC  
Offset + 0x10  
Ñ
RM Cell Time Stamp (RCTS)  
Offset + 0x12  
Offset + 0x14 FRST  
Offset + 0x16  
Ñ
CDF  
COUNT  
ICR  
Offset + 0x18  
CRM  
ADTF  
ER  
Offset + 0x1A  
Offset + 0x1C  
Offset + 0x1E  
ER-BRM  
Figure 29-36. ABR Protocol-Specific TCTE  
Table 29-27 describes ABR-speciÞc TCTE Þelds.  
Table 29-27. ABR-Specific TCTE Field Descriptions  
Offset Bits  
Name  
Description  
0x00  
0x02  
0x04  
0x06  
Ñ
Ñ
Ñ
0
ER-TA Explicit rateÐturn-around cell. Holds the ER of the last received F-RM cell. If another F-RM  
cell arrives before the previous F-RM cell was turned around, this Þeld is overwritten by the  
new RM cellÕs ER.  
CCR-TA Current cell rateÐturn-around cell. Holds the CCR of the last received F-RM cell. If another  
F-RM cell arrives before the previous F-RM cell was turned around, this Þeld is overwritten  
by the new RM cellÕs CCR.  
MCR-TA Minimum cell rateÐturn-around cell. Holds the MCR of the last received F-RM cell. If  
another F-RM cell arrives before the previous F-RM cell is turned around, this Þeld is  
overwritten by the new RM cellÕs MCR.  
TUAR Turn-around ßag. The CP sets TUAR to indicate that a new F-RM cell was received, which  
causes the transmitter to send a B-RM cell whenever the ABR ßow control permits.  
Initialize to 0.  
1
2
Ñ
Reserved, should be cleared.  
CI-TA Congestion indicationÐturn-around cell. Holds the CI of the last received F-RM cell. If  
another F-RM cell arrives before the previous F-RM cell was turned around, CI-TA is  
overwritten by the new RM cellÕs CI.  
3
NI-TA No increaseÐturn-around cell. Holds the NI of the last received F-RM cell. If another F-RM  
cell arrives before the previous one was turned around, NI-TA is overwritten by the new  
RM cellÕs NI.  
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Table 29-27. ABR-Specific TCTE Field Descriptions (Continued)  
Offset Bits  
Name  
Description  
4Ð6  
7
Ñ
Reserved, should be cleared.  
CP-TA Cell loss priorityÐturn-around cell. Holds the CLP of the last received F-RM cell. If another  
F-RM cell arrives before the previous one was turned around, CP-TA is overwritten by the  
new RM cellÕs CLP.  
8Ð9  
10  
Ñ
Reserved, should be cleared.  
CI-VC Congestion indication -VC. Holds the EFCI (explicit forward congestion indication) of the  
last user data cell. The CI bit of the turned around RM cell is ORed with the CI-VC.  
Initialize to 0.  
11Ð15  
Ñ
Reserved, should be cleared.  
0x08  
0x0A  
0x0C  
0x0E  
Ñ
Ñ
Ñ
MCR  
Minimum cell rate Holds the minimum number of cells/sec of the current ABR channel.  
Uses the ATMF TM 4.0 ßoating-point format.  
UNACK Used by the CP to count F-RM cells sent in an absence of received B-RM cells. Initialize to  
0.  
ACR  
Allowed cell rate The cells per second allowed for the current ABR channel. Uses the  
ATMF TM 4.0 ßoating-point format. Initialize with ICR.  
0
ACRC ACR change. Indicates a change in ACR. Initialize to one.  
Reserved, should be cleared.  
1Ð15  
Ñ
0
Ñ
0x10  
0x14  
RCTS RM cell time stamp. Used exclusively by the CP. Initialize to zero.  
FRST First turn. Used exclusively by the CP. Indicates the Þrst turn of a backward RM cell, which  
has priority over a data cell. Initialized to 0.  
1Ð3  
4Ð7  
Ñ
Reserved, should be cleared.  
CDF  
Cutoff decrease factor. Controls the decrease in the ACR associated with missing B-RM  
cells feedback. CDF represents a negative exponent of two, that is, the cutoff decrease  
-CDF  
factor = 2  
(CDF=0b0000). All other CDF values falling outside this range are invalid.  
. The cutoff decrease factor ranges from 1/64 (CDF=0b0110) to 1  
8Ð15  
Ñ
COUNT Count. Used only by the CP. Holds the number of cells sent since the last forward RM cell.  
Initialize with Nrm (in the parameter RAM).  
0x16  
0x18  
0x1A  
ICR  
Initial cell rate. The number of cells per second of the current ABR channel. The channelÕs  
ACR is initialized with ICR. ICR uses the ATMF TM 4.0 ßoating-point format.  
Ñ
CRM  
Missing RM cells count. Limits the number of forward RM cells that may be sent in the  
absence of received backward RM cell. The CRM is in units of cells.  
Ñ
ADTF ADTFÐACR decrease time factor. The ADTF period is 500 ms as deÞned in the TM 4.0.  
The ADTF value is deÞned by the system clock and the time stamp timer prescaler; see  
Section 13.3.7, ÒRISC Time-Stamp Control Register (RTSCR).Ó For a time stamp prescaler  
of 1 µs, ADTF should be programmed to 500m/(1µs ´ 1024)= 488.  
0x1C  
0x1E  
Ñ
Ñ
ER  
Explicit rate. Holds the explicit rate value (in cells/sec) of the current ABR channel. ER is  
copied to the F-RM cell ER Þeld. The user usually initializes this Þeld to PCR. ER uses the  
ATMF TM 4.0 ßoating-point format.  
ER-BRM Explicit rate-backward RM cell. Holds the maximum explicit rate value (in cells/sec)  
allowed for B-RM cells. The ER-TA Þeld which is inserted to each B-RM cell is limited by  
this value. ER-BRM uses the ATMF TM 4.0 ßoating-point format.  
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29.10.3 OAM Performance Monitoring Tables  
The OAM performance monitoring tables include performance monitoring block test  
parameters, as shown in Figure 29-37. Each block test needs a 32-byte performance  
monitoring table in the dual-port RAM. In the connectionÕs RCT and TCT, the user  
allocates an OAM performance table to a VCC or VPC. See Section 29.6.6, ÒPerformance  
Monitoring.Ó PMT_BASE in the parameter RAM points to the base address of the tables.  
The starting address of each PM table is given by PMT_BASE + RCT/TCT[PMT] ´ 32.  
0
1
2
3
4
5
6
7
8
9
10  
BLCKSIZE  
TX Cell Count (TCC)  
11  
12  
13  
14  
15  
Offset + 0x00 FMCE TSTE  
Offset + 0x02  
Offset + 0x04  
Offset + 0x06  
Offset + 0x08  
Offset + 0x0A  
Offset + 0x0C  
Offset + 0x0E  
Offset + 0x10  
Offset + 0x12  
Offset + 0x14  
Offset + 0x16  
Offset + 0x18  
Offset + 0x1A  
Offset + 0x1C  
Offset + 0x1E  
Ñ
Ñ
TUC1  
TUC0  
BEDC0+1-Tx  
BEDC0+1-RX  
TRCC1  
TRCC0  
Ñ
SN-FMC  
Ñ
PM CELL HEADER (VPI,VCI,PTI,CLP)  
Ñ
Figure 29-37. OAM Performance Monitoring Table  
Table 29-28 describes Þelds in the performance monitoring table.  
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Table 29-28. OAMÑPerformance Monitoring Table Field Descriptions  
Offset Bits  
Name  
Description  
Enables FMC transmission. Initialize to 1.  
0x00  
0
1
FMCE  
TSTE  
FMC time stamp enable  
0 The time stamp Þeld of the FMC is coded with all 1Õs.  
1 The value of the time stamp timer is inserted into the time stamp Þeld of the FMC.  
2Ð4  
Ñ
TCC  
Ñ
Reserved, should be cleared.  
5Ð15  
TX cell count. Used by the CP to count data cells sent. Initialize to zero.  
Reserved, should be cleared.  
0x02 0Ð4  
5Ð15  
BLCKSIZE Performance monitoring block size ranging from 1 to 2,047 cells.  
0x04  
0x06  
0x08  
Ñ
Ñ
Ñ
TUC1  
TUC0  
Total user cell 1. Count of CLP = 1 user cells (modulo 65,536) sent. Initialize to 0.  
Total user cell 0. Count of CLP = 0 user cells (modulo 65,536) sent. Initialize to 0.  
BEDC0+1-Tx Block error detection code 0+1Ðtransmitted cells. Even parity over the payload of the  
block of user cells sent since the last FMC. Initialize to 0.  
0x0A  
0x0C  
0x0E  
Ñ
Ñ
Ñ
BEDC0+1-RX Block error detection code 0+1Ðreceived cells. Even parity over the payload of the  
block of user cells received since the last FMC. Initialize to 0.  
TRCC1  
TRCC0  
Total received cell 1. Count of CLP = 1 user cells (modulo 65,536) received. Initialize  
to 0.  
Total received cell 0. Count of CLP = 0 user cells (modulo 65,536) received. Initialize  
to 0.  
0x10 0Ð7  
8Ð15  
Ñ
SN-FMC  
Ñ
Reserved, should be cleared.  
Sequence number of the last FMC sent. Initialize to 0.  
Reserved, should be cleared.  
0x12  
0x14  
Ñ
Ñ
PMCH  
PM cell header. Holds the ATM cell header of the FMC, BRC to be inserted by the CP  
into the Tx cell ßow.  
0x18Ð  
0x1E  
Ñ
Ñ
Reserved, should be cleared.  
29.10.4 APC Data Structure  
The APC data structure consists of three elements: the APC parameter tables for the PHY  
devices, the APC priority table, and the APC scheduling tables. See Figure 29-38.  
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APC Parameter Tables  
APC Priority Table  
APC Scheduling Tables  
Priority 1  
Priority 2  
Priority 3  
Priority 4  
Priority 5  
Priority 6  
Priority 7  
Priority 8  
Priority 1 Scheduling Table  
Priority 2 Scheduling Table  
Priority 3 Scheduling Table  
Priority 4 Scheduling Table  
Priority 5 Scheduling Table  
Priority 6 Scheduling Table  
Priority 7 Scheduling Table  
Priority 8 Scheduling Table  
Parameter Table  
PHY #0  
Parameter Table  
PHY #1  
Parameter Table  
PHY #31  
Note: The shaded areas represent the active structures for an example implementation of PHY #0  
with two priorities. (The unshaded areas and dashed arrows represent unused structures.)  
Figure 29-38. ATM Pace Control Data Structure  
29.10.4.1 APC Parameter Tables  
Each PHYÕs APC parameter table, shown in Table 29-29, holds parameters that deÞne the  
priority table location, the number of priority levels, and other APC parameters. The table  
resides in the dual-port RAM. The parameter APCP_BASE, described in Section 29.10.1,  
ÒParameter RAM,Ó points to the base address of PHY#0Õs parameter table.  
For multiple PHYs, the table structure is duplicated. Each table resides in 32 bytes of  
memory. The starting address of each APC parameter table is given by APCP_BASE +  
PHY# ´ 32. Note however that in slave mode with multiple PHYs, the parameter table  
always resides at APCP_BASE regardless of the PHY address.  
Table 29-29. APC Parameter Table  
1
Offset  
Name  
Width  
Description  
0x00  
0x02  
APCL_FIRST  
APCL_LAST  
Hword Address of Þrst entry in the priority table. Must be 8-byte aligned. User-initialized.  
Hword Address of last entry in the priority table. Must be 8-byte aligned. User-initialized  
as APCL_FIRST + 8 x (number_of_priorities - 1).  
0x04  
0x06  
APCL_PTR  
CPS  
Hword Address of current priority entry used by the CP. User-initialized with  
APCL_FIRST.  
Byte  
Cells per slot. Determines the number of cells sent per APC slot. See  
Section 29.3.2, ÒAPC Unit Scheduling Mechanism.Ó User-deÞned. (0x01 = 1 cell;  
0xFF = 255 cells.) Note that if ABR is used, CPS must be a power of two.  
0x07  
0x08  
CPS_CNT  
Byte  
Cells sent per APC slot counter. User-initialized to CPS; used by the CP.  
MAX_ITERATIO Byte  
Max iteration allowed. Number of scan iterations allowed in the APC. User-  
deÞned. This parameter limits the time spent in a single APC routine, thereby  
avoiding excessive APC latency.  
N
0x09  
CPS_ABR  
Byte  
ABR only. Cells per slot represented as a power of two. User-deÞned. (For  
example, if CPS is 1, CPS_ABR = 0x00; if CPS is 8, CPS_ABR = 0x03.)  
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Table 29-29. APC Parameter Table (Continued)  
1
Offset  
Name  
Width  
Description  
0x0A  
LINE_RATE_AB Hword ABR only. The PHY line rate in cells/sec, represented in TM 4.0 ßoating-point  
R
format. User-deÞned.  
0xC  
REAL_TSTP  
APC_STATE  
Word Real-time stamp pointer used internally by the APC. Initialize to 0.  
Word Used internally by the APC. Initialize to 0.  
0x10  
1
Offset values are to APCP_BASE+PHY# ´ 32. However, in slave mode, the offset is from APCP_BASE regard-  
less of the PHY address.  
29.10.4.2 APC Priority Table  
Each PHYÕs APC priority table holds pointers to the APC scheduling table of each priority  
level. It resides in the dual-port RAM. The priority table can hold up to eight priority levels.  
Table 29-30 shows the structure of a priority table entry.  
Table 29-30. APC Priority Table Entry  
Offset  
Name  
Width  
Description  
0x00  
APC_LEVi_BASE Hword APC level i base address. Pointer to the first slot in the APC scheduling table for  
level i. Should be half-word aligned. User-deÞned.  
0x02  
APC_LEVi_END Hword APC level i end address. Pointer to the last slot in the APC scheduling table for  
level i. Should be half-word aligned. User-deÞned.  
0x04  
0x06  
APC_LEVi_RPTR Hword APC level i real-time/service pointers. APC table pointers used internally by the  
APC. Initialize both pointers to APC_LEVi_BASE.  
APC_LEVi_SPTR Hword  
29.10.4.3 APC Scheduling Tables  
The APC uses APC scheduling tables (one table for each priority level) to schedule channel  
transmission. A scheduling table is divided into time slots, as shown in Figure 29-39. Each  
slot is a half-word entry. Note that the APC scheduling tables should be cleared before the  
APC unit is enabled.  
APC_LEVi_BASE  
Control  
Slot  
slot 0  
slot 1  
slot N  
Half Word Entry  
APC_LEVi_END  
Figure 29-39. The APC Scheduling Table Structure  
Slot N+1 is used as a control slot, as shown in Figure 29-40.  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Field  
TCTE  
000_0000_0000_0000  
Figure 29-40. Control Slot  
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Table 29-31 describes control slot Þelds.  
Table 29-31. Control Slot Field Description  
Bits Name  
Description  
0
TCTE Used for external channels only.  
0 Channels in this scheduling table do not use external TCTE. (No external VBR, ABR, UBR+  
channels)  
1 Channels in this scheduling table use external TCTE. (External VBR, ABR, UBR+ channels)  
1Ð15  
Ñ
Reserved, should be cleared.  
29.10.5 ATM Controller Buffer Descriptors (BDs)  
Each ATM channel has separate receive and transmit BD tables. The number of BDs per  
channel and the size of the buffers is user-deÞned. The last BD in each table holds a wrap  
indication. Each BD in the TxBD table points to a buffer to send. At the receive side, the  
user can choose one of two modes:  
¥
Static buffer allocation. In this mode, the user allocates dedicated buffers to each  
ATM channel (that is, the user associates each BD with one buffer). Static buffer  
allocation is useful when the connection rate is known and constant and when data  
must be reassembled in a particular memory space.  
¥
Global buffer allocation. Available for AAL5 only. In this mode, buffer allocation is  
dynamic. The user allocates receive buffers and places them in global buffer pools.  
When the CP needs a receive buffer, it Þrst fetches a buffer pointer from one of the  
global buffer pools and writes the pointer to the current RxBD. Global buffer  
allocation is optimized for allocating memory among many ATM channels with  
variable data rates, such as ABR channels.  
29.10.5.1 Transmit Buffer Operations  
The user prepares a table of BDs pointing to the buffers to be sent. The address of the Þrst  
BD is put in the channelÕs TCT[TBD_BASE]. The transmit process starts when the core  
issues an ATM TRANSMIT command. The CP reads the Þrst TxBD in the table and sends its  
associated buffer. When the current buffer is Þnished, the CP increments TBD_Offset,  
which holds the offset from TBD_BASE to the current BD. It then reads the next BD in the  
table. If the BD is ready (TxBD[R] = 1), the CP continues sending. If the current BD is not  
ready, the CP polls the ready bit at the channel rate unless TCT[AVCF] = 1, in which case  
the CP removes the channel from the APC and clears TCT[VCON]. The core must issue a  
new ATM TRANSMIT command to restart transmission.  
Figure 29-41 shows the ready bit in the TxBD tables and their associated buffers for two  
example ATM channels.  
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Ch1 TxBD Table  
Tx Buffer 1 of Channel 1  
Tx Buffer 2 of Channel 1  
Tx Buffer 3 of Channel 1  
Tx Buffer 4 of Channel 1  
Tx Buffer 5 of Channel 1  
TBD_BASE  
0
1
1
0
0
BD 1  
BD 2  
BD 3  
BD 4  
BD 5  
Ch1 TxBD Table  
Pointers in the TCT  
TBD_Offset  
Ch4 TxBD Table  
Tx Buffer 1 of Channel 4  
Tx Buffer 2 of Channel 4  
Tx Buffer 3 of Channel 4  
Tx Buffer 4 of Channel 4  
Tx Buffer 5 of Channel 4  
Tx Buffer 6 of Channel 4  
Tx Buffer 7 of Channel 4  
TBD_BASE  
TBD_Offset  
1
0
0
0
0
1
1
BD 1  
BD 2  
BD 3  
BD 4  
BD 5  
BD 6  
BD 7  
Ch4 TxBD Table  
Pointers in the TCT  
Note: The shaded buffers are ready to be sent; unshaded buffers are waiting to be prepared.  
Figure 29-41. Transmit Buffers and BD Table Example  
29.10.5.2 Receive Buffers Operation  
ForAAL5 channels, the user should choose to operate in static buffer allocation or in global  
buffer allocation by writing to RCT[BUFM]. AAL1 and AAL0 channels must use static  
buffer allocation.  
29.10.5.2.1 Static Buffer Allocation  
The user prepares a table of BDs pointing to the receive buffers. The address of the Þrst BD  
is put in the channelÕs RCT[RBD_BASE]. When anATM cell arrives, the CP opens the Þrst  
BD in the table and starts Þlling its associated buffer with received data. When the current  
buffer is full, the CP increments RBD_Offset, which is the offset to the current BD from  
RBD_BASE, and reads the next BD in the table. If the BD is empty (RxBD[E] = 1), the CP  
continues receiving. If the BD is not empty, a busy condition has occurred and a busy  
interrupt is sent to the event queue.  
Figure 29-42 shows the empty bit in the RxBD tables and their associated buffers for two  
example ATM channels.  
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Ch1 RxBD Table  
Rx Buffer 1 of Channel 1  
Rx Buffer 2 of Channel 1  
Rx Buffer 3 of Channel 1  
Rx Buffer 4 of Channel 1  
Rx Buffer 5 of Channel 1  
RBD_BASE  
0
1
1
0
0
BD 1  
BD 2  
BD 3  
BD 4  
BD 5  
Ch1 RxBD Table  
Pointers in the RCT  
RBD_Offset  
Ch4 RxBD Table  
Rx Buffer 1 of Channel 4  
Rx Buffer 2 of Channel 4  
Rx Buffer 3 of Channel 4  
Rx Buffer 4 of Channel 4  
Rx Buffer 5 of Channel 4  
Rx Buffer 6 of Channel 4  
Rx Buffer 7 of Channel 4  
RBD_BASE  
RBD_Offset  
1
0
0
0
0
1
1
BD 1  
BD 2  
BD 3  
BD 4  
BD 5  
BD 6  
BD 7  
Ch4 RxBD Table  
Pointers in the RCT  
Note: The shaded buffers are empty; unshaded buffers are waiting to be processed.  
Figure 29-42. Receive Static Buffer Allocation Example  
29.10.5.2.2 Global Buffer Allocation  
The user prepares a table of BDs without assigning buffers to them (no buffer pointers). The  
address of the Þrst BD is put into the channelÕs RCT[RBD_BASE]. The user also prepares  
sets of free buffers (of size RCT[MRBLR]) in up to four free buffer pools (chosen in  
RCT[BPOOL]); see Section 29.10.5.2.3, ÒFree Buffer Pools.Ó  
When an ATM cell arrives, the CP opens the Þrst BD in the table, fetches a buffer pointer  
from the free buffer pool associated with this channel, and writes the pointer to  
RxBD[RXDBPTR], the receive data buffer pointer Þeld in the BD. When the current buffer  
is full, the CP increments RBD_Offset, which is the offset from the RBD_BASE to the  
current BD, and reads the next BD in the table. If the BD is empty (RxBD[E] = 1), the CP  
fetches another buffer pointer from the free buffer pool and reception continues. If the BD  
is not empty, a busy condition occurs and a busy interrupt is sent to the event queue  
specifying the ATM channel code. As software then processes each full buffer (RxBD[E] =  
0), it sets RxBD[E] and copies the buffer pointer back to the free buffer pool.  
Figure 29-43 shows two ATM channelsÕ BD tables and one free buffer pool. Both channels  
are associated with free buffer pool 1. The CP allocates the Þrst two buffers of buffer pool  
1 to channel 1 and the third to channel 4.  
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Ch1 RxBD Table  
RBD_BASE  
RBD_Offset  
0
1
1
1
1
BD 1  
BD 2  
BD 3  
BD 4  
BD 5  
Buffer 1 of FBP1  
Buffer 2 of FBP1  
Free Buffer Pool 1  
FBP1_BASE  
FBP1_PTR  
Pointer 1  
Pointer 2  
Pointer 3  
Pointer 4  
Pointer 5  
Pointer 6  
Ch4 RxBD Table  
Buffer 4  
Buffer 5  
Buffer 6  
RBD_BASE,  
RBD_Offset  
1
1
1
1
BD 1  
BD 2  
BD 3  
BD 4  
Buffer 3 of FBP1  
Notes: Buffers 2 and 3 are receiving data. After buffer 1 is processed, it can be returned to the pool.  
Figure 29-43. Receive Global Buffer Allocation Example  
29.10.5.2.3 Free Buffer Pools  
As Figure 29-44 shows, when a buffer pointer is fetched from a pool, the CP clears the  
entryÕs valid bit and increments FBP#_PTR. After the CP uses an entry with the wrap bit  
set (W = 1), it returns to the Þrst entry in the pool. After a buffer pointer is returned to the  
pool, the user should set V to indicate that the entry is valid. If the CP tries to read an invalid  
entry (V = 0), the buffer pool is out of free buffers; the global-buffer-pool-busy event is then  
set in FCCE[GBPB] and a busy interrupt is sent to the interrupt queue specifying the ATM  
channel code associated with the pool.  
Word  
FBP#_BASE  
Software (Core) Pointer  
FBP#_PTR  
V = 1 W = 0  
V = 1 W = 0  
V = 1 W = 0  
V = 0 W = 0  
V = 0 W = 0  
V = 0 W = 0  
V = 1 W = 0  
V = 1 W = 0  
V = 1 W = 1  
Buffer Pointer  
Buffer Pointer  
Buffer Pointer  
Invalid  
Invalid  
Invalid  
Buffer Pointer  
Buffer Pointer  
Buffer Pointer  
Figure 29-44. Free Buffer Pool Structure  
Figure 29-45 describes the structure of a free buffer pool entry.  
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0
1
2
3
4
5
6
7
8
9
10  
Buffer Pointer (BP)  
Buffer Pointer (BP)  
11  
12  
13  
14  
15  
Offset + 0x00  
Offset + 0x02  
V
Ñ
W
I
Figure 29-45. Free Buffer Pool Entry  
Table 29-32 describes free buffer pool entry Þelds.  
Table 29-32. Free Buffer Pool Entry Field Descriptions  
Offset Bits Name  
Description  
0x00  
0
V
Valid buffer entry.  
0 This free buffer pool entry contains an invalid buffer pointer.  
1 This free buffer pool entry contains a valid buffer pointer.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap bit. When set, this bit indicates the last entry in the circular table. During initialization,  
the host must clear all W bits in the table except the last one, which must be set.  
3
I
Red-line interrupt. Can be used to indicate that the free buffer pool has reached a red line and  
additional buffers should be added to this pool to avoid a busy condition.  
0 No interrupt is generated.  
1 A red-line interrupt is generated when this buffer is fetched from the free buffer pool.  
4Ð15  
0Ð15  
BP Buffer pointer. Points to the start address of the receive buffer. The four msbs are control bits,  
and the four msbs of the real buffer pointer are taken from the four msbs of the parameter  
FBP_ENTRY_EXT in the free buffer pool parameter table.  
0x02  
29.10.5.2.4 Free Buffer Pool Parameter Tables  
The free buffer pool parameters are held in parameter tables in the dual-port RAM; see  
Table 29-33. FBT_BASE in the parameter RAM points to the base address of these tables.  
Each of the four free buffer pools has its own parameter table with a starting address given  
by FBT_BASE+ RCT[BPOOL] ´ 16.  
Table 29-33. Free Buffer Pool Parameter Table  
1
Offset  
Bits  
Name  
Description  
0x00  
Ñ
FBP_BASE  
Free buffer pool base. Holds the pointer to the Þrst entry in the free buffer pool.  
FBP_BASE should be word aligned. User-deÞned.  
0x04  
0x08  
0x0A  
Ñ
Ñ
0
FBP_PTR  
Free buffer pool pointer. Pointer to the current entry in the free buffer pool.  
Initialize to FBP_BASE.  
FBP_ENTRY_EXT Free buffer pool entry extension. FBP_ENTRY_EXT[0Ð3] holds the four left bits  
of FBP_ENTRY. FBP_ENTRY_EXT[4Ð15] should be cleared. User-deÞned.  
BUSY  
RLI  
The CP sets this bit when it tries to fetch buffer pointer with V bit clear.  
FCCE[GBPB] is also set. Initialize to zero.  
1
Red-line interrupt. Set by the CP when it fetches a buffer pointer with I = 1.  
FCCE[GRLI] is also set. Initialize to zero.  
2Ð7  
Ñ
Reserved, should be cleared.  
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Table 29-33. Free Buffer Pool Parameter Table (Continued)  
1
Offset  
Bits  
Name  
EPD  
Description  
8
Early packet discard.  
0 Normal operation.  
1 AAL5 frames in progress are received, but new AAL5 frames associated with  
this pool are discarded. Can be used to implement EPD under core control.  
9Ð15  
Ñ
Ñ
Reserved, should be cleared.  
0x0C  
FBP_ENTRY  
Free buffer pool entry. Initialize with the Þrst entry of the free buffer pool. Note  
that FBP_ENTRY must be reinitialized when a busy state occurs.  
1
Offset from FBT_BASE+RCT[BPOOL] ´ 16  
29.10.5.3 ATM Controller Buffers  
Table 29-34 describes properties of the ATM receive and transmit buffers.  
Table 29-34. Receive and Transmit Buffers  
Receive  
Transmit  
AAL  
Size  
Alignment  
Size  
Alignment  
AAL5 Multiple of 48 octets (except last buffer in frame)  
AAL1 At least 47 octets  
Double word aligned Any  
No requirement  
No requirement  
Burst-aligned  
At least 47 octets No requirement  
52Ð64 octets. No requirement  
AAL0 52-64 octets.  
29.10.5.4 AAL5 RxBD  
Figure 29-46 shows the AAL5 RxBD.  
0
1
2
3
4
L
5
F
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0x00  
Offset + 0x02  
Offset + 0x04  
Offset + 0x06  
E
Ñ
W
I
CM  
Ñ
CLP CNG ABRT CPUU LNE CRE  
Data Length (DL)  
Rx Data Buffer Pointer (RXDBPTR)  
Figure 29-46. AAL5 RxBD  
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Table 29-35 describes AAL5 RxBD Þelds.  
Table 29-35. AAL5 RxBD Field Descriptions  
Offset Bits  
Name  
E
Description  
0x00  
0
Empty.  
0 The buffer associated with this RxBD is full or data reception was aborted due to an  
error. The core can read or write any Þelds of this RxBD. The CP does not use this BD  
again while E remains zero.  
1 The buffer associated with this RxBD is empty or reception is in progress. This RxBD  
and its receive buffer are controlled by the CP. Once E is set, the core should not write  
any Þelds of this RxBD.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (Þnal BD in table)  
0 This is not the last BD in the RxBD table of the current channel.  
1 This is the last BD in the RxBD table of this current channel. After this buffer has been  
used, the CP receives incoming data into the Þrst BD in the table.The number of RxBDs  
in this table is programmable and is determined only by the W bit. The current table  
cannot exceed 64 Kbytes.  
3
4
I
Interrupt  
0 No interrupt is generated after this buffer has been used.  
1 An Rx buffer event is sent to the interrupt queue after the ATM controller uses this buffer.  
FCCE[GINTx] is set in the event register when INT_CNT reaches the global interrupt  
threshold.  
L
Last in frame. Set by the ATM controller for the last buffer in a frame.  
0 Buffer is not last in a frame.  
1 Buffer is last in a frame. ATM controller writes frame length in DL and updates the error  
ßags.  
5
6
F
First in frame. Set by the ATM controller for the Þrst buffer in a frame.  
0 The buffer is not the Þrst in a frame.  
1 The buffer is the Þrst in a frame.  
CM  
Continuous mode  
0 Normal operation.  
1 The CP does not clear the empty bit after this BD is closed, allowing the associated  
buffer to be overwritten automatically when the CP next accesses this BD.  
7Ð9  
10  
Ñ
Reserved, should be cleared.  
CLP  
Cell loss priority. At least one cell associated with the current message was received with  
CLP = 1. May be set at the last buffer of the message.  
11  
CNG  
Congestion indication. The last cell associated with the current message was received  
with PTI middle bit set. CNG may be set at the last buffer of the message.  
12  
13  
ABRT  
CPUU  
Abort message indication. The current message was received with Length Þeld zero.  
CPCS-UU+CPI indication. Set when the CPCS-UU+CPI Þeld is non zero. CPUU may be  
set at the last buffer of the message.  
14  
15  
LNE  
CRE  
Rx length error. AAL5 CPCS-PDU length violation. May be set only for the last BD of the  
frame if the pad length is greater than 47 or less than zero octets.  
Rx CRC error. Indicates CRC32 error in the current AAL5 PDU. Set only for the last BD of  
the frame.  
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Table 29-35. AAL5 RxBD Field Descriptions (Continued)  
Offset Bits  
Name  
Description  
0x02  
0x04  
Ñ
DL  
Data length.The number of octets written by the CP into this BDÕs buffer. It is written by the  
CP once the BD is closed. In the last BD of a frame, DL contains the total frame length.  
RXDBPTR Rx data buffer pointer. Points to the Þrst location of the associated buffer; may reside in  
internal or external memory. This pointer must be burst-aligned.  
29.10.5.5 AAL1 RxBD  
Figure 29-47 shows the AAL1 RxBD.  
0
1
2
3
4
5
6
7
8
9
10  
11  
Ñ
12  
13  
14  
15  
Offset + 0x00  
Offset + 0x02  
Offset + 0x04  
Offset + 0x06  
E
Ñ
W
I
SNE  
Ñ
CM  
Data Length  
Rx Data Buffer Pointer  
Figure 29-47. AAL1 RxBD  
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Table 29-36 describes AAL1 RxBD Þelds.  
Table 29-36. AAL1 RxBD Field Descriptions  
Offset Bits  
Name  
E
Description  
0x00  
0
Empty  
0 The buffer associated with this RxBD is Þlled with received data or data reception was  
aborted due to an error. The core can read or write any Þelds of this RxBD. The CP  
cannot use this BD again while E = 0.  
1 The buffer is not full.This RxBD and its associated receive buffer are owned by the CP.  
Once E is set, the core should not write any Þelds of this RxBD.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (Þnal BD in table)  
0 This is not the last BD in the RxBD table of the current channel.  
1 This is the last BD in the RxBD table of this current channel. After this buffer is used,  
the CP receives incoming data into the Þrst BD in the table. The number of RxBDs in  
this table is programmable and is determined only by the W bit. The current table  
overall space is constrained to 64 Kbytes.  
3
4
I
Interrupt  
0 No interrupt is generated after this buffer has been used.  
1 An Rx buffer event is sent to the interrupt queue after the ATM controller uses this  
buffer. FCCE[GINTx] is set when the INT_CNT reaches the global interrupt threshold.  
SNE  
Sequence number error. SNE is set when a sequence number error is detected in the  
current AAL1 buffer.  
5
6
Ñ
Reserved, should be cleared.  
CM  
Continuous mode  
0 Normal operation.  
1 The empty bit (RxBD[E]) is not cleared by the CP after this BD is closed, allowing the  
associated buffer to be overwritten automatically when the CP next accesses this BD.  
7Ð15  
Ñ
Ñ
Reserved, should be cleared.  
0x02  
0x04  
DL  
Data length. The number of octets the CP writes into the buffer once its BD is closed.  
Ñ
RXDBPTR Rx data buffer pointer. Points to the Þrst location of the associated buffer; may reside in  
either internal or external memory. This pointer must be burst-aligned.  
29.10.5.6 AAL0 RxBD  
Figure 29-48 shows the AAL0 RxBD.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12 13 14 15  
Ñ
Offset + 0x00  
Offset + 0x02  
Offset + 0x04  
Offset + 0x06  
E
Ñ
W
I
Ñ
CM  
Ñ
CRE OAM  
Data Length (DL)/Channel Code (CC)  
Rx Data Buffer Pointer (RXDBPTR)  
Figure 29-48. AAL0 RxBD  
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Table 29-37 describes AAL0 RxBD Þelds.  
Table 29-37. AAL0 RxBD Field Descriptions  
Offset  
Bits  
Name  
E
Description  
0x00  
0
Empty  
0 The buffer associated with this RxBD is Þlled with received data, or data reception  
was aborted due to an error. The core can examine or write to any Þelds of this  
RxBD. The CP does not use this BD again while E remains zero.  
1 The Rx buffer is empty or reception is in progress. This RxBD and its associated  
receive buffer are owned by the CP. Once E is set, the core should not write any  
Þelds of this RxBD.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (Þnal BD in table)  
0 This is not the last BD in the RxBD table of the current channel.  
1 This is the last BD in the RxBD table of the current channel. After this buffer has  
been used, the CP will receive incoming data into the Þrst BD in the table. The  
number of RxBDs in this table is programmable and is determined only by the W bit.  
The current table cannot exceed 64 Kbytes.  
3
I
Interrupt  
0 No interrupt is generated after this buffer has been used.  
1 An Rx buffer event is sent to the interrupt queue after the ATM controller uses this  
buffer. FCCE[GINTx] is set when the INT_CNT reaches the global interrupt  
threshold.  
4Ð5  
6
Ñ
Reserved, should be cleared.  
CM  
Continuous mode  
0 Normal operation.  
1 The CP does not clear the E bit after this BD is closed, allowing the associated buffer  
to be overwritten automatically when the CP next accesses this BD.  
7Ð9  
10  
Ñ
Reserved, should be cleared.  
CRE  
Rx CRC error. Indicates a CRC10 error in the current AAL0 buffer. The CRE bit is  
considered an error only if the received cell had a CRC10 Þeld in the cell payload.  
11  
OAM  
Operation and maintenance cell. If OAM is set, the current AAL0 buffer contains an  
OAM cell. This cell is associated with the channel indicated by the channel code Þeld  
(CC Þeld).  
12-15  
Ñ
Ñ
Reserved, should be cleared.  
0x02  
0x04  
DL/CC  
Data length/channel code. If RxBD[OAM] is set, this Þeld functions as CC; otherwise, it  
is DL. Data length is the size in octets of this buffer (MRBLR value). Channel code  
speciÞes the channel code associated with this OAM cell.  
Ñ
RXDBPTR Rx data buffer pointer. Points to the Þrst location of the associated buffer; may reside in  
either internal or external memory. This pointer must be burst-aligned.  
29.10.5.7 AAL5, AAL1 User-DeÞned CellÑRxBD Extension  
In user-deÞned cell mode, the AAL5 and AAL1 RxBDs are extended to 32 bytes; see  
Figure 29-49. Note that for AAL0, a complete cell, including the UDC header, is stored in  
the buffer; the AAL0 BD size is always 8 bytes.  
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Offset + 0x08  
Extra Cell Header.  
Used to store the user-deÞned cellÕs extra cell header. The extra cell header can be 1Ð12 bytes long.  
Offset + 0x14  
Reserved (12 bytes)  
Figure 29-49. User-Defined CellÑRxBD Extension  
29.10.5.8 AAL5 TxBDs  
Figure 29-50 shows the AAL5 TxBD.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0x00  
Offset + 0x02  
Offset + 0x04  
Offset + 0x06  
R
Ñ
W
I
L
Ñ
CM  
Ñ
CLP CNG  
Ñ
Data Length (DL)  
Tx Data Buffer Pointer (TXDBPTR)  
Figure 29-50. AAL5 TxBD  
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Table 29-38 describes AAL5 TxBD Þelds.  
Table 29-38. AAL5 TxBD Field Descriptions  
Offset Bits  
Name  
R
Description  
0x00  
0
Ready  
0 The buffer associated with this BD is not ready for transmission. The user is free to  
manipulate this BD or its associated buffer. The CP clears R after the buffer is sent or  
after an error condition is encountered.  
1 The user-prepared buffer has not been sent or is currently being sent. No Þelds of this  
BD may be written by the user once R is set.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (Þnal BD in table)  
0 Not the last BD in the TxBD table.  
1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data from  
the Þrst BD in the table (the BD pointed to by the channelÕs TCT[TBD_BASE]). The  
number of TxBDs in this table is determined only by the W bit.The current table cannot  
exceed 64 Kbytes.  
3
4
I
Interrupt  
0 No interrupt is generated after this buffer has been serviced.  
1 A Tx Buffer event is sent to the interrupt queue after this buffer is serviced.  
FCCE[GINTx] is set when the INT_CNT counter reaches the global interrupt threshold.  
L
Last in frame. Set by the user to indicate the last buffer in a frame.  
0 Buffer is not last in a frame.  
1 Buffer is last in a frame.  
5
6
Ñ
Reserved, should be cleared.  
CM  
Continuous mode  
0 Normal operation.  
1 The CP does not clear R after this BD is closed, allowing the associated buffer to be  
retransmitted automatically when the CP next accesses this BD. However, the R bit is  
cleared if an error occurs during transmission, regardless of CM.  
7-9  
10  
Ñ
Reserved, should be cleared.  
CLP  
The ATM cell header CLP bit of the cells associated with the current frame are ORed  
with this Þeld. This Þeld is valid only in the Þrst BD of the frame.  
11  
CNG  
The ATM cell header CNG bit of the cells associated with the current frame are ORed  
with this Þeld. This Þeld is valid only in the Þrst BD of the frame.  
12Ð15  
Ñ
Ñ
Reserved, should be cleared.  
0x02  
0x04  
DL  
The number of octets the ATM controller should transmit from this BDÕs buffer. It is not  
modiÞed by the CP. The value of DL should be greater than zero.  
Ñ
TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer, which may or may  
not be 8-byte-aligned. The buffer may reside in either internal or external memory. This  
value is not modiÞed by the CP.  
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29.10.5.9 AAL1 TxBDs  
Figure 29-51 shows the AAL1 TxBD.  
0
1
2
3
4
5
6
7
8
9
10  
11  
Ñ
12  
13  
14  
15  
Offset + 0x00  
Offset + 0x02  
Offset + 0x04  
Offset + 0x06  
R
Ñ
W
I
Ñ
CM  
Data Length (DL)  
Tx Data Buffer Pointer (TXDBPTR)  
Figure 29-51. AAL1 TxBD  
Table 29-39 describes AAL1 TxBD Þelds.  
Table 29-39. AAL1 TxBD Field Descriptions  
Offset Bits  
Name  
R
Description  
0x00  
0
Ready  
0 The buffer associated with this BD is not ready for transmission. The user is free to  
manipulate this BD or its associated buffer.The CP clears this bit after the buffer has  
been sent or after an error condition is encountered.  
1 The buffer prepared for transmission by the user has not been sent or is being sent.  
No Þelds of this BD may be written by the user once R is set.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (Þnal BD in table)  
0 Not the last BD in the TxBD table.  
1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data from  
the Þrst BD in the table (the BD pointed to by the channelÕs TCT[TBD_BASE]). The  
number of TxBDs in this table is determined only by the W bit. The current table  
cannot exceed 64 Kbytes.  
3
I
Interrupt  
0 No interrupt is generated after this buffer has been serviced.  
1 A Tx buffer event is sent to the interrupt queue after this buffer is serviced.  
FCCE[GINTx] is set when the INT_CNT counter reaches the global interrupt  
threshold.  
4Ð5  
6
Ñ
Reserved, should be cleared.  
CM  
Continuous mode  
0 Normal operation.  
1 The CP does not clear the ready bit after this BD is closed, allowing the associated  
buffer to be retransmitted automatically when the CP next accesses this BD.  
7Ð11  
Ñ
Ñ
Reserved, should be cleared.  
0x02  
0x04  
DL  
The number of octets the ATM controller should transmit from this BDÕs buffer. It is not  
modiÞed by the CP. The value of DL should be greater than zero.  
Ñ
TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer. The buffer may  
reside in either internal or external memory. This value is not modiÞed by the CP.  
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29.10.5.10 AAL0 TxBDs  
Figure 29-52 shows AAL0 TxBDs. Note that the data length Þeld is calculated internally as  
52 bytes, plus the extra header length (deÞned in FPSMR[TEHS]) when in UDC mode.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0x00  
Offset + 0x02  
Offset + 0x04  
Offset + 0x06  
R
Ñ
W
I
Ñ
CM  
Ñ
OAM  
Ñ
Ñ
Tx Data Buffer Pointer (TXDBPTR)  
Figure 29-52. AAL0 TxBDs  
Table 29-40 describes AAL0 TxBD Þelds.  
Table 29-40. AAL0 TxBD Field Descriptions  
Offset  
Bits  
Name  
R
Description  
0x00  
0
Ready  
0 The buffer is not ready for transmission. The user can manipulate this BD or its  
buffer. The CP clears R after the buffer has been sent or after an error occurs.  
1 The buffer that the user prepared for transmission has not been sent or is being  
sent. No Þelds of this BD may be written by the user once R is set.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (Þnal BD in table)  
0 Not the last BD in the TxBD table.  
1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data  
from the Þrst BD in the table (the BD pointed to by the channelÕs  
TCT[TBD_BASE]). The number of TxBDs in this table is determined by the W bit.  
The current table is constrained to 64 Kbytes.  
3
I
Interrupt  
0 No interrupt is generated after this buffer has been serviced.  
1 A Tx buffer event is sent to the interrupt queue after this buffer is serviced.  
FCCE[GINTx] is set when the INT_CNT counter reaches the global interrupt  
threshold.  
4Ð5  
6
Ñ
Reserved, should be cleared.  
CM  
Continuous mode  
0 Normal operation.  
1 The CP does not clear the ready bit after this BD is closed, allowing the associated  
buffer to be retransmitted automatically when the CP next accesses this BD.  
7Ð10  
11  
Ñ
Reserved, should be cleared.  
OAM  
Operation and maintenance cell. If OAM is set, the current AAL0 buffer contains an  
F5 or F4 OAM cell. Performance monitoring calculations are not done on OAM cells.  
11Ð15  
Ñ
Ñ
Ñ
Reserved, should be cleared.  
Reserved, should be cleared.  
0x02  
0x04  
Ñ
TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer, which may or  
may not be 8-byte-aligned. The buffer may reside in either internal or external  
memory. This value is not modiÞed by the CP.  
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29.10.5.11 AAL5, AAL1 User-DeÞned CellÑTxBD Extension  
In user-deÞned cell mode, the AAL5 and AAL1 TxBDs are extended to 32 bytes; see  
Figure 29-53. Note that for AAL0 a complete cell, including the UDC header, is stored in  
the buffer; the AAL0 BD size is always 8 bytes.  
Offset + 0x08  
Offset + 0x14  
Extra Cell Header.  
Used to store the user-deÞned cellÕs extra cell header. The extra cell header can be 1Ð12 bytes long.  
Reserved (12 bytes)  
Figure 29-53. User-Defined CellÑTxBD Extension  
29.10.6 AAL1 Sequence Number (SN) Protection Table (AAL1 Only)  
The 32-byte sequence number protection table, pointed to by AAL1_SNPT_BASE in the  
ATM parameter RAM, resides in dual-port RAM and is used for AAL1 only. The table  
should be initialized according to Figure 29-54.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0x00  
Offset + 0x02  
Offset + 0x04  
Offset + 0x06  
Offset + 0x08  
Offset + 0x0A  
Offset + 0x0C  
Offset + 0x0E  
Offset + 0x10  
Offset + 0x12  
Offset + 0x14  
Offset + 0x16  
Offset + 0x18  
Offset + 0x1A  
Offset + 0x1C  
Offset + 0x1E  
0x0000  
0x0007  
0x000D  
0x000A  
0x000E  
0x0009  
0x0003  
0x0004  
0x000B  
0x000C  
0x0006  
0x0001  
0x0005  
0x0002  
0x0008  
0x000F  
Figure 29-54. AAL1 Sequence Number (SN) Protection Table  
29.10.7 UNI Statistics Table  
The UNI statistics table, shown in Table 29-41, resides in the dual-port RAM and holds  
UNI statistics parameters. UNI_STATT_BASE points to the base address of this table.  
Each PHY has its own table with a starting address given by UNI_STATT_BASE+ PHY#  
´ 8.  
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Table 29-41. UNI Statistics Table  
1
Offset  
Name  
Width  
Description  
0x00  
UTOPIAE  
Hword Counts cells dropped as a result of UTOPIA parity error or state machine  
errors (short or long cells).  
0x02  
0x04  
0x06  
MIC_COUNT  
Hword Counts misinserted cells dropped as a result of address look-up failure.  
CRC10E_COUNT Hword Counts cells dropped as a result of CRC10 failure. AAL5-ABR only.  
Hword Reserved, should be cleared.  
Ñ
1
Offset from UNI_STATT_BASE+PHY# ´ 8  
29.11 ATM Exceptions  
The ATM controller interrupt handling involves two principal data structures: FCCEs (FCC  
event registers) and circular interrupt queues.  
Four priority interrupt queues are available. By programming RCT[INTQ] and  
TCT[INTQ], the user determines which queue receives the interrupt. Channel Rx buffer, Rx  
frame, or Tx buffer events can be masked by clearing interrupt mask bits in RCT and TCT.  
After an interrupt request, the host reads FCCE. If FCCE[GINTx] = 1, at least one entry  
was added to one of the interrupt queues. After clearing FCCE[GINTx], the host processes  
the valid interrupt queue entries and clears each entryÕs valid bit. The host follows this  
procedure until it reaches an entry with V = 0. See Section 29.11.2, ÒInterrupt Queue  
Entry.Ó  
The host controls the number of interrupts sent to the core using a counter in the interrupt  
queueÕs parameter table; see Section 29.11.3. For each event sent to an interrupt queue, a  
counter (that has been initialized to a threshold number of interrupts) is decremented. When  
the counter reaches zero, the global interrupt, FCCE[GINTx], is set.  
29.11.1 Interrupt Queues  
Interrupt queues are located in external memory. The parameters of each queue are stored  
in a table. See Section 29.11.3, ÒInterrupt Queue Parameter Tables.Ó  
When an interrupt occurs, the CP writes a new entry to the interrupt queue, the V bit is set,  
and the queue pointer (INTQ_PTR) is incremented. Once the CP uses an entry with W = 1,  
it returns to the Þrst entry in the queue. If the CP tries to overwrite a valid entry (V = 1), an  
overßow condition occurs and the queueÕs overßow ßag, FCCE[INTOx], is set.  
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Word  
INTQ_BASE  
Software (Core) Pointer  
INTQ_PTR  
V = 0 W = 0  
V = 0 W = 0  
V = 0 W = 0  
V = 1 W = 0  
V = 1 W = 0  
V = 1 W = 0  
V = 0 W = 0  
V = 0 W = 0  
V = 0 W = 1  
Invalid  
Invalid  
Invalid  
Interrupt Entry  
Interrupt Entry  
Interrupt Entry  
Invalid  
Invalid  
Invalid  
Figure 29-55. Interrupt Queue Structure  
29.11.2 Interrupt Queue Entry  
Each one-word interrupt queue entry provides detailed interrupt information to the host.  
Figure 29-56 shows an entry.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0x00  
Offset + 0x02  
V
Ñ
W
Ñ
TBNR RXF BSY TXB RXB  
Channel Code (CC)  
Figure 29-56. Interrupt Queue Entry  
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Table 29-42 describes interrupt queue entry Þelds.  
Table 29-42. Interrupt Queue Entry Field Description  
Offset  
Bits  
Name  
V
Description  
0x00  
0
Valid interrupt entry  
0 This interrupt queue entry is free and can be use by the CP.  
1 This interrupt queue entry is valid. The host should read this interrupt and clear this bit.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap bit. When set, this is the last interrupt circular table entry. During initialization, the  
host must clear all W bits in the table except the last one, which must be set.  
3Ð10  
11  
Ñ
Reserved, should be cleared.  
TBNR Tx buffer-not-ready. Set when a transmit buffer-not-ready interrupt is issued. This interrupt  
is issued when the CP tries to open a TxBD that is not ready (R = 0). This interrupt is sent  
only if TCT[BNM] = 1. This interrupt has an associated channel code.  
Note that for AAL5, this interrupt is sent only if frame transmission is started. In this case,  
an abort frame transmission is sent (last cell with length=0), the channel is taken out of the  
APC, and the TCT[VCON] ßag is cleared.  
12  
RXF Rx frame. RXF is set when an Rx frame interrupt is issued. This interrupt is issued at the  
end of AAL5 PDU reception. This interrupt is issued only if RCT[RXFM] = 1. This interrupt  
has an associated channel code.  
13  
14  
15  
Ñ
BSY Busy condition. The BD table or the free buffer pool associated with this channel is busy.  
Cells were discarded due to this condition. This interrupt has an associated channel code.  
TXB Tx buffer. TXB is set when a transmit buffer interrupt is issued. This interrupt is enabled  
when both TxBD[I] and TCT[IMK] = 1. This interrupt has an associated channel code.  
RXB Rx buffer. RXB is set when an Rx buffer interrupt is issued. This interrupt is enabled when  
both RxBD[I] and RCT[RXBM] = 1. This interrupt has an associated channel code.  
0x02  
CC  
Channel code speciÞes the channel associated with this interrupt.  
29.11.3 Interrupt Queue Parameter Tables  
The interrupt queue parameters are held in parameter tables in the dual-port RAM; see  
Table 29-43. INTT_BASE in the parameter RAM points to the base address of these tables.  
Each of the four interrupt queues has its own parameter table with a starting address given  
by INTT_BASE+ RCT/TCT[INTQ] ´ 16.  
Table 29-43. Interrupt Queue Parameter Table  
1
Offset  
Name  
Width  
Description  
0x00  
0x04  
0x08  
INTQ_BASE Word  
Base address of the interrupt queue. User-deÞned.  
INTQ_PTR Word  
Pointer to interrupt queue entry. Initialize to INTQ_BASE.  
INT_CNT  
INT_ICNT  
Half Word Interrupt counter. Initialize with INT_ICNT. The CP decrements INT_CNT for  
each interrupt. When INT_CNT reaches zero, the queueÕs global interrupt ßag  
FCCE[GINTx] is set.  
0x0A  
Half Word Interrupt initial count. User-deÞned global interrupt thresholdÑthe number of  
interrupts required before the CP issues a global interrupt (FCCE[GINTx]).  
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Table 29-43. Interrupt Queue Parameter Table (Continued)  
1
Offset  
Name  
Width  
Description  
0x0C  
INTQ_ENTRY Word  
Interrupt queue entry. Must be zero. Note that when an overrun occurs, this  
entry must be cleared again.  
1
Offset from INTT_BASE+RCT/TCT[INTQ] ´ 16  
29.12 The UTOPIA Interface  
The ATM controller interfaces with a PHY device through the UTOPIA interface. The  
MPC8260 supports UTOPIA level 2 for both master and slave modes.  
29.12.1 UTOPIA Interface Master Mode  
UTOPIA master signals are shown in Figure 29-57.  
TXDATA[0Ð15]/[0Ð7]  
TxSOC  
RXDATA[0Ð15]/[0Ð7]  
RXSOC  
TXENB  
RXENB  
MPC8260  
TXPRTY  
MPC8260  
RXPRTY  
TXCLK  
RXCLK  
TXCLAV[0Ð3]  
TXADD[0Ð4]  
RXCLAV[0Ð3]  
RXADD[0Ð4]  
Figure 29-57. UTOPIA Master Mode Signals  
Table 29-44 describes UTOPIA master mode signals.  
Table 29-44. UTOPIA Master Mode Signal Descriptions  
Signal  
Description  
TxDATA[0Ð15]/ Carries transmit data from the ATM controller to a PHY device.TxDATA[15]/[7] is the msb when using  
UTOPIA 16/8, TxDATA[0] is the lsb.  
[0Ð7]  
TxSOC  
Transmit start of cell. Asserted by the ATM controller when the Þrst byte of a cell is sent on TxDATA  
lines.  
TxENB  
Transmit enable. Asserted by the ATM controller when valid data is placed on the TxDATA lines.  
TxCLAV[0Ð3] Transmit cell available. Asserted by the PHY device to indicate that the PHY has room for a complete  
cell.  
TxPRTY  
TxCLK  
Transmit parity. Asserted by the ATM controller. It is an odd parity bit over the TxDATA bits.  
Transmit clock. Provides the synchronization reference for the TxDATA, TxSOC, TxENB, TxCLAV,  
TxPRTY signals. All the above signals are sampled at low-to-high transitions of TxCLK.  
TxADD[0Ð4]  
Transmit address. Address bus from the ATM controller to the PHY device used to select the  
appropriate M-PHY device. Each M-PHY device needs to maintain its address. TxADD[4] is the msb.  
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Table 29-44. UTOPIA Master Mode Signal Descriptions (Continued)  
Signal  
Description  
RxDATA[0Ð15] Carries receive data from the PHY to the ATM controller. RxDATA[15]/[7] is the msb when using  
/[0Ð7]  
UTOPIA 16/8, RxDATA[0] is the lsb.  
RxSOC  
RxENB  
Receive start of cell. Asserted by the PHY device as the Þrst byte of a cell is received on RxDATA.  
Receive enable. An ATM controller asserts to indicate that RxDATA and RxSOC will be sampled at  
the end of the next RxCLK cycle. For multiple PHYs, RxENB is used to three-state RxDATA and  
RxSOC at each PHYÕs output. RxDATA and RxSOC should be enabled only in cycles after those with  
RxENB asserted.  
RxCLAV[0Ð3] Receive cell available. Asserted by a PHY device when it has a complete cell to give the ATM  
controller.  
RxPRTY  
Receive parity. Asserted by the PHY device. It is an odd parity bit over the RxDATA. If there is a  
RxPRTY error and the receive parity check FPSMR[RxP] is enabled, the cell is discarded. See  
Section 29.13.2, ÒFCC Protocol-SpeciÞc Mode Register (FPSMR).Ó  
RxCLK  
Receiver clock. Synchronization reference for RxDATA, RxSOC, RxENB, RxCLAV, and RxPRTY, all of  
which are sampled at low-to-high transitions of RxCLK.  
RxADD[0Ð4]  
Receive address. Address bus from the ATM controller to the PHY device used to select the  
appropriate M-PHY device. Each M-PHY device needs to maintain its address. RxADD[4] is the msb.  
29.12.1.1 UTOPIA Master Multiple PHY Operation  
The cell transfer in a multiple PHY ATM port uses cell-level handshaking as deÞned in the  
UTOPIA standards. The MPC8260 supports two polling modes:  
¥
¥
Direct polling uses CLAV[0Ð3] with PHY selection using ADD[0Ð2]. Up to four  
PHYs can be supported.  
Multiplex polling uses CLAV[0] and ADD[0Ð4]. ATM controller polls all active  
PHYs starting from PHY address 0x0 to the address written in  
FPSMR[LAST_PHY]. Up to 31 PHY devices are supported.  
Both modes support round-robin priority or Þxed priority, described in Section 29.13.2,  
ÒFCC Protocol-SpeciÞc Mode Register (FPSMR).Ó  
29.12.2 UTOPIA Interface Slave Mode  
UTOPIA slave signals are shown in Figure 29-58  
TXDATA[0Ð15]/[0Ð7]  
TXSOC  
RXDATA[0Ð15]/[0Ð7]  
RXSOC  
TXENB  
RXENB  
MPC8260  
TXPRTY  
TXCLK  
MPC8260  
RXPRTY  
RXCLK  
TXCLAV  
TXADD[0Ð4]  
RXCLAV  
RXADD[0Ð4]  
Figure 29-58. UTOPIA Slave Mode Signals  
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Table 29-45 describes UTOPIA slave mode signals.  
Table 29-45. UTOPIA Slave Mode Signals  
Signal  
Description  
TxDATA[0Ð15] Transmit data bus. Carries transmit data from the ATM controller to the master device. TxDATA[15]/  
/[0Ð7]  
[7] is the msb, TxDATA[0] is the lsb.  
TxSOC  
Transmit start of cell. Asserted by an ATM controller as the Þrst byte of a cell is sent on the TxDATA  
lines.  
TxENB  
Transmit enable. An input to the ATM controller. It is asserted by the UTOPIA master to signal the  
slave to send data in the next TxCLK cycle.  
TxCLAV  
TxPRTY  
TxCLK  
Transmit cell available. Asserted by the ATM controller to indicate it has a complete cell to transmit.  
Transmit parity. Asserted by the ATM controller. It is an odd parity bit over the TxDATA.  
Transmit clock. Provides the synchronization reference for the TxDATA, TxSOC, TxENB, TxCLAV,  
and TxPRTY signals. All of the above signals are sampled at low-to-high transitions of TxCLK.  
TxADD[0Ð4]  
Transmit address. Address bus from the master to the ATM controller used to select the appropriate  
M-PHY device.  
RxDATA[0Ð  
15]/[0Ð7]  
Receive data bus. Carries receive data from the master to the ATM controller. RxDATA[15]/[7] is the  
msb, RxDATA[0] is the lsb.  
RxSOC  
Receive start of cell. Asserted by the master device whenever the Þrst byte of a cell is being received  
on the RxDATA lines.  
RxENB  
Receive enable. Asserted by the master device to signal the slave to sample the RxDATA and  
RxSOC signals.  
RxCLAV  
RxPRTY  
Receive cell available. Asserted by the ATM controller to indicate it can receive a complete cell.  
Receive parity. Asserted by the PHY device. It is an odd parity bit over the RxDATA[0Ð15]. If there is  
a RxPRTY error and the receive parity check FPSMR[RxP] is enabled, the cell is discarded. See see  
Section 29.13.2, ÒFCC Protocol-SpeciÞc Mode Register (FPSMR).Ó  
RxCLK  
Receive clock. Provides the synchronization reference for the RxDATA, RxSOC, RxENB, RxCLAV,  
and RxPRTY signals. All the above signals are sampled at low-to-high transitions of RxCLK.  
RxADD[0Ð4]  
Receive address. Address bus from master to the ATM controller device used to select the  
appropriate M-PHY device.  
29.12.2.1 UTOPIA Slave Multiple PHY Operation  
In multiple PHY UTOPIA slave mode, cells are transferred using cell-level handshake as  
deÞned by the UTOPIA level-2 standard. The user should write the ATM controller PHY  
address in FPSMR[PHY ID].  
29.12.2.2 UTOPIA Clocking Modes  
The UTOPIA clock is generated by one of the MPC8260Õs baud-rate generators. The user  
should assign one of the baud rate generators to supply the UTOPIA clock. See Chapter 15,  
ÒCPM Multiplexing.Ó  
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29.12.2.3 UTOPIA Loop-Back Modes  
The UTOPIA interface supports loop-back mode. In this mode, the Rx and Tx UTOPIA  
signals are shorted internally. Output pins are driven; input pins are ignored.  
Note that in loop-back mode, the transmitter and receiver must operate in complementary  
modes. For example, if the transmitter is master, the receiver must be a slave  
(FPSMR[TUMS] = 0, FPSMR[RUMS] = 1).  
Modes are selected through GFMR[DIAG], as shown in Table 29-46.  
Table 29-46. UTOPIA Loop-Back Modes  
DIAG  
Description  
00  
01  
1x  
Normal mode  
Loop-back. UTOPIA Rx and Tx signals are shorted internally. Output pins are driven, input pins are ignored.  
Reserved  
29.13 ATM Registers  
The following sections describe the conÞguration of the registers in ATM mode.  
29.13.1 General FCC Mode Register (GFMR)  
The GFMR mode Þeld should be programmed for ATM mode. To enable transmit and  
receive functions, ENT and ENR must be set as the last step in the initialization process.  
Full GFMR details are given in Section 28.2, ÒGeneral FCC Mode Registers (GFMRx).Ó  
29.13.2 FCC Protocol-SpeciÞc Mode Register (FPSMR)  
The FCC protocol-speciÞc mode register (FPSMR), shown in Figure 29-59, controls  
various protocol-speciÞc FCC functions. The user should initialize the FPSMR. Erratic  
behavior may result if there is an attempt to write to the FPSMR while the transmitter and  
receiver are enabled.  
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Bits  
Field  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14 15  
TEHS  
REHS  
ICD TUMS RUMS  
LAST PHY/PHY ID  
Reset  
R/W  
0000_0000_0000_0000  
R/W  
Address  
Bits  
0x11304 (FPSMR1), 0x11324 (FPSMR1), 0x11324 (FPSMR1)  
16 17 18  
Ñ
19  
20  
21  
22  
23  
Ñ
24  
25  
26  
27  
28  
29  
30 31  
Ñ
Field  
TUDC RUDC RXP TUMP  
TSIZE RSIZE UPRM UPLM RUMP HECI  
Reset  
R/W  
0000_0000_0000_0000  
R/W  
Address  
0x11306 (FPSMR1), 0x11326 (FPSMR2), 0x11326 (FPSMR3)  
Figure 29-59. FCC ATM Mode Register (FPSMR)  
Table 29-47 describes FPSMR Þelds.  
Table 29-47. FCC ATM Mode Register (FPSMR)  
Bits  
0Ð3  
Name  
Description  
TEHS  
Transmit extra header size. Used only in user-deÞned cell mode to hold the Tx user-deÞned  
cellsÕ extra header size. Values between 0-11 are valid. TEHS = 0 generates 1 byte of extra  
header; TEHS = 11 generates 12 bytes of extra header.  
4Ð7  
8
REHS  
ICD  
Receive extra header size. Used only in user-deÞned cell mode to hold the Rx user-deÞned  
cellsÕ extra header size. Values between 0Ð11 are valid. For REHS = 0, the receiver expects 1  
byte of extra header; for REHS = 11, it expects 12 bytes of extra header.  
Idle cells discard  
0 Discard idle cells (GFC, VPI, VCI, PTI =0).  
1 Do not discard idle cells.  
9
TUMS  
RUMS  
Transmit UTOPIA master/slave mode  
0 Transmit UTOPIA master mode is selected.  
1 Transmit UTOPIA slave mode is selected.  
10  
Receive UTOPIA master/slave mode  
0 Receive UTOPIA master mode is selected.  
1 Receive UTOPIA slave mode is selected.  
11Ð15 LAST PHY/ Last PHY. (Multiple PHY master mode only.) The UTOPIA interface polls all PHYs starting  
PHY ID  
from PHY address 0 and ending with the PHY address speciÞed in LAST PHY. (The number of  
active PHYs are LAST PHY+1). LAST PHY should be speciÞed in both multiplex and direct-  
polling modes.  
PHY ID. (Multiple PHY slave mode only.) Determines the PHY address of the ATM controller  
when conÞgured as a slave in a multiple PHY ATM port.  
16Ð18  
19  
Ñ
Reserved, should be cleared.  
TUDC  
Transmit user-deÞned cells  
0 Regular 53-byte cells.  
1 User-deÞned cells.  
20  
RUDC  
Receive user-deÞned cells  
0 Regular 53-byte cells.  
1 User-deÞned cells.  
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Table 29-47. FCC ATM Mode Register (FPSMR) (Continued)  
Bits  
21  
Name  
Description  
RxP  
Receive parity check.  
0 Check Rx parity line.  
1 Do not check Rx parity line.  
22  
TUMP  
Transmit UTOPIA multiple PHY mode  
0 Transmit UTOPIA single PHY mode is selected.  
1 Transmit UTOPIA multiple PHY mode is selected.  
23  
24  
Ñ
Reserved, should be cleared.  
TSIZE  
Transmit UTOPIA data bus size  
0 UTOPIA 8-bit data bus size.  
1 UTOPIA 16-bit data bus size.  
25  
26  
RSIZE  
UPRM  
Receive UTOPIA data bus size  
0 UTOPIA 8-bit data bus size.  
1 UTOPIA 16-bit data bus size.  
UTOPIA priority mode.  
0 Round robin. Polling is done from PHY zero to the PHY speciÞed in LAST PHY. When a  
PHY is selected, the UTOPIA interface continues to poll the next PHY in order.  
1 Fixed priority. Polling is done from PHY zero to the PHY speciÞed in LAST PHY. When a  
PHY is selected, the UTOPIA interface continues to poll from PHY zero.  
27  
UPLM  
UTOPIA polling mode.  
0 Multiplex polling. Polling is done using RxAdd[0Ð4] and Clav[0]. Selection is done using  
RxAdd[0Ð4]. Up to 31 PHYs can be polled.  
1 Direct polling. Polling is done using Clav[0Ð3]. Selection is done using RxAdd[0Ð2]. Up to 4  
PHYs can be polled.  
28  
RUMP  
HECI  
Ñ
Receive UTOPIA multiple PHY mode.  
0 Receive UTOPIA single PHY mode is selected.  
1 Receive UTOPIA multiple PHY mode is selected.  
29  
HEC included. Used in UDC mode only.  
0 HEC octet is not included when UDC mode is enabled.  
1 HEC octet is included when UDC mode is enabled.  
30Ð31  
Reserved, should be cleared.  
29.13.3 ATM Event Register (FCCE)/Mask Register (FCCM)  
The FCCE register is the ATM controller event register when the FCC operates in ATM  
mode. When it recognizes an event, the ATM controller sets the corresponding FCCE bit.  
Interrupts generated by this register can be masked in FCCM. FCCE is memory-mapped  
and can be read at any time. Bits are cleared by writing ones to them; writing zeros has no  
effect. Unmasked bits must be cleared before the CP clears the internal interrupt request.  
FCCM is the ATM controller mask register. It is a 16-bit read/write register with the same  
bit format as FCCE. If an FCCM bit is set, the corresponding interrupt is enabled in FCCE.  
If it is cleared, the corresponding interrupt is masked. FCCM is cleared at reset.  
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Part IV. Communications Processor Module  
Bits  
Field  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Ñ
TIRU GRLI GBPB GINT3 GINT2 GINT1 GINT0 INTO3 INTO2 INTO1 INTO0  
Reset  
R/W  
0000_0000_0000_0000  
R/W  
Address  
0x11310 (FCCE1), 0x11330 (FCCE2), 0x11350 (FCCE3)/  
0x11314 (FCCM1), 0x11334 (FCCM2), 0x11354 (FCCM3)  
Figure 29-60. ATM Event Register (FCCE)/FCC Mask Register (FCCM)  
Table 29-48 describes FCCE Þelds.  
Table 29-48. FCCE/FCCM Field Descriptions  
Bits Name  
0Ð4  
Description  
Ñ
Reserved, should be cleared.  
5
TIRU Transmit internal rate underrun. A transmit internal rate counter expired and a cell was not sent  
because the transmit FIFO was empty.TIRU may be set only when using transmit internal rate mode;  
see Section 29.13.4, ÒFCC Transmit Internal Rate Registers (FTIRRx).Ó  
6
7
GRLI Global red-line interrupt. GRLI is set when a free buffer poolÕs RLI ßag is set. The RLI ßag is also set  
in the free buffer poolÕs parameter table.  
GBPB Global buffer pool busy interrupt. GBPB is set when a free buffer poolÕs BUSY ßag is set. The BUSY  
ßag is also set in the free buffer poolÕs parameter table.  
8Ð11 GINTx Global interrupt. Set when an event is sent to the corresponding interrupt queue. See Section 29.11,  
ÒATM Exceptions.Ó  
12Ð  
15  
INTOx Interrupt queue overßow. Set when an overßow condition occurs in the corresponding interrupt  
queue. This occurs when the CP attempts to overwrite a valid interrupt entry. See Section 29.11.1,  
ÒInterrupt Queues.Ó  
29.13.4 FCC Transmit Internal Rate Registers (FTIRRx)  
The Þrst four PHY devices (address 00-03) have their own FCC transmit internal rate  
registers (FTIRRx_PHY0ÐFTIRRx_PHY3) for use in transmit internal rate mode. In this  
mode, the total transmission rate is determined by FCC internal rate timers. FTIRRx, shown  
in Figure 29-61, includes the initial value of the internal rate timer. The source clock of the  
internal rate timers is supplied by one of four baud-rate generators selected in CMXUAR;  
see Section 15.4.1, ÒCMX UTOPIA Address Register (CMXUAR).Ó Note that in slave  
mode, FTIRRx_PHY0 is used regardless of the slave PHY address.  
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Part IV. Communications Processor Module  
Bits  
Field  
0
1
2
3
4
5
6
7
TRM  
Initial Value  
Reset  
R/W  
0000_0000  
R/W  
Address  
FCC1: 0x1131F (FTIRR1_PHY0), 0x1131D (FTIRR1_PHY1),  
0x1131E (FTIRR1_PHY2), 0x1131F (FTIRR1_PHY3)  
FCC2: 0x1133F (FTIRR2_PHY0), 0x1133D (FTIRR2_PHY1),  
0x1133E (FTIRR2_PHY2), 0x1133F (FTIRR2_PHY3)  
Figure 29-61. FCC Transmit Internal Rate Registers (FTIRRx)  
Table 29-49 describes FTIRRx Þelds.  
Table 29-49. FTIRRx Field Descriptions  
Bits  
Name  
Description  
0
TRM Transmit mode.  
0 External rate mode.  
1 Internal rate mode.  
1Ð7  
Initial The initial value of the internal rate timer. A value of 0x7F produces the minimum clock rate (BRG  
Value CLK divided by 128); 0x00 produces the maximum clock rate (BRG CLK divided by 1).  
Figure 29-62 shows how transmit clocks are determined.  
.
PHY# 0 Tx Rate  
PHY# 1 Tx Rate  
PHY# 2 Tx Rate  
PHY# 3 Tx Rate  
PHY#0 Internal Rate Timer  
PHY#1 Internal Rate Timer  
BRG CLK  
PHY#2 Internal Rate Timer  
PHY#3 Internal Rate Timer  
Figure 29-62. FCC Transmit Internal Rate Clocking  
Example:  
Suppose the MPC8260 is connected to four 155 Mbps PHY devices and the maximum  
transmission rate is 155 Mbps for the Þrst PHY and 10 Mbps for the rest of the PHYs. The  
BRG CLK should be set according to the highest rate. If the system clock is 133 MHz, the  
BRG should be programmed to divide the system clock by 362 to generate cell transmit  
requests every 362 system clocks:  
(133MHz ´ (53 ´ 8))  
----------------------------------------------------- = 3 6 2  
155.52Mbps  
For the 155 Mbps PHY, the FTIRR divider should be programmed to zero (the BRG CLK  
is divided by one); for the rest of the 10 Mbps PHYs, the FTIRR divider should be  
programmed to 14 (the BRG CLK is divided by 15).  
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Chapter 29. ATM Controller  
29-89  
     
Part IV. Communications Processor Module  
See also Section 29.16.1, ÒUsing Transmit Internal Rate Mode.Ó  
29.14 ATM Transmit Command  
The CPM command set includes an ATM TRANSMIT that can be sent to the CP command  
register (CPCR), described in Section 13.4.1.  
The ATM TRANSMIT command (CPCR[opcode] = 0b1010, CPCR[SBC[code]] = 0b01110,  
CPCR[SBC[page]] = 0b00100 or 0b00101 (FCC1 or FCC2), CPCR[MCN] =  
0b0000_1010) turns a passive channel into an active channel by inserting it into the APC  
scheduling table. Note that an ATM TRANSMIT command should be issued only after the  
channelÕs TCT is completely initialized and the channel has BDs ready to transmit. Note  
also that CPCR[SBC[code]] = 0b01110 and not FCC1 or FCC2 code.  
Before issuing the command, the user should initialize COMM_INFO Þelds in the  
parameter RAM as described in Figure 29-63.  
Offset  
0x86  
0x88  
0x8A  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Ñ
CTB  
PHY#  
ACT  
PRI  
Channel Code (CC)  
BT  
Figure 29-63. COMM_INFO Field  
Table 29-50 describes COMM_INFO Þelds  
Table 29-50. COMM_INFO Field Descriptions  
Offset Bits  
Name  
Description  
0x86  
0Ð4  
5
Ñ
Reserved, should be cleared.  
CTB Connection tables bus. Used for external channels only  
0 External connection tables reside on the 60x bus.  
1 External connection tables reside on the local bus.  
6Ð10  
PHY# PHY number. In single PHY mode this Þeld should be cleared In multiple PHY mode this  
Þeld is an index to the APC parameter table associated with this channel.  
11Ð12  
ACT ATM channel type  
00 Other channel  
01 VBR channel  
1x Reserved  
13-15  
PRI  
APC priority level.  
000Ñhighest priority (APC_LEVEL1), 111Ñlowest priority (APC_LEVEL8).  
0x88  
0x8A  
0-15  
0-15  
CC  
BT  
Channel code. The channel code associated with the current channel.  
Burst tolerance. For use by VBR channels only (ACT Þeld is 0b01). SpeciÞes the initial burst  
tolerance (GCRA burst credit) of the current VC.  
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29.15 SRTS Generation and Clock Recovery Using  
External Logic  
The MPC8260 supports SRTS generation using external logic. If SRTS generation is  
enabled (TCT[SRT] = 1), the MPC8260 reads SRTS[0Ð3] from the external SRTS logic and  
inserts it into 4 cells whose SN Þelds equal 1, 3, 5, and 7, as shown in Figure 29-64.  
External SRTS Logic  
(N=3008 bits = 8 SAR PDU)  
SRTS  
fs  
Counter  
divided by N  
Latch  
2.43 MHz (E1/T1)  
1/64  
155.52 MHz  
p = 4 bit counter  
DMA reads new SRTS code  
SN=1 SN=3 SN=5 SN=7  
Figure 29-64. AAL1 SRTS Generation Using External Logic  
For every eight cells, the external SRTS logic should supply a valid SRTS code. The CP  
reads the SRTS code from the bus selected in TCT[BIB] using a DMA read cycle of 1-byte  
data size. Each AAL1 channel can be programmed to select one of 16 addresses available  
for reading the SRTS result. The SRTS code should be placed on the least-signiÞcant nibble  
of that address (SRTS[0]=lsb, SRTS[3]=msb). The SRTS is synchronized with the  
sequence count cycleÑSRTS[0] is inserted into the cell with SN = 7; SRTS[3] is inserted  
into the cell with SN = 1. For every eighth AAL1 SAR PDU, the SRTS logic samples a new  
SRTS and stores it internally. The SRTS is a sample of a 4-bit counter with a 2.43-MHz  
reference clock (for E1/T1) synchronized with the network clock.  
The MPC8260 supports clock recovery using an external SRTS PLL. If SRTS recovery is  
enabled (RCT[SRT]=1), the MPC8260 tracks the SRTS from four incoming cells whose  
SN Þeld equals 1, 3, 5, and 7 and writes the result to external SRTS logic, as shown in  
Figure 29-65.  
MOTOROLA  
Chapter 29. ATM Controller  
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Part IV. Communications Processor Module  
External SRTS Logic  
(N=3008 bits = 8 SAR PDU)  
SRTS  
fs  
Counter  
Latch  
divided by N  
2.43 MHz (E1/T1)  
155.52 MHz  
p = 4 bit  
counter  
1/64  
+
-
VCO  
SRTS Diff  
Latch  
DMA writes new SRTS code  
SN=1 SN=3 SN=5 SN=7  
Figure 29-65. AAL1 SRTS Clock Recovery Using External Logic  
On every eighth cell, the MPC8260 writes a new SRTS code to the external logic using the  
bus selected in RCT[BIB]. The CP writes the SRTS code using a DMA write cycle of 1-  
byte data size. Each AAL1 channel can be programmed to select one of 16 addresses  
available for writing the SRTS result. The SRTS code is written to the least-signiÞcant  
nibble of that address (SRTS[0]=lsb, SRTS[3]=msb). The SRTS is synchronized with the  
sequence count cycleÑSRTS[3] is read from the cell with SN = 1 and SRTS[0] is read from  
the cell with SN = 7. The SRTS PLL makes periodic clock adjustments based on the  
difference between a locally generated SRTS and a remotely generated SRTS retrieved  
every eight received cells.  
29.16 ConÞguring the ATM Controller for Maximum  
CPM Performance  
The following sections recommend ATM controller conÞgurations to maximize CPM  
performance.  
29.16.1 Using Transmit Internal Rate Mode  
When the total transmit rate is less than the PHY rate, use the transmit internal rate mode  
and conÞgure the internal rate clock to the maximum bit rate required. (See 29.2.1.4,  
ÒTransmit External Rate and Internal Rate Modes.Ó) The PHY then automatically Þlls the  
unused bandwidth with idle cells, not the ATM controller. If the internal rate mode is not  
used, CPM performance is consumed generating the idle cell payload and using the  
scheduling algorithm to Þll the unused bandwidth at the higher PHY rate.  
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For example, suppose a system uses a 155.52-Mbps OC-3 device as PHY0, but the  
maximum required data rate is only 100 Mbps. In transmit internal rate mode, the user can  
conÞgure the internal rate mechanism to clock the ATM transmitter at a cell rate of 100  
Mbps. If the system clock is 133 MHz, program a BRG to divide the system clock by 563  
to generate a transmit cell request every 563 CPM clocks:  
(133MHz ´ (53 ´ 8))  
----------------------------------------------------- = 5 6 3  
100Mbps  
Set FTIRRx_PHY0[TRM] to enable the transmit internal rate mode and clear  
FTIRRx_PHY0[Initial Value] since there is no need to further divide the BRG. See  
Section 29.13.4, ÒFCC Transmit Internal Rate Registers (FTIRRx).Ó  
In external rate mode, however, the transmit cell request frequency is determined by the  
PHYÕs maximum rate, not by internal FCC counters. If an OC-3 PHY is used with the ATM  
controller in external rate mode, the requests must be generated every 362 CPM clocks  
(assuming a 133-MHz CPM clock). If only 100 Mbps is used for real data, 36% of the  
transmit cell requests consume CPM processing time sending idle cells.  
29.16.2 APC ConÞguration  
Maximizing the number of cells per slot (CPS) and minimizing the priority levels deÞned  
in the APC data structure improves CPM performance:  
¥
Cells per slot. CPS deÞnes the maximum number of ATM cells allowed to be sent  
during a time slot. (See Section 29.3.3.1, ÒDetermining the Cells Per Slot (CPS) in  
a Scheduling Table.Ó) The scheduling algorithm is more efÞcient sending multiple  
cells per time slot using the linked-channel Þeld. Therefore, choose the maximum  
number of cells per slot allowed by the application.  
¥
Priority levels. The user can conÞgure the APC data structure to have from one to  
eight priority levels. (See Section 29.3.6, ÒDetermining the Priority of an ATM  
Channel.Ó) For each time slot, the scheduling algorithm scans all priority levels and  
maintains pointers for each level. Therefore, enable only the minimum number of  
priority levels required.  
29.16.3 Buffer ConÞguration  
Using statically allocated buffers of optimal sizes also improves CPM performance:  
¥
Buffer size. Opening and closing buffer descriptors consumes CPM processing time.  
Because smaller buffers require more opening and closing of BDs, the optimal  
buffer size for maximum CPM performance is equal to the packet size (an AAL5  
frame, for example).  
¥
Free buffer pool. When the free buffer pool is used, the CPM dynamically allocates  
buffers and links them to a channelÕs BD. In static buffer allocation, the core assigns  
a Þxed data buffer to each BD. (See Section 29.10.5.2, ÒReceive Buffers  
Operation.Ó) When allowed by the application, use static buffer allocation to  
increase CPM performance.  
MOTOROLA  
Chapter 29. ATM Controller  
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Chapter 30  
Fast Ethernet Controller  
300  
3T00 he Ethernet IEEE 802.3 protocol is a widely-used LAN based on the carrier-sense  
multiple access/collision detect (CSMA/CD) approach. Because Ethernet and IEEE 802.3  
protocols are similar and can coexist on the same LAN, both are referred to as Ethernet in  
this manual, unless otherwise noted. Ethernet/IEEE 802.3 frames are based on the frame  
structure shown in Figure 30-1.  
Frame Length is 64Ð1,518 Bytes  
Start Frame Destination  
Source  
Address  
Type/  
Length  
Frame Check  
Sequence  
Preamble  
7 Bytes  
Data  
Delimiter  
Address  
1 Byte  
6 Bytes  
6 Bytes  
2 Bytes  
46Ð1500 Bytes  
4 Bytes  
Note: The lsb of each octet is transmitted first.  
Figure 30-1. Ethernet Frame Structure  
The elements of an Ethernet frame are as follows:  
¥
¥
¥
¥
7-byte preamble of alternating ones and zeros.  
Start frame delimiter (SFD)ÑSigniÞes the beginning of the frame.  
48-bit destination address.  
48-bit source address. Original versions of the IEEE 802.3 speciÞcation allowed 16-  
bit addressing, which has never been used widely.  
¥
Ethernet type Þeld/IEEE 802.3 length Þeld. The type Þeld signiÞes the protocol used  
in the rest of the frame, such as TCP/IP; the length Þeld speciÞes the length of the  
data portion of the frame. For Ethernet and IEEE 802.3 frames to exist on the same  
LAN, the length Þeld must be unique from any type Þelds used in Ethernet. This  
requirement limits the length of the data portion of the frame to 1,500 bytes and,  
therefore, the total frame length to 1,518 bytes.  
¥
¥
Data  
Four-bytes frame-check sequence (FCS), which is the standard, 32-bit CCITT-CRC  
polynomial used in many protocols.  
When a station needs to transmit, it waits until the LAN becomes silent for a speciÞed  
period (interframe gap). When a station starts sending, it continually checks for collisions  
MOTOROLA  
Chapter 30. Fast Ethernet Controller  
30-1  
     
Part IV. Communications Processor Module  
on the LAN. If a collision is detected, the station forces a jam signal (all ones) on its frame  
and stops transmitting. Collisions usually occur close to the beginning of a frame. The  
station then waits a random time period (backoff) before attempting to send again. When  
the backoff completes, the station waits for silence on the LAN and then begins  
retransmission on the LAN. This process is called a retry. If the frame is not successfully  
sent within 15 retries, an error is indicated.  
10-Mbps Ethernet basic timing speciÞcations follow:  
¥
¥
¥
¥
Transmits at 0.8 µs per byte  
The preamble plus start frame delimiter is sent in 6.4 µs.  
The minimum interframe gap is 9.6 µs.  
The slot time is 51.2 µs.  
100-Mbps Ethernet basic timing speciÞcations follow:  
¥
¥
¥
¥
Transmits at 0.08 µs per byte  
The preamble plus start frame delimiter is sent in 0.64 µs.  
The minimum interframe gap is 0.96 µs.  
The slot time is 5.12 µs.  
30.1 Fast Ethernet on the MPC8260  
When a general FCC mode register (GFMRx[MODE]) selects Ethernet protocol, that FCC  
performs the full set of IEEE 802.3/Ethernet CSMA/CD media access control (MAC) and  
channel interface functions. Figure 30-2 shows a block diagram of the FCC Ethernet  
control logic.  
30-2  
MPC8260 PowerQUICC II UserÕs Manual  
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Part IV. Communications Processor Module  
60x-Bus  
Slot Time  
And Defer  
Counter  
Control  
Registers  
RX_CLK  
TX_CLK  
Clock  
Generator  
Peripheral Bus  
Internal Clocks  
RX_ER  
RX_DV  
COL  
TX_ER  
Receive  
Data  
FIFO  
Transmit  
Data  
FIFO  
Receiver  
Control  
UNIT  
Transmitter  
Control  
Unit  
TX_EN  
COL  
CRS  
CRS  
TXD[3Ð0]  
RXD[3Ð0]  
Shifter  
Shifter  
Figure 30-2. Ethernet Block Diagram  
30.2 Features  
The following is a list of Fast Ethernet key features:  
¥
¥
Support for Fast Ethernet through the MII (media-independent interface)  
Performs MAC (media access control) layer functions of Fast Ethernet and IEEE  
802.3x  
¥
¥
Performs framing functions  
Ñ Preamble generation and stripping  
Ñ Destination address checking  
Ñ CRC generation and checking  
Ñ Automatic padding of short frames on transmit  
Ñ Framing error (dribbling bits) handling  
Full collision support  
Ñ Enforces the collision (jamming and TX_ER assertion)  
Ñ Truncated binary exponential backoff algorithm for random wait  
Ñ Two nonaggressive backoff modes  
Ñ Automatic frame retransmission (until retry limit is reached)  
Ñ Automatic discard of incoming collided frames  
Ñ Delay transmission of new frames for speciÞed interframe gap  
Bit rates up to 100 Mbps  
¥
¥
¥
Receives back-to-back frames  
Detection of receive frames that are too long  
MOTOROLA  
Chapter 30. Fast Ethernet Controller  
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Part IV. Communications Processor Module  
¥
¥
Multibuffer data structure  
Supports 48-bit addresses in three modes  
Ñ Physical. One 48-bit address recognized or 64-bin hash table for physical  
addresses  
Ñ Logical. 64-bin group address hash table plus broadcast address checking  
Ñ Promiscuous. Receives all frames regardless of address (a CAM can be used for  
address Þltering)  
¥
¥
¥
¥
External CAM support on system bus interfaces  
Special RMON counters for monitoring network statistics  
Up to eight parallel I/O pins can be sampled and appended to any frame  
Transmitter network management and diagnostics  
Ñ Lost carrier sense  
Ñ Underrun  
Ñ Number of collisions exceeded the maximum allowed  
Ñ Number of retries per frame  
Ñ Deferred frame indication  
Ñ Late collision  
¥
Receiver network management and diagnostics  
Ñ CRC error indication  
Ñ Nonoctet alignment error  
Ñ Frame too short  
Ñ Frame too long  
Ñ Overrun  
Ñ Busy (out of buffers)  
¥
Error counters  
Ñ Discarded frames (out of buffers or overrun occurred)  
Ñ CRC errors  
Ñ Alignment errors  
¥
¥
¥
¥
¥
Internal and external loopback mode  
Supports Fast Ethernet in duplex mode  
Supports pause ßow control frames  
Support of out-of-sequence transmit queue (for ßow-control frames)  
External buffer descriptors (BDs)  
30.3 Connecting the MPC8260 to Fast Ethernet  
Figure 30-3 shows the basic components of the media-independent interface (MII) and the  
signals required to make the Fast Ethernet connection between the MPC8260 and a PHY.  
30-4  
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Part IV. Communications Processor Module  
Media-Independent Interface (MII)  
Transmit Error (TX_ER)  
Transmit Nibble Data 0Ð3 (TXD[0Ð3])  
Transmit Enable (TX_EN)  
Transmit Clock (TX_CLK)  
Collision Detect (COL)  
Receive Nibble Data (RXD[0Ð3])  
Receive Error (RX_ER)  
Medium  
Fast Ethernet  
PHY  
MPC8260  
Receive Clock (RX_CLK)  
Receive Data Valid (RX_DV)  
Carrier Sense Output (CRS)  
1
Management Data Clock (MDC)  
1
Management Data I/O (MDIO)  
1
The management signals (MDC and MDIO) can be common to all of the Fast Ethernet connections in  
the system, assuming that each PHY has a different management address. Use parallel I/O port pins to  
2
implement MDC and MDIO. (The I C controller cannot be used for this function.)  
Figure 30-3. Connecting the MPC8260 to Ethernet  
Each FCC has 18 signals, deÞned by the IEEE 802.3u standard, for connecting to an  
Ethernet PHY. The two management signals (MDC and MDIO) required by the MII should  
be implemented separately using the parallel I/O.  
The MPC8260 has additional signals for interfacing with an optional external  
content-addressable memory (CAM), which are described in Section 30.7, ÒCAM  
Interface.Ó  
The MPC8260 uses the SDMA channels to store every byte received after the start frame  
delimiter into system memory. On transmit, the user provides the destination address,  
source address, type/length Þeld, and transmit data. To meet minimum frame requirements,  
MPC8260 automatically pads frames with fewer than 64 bytes in the data Þeld. The  
MPC8260 also appends the FCS to the frame.  
30.4 Ethernet Channel Frame Transmission  
The Ethernet transmitter requires almost no core intervention. When the core enables the  
transmitter, the Ethernet controller polls the Þrst TxBD in the FCCÕs TxBD table every 256  
serial clocks. If the user has a frame ready to transmit, setting TODR[TOD] eliminates  
waiting for the next poll. When there is a frame to transmit, the Ethernet controller begins  
fetching the data from the data buffer and asserts TX_EN. The preamble sequence, start  
MOTOROLA  
Chapter 30. Fast Ethernet Controller  
30-5  
     
Part IV. Communications Processor Module  
frame delimiter, and frame information are sent in that order; see Figure 30-1. In full-  
duplex mode, since collisions are ignored, frame transmission maintains only the  
interframe gap (96 serial clocks) regardless of CRS.  
There is one internal buffer for out-of-sequence ßow control frames (in full-duplex Fast  
Ethernet). When the Fast Ethernet controller is between frames, this buffer is polled if ßow  
control is enabled. This buffer must contain the whole frame.  
However, in half-duplex mode, the controller defers transmission if the line is busy (CRS  
asserted). Before transmitting, the controller waits for carrier sense to become inactive, at  
which point the controller determines if CRS remains negated for 60 serial clocks. If so, the  
transmission begins after an additional 36 serial clocks (96 serial clocks after CRS  
originally became negated).  
If a collision occurs during the transmit frame, the Ethernet controller follows a speciÞed  
backoff procedure and tries to retransmit the frame until the retry limit is reached. The  
Ethernet controller stores at least the Þrst 64 bytes of data of the transmit frame in the dual-  
port RAM, so that the data does not have to be retrieved from system memory in case of a  
collision. This improves bus usage and latency if the backoff timer output requires an  
immediate retransmission.  
When the end of the current buffer is reached and TxBD[L] = 1, the FCS (32-bit CRC) bytes  
are appended (if TxBD[TC] = 1), and TX_EN is negated. This notiÞes the PHY of the need  
to generate the illegal Manchester encoding that signiÞes the end of an Ethernet frame.  
Following the transmission of the FCS, the Ethernet controller writes the frame status bits  
into the BD and clears TxBD[R]. When the end of the current buffer is reached and  
TxBD[L] = 0 (a frame is comprised of multiple buffers), only TxBD[R] is cleared.  
For both half- and full-duplex modes, an interrupt can be issued depending on TxBD[I].  
The Ethernet controller then proceeds to the next TxBD in the table. In this way, the core  
can be interrupted after each frame, after each buffer, or after a speciÞc buffer is sent. If  
TxBD[PAD] = 1, the Ethernet controller pads short frames to the value of the minimum  
frame length register (MINFLR), described in Table 30-2.  
To rearrange the transmit queue before the CP Þnishes sending all frames, issue a  
GRACEFUL STOP TRANSMIT command. This can be useful for transmitting expedited data  
ahead of previously linked buffers or for error situations. When the GRACEFUL STOP  
TRANSMIT command is issued, the Ethernet controller stops immediately if no transmission  
is in progress or continues transmission until the current frame either Þnishes or terminates  
with a collision. When the Ethernet controller is given the RESTART TRANSMIT command,  
it resumes transmission. The Ethernet controller sends bytes least-signiÞcant nibble Þrst.  
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MOTOROLA  
Part IV. Communications Processor Module  
30.5 Ethernet Channel Frame Reception  
The Ethernet receiver is designed to work with almost no core intervention and can perform  
address recognition, CRC checking, short frame checking, maximum DMA transfer  
checking, and maximum frame-length checking.  
When the core enables the Ethernet receiver, it enters hunt mode when RX_DV is asserted  
as long as COL remains negated (full-duplex mode ignores COL). In hunt mode, as data is  
shifted into the receive shift register four bits at a time, the contents of the register are  
compared to the contents of the SYN2 Þeld in the FCCÕs data synchronization register  
(FDSR). When the registers match, the hunt mode is terminated and character assembly  
begins.  
When the receiver detects the Þrst bytes of a frame, the Ethernet controller performs  
address recognition functions on the frame; see Section 30.12, ÒEthernet Address  
Recognition.Ó The receiver can receive physical (individual), group (multicast), and  
broadcast addresses. Because Ethernet receive frame data is not written to memory until the  
internal address recognition algorithm is complete, bus usage is not wasted on frames not  
addressed to this station. The receiver can also operate with an external CAM, in which case  
frame reception continues normally, unless the CAM speciÞcally signals the frame to be  
rejected. See Section 30.7, ÒCAM Interface.Ó  
If an address is recognized, the Ethernet controller fetches the next RxBD and, if it is empty,  
starts transferring the incoming frame to the RxBDÕs associated data buffer.  
In half-duplex mode, if a collision is detected during the frame, the RxBDs associated with  
this frame are reused. Thus, no collision frames are presented to the user except late  
collisions, which indicate serious LAN problems. When the buffer has been Þlled, the  
Ethernet controller clears RxBD[E] and generates an interrupt if RxBD[I] is set. If the  
incoming frame is larger than the buffer, the Ethernet controller fetches the next RxBD in  
the table; if it is empty, it continues receiving the rest of the frame.  
The RxBD length is determined by MRBLR in the parameter RAM. The user should  
program MRBLR to be at least 64 bytes. During reception, the Ethernet controller checks  
for frames that are too short or too long. When the frame ends (CRS is negated), the receive  
CRC Þeld is checked and written to the data buffer. The data length written to the last BD  
in the Ethernet frame is the length of the entire frame, which enables the software to  
recognize a frame-too-long condition.  
If an external CAM is used (FPSMRx[CAM] = 1), the Ethernet controller adds the two  
lower bytes of the CAM output at the end of each frame. Note that the data length does not  
include these two bytes; that is, the extra two bytes could push the buffer length past  
MRBLR.  
When the receive frame is complete, the Ethernet controller sets RxBD[L], writes the other  
frame status bits into the RxBD, and clears RxBD[E]. The Ethernet controller next  
generates a maskable interrupt, indicating that a frame was received and is in memory. The  
MOTOROLA  
Chapter 30. Fast Ethernet Controller  
30-7  
   
Part IV. Communications Processor Module  
Ethernet controller then waits for a new frame. The Ethernet controller receives serial data  
least-signiÞcant nibble Þrst.  
30.6 Flow Control  
Because collisions cannot occur in full-duplex mode, Fast Ethernet can operate at the  
maximum rate. When the rate becomes too fast for a stationÕs receiver, the stationÕs  
transmitter can send ßow-control frames to reduce the rate. Flow-control instructions are  
transferred by special frames of minimum frame size. The length/type Þelds of these frames  
have a special value. Table 30-1 shows the ßow-control frame structure.  
Table 30-1. Flow Control Frame Structure  
Size [Octets]  
Description  
Preamble  
Value  
Comment  
7
1
6
6
2
2
2
SFD  
Start frame delimiter  
01-80C2-00-00-01 Multicast address reserved for use in MAC frames  
Destination address  
Source address  
Length/type  
88-08  
00-01  
Control frame type  
Pause command  
MAC opcode  
MAC parameter  
Pause period measured in slot times, most-  
signiÞcant octet Þrst  
42  
4
Reserved  
FCS  
Ñ
Frame check sequence (CRC)  
When ßow-control mode is enabled (FPSMRx[FCE]) and the receiver identiÞes a pause-  
ßow control frame sent to individual or broadcast addresses, transmission stops for the time  
speciÞed in the control frame. During this pause, only the out-of-sequence frame is sent.  
Normal transmission resumes after the pause timer stops counting. If another pause-control  
frame is received during the pause, the period changes to the new value received.  
30.7 CAM Interface  
The MPC8260 internal address recognition logic can be used in combination with an  
external CAM. When using a CAM, the FCC must be in promiscuous mode  
(FPSMRx[PRO] = 1). See Section 30.12, ÒEthernet Address Recognition.Ó  
The Ethernet controller writes two 32-bit accesses to the CAM and then reads the result in  
a 32-bit access. If the high bit of the result is set, the frame is rejected; otherwise, the lower  
16 bits are attached to the end of the frame.  
30-8  
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Part IV. Communications Processor Module  
30.8 Ethernet Parameter RAM  
For Ethernet mode, the protocol-speciÞc area of the FCC parameter RAM is mapped as in  
Table 30-2.  
Table 30-2. Ethernet-Specific Parameter RAM  
1
Offset  
Name  
Width  
Description  
0x3C  
0x40  
0x44  
0x48  
0x4C  
STAT_BUF Word Buffer of internal usage  
CAM_PTR Word CAM address  
C_MASK  
C_PRES  
Word Constant MASK for CRC (initialize to 0xDEBB_20E3). For the 32-bit CRC-CCITT.  
Word Preset CRC (initialize to 0xFFFF_FFFF). For the 32-bit CRC-CCITT.  
2
CRCEC  
Word CRC error counter. Counts each received frame with a CRC error. Does not count  
frames not addressed to the station, frames received in the out-of-buffers condition,  
frames with overrun errors, or frames with alignment errors.  
2
0x50  
0x54  
0x58  
ALEC  
Word Alignment error counter. Counts frames received with dribbling bits. Does not count  
frames not addressed to the station, frames received in the out-of-buffers condition,  
or frames with overrun errors.  
2
DISFC  
Word Discard frame counter. Incremented for discarded frames because of an out-of-  
buffers condition or overrun error.The CRC need not be correct for this counter to be  
incremented.  
RET_LIM Hword Retry limit (typically 15 decimal). Number of retries that should be made to send a  
frame. If the frame is not sent after this limit is reached, an interrupt can be  
generated.  
0x5A  
0x5C  
RET_CNT Hword Retry limit counter. Temporary decrementer used to count retries made.  
P_PER  
Hword Persistence. Allows the Ethernet controller to be less persistent after a collision.  
Normally cleared, P_PER can be from 0 to 9 (9 = least persistent). The value is  
added to the retry count in the backoff algorithm to reduce the chance of  
transmission on the next time-slot. Using a less persistent backoff algorithm  
increases throughput in a congested Ethernet LAN by reducing the chance of  
collisions. FPSMR[SBT] can also reduce persistence of the Ethernet controller. The  
Ethernet/802.3 speciÞcations permit the use of P_PER.  
0x5E  
0x60  
0x64  
BOFF_CNT Hword Backoff counter  
GADDR_H Word Group address Þlters high and low are used in the hash table function of the group  
addressing mode. The user may write zeros to these values after reset and before  
GADDR_L Word  
the Ethernet channel is enabled to disable all group hash address recognition  
functions. The SET GROUP ADDRESS command is used to enable the hash table. See  
Section 30.13, ÒHash Table Algorithm.Ó  
0x68  
0x6A  
0x6C  
TFCSTAT Hword Out-of-sequence TxBD. Includes the status/control, data length, and buffer pointer  
Þelds in the same format as a regular TxBD. Useful for sending ßow control frames.  
TFCLEN  
TFCPTR  
Hword  
Word  
This areaÕs TxBD[R] is always checked between frames, regardless of  
FPSMRx[FCE]. If it is not ready, a regular frame is sent. The user must set TxBD[L]  
when preparing this BD. If TxBD[I] is set, a TXC event is generated after frame  
transmission. This area should be cleared when not in use.  
0x70  
MFLR  
Hword Maximum frame length register (typically1518 decimal). If the Ethernet controller  
detects an incoming frame exceeding MFLR, it sets RxBD[LG] (frame too long) in the  
last RxBD, but does not discard the rest of the frame. The controller also reports the  
frame status and length of the received frame in the last RxBD. MFLR includes all in-  
frame bytes between the start frame delimiter and the end of the frame.  
MOTOROLA  
Chapter 30. Fast Ethernet Controller  
30-9  
     
Part IV. Communications Processor Module  
Table 30-2. Ethernet-Specific Parameter RAM (Continued)  
1
Offset  
Name  
Width  
Description  
0x72  
0x74  
0x76  
0x78  
0x7A  
0x7C  
0x7E  
0x80  
PADDR1_H Hword The 48-bit individual address of this station. PADDR1_L is the lowest order half-  
word, and PADDR1_H is the highest order half-word.  
PADDR1_M Hword  
PADDR1_L Hword  
IBD_CNT Hword Internal BD counter  
IBD_START Hword Internal BD start pointer  
IBD_END Hword Internal BD end pointer  
TX_LEN  
Hword Tx frame length counter  
IBD_BASE  
32  
Bytes  
Internal microcode usage  
0xA0  
0xA4  
IADDR_H  
IADDR_L  
Word Individual address Þlter high/low. Used in the hash table function of the individual  
addressing mode.The user can write zeros to these values after reset and before the  
Word  
Ethernet channel is enabled to disable all individual hash address recognition  
functions. Issuing a SET GROUP ADDRESS command enables the hash table. See  
Section 30.13, ÒHash Table Algorithm.Ó  
0xA8  
MINFLR  
Hword Minimum frame length register (typically 64 decimal). If the Ethernet receiver detects  
an incoming frame shorter than MINFLR, it discards that frame unless FPSMR[RSH]  
(receive short frames) is set, in which case RxBD[SH] (frame too short) is set in the  
last RxBD. The Ethernet transmitter pads frames that are too short (according to  
TxBD[PAD] and the PAD value in the parameter RAM). PADs are added to make the  
transmit frame MINFLR bytes.  
0xAA  
0xAC  
0xAE  
0xB0  
TADDR_H Hword Allows addition of addresses to the individual and group hashing tables. After an  
address is placed in TADDR, issue a SET GROUP ADDRESS command. TADDR_L is  
the lowest-order half-word; TADDR_H is the highest.  
A zero in the I/G bit indicates an individual address; 1 indicates a group address.  
TADDR_M Hword  
TADDR_L Hword  
PAD_PTR Hword Internal PAD pointer. This internal 32-byte aligned pointer points to a 32-byte buffer  
Þlled with pad characters.The pads may be any value, but all the bytes should be the  
same to assure padding with a speciÞc character. If a speciÞc padding character is  
not needed, PAD_PTR should equal the internal temporary data pointer TIPTR; see  
Section 28.7, ÒFCC Parameter RAM.Ó  
0xB2  
0xB4  
0xB6  
0xB8  
Ñ
Hword Reserved, should be cleared.  
CF_RANGE Hword Control frame range. Internal usage  
MAX_B  
Hword Maximum BD byte count. Internal usage  
MAXD1  
Hword Max DMA1 length register (typically 1520 decimal). Lets the user prevent system bus  
writes after a frame exceeds a speciÞed size. The MAXD1 value is valid only if an  
address match is detected. If the Ethernet controller detects an incoming Ethernet  
frame larger than the user-deÞned value in MAXD1, the rest of the frame is  
discarded.The Ethernet controller waits for the end of the frame (or until MFLR bytes  
have been received) and reports the frame status and length (including the  
discarded bytes) in the last RxBD. This value must be greater than 32.  
30-10  
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MOTOROLA  
Part IV. Communications Processor Module  
Table 30-2. Ethernet-Specific Parameter RAM (Continued)  
1
Offset  
Name  
Width  
Description  
0xBA  
MAXD2  
Hword Max DMA2 length register (typically 1520 decimal). Lets the user prevent system bus  
writes after a frame exceeds a speciÞed size. The value of MAXD2 is valid in  
promiscuous mode when no address match is detected. If the Ethernet controller  
detects an incoming Ethernet frame larger than the value in MAXD2, the rest of the  
frame is discarded. The Ethernet controller waits for the end of the frame (or until  
MFLR bytes are received) and reports frame status and length (including the  
discarded bytes) in the last RxBD. In a monitor station, MAXD2 can be much less  
than MAXD1 to receive entire frames addressed to this station, but receive only the  
headers of all other frames.This value must be less than MAXD1.  
0xBC  
0xBE  
0xC0  
MAXD  
Hword Rx maximum DMA. Internal usage  
DMA_CNT Hword Rx DMA counter. Temporary down-counter used to track the frame length.  
2
OCTC  
COLC  
BROC  
MULC  
Word (RMON mode only) The total number of octets of data (including those in bad  
packets) received on the network (excluding framing bits but including FCS octets).  
2
2
2
0xC4  
0xC8  
Word (RMON mode only) The best estimate of the total number of collisions on this  
Ethernet segment.  
Word (RMON mode only) The total number of good packets received that were directed to  
the broadcast address. Note that this does not include multicast packets.  
0xCC  
0xD0  
0xD4  
Word (RMON mode only) The total number of good packets received that were directed to  
a multicast address. Note that this number does not include packets directed to the  
broadcast address.  
2
2
USPC  
FRGC  
Word (RMON mode only) The total number of packets received that were less than 64  
octets (excluding framing bits but including FCS octets) and were otherwise well-  
formed.  
Word (RMON mode only) The total number of packets received that were less than 64  
octets long (excluding framing bits but including FCS octets) and had either a bad  
FCS with an integral number of octets (FCS error) or a bad FCS with a non-integral  
number of octets (alignment error). Note that it is entirely normal for  
etherStatsFragments to increment because it counts both runts (which are normal  
occurrences due to collisions) and noise hits.  
2
2
0xD8  
0xDC  
OSPC  
JBRC  
Word (RMON mode only) The total number of packets received that were longer than 1518  
octets (excluding framing bits but including FCS octets) and were otherwise well-  
formed.  
Word (RMON mode only) The total number of packets received that were longer than 1518  
octets (excluding framing bits but including FCS octets), and had either a bad FCS  
with an integral number of octets (FCS error) or a bad FCS with a non-integral  
number of octets (alignment error). Note that this deÞnition of jabber is different than  
the deÞnition in IEEE-802.3 section 8.2.1.5 (10BASE5) and section 10.3.1.4  
(10BASE2). These documents deÞne jabber as the condition where any packet  
exceeds 20 ms. The allowed range to detect jabber is between 20 ms and 150 ms.  
2
2
0xE0  
0xE4  
P64C  
P65C  
Word (RMON mode only) The total number of packets (including bad packets) received  
that were 64 octets long (excluding framing bits but including FCS octets).  
Word (RMON mode only) The total number of packets (including bad packets) received  
that were between 65 and 127 octets long inclusive (excluding framing bits but  
including FCS octets).  
MOTOROLA  
Chapter 30. Fast Ethernet Controller  
30-11  
Part IV. Communications Processor Module  
Table 30-2. Ethernet-Specific Parameter RAM (Continued)  
1
Offset  
Name  
Width  
Description  
2
2
2
0xE8  
P128C  
Word (RMON mode only) The total number of packets (including bad packets) received  
that were between 128 and 255 octets long inclusive (excluding framing bits but  
including FCS octets).  
0xEC  
0xF0  
0xF4  
P256C  
P512C  
Word (RMON mode only) The total number of packets (including bad packets) received  
that were between 256 and 511 octets long inclusive (excluding framing bits but  
including FCS octets).  
Word (RMON mode only) The total number of packets (including bad packets) received  
that were between 512 and 1023 octets long inclusive (excluding framing bits but  
including FCS octets).  
2
P1024C  
Word (RMON mode only) The total number of packets (including bad packets) received  
that were between 1024 and 1518 octets long inclusive (excluding framing bits but  
including FCS octets).  
0xF8  
0xFC  
CAM_BUF Word Internal buffer for CAM result  
Word Reserved, should be cleared.  
Ñ
1
2
Offset from FCC base: 0x8400 (FCC1), 0x8500 (FCC2) and 0x8600 (FCC3); see Section 13.5.2, ÒParameter RAM.Ó  
32-bit (modulo 232) counters maintained by the CP; cleared by the user while the channel is disabled.  
30.9 Programming Model  
The core conÞgures an FCC to operate as an Ethernet controller using GFMR[MODE]. The  
receive errors (collision, overrun, nonoctet-aligned frame, short frame, frame too long, and  
CRC error) are reported through the RxBD. The transmit errors (underrun, heartbeat, late  
collision, retransmission limit, and carrier sense lost) are reported through the TxBD.  
The user should program the FDSR as described in Section 28.4, ÒFCC Data  
Synchronization Registers (FDSRx),Ó with FDSR[SYN2] = 0xD5 and FDSR[SYN1] =  
0x55.  
30.10 Ethernet Command Set  
The transmit and receive commands are issued to the CPCR; see Section 13.4, ÒCommand  
Set.Ó  
NOTE  
Before resetting the CPM, conÞgure TX_EN (RTS) to be an  
input.  
Transmit commands that apply to Ethernet are described in Table 30-3.  
Table 30-3. Transmit Commands  
Command  
Description  
STOP  
When used with the Ethernet controller, this command violates a speciÞc behavior of an Ethernet/IEEE  
802.3 station. It should not be used.  
TRANSMIT  
30-12  
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MOTOROLA  
           
Part IV. Communications Processor Module  
Table 30-3. Transmit Commands (Continued)  
Command  
Description  
COMMANDS:FA Used to smoothly stop transmission after the current frame Þnishes sending or undergoes a collision  
(immediately if there is no frame being sent). FCCE[GRA] is set once transmission stops. Then the  
COMMUNICATI Ethernet transmit parameters (including BDs) can be modiÞed by the user. The TBPTR points to the  
ST  
ONS  
next TxBD in the table. Transmission begins when the R bit of the next BD is set and the RESTART  
TRANSMIT command is issued. Note that if the GRACEFUL STOP TRANSMIT command is issued and the  
CONTROLLER  
(FCC):ETHER current transmit frame ends in a collision, the TBPTR points to the beginning of the collided frame with  
NET  
TxBD[R] still set (the frame looks as if it was never sent).  
MODE:TRANSMI  
T COMMANDS  
GRACEFUL  
STOP  
TRANSMIT  
RESTART  
TRANSMIT  
Enables transmission of characters on the transmit channel. It is expected by the Ethernet controller  
after a GRACEFUL STOP TRANSMIT command or transmitter error (underrun, retransmission limit  
reached, or late collision). The Ethernet controller resumes transmission from the current TBPTR in  
the channel TxBD table.  
INIT TX  
Initializes all the transmit parameters in this serial channel parameter RAM to their reset state. This  
command should be issued only when the transmitter is disabled. Note that the INIT TX AND RX  
PARAMETERS command can also be used to reset the transmit and receive parameters.  
PARAMETERS  
Receive commands that apply to Ethernet are described in Table 30-4.  
Table 30-4. Receive Commands  
Command  
Description  
ENTER HUNT  
MODE  
After the hardware or software is reset and the channel in the FCC mode register is enabled, the  
channel is in the receive enable mode and uses the Þrst BD in the table. This command is generally  
used to force the Ethernet receiver to abort reception of the current frame and enter hunt mode. In  
hunt mode, the Ethernet controller continually scans the input data stream for a transition of carrier  
sense from inactive to active followed by a preamble sequence and the start frame delimiter. After  
receiving the command, the current receive buffer is closed and the CRC calculation is reset. Further  
frame reception uses the next RxBD.  
Note that short frames pending in the internal FIFO may be lost.  
INIT RX  
Initializes all the receive parameters in this serial channel parameter RAM to their reset state and  
should only be issued when the receiver is disabled. Note that the INIT TX AND RX PARAMETERS  
command can also be used to reset the receive and transmit parameters.  
PARAMETERS  
SET GROUP  
ADDRESS  
Used to set one of the 64 bits of the four individual/group address hash Þlter registers (GADDR[1Ð4]  
or IADDR[1Ð4]). The individual or group address (48 bits) to be added to the hash table should be  
written to TADDR_L, TADDR_M, and TADDR_H in the parameter RAM prior to executing this  
command.The CP checks the I/G bit in the address stored in TADDR to determine whether to use the  
individual hash table or the group hash table. A 0 in the I/G bit indicates an individual address; 1  
indicates a group address. This command can be executed at any time, regardless of whether the  
Ethernet channel is enabled.  
If an address from the hash table must be deleted, the Ethernet channel must be disabled,  
the hash table registers must be cleared, and the SET GROUP ADDRESS command must be  
executed for the remaining preferred addresses. This is required because the hash table  
might have mapped multiple addresses to the same hash table bit.  
MOTOROLA  
Chapter 30. Fast Ethernet Controller  
30-13  
   
Part IV. Communications Processor Module  
30.11 RMON Support  
The Fast Ethernet controller can automatically gather network statistics required for  
RMON without the need to receive all addresses using promiscuous mode. Setting  
FPSMRx[MON] enables RMON support.  
The RMON statistics and their corresponding counters in the parameter RAM are described  
in Table 30-5.  
Table 30-5. RMON Statistics and Counters  
Statistic  
Description  
Counter  
etherStatsDropEvents  
The total number of events in which packets were detected as  
dropped by the probe due to lack of resources. Note that this may  
not be the number of packets dropped; it is the number of times this  
condition is detected.  
DISFC  
etherStatsOctets  
etherStatsPkts  
The total number of octets of data (including those in bad packets)  
received on the network (excluding framing bits but including FCS  
octets).  
OCTC  
The total number of packets (including bad packets, broadcast  
packets, and multicast packets) received.  
USPC +  
OSPC +  
FRGC +  
JBRC +  
P64C +  
P65C +  
P128C +  
P256C +  
P512C +  
P1024C  
etherStatsBroadcastPkts  
etherStatsMulticastPkts  
etherStatsCRCAlignErrors  
The total number of good packets received that were directed to  
the broadcast address. Note that this does not include multicast  
packets.  
BROC  
The total number of good packets received that were directed to a  
multicast address. Note that this number does not include packets  
directed to the broadcast address.  
MULC  
The total number of packets received that had a length (excluding  
framing bits but including FCS octets) of between 64 and 1518  
octets, inclusive, but had either an integral number of octets (FCS  
error) or a bad FCS with a non-integral number of octets (alignment  
error).  
CRCEC +  
ALEC -  
FRGC -  
GBRC  
etherStatsUndersizePkts  
etherStatsOversizePkts  
The total number of packets received that were less than 64 octets  
long (excluding framing bits but including FCS octets) and were  
otherwise well-formed.  
USPC  
OSPC  
The total number of packets received that were longer than 1518  
octets (excluding framing bits but including FCS octets) and were  
otherwise well-formed.  
30-14  
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MOTOROLA  
     
Part IV. Communications Processor Module  
Table 30-5. RMON Statistics and Counters (Continued)  
Statistic  
etherStatsFragments  
Description  
Counter  
The total number of packets received that were less than 64 octets  
long (excluding framing bits but including FCS octets) and had  
either a bad FCS with an integral number of octets (FCS error) or a  
bad FCS with a non-integral number of octets (alignment error).  
Note that it is entirely normal for etherStatsFragments to increment,  
because it counts both runts (which are normal occurrences due to  
collisions) and noise hits.  
FRGC  
etherStatsJabbers  
The total number of packets received that were longer than 1518  
octets (excluding framing bits but including FCS octets) and had  
either a bad FCS with an integral number of octets (FCS error) or a  
bad FCS with a non-integral number of octets (alignment error).  
Note that this deÞnition of jabber is different than the deÞnition in  
IEEE-802.3 Section 8.2.1.5 (10BASE5) and Section 10.3.1.4  
(10BASE2). These documents deÞne jabber as the condition  
where any packet exceeds 20 ms. The allowed range to detect  
jabber is between 20 ms and 150 ms.  
JBRC  
etherStatsCollisions  
The best estimate of the total number of collisions on this Ethernet  
segment.  
COLC  
P64C  
etherStatsPkts64Octets  
The total number of packets (including bad packets) received that  
were 64 octets long (excluding framing bits but including FCS  
octets).  
etherStatsPkts65to127Octets  
etherStatsPkts128to255Octets  
etherStatsPkts256to511Octets  
The total number of packets (including bad packets) received that  
were between 65 and 127 octets long inclusive (excluding framing  
bits but including FCS octets).  
P65C  
P128C  
P256C  
P512C  
P1024C  
The total number of packets (including bad packets) received that  
were between 128 and 255 octets long inclusive (excluding framing  
bits but including FCS octets).  
The total number of packets (including bad packets) received that  
were between 256 and 511 octets long inclusive (excluding framing  
bits but including FCS octets).  
etherStatsPkts512to1023Octets The total number of packets (including bad packets) received that  
were between 512 and 1023 octets long inclusive (excluding  
framing bits but including FCS octets).  
etherStatsPkts1024to1518Octets The total number of packets (including bad packets) received that  
were between 1024 and 1518 octets long inclusive (excluding  
framing bits but including FCS octets).  
30.12 Ethernet Address Recognition  
The Ethernet controller can Þlter the received frames based on different addressing typesÑ  
physical (individual), group (multicast), broadcast (all-ones group address), and  
promiscuous. The difference between an individual address and a group address is  
determined by the I/G bit in the destination address Þeld.  
Figure 30-4 is a ßowchart for address recognition on received frames.  
MOTOROLA  
Chapter 30. Fast Ethernet Controller  
30-15  
     
Part IV. Communications Processor Module  
Check  
Address  
G
I
I/G Address  
F
F
Individual  
Broadcast  
Addr  
Addr Match?  
T
Hash Search  
Hash Search  
T
Use Group  
Table  
Use Individual  
Table  
Broadcast  
Enabled  
T
T
Receive Frame  
Match?  
F
F
F
T
Promiscuous?  
T
Use  
CAM?  
F
T
F
Rejected  
by CAM?  
Discard Frame  
Start Receive  
Figure 30-4. Ethernet Address Recognition Flowchart  
30-16  
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MOTOROLA  
 
Part IV. Communications Processor Module  
In the physical type of address recognition, the Ethernet controller compares the destination  
address Þeld of the received frame with the physical address that the user programs in the  
PADDR. If it fails, the controller performs address recognition on multiple individual  
addresses using the IADDR_H/L hash table. Since the controller always checks PADDR  
and the individual hash, for individual address the user must write zeros to the hash in order  
to avoid a hash match and ones to PADDR in order to avoid individual address match.  
In the group type of address recognition, the Ethernet controller determines whether the  
group address is a broadcast address. If it is a broadcast and broadcast addresses are  
enabled, the frame is accepted. If the group address is not a broadcast address, the user can  
perform address recognition on multiple group addresses using the GADDR_H/L hash  
table. In promiscuous mode, the Ethernet controller receives all of the incoming frames  
regardless of their address when an external CAM is not used.  
If an external CAM is used for address recognition (FPSMR[CAM] = 1), the user should  
select promiscuous mode; the frame can be rejected if there is no match in the CAM. If the  
on-chip address recognition functions detect a match, the external CAM is not accessed.  
30.13 Hash Table Algorithm  
The hash table process used in the individual and group hash Þltering operates as follows.  
The Ethernet controller maps any 48-bit address into one of 64 bins, which are represented  
by the 64 bits in GADDR_H/L or IADDR_H/L. When the SET GROUP ADDRESS command  
is executed, the Ethernet controller maps the selected 48-bit address in TADDR into one of  
the 64 bits. This is performed by passing the 48-bit address through the on-chip 32-bit CRC  
generator and using 6 bits of the CRC-encoded result to generate a number between 1 and  
64. Bit 26 of the CRC result selects between the two GADDRs or IADDRs; bits 27Ð31 of  
the CRC result select which bit is set.  
The same process is used when the Ethernet controller receives a frame. If the CRC  
generator selects a bit that is set in the group/individual hash table, the frame is accepted;  
otherwise, it is rejected. The result is that if eight group addresses are stored in the hash  
table and random group addresses are received, the hash table prevents roughly 56/64  
(87.5%) of the group address frames from reaching memory. The core must further Þlter  
those that reach memory to determine if they contain one of the eight preferred addresses.  
Better performance is achieved by using the group and individual hash tables in  
combination. For instance, if eight group and eight physical addresses are stored in their  
respective hash tables, 87.5% of all frames (not just group address frames) are prevented  
from reaching memory.  
The effectiveness of the hash table declines as the number of addresses increases. For  
instance, with 128 addresses stored in a 64-bin hash table, the vast majority of the hash table  
bits are set, preventing only a small fraction of frames from reaching memory. In such  
instances, an external CAM is advised if the extra bus use cannot be tolerated. See  
Section 30.7, ÒCAM Interface.Ó  
MOTOROLA  
Chapter 30. Fast Ethernet Controller  
30-17  
     
Part IV. Communications Processor Module  
NOTE  
The hash tables cannot be used to reject frames that match a set  
of selected addresses because unintended addresses can map to  
the same bit in the hash table. Thus, an external CAM must be  
used to implement this function.  
30.14 Interpacket Gap Time  
The minimum interpacket gap time for back-to-back transmission is 96 serial clocks. The  
receiver receives back-to-back frames with this minimum spacing. In addition, after the  
backoff algorithm, the transmitter waits for carrier sense to be negated before retransmitting  
the frame. The retransmission begins 96 serial clocks after carrier sense is negated if it stays  
negated for at least 60 serial clocks. So if there is no change in the carrier sense indication  
during the Þrst 60 serial clocks after the retransmission begins 96 clocks after carrier sense  
is Þrst negated  
30.15 Handling Collisions  
If a collision occurs during frame transmission, the Ethernet controller continues  
transmission for at least 32-bit times, transmitting a jam pattern of 32 ones. If the collision  
occurs during the preamble sequence, the jam pattern is sent after the sequence ends.  
If a collision occurs within 64 byte times, the process is retried. The transmitter waits a  
random number of slot times. (A slot time is 512 bit times.) If a collision occurs after 64  
byte times, no retransmission is performed, FCCE[TXE] is set, and the buffer is closed with  
a late-collision error indication in TxBD[LC]. If a collision occurs during frame reception,  
reception is stopped. This error is reported only in the RxBD if the frame is at least as long  
as the MINFLR or if FPSMR[RSH] = 1.  
30.16 Internal and External Loopback  
Both internal and external loopback are supported by the Ethernet controller. In loopback  
mode, both receive and transmit FIFO buffers are used and the FCC operates in full-duplex.  
Both internal and external loopback are conÞgured using combinations of FPSMR[LPB]  
and GFMR[DIAG]. Because of the full-duplex nature of the loopback operation, the  
performance of the other FCCs is degraded.  
Internal loopback disconnects the FCC from the SI. The receive data is connected to the  
transmit data. The transmitted data from the transmit FIFO is received immediately into the  
receive FIFO. There is no heartbeat check in this mode.  
In external loopback operation, the Ethernet controller listens for data received from the  
PHY while it is sending.  
30-18  
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Part IV. Communications Processor Module  
30.17 Ethernet Error-Handling Procedure  
The Ethernet controller reports frame reception and transmission error conditions using the  
channel BDs, the error counters, and the FCC event register.  
Transmission errors are described in Table 30-6.  
Table 30-6. Transmission Errors  
Error  
Response  
Transmitter underrun  
The controller sends 32 bits that ensure a CRC error, terminates buffer transmission, closes  
the buffer, sets TxBD[UN] and FCCE[TXE]. The controller resumes transmission after  
receiving the RESTART TRANSMIT command.  
Carrier sense lost during If no collision is detected in the frame, the controller sets TxBD[CSL] and FCCE[TXE], and it  
frame transmission  
continues the buffer transmission normally. No retries are performed as a result of this error.  
Retransmission  
attempts limit expired  
The controller terminates buffer transmission, closes the buffer, sets TxBD[RL] and  
FCCE[TXE]. Transmission resumes after receiving the RESTART TRANSMIT command.  
Late collision  
The controller terminates buffer transmission, closes the buffer, sets TxBD[LC] and  
FCCE[TXE]. The controller resumes transmission after receiving the RESTART TRANSMIT  
command. Note that late collision parameters are deÞned in FPSMR[LCW].  
Reception errors are described in Table 30-7.  
Table 30-7. Reception Errors  
Error  
Description  
Overrun error  
The Ethernet controller maintains an internal FIFO buffer for receiving data. If a receiver FIFO buffer  
overrun occurs, the controller writes the received data byte to the internal FIFO buffer over the  
previously received byte. The previous data byte and frame status are lost. The controller closes the  
buffer, sets RxBD[OV] and FCCE[RXF], and increments the discarded frame counter (DISFC). The  
receiver then enters hunt mode.  
Busy error  
A frame is received and discarded due to a lack of buffers. The controller sets FCCE[BSY] and  
increments the discarded frame counter (DISFC).  
Non-octet error The Ethernet controller handles a nibble of dribbling bits when the receive frame terminates as  
(dribbling bits)  
nonoctet aligned and it checks the CRC of the frame on the last octet boundary. If there is a CRC  
error, the frame nonoctet aligned (RxBD[NO]) error is reported, FCCE[RXF] is set, and the  
alignment error counter (ALEC) in the parameter RAM is incremented. If there is no CRC error, no  
error is reported.  
CRC error  
When a CRC error occurs, the controller closes the buffer, and sets RxBD[CR] and FCCE[RXF].  
Also, the CRC error counter (CRCEC) in the parameter RAM is incremented. After receiving a frame  
with a CRC error, the receiver enters hunt mode. CRC checking cannot be disabled, but the CRC  
error can be ignored if checking is not required.  
30.18 Fast Ethernet Registers  
The following sections describe registers used for conÞguring and operating the Fast  
Ethernet controller.  
MOTOROLA  
Chapter 30. Fast Ethernet Controller  
30-19  
           
Part IV. Communications Processor Module  
30.18.1 FCC Ethernet Mode Register (FPSMR)  
In Ethernet mode, the FCC protocol-speciÞc mode register, shown in Figure 30-5,  
functions as the Ethernet mode register.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
HBC FC SBT LPB LCW FDE MON  
Ñ
PRO FCE RSH  
Ñ
0000_0000_0000_0000  
R/W  
Addr  
Bits  
0x11304 (FPSMR1), 0x11324 (FPSMR2), 0x11324 (FPSMR3)  
16  
17  
18  
Ñ
19  
20  
21  
22  
23  
Ñ
24  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
CAM BRO  
CRC  
Ñ
0000_0000_0000_0000  
R/W  
Addr  
0x11306 (FPSMR1), 0x11326 (FPSMR2), 0x11326 (FPSMR3)  
Figure 30-5. FCC Ethernet Mode Registers (FPSMR)  
Table 30-8 describes FPSMR Þelds.  
Table 30-8. FPSMR Ethernet Field Descriptions  
Bits  
Name  
Description  
0
1
HBC  
Heartbeat checking  
0
1
Heartbeat checking is not performed. Do not wait for a collision after transmission.  
Wait 40 transmit serial clocks for a collision asserted by the transceiver after transmission.  
TxBD[HB] is set if the heartbeat is not heard within 40 transmit serial clocks.  
FC  
Force collision  
0
1
Normal operation.  
The controller forces a collision on transmission of every transmit frame. The MPC8260  
should be conÞgured in loopback operation when using this feature, which allows the user to  
test the MPC8260 collision logic. It causes the retry limit to be exceeded for each transmit  
frame.  
2
SBT  
Stop backoff timer  
0
1
The backoff timer functions normally.  
The backoff timer (for the random wait after a collision) is stopped whenever carrier sense is  
active. In this method, the retransmission is less aggressive than the maximum allowed in the  
IEEE 802.3 standard.The persistence (P_PER) feature in the parameter RAM can be used in  
combination with the SBT bit (or in place of the SBT bit).  
3
4
LPB  
Local protect bit  
0
1
Receiver is blocked when transmitter sends (default).  
Receiver is not blocked when transmitter sends. Must be set for full-duplex operation. For  
loopback operation, GFMR[DIAG] must be programmed also; see Section 28.2, ÒGeneral  
FCC Mode Registers (GFMRx).Ó  
LCW  
Late collision window  
0
1
A late collision is any collision that occurs at least 64 bytes from the preamble.  
A late collision is any collision that occurs at least 56 bytes from the preamble.  
30-20  
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MOTOROLA  
         
Part IV. Communications Processor Module  
Table 30-8. FPSMR Ethernet Field Descriptions (Continued)  
Bits  
Name  
Description  
5
6
FDE  
Full duplex Ethernet  
0
1
Disable full-duplex.  
Enable full-duplex. Must be set if FSMR[LPB] is set or external loopback is performed.  
MON  
RMON mode  
0
1
Disable RMON mode.  
Enable RMON mode.  
7Ð8  
9
Ñ
Reserved, should be cleared.  
PRO  
Promiscuous  
0
1
Check the destination address of incoming frames.  
Receive the frame regardless of its address. A CAM can be used for address Þltering when  
FSMR[CAM] is set.  
10  
11  
FCE  
RSH  
Flow control enable  
0
1
Flow control is not enabled.  
Flow control is enabled.  
Receive short frames  
0
1
Discard short frames (frames smaller than the value speciÞed in MINFLR).  
Receive short frames.  
12Ð20  
21  
Ñ
Reserved, should be cleared.  
CAM  
CAM address matching  
0
1
Normal operation.  
Use the CAM for address matching; CAM result (16 bits) is added at the end of the frame.  
22  
23  
BRO  
Ñ
Broadcast address  
0
1
Receive all frames containing the broadcast address.  
Reject all frames containing the broadcast address unless FSMR[PRO] = 1.  
Reserved, should be cleared.  
24Ð25 CRC  
CRC selection  
0x Reserved.  
10 32-bit CCITT-CRC (Ethernet). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 +  
X5 + X4 + X2 + X1 +1. Select this to comply with Ethernet speciÞcations.  
11 Reserved.  
26Ð31  
Ñ
Reserved, should be cleared.  
30.18.2 Ethernet Event Register (FCCE)/Mask Register (FCCM)  
The FCCE, shown in Figure 30-6, is used as the Ethernet event register when the FCC  
functions as an Ethernet controller. It generates interrupts and reports events recognized by  
the Ethernet channel. On recognition of an event, the Ethernet controller sets the  
corresponding FCCE bit. Interrupts generated by this register can be masked in the Ethernet  
mask register (FCCM).  
The FCCM has the same bit format as FCCE. Setting an FCCM bit enables and clearing a  
bit masks the corresponding interrupt in the FCCE.  
The FCCE can be read at any time. Bits are cleared by writing ones; writing zeros does not  
MOTOROLA  
Chapter 30. Fast Ethernet Controller  
30-21  
     
Part IV. Communications Processor Module  
affect bit values. Unmasked FCCE bits must be cleared before the CP clears the internal  
interrupt request.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Ñ
GRA RXC TXC TXE RXF BSY TXB RXB  
0000_0000_0000_0000  
R/W  
Addr  
0x11310 (FCCE1), 0x11330 (FCCE2), 0x11350 (FCCE3)/  
0x11314 (FCCM1), 0x11334 (FCCM2), 0x11354 (FCCM3)  
Figure 30-6. Ethernet Event Register (FCCE)/Mask Register (FCCM)  
Table 30-9 describes FCCE/FCCM Þelds.  
Table 30-9. FCCE/FCCM Field Descriptions  
Bits Name  
Description  
0Ð7  
8
Ñ
Reserved, should be cleared.  
GRA Graceful stop complete. A graceful stop, initiated by the GRACEFUL STOP TRANSMIT command, is  
complete. When the command is issued, GRA is set as soon the transmitter Þnishes sending a frame  
in progress. If no frame is in progress, GRA is set immediately.  
9
RXC RX control. A control frame has been received (FSMR[FCE] must be set). As soon as the transmitter  
Þnishes sending the current frame, a pause operation is performed.  
10  
11  
12  
13  
14  
15  
TXC TX control. An out-of-sequence frame was sent.  
TXE Tx error. An error occurred on the transmitter channel.  
RXF Rx frame. Set when a complete frame is received on the Ethernet channel.  
BSY Busy condition. Set when a frame is received and discarded due to a lack of buffers.  
TXB Tx buffer. Set when a buffer has been sent on the Ethernet channel.  
RXB Rx buffer. A buffer that was not a complete frame is received on the Ethernet channel.  
Figure 30-7 shows interrupts that can be generated in the Ethernet protocol.  
30-22  
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Part IV. Communications Processor Module  
Frame  
Received in Ethernet  
Stored in Rx Buffer  
Time  
P
SFD DA SA T/L  
D
CR  
RXD  
Line Idle  
Line Idle  
RX_DV  
Ethernet FCCE  
Events  
RXB  
RXF  
Notes  
:
1. RXB event assumes receive buffers are 64 bytes each.  
2. The RXF interrupt may occur later than RX_DV due to receive FIFO latency.  
Frame  
Transmitted by Ethernet  
Stored in Tx Buffer  
P
SFD DA SA T/L  
D
CR  
TXD  
Line Idle  
Line Idle  
TX_EN  
COL  
Ethernet FCCE  
Events  
TXB  
TXB, GRA  
Notes:  
1. TXB events assume the frame required two transmit buffers.  
2. The GRA event assumes a GRACEFUL STOP TRANSMIT command was issued during frame transmission.  
Legend:  
P = Preamble, SFD = Start frame delimiter, DA and SA = Destination/Source address,  
T/L = Type/Length, D = Data, CR = CRC bytes  
Figure 30-7. Ethernet Interrupt Events Example  
Note that the FCC status register is not valid for the Ethernet protocol. The current state of  
the MII signals can be read through the parallel ports.  
30.19 Ethernet RxBDs  
The Ethernet controller uses the RxBD to report information about the received data for  
each buffer. Figure 30-8 shows the FCC Ethernet RxBD format.  
MOTOROLA  
Chapter 30. Fast Ethernet Controller  
30-23  
         
Part IV. Communications Processor Module  
0
1
2
3
4
L
5
F
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
E
Ñ
W
I
Ñ
M
BC  
MC  
LG  
NO  
SH  
CR  
OV  
CL  
Data Length  
Rx Data Buffer Pointer  
Figure 30-8. Fast Ethernet Receive Buffer (RxBD)  
Table 30-10 describes Ethernet RxBD Þelds.  
Table 30-10. RxBD Field Descriptions  
Bits Name  
Description  
0
E
Empty  
0
The buffer associated with this RxBD is full or reception terminated due to an error. The core can  
examine or read to any Þelds of this RxBD. The CP does not use this BD as long as E = 0.  
The associated buffer is empty. The RxBD and buffer are owned by the CP. Once E = 1, the core  
should not write any Þelds of this RxBD.  
1
1
2
Ñ
Reserved, should be cleared.  
Wrap (Þnal BD in RxBD table)  
W
0
1
Not the last BD in the table.  
Last BD in the table. After this buffer is used, the CP receives incoming data into the Þrst BD that  
RBASE points to in the table.The number of RxBDs in this table is programmable and determined  
only by the W bit.  
The RxBD table must contain more than one BD in Ethernet mode.  
3
4
I
Interrupt  
0
1
No interrupt is generated after this buffer is used.  
FCCE[RXB] or FCCE[RXF] are set when this buffer is used by the Ethernet controller. These two  
bits can cause interrupts if they are enabled.  
L
Last in frame. Set by the Ethernet controller when this buffer is the last in a frame. This implies the  
end of the frame or a reception error, in which case one or more of the CL, OV, CR, SH, NO, and LG  
bits are set. The Ethernet controller writes the number of frame octets to the data length Þeld.  
0
1
Not the last buffer in a frame.  
Last buffer in a frame.  
5
F
First in frame. Set by the Ethernet controller when this buffer is the Þrst in a frame.  
0
1
Not the Þrst buffer in a frame.  
First buffer in a frame.  
6
7
Ñ
M
Reserved, should be cleared.  
Miss. Set by the Ethernet controller for frames that are accepted in promiscuous mode, but are  
ßagged as a miss by the internal address recognition. Thus, while using promiscuous mode, the user  
uses the miss bit to determine quickly whether the frame is destined for this station. Valid only if  
RxBD[I] is set.  
0
1
The frame is received because the address is recognized.  
The frame is received because of promiscuous mode (address is not recognized).  
8
9
BC Broadcast address.Valid only for the last buffer in a frame (RxBD[L] = 1).The received frame address  
is the broadcast address.  
MC Multicast address. Valid only for the last buffer in a frame (RxBD[L] = 1). The received frame address  
is a multicast address other than a broadcast address.  
30-24  
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MOTOROLA  
   
Part IV. Communications Processor Module  
Table 30-10. RxBD Field Descriptions (Continued)  
Bits Name  
Description  
10  
11  
12  
LG Rx frame length violation. A frame length greater than the MFLR (maximum frame length) deÞned for  
this FCC is recognized.  
NO Rx nonoctet aligned frame. A frame that contained a number of bits not divisible by eight is received  
and the CRC check at the preceding byte boundary generated an error.  
SH Short frame. A frame length less than the MINFLR (minimum frame length) deÞned for this channel is  
recognized. This indication is possible only if the FPSMR[RSH] = 1.  
13  
14  
15  
CR Rx CRC error. This frame contains a CRC error.  
OV Overrun. A receiver overrun occurred during frame reception.  
CL  
Collision. This frame is closed because a collision occurred during frame reception. Set only if a late  
collision occurs or if FPSMR[RSH] is set. The late collision deÞnition is determined by the setting of  
FPSMR[LCW].  
Data length is the number of octets the CP writes into this BD data buffer. It is written by  
the CP as the buffer is closed. When this BD is the last BD in the frame (RxBD[L] = 1), the  
data length contains the total number of frame octets (including four bytes for CRC). Note  
that at least as much memory should be allocated for each receive buffer as the size  
speciÞed in MRBLR. MRBLR should be divisible by 32 and not less than 64.  
The receive buffer pointer, which points to the Þrst location of the associated data buffer,  
can reside in internal or external memory. This value must be divisible by 32.  
When a received frameÕs data length is an exact multiple of MRBLR, the last BD contains  
only the status and total frame length.  
Note that at least two BDs must be prepared before beginning reception.  
Figure 30-9 shows how RxBDs are used during Ethernet reception.  
MOTOROLA  
Chapter 30. Fast Ethernet Controller  
30-25  
Part IV. Communications Processor Module  
MRBLR = 64 Bytes for this FCC  
Buffer  
Receive BD 0  
E
0
L
0
F
1
Status  
Length  
Destination Address (6)  
Source Address (6)  
0x0040  
Buffer Full  
Pointer  
32-Bit Buffer Pointer  
64 Bytes  
Type/Length (2)  
Data Bytes (50)  
Receive BD 1  
Buffer  
CRC Bytes (4)  
Tag Byte (1)  
Empty  
E
0
L
1
F
0
Status  
Length  
0x0045  
Buffer Closed  
after CRC Received.  
Optional Tag Byte  
Appended  
Pointer  
32-Bit Buffer Pointer  
64 Bytes  
Receive BD 2  
Buffer  
E
1
Status  
Length  
Old Data from  
Collided Frame Will  
be Overwritten  
XXXX  
64 Bytes  
Collision  
Causes Buffer  
to be Reused  
Pointer  
32-Bit Buffer Pointer  
Empty  
Buffer  
Receive BD 3  
E
1
Status  
Length  
XXXX  
64 Bytes  
Empty  
Buffer  
Still Empty  
Pointer  
32-Bit Buffer Pointer  
Non-Collided Ethernet Frame 1  
Line Idle  
Frame 2  
Two Frames  
Received in Ethernet  
Collision  
Present  
Time  
Time  
Figure 30-9. Ethernet Receiving Using RxBDs  
30.20 Ethernet TxBDs  
Data is sent to the Ethernet controller for transmission on an FCC channel by arranging it  
in buffers referenced by the channelÕs TxBD table. The Ethernet controller uses TxBDs to  
conÞrm transmission or indicate errors so the core knows when buffers have been serviced.  
Figure 30-10 shows the FCC Ethernet TxBD format.  
30-26  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part IV. Communications Processor Module  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
R
PAD  
W
I
L
TC DEF HB  
LC  
RL  
RC  
UN CSL  
Data length  
Tx data Buffer Pointer  
Figure 30-10. Fast Ethernet Transmit Buffer (TxBD)  
Table 30-11 describes Ethernet TxBD Þelds.  
Table 30-11. Ethernet TxBD Field Definitions  
Field Name  
Description  
0
R
Ready  
0
The buffer associated with this BD is not ready for transmission; the user can manipulate this BD  
or its associated buffer. The CP clears R after the buffer has been sent or after an error.  
The buffer is ready to be sent. The buffer is either waiting or in the process of being sent. The  
user cannot change Þelds in this BD or its associated buffer once R = 1.  
1
1
2
PAD Short frame padding. Valid only when L = 1; otherwise, it is ignored.  
0
1
Do not add PADs to short frames.  
Add PADs to short frames. PAD bytes are inserted until the length of the transmitted frame equals  
the MINFLR.The PAD bytes are stored in a buffer pointed to by PAD_PTR in the parameter RAM.  
W
Wrap (Þnal BD in table)  
0
1
Not the last BD in the TxBD table.  
Last BD in the TxBD table. After this buffer is used, the CP receives incoming data into the Þrst  
BD that TBASE points to in the table. The number of TxBDs in this table is programmable and  
determined only by the W bit.  
The TxBD table must contain more than one BD in Ethernet mode.  
3
I
Interrupt  
0
1
No interrupt is generated after this buffer is serviced.  
FCCE[TXB] or FCCE[TXE] is set after this buffer is serviced. These bits can cause interrupts if  
they are enabled.  
4
5
L
Last  
0
1
Not the last buffer in the transmit frame.  
Last buffer in the current transmit frame.  
TC  
Tx CRC. Valid only when the L bit is set; otherwise, it is ignored.  
0
1
End transmission immediately after the last data byte.  
Transmit the CRC sequence after the last data byte.  
6
7
DEF Defer indication.This frame did not have a collision before it was sent but it was sent late because of  
deferring.  
HB  
Heartbeat. The collision input is not asserted within 40 transmit serial clocks following completion of  
transmission.This bit cannot be set unless FPSMR[HBC] = 1.Written by the Ethernet controller after  
sending the associated buffer.  
8
9
LC  
RL  
Late collision. A collision occurred after the number of bytes deÞned in FPSMR[LCW] (56 or 64) are  
sent. The Ethernet controller terminates the transmission and updates LC after sending the buffer.  
Retransmission limit.The transmitter failed (RET_LIM + 1) attempts to successfully send a message  
due to repeated collisions. The Ethernet controller updates RL after sending the buffer.  
MOTOROLA  
Chapter 30. Fast Ethernet Controller  
30-27  
   
Part IV. Communications Processor Module  
Table 30-11. Ethernet TxBD Field Definitions (Continued)  
Field Name  
Description  
10Ð13  
RC Retry count. Indicates the number of retries required for this frame to be successfully sent. If RC = 0,  
the frame is sent correctly the Þrst time. If RC = 15 and RET_LIM = 15 in the parameter RAM, 15  
retries were needed. If RC = 15 and RET_LIM > 15, 15 or more retries were needed. The Ethernet  
controller updates RC after sending the buffer.  
14  
15  
UN Underrun. The Ethernet controller encountered a transmitter underrun condition while sending the  
associated buffer. The Ethernet controller updates UN after sending the buffer.  
CSL Carrier sense lost. Carrier sense is lost during frame transmission. The Ethernet controller updates  
CSL after sending the buffer.  
Data length is the number of octets the Ethernet controller should transmit from this BD  
data buffer. This value should be greater than zero. The CP never modiÞes the data length  
in a TxBD.  
Tx data buffer pointer, which contains the address of the associated data buffer, can be even  
or odd. The buffer can reside in internal or external memory. The CP never modiÞes the  
buffer pointer.  
30-28  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Chapter 31  
FCC HDLC Controller  
310  
3L10 ayer 2 of the seven-layer OSI model is the data link layer (DLL), in which HDLC is one  
of the most common protocols. The framing structure of HDLC is shown in Figure 31-1.  
HDLC uses a zero insertion/deletion process (commonly known as bit stufÞng) to ensure  
that the bit pattern of the delimiter ßag does not occur in the Þelds between ßags. The  
HDLC frame is synchronous and therefore relies on the physical layer for a method of  
clocking and of synchronizing the transmitter/receiver.  
Because the layer 2 frame can be transmitted over a point-to-point link, a broadcast  
network, or a packet-and-circuit switched system, an address Þeld is needed for the frame's  
destination address. The length of this Þeld is commonly 0, 8, or 16 bits, depending on the  
data link layer protocol. For instance, SDLC and LAPB use an 8-bit address and SS#7 has  
no address Þeld because it is used always in point-to-point signaling links. LAPD further  
divides its 16-bit address into different Þelds to specify various access points within one  
device. It also deÞnes a broadcast address. Some HDLC-type protocols also permit  
extended addressing beyond 16 bits.  
The 8- or 16-bit control Þeld provides a ßow-control number and deÞnes the frame type  
(control or data). The exact use and structure of this Þeld depends upon the protocol using  
the frame. Data is transmitted in the data Þeld, which can vary in length depending upon  
the protocol using the frame. Layer 3 frames are carried in this data Þeld.  
Error control is implemented by appending a cyclic redundancy check (CRC) to the frame,  
which in most protocols is 16-bits long but can be as long as 32-bits. In HDLC, the lsb of  
each octet is transmitted Þrst and the msb of the CRC is transmitted Þrst.  
When GFMR[MODE] selects HDLC mode, that FCC functions as an HDLC controller.  
When an FCC in HDLC mode is used with a nonmultiplexed modem interface, the FCC  
outputs are connected directly to the external pins. Modem signals can be supported  
through the appropriate port pins. The receive and transmit clocks can be supplied either  
externally or from the bank of baud-rate generators. The HDLC controller can also be  
connected to one of the TDM channels of the serial interface and used with the TSA. The  
HDLC controller consists of separate transmit and receive sections whose operations are  
asynchronous with the core and can either be synchronous or asynchronous with other  
FCCs. The user can allocate external buffer descriptors (BDs) for receive and transmit tasks  
so many frames can be sent or received without core intervention.  
MOTOROLA  
Chapter 31. FCC HDLC Controller  
31-1  
         
Part IV. Communications Processor Module  
31.1 Key Features  
Key features of the HDLC include the following:  
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
Flexible data buffers with multiple buffers per frame  
Separate interrupts for frames and buffers (receive and transmit)  
Received frames threshold to reduce interrupt overhead  
Four address comparison registers with masks  
Maintenance of four 16-bit error counters  
Flag/abort/idle generation and detection  
Zero insertion/deletion  
16- or 32-bit CRC-CCITT generation/checking  
Detection of nonoctet-aligned frames  
Detection of frames that are too long  
Programmable ßags (0Ð15) between successive frames  
External BD table  
Up to T3 rate  
Support of time stamp mode for Rx frames  
Support of nibble mode HDLC (4 bits per clocks)  
31.2 HDLC Channel Frame Transmission Processing  
The HDLC transmitter is designed to work with almost no core intervention. When the core  
enables a transmitter, it starts sending ßags or idles as programmed in the HDLC mode  
register (FPSMR). The HDLC controller polls the Þrst BD in the transmit channel BD table.  
When there is a frame to transmit, the HDLC controller fetches the data (address, control,  
and information) from the Þrst buffer and begins sending the frame after Þrst inserting the  
user-speciÞed minimum number of ßags between frames. When the end of the current  
buffer is reached and TxBD[L] (last buffer in frame) is set, the FCC appends the CRC (if  
selected) and closing ßag. In HDLC, the lsb of each octet and the msb of the CRC are sent  
Þrst. Figure 31-1 shows a typical HDLC frame.  
Opening Flag  
Address  
Control  
Information (Optional)  
CRC  
Closing Flag  
8 Bits  
16 Bits  
8 Bits  
8n Bits  
16 Bits  
8 Bits  
Figure 31-1. HDLC Framing Structure  
After the closing ßag is sent, the HDLC controller writes the frame status bits into the BD  
and clears the R bit. When the end of the current BD is reached and the L (last) bit is not  
set (working in multibuffer mode), only the R bit is cleared. In either mode, an interrupt can  
be issued if the I bit in the TxBD is set. The HDLC controller then proceeds to the next  
TxBD in the table. In this way, the core can be interrupted after each buffer, after a speciÞc  
buffer, after each frame, or after a number of frames.  
31-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part IV. Communications Processor Module  
To rearrange the transmit queue before the CP has sent all buffers, issue the STOP TRANSMIT  
command. This can be useful for sending expedited data before previously linked buffers  
or for error situations. When receiving the STOP TRANSMIT command, the HDLC controller  
aborts the current frame transmission and starts transmitting idles or ßags. When the HDLC  
controller is given the RESTART TRANSMIT command, it resumes transmission. To insert a  
high-priority frame without aborting the current frame, the GRACEFUL STOP TRANSMIT  
command can be issued. A special interrupt (GRA) can be generated in the event register  
when the current frame is complete.  
31.3 HDLC Channel Frame Reception Processing  
The HDLC receiver is designed to work with almost no core intervention and can perform  
address recognition, CRC checking, and maximum frame length checking. The received  
frame is available for any HDLC-based protocol. When the core enables a receiver, the  
receiver waits for an opening ßag character. When it detects the Þrst byte of the frame, the  
HDLC controller compares the frame address against the user-programmable addresses.  
The user has four 16-bit address registers and an address mask available for address  
matching. The HDLC controller compares the received address Þeld to the user-deÞned  
values after masking with the address mask. The HDLC controller can also detect broadcast  
(all ones) address frames if one address register is written with all ones.  
If a match is detected, the HDLC controller checks the prefetched BD; if it is empty, it starts  
transferring the incoming frame to the BDÕs associated buffer. When the buffer is full, the  
HDLC controller clears BD[E] and generates an interrupt if BD[I] = 1. If the incoming  
frame is larger than the buffer, the HDLC controller fetches the next BD in the table and, if  
it is empty, continues transferring the frame to the associated buffer.  
During this process, the HDLC controller checks for frames that are too long. When the  
frame ends, the CRC Þeld is checked against the recalculated value and written to the  
buffer. The data length written to the last BD in the HDLC frame is the length of the entire  
frame. This enables HDLC protocols that lose frames to correctly recognize a frame-too-  
long condition.  
The HDLC controller then sets the last buffer in frame bit, writes the frame status bits into  
the BD, and clears the E bit and fetched the next BD. The HDLC controller then generates  
a maskable interrupt, indicating that a frame was received and is in memory. The HDLC  
controller then waits for a new frame. Back-to-back frames can be received separated only  
by a single shared ßag.  
The user can conÞgure the HDLC controller not to interrupt the core until a speciÞed  
number of frames have been received. This is conÞgured in the received frames threshold  
(RFTHR) location of the parameter RAM. This function can be combined with a timer to  
implement a time-out if fewer than the threshold number of frames are received.  
MOTOROLA  
Chapter 31. FCC HDLC Controller  
31-3  
   
Part IV. Communications Processor Module  
31.4 HDLC Parameter RAM  
When an FCC operates in HDLC mode, the protocol-speciÞc area of the FCC parameter  
RAM is mapped with the HDLC-speciÞc parameters in Table 31-1.  
Table 31-1. FCC HDLC-Specific Parameter RAM Memory Map  
1
Offset  
Name  
Width  
Description  
0x38  
0x44  
Ñ
3 Words Reserved  
C_MASK  
Word CRC constant. For the 16-bit CRC-CCITT, initialize C_MASK to 0x0000_F0B8. For the  
32-bit CRC-CCITT, initialize C_MASK to 0xDEBB_20E3.  
0x48  
C_PRES  
Word CRC preset. For the 16-bit CRC-CCITT, initialize C_PRES to 0x0000_FFFF. For the  
32-bit CRC-CCITT, initialize C_PRES to 0xFFFF_FFFF.  
2
0x4C  
0x4E  
DISFC  
Hword Discard frame counter. Counts error-free frames discarded due to lack of buffers.  
2
CRCEC  
Hword CRC error counter. Counts frames not addressed to the user or frames received in the  
BSY condition, but does not include overrun, CD lost, or abort errors.  
2
0x50  
0x52  
ABTSC  
Hword Abort sequence counter  
2
NMARC  
Hword Nonmatching address Rx counter. Counts nonmatching addresses received (error-free  
frames only). See the HMASK and HADDR[1Ð4] parameter description.  
0x54 MAX_CNT Word Max_length counter. Temporary decrementing counter that tracks frame length.  
0x58  
MFLR  
Hword Max frame length register. If the HDLC controller detects an incoming HDLC frame that  
exceeds the user-deÞned value in MFLR, the rest of the frame is discarded and the LG  
(Rx frame too long) bit is set in the last BD belonging to that frame. The HDLC controller  
waits for the end of the frame and then reports the frame status and length in the last  
RxBD. MFLR includes all in-frame bytes between the opening and closing ßags (address,  
control, data, and CRC).  
0x5A  
0x5C  
RFTHR  
Hword Received frames threshold. Used to reduce the interrupt overhead that might otherwise  
occur when a series of short HDLC frames arrives, each causing an RXF interrupt. By  
programming RFTHR, the user lowers the frequency of RXF interrupts, which occur only  
when the RFTHR value is reached. Note that the user should provide enough empty  
RxBDs to receive the number of frames speciÞed in RFTHR.  
RFCNT  
HMASK  
Hword Received frames count. A decrementing counter used to implement this feature. Initialize  
this counter with RFTHR.  
0x5E  
0x60  
0x62  
0x64  
0x66  
Hword HMASK and HADDR[1Ð4].The HDLC controller reads the frame address from the HDLC  
receiver, checks it against the four address register values, and masks the result with  
HADDR1 Hword  
HADDR2 Hword  
HADDR3 Hword  
HADDR4 Hword  
HMASK. In HMASK, a 1 represents a bit position for which address comparison should  
occur; 0 represents a masked bit position. When addresses match, the address and  
subsequent data are written into the buffers. When addresses do not match and the  
frame is error-free, the nonmatching address received counter (NMARC) is incremented.  
Note that for 8-bit addresses, mask out (clear) the eight high-order bits in HMASK. The  
eight low-order bits and HADDRx should contain the address byte that immediately  
follows the opening ßag. For example, to recognize a frame that begins 0x7E (ßag), 0x68,  
0xAA, using 16-bit address recognition, HADDRx should contain 0xAA68 and HMASK  
should contain 0xFFFF. See Figure 31-2.  
0x68  
0x6A  
TS_TMP  
Hword Temporary storage  
TMP_MB Hword Temporary storage  
1
2
Offset from FCC base: 0x8400 (FCC1), 0x8500 (FCC2) and 0x8600 (FCC3); see Section 13.5.2, ÒParameter RAM.Ó  
DISFC, CRCEC, ABTSC, and NMARCÑThese 16-bit (modulo 216) counters are maintained by the CP.The user can  
initialize them while the channel is disabled.  
31-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part IV. Communications Processor Module  
Figure 31-2 shows an example of using HMASK and HADDR[1Ð4].  
16-Bit Address Recognition  
8-Bit Address Recognition  
Flag  
0x7E  
Address  
0x68  
Address  
0xAA  
Control  
0x44  
Flag  
0x7E  
Address  
0x55  
Control  
0x44  
etc.  
etc.  
HMASK  
HADDR1  
HADDR2  
HADDR3  
HADDR4  
0xFFFF  
HMASK  
0x00FF  
0xXX55  
0xXX55  
0xXX55  
0xXX55  
0xAA68  
0xFFFF  
0xAA68  
0xAA68  
HADDR1  
HADDR2  
HADDR3  
HADDR4  
Recognizes one 16-bit address (HADDR1) and  
the 16-bit broadcast address (HADDR2)  
Recognizes one 8-bit address (HADDR1)  
Figure 31-2. HDLC Address Recognition Example  
31.5 Programming Model  
The core conÞgures each FCC to operate in the protocol speciÞed in GFMR[MODE]. The  
HDLC controller uses the same data structure as other modes. This data structure supports  
multibuffer operation and address comparisons.  
31.5.1 HDLC Command Set  
The transmit and receive commands are issued to the CPCR; see Section 13.4, ÒCommand  
Set.Ó  
Table 31-2 describes the transmit commands that apply to the HDLC controller.  
Table 31-2. Transmit Commands  
Command  
Description  
STOP  
After the hardware or software is reset and the channel is enabled in the FCC mode register, the  
channel is in transmit enable mode and starts polling the Þrst BD in the table every 256 transmit clocks  
(immediately if TODR[TOD] = 1). STOP TRANSMIT command disables the transmission of frames on the  
transmit channel. If this command is received by the HDLC controller during frame transmission,  
transmission is aborted after a maximum of 64 additional bits are sent and the transmit FIFO buffer is  
ßushed. The TBPTR is not advanced, no new BD is accessed, and no new frames are sent for this  
channel. The transmitter sends an abort sequence consisting of 0x7F (if the command was given  
during frame transmission) and begins sending ßags or idles, as indicated by the HDLC mode register.  
Note that if FPSMR[MFF] = 1, one or more small frames can be ßushed from the transmit FIFO buffer.  
The GRACEFUL STOP TRANSMIT command can be used to avoid this.  
TRANSMIT  
GRACEFUL  
STOP  
Used to stop transmission smoothly rather than abruptly, as performed by the regular STOP TRANSMIT  
command. It stops transmission after the current frame Þnishes sending or immediately if no frame is  
being sent. FCCE[GRA] is set once transmission has stopped. Then the HDLC transmit parameters  
(including BDs) can be modiÞed. The TBPTR points to the next TxBD in the table. Transmission begins  
once the R bit of the next BD is set and the RESTART TRANSMIT command is issued.  
TRANSMIT  
MOTOROLA  
Chapter 31. FCC HDLC Controller  
31-5  
           
Part IV. Communications Processor Module  
Table 31-2. Transmit Commands (Continued)  
Command  
Description  
RESTART  
TRANSMIT  
Enables character transmission on the transmit channel. This command is expected by the HDLC  
controller after a STOP TRANSMIT command, after a STOP TRANSMIT command is issued and the channel  
in its FCC mode register is disabled, after a GRACEFUL STOP TRANSMIT command, or after a transmitter  
error (underrun or CTS lost with no automatic frame retransmission). The HDLC controller resumes  
sending from the current TBPTR in the channel TxBD table.  
INIT TX  
Initializes all transmit parameters in this serial channel parameter RAM to their reset state. This  
PARAMETERS command should only be issued when the transmitter is disabled. Notice that the INIT TX AND RX  
PARAMETERS command can also be used to reset the transmit and receive parameters.  
Table 31-3 describes the receive commands that apply to the HDLC controller.  
Table 31-3. Receive Commands  
Command  
Description  
ENTER HUNT  
MODE  
After the hardware or software is reset and the channel is enabled in the FCC mode register, the  
channel is in receive enable mode and uses the Þrst BD in the table. The ENTER HUNT MODE  
command is generally used to force the HDLC receiver to abort reception of the current frame and  
enter the hunt mode. In hunt mode, the HDLC controller continually scans the input data stream for  
the ßag sequence. After receiving the command, the current receive buffer is closed and the CRC is  
reset. Further frame reception uses the next BD.  
INIT RX  
Initializes all the receive parameters in this serial channel parameter RAM to their reset state and  
should be issued only when the receiver is disabled. Notice that the INIT TX AND RX PARAMETERS  
command resets both receive and transmit parameters.  
PARAMETERS  
31.5.2 HDLC Error Handling  
The HDLC controller reports frame reception and transmission error conditions using the  
channel BDs, error counters, and HDLC event register (FCCE). Table 31-4 describes  
HDLC transmission errors, which are reported through the TxBD.  
Table 31-4. HDLC Transmission Errors  
Error  
Description  
Transmitter  
Underrun  
When this error occurs, the channel terminates buffer transmission, closes the buffer, sets the  
underrun (U) bit in the BD, and generates the TXE interrupt if it is enabled. The channel resumes  
transmission after receiving the RESTART TRANSMIT command.  
CTS Lost  
When this error occurs, the channel terminates buffer transmission, closes the buffer, sets TxBD[CT],  
during Frame and generates a TXE interrupt (if it is enabled). The channel resumes transmission after receiving  
Transmission the RESTART TRANSMIT command.  
31-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
           
Part IV. Communications Processor Module  
Table 31-5 describes HDLC reception errors, which are reported through the RxBD.  
Table 31-5. HDLC Reception Errors  
Error  
Description  
Overrun Error The HDLC controller maintains an internal FIFO buffer for receiving data. The CP begins  
programming the SDMA channel and updating the CRC whenever data is received in the FIFO buffer.  
When a receive FIFO overrun occurs, the channel writes the received data byte to the internal FIFO  
buffer over the previously received byte. The previous byte and the frame status are lost. The channel  
closes the buffer with RxBD[OV] set and generates the RXF interrupt if it is enabled.The receiver then  
enters hunt mode. Even if the overrun occurs during a frame whose address is not matched in the  
address recognition logic, an RxBD with data length two is opened to report the overrun and the RXF  
interrupt is generated if it is enabled.  
CD Lost  
When this error occurs, the channel terminates frame reception, closes the buffer, sets RxBD[CD],  
During Frame and generates the RXF interrupt if it is enabled. This error has highest priority. The rest of the frame is  
Reception  
lost and other errors are not checked in that frame. At this point, the receiver enters hunt mode.  
Abort  
Sequence  
The HDLC controller detects an abort sequence when seven or more consecutive ones are received.  
When this error occurs and the HDLC controller receives a frame, the channel closes the buffer by  
setting RxBD[AB] and generates the RXF interrupt (if enabled).The channel also increments the abort  
sequence counter. The CRC and nonoctet error status conditions are not checked on aborted frames.  
The receiver then enters hunt mode. When an abort sequence is received, the user is given no  
indication that an HDLC controller is not currently receiving a frame.  
Nonoctet  
When this error occurs, the channel writes the received data to the data buffer, closes the buffer, sets  
Aligned Frame the Rx nonoctet aligned frame bit RxBD[NO], and generates the RXF interrupt (if it is enabled). The  
CRC error status should be disregarded on nonoctet frames. After a nonoctet aligned frame is  
received, the receiver enters hunt mode. An immediate back-to-back frame is still received. The  
nonoctet data portion may be derived from the last byte in the buffer by Þnding the least-signiÞcant set  
bit, which marks the end of valid data as follows:  
msb  
lsb  
0
Valid data  
1
0
0
CRC Error  
When this error occurs, the channel writes the received CRC to the data buffer, closes the buffer, sets  
RxBD[CR], and generates the RXF interrupt (if it is enabled). The channel also increments the CRC  
error counter. After receiving a frame with a CRC error, the receiver enters hunt mode. An immediate  
back-to-back frame is still received. CRC checking cannot be disabled, but the CRC error can be  
ignored if checking is not required.  
31.6 HDLC Mode Register (FPSMR)  
When an FCC is conÞgured for HDLC mode, the FPSMR is used as the HDLC mode  
register, shown in Figure 31-3.  
MOTOROLA  
Chapter 31. FCC HDLC Controller  
31-7  
         
Part IV. Communications Processor Module  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
NOF  
FSE MFF  
Ñ
TS  
Ñ
0000_0000_0000_0000  
R/W  
Addr  
Bits  
0x11304 (FPSMR1), 0x11324 (FPSMR2), 0x11324 (FPSMR3)  
16  
17  
18  
19  
20  
Ñ
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field  
Reset  
R/W  
NBL  
CRC  
Ñ
0000_0000_0000_0000  
R/W  
Addr  
0x11306 (FPSMR1), 0x11326 (FPSMR2), 0x11326 (FPSMR3)  
Figure 31-3. HDLC Mode Register (FPSMR)  
The FPSMR Þelds are described in Table 31-6.  
Table 31-6. FPSMR Field Descriptions  
Bits Name  
Description  
0Ð3  
4
NOF Number of ßags. Minimum number of ßags between or before frames (0Ð15 ßags). If NOF = 0000, no  
ßags are inserted between the frames. Thus, for back-to-back frames, the closing ßag of one frame is  
immediately followed by the opening ßag of the next frame.  
FSE Flag sharing enable. This bit is valid only if GFMR[RTSM] is set.  
0
1
Normal operation  
If NOF = 0000, a single shared ßag is transmitted between back-to-back frames. Other values of  
NOF are decremented by 1 when FSE is set. This is useful in signaling system #7 applications.  
5
MFF Multiple Frames in FIFO  
0
Normal operation. The transmit FIFO buffer must never contain more than one HDLC frame. The  
CTS lost status is reported accurately on a per-frame basis. The receiver is not affected by this bit.  
The transmit FIFO buffer can contain multiple frames, but lost CTS is not guaranteed to be  
reported on the exact buffer/frame it occurred on. This option, however, can improve the  
performance of HDLC transmissions for small back-to-back frames or if the user prefers to  
strongly limit the number of ßags sent between frames. MFF does not affect the receiver.  
1
7Ð8  
9
Ñ
Reserved, should be cleared.  
TS Time stamp  
0
1
Normal operation.  
A 32-bit time stamp is added at the beginning of the receive BD data buffer, thus the buffer pointer  
must be (32-byte aligned - 4). The BDÕs data length does not include the time stamp. See  
Section 13.3.7, ÒRISC Time-Stamp Control Register (RTSCR).Ó  
10Ð15  
16  
Ñ
Reserved, should be cleared.  
NBL 0 nibble mode disabled (1 bit of data per clock).  
1 nibble mode (4 bits of data per clock).  
17Ð23  
Ñ
Reserved, should be cleared.  
31-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
Table 31-6. FPSMR Field Descriptions (Continued)  
Bits Name  
Description  
24-25 CRC CRC selection  
00 16-bit CCITT-CRC (HDLC). X16 + X12 + X5 + 1  
01 Reserved  
10 32-bit CCITT-CRC (Ethernet and HDLC). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8  
+ X7 + X5 + X4 + X2 + X1 +1  
11 Reserved  
26Ð31  
Ñ
Reserved, should be cleared.  
31.7 HDLC Receive Buffer Descriptor (RxBD)  
The HDLC controller uses the RxBD to report on data received for each buffer. Figure 31-4  
shows an example of the RxBD process.  
MOTOROLA  
Chapter 31. FCC HDLC Controller  
31-9  
   
Part IV. Communications Processor Module  
MRBLR = 32 Bytes for this FCC  
Buffer  
RxBD 0  
E
0
L
0
F
1
Status  
Length  
Address 1  
Address 2  
0x0020  
Buffer Full  
Pointer  
32-Bit Buffer Pointer  
32 Bytes  
Control Byte  
29  
Information  
(I-Field) Bytes  
RxBD 1  
Buffer  
E
0
L
1
F
0
Status  
Length  
Last I-Field Byte  
CRC Byte 1  
CRC Byte 2  
0x0023  
Buffer Closed  
When Closing Flag  
Received  
Pointer  
32-Bit Buffer Pointer  
32 Bytes  
Empty  
RxBD 2  
Buffer  
E
0
L
1
F
1
AB  
1
Status  
Length  
Address 1  
Address 2  
Control Byte  
0x0003  
32 Bytes  
Abort was  
Received after  
Control Byte  
Pointer  
32-Bit Buffer Pointer  
RxBD 3  
Empty  
Buffer  
E
1
Status  
Length  
XXXX  
32 Bytes  
Empty  
Buffer  
Still Empty  
Pointer  
32-Bit Buffer Pointer  
Stored in Rx Buffer  
Stored in Rx Buffer  
. . .  
F
A
A
C
I
I
I
CR CR  
F
Line Idle  
F
A
A
C
Abort/Idle  
Two Frames  
Received in HDLC  
Unexpected Abort Present  
Time  
Occurs before  
Closing Flag  
Time  
Legend:  
F = Flag  
A = Address Byte  
C = Control Byte  
I = Information Byte  
CR = CRC Byte  
Figure 31-4. FCC HDLC Receiving Using RxBDs  
31-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part IV. Communications Processor Module  
Figure 31-5 shows the FCC HDLC RxBD.  
0
1
2
3
4
L
5
F
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
E
Ñ
W
I
CM  
Ñ
LG  
NO  
AB  
CR  
OV  
CD  
Data Length  
Rx Data Buffer Pointer  
Figure 31-5. FCC HDLC Receive Buffer Descriptor (RxBD)  
Table 31-7 describes RxBD Þelds.  
Table 31-7. RxBD field Descriptions  
Bits Name  
Description  
0
E
Empty  
0
The buffer is full with received data or data reception stopped because of an error. The core can  
read or write to any Þelds of this RxBD. The CP does not use this BD while E = 0.  
The buffer associated with this BD is empty. This RxBD and its associated receive buffer are  
owned by the CP. Once E is set, the core should not write any Þelds of this RxBD.  
1
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (Þnal BD in table)  
0
1
Not the last BD in the RxBD table.  
Last BD in the RxBD table. After this buffer is used, the CP receives incoming data into the Þrst  
BD that RBASE points to in the table. The number of RxBDs in this table is programmable and is  
determined only by the W bit and the overall space constraints of the dual-port RAM.  
The RxBD table must contain more than one BD in HDLC mode.  
3
4
I
Interrupt  
0
1
The RXB bit is not set after this buffer is used, but RXF operation remains unaffected.  
FCCE[RXB] or FCCE[RXF] is set when the HDLC controller uses this buffer. These two bits can  
cause interrupts if they are enabled.  
L
Last in frame. Set by the HDLC controller when this buffer is the last one in a frame. This implies the  
reception of a closing ßag or reception of an error, in which case one or more of the CD, OV, AB, and  
LG bits are set. The HDLC controller writes the number of frame octets to the data length Þeld.  
0
1
Not the last buffer in a frame.  
Last buffer in a frame.  
5
6
F
First in frame. Set by the HDLC controller when this buffer is the Þrst in a frame.  
0
1
Not the Þrst buffer in a frame.  
First buffer in a frame.  
CM Continuous mode  
0
1
Normal operation.  
The E bit is not cleared by the CP after this BD is closed, allowing the associated data buffer to be  
automatically overwritten the next time the CP accesses this BD. However, the E bit is cleared if  
an error occurs during reception, regardless of the CM bit.  
7Ð9  
10  
Ñ
Reserved, should be cleared.  
LG Rx frame length violation. A frame length greater than the maximum deÞned for this channel is  
recognized, and only the maximum-allowed number of bytes (MFLR) is written to the data buffer.This  
event is not reported until the RxBD is closed, the RXF bit is set, and the closing ßag is received.The  
number of bytes received between ßags is written to the data length Þeld of this BD.  
MOTOROLA  
Chapter 31. FCC HDLC Controller  
31-11  
   
Part IV. Communications Processor Module  
Table 31-7. RxBD field Descriptions (Continued)  
Bits Name  
Description  
11  
NO Rx nonoctet-aligned frame. Set when a received frame contains a number of bits not divisible by  
eight.  
12  
13  
AB Rx abort sequence. At least seven consecutive 1s are received during frame reception.  
CR Rx CRC error. This frame contains a CRC error. Received CRC bytes are written to the receive  
buffer.  
14  
15  
OV Overrun. A receiver overrun occurs during frame reception.  
CD Carrier detect lost. CD has negated during frame reception. This bit is valid only for NMSI mode.  
The RxBD status bits are written by the HDLC controller after receiving the associated data  
buffer.  
The remaining RxBD parameters are as follows:  
¥
Data length is the number of octets the CP writes into this BDÕs data buffer. It is  
written by the CP once the BD is closed. When this is the last BD in the frame (L =  
1), this Þeld contains the total number of frame octets, including 2 or 4 bytes for  
CRC. The memory allocated for this buffer should be no smaller than the MRBLR  
value.  
¥
Rx data buffer pointer. The receive buffer pointer, which always points to the Þrst  
location of the associated data buffer, resides in internal or external memory and  
must be divisible by 32 unless FPSMR[TS] = 1 (see Table 31-6).  
31.8 HDLC Transmit Buffer Descriptor (TxBD)  
Data is presented to the HDLC controller for transmission on an FCC channel by arranging  
it in buffers referenced by the channel TxBD table. The HDLC controller conÞrms  
transmission (or indicates errors) using the BDs to inform the core that the buffers have  
been serviced. Figure 31-6 shows the FCC HDLC TxBD.  
0
1
2
3
4
5
6
7
8
9
10  
Ñ
11  
12  
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
R
Ñ
W
I
L
TC  
CM  
UN  
CT  
Data Length  
Tx Data Buffer Pointer  
Figure 31-6. FCC HDLC Transmit Buffer Descriptor (TxBD)  
31-12  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part IV. Communications Processor Module  
Table 31-8 describes HDLC TxBD Þelds.  
Table 31-8. HDLC TxBD Field Descriptions  
Bits  
Name  
R
Description  
0
Ready  
0
The buffer associated with this BD is not ready for transmission. The user can manipulate this  
BD or its associated buffer. The CP clears R after the buffer has been sent or an error occurs.  
The buffer is ready to be sent.The transmission may have begun, but it has not completed.The  
user cannot set Þelds in this BD once R is set.  
1
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (Þnal BD in table)  
0
1
Not the last BD in the TxBD table.  
Last BD in the TxBD table. After this buffer has been used, the CP sends data from the Þrst BD  
that TBASE points to in the table. The number of TxBDs in this table is determined only by the  
W bit and the overall space constraints of the dual-port RAM.  
3
I
Interrupt  
0
1
No interrupt is generated after this buffer is serviced.  
Either FCCE[TXB] or FCCE[TXE] is set when this buffer is serviced by the HDLC controller.  
These bits can cause interrupts if they are enabled.  
4
5
L
Last  
0
1
Not the last buffer in the frame.  
Last buffer in the current frame.  
TC  
Tx CRC.Valid only when the L bit is set. Otherwise, it is ignored.  
0
Transmit the closing ßag after the last data byte. This setting can be used to send a bad CRC  
after the data for testing purposes.  
Transmit the CRC sequence after the last data byte.  
1
6
CM  
Continuous mode  
0
1
Normal operation.  
The R bit is not cleared by the CP after this BD is closed, allowing the buffer to be retransmitted  
automatically the next time the CP accesses this BD. However, the R bit is cleared if an error  
occurs during transmission, regardless of the CM bit.  
7Ð13  
14  
Ñ
Reserved, should be cleared.  
UN  
Underrun. The HDLC controller encounters a transmitter underrun condition while sending the  
buffer. The HDLC controller writes UN after sending the buffer.  
15  
CT  
CTS lost. Set when CTS is lost during frame transmission in NMSI mode. If data from more than  
one buffer is in the FIFO buffer when this error occurs, CT is set in the currently open TxBD. The  
HDLC controller writes CT after sending the buffer.  
The TxBD status bits are written by the HDLC controller after sending the associated data  
buffer.  
MOTOROLA  
Chapter 31. FCC HDLC Controller  
31-13  
 
Part IV. Communications Processor Module  
The remaining TxBD parameters are as follows:  
¥
Data length is the number of bytes the HDLC controller should transmit from this  
data buffer; it is never modiÞed by the CP. The value of this Þeld should be greater  
than zero.  
¥
Tx data buffer pointer. The transmit buffer pointer, which contains the address of the  
associated data buffer, can be even or odd. The buffer can reside in internal or  
external memory. This value is never modiÞed by the CP.  
31.9 HDLC Event Register (FCCE)/Mask Register  
(FCCM)  
The FCCE is used as the HDLC event register when the FCC operates as an HDLC  
controller. The FCCE reports events recognized by the HDLC channel and generates  
interrupts. On recognition of an event, the HDLC controller sets the corresponding FCCE  
bit. FCCE bits are cleared by writing ones; writing zeros does not affect bit values. All  
unmasked bits must be cleared before the CP clears the internal interrupt request.  
Interrupts generated by the FCCE can be masked in the HDLC mask register (FCCM),  
which has the same bit format as FCCE. If an FCCM bit = 1, the corresponding interrupt  
in the event register is enabled. If the bit is 0, the interrupt is masked.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10 11  
12  
13  
14  
15  
Ñ
GRA  
Ñ TXE RXF BSY TXB RXB  
0000_0000_0000_0000  
R/W  
Addr  
0x11310 (FCCE1), 0x11330 (FCCE2), 0x11350 (FCCE3)/  
0x11314 (FCCM1), 0x11334 (FCCM2), 0x11354 (FCCM3)  
Bits  
Field  
Reset  
R/W  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25 26 27  
28  
29  
30  
31  
Ñ
FLG  
IDL  
Ñ
0000_0000_0000_0000  
R/W  
Addr  
0x11312 (FCCE1), 0x11332 (FCCE2), 0x11352 (FCCE3)/  
0x11316 (FCCM1), 0x11336 (FCCM2), 0x11356 (FCCM3)  
Figure 31-7. HDLC Event Register (FCCE)/Mask Register (FCCM)  
Table 31-9 describes FCCE/FCCM Þelds.  
31-14  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part IV. Communications Processor Module  
Table 31-9. FCCE/FCCM Field Descriptions  
Bits  
Name  
Description  
0Ð7  
8
Ñ
Reserved, should be cleared.  
GRA Graceful stop complete. A graceful stop, which was initiated by the GRACEFUL STOP TRANSMIT  
command, is now complete. GRA is set as soon as the transmitter Þnishes transmitting any frame  
that is in progress when the command was issued. It is set immediately if no frame is in progress  
when the command is issued.  
9Ð10  
11  
Ñ
Reserved, should be cleared.  
TXE  
RXF  
Tx error. An error (CTS lost or underrun) occurs on the transmitter channel.  
12  
Rx frame. A complete frame is received on the HDLC channel. This bit is set no sooner than two  
clocks after receipt of the last bit of the closing ßag.  
13  
14  
BSY  
TXB  
Busy condition. A frame is received and discarded due to a lack of buffers.  
Transmit buffer. A buffer is sent on the HDLC channel. TXB is set no sooner than when the last bit  
of the closing ßag begins its transmission if the buffer is the last one in the frame. Otherwise, TXB  
is set after the last byte of the buffer is written to the transmit FIFO buffer.  
15  
16Ð21  
22  
RXB Receive buffer. A buffer that is not a complete frame is received on the HDLC channel.  
Ñ
Reserved, should be cleared.  
FLG  
Flag status changed. The HDLC controller stops or starts receiving HDLC ßags. The real-time  
status can be obtained in FCCS; see Section 31.10, ÒFCC Status Register (FCCS).Ó  
23  
IDL  
Ñ
Idle sequence status changed. A change in the status of the serial line is detected on the HDLC  
line. The real-time status can be read in FCCS; see Section 31.10, ÒFCC Status Register (FCCS).Ó  
24Ð31  
Reserved, should be cleared.  
Figure 31-8 shows interrupts that can be generated in the HDLC protocol.  
MOTOROLA  
Chapter 31. FCC HDLC Controller  
31-15  
 
Part IV. Communications Processor Module  
Frame  
Received by HDLC  
Stored in Rx Buffer  
Time  
F
F
A
A
C
I
I
I
CR CR  
F
RXD  
CD  
Line Idle  
Line Idle  
HDLC FCCE  
Events  
CD  
IDL FLG  
FLG  
RXB  
RXF FLG IDL  
FLG  
CD  
Notes:  
1. RXB event assumes receive buffers are 6 bytes each.  
2. The second IDL event occurs after 15 ones are received in a row.  
3. The FLG interrupts show the beginning and end of flag reception.  
4. The FLG interrupt at the end of the frame may precede the RXF interrupt due to receive FIFO latency.  
5. The CD event must be programmed in the parallel I/O port, not in the FCC itself.  
6. F = flag, A = address byte, C = control byte, I = information byte, and CR = CRC byte  
Stored in Tx Buffer  
Frame  
Transmitted by HDLC  
TXD  
RTS  
CTS  
Line Idle  
F
F
A
A
C
CR CR  
F
Line Idle  
HDLC FCCE  
Events  
CT  
TXB  
CT  
Notes:  
1. TXB event shown assumes all three bytes were put into a single buffer.  
2. Example shows one additional opening flag. This is programmable.  
3. The CT event must be programmed in the parallel I/O port, not in the FCC itself.  
Figure 31-8. HDLC Interrupt Event Example  
31.10 FCC Status Register (FCCS)  
The FCCS register, shown in Figure 31-9, allows the user to monitor real-time status  
conditions on the RXD line. The real-time status of the CTS and CD signals are part of the  
parallel I/O port; see Chapter 35, ÒParallel I/O Ports.Ó  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
Ñ
FG  
Ñ
ID  
0000_0000  
R
Addr  
0x11318 (FCCS1), 0x11338 (FCCS2), 0x11358 (FCCS3)  
Figure 31-9. FCC Status Register (FCCS)  
31-16  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part IV. Communications Processor Module  
Table 31-10 describes FCCS bits.  
Table 31-10. FCCS Register Field Descriptions  
Bits Name  
Description  
0Ð4  
5
Ñ
Reserved, should be cleared.  
FG  
Flags. While FG is cleared, each time a new bit is received the most recently received 8 bits are  
examined to see if a ßag is present. FG is set as soon as an HDLC ßag (0x7E) is received on the line.  
Once FG is set, it remains set at least 8 bit times while the next 8 bits of input data are examined. If  
another ßag occurs, FG stays set for at least another eight bits. Otherwise, FG is cleared and the  
search begins again.  
0
1
HDLC ßags are not currently being received.  
HDLC ßags are currently being received.  
6
7
Ñ
ID  
Reserved, should be cleared.  
Idle status. ID is set when the RXD signal is a logic one for 15 or more consecutive bit times; it is  
cleared after a logic zero is received.  
0
1
The line is busy.  
The line is idle.  
MOTOROLA  
Chapter 31. FCC HDLC Controller  
31-17  
 
Part IV. Communications Processor Module  
31-18  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Chapter 32  
FCC Transparent Controller  
320  
3T20 he FCC transparent controller functions as a high-speed serial-to-parallel and parallel-to-  
serial converter. Transparent mode provides a clear channel on which the FCC performs no  
bit-level manipulationÑimplementing higher-level protocols would require software.  
Transparent mode is also referred to as a totally transparent or promiscuous operation.  
Basic applications for an FCC in transparent mode include the following:  
¥
¥
For data, such as voice, moving serially without the need for protocol processing  
For board-level applications, such as chip-to-chip communications, requiring a  
serial-to-parallel and parallel-to-serial conversion  
¥
For applications requiring the switching of data paths without altering the protocol  
encoding itself, such as a multiplexer in which data from a high-speed TDM serial  
stream is divided into multiple low-speed data streams  
An FCC transmitter and receiver can be programmed in transparent mode independently.  
Setting GFMRx[TTx] enables the transparent transmitter; setting GFMRx[TRx] enables  
the transparent receiver. Both bits must be set for full-duplex transparent operation. If only  
one bit is set, the other half of the FCC operates with the protocol programmed in  
GFMRx[MODE]. This allows loopback modes to transfer data from one memory location  
to another (using DMA) while the data is converted to a speciÞc serial format. However,  
the Ethernet and ATM controllers cannot be split in this way. See Section 28.2, ÒGeneral  
FCC Mode Registers (GFMRx).Ó  
The FCC in transparent mode can work with the TSA or NMSI and support modem lines  
using the general-purpose I/O signals. The data can be transmitted and received with msb  
or lsb Þrst in each octet. The FCC consists of separate transmit and receive sections whose  
operations are asynchronous with the core and can either be synchronous or asynchronous  
with respect to the other FCCs. Each clock can be supplied from the internal BRG bank or  
external signals.  
MOTOROLA  
Chapter 32. FCCTransparent Controller  
32-1  
       
Part IV. Communications Processor Module  
32.1 Features  
The following is a list of the transparent controllerÕs important features:  
¥
¥
Flexible data buffers  
Automatic SYNC detection on receive  
Ñ 16-bit pattern  
Ñ 8-bit pattern  
Ñ Automatic sync (always synchronized)  
Ñ External sync signal support  
¥
¥
¥
CRCs can optionally be transmitted and received  
Reverse data mode  
Another protocol can be performed on the FCCÕs other half (transmitter or receiver)  
during transparent mode  
¥
External BD table  
32.2 Transparent Channel Operation  
The transparent transmitter and receiver operates in the same way as the HDLC controller  
of the FCC (see Chapter 31, ÒFCC HDLC ControllerÓ) except in the following ways:  
1. The FPSMR does not affect the transparent controller, only the GFMR does.  
2. In Table 31-1, MFLR, HMASK, RFTHR, and RFCNT must be cleared for proper  
operation of the transparent receiver.  
3. Transmitter synchronization has to be achieved using CTS before the transmitter  
begins sending; see Section 32.3, ÒAchieving Synchronization in Transparent  
Mode.Ó  
32.3 Achieving Synchronization in Transparent Mode  
Once the FCC transmitter is enabled for transparent operation in the GFMR, the TxBD is  
prepared for the FCC, and the transmit FIFO is preloaded by the SDMA channel, another  
process must occur before data can be transmitted. It is called transmit synchronization.  
Similarly, once the FCC receiver is enabled for transparent operation in the GFMR and the  
RxBD is made empty for the FCC, receive synchronization must occur before data can be  
received. The synchronization process gives the user bit-level control of when the  
transmission and reception begins. The methods for this are as follows:  
¥
¥
¥
An in-line synchronization pattern  
External synchronization signals  
Automatic sync  
32-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
           
Part IV. Communications Processor Module  
32.3.1 In-Line Synchronization Pattern  
The transparent channel can be programmed to transmit and receive a synchronization  
pattern if GFMR[SYNL] ¹ 0; see Section 28.2, ÒGeneral FCC Mode Registers (GFMRx).Ó  
The pattern is deÞned in the FDSR; see Section 28.4, ÒFCC Data Synchronization Registers  
(FDSRx).Ó GFMR[SYNL] deÞnes the SYNC pattern length. The synchronization pattern  
is shown in Figure 32-1.  
Bits  
Field  
Field  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
8-Bit Sync Pattern  
Ñ
16-Bit Sync Pattern  
Figure 32-1. In-Line Synchronization Pattern  
The receiver synchronizes on the synchronization pattern located in the FDSR. For  
instance, if an 8-bit SYNC is selected, reception begins as soon as these eight bits are  
received, beginning with the Þrst bit following the 8-bit SYNC. This effectively links the  
transmitter synchronization to the receiver synchronization.  
32.3.2 External Synchronization Signals  
If GFMR[SYNL] = 00, an external signal is used to begin the sequence. CTS is used for the  
transmitter and CD is used for the receiver; these signals share the following sampling  
options.  
¥
The pulse option determines whether CD or CTS need to only be asserted once to  
begin reception/transmission or whether they must be asserted and stay that way for  
the duration of the transparent frame. This is controlled by the CDP and CTSP bits  
of the GFMR. If the user expects a continuous stream of data without interruption,  
then the pulse operation should be used. However, if the user is trying to identify  
frames of transparent data, the envelope mode of the these signals should be used.  
¥
The sampling option determines the delay between CD and CTS being asserted and  
the resulting action by the FCC. These signals can be assumed to be asynchronous  
to the data and then internally synchronized by the FCC, or they can be assumed to  
be synchronous to the data giving faster operation. This option allows the RTS of one  
FCC to be connected to the CD of another FCC (on another MPC8260) and to have  
the data synchronized and bit aligned. It is also an option to link the transmitter  
synchronization to the receiver synchronization.  
Diagrams for the pulse/envelope and sampling options are in Section 28.11, ÒFCC Timing  
Control.Ó  
MOTOROLA  
Chapter 32. FCCTransparent Controller  
32-3  
           
Part IV. Communications Processor Module  
32.3.3 Transparent Synchronization Example  
Figure 32-2 shows an example of synchronization using external signals.  
MPC8260 A  
MPC8260 B  
TXD  
RXD  
RTS  
BRGOx  
RXD  
CD  
CLKx  
TXD  
CD  
RTS  
CLKx  
BRGOx  
BRGOx  
(Output is CLKx Input)  
TXD  
(Output is RXD Input)  
Last Bit of Frame Data  
or CRC  
First Bit of Frame Data  
RTS  
(Output is CD Input)  
TxBD[L] = 1 Causes Negation of RTS  
CD Lost Condition Terminates Reception of Frame  
Notes:  
1. Each MPC8260 generates its own transmit clocks. If the transmit and receive clocks are the same, one can  
generate transmit and receive clocks for the other MPC8260. For example, CLKx on MPC8260 (B) could be used to  
clock the transmitter and receiver.  
2. CTS should be conÞgured as always asserted in the parallel I/O port or connected to ground externally.  
3. The required GSMR conÞgurations are DIAG= 00, CTSS=1, CTSP is a donÕt care, CDS=1, CDP=0, TTX=1, and  
TRX=1. REVD and TCRC are application-dependent.  
4. The transparent frame contains a CRC if TxBD[TC] is set.  
Figure 32-2. Sending Transparent Frames between MPC8260s  
MPC8260(A) and MPC8260(B) exchange transparent frames and synchronize each other  
using RTS and CD. However, CTS is not required because transmission begins at any time.  
Thus, RTS is connected directly to the other MPC8260Õs CD. GFMR[SYNL] is not used  
and transmission and reception from each MPC8260 are independent.  
32-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Chapter 33  
Serial Peripheral Interface (SPI)  
330  
3T30 he serial peripheral interface (SPI) allows the MPC8260 to exchange data between other  
MPC8260 chips, the MPC860, the MC68360, the MC68302, the M68HC11 and M68HC05  
microcontroller families, and peripheral devices such as EEPROMs, real-time clocks, A/D  
converters, and ISDN devices.  
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire  
interface (receive, transmit, clock and slave select). The SPI block consists of transmitter  
and receiver sections, an independent baud-rate generator, and a control unit. The  
transmitter and receiver sections use the same clock, which is derived from the SPI baud  
rate generator in master mode and generated externally in slave mode. During an SPI  
transfer, data is sent and received simultaneously.  
Because the SPI receiver and transmitter are double-buffered, as shown in Figure 33-1, the  
effective FIFO size (latency) is 2 characters. The SPIÕs msb is shifted out Þrst. When the  
SPI is disabled in the SPI mode register (SPMODE[EN] = 0), it consumes little power.  
60x Bus  
Peripheral Bus  
SPI Mode Register  
Transmit_Register  
Receive_Register  
Counter  
Shift_Register  
TxD  
RxD  
IN_CLK  
Pins Interface  
SPIBRG  
BRGCLK  
SPISEL  
SPIMOSI  
SPIMISO  
SPICLK  
Figure 33-1. SPI Block Diagram  
MOTOROLA  
Chapter 33. Serial Peripheral Interface (SPI)  
33-1  
       
Part IV. Communications Processor Module  
33.1 Features  
The following is a list of the SPIÕs main features:  
¥
Four-signal interface (SPIMOSI, SPIMISO, SPICLK, and SPISEL) multiplexed  
with Port B signals  
¥
¥
¥
¥
¥
¥
¥
Full-duplex operation  
Works with data characters from 4 to 16 bits long  
Supports back-to-back character transmission and reception  
Master or slave SPI modes supported  
Multimaster environment support  
Continuous transfer mode for automatic scanning of a peripheral  
Supports maximum clock rates of 25 in master mode and 50 MHz in slave mode,  
assuming a 100-MHz system clock  
¥
¥
¥
¥
Independent programmable baud rate generator  
Programmable clock phase and polarity  
Open-drain outputs support multimaster conÞguration  
Local loopback capability for testing  
33.2 SPI Clocking and Signal Functions  
The SPI can be conÞgured as a slave or as a master in single- or multiple-master  
environments. The master SPI generates the transfer clock SPICLK using the SPI baud rate  
generator (BRG). The SPI BRG takes its input from BRGCLK, which is generated in the  
MPC8260 clock synthesizer.  
SPICLK is a gated clock, active only during data transfers. Four combinations of SPICLK  
phase and polarity can be conÞgured with SPMODE[CI, CP]. SPI signals can also be  
conÞgured as open-drain to support a multimaster conÞguration in which a shared SPI  
signal is driven by the MPC8260 or an external SPI device.  
The SPI master-in slave-out SPIMISO signal acts as an input for master devices and as an  
output for slave devices. Conversely, the master-out slave-in SPIMOSI signal is an output  
for master devices and an input for slave devices. The dual functionality of these signals  
allows the SPIs in a multimaster environment to communicate with one another using a  
common hardware conÞguration.  
¥
When the SPI is a master, SPICLK is the clock output signal that shifts received data  
in from SPIMISO and transmitted data out to SPIMOSI. SPI masters must output a  
slave select signal to enable SPI slave devices by using a separate general-purpose  
I/O signal. Assertion of an SPIÕs SPISEL while it is master causes an error.  
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Part IV. Communications Processor Module  
¥
When the SPI is a slave, SPICLK is the clock input that shifts received data in from  
SPIMOSI and transmitted data out through SPIMISO. SPISEL is the enable input to  
the SPI slave. In a multimaster environment, SPISEL (always an input) is used to  
detect an error when more than one master is operating.  
As described in Chapter 35, ÒParallel I/O Ports,Ó SPIMISO, SPIMOSI, SPICLK, and  
SPISEL are multiplexed with port B[28Ð31] signals, respectively. They are conÞgured as  
SPI signals through the port B signal assignment register (PBPAR) and the Port B data  
direction register (PBDIR), speciÞcally by setting PBPAR[DDn] and PBDIR[DRn].  
33.3 ConÞguring the SPI Controller  
The SPI can be programmed to work in a single- or multiple-master environment. This  
section describes SPI master and slave operation in a single-master conÞguration and then  
discusses the multi-master environment.  
33.3.1 The SPI as a Master Device  
In master mode, the SPI sends a message to the slave peripheral, which sends back a  
simultaneous reply. A single master MPC8260 with multiple slaves can use general-  
purpose parallel I/O signals to selectively enable slaves, as shown in Figure 33-2. To  
eliminate the multimaster error in a single-master environment, the masterÕs SPISEL input  
can be forced inactive by selecting port B[31] for general-purpose I/O  
(PBPAR[DD31] = 0).  
MPC8260  
Slave 0  
SPIMOSI  
SPIMISO  
SPICLK  
SPIMOSI  
SPIMISO  
SPICLK  
SPISEL  
Master SPI  
Slave 1  
SPIMOSI  
SPIMISO  
SPICLK  
SPISEL  
The SPISEL  
decoder can be  
either internal or  
external logic.  
Slave 2  
SPIMOSI  
SPIMISO  
SPICLK  
SPISEL  
Figure 33-2. Single-Master/Multi-Slave Configuration  
MOTOROLA  
Chapter 33. Serial Peripheral Interface (SPI)  
33-3  
         
Part IV. Communications Processor Module  
To start exchanging data, the core writes the data to be sent into a buffer, conÞgures a TxBD  
with TxBD[R] set, and conÞgures one or more RxBDs. The core then sets SPCOM[STR]  
in the SPI command register to start sending data, which starts once the SDMA channel  
loads the Tx FIFO with data.  
The SPI then generates programmable clock pulses on SPICLK for each character and  
simultaneously shifts Tx data out on SPIMOSI and Rx data in on SPIMISO. Received data  
is written into a Rx buffer using the next available RxBD. The SPI keeps sending and  
receiving characters until the whole buffer is sent or an error occurs. The CP then clears  
TxBD[R] and RxBD[E] and issues a maskable interrupt to the interrupt controller in the  
SIU.  
When multiple TxBDs are ready, TxBD[L] determines whether the SPI keeps transmitting  
without SPCOM[STR] being set again. If the current TxBD[L] is cleared, the next TxBD  
is processed after data from the current buffer is sent. Typically there is no delay on  
SPIMOSI between buffers. If the current TxBD[L] is set, sending stops after the current  
buffer is sent. In addition, the RxBD is closed after transmission stops, even if the Rx buffer  
is not full; therefore, Rx buffers need not be the same length as Tx buffers.  
33.3.2 The SPI as a Slave Device  
In slave mode, the SPI receives messages from an SPI master and sends a simultaneous  
reply. The slaveÕs SPISEL must be asserted before Rx clocks are recognized; once SPISEL  
is asserted, SPICLK becomes an input from the master to the slave. SPICLK can be any  
frequency from DC to BRGCLK/2 (12.5 MHz for a 25-MHz system).  
To prepare for data transfers, the slaveÕs core writes data to be sent into a buffer, conÞgures  
a TxBD with TxBD[R] set, and conÞgures one or more RxBDs. The core then sets  
SPCOM[STR] to activate the SPI. Once SPISEL is asserted, the slave shifts data out from  
SPIMISO and in through SPIMOSI. A maskable interrupt is issued when a full buffer  
Þnishes receiving and sending or after an error. The SPI uses successive RxBDs in the table  
to continue reception until it runs out of Rx buffers or SPISEL is negated.  
Transmission continues until no more data is available or SPISEL is negated. If it is negated  
before all data is sent, it stops but the TxBD stays open. Transmission continues once  
SPISEL is reasserted and SPICLK begins toggling. After the characters in the buffer are  
sent, the SPI sends ones as long as SPISEL remains asserted.  
33.3.3 The SPI in Multimaster Operation  
The SPI can operate in a multimaster environment in which SPI devices are connected to  
the same bus. In this conÞguration, the SPIMOSI, SPIMISO, and SPICLK signals of all  
SPIs are shared; the SPISEL inputs are connected separately, as shown in Figure 33-3. Only  
one SPI device can act as master at a timeÑall others must be slaves. When an SPI is  
conÞgured as a master and its SPISEL input is asserted, a multimaster error occurs because  
more than one SPI device is a bus master. The SPI sets SPIE[MME] in the SPI event register  
and a maskable interrupt is issued to the core. It also disables SPI operation and the output  
33-4  
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Part IV. Communications Processor Module  
drivers of SPI signals. The core must clear SPMODE[EN] before the SPI is used again.  
After correcting the problems, clear SPIE[MME] and reenable the SPI.  
MPC8260  
SPI #0  
SPIMOSI  
SPIMISO  
SPICLK  
SPISEL  
SELOUT1  
SELOUT2  
SELOUT3  
MPC8260  
SPI #1  
SPIMOSI  
SPIMISO  
SPICLK  
SPISEL  
SELOUT0  
SELOUT2  
SELOUT3  
MPC8260  
SPI #2  
SPIMOSI  
SPIMISO  
SPICLK  
SPISEL  
SELOUT0  
SELOUT1  
SELOUT3  
MPC8260  
SPI #3  
SPIMOSI  
SPIMISO  
SPICLK  
SPISEL  
SELOUT0  
SELOUT1  
SELOUT2  
Notes:  
¥ All signals are open-drain  
¥ For a system with more than two masters, SPISEL and SPIE[MME] do not detect all possible conflicts  
¥ It is the responsibility of software to arbitrate for the SPI bus (with token passing, for example)  
¥ SELOUTx signals are implemented in software with general-purpose I/O signals  
Figure 33-3. Multimaster Configuration  
MOTOROLA  
Chapter 33. Serial Peripheral Interface (SPI)  
33-5  
 
Part IV. Communications Processor Module  
The maximum sustained data rate that the SPI supports is SYSTEMCLK/50. However, the  
SPI can transfer a single character at much higher ratesÑSYSTEMCLK/4 in master mode  
and SYSTEMCLK/2 in slave mode. Gaps should be inserted between multiple characters  
to keep from exceeding the maximum sustained data rate.  
33.4 Programming the SPI Registers  
The following sections describe the registers used in conÞguring and operating the SPI.  
33.4.1 SPI Mode Register (SPMODE)  
The SPI mode register (SPMODE), shown in Figure 33-4, controls both the SPI operation  
mode and clock source.  
Bit  
0
1
2
3
4
5
6
7
8
9
10  
LEN  
11  
12  
13  
14  
15  
Field  
Reset  
R/W  
Ñ
LOOP CI  
CP DIV16 REV M/S EN  
PM  
0000_00  
—
0_0000_0000  
R/W  
Addr  
0x11AA0  
Figure 33-4. SPMODEÑSPI Mode Register  
Table 33-1 describes the SPMODE Þelds.  
Table 33-1. SPMODE Field Descriptions  
Bits Name  
Description  
0
Ñ
Reserved, should be cleared.  
1
LOOP Loop mode. Enables local loopback operation.  
0 Normal operation.  
1 Loopback mode. The transmitter output is internally connected to the receiver input. The receiver  
and transmitter operate normally, except that received data is ignored.  
2
3
4
CI  
Clock invert. Inverts SPI clock polarity. See Figure 33-5 and Figure 33-6.  
0 The inactive state of SPICLK is low.  
1 The inactive state of SPICLK is high.  
CP  
Clock phase. Selects the transfer format. See Figure 33-5 and Figure 33-6.  
0 SPICLK starts toggling at the middle of the data transfer.  
1 SPICLK starts toggling at the beginning of the data transfer.  
DIV16 Divide by 16. Selects the clock source for the SPI baud rate generator when conÞgured as an SPI  
master. In slave mode, SPICLK is the clock source.  
0 BRGCLK is the input to the SPI BRG.  
1 BRGCLK/16 is the input to the SPI BRG.  
5
6
REV  
M/S  
Reverse data. Determines the receive and transmit character bit order.  
0 Reverse dataÑlsb of the character sent and received Þrst.  
1 Normal operationÑmsb of the character sent and received Þrst.  
Master/slave. Selects master or slave mode.  
0 The SPI is a slave.  
1 The SPI is a master.  
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Part IV. Communications Processor Module  
Table 33-1. SPMODE Field Descriptions (Continued)  
Bits Name  
Description  
7
EN  
Enable SPI. Do not change other SPMODE bits when EN is set.  
0 The SPI is disabled. The SPI is in a reset state and consumes minimal power. The SPI BRG is not  
functioning and the input clock is disabled.  
1 The SPI is enabled. ConÞgure SPIMOSI, SPIMISO, SPICLK, and SPISEL to connect to the SPI as  
described in Section 35.2, ÒPort Registers. Ò  
8Ð11 LEN  
Character length in bits per character. Must be between 0011 (4 bits) and 1111 (16 bits). A value less  
than 4 causes erratic behavior. If the value is not greater than a byte, every byte in memory holds LEN  
valid bits. If the value is greater than a byte, every half-word holds LEN valid bits. See  
Section 33.4.1.1, ÒSPI Examples with Different SPMODE[LEN] Values.Ó  
12Ð15 PM  
Prescale modulus select. SpeciÞes the divide ratio of the prescale divider in the SPI clock generator.  
BRGCLK is divided by 4 * ([PM0ÐPM3] + 1), a range from 4 to 64. The clock has a 50% duty cycle.  
SPICLK  
(CI = 0)  
(CI = 1)  
SPICLK  
SPIMOSI  
(From Master)  
msb  
lsb  
lsb  
SPIMISO  
(From Slave)  
msb  
Q
SPISEL  
NOTE: Q = Undefined Signal.  
Figure 33-5. SPI Transfer Format with SPMODE[CP] = 0  
Figure 33-6 shows the SPI transfer format in which SPICLK starts toggling at the  
beginning of the transfer (SPMODE[CP] = 1).  
SPICLK  
SPICLK  
(CI = 0)  
(CI = 1)  
SPIMOSI  
(From Master)  
msb  
msb  
lsb  
SPIMISO  
(From Slave)  
Q
lsb  
SPISEL  
NOTE: Q = Undefined Signal.  
Figure 33-6. SPI Transfer Format with SPMODE[CP] = 1  
MOTOROLA  
Chapter 33. Serial Peripheral Interface (SPI)  
33-7  
   
Part IV. Communications Processor Module  
33.4.1.1 SPI Examples with Different SPMODE[LEN] Values  
The examples below show how SPMODE[LEN] is used to determine character length. To  
help map the process, the conventions shown in Table 33-2 are used in the examples.  
Table 33-2. Example Conventions  
Convention  
Description  
gÐv  
x
Binary symbols  
Deleted bit  
1
__  
Original byte boundary  
Original 4-bit boundary.  
1
_
1
Both __ and _ are used to aid readability.  
Once the data string image is determined, it is always transmitted byte by byte with the lsb  
of the most-signiÞcant byte sent Þrst. For all examples below, assume the memory contains  
the following binary image:  
msb  
ghij_klmn__opqr_stuv  
lsb  
Example 1  
with LEN=4 (data size=5), the following data is selected:  
msb xxxj_klmn__xxxr_stuv  
with REV=0, the data string image is:  
msb j_klmn__r_stuv  
lsb  
lsb  
the order of the string appearing on the line, a byte at a time is:  
first nmlk_j__vuts_r last  
with REV=1,the string has each byte reversed, and the data string image is:  
msb nmlk_j__vuts_r lsb  
the order of the string appearing on the line, one byte at a time is:  
first  
j_klmn__r_stuv  
last  
Example 2  
with LEN=7 (data size=8), the following data is selected:  
msb ghij_klmn__opqr_stuv  
the data string is selected:  
msb ghij_klmn__opqr_stuv  
lsb  
lsb  
with REV=0, the string transmitted, a byte at a time with lsb first is:  
first nmlk_jihg__vuts_rqpo last  
with REV=1, the string is byte reversed and transmitted, a byte at a time, with  
lsb first:  
first  
ghij_klmn__opqr_stuv  
last  
Example 3:  
with LEN=0xC (data size=13), the following data is selected:  
msb  
ghij_klmn__xxxr_stuv  
lsb  
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Part IV. Communications Processor Module  
the data string selected is:  
msb r_stuv__ghij_klmn  
with REV=0, the string transmitted, a byte at a time with lsb first is:  
lsb  
first  
vuts_r__nmlk_jihg  
last  
with REV=1, the string is half-word reversed:  
msb nmlk_jihg__vuts_r  
and transmitted a byte at a time with lsb first:  
first ghij_klmn__r_stuv  
lsb  
last  
33.4.2 SPI Event/Mask Registers (SPIE/SPIM)  
The SPI event register (SPIE) generates interrupts and reports events recognized by the SPI.  
When an event is recognized, the SPI sets the corresponding SPIE bit. Clear SPIE bits by  
writing a 1Ñwriting 0 has no effect. Setting a bit in the SPI mask register (SPIM) enables  
and clearing a bit masks the corresponding interrupt. Unmasked SPIE bits must be cleared  
before the CP clears internal interrupt requests. Figure 33-7 shows both registers.  
Bit  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
Ñ
MME  
TXE  
Ñ
BSY  
TXB  
RXB  
0000_0000  
R/W  
Addr  
0x11AA6 (SPIE); 0x11AAA (SPIM)  
Figure 33-7. SPIE/SPIMÑSPI Event/Mask Registers  
Table 33-3 describes the SPIE/SPIM Þelds.  
Table 33-3. SPIE/SPIM Field Descriptions  
Bits Name  
Description  
0Ð1  
2
Ñ
Reserved, should be cleared.  
MME Multimaster error. Set when SPISEL is asserted externally while the SPI is in master mode.  
3
TXE  
Ñ
Tx error. Set when an error occurs during transmission.  
Reserved, should be cleared.  
4
5
BSY Busy. Set after the Þrst character is received but discarded because no Rx buffer is available.  
6
TXB  
Tx buffer. Set when the Tx data of the last character in the buffer is written to the Tx FIFO. Wait two  
character times to be sure data is completely sent over the transmit signal.  
7
RXB Rx buffer. Set after the last character is written to the Rx buffer and the BD is closed.  
33.4.3 SPI Command Register (SPCOM)  
The SPI command register (SPCOM), shown in Figure 33-8, is used to start SPI operation.  
MOTOROLA  
Chapter 33. Serial Peripheral Interface (SPI)  
33-9  
               
Part IV. Communications Processor Module  
0
1
2
3
4
5
6
7
Bit  
STR  
Ñ
Field  
Reset  
R/W  
0000_0000  
Write Only  
0x11AAD  
Addr  
Figure 33-8. SPCOMÑSPI Command Register  
Table 33-4 describes the SPCOM Þelds.  
Table 33-4. SPCOM Field Descriptions  
Bits Name  
Description  
0
STR  
Start transmit. For an SPI master, setting STR causes the SPI to start transferring data to and from the  
Tx/Rx buffers if they are prepared. For a slave, setting STR when the SPI is idle causes it to load the Tx  
data register from the SPI Tx buffer and start sending with the next SPICLK after SPISEL is asserted.  
STR is cleared automatically after one system clock cycle.  
1Ð7  
Ñ
Reserved and should be cleared.  
33.5 SPI Parameter RAM  
The SPI parameter RAM area is similar to the SCC general-purpose parameter RAM. The  
CP accesses the SPI parameter table using a user-programmed pointer (SPI_BASE) located  
in the parameter RAM; see Section 13.5.2, ÒParameter RAM.Ó The SPI parameter table can  
be placed at any 64-byte aligned address in the dual-port RAMÕs general-purpose area  
(banks #1Ð#8). Some parameter values must be user-initialized before the SPI is enabled;  
the CP initializes the others. Once initialized, parameter RAM values do not usually need  
to be accessed. They should be changed only when the SPI is inactive. Table 33-5 shows  
the memory map of the SPI parameter RAM.  
Table 33-5. SPI Parameter RAM Memory Map  
1
Offset  
Name Width  
Description  
0x00 RBASE Hword Rx/Tx BD table base address. Indicate where the BD tables begin in the dual-port RAM.  
Setting Rx/TxBD[W] in the last BD in each BD table determines how many BDs are  
0x02 TBASE Hword  
allocated for the Tx and Rx sections of the SPI. Initialize RBASE/TBASE before enabling  
the SPI. Furthermore, do not conÞgure BD tables of the SPI to overlap any other active  
controllerÕs parameter RAM.  
RBASE and TBASE should be divisible by eight.  
0x04 RFCR  
Byte  
Byte  
Rx/Tx function code registers. The function code registers contain the transaction  
speciÞcation associated with SDMA channel accesses to external memory. See  
Section 33.5.1, ÒReceive/Transmit Function Code Registers (RFCR/TFCR).Ó  
0x05 TFCR  
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Part IV. Communications Processor Module  
Table 33-5. SPI Parameter RAM Memory Map (Continued)  
1
Offset  
Name Width  
Description  
0x06 MRBLR Hword Maximum receive buffer length. The SPI has one MRBLR entry to deÞne the maximum  
number of bytes the MPC8260 writes to a Rx buffer before moving to the next buffer. The  
MPC8260 can write fewer bytes than MRBLR if an error or end-of-frame occurs, but  
never exceeds the MRBLR value. User-supplied buffers should be no smaller than  
MRBLR.  
Tx buffers are unaffected by MRBLR and can have varying lengths; the number of bytes  
to be sent is programmed in TxBD[Data Length].  
MRBLR is not intended to be changed while the SPI is operating. However it can be  
changed in a single bus cycle with one 16-bit move (not two 8-bit bus cycles back-to-  
back). The change takes effect when the CP moves control to the next RxBD. To  
guarantee the exact RxBD on which the change occurs, change MRBLR only while the  
SPI receiver is disabled. MRBLR should be greater than zero; it should be an even  
number if the character length of the data exceeds 8 bits.  
2
0x08 RSTATE Word Rx internal state. Reserved for CP use.  
2
0x0C  
Ñ
Word The Rx internal data pointer is updated by the SDMA channels to show the next  
address in the buffer to be accessed.  
0x10 RBPTR Hword RxBD pointer. Points to the current Rx BD being processed or to the next BD to be  
serviced when idle. After a reset or when the end of the BD table is reached, the CP  
initializes RBPTR to the RBASE value. Most applications should not modify RBPTR, but  
it can be updated when the receiver is disabled or when no Rx buffer is in use.  
2
0x12  
Ñ
Hword The Rx internal byte count is a down-count value that is initialized with the MRBLR  
value and decremented with every byte the SDMA channels write.  
2
0x14  
Ñ
Word Rx temp. Reserved for CP use.  
2
0x18 TSTATE Word Tx internal state. Reserved for CP use.  
2
0x1C  
Ñ
Word The Tx internal data pointer is updated by the SDMA channels to show the next address  
in the buffer to be accessed.  
0x20 TBPTR Hword TxBD pointer. Points to the current Tx BD during frame transmission or the next BD to be  
processed when idle. After reset or when the end of the Tx BD table is reached, the CP  
initializes TBPTR to the TBASE value. Most applications do not need to modify TBPTR,  
but it can be updated when the transmitter is disabled or when no Tx buffer is in use.  
2
0x22  
Ñ
Hword The Tx internal byte count is a down-count value initialized with TxBD[Data Length] and  
decremented with every byte read by the SDMA channels.  
2
0x24  
0x34  
Ñ
Ñ
Word Tx temp. Reserved for CP use.  
Word SDMA temp.  
1
2
From the pointer value programmed in SPI_BASE at IMMR + 0x89FC.  
Normally, these parameters need not be accessed. They are listed to help experienced users in debugging.  
MOTOROLA  
Chapter 33. Serial Peripheral Interface (SPI)  
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Part IV. Communications Processor Module  
33.5.1 Receive/Transmit Function Code Registers (RFCR/TFCR)  
Figure 33-9 shows the Þelds in the receive/transmit function code registers (RFCR/TFCR)  
Bit  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
Ñ
GBL  
BO  
0000_0000  
R/W  
TC2  
DTB  
Ñ
Addr  
SPI Base + 04 (RFCR)/SPI Base + 05 (TFCR)  
Figure 33-9. RFCR/TFCRÑFunction Code Registers  
Table 33-6 describes the RFCR/TFCR Þelds.  
Table 33-6. RFCR/TFCR Field Descriptions  
Bits Name  
Description  
0Ð1  
2
Ñ
Reserved, should be cleared.  
GBL Global access bit  
0 Disable memory snooping  
0 Enable memory snooping  
3Ð4  
BO  
Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-ßy, it  
takes effect at the beginning of the next frame or BD.  
00 True little-endian. Note this mode can only be used with 32-bit port size memory.  
01 PowerPC little-endian.  
1x Big-endian.  
5
6
TC2  
Transfer code 2. Contains the transfer code value of TC[2], used during this SDMA channel memory  
access. TC[0Ð1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.  
DTB Data bus indicator.  
0 Use 60x bus for SDMA operation.  
1 Use local bus for SDMA operation.  
7
Ñ
Reserved, should be cleared.  
33.6 SPI Commands  
Table 33-7 lists transmit/receive commands sent to the CP command register (CPCR).  
Table 33-7. SPI Commands  
Command  
Description  
INIT TX  
Initializes all transmit parameters in the parameter RAM to their reset state and should be issued only  
PARAMETERS when the transmitter is disabled. The INIT TX AND RX PARAMETERS command can also be used to reset  
both the Tx and Rx parameters.  
CLOSE RXBD Forces the SPI controller to close the current RxBD and use the next BD for subsequently received data.  
If the controller is not receiving data, no action is taken. Use this command to extract data from a  
partially full buffer.  
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Part IV. Communications Processor Module  
Table 33-7. SPI Commands (Continued)  
Command  
Description  
INIT RX  
Initializes all receive parameters in the parameter RAM to their reset state. Should be issued only when  
PARAMETERS the receiver is disabled.The INIT TX AND RX PARAMETERS command can also be used to reset both the Tx  
and Rx parameters.  
33.7 The SPI Buffer Descriptor (BD) Table  
As shown in Figure 33-10, BDs are organized into separate RxBD and TxBD tables in dual-  
port RAM. The tables have the same basic conÞguration as for the SCCs and SMCs and  
form circular queues that determine the order buffers are transferred. The CP uses BDs to  
conÞrm reception and transmission or to indicate error conditions so that the core knows  
buffers have been serviced. The buffers themselves can be placed in external memory or in  
any unused parameter area of the dual-port RAM.  
Dual-Port RAM  
External Memory  
TxBD Table  
Tx Buffer  
Frame Status  
Data Length  
Buffer Pointer  
Tx Buffer  
Rx Buffer  
Pointer to SPI  
TxBD Table  
RxBD Table  
Pointer to SPI  
RxBD Table  
Frame Status  
Data Length  
Buffer Pointer  
Figure 33-10. SPI Memory Structure  
33.7.1 SPI Buffer Descriptors (BDs)  
Receive and transmit BDs report information about each buffer transferred and whether a  
maskable interrupt should be generated. Each 64-bit BD, shown in Figure 33-11 and  
Figure 33-12, has the following structure:  
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The half word at offset + 0 contains status and control bits. The CP updates the status  
bits after the buffer is sent or received.  
The half word at offset + 2 contains the data length (in bytes) that is sent or received.  
Ñ For an RxBD, this is the number of octets the CP writes into this RxBDÕs buffer  
once the BD closes. The CP updates this Þeld after the received data is placed  
into the buffer. Memory allocated for this buffer should be no smaller than  
MRBLR.  
Ñ For a TxBD, this is the number of octets the CP should transmit from its buffer.  
Normally, this value should be greater than zero. If the character length is more  
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Part IV. Communications Processor Module  
than 8 bits, the data length should be even. For example, to send three characters  
of 8-bit data, 1 start, and 1 stop, the data length Þeld should be initialized to 3.  
However, to send three characters of 9-bit data, the data length Þeld should be  
initialized to 6 since the three 9-bit data Þelds occupy three half-words in  
memory. The CP never modiÞes this Þeld.  
¥
The word at offset + 4 points to the beginning of the buffer.  
Ñ For an RxBD, the pointer must be even and can point to internal or external  
memory.  
Ñ For a TxBD, the pointer can be even or odd, unless the character exceeds 8 bits,  
for which it must be even. The buffer can be in internal or external memory.  
33.7.1.1 SPI Receive BD (RxBD)  
The CP uses RxBDs to report on each received buffer. It closes the current buffer, generates  
a maskable interrupt, and starts receiving data in the next buffer once the current buffer is  
full. The CP also closes the buffer when the SPI is conÞgured as a slave and SPISEL is  
negated, indicating that reception stopped. The core should write RxBD bits before the SPI  
is enabled. The format of an RxBD is shown in Figure 33-11.  
0
1
2
3
4
L
5
6
7
8
9
10  
Ñ
11  
12  
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
E
Ñ
W
I
Ñ
CM  
OV ME  
Data Length  
Rx Buffer Pointer  
Figure 33-11. SPI RxBD  
Table 33-8 describes the RxBD status and control Þelds.  
Table 33-8. SPI RxBD Status and Control Field Descriptions  
Bits Name  
Description  
0
E
Empty.  
0 The buffer is full or stopped receiving because of an error.The core can examine or write to any Þelds  
of this RxBD, but the CP does not use this BD while E = 0.  
1 The buffer is empty or reception is in progress. The CP owns this RxBD and its buffer. Once E is set,  
the core should not write any Þelds of this RxBD.  
1
2
Ñ
Reserved, should be cleared.  
W
Wrap (last BD in table).  
0 Not the last BD in the RxBD table.  
1 Last BD in the RxBD table. After this buffer is used, the CP receives incoming data using the BD  
pointed to by RBASE (top of the table). The number of BDs in this table is determined only by the W  
bit and overall space constraints of the dual-port RAM.  
3
I
Interrupt.  
0 No interrupt is generated after this buffer is Þlled.  
1 SPIE[RXB] is set when this buffer is full, indicating the need for the core to process the buffer.  
SPIE[RXB] causes an interrupt if not masked.  
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Table 33-8. SPI RxBD Status and Control Field Descriptions (Continued)  
Bits Name  
Description  
4
L
Last. Updated by the SPI when the buffer is closed because SPISEL was negated (slave mode only).  
Otherwise, RxBD[ME] is set. The SPI updates L after received data is placed in the buffer.  
0 This buffer does not contain the last character of the message.  
1 This buffer contains the last character of the message.  
5
6
Ñ
Reserved, should be cleared.  
CM  
Continuous mode. Master mode only; in slave mode, CM should be cleared.  
0 Normal operation.  
1 The CP does not clear RxBD[E] after this BD is closed; the buffer is overwritten when the CP next  
accesses this BD.This allows continuous reception from an SPI slave into one buffer for autoscanning  
of a serial A/D peripheral with no core overhead.  
7Ð13  
14  
Ñ
Reserved, should be cleared.  
OV  
Overrun. Set when a receiver overrun occurs during reception (slave mode only). The SPI updates OV  
after the received data is placed in the buffer.  
15  
ME  
Multimaster error. Set when this buffer is closed because SPISEL was asserted when the SPI was in  
master mode. Indicates a synchronization problem between multiple masters on the SPI bus. The SPI  
updates ME after the received data is placed in the buffer.  
33.7.1.2 SPI Transmit BD (TxBD)  
Data to be sent with the SPI is sent to the CP by arranging it in buffers referenced by TxBDs  
in the TxBD table. TxBD Þelds should be prepared before data is sent. The format of an  
TxBD is shown in Figure 33-12.  
0
1
2
3
4
5
6
7
8
9
10  
Ñ
11  
12  
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
R
Ñ
W
I
L
Ñ
CM  
UN ME  
Data Length  
Tx Buffer Pointer  
Figure 33-12. SPI TxBD  
Table 33-9 describes the TxBD status and control Þelds.  
Table 33-9. SPI TxBD Status and Control Field Descriptions  
Bits Name  
Description  
0
R
Ready.  
0 The buffer is not ready to be sent. This BD or its buffer can be modiÞed. The CP clears R (unless  
RxBD[CM] is set) after the buffer is sent (unless RxBD[CM] is set) or an error occurs.  
1 The buffer is ready for transmission or is being sent. The BD cannot be modiÞed once R is set.  
1
Ñ
Reserved, should be cleared.  
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Part IV. Communications Processor Module  
Table 33-9. SPI TxBD Status and Control Field Descriptions (Continued)  
Bits Name  
Description  
2
W
Wrap (last BD in TxBD table).  
0 Not the last BD in the table.  
1 Last BD in the table. After this buffer is used, the CP receives incoming data using the BD pointed to  
by TBASE (top of the table). The number of BDs in this table is determined only by the W bit and  
overall space constraints of the dual-port RAM.  
3
4
I
Interrupt.  
0 No interrupt is generated after this buffer is processed.  
1 SPIE[TXB] or SPIE[TXE] are set when this buffer is processed and causes interrupts if not masked.  
L
Last.  
0 This buffer does not contain the last character of the message.  
1 This buffer contains the last character of the message.  
5
6
Ñ
Reserved, should be cleared.  
CM  
Continuous mode. Valid only when the SPI is in master mode. In slave mode, it should be cleared.  
0 Normal operation.  
1 The CP does not clear TxBD[R] after this BD is closed, allowing the buffer to be resent automatically  
when the CP next accesses this BD.  
7Ð13  
14  
Ñ
Reserved, should be cleared.  
UN  
Underrun. Indicates that the SPI encountered a transmitter underrun condition while sending the buffer.  
This error occurs only when the SPI is in slave mode. The SPI updates UN after it sends the buffer.  
15  
ME  
Multimaster error. Indicates that this buffer is closed because SPISEL was asserted when the SPI was  
in master mode. A synchronization problem occurred between devices on the SPI bus. The SPI  
updates ME after sending the buffer.  
33.8 SPI Master Programming Example  
The following sequence initializes the SPI to run at a high speed in master mode:  
1. ConÞgure port D to enable SPIMISO, SPIMOSI, SPICLK and SPISEL.  
2. ConÞgure a parallel I/O signal to operate as the SPI select output signal if needed.  
3. In address 0x89FC, assign a pointer to the SPI parameter RAM.  
4. Write RBASE and TBASE in the SPI parameter RAM to point to the RxBD and  
TxBD tables in the dual-port RAM. Assuming one RxBD followed by one TxBD at  
the beginning of the dual-port RAM, write RBASE with 0x0000 and TBASE with  
0x0008.  
5. Write RFCR and TFCR with 0x10 for normal operation.  
6. Write MRBLR with the maximum number of bytes per Rx buffer. For this case,  
assume 16 bytes, so MRBLR = 0x0010.  
7. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory.  
Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length]  
(optional), and 0x0000_1000 to RxBD[Buffer Pointer].  
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8. Initialize the TxBD. Assume the Tx buffer is at 0x0000_2000 in main memory and  
contains Þve 8-bit characters. Write 0xB800 to TxBD[Status and Control], 0x0005  
to TxBD[Data Length], and 0x0000_2000 to TxBD[Buffer Pointer].  
9. Execute the INIT RX AND TX PARAMETERS command by writing 0x2541_0000 to  
CPCR.  
10.Write 0xFF to SPIE to clear any previous events.  
11.Write 0x37 to SPIM to enable all possible SPI interrupts.  
12.Write 0x0370 to SPMODE to enable normal operation (not loopback), master mode,  
SPI enabled, 8-bit characters, and the fastest speed possible.  
13.Set SPCOM[STR] to start the transfer.  
After 5 bytes are sent, the TxBD is closed. Additionally, the Rx buffer is closed after 5 bytes  
are received because TxBD[L] is set.  
33.9 SPI Slave Programming Example  
The following is an example initialization sequence to follow when the SPI is in slave  
mode. It is very similar to the SPI master example, except that SPISEL is used instead of a  
general-purpose I/O signal (as shown in Figure 33-2).  
1. Enable SPIMISO, SPIMOSI, SPICLK, and SPISEL.  
2. In address 0x89FC, assign a pointer to the SPI parameter RAM.  
3. Assuming one RxBD at the beginning of the dual-port RAM followed by one TxBD,  
write RBASE with 0x0000 and TBASE with 0x0008 in the SPI parameter RAM.  
4. Write RFCR and TFCR with 0x10 for normal operation.  
5. Program MRBLR = 0x0010 for 16 bytes, the maximum number of bytes per buffer.  
6. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory.  
Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length]  
(optional), and 0x0000_1000 to RxBD[Buffer Pointer].  
7. Initialize the TxBD. Assume the Tx buffer is at 0x0000_2000 in main memory and  
contains Þve 8-bit characters. Write 0xB800 to TxBD[Status and Control], 0x0005  
to TxBD[Data Length], and 0x0000_2000 to TxBD[Buffer Pointer].  
8. Execute the INIT RX AND TX PARAMETERS command by writing 0x2541_0000 to  
CPCR.  
9. Write 0xFF to SPIE to clear any previous events.  
10.Write 0x37 to SPIM to enable all SPI interrupts.  
11.Set SPMODE to 0x0170 to enable normal operation (not loopback), slave mode, SPI  
enabled, and 8-bit characters. BRG speed is ignored in slave mode.  
12.Set SPCOM[STR] to enable the SPI to be ready once the master begins the transfer.  
Note that if the master sends 3 bytes and negates SPISEL, the RxBD is closed but the TxBD  
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Part IV. Communications Processor Module  
remains open. If the master sends 5 or more bytes, the TxBD is closed after the Þfth byte.  
If the master sends 16 bytes and negates SPISEL, the RxBD is closed without triggering an  
out-of-buffers error. If the master sends more than 16 bytes, the RxBD is closed (full) and  
an out-of-buffers error occurs after the 17th byte is received.  
33.10 Handling Interrupts in the SPI  
The following sequence should be followed to handle interrupts in the SPI:  
1. Once an interrupt occurs, read SPIE to determine the interrupt source. Normally,  
SPIE bits should be cleared at this time.  
2. Process the TxBD to reuse it and the RxBD to extract the data from it. To transmit  
another buffer, simply set TxBD[R], RxBD[E], and SPCOM[STR].  
3. Execute an rÞ instruction.  
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Chapter 34  
2
I C Controller  
340  
3T40 he inter-integrated circuit (I2C¨) controller lets the MPC8260 exchange data with other  
I2C devices, such as microcontrollers, EEPROMs, real-time clock devices, A/D converters,  
and LCD displays. The I2C controller uses a synchronous, multimaster bus that can connect  
several integrated circuits on a board. It uses two signalsÑserial data (SDA) and serial  
clock (SCL)Ñto carry information between the integrated circuits connected to it.  
As shown in Figure 34-1, the I2C controller consists of transmit and receive sections, an  
independent baud-rate generator (BRG), and a control unit. The transmit and receive  
sections use the same clock, which is derived from the I2C BRG when in master mode and  
generated externally when in slave mode. Wait states are inserted during a data transfer if  
SCL is held low by a slave device. In the middle of a data transfer, the master I2C controller  
recognizes the need for wait states by monitoring SCL. However, the I2C controller has no  
automatic time-out mechanism if the slave device does not release SCL; therefore, software  
should monitor how long SCL stays low to generate bus timeouts.  
Peripheral Bus  
60x Bus  
Rx Data Register  
Tx Data Register  
Shift Register  
Mode Register  
Shift Register  
SDA  
Control  
Baud-Rate Generator  
SCL  
Figure 34-1. I2C Controller Block Diagram  
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The I2C receiver and transmitter are double-buffered, which corresponds to an effective  
two-character FIFO latency. In normal operation, the transmitter shifts the msb (bit 0) out  
Þrst. When the I2C is not enabled in the I2C mode register (I2MOD[EN] = 0), it consumes  
little power.  
34.1 Features  
The following is a list of the I2C controllerÕs main features:  
¥
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Two-signal interface (SDA and SCL)  
Support for master and slave I2C operation  
Multiple-master environment support  
Continuous transfer mode for automatic scanning of a peripheral  
Supports a maximum clock rate of 2,080 KHz (with a CPM utilization of 25%),  
assuming a 100-MHz system clock.  
¥
¥
¥
¥
Independent, programmable baud-rate generator  
Supports 7-bit I2C addressing  
Open-drain output signals allow multiple master conÞguration  
Local loopback capability for testing  
34.2 I2C Controller Clocking and Signal Functions  
The I2C controller can be conÞgured as a master or slave for the serial channel. As a master,  
the controllerÕs BRG provides the transfer clock. The I2C BRG takes its input from the BRG  
clock (BRGCLK), which is generated from the CPM clock; see Section 9.8, ÒSystem Clock  
Control Register (SCCR).Ó  
SDA and SCL are bidirectional signals connected to a positive supply voltage through an  
external pull-up resistor. When the bus is free, both signals are pulled high. The general I2C  
master/slave conÞguration is shown in Figure 34-2.  
V
DD  
Master  
Slave  
SCL  
SDA  
SCL  
SDA  
(EEPROM, for example)  
V
DD  
Figure 34-2. I2C Master/Slave General Configuration  
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When the I2C controller is master, the SCL clock output, taken directly from the I2C BRG,  
shifts receive data in and transmit data out through SDA. The transmitter arbitrates for the  
bus during transmission and aborts if it loses arbitration. When the I2C controller is a slave,  
the SCL clock input shifts data in and out through SDA. The SCL frequency can range from  
DC to BRGCLK/48.  
34.3 I2C Controller Transfers  
To initiate a transfer, the master I2C controller sends a message specifying a read or write  
request to an I2C slave. The Þrst byte of the message consists of a 7-bit slave port address  
and a R/W request bit. Note that because the R/W request follows the slave port address in  
the I2C bus speciÞcation, the R/W request bit must be placed in the lsb (bit 7) unless  
operating in reverse data mode; see Section 34.4.1, ÒI2C Mode Register (I2MOD).Ó  
To write to a slave, the master sends a write request (R/W = 0) along with either the target  
slaveÕs address or a general call (broadcast) address of all zeros, followed by the data to be  
written. To read from a slave, the master sends a read request (R/W = 1) and the target  
slaveÕs address. When the target slave acknowledges the read request, the transfer direction  
is reversed, and the master receives the slaveÕs transmit buffer(s). If the receiver (master or  
slave) does not acknowledge each byte transfer in the ninth bit frame, the transmitter signals  
a transmission error event (I2ER[TXE]). An I2C transfer timing diagram is shown in  
Figure 34-3.  
Start Condition  
Stop Condition  
SCL  
SDA  
1
2
3
4
5
6
7
8
9
A
C
K
Data Byte  
Figure 34-3. I2C Transfer Timing  
Select master or slave mode for the controller using the I2C command register (I2COM[M/  
S]). Set the masterÕs start bit, I2COM[STR], to begin a transfer; setting a slaveÕs  
I2COM[STR] activates the slave to wait for a transfer request from a master.  
If a master or slave transmitterÕs current TxBD[L] is set, transmission stops once the buffer  
is sent; that is, I2COM[STR] must be set again to reactivate transfers. If TxBD[L] is zero,  
once the current buffer is sent, the controller begins processing the next TxBD without  
waiting for I2COM[STR] to be set again.  
The following sections further detail the transfer process.  
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Chapter 34. I2C Controller  
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Part IV. Communications Processor Module  
34.3.1 I2C Master Write (Slave Read)  
If the MPC8260 is the master, prepare the transmit buffers and BDs before initiating a write.  
Initialize the Þrst transmit data byte with the slave address and write request (R/W = 0).  
If the MPC8260 is the slave target of the write, prepare receive buffers and BDs to await  
the masterÕs request. Figure 34-4 shows the timing for a master write.  
S
S
T
O
P
T
A
R
T
A
C
W K  
A
C
K
Data Byte  
SDA  
Device Address  
Note: Data and ACK are repeated n times.  
Figure 34-4. I2C Master Write Timing  
A master write occurs as follows:  
1. The master core sets I2COM[STR]. The transfer starts when the SDMA channel  
loads the Tx FIFO with data and the I2C bus is not busy.  
2. The I2C master generates a start conditionÑa high-to-low transition on SDA while  
SCL is highÑand the transfer clock SCL pulses for each bit shifted out on SDA. If  
the master transmitter detects a multiple-master collision (by sensing a Ô0Õ on SDA  
while sending a Ô1Õ), transmission stops and the channel reverts to slave mode. A  
maskable interrupt is sent to the masterÕs core so software can try to retransmit later.  
3. The slave acknowledges each byte and writes to its current receive buffer until a new  
start or stop condition is detected.  
4. After sending each byte, the master monitors the acknowledge indication. If the  
slave receiver fails to acknowledge a byte, transmission stops and the master  
generates a stop conditionÑa low-to-high transition on SDA while SCL is high.  
34.3.2 I2C Loopback Testing  
When in master mode, an I2C controller supports loopback operation for master write  
requests. The master I2C controller simply issues a write request directed to its own address  
(programmed in I2ADD). The masterÕs receiver monitors the transmission and reads the  
transmitted data into its receive buffer. Loopback operation requires no special register  
programming.  
34.3.3 I2C Master Read (Slave Write)  
Before initiating a master read with the MPC8260, prepare a transmit buffer of size n+1  
bytes, where n is the number of bytes to be read from the slave. The Þrst transmit byte  
should be initialized to the slave address with R/W = 1. The next n transmit bytes are used  
strictly for timing and can be left uninitialized. ConÞgure suitable receive buffers and BDs  
to receive the slaveÕs transmission.  
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If the MPC8260 is the slave target of the read, prepare the I2C transmit buffers and BDs and  
activate it by setting I2COM[STR]. Figure 34-5 shows the timing for a master read.  
N
O
S
T
A
R
T
S
T
O
P
A
C
K
A
C
K
R
SDA  
Device Address  
Data Byte  
Note: After the nth data byte, the master does not acknowledge the slave.  
Figure 34-5. I2C Master Read Timing  
A master read occurs as follows:  
1. Set the masterÕs I2COM[STR] to initiate the read. The transfer starts when the  
SDMA channel loads the transmit FIFO with data and the I2C bus is not busy.  
2. The slave detects a start condition on SDA and SCL.  
3. After the Þrst byte is shifted in, the slave compares the received data to its slave  
address. If the slave is an MPC8260, the address is programmed in its I2C address  
register (I2ADD).  
Ñ If a match is found, the slave acknowledges the received byte and begins  
transmitting on the clock pulse immediately following the acknowledge.  
Ñ If a match is found but the slave is not ready, the read request is not  
acknowledged and the transaction is aborted. If the slave is an MPC8260, a  
maskable transmission error interrupt is triggered to allow software to prepare  
data for transmission on the next try.  
Ñ If a mismatch occurs, the slave ignores the message and searches for a new start  
condition.  
4. The master acknowledges each byte sent as long as an overrun does not occur. If the  
master receiver fails to acknowledge a byte, the slave aborts transmission. For a  
slave MPC8260, the abort generates a maskable interrupt. A maskable interrupt is  
also issued after a complete buffer is sent or after an error. If an underrun occurs, the  
MPC8260 slave sends ones until a stop condition is detected.  
34.3.4 I2C Multi-Master Considerations  
The I2C controller supports a multi-master conÞguration, in which the I2C controller must  
alternate between master and slave modes. The I2C controller supports this by  
implementing I2C master arbitration in hardware. However, due to the nature of the I2C bus  
and the implementation of the I2C controller, certain software considerations must be made.  
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Chapter 34. I2C Controller  
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Part IV. Communications Processor Module  
An MPC8260 I2C controller attempting a master read request could simultaneously be  
targeted for an external master write (slave read). Both operations trigger the controllerÕs  
I2CER[RXB] event, but only one operation wins the bus arbitration. To determine which  
operation caused the interrupt, software must verify that its transmit operation actually  
completed before assuming that the received data is the result of its read operation.  
Problems could also arise if the MPC8260's I2C controller master sets up a transmit buffer  
and BD for a write request, but then is the target of a read request from another master.  
Without software precautions, the I2C controller responds to the other master with the  
transmit buffer originally intended for its own write request. To avoid this situation, a  
higher-level handshake protocol must be used. For example, a master, before reading a  
slave, writes the slave with a description of the requested data (which register should be  
read, for example). This operation is typical with many I2C devices.  
34.4 I2C Registers  
The following sections describe the I C registers.  
2
34.4.1 I2C Mode Register (I2MOD)  
2
The I C mode register, shown in Figure 34-6, controls the I2C modes and clock source.  
Bit  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
Ñ
REVD  
GCD  
FLT  
PDIV  
EN  
0000_0000  
R/W  
Addr  
0x11860  
Figure 34-6. I2C Mode Register (I2MOD)  
Table 34-1 describes I2MOD bit functions.  
Table 34-1. I2MOD Field Descriptions  
Bits Name  
Description  
0Ð1  
2
Ñ
Reserved and should be cleared.  
REVD Reverse data. Determines the Rx and Tx character bit order.  
0 Normal operation. The msb (bit 0) of a character is transferred Þrst.  
1 Reverse data. the lsb (bit 7) of a character is transferred Þrst.  
Note: Clearing REVD is strongly recommended to ensure consistent bit ordering across devices.  
3
4
GCD General call disable. Determines whether the receiver acknowledges a general call address.  
0 General call address is enabled.  
1 General call address is disabled.  
2
FLT  
Clock Þlter. Determines if the I C input clock SCL is Þltered to prevent spikes in a noisy environment.  
0 SCL is not Þltered.  
1 SCL is Þltered by a digital Þlter.  
34-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
             
Part IV. Communications Processor Module  
Table 34-1. I2MOD Field Descriptions (Continued)  
Bits Name  
Description  
2
5Ð6 PDIV Predivider. Selects the clock division factor before it is input into the I C BRG. The clock source for the  
2
I C BRG is the BRGCLK generated from the CPM clock; see Section 9.8, ÒSystem Clock Control  
Register (SCCR).Ó  
00 BRGCLK/32  
01 BRGCLK/16  
10 BRGCLK/8  
11 BRGCLK/4  
Note: To both save power and reduce noise susceptibility, select the PDIV with the largest division  
factor (slowest clock) that still meets performance requirements.  
2
7
EN  
Enable I C operation.  
2
2
0 I C is disabled. The I C is in a reset state and consumes minimal power.  
1 I C is enabled. Do not change other I2MOD bits when EN is set.  
2
34.4.2 I2C Address Register (I2ADD)  
The I2C address register, shown in Figure 34-7, holds the address for this I2C port.  
Bit  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
SAD  
Ñ
0000_0000  
R/W  
Addr  
0x11864  
Figure 34-7. I2C Address Register (I2ADD)  
Table 34-2 describes I2CADD Þelds.  
Table 34-2. I2ADD Field Descriptions  
Bits  
0Ð6  
Name  
Description  
2
SAD  
Ñ
Slave address 0Ð6. Holds the slave address for the I C port.  
7
Reserved and should be cleared.  
34.4.3 I2C Baud Rate Generator Register (I2BRG)  
The I2C baud rate generator register, shown in Figure 34-8, sets the divide ratio of the I2C  
BRG.  
Bit  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
DIV  
1111_1111  
R/W  
Addr  
0x11868  
Figure 34-8. I2C Baud Rate Generator Register (I2BRG)  
MOTOROLA  
Chapter 34. I2C Controller  
34-7  
                 
Part IV. Communications Processor Module  
Table 34-3 describes I2BRG Þelds.  
Table 34-3. I2BRG Field Descriptions  
Bits Name  
Description  
2
0Ð7 DIV  
Division ratio 0Ð7. SpeciÞes the divide ratio of the BRG divider in the I C clock generator.The output of  
the prescaler is divided by 2 * ([DIV0ÐDIV7] + 3) and the clock has a 50% duty cycle. DIV must be  
programmed to a minimum value of 3 if the digital Þlter is disabled and 6 if it is enabled.  
34.4.4 I2C Event/Mask Registers (I2CER/I2CMR)  
The I2C event register (I2CER) is used to generate interrupts and report events. When an  
event is recognized, the I2C controller sets the corresponding I2CER bit. I2CER bits are  
cleared by writing ones; writing zeros has no effect. Setting a bit in the I2C mask register  
(I2CMR) enables and clearing a bit masks the corresponding interrupt. Unmasked I2CER  
bits must be cleared before the CP clears internal interrupt requests. Figure 34-9 shows both  
registers.  
Bit  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
Ñ
TXE  
Ñ
BSY  
TXB  
RXB  
0000_0000  
R/W  
Addr  
0x11870(I2CER)/0x11874 I2CMR)  
Figure 34-9. I2C Event/Mask Registers (I2CER/I2CMR)  
Table 34-4 describes the I2CER/I2CMR Þelds.  
Table 34-4. I2CER/I2CMR Field Descriptions  
Bits Name  
Description  
0Ð2  
3
Ñ
Reserved and should be cleared.  
TXE Tx error. Set when an error occurs during transmission.  
Reserved and should be cleared.  
BSY Busy. Set after the Þrst character is received but discarded because no Rx buffer is available.  
4
Ñ
5
6
TXB Tx buffer. Set when the Tx data of the last character in the buffer is written to the Tx FIFO.Two character  
times must elapse to guarantee that all data has been sent.  
7
RXB Rx buffer. Set after the last character is written to the Rx buffer and the RxBD is closed.  
34.4.5 I2C Command Register (I2COM)  
The I2C command register, shown in Figure 34-10, is used to start I2C transfers and to select  
master or slave mode.  
34-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
                 
Part IV. Communications Processor Module  
Bit  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
STR  
Ñ
M/S  
0000_0000  
R/W  
Addr  
0x1186C  
Figure 34-10. I2C Command Register (I2COM)  
Table 34-5 describes I2COM Þelds.  
Table 34-5. I2COM Field Descriptions  
Bits Name  
Description  
2
0
STR Start transmit. In master mode, setting STR causes the I C controller to start sending data from the  
2
2
I C Tx buffers if they are ready. In slave mode, setting STR when the I C controller is idle causes it to  
load the Tx data register from the I C Tx buffer and start sending when it receives an address byte that  
matches the slave address with R/W = 1. STR is always read as a 0.  
2
1Ð6  
7
Ñ
Reserved and should be cleared.  
2
M/S  
Master/slave. ConÞgures the I C controller to operate as a master or a slave.  
2
0 I C is a slave.  
2
1 I C is a master.  
34.5 I2C Parameter RAM  
The I2C controller parameter table is used for the general I2C parameters and is similar to  
the SCC general-purpose parameter RAM. The CP accesses the I2C parameter table using  
a user-programmed pointer (I2C_BASE) located in the parameter RAM; see  
Section 13.5.2, ÒParameter RAM.Ó The I2C parameter table can be placed at any 64-byte  
aligned address in the dual-port RAMÕs general-purpose area (banks #1Ð#8). The user must  
initialize certain parameter RAM values before the I2C is enabled; the CP initializes the  
other values. Software usually does not access parameter RAM entries once they are  
initialized; they should be changed only when the I2C is inactive.  
Table 34-6. I2C Parameter RAM Memory Map  
1
Offset  
Name  
Width  
Description  
0x00  
0x02  
RBASE  
TBASE  
Hword Rx/TxBD table base address. Indicate where the BD tables begin in the dual-port RAM.  
Setting Rx/TxBD[W] in the last BD in each BD table determines how many BDs are  
2
Hword  
allocated for the Tx and Rx sections of the I C. Initialize RBASE/TBASE before enabling  
2
2
the I C. Furthermore, do not conÞgure BD tables of the I C to overlap any other active  
controllerÕs parameter RAM.  
RBASE and TBASE should be divisible by eight.  
0x04  
0x05  
RFCR  
TFCR  
Byte  
Byte  
Rx/Tx function code registers. The function code registers contain the transaction  
speciÞcation associated with SDMA channel accesses to external memory. See  
Figure 34-11 and Table 34-7.  
MOTOROLA  
Chapter 34. I2C Controller  
34-9  
         
Part IV. Communications Processor Module  
Table 34-6. I2C Parameter RAM Memory Map (Continued)  
1
Offset  
Name  
Width  
Description  
0x06  
MRBLR Hword Maximum receive buffer length. DeÞnes the maximum number of bytes the MPC8260  
writes to a Rx buffer before moving to the next buffer. The MPC8260 writes fewer bytes  
to the buffer than the MRBLR value if an error or end-of-frame occurs. Buffers should not  
be smaller than MRBLR.  
Tx buffers are unaffected by MRBLR and can vary in length; the number of bytes to be  
sent is speciÞed in TxBD[Data Length].  
2
MRBLR is not intended to be changed while the I C is operating. However it can be  
changed in a single bus cycle with one 16-bit move (not two 8-bit bus cycles back-to-  
back). The change takes effect when the CP moves control to the next RxBD. To  
guarantee the exact RxBD on which the change occurs, change MRBLR only while the  
2
I C receiver is disabled. MRBLR should be greater than zero; it should be an even  
number if the character length of the data exceeds 8 bits.  
2
0x08  
0x0C  
RSTATE Word Rx internal state. Reserved for CP use.  
2
RPTR  
Word Rx internal data pointer is updated by the SDMA channels to show the next address in  
the buffer to be accessed.  
0x10  
RBPTR  
Hword RxBD pointer. Points to the next descriptor the receiver transfers data to when it is in an  
2
idle state or to the current descriptor during frame processing for each I C channel. After  
a reset or when the end of the descriptor table is reached, the CP initializes RBPTR to  
the value in RBASE. Most applications should not write RBPTR, but it can be modiÞed  
when the receiver is disabled or when no receive buffer is used.  
2
0x12  
RCOUNT Hword Rx internal byte count is a down-count value that is initialized with the MRBLR value  
and decremented with every byte the SDMA channels write.  
2
0x14  
0x18  
0x1C  
RTEMP  
Word Rx temp. Reserved for CP use.  
2
TSTATE Word Tx internal state. Reserved for CP use.  
2
TPTR  
Word Tx internal data pointer is updated by the SDMA channels to show the next address in  
the buffer to be accessed.  
0x20  
TBPTR  
Hword TxBD pointer. Points to the next descriptor that the transmitter transfers data from when  
it is in an idle state or to the current descriptor during frame transmission. After a reset or  
when the end of the descriptor table is reached, the CP initializes TBPTR to the value in  
TBASE.Most applications should not write TBPTR, but it can be modiÞed when the  
transmitter is disabled or when no transmit buffer is used.  
2
0x22  
0x24  
TCOUNT Hword Tx internal byte count is a down-count value initialized with TxBD[Data Length] and  
decremented with every byte read by the SDMA channels.  
2
TTEMP  
Word Tx temp. Reserved for CP use.  
1
2
From the pointer value programmed in I2C_BASE at IMMR + 0x8AFC.  
Normally, these parameters need not be accessed.  
34-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part IV. Communications Processor Module  
Figure 34-11 shows the RFCR/TFCR bit Þelds.  
Bit  
0
1
2
3
4
5
6
7
Field  
Reset  
R/W  
GBL  
BO  
0000_0000  
R/W  
TC2  
DTB  
Ñ
Addr  
I2C_BASE + 04 (RFCR)/I2C_BASE + 05 (TFCR)  
Figure 34-11. I2C Function Code Registers (RFCR/TFCR)  
Table 34-7 describes the RFCR/TFCR bit Þelds.  
Table 34-7. RFCR/TFCR Field Descriptions  
Bits Name  
Description  
0Ð1  
2
Ñ
Reserved, should be cleared.  
GBL  
Global access bit  
0 Disable memory snooping  
0 Enable memory snooping  
3Ð4  
BO  
Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-ßy, it  
takes effect at the beginning of the next frame or BD.  
00 True little-endian. Note this mode can only be used with 32-bit port size memory.  
01 PowerPC little-endian.  
1x Big-endian.  
5
6
TC2  
DTB  
Transfer code 2. Contains the transfer code value of TC[2], used during this SDMA channel memory  
access. TC[0Ð1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.  
Data bus indicator.  
0 Use 60x bus for SDMA operation.  
1 Use local bus for SDMA operation.  
7
Ñ
Reserved, should be cleared.  
34.6 I2C Commands  
2
The I C transmit and receive commands, shown in Table 34-8, are issued to the CP  
command register (CPCR).  
Table 34-8. I2C Transmit/Receive Commands  
Command  
Description  
INIT TX  
Initializes all transmit parameters in the parameter RAM to their reset state. Should be issued only  
PARAMETERS when the transmitter is disabled. The INIT TX AND RX PARAMETERS command can also be used to reset  
both the Tx and Rx parameters.  
2
CLOSE RXBD Forces the I C controller to close the current Rx BD and use the next BD for subsequently received  
data. If the controller is not receiving data, no action is taken. Use this command to extract data from a  
partially full buffer.  
INIT RX  
Initializes all receive parameters in the parameter RAM to their reset state. Should be issued only when  
PARAMETERS the receiver is disabled. The INIT TX AND RX PARAMETERS command can also be used to reset both the  
Tx and Rx parameters.  
MOTOROLA  
Chapter 34. I2C Controller  
34-11  
         
Part IV. Communications Processor Module  
34.7 The I2C Buffer Descriptor (BD) Table  
As shown in Figure 34-12, buffer descriptors (BDs) are organized into separate RxBD and  
TxBD tables in dual-port RAM. The tables have the same basic conÞguration as for the  
SCCs and SMCs and form circular queues that determine the order buffers are transferred.  
The CP uses BDs to conÞrm reception and transmission or to indicate error conditions so  
that the core knows buffers have been serviced. The buffers themselves can be placed in  
external memory or in any unused parameter area of the dual-port RAM.  
Dual-Port RAM  
External Memory  
TxBD Table  
Tx Buffer  
Status and Control  
Data Length  
Tx Buffer  
Rx Buffer  
2
Buffer Pointer  
I C TxBD Table  
2
I C RxBD Table  
RxBD Table  
Status and Control  
Data Length  
2
I C RxBD Table Pointer  
(RBASE)  
Buffer Pointer  
2
I C TxBD Table Pointer  
(TBASE)  
Figure 34-12. I2C Memory Structure  
34.7.1 I2C Buffer Descriptors (BDs)  
Receive and transmit buffer descriptors report information about each buffer transferred  
and whether a maskable interrupt should be generated. Each 64-bit BD, shown in  
Figure 34-13 and Figure 34-14, has the following structure:  
¥
The half word at offset + 0 contains status and control bits. The CP updates the status  
bits after the buffer is sent or received.  
¥
The half word at offset + 2 contains the data length (in bytes) that is sent or received.  
Ñ For an RxBD, this is the number of octets the CP writes into this RxBDÕs buffer  
once the descriptor closes. The CP updates this Þeld after the received data is  
placed into the associated buffer. Memory allocated for this buffer should be no  
smaller than MRBLR.  
Ñ For a TxBD, this is the number of octets the CP should transmit from its buffer.  
Normally, this value should be greater than zero. The CP never modiÞes this  
Þeld.  
¥
The word at offset + 4 points to the beginning of the buffer.  
Ñ For an RxBD, the pointer must be even and can point to internal or external  
memory.  
Ñ For a TxBD, the pointer can be even or odd. The buffer can reside in internal or  
external memory.  
34-12  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
     
Part IV. Communications Processor Module  
34.7.1.1 I2C Receive Buffer Descriptor (RxBD)  
Using RxBDs, the CP reports on each buffer received, closes the current buffer, generates  
a maskable interrupt, and starts receiving data in the next buffer when the current one is full.  
It closes the buffer when a stop or start condition is found on the I2C bus or when an overrun  
error occurs. The core should write RxBD bits before the I2C controller is enabled.  
0
1
2
3
4
L
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Ñ
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
E
Ñ
W
I
Ñ
OV  
Data Length  
RX Buffer Pointer  
Figure 34-13. I2C RxBD  
2
Table 34-9 describes I C RxBD status and control bits.  
Table 34-9. I2C RxBD Status and Control Bits  
Bits Name  
Description  
0
E
Empty.  
0 The buffer is full or stopped receiving because of an error. The core can examine or write to any  
Þelds of this RxBD, but the CP does not use this BD while E = 0.  
1 The buffer is empty or reception is in progress. The CP owns this RxBD and its buffer. Once E is set,  
the core should not write any Þelds of this RxBD.  
1
2
Ñ
Reserved and should be cleared.  
W
Wrap (last BD in table).  
0 Not the last BD in the RxBD table.  
1 Last BD in the RxBD table. After this buffer is used, the CP receives incoming data using the BD  
pointed to by RBASE (top of the table). The number of BDs in this table is determined only by the W  
bit and overall space constraints of the dual-port RAM.  
3
4
I
Interrupt.  
0 No interrupt is generated after this buffer is full.  
1 The I2CER[RXB] is set when the CP Þlls this buffer, indicating that the core needs to process the  
buffer. The RXB bit can cause an interrupt if it is enabled.  
2
L
Last. The I C controller sets L.  
0 This buffer does not contain the last character of the message.  
1 This buffer holds the last character of the message.The I C controller sets L after all received data is  
placed into the associated buffer, or because of a stop or start condition or an overrun.  
2
5Ð13  
14  
Ñ
Reserved and should be cleared.  
2
OV  
Overrun. Set when a receiver overrun occurs during reception. The I C controller updates this bit after  
the received data is placed into the associated buffer.  
15  
Ñ
Reserved and should be cleared.  
MOTOROLA  
Chapter 34. I2C Controller  
34-13  
       
Part IV. Communications Processor Module  
34.7.1.2 I2C Transmit Buffer Descriptor (TxBD)  
Transmit data is arranged in buffers referenced by TxBDs in the TxBD table. The Þrst word  
of the TxBD, shown in Figure 34-14, contains status and control bits.  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
Offset + 0  
Offset + 2  
Offset + 4  
Offset + 6  
R
Ñ
W
I
L
S
Ñ
NAK UN  
CL  
Data Length  
Tx Buffer Pointer  
Figure 34-14. I2C TxBD  
2
Table 34-10 describes I C TxBD status and control bits.  
Table 34-10. I2C TxBD Status and Control Bits  
Bits Name  
Description  
0
R
Ready.  
0 The buffer is not ready to be sent. This BD or its buffer can be modiÞed. The CP clears R after the  
buffer is sent or an error occurs.  
1 The buffer is ready for transmission or is being sent. The BD cannot be modiÞed once R is set.  
1
2
Ñ
Reserved and should be cleared.  
W
Wrap (last BD in TxBD table).  
0 Not the last BD in the table.  
1 Last BD in the table. After this buffer is used, the CP transmits data using the BD pointed to by  
TBASE (top of the table).The number of BDs in this table is determined only by the W bit and overall  
space constraints of the dual-port RAM.  
3
4
I
Interrupt.  
0 No interrupt is generated after this buffer is serviced.  
1 I2CER[TXB] or I2CER[TXE] is set when the buffer is serviced. If enabled, an interrupt occurs.  
L
Last.  
0 This buffer does not contain the last character of the message.  
2
1 This buffer contains the last character of the message. The I C controller generates a stop condition  
after sending this buffer.  
5
S
Generate start condition. Provides ability to send back-to-back frames with one I2COM[STR] trigger.  
0 Do not send a start condition before the Þrst byte of the buffer.  
1 Send a start condition before the Þrst byte of the buffer. (Used to separate frames.)  
Note: If this BD is the Þrst one in the frame when I2COM[STR] is triggered, a start condition is sent  
regardless of the value of TxBD[S].  
6Ð12  
13  
Ñ
Reserved and should be cleared.  
NAK No acknowledge. Indicates that the transmission was aborted because the last byte sent was not  
2
acknowledged. The I C controller updates NAK after the buffer is sent.  
2
14  
15  
UN  
CL  
Underrun. Indicates that the I C controller encountered a transmitter underrun condition while sending  
2
the associated buffer. The I C controller updates UN after the buffer is sent.  
Collision. Indicates that transmission terminated because the transmitter was lost while arbitrating for  
2
the bus. The I C controller updates CL after the buffer is sent.  
34-14  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Chapter 35  
Parallel I/O Ports  
350  
3T50 he CPM supports four general-purpose I/O portsÑports A, B, C, and D. Each pin in the  
I/O ports can be conÞgured as a general-purpose I/O signal or as a dedicated peripheral  
interface signal. Port C is unique in that 16 of its pins can generate interrupts to the interrupt  
controller.  
Each pin can be conÞgured as an input or output and has a latch for data output, read or  
written at any time, and conÞgured as general-purpose I/O or a dedicated peripheral pin.  
Part of the pins can be conÞgured as open-drain (the pin can be conÞgured in a wired-OR  
conÞguration on the board). The pin drives a zero voltage but three-states when driving a  
high voltage.  
Note that port pins do not have internal pull-up resistors. Due to the CPMÕs signiÞcant  
ßexibility, many dedicated peripheral functions are multiplexed onto the ports. The  
functions are grouped to maximize the pinsÕusefulness in the greatest number of MPC8260  
applications. The reader may not obtain a full understanding of the pin assignment  
capability described in this chapter without understanding the CPM peripherals.  
35.1 Features  
The following is a list of the parallel I/O portsÕ important features:  
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
Port A is 32 bits  
Port B is 28 bits  
Port C is 32 bits  
Port D is 28 bits  
All ports are bidirectional  
All ports have alternate on-chip peripheral functions  
All ports are three-stated at system reset  
All pin values can be read while the pin is connected to an on-chip peripheral  
Open-drain capability on some pins  
Port C offers 16 interrupt input pins  
MOTOROLA  
Chapter 35. Parallel I/O Ports  
35-1  
         
Part IV. Communications Processor Module  
35.2 Port Registers  
Each port has four memory-mapped, read/write, 32-bit control registers.  
35.2.1 Port Open-Drain Registers (PODRAÐPODRD)  
The port open-drain register (PODR), shown in Figure 35-1, indicates a normal or wired-  
OR conÞguration of the port pins.  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
1
1
1
1
Field OD0 OD1 OD2 OD3 OD4 OD5 OD6 OD7 OD8 OD9 OD10 OD11 OD12 OD13 OD14 OD15  
Reset  
R/W  
Addr  
Bits  
0000_0000_0000_0000  
R/W  
0x10D0C (PODRA), 0x10D2C (PODRB), 0x10D4C (PODRC), 0x10D6C (PODRD)  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field OD16 OD17 OD18 OD19 OD20 OD21 OD22 OD23 OD24 OD25 OD26 OD27 OD28 OD29 OD30 OD31  
Reset  
R/W  
0000_0000_0000_0000  
R/W  
Addr  
0x10D0E (PODRA), 0x10D2E (PODRB), 0x10D4E (PODRC), 0x10D6E (PODRD)  
1
These bits are valid for PODRA and PODRC only  
Figure 35-1. Port Open-Drain Registers (PODRAÐPODRD)  
Table 35-1 describes PODR Þelds.  
Table 35-1. PODRx Field Descriptions  
Bits Name  
Description  
0Ð31 ODx Open-drain conÞguration. Determines whether the corresponding pin is actively driven as an output or is  
an open-drain driver. Note that bits OD0ÐOD3 are valid for PODRA and PODRC only.  
0 The I/O pin is actively driven as an output.  
1 The I/O pin is an open-drain driver. As an output, the pin is driven active-low, otherwise it is three-stated.  
35.2.2 Port Data Registers (PDATAÐPDATD)  
A read of a port data register (PDATx), shown in Figure 35-2, returns the data at the pin,  
independent of whether the pin is deÞned as an input or output. This allows detection of  
output conßicts at the pin by comparing the written data with the data on the pin.  
A write to the PDATx is latched and if the equivalent PDIR bit is conÞgured as an output,  
the value latched for that bit is driven onto its respective pin. PDATx can be read or written  
at any time and is not initialized.  
If a port pin is selected as a general-purpose I/O pin, it can be accessed through the port  
data register (PDATx). Data written to the PDATx is stored in an output latch. If a port pin  
is conÞgured as an output, the output latch data is gated onto the port pin. In this case, when  
PDATx is read, the port pin itself is read. If a port pin is conÞgured as an input, data written  
35-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
                     
Part IV. Communications Processor Module  
to PDATx is still stored in the output latch, but is prevented from reaching the port pin. In  
this case, when PDATx is read, the state of the port pin is read.  
Bits  
Field  
Reset  
R/W  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
1
1
1
1
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9 D10 D11 D12 D13 D14 D15  
Ñ
R/W  
0x10D10 (PDATA), 0x10D30 (PDATB), 0x10D50 (PDATC), 0x10D70 (PDATD)  
18 19 20 21 22 23 24 25 26 27 28 29  
Addr  
Bits  
16  
17  
30  
31  
Field  
Reset  
R/W  
D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31  
Ñ
R/W  
Addr  
0x10D12 (PDATA), 0x10D32 (PDATB), 0x10D52 (PDATC), 0x10D72 (PDATD)  
1
These bits are valid for PDATA and PDATC only  
Figure 35-2. Port Data Registers (PDATAÐPDATD)  
35.2.3 Port Data Direction Registers (PDIRAÐPDIRD)  
The port data direction register(PDIR), shown in Figure 35-3, is cleared at system reset.  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
1
1
1
1
Field DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 DR8 DR9 DR10 DR11 DR12 DR13 DR14 DR15  
Reset  
R/W  
Addr  
Bits  
0000_0000_0000_0000  
R/W  
0x10D00 (PDIRA), 0x10D20 (PDIRB), 0x10D40 (PDIRC), 0x10D60 (PDIRD)  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field DR16 DR17 DR18 DR19 DR20 DR21 DR22 DR23 DR24 DR25 DR26 DR27 DR28 DR29 DR30 DR31  
Reset  
R/W  
0000_0000_0000_0000  
R/W  
Addr  
0x10D02 (PDIRA), 0x10D22 (PDIRB), 0x10D42 (PDIRC), 0x10D62 (PDIRD)  
1
These bits are valid for PDIRA and PDIRC only  
Figure 35-3. Port Data Direction Register (PDIR)  
Table 35-2 describes PDIR Þelds.  
Table 35-2. PDIR Field Descriptions  
Bits Name  
Description  
0Ð31 DRx Direction. Indicates whether a pin is used as an input or an output. Note that bits DR0ÐDR3 are valid  
for PDIRA and PDIRC only.  
0 The corresponding pin is an input.  
1 The corresponding pin is an output.  
MOTOROLA  
Chapter 35. Parallel I/O Ports  
35-3  
           
Part IV. Communications Processor Module  
35.2.4 Port Pin Assignment Register (PPAR)  
The port pin assignment register (PPAR) is cleared at system reset.  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
1
1
1
1
Field DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15  
Reset  
R/W  
Addr  
Bits  
0000_0000_0000_0000  
R/W  
0x10D04 (PPARA), 0x10D24 (PPARB), 0x10D44 (PPARC), 0x10D64 (PPARD)  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field DD16 DD17 DD18 DD19 DD20 DD21 DD22 DD23 DD24 DD25 DD26 DD27 DD28 DD29 DD30 DD31  
Reset  
R/W  
0000_0000_0000_0000  
R/W  
Addr  
0x10D06 (PPARA), 0x10D26 (PPARB), 0x10D46 (PPARC), 0x10D66 (PPARD)  
1
These bits are valid for PPARA and PPARC only  
Figure 35-4. Port Pin Assignment Register (PPARAÐPPARD)  
Table 35-2 describes PPARx Þelds.  
Table 35-3. PPAR Field Descriptions  
Bits Name  
Description  
0Ð31 DDx Dedicated enable. Indicates whether a pin is a general-purpose I/O or a dedicated peripheral pin.  
Note that bits DD0ÐDD3 are valid for PPARA and PPARC only.  
0 General-purpose I/O. The peripheral functions of the pin are not used.  
1 Dedicated peripheral function. The pin is used by the internal module. The on-chip peripheral  
function to which it is dedicated can be determined by other bits such as those is the PDIR.  
35.2.5 Port Special Options Registers AÐD (PSORAÐPSORD)  
Figure 35-5 shows the port special options registers (PSORx).  
35-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
             
Part IV. Communications Processor Module  
Bits  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
1
1
1
1
Field SO0 SO1 SO2 SO3 SO4 SO5 SO6 SO7 SO8 SO9 SO10 SO11 SO12 SO13 SO14 SO15  
Reset  
R/W  
Addr  
Bits  
0000_0000_0000_0000  
R/W  
0x10D08 (PSORA), 0x10D28 (PSORB), 0x10D48 (PSORC), 0x10D68 (PSORD)  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Field SO16 SO17 SO18 SO19 SO20 SO21 SO22 SO23 SO24 SO25 SO26 SO27 SO28 SO29 SO30 SO31  
Reset  
R/W  
0000_0000_0000_0000  
R/W  
Addr  
0x10D0A (PSORA), 0x10D2A (PSORB), 0x10D4A (PSORC), 0x10D6A (PSORD)  
1
These bits are valid for PSORA and PSORC only  
Figure 35-5. Special Options Registers (PSORAÐPOSRD)  
PSOR bits are effective only if the corresponding PPARx[DDx] = 1 (a dedicated peripheral  
function). Table 35-4 describes PSORx Þelds.  
Table 35-4. PSORx Field Descriptions  
Bits Name  
Description  
0Ð31 SOx Special-option. Determines whether a pin conÞgured for a dedicated function (PPARx[DDx] = 1) uses  
option 1 or option 2. Note that bits SO0ÐSO3 are valid for PSORA and PSORC only. Options are  
described in Section 35.2, ÒPort Registers.Ó  
0 Dedicated peripheral function. Option 1.  
1 Dedicated peripheral function. Option 2.  
NOTE  
If the corresponding PPARx[DDx] = 1 (conÞgured as a general-purpose pin) before  
programming a PSORx or PDIRx bit, a pin might function for a short period as an unwanted  
dedicated function and cause unknown behavior.  
MOTOROLA  
Chapter 35. Parallel I/O Ports  
35-5  
   
Part IV. Communications Processor Module  
35.3 Port Block Diagram  
Figure 35-6 shows the functional block diagram.  
To/from peripheral bus  
Read  
To/from internal bus  
PDATx Write  
PDATx Read  
PDATx  
Latch  
0
Open  
Drain  
Control  
0
1
From DED OUT1  
From DED OUT2  
EN  
1
Pin  
PDIR  
PODR  
PPAR  
PSOR  
Default  
Input IN1  
0
To DED IN1  
1
PPAR & PSOR & PDIR  
Default  
Input IN2  
0
1
To DED IN2  
PPAR & PSOR & PDIR  
Register Name  
0
1
Description  
PPARx  
PSORx  
PDIRx  
PODRx  
PDATx  
General purpose  
Dedicated 1  
Input  
Dedicated  
Dedicated 2  
Output  
Port pin assignment  
Special operation  
1
Direction  
Regular  
0
Open drain  
1
Data  
1
Bidirectional signals must be programmed as inputs (PDIR = 0).  
Figure 35-6. Port Functional Operation  
35.4 Port Pins Functions  
Each pin can operate as a general purpose I/O pin or as a dedicated input or output pin.  
35-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Part IV. Communications Processor Module  
35.4.1 General Purpose I/O Pins  
Each one of the port pins is independently conÞgured as a general-purpose I/O pin if the  
corresponding port pin assignment register (PPAR) bit is cleared. Each pin is conÞgured as  
a dedicated on-chip peripheral pin if the corresponding PPAR bit is set.When the port pin  
is conÞgured as a general-purpose I/O pin, the signal direction for that pin is determined by  
the corresponding control bit in the port data direction register (PDIR). The port I/O pin is  
conÞgured as an input if the corresponding PDIR bit is cleared; it is conÞgured as an output  
if the corresponding PDIR bit is set. All PPAR and PDIR bits are cleared on total system  
reset, conÞguring all port pins as general-purpose input pins.  
If a port pin is selected as a general-purpose I/O pin, it can be accessed through the port  
data register (PDATx). Data written to the PDATx is stored in an output latch. If a port pin  
is conÞgured as an output, the output latch data is gated onto the port pin. In this case, when  
PDATx is read, the port pin itself is read. If a port pin is conÞgured as an input, data written  
to PDATx is still stored in the output latch, but is prevented from reaching the port pin. In  
this case, when PDATx is read, the state of the port pin is read.  
35.4.2 Dedicated Pins  
When a port pin is not conÞgured as a general-purpose I/O pin, it has a dedicated  
functionality, as described in the following tables. Note that if an input to a peripheral is not  
supplied from a pin, a default value is supplied to the on-chip peripheral as listed in the  
right-most column.  
NOTE  
Some output functions can be output on 2 different pins. For  
example, the output for BRG1 can come out on both PC31 and  
PD19. The user can freely conÞgure such functions to be  
output on two pins at once. However, there is typically no  
advantage in doing so unless there is a large fanout where it is  
advantageous to share the load between two pins.  
Many input functions can also come from two different pins;  
see Section 35.5, ÒPorts Tables.Ó  
35.5 Ports Tables  
Table 35-5 through Table 35-8 describe the ports functionality according to the  
conÞguration of the port registers (PPARx, PSORx, and PDIRx). Each pin can function as  
a general purpose I/O, one of two dedicated outputs, or one of two dedicated inputs.  
As shown in Figure 35-7, some input functions can come from two different pins for  
ßexibility. Secondary option programming is relevant only if primary option is  
programmed to the default value.  
MOTOROLA  
Chapter 35. Parallel I/O Ports  
35-7  
       
Part IV. Communications Processor Module  
PD4  
PA8  
Secondary option  
for SMC2 RxD  
Primary option  
for SMC2 RxD  
GND  
0
1
0
to SMC2 RxD  
Pin PD4  
1
Pin PA8  
PPARD[4] == 1 &  
PSORD[4] == 1 &  
PDIRD[4] == 0  
PPARA[8] == 1 &  
PSORA[8] == 0 &  
PDIRA[8] == 0  
Figure 35-7. Primary and Secondary Option Programming  
In the tables below, the default value for a primary option is simply a reference to the  
secondary option. In the secondary option, the programming is relevant only if the primary  
option is not used for the function.  
Table 35-5 shows the port A pin assignments.  
Table 35-5. Port AÑDedicated Pin Assignment (PPARA = 1)  
Pin Function  
PSORA = 0  
PSORA = 1  
Pin  
Default  
Input  
PDIRA = 0 (Input, or Default  
PDIRA = 1 (Output)  
PDIRA = 0 (Input)  
PDIRA = 1 (Output)  
Inout if SpeciÞed)  
Input  
PA31  
PA30  
FCC1:TxEnb  
UTOPIA master  
FCC1:TxEnb  
UTOPIA slave  
GND  
GND  
FCC1: COL  
MII  
GND  
FCC1: TxClav  
UTOPIA slave  
FCC1: TxClav  
UTOPIA master  
FCC1: TxClav0  
MPHY, master, direct  
polling  
FCC1: RTS  
FCC1: CRS  
MII  
GND  
PA29  
PA28  
PA27  
PA26  
FCC1:TxSOC  
UTOPIA  
FCC1:TX_ER  
MII  
FCC1: RxEnb  
UTOPIA master  
FCC1: RxEnb  
UTOPIA slave  
GND  
GND  
GND  
FCC1:TX_EN  
MII  
FCC1: RxSOC  
UTOPIA  
FCC1: RX_DV  
MII  
GND  
GND  
FCC1: RxClav  
UTOPIA slave  
FCC1: RxClav  
UTOPIA master  
FCC1: RxClav0  
MPHY, master, direct  
polling  
FCC1: RX_ER  
MII  
35-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
       
Part IV. Communications Processor Module  
Table 35-5. Port AÑDedicated Pin Assignment (PPARA = 1) (Continued)  
Pin Function  
PSORA = 0  
PSORA = 1  
Pin  
Default  
Input  
PDIRA = 0 (Input, or Default  
PDIRA = 1 (Output)  
PDIRA = 0 (Input)  
PDIRA = 1 (Output)  
Inout if SpeciÞed)  
Input  
1
PA25  
FCC1:TxD[0]  
UTOPIA 8  
MSNUM[0]  
FCC1:TxD[8]  
UTOPIA 16  
1
PA24  
PA23  
PA22  
PA21  
FCC1:TxD[1]  
UTOPIA 8  
FCC1:TxD[9]  
UTOPIA 16  
MSNUM[1]  
FCC1:TxD[2]  
UTOPIA 8  
FCC1: TxD[10]  
UTOPIA 16  
FCC1:TxD[3]  
UTOPIA 8  
FCC1: TxD[11]  
UTOPIA 16  
FCC1:TxD[4]  
UTOPIA 8  
FCC1:TxD[12]  
UTOPIA 16  
FCC1:TxD[3]  
MII/HDLC/transp.  
nibble  
PA20  
PA19  
FCC1:TxD[5]  
UTOPIA 8  
FCC1:TxD[13]  
UTOPIA 16  
FCC1:TxD[2]  
MII/HDLC/transp  
nibble  
FCC1:TxD[6]  
UTOPIA 8  
FCC1:TxD[14]  
UTOPIA 16  
FCC1:TxD[1]  
MII/HDLC/transp  
nibble  
MOTOROLA  
Chapter 35. Parallel I/O Ports  
35-9  
Part IV. Communications Processor Module  
Table 35-5. Port AÑDedicated Pin Assignment (PPARA = 1) (Continued)  
Pin Function  
PSORA = 0  
PSORA = 1  
Pin  
Default  
Input  
PDIRA = 0 (Input, or Default  
PDIRA = 1 (Output)  
PDIRA = 0 (Input)  
PDIRA = 1 (Output)  
Inout if SpeciÞed)  
Input  
PA18  
FCC1:TxD[7]  
UTOPIA 8  
FCC1:TxD[15]  
UTOPIA 16  
FCC1:TxD[0]  
MII/HDLC/transp  
nibble  
FCC1: TxD  
HDLC/Transp  
PA17  
FCC1: RxD[7]  
UTOPIA 8  
GND  
FCC1: RxD[15]  
UTOPIA 16  
FCC1: RxD[0]  
MII/HDLC/transp.  
nibble  
FCC1: RxD  
HDLC/transp.  
PA16  
PA15  
PA14  
PA13  
FCC1: RxD[6]  
UTOPIA 8  
FCC1: RxD[14]  
UTOPIA 16  
FCC1: RxD[1]  
MII/HDLC/transp  
nibble  
GND  
GND  
GND  
GND  
FCC1: RxD[5]  
UTOPIA 8  
FCC1: RxD[13]  
UTOPIA 16  
FCC1: RxD[2]  
MII/HDLC/transp  
nibble  
FCC1: RxD[4]  
UTOPIA 8  
FCC1: RxD[12]  
UTOPIA 16  
FCC1: RxD[3]  
MII/HDLC/transp  
nibble  
1
FCC1: RxD[3]  
UTOPIA 8  
MSNUM[2]  
FCC1: RxD[11]  
UTOPIA 16  
35-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part IV. Communications Processor Module  
Table 35-5. Port AÑDedicated Pin Assignment (PPARA = 1) (Continued)  
Pin Function  
PSORA = 0  
PSORA = 1  
Pin  
Default  
Input  
PDIRA = 0 (Input, or Default  
PDIRA = 1 (Output)  
PDIRA = 0 (Input)  
PDIRA = 1 (Output)  
Inout if SpeciÞed)  
Input  
1
PA12  
FCC1: RxD[2]  
UTOPIA 8  
FCC1: RxD[10]  
UTOPIA 16  
GND  
GND  
GND  
MSNUM[3]  
1
PA11  
PA10  
FCC1: RxD[1]  
UTOPIA 8  
FCC1: RxD[9] FCC1  
UTOPIA 16  
MSNUM[4]  
1
FCC1: RxD[0]  
UTOPIA 8  
MSNUM[5]  
FCC1: RxD[8]  
UTOPIA 16  
PA9  
PA8  
SMC2: SMTXD  
TDM_A1: L1TXD[0]  
Output  
GND  
GND  
SMC2: SMRXD  
(primary option)  
by PD4  
by PC0  
TDM_A1: L1RXD[0]  
Input, nibble  
TDM_A1: L1RXD  
Inout, serial  
PA7  
SMC2: SMSYN  
(primary option)  
TDM_A1: L1TSYNC/ GND  
GRANT  
PA6  
PA5  
TDM_A1: L1RSYNC  
IDMA4: DREQ  
GND  
GND  
SCC2: RSTRT  
FCC2: RxAddr[2]  
MPHY master  
PA4  
PA3  
PA2  
PA1  
PA0  
FCC2: RxAddr[1]  
MPHY master  
SCC2: REJECT  
CLK19  
VDD  
GND  
GND  
VDD  
IDMA4: DONE  
Inout  
VDD  
GND  
FCC2: RxAddr[0]  
MPHY master  
IDMA4: DACK  
IDMA3: DACK  
TDM_A2: L1RXD[1]  
Nibble  
FCC2:TxAddr[0]  
MPHY master  
CLK20  
FCC2:TxAddr[1]  
MPHY master  
SCC1: REJECT  
IDMA3: DONE  
Inout  
VDD  
GND  
SCC1: RSTRT  
FCC2: TxAddr[2]  
MPHY master  
IDMA3: DREQ  
1
MSNUM[0Ð4] is the sub-block code of the peripheral controller using SDMA; MSNUM[5] indicates which section,  
transmit or receive, is active during the transfer. See Section 18.2.4, ÒSDMA Transfer Error MSNUM Registers  
(PDTEM and LDTEM).Ó  
MOTOROLA  
Chapter 35. Parallel I/O Ports  
35-11  
 
Part IV. Communications Processor Module  
Table 35-6 shows the port B pin assignments.  
Table 35-6. Port B Dedicated Pin Assignment (PPARB = 1)  
Pin Function  
PSORB = 0  
PSORB = 1  
Pin  
Default  
Input  
PDIRB = 0 (Input or Default  
Inout if SpeciÞed) Input  
PDIRB = 1 (Output)  
PDIRB = 0 (Input)  
PDIRB = 1 (Output)  
PB31  
PB30  
PB29  
PB28  
PB27  
PB26  
PB25  
FCC2:TX_ER  
MII  
FCC2: RxSOC  
UTOPIA  
GND  
TDM_B2: L1TXD  
Inout  
GND  
GND  
FCC2: TxSOC  
UTOPIA  
FCC2: RX_DV  
MII  
GND  
GND  
GND  
GND  
GND  
TDM_B2: L1RXD  
Inout  
FCC2: RxClav  
UTOPIA slave  
FCC2: RxClav  
UTOPIA master  
FCC2:TX_EN  
MII  
TDM_B2:L1RSYNC GND  
FCC2: RTS  
FCC2: RX_ER  
MII  
SCC1:TXD  
TDM_B2:  
L1TSYNC/GRANT  
GND  
GND  
GND  
GND  
FCC2:TxD[0]  
UTOPIA 8  
FCC2: COL  
MII  
TDM_C2: L1TXD  
Inout  
FCC2:TxD[1]  
UTOPIA 8  
FCC2: CRS  
MII  
TDM_C2: L1RXD  
Inout  
FCC2:TxD[4]  
UTOPIA 8  
TDM_A1: L1TXD[3]  
Nibble  
TDM_C2:  
L1TSYNC/GRANT  
FCC2:TxD[3]  
MII/HDLC/transp.  
nibble  
PB24  
PB23  
PB22  
FCC2:TxD[5]  
UTOPIA 8  
FCC2:TxD[2]  
MII/HDLC/transp.  
nibble  
TDM_A1: L1RXD[3]  
Nibble  
GND  
GND  
GND  
TDM_C2:L1RSYNC GND  
FCC2:TxD[6]  
UTOPIA  
FCC2:TxD[1]  
MII/HDLC/transp.  
nibble  
TDM_A1: L1RXD[2]  
Nibble  
TDM_D2: L1TXD  
Inout  
GND  
GND  
FCC2:TxD[7]  
UTOPIA  
TDM_A1: L1RXD[1]  
Nibble  
TDM_D2: L1RXD  
Inout  
FCC2:TxD[0]  
MII/HDLC/transp.  
nibble  
FCC2:TxD  
HDLC/transp. serial  
PB21  
FCC2: RxD[7]  
UTOPIA 8  
FCC2: RxD[0]  
GND TDM_A1: L1TXD[2]  
Nibble  
TDM_D2:  
L1TSYNC/GRANT  
GND  
MII/HDLC/transp. nibble  
FCC2: RxD  
HDLC/transp.. serial  
35-12  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part IV. Communications Processor Module  
Table 35-6. Port B Dedicated Pin Assignment (PPARB = 1) (Continued)  
Pin Function  
PSORB = 0  
PSORB = 1  
Pin  
Default  
Input  
PDIRB = 0 (Input or Default  
Inout if SpeciÞed) Input  
PDIRB = 1 (Output)  
PDIRB = 0 (Input)  
PDIRB = 1 (Output)  
PB20  
FCC2: RxD[6]  
UTOPIA 8  
GND  
TDM_A1-L1TXD[1] TDM_D2:L1RSYNC GND  
Nibble  
FCC2: RxD[1]  
MII/HDLC/transp.  
nibble  
PB19  
PB18  
PB17  
FCC2: RxD[5]  
UTOPIA 8  
FCC2: RxD[2]  
GND  
GND  
TDM_D2: L1RQ  
TDM_A2: L1RXD[3] GND  
Nibble  
MII/HDLC/transp. nibble  
FCC2: RxD[4]  
UTOPIA 8  
FCC2: RxD[3]  
TDM_D2: L1CLKO TDM A2: L1RXD[2] GND  
Nibble  
MII/HDLC/transp. nibble  
TDM_A1: L1RQ  
FCC3: RX_DV  
MII  
GND  
GND  
CLK17  
CLK18  
GND  
GND  
PB16 TDM_A1: L1CLKO  
FCC3: RX_ER  
MII  
PB15  
PB14  
PB13  
FCC3: TX_ER  
MII  
SCC2: RXD  
(primary option)  
by  
PD28  
TDM_C1: L1TXD  
Inout  
(primary option)  
by  
PD28  
FCC3:TX_EN  
MII  
SCC3: RXD  
(primary option)  
by  
PD25  
TDM_C1: L1RXD  
Inout  
(primary option)  
by  
PD27  
TDM_B1: L1RQ  
FCC3: COL  
MII  
GND TDM_A2: L1TXD[1]  
Nibble  
TDM_C1:  
L1TSYNC/GRANT PD16  
by  
(primary option)  
PB12 TDM_B1: L1CLKO  
FCC3: CRS  
MII  
GND  
GND  
SCC2:TXD  
TDM_C1: L1RSYNC  
(primary option)  
by  
PD26  
PB11  
PB10  
PB9  
FCC2:TxD[0]  
UTOPIA 8  
FCC3: RxD[3]  
MII/HDLC/transp. nibble  
TDM_D1: L1TXD  
Inout  
(primary option)  
by  
PD25  
FCC2: TxD[1]  
UTOPIA 8  
FCC3: RxD[2]  
MII/HDLC/transp. nibble  
GND  
TDM_D1: L1RXD  
Inout  
(primary option)  
by  
PD24  
FCC2: TxD[2]  
UTOPIA 8  
FCC3: RxD[1]  
MII/HDLC/transp. nibble  
GND TDM_A2: L1TXD[2]  
Nibble  
TDM_D1:  
L1TSYNC/GRANT  
(primary option)  
by PD4  
PB8  
FCC2: TxD[3]  
UTOPIA 8  
FCC3: RxD[0]  
MII/HDLC/transp. nibble  
FCC3: RxD  
GND  
SCC3:TXD  
TDM_D1: L1RSYNC  
(primary option)  
by  
PD23  
HDLC/transp. serial  
MOTOROLA  
Chapter 35. Parallel I/O Ports  
35-13  
Part IV. Communications Processor Module  
Table 35-6. Port B Dedicated Pin Assignment (PPARB = 1) (Continued)  
Pin Function  
PSORB = 0  
PSORB = 1  
Pin  
Default  
Input  
PDIRB = 0 (Input or Default  
Inout if SpeciÞed) Input  
PDIRB = 1 (Output)  
PDIRB = 0 (Input)  
PDIRB = 1 (Output)  
PB7  
FCC3:TXD[0]  
MII/HDLC/transp.  
nibble  
FCC2: RxD[3]  
UTOPIA 8  
(primary option)  
by  
PC10  
TDM_A2: L1TXD[0]  
TDM_A2: L1TXD  
Inout, serial  
(primary option)  
by  
PD22  
Output, nibble  
FCC3: TXD  
HDLC/transp. serial  
PB6  
FCC3:TXD[1]  
MII/HDLC/transp.  
nibble  
FCC2: RxD[2]  
UTOPIA 8  
(primary option)  
by  
PC11  
TDM_A2: L1RXD  
Inout, serial  
TDM_A2: L1RXD[0]  
Input, nibble  
by  
PD21  
(primary option)  
PB5  
PB4  
FCC3:TXD[2]  
MII/HDLC/transp.  
nibble  
FCC2: RxD[1]  
UTOPIA 8  
(primary option)  
by  
PD10  
TDM_A2:  
L1TSYNC/GRANT  
(primary option)  
by PC9  
FCC3:TXD[3]  
MII/HDLC/transp.  
nibble  
FCC2: RxD[0]  
UTOPIA 8  
(primary option)  
by  
PD11  
FCC3: RTS  
TDM_A2: L1RSYNC  
(primary option)  
by  
PD20  
Table 35-7 shows the port C pin assignments.  
Table 35-7. Port C Dedicated Pin Assignment (PPARC = 1)  
Pin Function  
PSORC = 0  
PSORC = 1  
PDIRC = 0 (Input or Default  
PIN  
Default  
Input  
PDIRC = 1 (Output) PDIRC = 0 (Input)  
PDIRC = 1 (Output)  
Timer1:TOUT  
Inout if SpeciÞed)  
Input  
PC31  
PC30  
BRG1: BRGO  
CLK1  
CLK2  
CLK5  
CLK6  
FCC2:TxD[3]  
UTOPIA 8  
1
PC29  
PC28  
PC27  
BRG2: BRGO  
Timer2:TOUT  
CLK3/TIN2  
CLK4/TIN1  
CLK5  
CLK7  
CLK8  
GND  
SCC1: CTS  
SCC1: CLSN  
GND  
GND  
1
Ethernet  
(secondary option)  
1
SCC2: CTS  
SCC2: CLSN  
1
Ethernet  
(secondary option)  
FCC3: TxD  
HDLC/transp. serial  
FCC3: TxD[0]  
MII/HDLC/transp.  
nibble  
BRG3: BRGO  
35-14  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
 
Part IV. Communications Processor Module  
Table 35-7. Port C Dedicated Pin Assignment (PPARC = 1) (Continued)  
Pin Function  
PSORC = 0  
PSORC = 1  
PIN  
Default  
Input  
PDIRC = 0 (Input or Default  
PDIRC = 1 (Output) PDIRC = 0 (Input)  
PDIRC = 1 (Output)  
Inout if SpeciÞed)  
Input  
PC26  
PC25  
PC24  
PC23  
PC22  
Timer3:TOUT  
CLK6  
CLK7  
CLK8  
CLK9  
CLK10  
GND  
GND  
TMCLK  
real-time counter  
BRGO1  
FCC2:TxD[2]  
UTOPIA 8  
BRG4: BRGO  
Timer4: TOUT  
IDMA1: DACK  
FCC2:TxD[3]  
UTOPIA 8  
GND  
BRG5: BRGO  
CLK13  
CLK14  
IDMA1: DONE  
Inout  
by PD5  
(primary option)  
PC21  
BRG6: BRGO  
BRG7: BRGO  
BRG8: BRGO  
SMC2: SMTXD  
CLK11  
CLK15  
PC20  
PC19  
CLK12  
CLK13  
CLK16  
GND  
timer1/2:TGATE1  
timer3/4:TGATE2  
GND  
GND  
PC18  
PC17  
CLK14  
GND  
GND  
CLK15/TIN4  
PC16  
PC15  
CLK16/TIN3  
GND  
2
SCC1: CTS  
SCC1: CLSN  
Ethernet  
by PC5  
FCC1:TxAddr[0]  
MPHY, master  
FCC1:TxAddr[0]  
GND  
GND  
GND  
GND  
GND  
MPHY, slave  
FCC2:TxAddr[4]  
MPHY, slave  
(primary option)  
2
PC14  
PC13  
PC12  
SCC1: CD  
SCC1: RENA  
Ethernet  
GND  
by PC4  
GND  
FCC1: RxAddr[0]  
MPHY, master  
FCC1: RxAddr[0]  
MPHY, slave  
FCC2: RxAddr[4]  
MPHY, slave  
2
TDM_D1: L1RQ  
SI1: L1ST3  
SCC2: CTS  
SCC2: CLSN  
Ethernet  
FCC1:TxAddr[1]  
MPHY, master  
FCC1:TxAddr[1]  
MPHY, slave  
FCC2: TxAddr[3]  
MPHY, slave  
(primary option)  
2
SCC2: CD  
SCC2: RENA  
Ethernet  
FCC1: RxAddr[1]  
MPHY, master  
FCC1: RxAddr[1]  
MPHY, slave  
FCC2: RxAddr[3]  
MPHY, slave  
1
PC11 TDM_D1: L1CLKO  
SCC3: CTS  
SCC3: CLSN  
by PC8 TDM_A2: L1TXD[3]  
Nibble  
FCC2: RxD[2]  
UTOPIA 8  
1
Ethernet  
(primary option)  
(secondary option)  
35-15  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part IV. Communications Processor Module  
Table 35-7. Port C Dedicated Pin Assignment (PPARC = 1) (Continued)  
Pin Function  
PSORC = 0  
PSORC = 1  
PIN  
Default  
Input  
PDIRC = 0 (Input or Default  
PDIRC = 1 (Output) PDIRC = 0 (Input)  
PDIRC = 1 (Output)  
Inout if SpeciÞed)  
Input  
1
PC10  
PC9  
FCC1: TxD[2]  
UTOPIA 16  
SCC3: CD  
SCC3: RENA  
Ethernet  
GND  
SI1: L1ST4  
strobe  
FCC2: RxD[3]  
UTOPIA  
GND  
(secondary option)  
FCC1:TxD[1]  
UTOPIA 16  
SCC4: CTS  
SCC4: CLSN  
Ethernet  
by PC3  
SI2: L1ST1  
strobe  
TDM_A2: L1TSYNC/ GND  
GRANT  
(secondary option)  
1
(primary option)  
1
PC8  
PC7  
FCC1:TxD[0]  
UTOPIA 16  
SCC4: CD  
SCC4: RENA  
Ethernet  
GND  
GND  
SI2: L1ST2  
Strobe  
SCC3: CTS  
(secondary option)  
GND  
GND  
2
TDM_C1: L1RQ  
FCC1: CTS  
FCC1:TxAddr[2]  
MPHY master,  
FCC1:TxAddr[2]  
MPHY, slave,  
multiplexed: polling  
multiplexed polling  
FCC1:TxClav1  
2
MPHY, master, direct  
polling  
FCC2: TxAddr[2]  
MPHY, slave,  
multiplexed polling  
2
PC6  
TDM_C1: L1CLKO  
FCC1: CD  
GND  
FCC1: RxAddr[2]  
MPHY, master,  
FCC1: RxAddr[2]  
MPHY, slave,  
GND  
multiplexed polling  
multiplexed polling)  
FCC1: RxClav1  
2
MPHY, master, direct  
polling  
FCC2: RxAddr[2]  
MPHY, slave,  
multiplexed polling  
PC5  
PC4  
PC3  
PC2  
FCC2:TxClav  
UTOPIA, slave  
FCC2:TxClav  
UTOPIA, master  
GND  
GND  
GND  
GND  
SI2: L1ST3  
Strobe  
FCC2: CTS  
GND  
GND  
GND  
FCC2: RxEnb  
UTOPIA, master  
FCC2: RxEnb  
UTOPIA, slave  
SI2: L1ST4  
Strobe  
FCC2: CD  
1
FCC2:TxD[2]  
UTOPIA 8  
FCC3: CTS  
IDMA2: DACK  
SCC4: CTS  
(secondary option)  
FCC2:TxD[3]  
UTOPIA 8  
FCC3: CD  
IDMA2: DONE  
Inout  
V
DD  
PC1  
PC0  
BRG6: BRGO  
BRG7: BRGO  
IDMA2: DREQ  
IDMA1: DREQ  
GND  
GND  
TDM_A2: L1RQ  
1
TDM_A2: L1CLKO  
SMC2: SMSYN  
(secondary option)  
GND  
1
2
Available only when the primary option for this function is not used.  
MPHY Address pins 3,4 (master mode) can come from FCC2, depending on CMXUAR programming. (See  
Section 15.4.1, ÒCMX UTOPIA Address Register (CMXUAR).Ó).  
35-16  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
   
Part IV. Communications Processor Module  
Table 35-8 shows the port D pin assignments.  
Table 35-8. Port D Dedicated Pin Assignment (PPARD = 1)  
Pin Function  
PSORD = 0  
PSORD = 1  
Pin  
Default  
Input  
PDIRD = 0 (Input, or Default  
PDIRD = 1 (Output)  
PDIRD = 0 (Input)  
PDIRD = 1 (Output)  
Inout if SpeciÞed)  
Input  
PD31  
PD30  
SCC1: RXD  
GND  
GND  
FCC2:TxEnb  
UTOPIA master  
FCC2:TxEnb  
UTOPIA slave  
SCC1: TXD  
1
2
PD29  
SCC1: RTS  
SCC1:TENA  
Ethernet  
FCC1: RxAddr[3]  
MPHY, master,  
FCC1: RxAddr[3]  
MPHY, slave,  
GND  
multiplexed polling  
FCC2: RxAddr[4]  
MPHY, master,  
multiplexed polling  
2
FCC1: RxClav2  
MPHY, master, direct  
polling  
multiplexed polling  
FCC2: RxAddr[1]  
MPHY, slave,  
multiplexed polling  
3
3
PD28  
PD27  
PD26  
PD25  
PD24  
PD23  
PD22  
PD21  
FCC1:TxD[7]  
UTOPIA 16 bit  
SCC2: RXD  
(secondary option)  
GND  
GND  
GND  
GND  
GND  
GND  
TDM_C1: L1TXD  
Inout  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
(secondary option)  
3
SCC2:TXD  
FCC1: RxD[7]  
UTOPIA 16  
TDM_C1: L1RXD  
Inout  
(secondary option)  
3
SCC2: RTS  
SCC2:TENA  
Ethernet  
FCC1: RxD[6]  
UTOPIA 16  
TDM_C1: L1RSYNC  
(secondary option)  
3
3
FCC1:TxD[6]  
UTOPIA 16  
SCC3: RXD  
(secondary option)  
TDM_D1: L1TXD  
Inout  
(secondary option)  
3
SCC3:TXD  
FCC1: RxD[5]  
UTOPIA 16  
TDM_D1: L1RXD  
Inout  
(secondary option)  
3
SCC3: RTS  
SCC3:TENA  
Ethernet  
FCC1: RxD[4]  
UTOPIA 16  
TDM_D1: L1RSYNC  
(secondary option)  
3
3
FCC1:TxD[5]  
UTOPIA 16  
SCC4: RXD  
GND TDM_A2: L1TXD[0]  
Output, nibble  
TDM_A2: L1TXD  
Inout, serial  
(secondary option)  
(secondary option)  
3
SCC4:TXD  
FCC1: RxD[3]  
UTOPIA 16  
GND  
TDM_A2: L1RXD  
Inout, serial  
3
TDM_A2: L1RXD[0]  
Input, nibble  
(secondary option)  
MOTOROLA  
Chapter 35. Parallel I/O Ports  
35-17  
 
Part IV. Communications Processor Module  
Table 35-8. Port D Dedicated Pin Assignment (PPARD = 1) (Continued)  
Pin Function  
PSORD = 0  
PSORD = 1  
Pin  
Default  
Input  
PDIRD = 0 (Input, or Default  
PDIRD = 1 (Output)  
PDIRD = 0 (Input)  
PDIRD = 1 (Output)  
Inout if SpeciÞed)  
Input  
3
PD20  
PD19  
SCC4: RTS  
SCC4: TENA  
Ethernet  
FCC1: RxD[2]  
UTOPIA 16  
GND  
TDM_A2: L1RSYNC  
(secondary option)  
GND  
1
2
FCC1:TxAddr[4]  
FCC1:TxAddr[4]  
MPHY, slave,  
multiplexed polling  
FCC1: TxClav3  
MPHY, master, direct  
polling  
GND  
BRG1: BRGO  
SPI: SPISEL  
V
DD  
MPHY, master,  
multiplexed polling  
FCC2: TxAddr[3]  
MPHY, master,  
2
multiplexed polling  
FCC2: TxAddr[0]  
MPHY, slave,  
multiplexed polling  
1
2
PD18  
FCC1: RxAddr[4]  
FCC1: RxAddr[4]  
MPHY, slave,  
GND  
SPI: SPICLK  
Inout  
GND  
MPHY, master,  
multiplexed polling  
FCC2: RxAddr[3]  
MPHY, master,  
multiplexed polling  
2
FCC1: RxClav3  
MPHY, master, direct  
polling  
multiplexed polling  
FCC2: RxAddr[0]  
MPHY, slave,  
multiplexed polling  
PD17  
PD16  
BRG2: BRGO  
FCC1: RxPrty  
UTOPIA  
GND  
SPI: SPIMOSI  
Inout  
V
DD  
FCC1:TxPrty  
UTOPIA  
TDM_C1: L1TSYNC/ GND  
SPI: SPIMISO  
Inout  
SPIMO  
SI  
3
GRANT  
(secondary option)  
PD15  
PD14  
PD13  
PD12  
PD11  
TDM_C2: L1RQ  
TDM_C2: L1CLKO  
SI1: L1ST1  
FCC1: RxD[1]  
UTOPIA 16  
GND  
GND  
I2C: I2CSDA  
Inout  
V
DD  
FCC1: RxD[0]  
UTOPIA 16  
I2C: I2CSCL  
Inout  
GND  
GND  
GND  
TDM_B1: L1TXD  
Inout  
SI1: L1ST2  
TDM_B1: L1RXD  
Inout  
3
TDMB2: L1RQ  
FCC2: RxD[0]  
UTOPIA 8  
GND  
GND  
TDM_B1: L1TSYNC/ GND  
GRANT  
(secondary option)  
3
PD10  
PD9  
TDMB2: L1CLKO  
SMC1: SMTXD  
FCC2: RxD[1]  
UTOPIA 8  
BRG4: BRGO  
BRG3: BRGO  
TDM_B1: L1RSYNC GND  
(secondary option)  
FCC2: RxPrty  
UTOPIA  
GND  
35-18  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Part IV. Communications Processor Module  
Table 35-8. Port D Dedicated Pin Assignment (PPARD = 1) (Continued)  
Pin Function  
PSORD = 0  
PSORD = 1  
Pin  
Default  
Input  
PDIRD = 0 (Input, or Default  
PDIRD = 1 (Output)  
PDIRD = 0 (Input)  
PDIRD = 1 (Output)  
BRG5: BRGO  
Inout if SpeciÞed)  
Input  
PD8  
PD7  
FCC2:TxPrty  
UTOPIA  
SMC1: SMRXD  
SMC1: SMSYN  
GND  
GND  
1
2
FCC1:TxAddr[3]  
FCC1:TxAddr[3]  
MPHY, slave,  
GND  
MPHY, master,  
multiplexed polling  
FCC2: TxAddr[4]  
MPHY, master,  
multiplexed polling  
2
FCC1:TxClav2  
MPHY, master, direct  
polling  
multiplexed polling  
FCC2: TxAddr[1]  
MPHY, slave,  
multiplexed polling  
PD6  
PD5  
FCC1:TxD[4]  
UTOPIA 16  
IDMA1: DACK  
3
FCC1:TxD[3]  
UTOPIA 16  
IDMA1: DONE  
Inout  
V
DD  
(secondary option)  
3
PD4  
BRG8: BRGO  
TDM_D1: L1TSYNC/ GND  
GRANT  
(secondary option)  
FCC3: RTS  
SMC2: SMRXD  
(secondary option)  
GND  
3
1
2
3
MPHY address pins 3 and 4 (master mode) can come from FCC2, depending on CMXUAR programming. (See  
Section 15.4.1, ÒCMX UTOPIA Address Register (CMXUAR).Ó)  
MPHY address pins 0Ð4 (slave mode) can come from FCC2, depending on CMXUAR programming. (See  
Section 15.4.1, ÒCMX UTOPIA Address Register (CMXUAR).Ó)  
Available only when the primary option for this function is not used.  
35.6 Interrupts from Port C  
The port C lines associated with CDx and CTSx have a mode of operation where the pin  
can be internally connected to the SCC/FCC but can also generate interrupts. Port C still  
detects changes on the CTS and CD pins and asserts the corresponding interrupt request,  
but the SCC/FCC simultaneously uses CTS and/or CD to automatically control operation.  
This lets the user fully implement protocols V.24, X.21, and X.21 bis (with the assistance  
of other general-purpose I/O lines).  
To conÞgure a port C pin as a CTS or CD pin that connects to the SCC/FCC and generates  
interrupts, these steps should be followed:  
1. Write the corresponding PPARC bit with a 1 and PSORC bit with 0.  
2. Write the corresponding PDIRC bit with a zero.  
3. Set the SIEXR bit (in the interrupt controller) to determine which edges cause  
interrupts.  
MOTOROLA  
Chapter 35. Parallel I/O Ports  
35-19  
           
Part IV. Communications Processor Module  
4. Write the corresponding SIMR (mask register) bit with a 1 to allow interrupts to be  
generated to the core.  
5. The pin value can be read at any time using PDATC.  
Note  
After connecting CTS or CD to the SCC/FCC, the user must  
also choose the normal operation mode in GSMR[DIAG] to  
enable and disable SCC/FCC transmission and reception with  
these pins.  
The IDMA-DREQ lines in ports C can assert an external request to the CP instead of  
asserting an interrupt to the core. Each line can be programmed to assert an interrupt request  
upon a high-to-low change or any change as conÞgured in SIEXR.  
Note  
Do not program the IDMAx-DREQ pins to assert external  
requests to the IDMA, unless the IDMA is used. Otherwise,  
erratic operation occurs.  
35-20  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Appendix A  
Register Quick Reference Guide  
A0  
AT0 his section provides a brief guide to the core registers.  
A.1 PowerPC RegistersÑUser Registers  
The implements the user-level registers deÞned by the PowerPC architecture except those  
required for supporting ßoating-point operations (the ßoating-point register Þle (FPRs) and  
the ßoating-point status and control register (FPSCR)). User-level, PowerPC registers are  
listed in Table A-1 and Table A-2. Table A-2 lists user-level special-purpose registers  
(SPRs).  
Table A-1. User-Level PowerPC Registers (Non-SPRs)  
Description  
Name  
Comments  
Access Level Serialize Access  
General-purpose  
registers  
GPRs The thirty-two 32-bit (GPRs) are used for source  
and destination operands. See the  
Programming Environments Manual for more  
information.  
User  
Ñ
Condition register  
CR  
See the Programming Environments Manual  
User  
Only mtcrf  
Table A-2 lists SPRs deÞned by the PowerPC architecture implemented on the MPC8260.  
Table A-2. User-Level PowerPC SPRs  
SPR Number  
Name  
Comments  
Serialize Access  
Decimal SPR [5Ð9] SPR [0Ð4]  
1
8
9
00000  
00000  
00000  
00001  
01000  
01001  
XER  
LR  
See the Programming Write: Full sync  
Environments Manual Read: Sync relative to load/store operations  
See the Programming No  
Environments Manual  
CTR  
See the Programming No  
Environments Manual  
1
2
268  
269  
01000  
01000  
01100  
01101  
TBL read  
TBU read  
See the Programming Write (as a store)  
Environments Manual  
1
2
Extended opcode for mftb, 371 rather than 339.  
Any write (mtspr) to this address causes an implementation-dependent software emulation exception.  
MOTOROLA  
Appendix A.Register Quick Reference Guide  
A-1  
             
Appendixes  
A.2 PowerPC RegistersÑSupervisor Registers  
All supervisor-level registers implemented on the MPC8260 are SPRs, except for the machine  
state register (MSR), described in Table A-3.  
Table A-3. Supervisor-Level PowerPC Registers (Non-SPR)  
Description  
Name  
Comments  
Serialize Access  
Machine state register MSR See the Programming Environments Manual  
and MPC603e RISC Microprocessor UserÕs  
Manual  
Write fetch sync  
Table A-4 lists supervisor-level SPRs defined by the PowerPC architecture.  
Table A-4. Supervisor-Level PowerPC SPRs  
SPR Number  
Name  
Comments  
Serialize Access  
Decimal SPR[5Ð9] SPR[0Ð4]  
18  
00000  
10010  
DSISR  
See the Programming Environments Write: Full sync  
Manual Read: Sync relative to  
load/store operations  
19  
00000  
10011  
DAR  
See the Programming Environments Write: Full sync  
Manual Read: Sync relative to load/  
store operations  
22  
26  
27  
00000  
00000  
00000  
10110  
11010  
11011  
DEC  
See the Programming Environments Write  
Manual  
SRR0  
SRR1  
See the Programming Environments Write  
Manual  
See the Programming Environments Write  
Manual  
272  
273  
274  
275  
284  
285  
287  
01000  
01000  
01000  
01000  
01000  
01000  
01000  
10000  
10001  
10010  
10011  
11100  
11101  
11111  
SPRG0  
SPRG1  
SPRG2  
SPRG3  
See the Programming Environments Write  
Manual  
1
TBL write See the Programming Environments Write (as a store)  
Manual  
TBU write  
1
PVR  
See Section 2.3.1.2.4, ÒProcessor  
Version Register (PVR).Ó  
No (read-only register)  
1
Any read (mftb) to this address causes an implementation-dependent software emulation exception.  
A-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
         
Appendixes  
A.3 MPC8260-SpeciÞc SPRs  
Table A-2 and Table A-5 list SPRs speciÞc to the MPC8260. Supervisor-level registers are  
described in Table A-5.  
Table A-5. MPC8260-Specific Supervisor-Level SPRs  
SPR Number  
Name  
Comments  
Serialize Access  
Decimal SPR[5Ð9] SPR[0Ð4]  
976  
977  
978  
979  
980  
981  
982  
1008  
11110  
11110  
11110  
11110  
11110  
11110  
11110  
11111  
10000  
10001  
10010  
10011  
10100  
10101  
10110  
10000  
DMISS  
DCMP  
HASH1  
HASH2  
IMISS  
ICMP  
See the MPC603e RISC  
Microprocessor UserÕs Manual  
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
See the MPC603e RISC  
Microprocessor UserÕs Manual  
See the MPC603e RISC  
Microprocessor UserÕs Manual  
See the MPC603e RISC  
Microprocessor UserÕs Manual  
See the MPC603e RISC  
Microprocessor UserÕs Manual  
See the MPC603e RISC  
Microprocessor UserÕs Manual  
RPA  
See the MPC603e RISC  
Microprocessor UserÕs Manual  
HID0  
See Section 2.3.1.2.1, ÒHardware  
Implementation-Dependent Register 0  
(HID0).Ó  
1009  
11111  
10001  
HID1  
See Section 2.3.1.2.2, ÒHardware  
Implementation-Dependent Register 1  
(HID1).Ó  
Ñ
1010  
1011  
11111  
11111  
10010  
10011  
IABR  
HID2  
See the MPC603e RISC  
Microprocessor UserÕs Manual  
Ñ
Ñ
See Section 2.3.1.2.3, ÒHardware  
Implementation-Dependent Register 2  
(HID2).Ó  
MOTOROLA  
Appendix A.Register Quick Reference Guide  
A-3  
     
Appendixes  
A-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
INDEX  
no-pipeline mode, 8-26  
one-level pipeline mode, 8-26  
overview, 8-1  
Numerics  
603e features list, 2-3  
60x bus  
pipeline control, 8-26  
port size device interfaces, 8-17  
processor state signals, 8-32  
PSDMR register, 10-21  
single-MPC8260 bus mode, 8-2  
TBST signal, 8-13  
TCn signals, 8-13  
terminology, 8-1  
TESCRx registers, 10-33  
TLBISYNC input, 8-33  
TSIZn signals, 8-13  
60x-compatible mode  
60x-compatible bus mode, 8-3  
address latch enable (ALE), 10-11  
BUFCMD, 10-42  
EAMUX signal, 10-41  
MAR, 10-77  
overview, 10-101  
size calculation, 8-19  
60x-to-local bus transaction priority, 10-8  
address  
arbitration, 8-7  
TTn signals, 8-10  
write cycle data bus contents, 8-19  
60x bus memory controller, see Memory controller  
ARTRY, 8-23  
operations, 8-7  
pipelining, 8-9  
timing configuration, 8-25  
transfer attribute signals, 8-10  
transfer termination, 8-23  
bandwidth control on the IDMA channel, 18-12  
bus protocol  
A
Accessing dual-port RAM, 13-15  
Acronyms and abbreviated terms, list, lxi, I-lxviii,  
II-ii, III-iii, IV-iv  
address pipelining, 8-7  
arbitration phase, 8-5  
overview, 8-4  
split-bus transactions, 8-7  
configuration, 8-2  
data  
AppleTalk mode  
GSMR, 25-3  
programming example, 25-3  
PSMR, 25-4  
TODR, 25-4  
ATM controller  
asserting TEA, 8-30  
AAL1 sequence number protection table, 29-78  
AALn RxBD, 29-6, 29-69  
AALn TxBD, 29-5, 29-74  
ABR flow control, 29-8, 29-20  
address compression, 29-15  
ATM layer statistics, 29-33  
ATM memory structure, 29-37  
ATM pace control (APC) unit  
ATM service types, 29-8  
configuration, 29-93  
data structures, 29-61  
modes, 29-8  
overview, 29-8  
parameter tables, 29-62  
priority table, 29-63  
data bus arbitration, 8-26  
data bus transfers, 8-27  
data streaming mode, 8-27  
effect of ARTRY assertion, 8-28  
normal termination, 8-27  
operations, 8-26  
port size data bus transfers and PSDVAL  
termination, 8-28  
data transfers  
alignment, 8-14  
burst ordering, 8-14  
port size, 8-16  
extended transfer mode, 8-20  
extended write cycle data bus contents, 8-21  
little-endian mode, 8-33  
LSDMR register, 10-24  
lwarx/stwcx. support, 8-33  
MEI protocol, 8-31  
scheduling mechanism, 29-9  
scheduling tables, 29-63  
traffic type, 29-11  
UBR+ traffic, 29-13  
memory coherency, 8-31  
MOTOROLA  
Index  
Index-1  
INDEX  
VBR traffic, 29-12  
overview, 29-32  
ATM TRANSMIT command, 29-90  
ATM-to-ATM data forwarding, 29-37  
ATM-to-TDM interworking, 29-34  
buffer descriptors, 29-64  
exceptions, 29-79  
external rate mode, 29-6  
FCCE, 29-87  
FCCM, 29-87  
features list, 29-2  
FPSMR, 29-85  
FTIRRx, 29-88  
GFMR register, 29-85  
global mode entry (GMODE), 29-41  
internal rate mode, 29-6  
interrupt queues, 29-79  
maximum performance configuration, 29-92  
OAM performance monitoring, 29-29, 29-60  
OAM support, 29-27  
operations and maintenance (OAM) support, 29-27  
overview, 29-4  
parameter RAM, 29-37  
RxBD extension (AAL5/AAL1), 29-73  
TxBD extension (AAL5/AAL1), 29-78  
user-defined RxBD extension  
(AAL5/AAL1), 29-73  
user-defined TxBD extension  
(AAL5/AAL1), 29-78  
UTOPIA interface, 29-82  
VCI filtering, 29-40  
VCI/VPI address lookup, 29-14  
VC-level address compression tables  
(VCLT), 29-18  
VP-level address compression table  
(VPLT), 29-17  
B
Baud-rate generator (BRG)  
BRGCLK, 34-2  
memory map, 3-8  
BCR (bus configuration register), 4-25  
BDLE (SCC BISYNC DLE) register, 22-8  
BISYNC mode  
performance monitoring, 29-8  
performance, maximum (configuration), 29-92  
programming model, 29-85  
receive connection table (RCT)  
AALn protocol-specific RCTs, 29-46  
ATM channel code, 29-42  
overview, 29-41  
commands, 22-5  
control character recognition, 22-6  
error handling, 22-9  
frame reception, 22-3  
frame transmission, 22-2  
frames, classes, 22-1  
memory map, 22-4  
overview, 22-1  
parameter RAM, 22-3  
programming example, 22-18  
programming the controller, 22-17  
receiving synchronization sequence, 22-9  
RxBD, 22-12  
raw cell queue, 29-19  
RCT entry format, 29-44  
registers, 29-85  
RxBD, 29-69  
RxBD extension, 29-73  
SRTS generation using external logic, 29-91  
transmit connection table (TCT)  
AALn protocol-specific TCTs, 29-54  
ATM channel code, 29-42  
overview, 29-41  
TCT entry format, 29-51  
transmit connection table extension (TCTE)  
ABR protocol-specific, 29-58  
ATM channel code, 29-42  
overview, 29-41  
sending synchronization sequence, 22-9  
TxBD, 22-14  
Block diagrams  
cascaded mode, 17-4  
communications processor (CP), 13-5  
communications processor module (CPM), 13-3  
CPM multiplexing logic (CMX), 15-2  
DPLL receiver, 19-22  
dual-bus architecture, 10-3  
dual-port RAM, 13-15  
Fast Ethernet, 30-3  
UBR+ protocol-specific, 29-57  
VBR protocol-specific, 29-56  
transmit rate modes, 29-6  
TxBD, 29-74  
FCC overview, 28-3  
2
I C controller, 34-1  
TxBD extension, 29-78  
IEEE 1149.1 test access port, 12-2  
parallel I/O ports, 35-6  
PLL block diagram, 9-5  
SCC block diagram, 19-2  
serial interface, 14-2  
serial peripheral interface (SPI), 33-1  
UDC extended address mode, 29-33  
UEAD_OFFSET determination, 29-40  
UNI statistics table, 29-78  
user-defined cells (UDC)  
extended address mode, 29-33  
Index-2  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
INDEX  
system interface unit (SIU)  
periodic interrupt timer, 4-5  
SIU block diagram, 4-1  
software watchdog timer, 4-7  
system configuration/protection logic, 4-3  
time counter (TMCNT), 4-5  
system PLL, 9-5  
timers, 17-1  
Branch processing unit overview, 2-6  
BRGCLK, 34-2  
BRn (base registers), 10-14  
BSYNC (BISYNC SYNC) register, 22-7  
BUFCMD (external address and command  
buffers), 10-42  
Buffer descriptors  
ATM controller  
receive, 29-65, 29-69  
transmit, 29-64, 29-74  
BISYNC mode, 22-12  
fast communications controllers (FCCs)  
Fast Ethernet mode  
receive, 30-23  
transmit, 30-26  
HDLC mode  
receive, 31-9  
transmit, 31-12  
Byte stuffing, 22-1  
Byte-select signals, 10-75  
C
Cascaded mode, 17-3  
CHAMR (channel mode register), 27-10  
CHAMR (channel mode register,  
transparent mode), 27-13  
Chip-select  
assertion timing, 10-53  
chip-select machine, 10-51  
signals, 10-74  
write enable deassertion timing, 10-54  
Clock glitch detection, 19-26  
Clocks  
basic power structure, 9-10  
clock divider, 9-6  
clock unit, 9-1  
external clock inputs, 9-5  
general system clocks, 9-7  
input clock interface, 9-1  
internal clock signals, 9-6  
main PLL, 9-5  
memory map, 3-4  
OSCM, 9-1  
overview, 9-1  
PLL block diagram, 9-5  
PLL pins, 9-7  
overview  
receive, 28-9  
transmit, 28-9  
SCC clock glitch detection, 19-26  
SCCR, 9-8  
SCMR, 9-9  
GCI mode  
monitor channel, 26-32  
HDLC mode, 21-8  
skew elimination, 9-6  
2
I C controller  
receive, 34-13  
CMXFCR (CMX FCC clock route register), 15-12  
CMXSCR (CMX SCC clock route register), 15-14  
CMXSI1CR (CMX SI1 clock route register), 15-10  
CMXSI2CR (CMX SI2 clock route register), 15-11  
CMXSMR (CMX SMC clock route register), 15-17  
CMXUAR (CMX UTOPIA address register), 15-7  
Commands  
ATM TRANSMIT command, 29-90  
fast communications controllers (FCCs)  
Ethernet mode  
transmit, 34-14  
IDMA emulation  
auto buffer, 18-15  
IDMA buffers, 18-23  
multi-channel controllers (MCCs)  
receive, 27-21  
transmit, 27-23  
overview, 19-10  
serial management controllers (SMCs), 26-5  
serial peripheral interface (SPI)  
receive, 33-14  
transmit, 33-15  
transparent mode  
serial communications controllers (SCCs), 23-9  
serial management controllers (SMCs), 26-26  
UART mode  
serial communications controllers (SCCs), 20-15  
serial management controllers (SMCs), 26-14  
Bus interface  
receive commands, 30-13  
transmit commands, 30-12  
HDLC mode  
receive commands, 31-6  
transmit commands, 31-5  
I C controller, 34-11  
2
IDMA emulation, 18-26  
multi-channel controllers (MCCs)  
receive commands, 27-17  
serial peripheral interface (SPI), 33-12  
hierarchical bus interface example, 10-100  
BxTx (byte-select signals), 10-75  
MOTOROLA  
Index  
Index-3  
INDEX  
Communications processor (CP)  
block diagram, 13-5  
execution from RAM, 13-7  
features list, 13-4  
operations and maintenance (OAM)  
support, 29-27  
overview, 29-4  
parameter RAM, 29-37  
interfacing with the core, 13-6  
memory map, 3-9  
performance monitoring, 29-8  
performance, maximum (configuration), 29-92  
programming model, 29-85  
receive connection table (RCT)  
AALn protocol-specific RCTs, 29-46Ð29-50  
ATM channel code, 29-42  
overview, 29-41  
microcode execution from RAM, 13-7  
microcode revision number, 13-10  
peripheral interface, 13-6  
PowerPC core interface, 13-6  
RCCR, 13-7  
REV_NUM, 13-10  
RTSCR, 13-9  
RTSR, 13-10  
Communications processor module (CPM)  
ATM controller  
raw cell queue, 29-19  
RCT entry format, 29-44  
registers, 29-85  
RxBD, 29-69  
RxBD extension, 29-73  
AAL1 sequence number protection table, 29-78  
AALn RxBD, 29-6, 29-69  
AALn TxBD, 29-5, 29-74  
ABR flow control, 29-8, 29-20  
address compression, 29-15  
ATM layer statistics, 29-33  
ATM memory structure, 29-37  
ATM pace control (APC) unit  
ATM service types, 29-8  
configuration, 29-93  
SRTS generation using external logic, 29-91  
transmit connection table (TCT)  
AALn protocol-specific TCTs, 29-54Ð29-56  
ATM channel code, 29-42  
overview, 29-41  
TCT entry format, 29-51  
transmit connection table extension (TCTE)  
ABR protocol-specific, 29-58  
ATM channel code, 29-42  
overview, 29-41  
data structure, 29-61  
modes, 29-8  
overview, 29-8  
parameter tables, 29-62  
priority table, 29-63  
UBR+ protocol-specific, 29-57  
VBR protocol-specific, 29-56  
transmit rate modes, 29-6  
TxBD, 29-74  
TxBD extension, 29-78  
scheduling mechanism, 29-9  
scheduling tables, 29-63  
traffic type, 29-11  
UBR+ traffic, 29-13  
VBR traffic, 29-12  
ATM TRANSMIT command, 29-90  
ATM-to-ATM data forwarding, 29-37  
ATM-to-TDM interworking, 29-34  
buffer descriptors, 29-64  
exceptions, 29-79  
UDC extended address mode, 29-33  
UEAD_OFFSET determination, 29-40  
UNI statistics table, 29-78  
user-defined cells (UDC)  
extended address mode, 29-33  
overview, 29-32  
RxBD extension (AAL5/AAL1), 29-73  
TxBD extension (AAL5/AAL1), 29-78  
user-defined RxBD extension  
(AAL5/AAL1), 29-73  
external rate mode, 29-6  
FCCE, 29-87  
FCCM, 29-87  
features list, 29-2  
FPSMR, 29-85  
user-defined TxBD extension  
(AAL5/AAL1), 29-78  
UTOPIA interface, 29-82  
VCI filtering, 29-40  
VCI/VPI address lookup, 29-14  
VC-level address compression  
tables (VCLT), 29-18  
FTIRRx, 29-88  
GFMR register, 29-85  
global mode entry (GMODE), 29-41  
internal rate mode, 29-6  
interrupt queues, 29-79  
maximum performance configuration, 29-92  
OAM performance monitoring, 29-29, 29-60  
OAM support, 29-27  
VP-level address compression table  
(VPLT), 29-17  
block diagram, 13-3  
command set  
command descriptions, 13-14  
command execution latency, 13-15  
Index-4  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
INDEX  
command register example, 13-15  
CPCR, 13-11  
opcodes, 13-13  
error handling, 31-6  
FCCE, 31-14  
FCCM, 31-14  
overview, 13-11  
communications processor (CP)  
block diagram, 13-5  
FCCS, 31-16  
features list, 31-2  
FPSMR, 31-7  
execution from RAM, 13-7  
features list, 13-4  
frame reception, 31-3  
frame transmission, 31-2  
overview, 31-1  
parameter RAM, 31-4  
programming model, 31-5  
receive commands, 31-6  
reception errors, 31-7  
RxBD, 31-9  
interfacing with the core, 13-6  
microcode execution from RAM, 13-7  
microcode revision number, 13-10  
peripheral interface, 13-6  
PowerPC core interface, 13-6  
RCCR, 13-7  
REV_NUM, 13-10  
RTSCR, 13-9  
RTSR, 13-10  
transmission errors, 31-6  
transmit commands, 31-5  
TxBD, 31-12  
CPM multiplexing logic (CMX)  
block diagram, 15-2  
overview, 15-1  
overview  
block diagram, 28-3  
disabling FCCs, 28-19  
FCCEx, 28-14  
dual-port RAM  
accessing dual-port RAM, 13-15  
block diagram, 13-15  
buffer descriptors, 13-17  
memory map, 13-16  
overview, 13-15  
parameter RAM, 13-17  
fast communications controllers (FCCs)  
Fast Ethernet mode  
FCCMx, 28-14  
FCCSx, 28-14  
FCRx, 28-13  
FDSRx, 28-7  
FPSMRx, 28-7  
FTODRx, 28-7  
GFMRx, 28-3  
initialization, 28-14  
interrupt handling, 28-15  
interrupts, 28-13  
address recognition, 30-15  
block diagram, 30-3  
CAM interface, 30-8  
collision handling, 30-18  
connecting to the MPC8260, 30-4  
error handling, 30-19  
FCCE, 30-21  
FCCM, 30-21  
features list, 30-3  
FPSMR, 30-20  
overview, 28-2  
parameter RAM, 28-10  
RxBD, 28-8  
saving power, 28-21  
switching protocols, 28-21  
timing control, 28-15  
TxBD, 28-8  
transparent mode  
frame reception, 30-7  
frame transmission, 30-5  
hash table algorithm, 30-17  
hash table effectiveness, 30-17  
interpacket gap time, 30-18  
interrupt events, 30-23  
loopback mode, 30-18  
parameter RAM, 30-9  
programming model, 30-12  
registers, 30-19  
RMON support, 30-14  
RxBD, 30-23  
TxBD, 30-26  
HDLC mode  
bit stuffing, 31-1  
error control, 31-1  
achieving synchronization, 32-2  
external synchronization signals, 32-3  
features list, 32-2  
in-line synchronization pattern, 32-3  
receive operation, 32-2  
synchronization example, 32-4  
transmit operation, 32-2  
features list, 13-1  
I C controller  
block diagram, 34-1  
BRGCLK, 34-2  
clocking and pin functions, 34-2  
commands, 34-11  
features list, 34-2  
loopback testing, 34-4  
master read (slave write), 34-4  
2
MOTOROLA  
Index  
Index-5  
INDEX  
master write (slave read), 34-4  
multi-master considerations, 34-5  
parameter RAM, 34-9  
programming model, 34-6  
registers, 34-6  
HDLC parameters (channel-specific), 27-8  
initialization, 27-24  
INTMSK, 27-9  
latency, 27-26  
MCCE, 27-18  
RxBD, 34-13  
MCCFx, 27-15  
MCCM, 27-18  
parameters for transparent operation, 27-12  
performance, 27-26  
receive commands, 27-17  
RSTATE, 27-11  
slave read (master write), 34-4  
slave write (master read), 34-4  
transfers, 34-3  
TxBD, 34-14  
IDMA emulation  
auto buffer, 18-15  
buffer chaining, 18-15  
buffers, 18-23  
bus exceptions, 18-27  
commands, 18-26  
controlling 60x bus bandwidth, 18-12  
DACKx, 18-13  
DCM, 18-18  
DONEx, 18-14  
DREQx, 18-13  
DTS/STS programming, 18-20  
dual-address transfers, 18-10  
edge-sensitive mode, 18-13  
exceptions, bus, 18-27  
external request mode, 18-8  
features list, 18-5  
RxBD, 27-21  
super channel table, 27-5  
TSTATE, 27-9  
TxBD, 27-23  
overview, CPM, 13-1  
parallel I/O ports  
block diagram, 35-6  
features, 35-1  
overview, 35-1  
PDATx, 35-2  
PDIRx, 35-3  
pin assignments (port AÐport D), 35-8Ð35-19  
PODRx, 35-2  
port C interrupts, 35-19  
port pin functions, 35-6  
PPAR, 35-4  
IDMR, 18-22  
IDSR, 18-22  
level-sensitive mode, 18-13  
normal mode, 18-9  
operand transfers, recognizing, 18-27  
operation, 18-14  
overview, 18-5  
parallel I/O register programming, 18-28  
parameter RAM, 18-16  
priorities, 18-12  
programming examples, 18-29  
programming the parallel I/O registers, 18-28  
signals, 18-12  
single address transfers (fly-by), 18-11  
transfers, 18-6  
interrupt controller  
programming options, 35-8  
PSORx, 35-4  
registers, 35-2  
resetting registers and parameters for  
all channels, 13-11  
RISC timer tables  
CP loading tracking, 13-24  
features list, 13-19  
initializing RISC timer tables, 13-22  
interrupt handling, 13-23  
overview, 13-18  
parameter RAM, 13-19  
pulse width modulation (PWM) channels, 13-19  
RAM usage, 13-19  
RTER, 13-21  
RTMR, 13-21  
memory map, 3-4  
scan algorithm, 13-23  
SET TIMER command, 13-22  
table entries, 13-21  
timer counts, comparing, 13-24  
TM_CMD, 13-20  
multi-channel controllers (MCCs)  
CHAMR  
HDLC mode, 27-10  
transparent mode, 27-13  
channel extra parameters, 27-5  
commands, 27-16  
tracking CP loading, 13-24  
SDMA channels  
data structure organization, 27-2  
exceptions, 27-17  
features list, 27-1  
bus arbitration, 18-2  
bus transfers, 18-2  
LDTEA, 18-4  
global parameters, 27-3  
LDTEM, 18-4  
Index-6  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
INDEX  
overview, 18-1  
PDTEA, 18-4  
PDTEM, 18-4  
programming model, 18-3  
registers, 18-3  
SDMR, 18-4  
local bus monitor function, 4-2  
masking interrupt sources, 4-13  
MCC relative priority, 4-12  
periodic interrupt timer (PIT), 4-5  
periodic interrupt timer (PIT) function, 4-2  
pin multiplexing, 4-44  
PISCR, 4-42  
SDSR, 18-3  
serial configuration, 13-3  
serial peripheral interface (SPI)  
block diagram, 33-1  
clocking and pin functions, 33-2  
commands, 33-12  
configuring the SPI, 33-3  
features list, 33-2  
interrupt handling, 33-18  
master mode, 33-3  
maximum receive buffer length (MRBLR), 33-11  
multi-master operation, 33-4  
parameter RAM, 33-10  
programming example  
master, 33-16  
PITC, 4-43  
PITR, 4-44  
port C interrupts, 4-16  
PPC_ACR, 4-28  
PPC_ALRH, 4-28  
PPC_ALRL, 4-29  
programming model, 4-17  
registers, 4-17  
SCC relative priority, 4-12  
SCPRR_H, 4-19  
SCPRR_L, 4-20  
SICR, 4-17  
SIEXR, 4-24  
signal multiplexing, 4-44  
SIMR_H, 4-22  
SIMR_L, 4-22  
slave, 33-17  
programming model, 33-6  
RxBD, 33-14  
slave mode, 33-4  
SIPNR_H, 4-21  
SIPNR_L, 4-21  
SPCOM, 33-9  
SPIE, 33-9  
SPIM, 33-9  
SPMODE, 33-6  
TxBD, 33-15  
system interface unit (SIU)  
60x bus monitor function, 4-2  
add flexibility to CPM interrupt priorities, 4-12  
BCR, 4-25  
block diagram, 4-1  
bus monitor, 4-3  
clocks, 4-4  
configuration functions, 4-2  
configuration/protection logic block diagram, 4-3  
encoding the interrupt vector, 4-14  
FCC relative priority, 4-12  
flexibility of interrupt priorities, 4-12  
highest priority interrupt, 4-13  
IMMR, 4-34  
interrupt controller features list, 4-7  
interrupt priorities, add flexibility, 4-12  
interrupt source priorities, 4-9  
interrupt vector calculation, 4-14  
interrupt vector encoding, 4-14  
interrupt vector generation, 4-14  
L_TESCR1, 4-38  
SIPRR, 4-18  
SIUMCR, 4-31  
SIVEC, 4-23  
software watchdog timer, 4-6  
SWR, 4-7  
SWSR, 4-36  
SYPCR, 4-35  
system protection, 4-2  
TESCR1, 4-36  
TESCR2, 4-37  
time counter (TMCNT)  
function, 4-2  
overview, 4-4  
timers, 4-4  
TMCNT, 4-41  
TMCNTAL, 4-41  
TMCNTSC, 4-40  
timers  
memory map, 3-5  
Conventions  
notational conventions, lx, II-ii, III-ii, IV-iv  
terminology, lxiv  
CPCR (CP command register), 13-11  
CPM multiplexing logic (CMX)  
overview, 15-1  
see also Serial interface (SI)  
CPM multiplexing, see CPM multiplexing  
logic (CMX)  
L_TESCR2, 4-39  
LCL_ACR, 4-29  
LCL_ALRH, 4-30  
LCL_ALRL, 4-30  
CPM MUX memory map, 3-12  
CPM MUX, see CPM multiplexing logic (CMX)  
MOTOROLA  
Index  
Index-7  
INDEX  
CxTx (chip-select signals), 10-74  
F
Fast communications controllers (FCCs)  
D
Fast Ethernet mode  
address recognition, 30-15  
block diagram, 30-3  
CAM interface, 30-8  
collision handling, 30-18  
connecting to the MPC8260, 30-4  
error handling, 30-19  
FCCE, 30-21  
DCM (IDMA channel mode), 18-18  
Digital phase-locked loop (DPLL) operation, 19-22  
DSR (data synchronization register)  
overview, 19-9  
UART mode, 20-11  
Dual-port RAM  
accessing dual-port RAM, 13-15  
block diagram, 13-15  
buffer descriptors, 13-17  
memory map, 13-16  
overview, 13-15  
FCCM, 30-21  
features list, 30-3  
FPSMR, 30-20  
frame reception, 30-7  
frame transmission, 30-5  
hash table algorithm, 30-17  
hash table effectiveness, 30-17  
interpacket gap time, 30-18  
interrupt events, 30-23  
loopback mode, 30-18  
parameter RAM, 30-9  
programming model, 30-12  
registers, 30-19  
parameter RAM, 13-17  
E
EAMUX (external address multiplexing)  
signal, 10-41  
EDO interface connection, MPC8260 to 60x  
bus, 10-92  
Ethernet mode  
fast communications controller (FCC)  
address recognition, 30-15  
block diagram, 30-3  
RMON support, 30-14  
RxBD, 30-23  
TxBD, 30-26  
CAM interface, 30-8  
collision handling, 30-18  
connecting to the MPC8260, 30-4  
error handling, 30-19  
FCCE, 30-21  
HDLC mode  
bit stuffing, 31-1  
error control, 31-1  
error handling, 31-6  
FCCE, 31-14  
FCCM, 30-21  
features list, 30-3  
FPSMR, 30-20  
FCCM, 31-14  
FCCS, 31-16  
features list, 31-2  
FPSMR, 31-7  
frame reception, 31-3  
frame transmission, 31-2  
overview, 31-1  
parameter RAM, 31-4  
programming model, 31-5  
receive commands, 31-6  
reception errors, 31-7  
RxBD, 31-9  
frame reception, 30-7  
frame transmission, 30-5  
hash table algorithm, 30-17  
hash table effectiveness, 30-17  
interpacket gap time, 30-18  
interrupt events, 30-23  
loopback mode, 30-18  
parameter RAM, 30-9  
programming model, 30-12  
registers, 30-19  
transmission errors, 31-6  
transmit commands, 31-5  
TxBD, 31-12  
RMON support, 30-14  
RxBD, 30-23  
TxBD, 30-26  
overview  
Exceptions  
block diagram, 28-3  
disabling FCCs, 28-19  
FCCEx, 28-14  
FCCMx, 28-14  
FCCSx, 28-14  
exception handling, 10-73  
overview, 2-22  
Execution units, 2-6  
FCRx, 28-13  
FDSRx, 28-7  
Index-8  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
INDEX  
FPSMRx, 28-7  
FTODRx, 28-7  
GFMRx, 28-3  
new features supported, 10-2  
multi-channel controllers (MCCs), 27-1  
processor core, 2-3  
initialization, 28-14  
interrupt handling, 28-15  
interrupts, 28-13  
RISC timer tables, 13-19  
serial communications controllers (SCCs)  
AppleTalk mode, 25-2  
overview, 28-2  
parameter RAM, 28-10  
RxBD, 28-8  
saving power, 28-21  
switching protocols, 28-21  
timing control, 28-15  
TxBD, 28-8  
switching protocols, 28-21  
transparent mode  
features list, 32-2  
BISYNC mode, 22-2  
general list, 19-2  
HDLC mode, 21-2  
transparent mode, 23-1  
UART mode, 20-2  
serial interface, 14-3  
serial management controllers (SMCs)  
general list, 26-2  
transparent mode, 26-21  
UART mode, 26-11  
receive operation, 32-2  
synchronization  
achieving, 32-2  
UART mode, features not supported, 26-10  
serial peripheral interface (SPI), 33-2  
timers, 17-2  
example, 32-4  
FPSMR register  
Ethernet, 30-20  
HDLC, 31-7  
protocol-specific mode, 28-7  
FTIRRx (FCC transmit internal rate registers), 29-88  
FTODRx (FCC transmit-on-demand registers), 28-7  
external signals, 32-3  
in-line pattern, 32-3  
transmit operation, 32-2  
FCCE register  
ATM, 29-87  
Ethernet, 30-21  
FCC overview, 28-14  
HDLC, 31-14  
FCCM register  
ATM, 29-87  
Ethernet, 30-21  
FCC overview, 28-14  
HDLC, 31-14  
FCCS (FCC status) register, 28-14, 31-16  
FCRx (function code registers), 28-13  
FDSRx (FCC data synchronization registers), 28-7  
Features list  
G
GCI  
activation and deactivation, 14-33  
programming, 14-33  
support, 14-31  
General-purpose chip-select machine (GPCM)  
common features, 10-6  
differences between MPC8xx and MPC8260, 10-62  
external access termination, 10-60  
implementation differences with UPMs  
and SDRAM machine, 10-7  
interface signals, 10-51  
MPC8xx versus MPC8260, 10-62  
overview, 10-51  
SRAM configuration, 10-51  
strobe signal behavior, 10-52  
terminating external accesses, 10-60  
timing configuration, 10-52  
General-purpose signals, 10-76  
GFMR (general FCC mode register), 28-3, 29-85  
GMODE (global mode entry), 29-41  
GPLn (general-purpose signals), 10-76  
GSMR (general SCC mode register)  
AppleTalk mode, 25-3  
SIU interrupt controller, 4-7  
Features lists  
communications processor (CP), 13-4  
communications processor module (CPM), 13-1  
ATM controller, 29-2  
parallel I/O ports, 35-1  
CPM multiplexing, 15-2  
Ethernet mode, 24-3  
fast communications controllers (FCCs)  
Fast Ethernet, 30-3  
HDLC mode, 31-2  
transparent mode, 32-2  
HDLC bus controller, 21-19  
2
I C controller, 34-2  
HDLC bus protocol, programming, 21-23  
overview, 19-3  
IDMA emulation, 18-5  
implementation-specific, 1-1  
memory controller  
features list, 10-3  
MOTOROLA  
Index  
Index-9  
INDEX  
features list, 34-2  
H
HDLC mode  
accessing the bus, 21-19  
bus controller, 21-17  
collision detection, 21-17, 21-20  
commands, 21-5  
delayed RTS mode, 21-21  
error handling, 21-6  
fast communications controllers (FCCs)  
bit stuffing, 31-1  
error control, 31-1  
loopback testing, 34-4  
master read (slave write), 34-4  
master write (slave read), 34-4  
multi-master considerations, 34-5  
parameter RAM, 34-9  
programming model, 34-6  
registers, 34-6  
RxBD, 34-13  
slave read (master write), 34-4  
slave write (master read), 34-4  
transfers, 34-3  
error handling, 31-6  
FCCE, 31-14  
FCCM, 31-14  
FCCS, 31-16  
features list, 31-2  
FPSMR, 31-7  
frame reception, 31-3  
frame transmission, 31-2  
overview, 31-1  
parameter RAM, 31-4  
programming model, 31-5  
receive commands, 31-6  
reception errors, 31-7  
RxBD, 31-9  
transmission errors, 31-6  
transmit commands, 31-5  
TxBD, 31-12  
TxBD, 34-14  
I C memory map, 3-9  
2
2
I2CER (I C event register), 34-8  
2
I2CMR (I C mask register), 34-8  
2
I2COM (I C command) register, 34-8  
2
I2MOD (I C mode) register, 34-6  
IDL interface programming, 14-29  
IDL interface support, 14-25  
IDMA emulation  
auto buffer, 18-15  
buffer chaining, 18-15  
buffers, 18-23  
bus exceptions, 18-27  
commands, 18-26  
controlling 60x bus bandwidth, 18-12  
DACKx, 18-13  
DCM, 18-18  
DONEx, 18-14  
DREQx, 18-13  
DTS/STS programming, 18-20  
dual-address transfers, 18-10  
edge-sensitive mode, 18-13  
exception, bus, 18-27  
external request mode, 18-8  
features list, 18-5  
IDMR, 18-22  
IDSR, 18-22  
level-sensitive mode, 18-13  
normal mode, 18-9  
operand transfers, recognizing, 18-27  
operation, 18-14  
overview, 18-5  
parallel I/O register programming, 18-28  
parameter RAM, 18-16  
priorities, 18-12  
programming examples, 18-29  
programming the parallel I/O registers, 18-28  
signals, 18-12  
single address transfers (fly-by), 18-11  
transfers, 18-6  
features list, 21-2  
GSMR, HDLC bus protocol programming, 21-23  
multi-master bus configuration, 21-18  
overview, 21-1  
parameter RAM, 21-3  
performance, increasing, 21-20  
programming example, 21-15, 21-23  
programming the controller, 21-5  
PSMR, 21-7  
RxBD, 21-8  
single-master bus configuration, 21-19  
TxBD, 21-11  
using the TSA, 21-22  
HID0 register  
bit settings, 2-12  
doze, nap, sleep, DPM bits, 2-12  
I
I2ADD (I C address) register, 34-7  
2
2
I2BRG (I C baud rate generator) register, 34-7  
2
I C controller  
block diagram, 34-1  
BRGCLK, 34-2  
IDMA parameter RAM, 18-16  
IDMR (IDMA mask registers), 18-22  
clocking and pin functions, 34-2  
commands, 34-11  
Index-10  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
INDEX  
IDSR (IDMA event (status) register), 18-22  
IEEE 1149.1 test access port  
block diagram, 12-2  
MDR (memory data register), 10-28  
Memory controller  
address checking, 10-8  
boundary scan register, 12-3  
instruction decoding, 12-29  
instruction register, 12-28  
nonscan chain operation, 12-30  
overview, 12-1  
address latch enable (ALE), 10-11  
address space checking, 10-8  
architecture overview, 10-5  
atomic bus operation, 10-10, 10-10  
basic architecture, 10-5  
restrictions, 12-30  
TAP controller, 12-2  
basic operation, 10-8  
boot chip-select operation, 10-61  
controlling the timing of GPL1, GPL2, and  
CSx, 10-68  
CSx timing example, 10-68  
delayed read, 10-10  
EDO interface connection, MPC8260 to  
60x bus, 10-92  
error checking and correction (ECC), 10-9  
external master support, 10-101  
external support, 10-11  
IMMR (internal memory map register), 4-34  
Input/output port memory map, 3-5  
Instruction field conventions, lxv  
Instruction timing overview, 2-29  
Instruction unit, 2-5  
Integer unit overview, 2-6  
Interrupts  
ATM interrupt queues, 29-79  
RISC timer tables  
interrupt handling, 13-23  
SCC interrupt handling, 19-16  
features common to all machines, 10-6  
features list, 10-3  
general-purpose chip-select machine (GPCM)  
access termination, external, 10-60  
assertion timing, 10-53  
common features, 10-6  
differences between MPC8xx and  
MPC8260, 10-62  
J
JTAG implementation, 12-28  
L
external access termination, 10-60  
implementation differences with UPMs  
and SDRAM machine, 10-7  
interface signals, 10-51  
L_TESCR1 (local bus transfer error status and control  
register 1), 4-38  
L_TESCR2 (local bus transfer error status and control  
register 2), 4-39  
MPC8xx versus MPC8260, 10-62  
OE timing, 10-57, 10-57  
overview, 10-51  
programmable wait state  
configuration, 10-57  
L_TESCRx (local bus error status and control  
registers), 10-33  
LCL_ACR (local bus arbiter configuration  
register), 4-29  
LCL_ALRH (local bus arbitration high-level  
register), 4-30  
PSDVAL, 10-57  
read access extended hold time, 10-57  
relaxed timing, 10-55  
LCL_ALRL (local bus arbitration low-level  
register), 4-30  
SRAM configuration, 10-51  
strobe signal behavior, 10-52  
terminating external accesses, 10-60  
timing configuration, 10-52, 10-52  
write enable deassertion timing, 10-54  
GPLn timing example, 10-68  
implementation differences between  
machines, 10-7  
LDTEA (SDMA local bus transfer error address  
register), 18-4  
LDTEM (SDMA local bus transfer error MSNUM  
register), 18-4  
Loopback mode, 14-7  
LSDMR (local bus SDRAM mode register), 10-24  
LSRT (local bus-assigned SDRAM refresh timer)  
register, 10-32  
LURT (local bus-assigned UPM refresh timer)  
register, 10-30  
machine selection, 10-6  
MAR in 60x-compatible mode, 10-77  
new features supported, 10-2  
overview, 10-1  
M
page hit checking, 10-9  
MCCE (MCC event) register, 27-18  
MCCFx (MCC configuration registers), 27-15  
MCCM (MCC mask) register, 27-18  
parity byte select (PBSE), 10-11  
parity checking, 10-9  
parity generation, 10-9  
MOTOROLA  
Index  
Index-11  
INDEX  
programming model, 10-13  
PSDVAL, 10-12, 10-57  
register descriptions, 10-13  
SDRAM machine (synchronous DRAM machine)  
address multiplexing, 10-37  
bank interleaving, 10-36  
BSMA bit, 10-37  
commands, JEDEC-standard, 10-35  
common features, 10-6  
configuration example, 10-48  
implementation differences with UPMs and  
GPCM, 10-7  
RAM array, 10-69  
RAM word, 10-70  
refresh timer requests, 10-65  
register settings, 10-80  
requests, 10-64  
signal negation, 10-78  
signals, 10-62  
software requests, 10-66  
UPWAIT signal, 10-78  
wait mechanism, 10-78  
Memory management unit  
overview, 2-8  
JEDEC-standard commands, 10-35  
MODE-SET command timing, 10-46  
overview, 10-33  
page mode support, 10-36  
parameters  
activate-to-read/write interval, 10-39  
column address to first data out, 10-40  
last data in to precharge, 10-41  
last data out to precharge, 10-40  
overview, 10-38  
Memory management unit overview, 2-26  
Memory maps  
cross-reference guide, 3-1  
quick reference guide, 3-1  
serial communications controllers (SCCs)  
BISYNC mode, 22-4  
HDLC mode, 21-4  
UART mode, 20-4  
serial management controllers (SMCs)  
GCI mode, 26-30  
precharge-to-activate interval, 10-38  
refresh recovery interval (RFRC), 10-41  
pipeline accesses, 10-36  
power-on initialization, 10-35  
read/write transactions supported, 10-46  
refresh, 10-47  
SDAM bit, 10-37  
supported configurations, 10-35  
timing examples, 10-42  
transparent mode, 26-6  
UART mode, 26-6  
Microcode revision number, 13-10  
Modes  
60x bus mode  
60x-compatible bus mode, 8-3  
address latch enable (ALE), 10-11  
data streaming mode, 8-27  
extended transfer mode, 8-20  
no-pipeline mode, 8-26  
one-level pipeline mode, 8-26  
single-MPC8260 bus mode, 8-2  
ATM controller  
TEA generation, 10-9  
UPMs (user-programmable machines)  
access times, handling devices, 10-100  
address control bits, 10-77  
address multiplexing, 10-77  
clock timing, 10-67  
common features, 10-6  
data sample control, 10-77  
data valid, 10-77  
APC modes, 29-8  
external rate mode, 29-6  
internal rate mode, 29-6  
transmit rate modes, 29-6  
BISYNC mode, 22-1  
differences between MPC8xx and MPC8260, 10-  
80  
cascaded mode, 17-3  
echo mode, 26-1  
DRAM configuration example, 10-79  
EDO interface example, 10-92  
exception requests, 10-66  
HDLC mode, 21-1  
hunt mode, 20-10  
IDMA emulation  
hierarchical bus interface example, 10-100  
implementation differences with SDRAM  
machine and GPCM, 10-7  
edge-sensitive mode, 18-13  
external request mode, 18-8  
level-sensitive mode, 18-13  
normal mode, 18-9  
loop control, 10-76  
memory access requests, 10-65  
memory system interface example, 10-81  
MPC8xx versus MPC8260, 10-80  
overview, 10-62  
loopback mode, 26-1  
NMSI mode, synchronization, 23-3  
SCC AppleTalk mode, 25-1, 25-1  
serial interface (SI)  
programming the UPM, 10-66  
echo mode, 14-7  
Index-12  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
INDEX  
serial peripheral interace (SPI)  
master mode, 33-3  
slow go, 17-2  
transparent mode  
overview, 32-1  
serial communications controllers (SCCs), 23-1  
serial management controllers (SMCs), 26-20  
UART mode  
serial communications controllers (SCCs), 20-1  
serial management controllers (SMCs), 26-10  
MPTPR (memory refresh timer prescaler  
register), 10-32  
Multi-channel controllers (MCCs)  
CHAMR  
HDLC mode, 27-10  
transparent mode, 27-13  
channel extra parameters, 27-5  
commands, 27-16  
data structure organization, 27-2  
exceptions, 27-17  
features list, 27-1  
global parameters, 27-3  
HDLC parameters (channel-specific), 27-8  
initialization, 27-24  
INTMSK, 27-9  
latency, 27-26  
MCCE, 27-18  
MCCFx, 27-15  
MCCM, 27-18  
parameters for transparent operation, 27-12  
performance, 27-26  
receive commands, 27-17  
RSTATE, 27-11  
RxBD, 27-21  
P
Parallel I/O ports  
block diagram, 35-6  
features, 35-1  
overview, 35-1  
PDATx, 35-2  
PDIRx, 35-3  
pin assignments (port AÐport D), 35-8Ð35-19  
PODRx, 35-2  
port C interrupts, 35-19  
port pin functions, 35-6  
PPAR, 35-4  
programming options, 35-8  
PSORx, 35-4  
registers, 35-2  
Parameter RAM  
ATM controller, 29-37  
fast communications controllers (FCCs)  
Fast Ethernet mode, 30-9  
HDLC mode, 31-4  
overview, 28-10  
HDLC mode, 21-3  
2
I C controller, 34-9  
IDMA emulation, 18-16  
serial communications controllers (SCCs)  
all protocols, 19-13  
base addresses, 19-15  
BISYNC mode, 22-3  
overview, 19-13  
UART mode, 20-4  
serial management controllers (SMCs)  
GCI mode, 26-30  
overview, 26-6, 26-30  
transparent mode, 26-6  
UART mode, 26-6  
super channel table, 27-5  
TSTATE, 27-9  
TxBD, 27-23  
serial peripheral interface (SPI), 33-10  
Parity byte select (PBSE), 10-11  
PDATx (port data) registers, 35-2  
PDIRx (port data direction registers), 35-3  
PDTEA (SDMA 60x bus transfer error address  
register), 18-4  
PDTEM (SDMA 60x bus transfer error MSNUM  
register), 18-4  
PISCR (periodic interrupt status and control  
register), 4-42  
MxMR (machine x mode registers), 10-26  
N
NMSI (non-multiplexed serial interface)  
configuration, 15-4  
SMC NMSI connection, receive and transmit, 26-2  
synchronization in NMSI mode,  
transparent operation, 23-3  
PITC (periodic interrupt timer count register), 4-43  
PITR (periodic interrupt timer register), 4-44  
PODRx (port open-drain registers), 35-2  
Power consumption  
FCCs, 28-21  
SCCs, 19-27  
PPAR (port pin assignment register), 35-4  
PPC_ACR (60x bus arbiter configuration  
register), 4-28  
O
Operations  
atomic bus operation, 10-10  
digital phase-locked loop (DPLL) operation, 19-22  
SMC buffer descriptor, 26-5  
transparent operation, NMSI sychronization, 23-3  
ORx (option registers), 10-16  
MOTOROLA  
Index  
Index-13  
INDEX  
PPC_ALRH (60x bus arbitration high-level  
register), 4-28  
PPC_ALRL (60x bus arbitration low-level  
register), 4-29  
Programming examples  
serial communications controllers (SCCs)  
GSMR (general SCC mode register)  
AppleTalk mode, 25-3  
HDLC bus protocol, 21-23  
PSMR (protocol-specific mode register)  
AppleTalk mode, 25-4  
TODR (transmit-on-demand register)  
AppleTalk mode, 25-4  
transparent mode, 23-13  
UART mode, 20-22  
transparent mode  
NMSI programming example, 26-29  
Promiscuous mode, see Transparent mode  
Promiscuous operation, 32-1  
PSDMR (60x SDRAM mode register), 10-21  
PSMR (protocol-specific mode register)  
AppleTalk mode, 25-4  
BISYNC mode, 22-10  
Ethernet mode, 24-15  
HDLC bus protocol, programming, 21-23  
HDLC mode, 21-7  
overview, 19-9  
transparent mode, 23-9  
UART mode, 20-13  
PSORx (port special options registers), 35-4  
PSRT (60x bus-assigned SDRAM refresh timer)  
register, 10-31  
BDLE, 22-8  
BSYNC, 22-7  
PSMR, 22-10  
SCCE, 22-15  
SCCM, 22-15  
SCCS, 22-16  
communications processor (CP)  
RCCR, 13-7  
RTSCR, 13-9  
RTSR, 13-10  
communications processor module (CPM)  
CPCR, 13-11  
parallel I/O ports  
PDATx, 35-2  
PDIRx, 35-3  
PODRx, 35-2  
PPAR, 35-4  
PSORx, 35-4  
CPM multiplexing  
CMXFCR, 15-12  
CMXSCR, 15-14  
CMXSI1CR, 15-10  
CMXSI2CR, 15-11  
CMXSMR, 15-17  
CMXUAR, 15-7  
DSR  
overview, 19-9  
UART mode, 20-11  
fast communications controllers (FCCs)  
Fast Ethernet mode  
FCCE, 30-21  
FCCM, 30-21  
Pulse width modulation (PWM) channels, 13-19  
PURT (60x bus-assigned UPM refresh timer)  
register, 10-30  
FPSMR, 30-20  
HDLC mode  
FCCE, 31-14  
PWM channels (pulse width modulation  
channels), 13-19  
FCCM, 31-14  
FCCS, 31-16  
FPSMR, 31-7  
overview  
FCCEx, 28-14  
FCCMx, 28-14  
FCCSx, 28-14  
FCRx, 28-13  
R
RAM word, 10-70  
RCCR (RISC controller configuration register), 13-7  
Registers  
AppleTalk mode  
GSMR, 25-3  
PSMR, 25-4  
TODR, 25-4  
ATM controller  
FDSRx, 28-7  
FPSMRx, 28-7  
FTODRx, 28-7  
GFMRx, 28-3  
interrupts, 28-13  
timing control, 28-15  
GSMR  
AppleTalk mode, 25-3  
overview, 19-3  
HDLC mode  
FCCE, 29-87  
FCCM, 29-87  
FPSMR (FCC protocol-specific mode  
register, 29-85  
FTIRRx, 29-88  
GFMR register, 29-85  
BISYNC mode  
PSMR, 21-7  
Index-14  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
INDEX  
SCCE, 21-12  
SCCM, 21-12  
SCCS, 21-14  
I C controller  
I2ADD, 34-7  
I2BRG, 34-7  
I2CER, 34-8  
I2CMR, 34-8  
I2COM, 34-8  
I2MOD, 34-6  
transparent mode, 23-9  
UART mode, 20-13  
quick reference guide, A-1  
reset mode, 5-5  
reset status, 5-4  
RFCR, 19-15  
RISC timer tables  
RTER, 13-21  
RTMR, 13-21  
TM_CMD, 13-20  
SCCE  
BISYNC mode, 22-15  
Ethernet mode, 24-21  
transparent mode, 23-12  
UART mode, 20-19  
SCCM  
BISYNC mode, 22-15  
Ethernet mode, 24-21  
transparent mode, 23-12  
UART mode, 20-19  
SCCS  
BISYNC mode, 22-16  
transparent mode, 23-13  
UART mode, 20-21  
SDMA channels  
LDTEA, 18-4  
2
IDMA emulation  
DCM, 18-18  
IDMR, 18-22  
IDSR, 18-22  
IEEE 1149.1 test access port  
boundary scan registers, 12-3  
instruction register, 12-28  
memory controller  
60x bus control registers, 10-13  
BRn, 10-14  
GPCM mode  
ORx, 10-18  
L_TESCRx, 10-33  
MPTPR, 10-32  
MxMR, 10-26  
SDRAM mode  
LSDMR, 10-24  
LSRT, 10-32  
LDTEM, 18-4  
PDTEA, 18-4  
ORx, 10-16  
PSDMR, 10-21  
PSRT, 10-31  
PDTEM, 18-4  
SDMR, 18-4  
SDSR, 18-3  
TESCRx, 10-33  
UPM mode  
LURT, 10-30  
MDR, 10-28  
ORx, 10-20  
PURT, 10-30  
serial interface (SI)  
SIxCMDR, 14-24  
SIxGMR, 14-17  
SIxMR, 14-17  
SIxRSR, 14-23  
SIxSTR, 14-25  
register settings, 10-80  
multi-channel controllers (MCCs)  
CHAMR  
serial management controllers  
GCI mode  
SMCE, 26-34  
HDLC mode, 27-10  
CHAMR, 27-13  
MCCE, 27-18  
MCCFx, 27-15  
MCCM, 27-18  
RSTATE, 27-11  
TSTATE, 27-9  
PowerPC  
SMCM, 26-34  
SMCMRs, 26-3  
transparent mode  
SMCE, 26-28  
SMCM, 26-28  
UART mode  
RxBD, 26-14  
SMCE, 26-18  
supervisor-level, A-2, A-3  
user-level, A-1  
PSMR  
AppleTalk mode, 25-4  
BISYNC mode, 22-10  
Ethernet mode, 24-15  
overview, 19-9  
SMCM, 26-18  
TxBD, 26-16  
serial management controllers (SMCs)  
GCI mode  
RxBD, 26-33  
serial management controllers(SMCs)  
GCI mode  
MOTOROLA  
Index  
Index-15  
INDEX  
TxBD, 26-33  
serial peripheral interface (SPI)  
SPCOM, 33-9  
SPIE, 33-9  
SCCM, 23-12  
SCCS, 23-13  
UART mode  
DSR, 20-11  
SPIM, 33-9  
PSMR, 20-13  
SCCE, 20-19  
SCCM, 20-19  
SCCS, 20-21  
TOSEQ, 20-10  
SPMODE, 33-6  
system interface unit (SIU)  
BCR, 4-25  
IMMR, 4-34  
L_TESCR1, 4-38  
L_TESCR2, 4-39  
LCL_ACR, 4-29  
LCL_ALRH, 4-30  
LCL_ALRL, 4-30  
PISCR, 4-42  
Reset  
actions, 5-2  
causes, 5-1  
external HRESET flow, 5-3  
external SRESET flow, 5-3  
power-on reset flow, 5-2  
receiver reset sequence, SCC, 19-27  
resetting registers and parameters for all  
channels, 13-11  
software watchdog reset, 5-1  
transmitter reset sequence, SCC, 19-27  
RFCR (Rx buffer function code register)  
overview, 19-15  
RISC microcontroller, seeCommunications  
processor (CP)  
RISC timer tables  
CP loading tracking, 13-24  
features list, 13-19  
PITC, 4-43  
PITR, 4-44  
PPC_ACR, 4-28  
PPC_ALRH, 4-28  
PPC_ALRL, 4-29  
SCPRR_H, 4-19  
SCPRR_L, 4-20  
SICR, 4-17  
SIEXR, 4-24  
SIMR_H, 4-22  
SIMR_L, 4-22  
SIPNR_H, 4-21  
SIPNR_L, 4-21  
SIPRR, 4-18  
SIUMCR, 4-31  
SIVEC, 4-23  
SWR, 4-7  
initializing RISC timer tables, 13-22  
interrupt handling, 13-23  
overview, 13-18  
parameter RAM, 13-19  
pulse width modulation (PWM) channels, 13-19  
RAM usage, 13-19  
RTER, 13-21  
RTMR, 13-21  
scan algorithm, 13-23  
SET TIMER command, 13-22  
table entries, 13-21  
timer counts, comparing, 13-24  
TM_CMD, 13-20  
SWSR, 4-36  
SYPCR, 4-35  
TESCR1, 4-36  
TESCR2, 4-37  
TMCNT, 4-41  
TMCNTAL, 4-41  
TMCNTSC, 4-40  
TFCR, 19-15  
timers  
TCN, 17-8  
TCR, 17-8  
TER, 17-8  
TGCR, 17-4  
TMR, 17-6  
TRR, 17-7  
tracking CP loading, 13-24  
RMR (reset mode) register, 5-5  
RSR (reset status) register, 5-4  
RSTATE (internal receiver state) register, 27-11  
RTER (RISC timer event register), 13-21  
RTMR (RISC timer mask register), 13-21  
RTSCR (RISC time-stamp control register), 13-9  
RTSR (RISC time-stamp register), 13-10  
TODR  
AppleTalk mode, 25-4  
overview, 19-9  
TOSEQ, 20-10  
transparent mode  
PSMR, 23-9  
S
SCC memory map, 3-9  
SCCE (SCC event) register  
BISYNC mode, 22-15  
HDLC mode, 21-12  
SCCE, 23-12  
Index-16  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
INDEX  
transparent mode, 23-12  
UART mode, 20-19  
SCCE register  
sending synchronization sequence, 22-9  
TxBD, 22-14  
Ethernet mode  
Ethernet mode, 24-21  
SCCM (SCC mask) register  
BISYNC mode, 22-15  
HDLC mode, 21-12  
transparent mode, 23-12  
UART mode, 20-19  
SCCM register  
Ethernet mode, 24-21  
SCCS (SCC status) register  
BISYNC mode, 22-16  
HDLC mode, 21-14  
transparent mode, 23-13  
UART mode, 20-21  
SCIT programming, 14-33  
address recognition, 24-11  
collision handling, 24-13  
commands, 24-10  
connecting to Ethernet, 24-4  
error handling, 24-14  
frame reception, 24-6  
hash table algorithm, 24-13  
loopback, 24-14  
overview, 24-1  
programming example, 24-23  
programming the controller, 24-10  
receive buffer, 24-17  
transmit buffer, 24-19  
HDLC mode  
SCPRR_H (CPM high interrupt priority register), 4-19  
SCPRR_L (CPM low interrupt priority register), 4-20  
SDMA channels  
bus arbitration, 18-2  
bus transfers, 18-2  
accessing the bus, 21-19  
bus controller, 21-17  
collision detection, 21-17, 21-20  
commands, 21-5  
delayed RTS mode, 21-21  
error handling, 21-6  
features list, 21-2  
LDTEA, 18-4  
LDTEM, 18-4  
overview, 18-1  
PDTEA, 18-4  
PDTEM, 18-4  
GSMR, HDLC bus protocol programming, 21-23  
interrupts, 21-13  
memory map, 21-4  
programming model, 18-3  
registers, 18-3  
SDMR, 18-4  
multi-master bus configuration, 21-18  
overview, 21-1  
parameter RAM, 21-3  
performance, increasing, 21-20  
programming example, 21-15, 21-23  
programming the controller, 21-5  
PSMR, 21-7  
SDSR, 18-3  
SDMR (SDMA mask register), 18-4  
SDRAM interface, see SDRAM machine  
SDSR (SDMA status register), 18-3  
Serial communications controllers (SCCs)  
AppleTalk mode  
RxBD, 21-8  
single-master bus configuration, 21-19  
TxBD, 21-11  
using the TSA, 21-22  
connecting to AppleTalk, 25-3  
operating LocalTalk frame, 25-1  
overview, 25-1, 25-1  
overview  
programming example, 21-23, 25-4  
programming the controller, 25-3  
BISYNC mode  
buffer descriptors, 19-10  
controlling SCC timing, 19-18  
DPLL operation, 19-22  
features, 19-2  
commands, 22-5  
control character recognition, 22-6  
error handling, 22-9  
frame reception, 22-3  
frame transmission, 22-2  
frames, classes, 22-1  
memory map, 22-4  
overview, 22-1  
parameter RAM, 22-3  
programming example, 22-18  
programming the controller, 22-17  
receiving synchronization sequence, 22-9  
RxBD, 22-12  
initialization, 19-17  
interrupt handling, 19-16  
parameter RAM, 19-13  
reconfiguration, 19-26  
reset sequence, 19-27  
switching protocols, 19-27  
transparent mode  
achieving synchronization, 23-3  
commands, 23-7  
DSR receiver SYNC pattern lengths, 23-3  
end of frame detection, 23-6  
error handling, 23-8  
MOTOROLA  
Index  
Index-17  
INDEX  
frame reception, 23-2  
frame transmission, 23-2  
inherent synchronization, 23-6  
in-line synchronization, 23-6  
overview, 23-1  
C/I channel  
handling the SMC, 26-31  
reception process, 26-31  
RxBD, 26-33  
transmission process, 26-31  
TxBD, 26-33  
commands, 26-32  
programming example, 23-13  
RxBD, 23-9  
synchronization signals, 23-4  
synchronization, user-controlled, 23-5  
transmit synchronization, 23-3  
TxBD, 23-10  
UART mode  
commands, 20-6  
control character insertion, 20-10  
data handling, character and message-based, 20-5  
error reporting, 20-6  
features list, 20-2  
fractional stop bits, 20-11  
handling errors, 20-12  
hunt mode, 20-10  
monitor channel  
reception process, 26-31  
RxBD, 26-32  
transmission process, 26-31  
TxBD, 26-32  
overview, 26-30  
parameter RAM, 26-30  
memory structure, 26-5  
mode selection, 26-3  
NMSI connection, receive and transmit, 26-2  
parameter RAM  
GCI mode, 26-30  
overview, 26-6, 26-30  
transparent mode, 26-6  
UART mode, 26-6  
memory map, 20-4  
normal asynchronous mode, 20-3  
overview, 20-1  
parameter RAM, 20-4  
programming example, 20-22  
RxBD, 20-15  
S-records loader application, 20-23  
status reporting, 20-6  
synchronous mode, 20-3  
TxBD, 20-18  
power, saving, 26-10  
programming the controller, 26-12  
protocol switching, 26-10  
reinitializing the receiver, 26-10  
reinitializing the transmitter, 26-9  
selecting modes, 26-3  
sending a break, 26-13  
sending a preamble, 26-13  
switching protocols, 26-10  
transparent mode  
features list, 26-21  
overview, 26-20  
parameter RAM, 26-6  
reception process, 26-21  
RxBD, 26-26  
TxBD, 26-27  
UART mode  
character mode, 26-12  
commands, 26-12  
data handling, 26-12  
error handling, 26-13  
features list, 26-11  
features not supported by SMCs, 26-10  
frame format, 26-11  
message-oriented mode, 26-12  
overview, 26-10  
Serial configuration, 13-3  
Serial interface (SI)  
block diagram, 14-2  
enabling connections, 14-7  
features, 14-3  
GCI support, 14-31  
IDL bus implementation  
programming the IDL, 14-29  
IDL interface support, 14-25  
overview, 14-4  
programming GCI, 14-33  
programming RAM entries, 14-10  
registers, 14-17  
see also CPM multiplexing logic (CMX)  
SI RAM, 14-8  
Serial management controllers (SMCs)  
buffer descriptors, overview, 26-5  
disabling SMCs on-the-fly, 26-9  
disabling the receiver, 26-9  
disabling the transmitter, 26-9  
enabling the receiver, 26-9  
enabling the transmitter, 26-9  
features list, 26-2  
parameter RAM, 26-6  
programming example, 26-19  
reception process, 26-12  
RxBD, 26-14  
transmission process, 26-11  
TxBD, 26-16  
GCI mode  
Index-18  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
INDEX  
Serial peripheral interface (SPI)  
block diagram, 33-1  
clocking and pin functions, 33-2  
commands, 33-12  
configuring the SPI, 33-3  
features list, 33-2  
interrupt handling, 33-18  
master mode, 33-3  
maximum receive buffer length (MRBLR), 33-11  
multi-master operation, 33-4  
parameter RAM, 33-10  
programming example  
master, 33-16  
SIUMCR (SIU module configuration register), 4-31  
SIVEC (SIU interrupt vector register), 4-23  
SMC memory map, 3-12  
SMCE (SMC event) register  
GCI mode, 26-34  
transparent mode, 26-28  
UART mode, 26-18  
SMCM (SMC mask) register  
GCI mode, 26-34  
transparent mode, 26-28  
UART mode, 26-18  
SMCMRs (SMC mode registers), 26-3  
SPCOM (SPI command) register, 33-9  
SPI memory map, 3-12  
slave, 33-17  
programming model, 33-6  
RxBD, 33-14  
slave mode, 33-4  
SPCOM, 33-9  
SPIE, 33-9  
SPIM, 33-9  
SPMODE, 33-6  
TxBD, 33-15  
SI memory map, 3-13  
SI RAM programming example, 14-13  
SICR (SIU interrupt configuration register), 4-17  
SIEXR (SIU external interrupt control register), 4-24  
Signals  
SPIE (SPI event) register, 33-9  
SPIM (SPI mask) register, 33-9  
SPMODE (SPI mode) register, 33-6  
SWR (software watchdog register), 4-7  
SWSR (software service register), 4-36  
SYPCR (system protection control register), 4-35  
System integration timers memory map, 3-4  
System interface unit (SIU)  
60x bus monitor function, 4-2  
BCR, 4-25  
block diagram, 4-1  
bus monitor, 4-3  
clocks, 4-4  
60x bus  
TBST, 8-13  
TCn, 8-13  
TSIZn, 8-13  
TTn, 8-10  
byte-select signals, 10-75  
chip-select signals, 10-74  
clock signals, 9-6  
general-purpose signals, 10-76, 10-76  
IDMA emulation  
DACKx, 18-13  
DONEx, 18-14  
configuration functions, 4-2  
configuration/protection logic block diagram, 4-3  
encoding the interrupt vector, 4-14  
FCC relative priority, 4-12  
highest priority interrupt, 4-13  
IMMR, 4-34  
interrupt controller features list, 4-7  
interrupt source priorities, 4-9  
interrupt vector calculation, 4-14  
interrupt vector encoding, 4-14  
interrupt vector generation, 4-14  
L_TESCR1, 4-38  
DREQx, 18-13  
memory controller  
L_TESCR2, 4-39  
LCL_ACR, 4-29  
byte-select signals, 10-11  
EAMUX, 10-41  
LCL_ALRH, 4-30  
LCL_ALRL, 4-30  
PSDVAL, 10-12, 10-57  
SDRAM interface signals, 10-33  
UPM interface signals, 10-62  
UPM signal negation, 10-78  
UPWAIT, 10-78  
local bus monitor function, 4-2  
masking interrupt sources, 4-13  
MCC relative priority, 4-12  
periodic interrupt timer (PIT), 4-5  
periodic interrupt timer (PIT) function, 4-2  
pin multiplexing, 4-44  
overview, 6-2  
SIPMR_H (SIU high interrupt mask register), 4-22  
SIPMR_L (SIU low interrupt mask register), 4-22  
SIPNR_H (SIU high interrupt pending register), 4-21  
SIPNR_L (SIU low interrupt pending register), 4-21  
SIPRR (SIU interrupt priority register), 4-18  
SIU memory map, 3-1  
PISCR, 4-42  
PITC, 4-43  
PITR, 4-44  
port C interrupts, 4-16  
PPC_ACR, 4-28  
PPC_ALRH, 4-28  
MOTOROLA  
Index  
Index-19  
INDEX  
PPC_ALRL, 4-29  
programming model, 4-17  
registers, 4-17  
SCC relative priority, 4-12  
SCPRR_H, 4-19  
SCPRR_L, 4-20  
SICR, 4-17  
SCC timing, controlling, 19-18  
TM_CMD (RISC timer command) register, 13-20  
TMCNT (time counter register), 4-41  
TMCNTAL (time counter alarm register), 4-41  
TMCNTSC (time counter status and control  
register), 4-40  
TMR (timer mode registers), 17-6  
TODR (transmit-on-demand register)  
AppleTalk mode, 25-4  
overview, 19-9  
TOSEQ (transmit out-of-sequence) register, 20-10  
Transparent mode  
achieving synchronization, 23-3  
commands, 23-7  
DSR receiver SYNC pattern lengths, 23-3  
end of frame detection, 23-6  
error handling, 23-8  
fast communications controllers (FCCs)  
features list, 32-2  
receive operation, 32-2  
SIEXR, 4-24  
signal multiplexing, 4-44  
SIMR_H, 4-22, 4-22  
SIPNR_H, 4-21  
SIPNR_L, 4-21  
SIPRR, 4-18  
SIUMCR, 4-31  
SIVEC, 4-23  
software watchdog timer, 4-6  
SWR, 4-7  
SWSR, 4-36  
SYPCR, 4-35  
system protection, 4-2  
TESCR1, 4-36  
TESCR2, 4-37  
synchronization  
achieving, 32-2  
time counter (TMCNT)  
function, 4-2  
overview, 4-4  
timers, 4-4  
TMCNT, 4-41  
example, 32-4  
external signals, 32-3  
in-line pattern, 32-3  
transmit operation, 32-2  
frame reception, 23-2  
frame transmission, 23-2  
inherent synchronization, 23-6  
in-line synchronization, 23-6  
overview, 23-1  
TMCNTAL, 4-41  
TMCNTSC, 4-40  
T
programming example, 23-13  
RxBD, 23-9  
serial management controllers (SMCs)  
features list, 26-21  
overview, 26-20  
parameter RAM, 26-6  
reception process, 26-21  
synchronization signals, 23-4  
synchronization, user-controlled, 23-5  
transmit synchronization, 23-3  
TxBD, 23-10  
TBST (transfer burst) signal, 8-13  
TCN (timer counter registers), 17-8  
TCn (transfer code) signals, 8-13  
TCR (timer capture registers), 17-8  
TER (timer event registers), 17-8  
Terminology conventions, lxiv  
TESCRx (60x bus error status and control  
registers), 4-36, 10-33  
TFCR (Tx buffer function code register)  
overview, 19-15  
TGCR (timer global configuration registers), 17-4  
Timers  
block diagram, 17-1  
TRR (timer reference registers), 17-7  
TSIZn (transfer size) signals, 8-13  
TSTATE (internal transmitter state) register, 27-9  
TTn (transfer type) signals, 8-10  
bus monitoring, 17-3  
cascaded mode block diagram, 17-4  
features, 17-2  
U
UART mode  
commands, 20-6  
general-purpose units, 17-2  
pulse measurement, 17-3  
Time-slot assigner  
connecting to the TSA, 14-7  
Time-slot assigner (TSA)  
synchronization in transparent mode, 23-5  
Timing  
control character insertion, 20-10  
data handling, character and message-based, 20-5  
error reporting, 20-6  
features list, 20-2  
Index-20  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
INDEX  
fractional stop bits, 20-11  
handling errors, 20-12  
hunt mode, 20-10  
software requests, 10-66  
UPWAIT signal, 10-78  
wait mechanism, 10-78  
memory map, 20-4  
normal asynchronous mode, 20-3  
overview, 20-1  
parameter RAM, 20-4  
programming example, 20-22  
RxBD, 20-15  
serial management controllers  
character mode, 26-12  
commands, 26-12  
data handling, 26-12  
error handling, 26-13  
features list, 26-11  
features not supported by SMCs, 26-10  
frame format, 26-11  
message-oriented mode, 26-12  
overview, 26-10  
parameter RAM, 26-6  
programming example, 26-19  
reception process, 26-12  
RxBD, 26-14  
transmission process, 26-11  
TxBD, 26-16  
S-records loader application, 20-23  
status reporting, 20-6  
synchronous mode, 20-3  
TxBD, 20-18  
UPMs (user-programmable machines)  
access times, handling devices, 10-100  
address control bits, 10-77  
address mulitplexing, 10-77  
clock timing, 10-67  
data sample control, 10-77  
data valid, 10-77  
differences between MPC8xx and MPC8260, 10-80  
DRAM configuration example, 10-79  
EDO interface example, 10-92  
exception requests, 10-66  
hierarchical bus interface example, 10-100  
implementation differences with SDRAM machine  
and GPCM, 10-7  
loop control, 10-76  
memory access requests, 10-65  
memory system interface example, 10-81  
MPC8xx versus MPC8260, 10-80  
overview, 10-62  
programming the UPM, 10-66  
RAM array, 10-69  
RAM word, 10-70  
refresh timer requests, 10-65  
register settings, 10-80  
requests, 10-64  
signal negation, 10-78  
MOTOROLA  
Index  
Index-21  
INDEX  
Index-22  
MPC8260 PowerQUICC II UserÕs Manual  
MOTOROLA  
Overview  
PowerPC Processor Core  
Memory Map  
1
2
3
System Interface Unit (SIU)  
4
Reset  
External Signals  
5
6
60x Signals  
The 60x Bus  
7
8
Clocks and Power Control  
Memory Controller  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
Secondary (L2) Cache Support  
IEEE 1149.1 Test Access Port  
Communications Processor Module Overview  
Serial Interface with Time-Slot Assigner  
CPM Multiplexing  
Baud-Rate Generators (BRGs)  
Timers  
SDMA Channels and IDMA Emulation  
Serial Communications Controllers (SCCs)  
SCC UART Mode  
SCC HDLC Mode  
SCC BISYNC Mode  
SCC Transparent Mode  
SCC Ethernet Mode  
SCC AppleTalk Mode  
Serial Management Controllers (SMCs)  
Multi-Channel Controllers (MCCs)  
Fast Communications Controllers  
ATM Controller  
Fast Ethernet Controller  
FCC HDLC Controller  
FCC Transparent Controller  
Serial Peripheral Interface (SPI)  
2
I C Controller  
Parallel I/O Ports  
Register Quick Reference Guide  
A
Glossary  
Index  
GLO  
IND  
1
Overview  
PowerPC Processor Core  
Memory Map  
System Interface Unit (SIU)  
2
3
4
Reset  
External Signals  
5
6
60x Signals  
The 60x Bus  
7
8
Clocks and Power Control  
Memory Controller  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
Secondary (L2) Cache Support  
IEEE 1149.1 Test Access Port  
Communications Processor Module Overview  
Serial Interface with Time-Slot Assigner  
CPM Multiplexing  
Baud-Rate Generators (BRGs)  
Timers  
SDMA Channels and IDMA Emulation  
Serial Communications Controllers (SCCs)  
SCC UART Mode  
SCC HDLC Mode  
SCC BISYNC Mode  
SCC Transparent Mode  
SCC Ethernet Mode  
SCC AppleTalk Mode  
Serial Management Controllers (SMCs)  
Multi-Channel Controllers (MCCs)  
Fast Communications Controllers  
ATM Controller  
Fast Ethernet Controller  
FCC HDLC Controller  
FCC Transparent Controller  
Serial Peripheral Interface (SPI)  
2
I C Controller  
Parallel I/O Ports  
Register Quick Reference Guide  
A
Glossary  
Index  
GLO  
IND  
Attention!  
This book is a companion to the PowerPC Microprocessor Family: The Programming  
Environments, referred to as The Programming Environments Manual. Note that the  
companion Programming Environments Manual exists in two versions. See the Preface for  
a description of the following two versions:  
¥
PowerPC Microprocessor Family: The Programming Environments, Rev 1  
Order #: MPCFPE/AD  
¥
PowerPC Microprocessor Family: The Programming Environments for 32-Bit  
Microprocessors, Rev 1  
Order #: MPCFPE32B/AD  
Call the Motorola LDC at 1-800-441-2447 (website: http://ldc.nmd.com) or contact your  
local sales ofÞce to obtain copies.  

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