SERVICE MANUAL FOR
8050QMA
BY: ZX Xiao
Repair Technology Research Department /EDVD
Jun.2005 / R01
8050QMA N/B Maintenance
Contents
5. Pin Description of Major Component …….……………………………………………………………….
5.1 Intel 915PM North Bridge ……………………………………………………………………………………………….
5.2 Intel ICH6-M South Bridge ………………………………………………………………………………………………
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6. System Block Diagram ……………………………………………………………………………………… 98
7. Maintenance Diagnostics …………………………………………………………………………………… 99
7.1 Introduction ………………………………………………………………………………………………………………..
7.2 Maintenance Diagnostics…………………………………………………………………………………………………..
7.3 Error Codes ………………………………………………………………………………………………………………..
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8. Trouble Shooting ……………………………………………………………………………………………. 103
8.1 No Power ……………………………………………………………………………………………………………………
8.2 No Display ………………………………………………………………………………………………………………….
8.3 VGA Controller Failure LCD No Display ………………………………………………………………………………..
8.4 External Monitor No Display ……………………………………………………………………………………………..
8.5 Memory Test Error ………………………………………………………………………………………………………..
8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error ……………………………………………………………………………
8.7 Hard Drive Test Error ……………………………………………………………………………………………………
8.8 CD-ROM Drive Test Error ………………………………………………………………………………………………
8.9 USB Port Test Error ……………………………………………………………………………………………………….
8.10 Audio Failure ……………………………………………………………………………………………………………..
8.11 LAN Test Error …………………………………………………………………………………………………………..
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Contents
8.12 PC Card Socket Failure …………………………………………………………………………………………………
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9. Spare Parts List ……………………………………………………………………………………………... 136
10. Reference Material …...……………………………………………………………………………………. 150
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1. Hardware Engineering Specification
1.1 Introduction
1.1.1 General Description
This document describes the brief introduction for MiTAC 8050QMA portable notebook computer system.
1.1.2 System Overview
The MiTAC 8050Q model is designed for Intel Dothan processor with 533MHz FSB with Micro-FCPGA package.
This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has
standard hardware peripheral interface. The power management complies with Advanced Configuration and Power
Interface. It also provides easy configuration through CMOS setup, which is built in system BIOS software and can
be pop-up by pressing F2 key at system start up or warm reset. System also provides icon LEDs to display system
status, such as AC Power indicator, Battery Power indicator, Battery status indicator, HDD,CD-ROM, NUM
LOCK, CAP LOCK, SCROLL LOCK, Wireless on/off Card Reader Accessing. It also equipped with LAN, 56K
Fax MODEM, 4 USB port, S-Video and audio line in/out , external microphone function.
The memory subsystem supports DDR or DDR2 SDRAM channels (64-bits wide).
The 915PM MCH Host Memory Controller integrates a high performance host interface for Intel Dothan processor,
a high performance PCI Express interface, a high performance memory controller and Direct Media Interface
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(DMI) connecting with Intel ICH6-M.
The Intel ICH6-M integrates three Universal Serial Bus 2.0 Host Controllers Interface (UHCI), the Audio
Controller with AC97 interface, the Ethernet includes a 32-bit PCI controller, the IDE Master/Slave controllers, the
SATA controller and Direct Media Interface technology.
The Realtek RTL8100CL is a highly integrated, cost-effective single-chip Fast Ethernet controller that provides 32-
bit performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications and
IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration Power management Interface
(ACPI).
The VT6301S is a single chip PCI Host Controller for IEEE 1394-1995 Release 1.0 and IEEE 1394a P2000. It
implements the Link and PHY layers for IEEE 1394-1995 High Performance Serial Bus specification release 1.0
and 1394a P2000. It is compliant with 1394 Open HCI 1.0 and 1.1 with DMA engine support for high performance
data transfer via a 32-bit bus master PCI host bus interface. The VT6301S supports 100, 200 and 400 Mbit/sec
transmission via an integrated 1-port PHY. The VT6301S services two types of data packets: asynchronous and
isochronous (real time). The 1394 link core performs arbitration requesting, packet generation and checking, and
bus cycle master operations. It also has root node capability and performs retry operations.
The ENE CB712 CardBus/Media Reader controller functions as a single slot PCI to Cardbus bridge and also PCI
interface MS/SD/MMC flash card reader. The CB712 provide one Cardbus slot and all reader interface may
operate simultaneously.
The W83L950D is a high performance microcontroller on-chip supporting functions optimized for embedded
control. These include ROM, RAM, four types of timers, a serial communication interface, optional I²C bus
interface, host interface, A/D converter, D/A converter, I/O ports and other functions needed in control system
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configurations, so that compact, high performance systems can be implemented easily.
A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME,
Windows 2000 and Windows XP to take full advantage of the hardware capabilities. Features such as bus mastering
IDE, Plug and Play, Advanced Power Management (APM) with application restart, software-controlled power
shutdown.
Following chapters will have more detail description for each individual sub-systems and functions.
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1.2 System Hardware Parts
Intel® Pentium® M Processor (Dothan) 90nm, 2M L2, 533 MHz FSB
Intel® Celeron® M processor, 90nm, 512K L2, 400 MHz FSB
CPU
Intel 915PM + ICH6-M chipset
SST49LF004A
Core logic
System BIOS
0MB DDR2-SDRAM on Board
Expandable with combination of optional 128MB/256MB/512MB/1GB(P) memory
Two 200-pin DDR2 400/533 SDRAM Memory Module
Memory
Type I MXM Interface (max 25W) with 8 cells Vram
Priority at launch: NV44M + 32MB discrete Vram + Turbo Memory
VGA Control
ICS 954226
VT6301S
Clock Generator
IEEE1394
RTL8100CL
ENE CB712
LAN
PCMCIA + 4 IN 1 CARD
AC97 CODEC: Advance Logic, Inc, ALC655
Power Amplifier: TI TPA0212
Audio System
Modem
AC97 Link: MDC (Mobile Daughter Card) Askey: V1456VQL-P1(INT)
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1.2.1 Intel Dothan Processors in Micro-FCBGA Package
Intel Dothan Processors with 479 pins Micro-FCBGA package.
It will be manufactured on Intel’s advanced 90 nanometer process technology with copper interconnect. It’s features
include Intel Architecture with Dynamic Execution, On-die primary 32-kB instruction cache and 32-kB write-back
data cache, on-die 2-MB second level cache with advanced Transfer Cache Architecture, Data Prefetch Logic,
Streaming SIMD Extensions 2 (SSE2), 533-MHz FSB.
The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications
including 3-D graphics, video decoding/encoding, and speech recognition.
Use Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times
per bus clock.
Support Enhanced Intel SpeedStep technology, which enables real-time dynamic switching of the voltage and
frequency between two performance modes.
1.2.2 Clock Generator
System frequency synthesizer: ICS954226 is a CK410M Compliant clock synthesizer. It provides a single-chip
solution for mobile systems built with Intel P4-M processors and Intel mobile chipsets. It is driven with a
14.318MHz crystal and generates CPU outputs up to 400MHz. It provides the tight ppm accuracy required by
Serial ATA and PCI-Express.
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• Supports tight ppm accuracy clocks for Serial-ATA and SRC.
• Supports spread spectrum modulation, 0 to –0.5% down spread.
• Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning.
• Supports undriven differential CPU, SRC pair in PD# for power management.
1.2.3 The Mobile Intel 915PM Express Chipset
The Mobile Intel 915PM Express Chipset integras a memory controller hub (MCH) designed for use with the
Dothan, Yonah and Intel Celeron M Processor. It is PCI Express based Graphics.
The 915PM MCH integrates a system memory DDR/DDR2 controller with two, 64-bit wide interfaces. Only
Double Data Rate (DDR/DDR2) memory is supported; the buffers support DDR SSTL_2 and DDR2 SSTL_18
signaling interfaces. The memory controller interface is fully configurable through a set of control registers. It
integras a high performance transition interface PCI Express Interface. PCI Express operates at a data rate of 2.5
for 8050QMA project. GB/s. This allows a maximum theoretical bandwidth of 40 GB/s each direction. The 915PM
MCH integrates Direct media interface (DMI) chip-to-chip interconnect between the MCH and ICH6-M. DMI
supports DMI x2 and DMI x4 configuration.
Features:
ꢀ Processor/FSB Support
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• Intel® Dothan processor
• AGTL+ bus driver technology with integrated GTL termination resistors (gated AGTL+ receivers for reduced
power)
• Supports 32-bit AGTL+ host bus addressing
• Supports system bus at 533MT/s (533 MHz) and 400MT/s (400 MHz)
• 2X Address, 4X data
• Host bus dynamic bus inversion HDINV support
• 12 deep, in-order queue
ꢀ Memory System
• Directly supports to two DDR or DDR2 SDRAM channels, 64-bts wide.
• Supports SO-DIMMs of the same type (e.g.,all DDR or all DDR2), not mixed.
• Maximum of two, double-sided unbuffered SO-DIMMs (4 rows populated)
• Minimum amount of memory supported is 128 MB (16 MB x 16-b x 4 devices x 1 rows = 128 MB) using
256-MB technology
• Maximum amount of memory supported is 2 GB using 1-GB technology.
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• 256-MB, 512-MB and 1-GB technology using x8 and x16 devices.
• Three memory channel organizations are supported for DDR / DDR2 :
– Single channel
– Dual channel interleaved
– Dual channel asymmetric
• Supports DDR 333 devices and DDR2 400 /533 devices
– Supports on-die termination (ODT) for DDR2
• Supports Fast Chip Select mode
• Supports partial write to memory using Data Mask signal (DM)
• Supports high-density memory package for DDR or DDR2 type devices
ꢀ PCI Express Interface
• One x16 (16 lanes) PCI Express port intended for graphics attach
• Maximum theoretical realized bandwidth on interface of 4 GB/s in each direction simultaneously, for an
average of 8 GB/s when x16
• Automatic discovery, negotiation and training of link out of reset
• Supports traditional PCI style traffic (asynchronous snooped, PCI ordering)
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• Supports only 1.5-V AGP electrics
• 32 deep AGP request queue
• Hierarchical PCI-compliant configuration mechanism for downstream devices
• Direct Media Interface (DMI)
– Chip-to-chip interconnect between the GMCH and ICH6-M
– DMI x2 and DMI x4 configuration supported
– Bit swapping is supported
– Lane reversal is not supported
1.2.4 I/O Controller Hub : Intel ICH6-M
The ICH6 provides extensive I/O support. Functions and capabilities include:
• PCI Express Base Specification, Revision 1.0a-compliant
• PCI Local Bus Specification, Revision 2.3-compliant with support for 33 MHz PCI operations(supports up to
seven Req/Gnt pairs)
• ACPI Power Management Logic Support
• Enhanced DMA controller, interrupt controller and timer functions
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• Integrated Serial ATA host controller with independent DMA operation on two ports and AHCI support
• Integrated IDE controller supports Ultra ATA100/66/33
• USB host interface with support for three USB ports; three UHCI host controllers; one EHCI high-speed
USB2.0 Host controller
• Integrated LAN controller
• System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices
• Supports Audio Codec ’97, Revision 2.3 Specification (a.k.a.,AC ’97 Component Specification, Revision 2.3)
which provides a link for Audio and Telephony codecs (up to 7 channels)
• Supports Intel High Definition Audio
• Low Pin Count (LPC) interface
• Firmware Hub (FWH) interface support
1.2.5 CardBus: CB712
Features:
3.3V operation with 5V tolerant
LFBGA 169-ball package
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Pin out Compatible with CB1410
• PCI Interface
– Compliant with PCI Local Bus Specification Revision 2.3
– Compliant with PCI Bus Power Management Interface Specification Revision 1.1
– Compliant with PCI Mobile Design Guide Version 1.1
– Compliant with Advanced Configuration and Power Interface Specification Revision 1.0
• CardBus Interface
– Compliant with PC Card Standard 8.0
– Support Standardized Zoomed Video Register Model
– Support SPKROUT CAUDIO and RIOUT#
• Secure Digital Interface
– Compliant with SD Host Controller Standard Specification Version 1.0
– Support SD Suspend/Resume Functionality
– Support DMA Mode to Minimize CPU Overhead
– Support High Speed with the SD Clock Frequency Up to 50Mhz
– Contain two 512-byte buffer to maximize the transfer speed
– Support Traffic LED Light
– Support Over Current Protection
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• Memory Stick Interface
– Compliant with Memory Stick PRO Format Specification Version 1.0
– Support 4-bit Parallel Data Transfer Mode
– Memory Stick Clock Frequency Up to 40Mhz
– Support DMA Mode to Minimize CPU Overhead
– Support Traffic LED Light
– Support Over Current Protection
• Interrupt Configuration
– Support Parallel PCI Interrupts
– Support Parallel IRQ and Parallel PCI Interrupts
– Support Serialized IRQ and Parallel PCI Interrupts
– Support Serialized IRQ and PCI Interrupts
• Power Management Control Logic
– Support CLKRUN# protocol
– Support SUSPEND#
– Support PCI PME# from D3, D2, D1 and D0
– Support PCI PME# from D3cold
• Support Zoomed Video port
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• Support parallel 4-wire power switch interface
1.2.6 AC’97 Audio System: Advance Logic, Inc, ALC655
The ALC655 is a 16-bit, full duplex AC'97 2.3 compatible six channels audio CODEC designed for PC multimedia
systems, including host/soft audio and AMR/CNR based designs. The ALC655 incorporates proprietary converter
technology to meet performance requirements on PC99/2001 systems. The ALC655 CODEC provides three pairs of
stereo outputs with 5-Bitvolume controls, a mono output, and multiple stereo and mono inputs, along with flexible
mixing, gain and mute functions to provide a complete integrated audio solution for PCs. The digital interface
circuitry of the ALC655 CODEC operates from a 3.3V power supply for use in notebook and PC applications. The
ALC655 integrates 50mW/20ohm headset audio amplifiers at
Front-Out and Surr-Out, built-in 14.318M 24.576MHz PLL and PCBEEP generator, those can save BOM costs. The
ALC655 also supports the S/PDIF input and output function, which can offer easy connection of PCs to consumer
electronic products, such as AC3 decoder/speaker and mini disk devices. ALC655 supports host/soft audio from Intel
ICH6 chipsets as well as audio controller based VIA/SIS/ALI/AMD/nVIDIA/ATI chipset. Bundled Windows series
drivers (WinXP/ME/2000/98/NT), EAX/
Direct Sound 3D/ I3DL2/ A3D compatible sound effect utilities (supporting Karaoke, 26-kind of environment sound
emulation,10-band equalizer), HRTF 3D positional audio and Sensaura™ 3D (optional) provide an excellent
entertainment package and game experience for PC users. Besides, ALC655 includes Realtek’s impedance sensing
techniques that makes device load on outputs and inputs can be detected.
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• Meets performance requirements for audio on PC99/2001 systems
• Meets Microsoft WHQL/WLP 2.0 audio requirements
• 16-bit Stereo full-duplex CODEC with 48KHz sampling rate
• Compliant with AC’97 2.3 specifications
– 14.318MHz- 24.576MHz PLL to save crystal
– 12.288MHz BITCLK input can be consumed
– Integrated PCBEEP generator to save buzzer
– Interrupt capability
• Three analog line-level stereo inputs with 5-bit volume control: LINE_IN, CD, AUX
• High quality differential CD input
• Two analog line-level mono input: PCBEEP,PHONE-IN
• Two software selectable MIC inputs applications (software selectable)
• Boost preamplifier for MIC input 50mW/20 amplifier
• External Amplifier Power Down (EAPD) capability
• Power management and enhanced power saving features
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• Stereo MIC record for AEC/BF application
• Supports Power Off CD function
• Adjustable VREFOUT control Supports double sampling rate (96KHz) of DVD audio playback
• Support 48KHz of S/PDIF output is compliant with AC’97 rev2.3 specification
• Power support: Digital: 3.3V; Analog: 3.3V/5V
1.2.7 MDC: Pctel Modem Daughter Card PCT2303W (Askey V1456VQL-P1)
The PCT2303W chipset is designed to meet the demand of this emerging worldwide AMR/MDC market. The
combination of PC-TEL’s well proven PCT2303W chipset and the HSP56TM MR software modem driver allows
systems manufactures to implement modem functions in PCs at a lower bill of materials (BOM) while maintaining
higher system performance.
PC-TEL has streamlined the traditional modem into the Host Signal Processing (HSP) solution. Operating with the
Pentium class processors, HSP becomes part of the host computer’s system software. It requires less power to
operate and less physical space than standard modem solutions. PC-TEL’s HSP modem is an easily integrated, cost-
effective communications solution that is flexible enough to carry you into the future.
The PCT2303W chip set is an integrated direct access arrangement (DAA) and Codec that provides a programmable
line interface to meet international telephone line requirements. The PCT2303W chip set is available in two 16-pin
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small outline packages (AC’97 interface on PCT303A and phone-line interface on PCT303W). The chip set
eliminates the need for an AFE, an isolation transformer, relays, opto-isolators, and 2-to 4-wire hybrid. The
PCT2303W chip set dramatically reduces the number of discrete components and cost required to achieve
compliance with international regulatory requirements. The PCT2303W complies with AC’97 Interface specification
Rev. 2.1.
The chip set is fully programmable to meet world-wide telephone line interface requirements including those
described by CTR21, NET4, JATE, FCC, and various country-specific PTT specifications. The programmable
parameters of the PCT2303W chip set include AC termination, DC termination, ringer impedance, and ringer
threshold. The PCT2303W chip set has been designed to meet stringent world-wide requirements for out-of-band
energy, billing-tone immunity, lightning surges, and safety requirements.
Features:
Virtual com port with a DTE throughout up to 460.8Kbps.
G3 Fax compatible
Auto dial and auto answer
Ring detection
ꢀ Codec/DAA Features
• AC97 2.1 compliant
• 86dB dynamic range TX/RX paths
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• 2-4-wire hybrid
• Integrated ring detector
• High voltage isolation of 4000V
• Support for “Caller ID”
• Compliant with FCC Part68, CTR21, Net4 and JATE
• Low power standby
• Low profile SOIC package 16 pins 10x3x1.55mm
• Low power consumption
• 10mA @ 3.3V operation
• 1mA @ 3.3V power down
• Integrated modem codec
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ꢀ Standard Features
• Data
– ITU-T V.90 (56Kbps), V.34 (4.8Kbps TO 33.6 Kbps), V.32 bis (4.8Kbps to 14.4Kbps), V.22 bis (1.2 bps
to 2.4 Kbps), V.21 and Bell 103 and 212A(300 to 1200 bps) modulation protocol
– Data Compression ITU-T V.42bis MNP Class 5
– Error Correction ITU-T V.42 LAPM MNP 2-4
• Fax
– ITU-T V. 17, V.29, V.27ter, V.21, Channel 2, Group 3, EIA Class I
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1.2.8 IEEE1394 VT6301S
1.2.8.1 Overview
The VT6301S IEEE 1394 OHCI Host Controller provides high performance serial connectivity. It implements
the Link and Phy layers for IEEE 1394-1995 High Performance Serial Bus specification release 1.0 and 1394a-
2000. It is compliant with 1394 Open HCI 1.0 and 1.1 with DMA engine support for high performance data
transfer via a 32-bit bus master PCI host bus interface. The VT6301S supports 100, 200 and 400 Mbit/sec
transmission via an integrated 1-port PHY. The VT6301S services two types of data packets: asynchronous and
isochronous (real time). The 1394 link core performs arbitration requesting, packet generation and checking,
and bus cycle master operations. It also has root node capability and performs retry operations. The VT6301S is
ready to provide industry-standard IEEE 1394 peripheral connections for desktop and mobile PC platforms.
Support for the VT6301S is built into Microsoft Windows 98, Windows ME, Windows 2000 and Windows XP
1.2.8.2 Features
• 32 bit CRC generator and checker for receive and transmit data
• On-chip isochronous and asynchronous receive and transmit FIFOs for packets (2K for general
receive plus 2K for isochronous transmit plus 2K for asynchronous transmit)
• 8 isochronous transmit contexts
• 4 isochronous receive contexts
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• 3-deep physical post-write queue
• 2-deep physical response queue
• Dual buffer mode enhancements
• Skip Processing enhancements
• Block Read Request handling
• Ack_tardy processing
1.2.9 System Flash Memory (BIOS)
Firmware Hub for Intel® 810, 810E, 815, 815E,815EP, 820, 840, 850 Chipsets
Flexible Erase Capability
– Uniform 4 KByte Sectors
– Uniform 16 KByte overlay blocks for SST49LF002A
– Uniform 64 KByte overlay blocks for SST49LF004A
– Top boot block protection
– 16 KByte for SST49LF002A
– 64 KByte for SST49LF004A
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– Chip-Erase for PP Mode
Single 3.0-3.6V Read and Write Operations
Superior Reliability
Firmware Hub Hardware Interface Mode Supports Intel High Definition Audio
– 5-signal communication interface supporting byte Read and Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write protect for entire chip and/or top Boot Block
– Block Locking Register for all blocks
– Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Write detection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
1.2.10 Memory System
1.2.10.1 256MB, 512MB, 1GB (x64) 200-Pin DDR2 SDRAM SODIMMs
• JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM)
• VDD=+1.8V±0.1V, VDDQ=+1.8V±0.1V
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• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS,DQS#) option
• Four-bit prefetch architecture
• Differential clock input (CK,CK#)
• Command entered on each rising CK edge
• DQS edge-aligned with data for Reads
• DQS center-aligned with data for Writes
• Duplicate output strobe (RDQS) option for x8 configuration
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
• Programmable CAS Latency (CL) : 2,3,4 and 5
• Posted CAS additive latency (AL) : 0,1,2,3 and 4
• Write latency = Read latency – 1tCK
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• Programmable burst lengths : 4 or 8
• Read burst interrupt supported by another READ
• Write burst interrupt supported by another WRITE
• Adjustable data – output drive strength
• Concurrent auto precharge option is supported
• Auto Refresh (CBS) and Self Refresh Mode
• 64ms, 8,192-cycle refresh
• Off-chip drive (OCD) impedance calibration
• On-die termination (ODT)
1.2.11 LAN PHY: RTL8100C(L)
General
The Realtek RTL8100C(L) is a highly integrated, cost-effective single-chip Fast Ethernet controller that provides 32-
bit performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications and
IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration Power management Interface
(ACPI), PCI power management for modern operating systems that are capable of Operating System Directed Power
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Management (OSPM) to achieve the most efficient power management possible. The RTL8100C(L) does not
support CardBus mode as the RTL8139C does. In addition to the ACPI feature, the RTL8100C(L) also supports
remote wake-up (including AMD Magic Packet, LinkChg, and Microsoft® wake-up frame) in both ACPI and APM
environments. The RTL8100C(L) is capable of performing an internal reset through the application of auxiliary
power. When auxiliary power is applied and the main power remains off, the RTL8100C(L) is ready and waiting for
the Magic Packet or Link Change to wake the system up. Also, the LWAKE pin provides 4 different output signals
including active high, active low, positive pulse, and negative pulse. The versatility of the RTL8100C(L) LWAKE
pin provides motherboards with Wake-On-LAN (WOL) functionality. The RTL8100C(L) also supports Analog
Auto-Power-down, that is, the analog part of the RTL8100C(L) can be shut down temporarily according to
user requirements or when the RTL8100C(L) is in a power down state with the wakeup function disabled. In
addition, when the analog part is shut down and the IsolateB pin is low (i.e. the main power is off), then both the
analog and digital parts stop functioning and the power consumption of the RTL8100C(L) will be negligible.
The RTL8100C(L) also supports an auxiliary power auto-detect function and will auto-configure related bits
of their own PCI power management registers in PCI configuration space.
• 128 pin QFP/LQFP
• Integrated Fast Ethernet MAC, Physical chip and transceiver in one chip
• 10 Mb/s and 100 Mb/s operation
• Supports 10 Mb/s and 100 Mb/s N-way Auto-negotiation operation
• PCI local bus single-chip Fast Ethernet controller
1. Compliant to PCI Revision 2.2
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2. Supports PCI clock 16.75MHz-40MHz
3. Supports PCI target fast back-to-back transaction
4. Provides PCI bus master data transfers and PCI memory space or I/O space mapped data transfers of
RTL8100C(L)'s operational registers
5. Supports PCI VPD (Vital Product Data)
6. Supports ACPI, PCI power management
• Supports 25MHz crystal or 25MHz OSC as the internal clock source. The frequency deviation of either crystal
or OSC must be within 50 PPM.
• Compliant to PC99/PC2001 standard
• Supports Wake-On-LAN function and remote wake-up (Magic Packet*, LinkChg and Microsoft® wake-up
frame)
• Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse and negative pulse)
• Supports auxiliary power-on internal reset, to be ready for remote wake-up when main power still remains off
• Supports auxiliary power auto-detect, and sets the related capability of power management registers in PCI
configuration space
• Includes a programmable, PCI burst size and early Tx/Rx threshold
• Supports a 32-bit general-purpose timer with the external PCI clock as clock source, to generate timer-interrupt
• Contains two large (2Kbyte) independent receive and transmit FIFOs
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• Advanced power saving mode when LAN function or wakeup function is not used
• Uses 93C46 (64*16-bit EEPROM) to store resource configuration, ID parameter and VPD data
• Supports LED pins for various network activity indications
• Supports loop back capability
• Half/Full duplex capability
• Supports Full Duplex Flow Control (IEEE 802.3x)
1.2.12 Keyboard System: Winbond W83L950D
The Winbond Keyboard controller architecture consists of a Turbo 51 core controller surrounded by various registers,
nine general purpose I/O port, 2k+256 bytes of RAM, four timer/counters, dual serial ports, 40K MTP-ROM that is
divided into four banks, two SMBus interface for master and slave, Support 4 PWM channels, 2 D-A and 8 A-D
converters.
• 8051 uC based
• Keyboard Controller Embedded Controller
• Supply embedded programmable flash memory (internal ROM size: 40KB) and RAM size is 2 KB
• Support 4 Timer (8 bit) signal with 3 prescalers
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• Support 2 PWM channels, 2 D-A and 8 A-D converters
• Reduce Firmware burden by Hardware PS/2 decoding
• Support 72 useful GPIOs totally
• Support Flash utility for on board re-flash
• Support ACPI
• Hardware fast Gate A20 with software programmable
1.2.13 Hard Disk Drive
IDE HDD
The ICH6 IDE controller features one set of interface signals that can be enabled, tri-stated or driven low. The IDE
interfaces of the ICH6 can support several types of data transfers:
• Programmed I/O (PIO): processor is in control of the data transfer
• 8237 style DMA: DMA protocol that resembles the DMA on the ISA bus, although it does not use the 8237 in
the ICH6. This protocol off loads the processor from moving data. This allows higher transfer rate of up to
16MB/s
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• Ultra ATA/33/66/100: DMA protocol that redefines signals on the IDE cable to allow both host and target
throttling of data and transfer rates of up to 33/66/100 MB/s
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1.3 Other Functions
1.3.1 Hot Key Function
Keys
Combination
Feature
Meaning
Mini PCI power down
Fn + F1
Power down
Reserve
Fn + F2
Fn + F3
Fn + F4
Volume Down
Volume Up
Rotate display mode in LCD only, CRT only, and
simultaneously display.
Fn + F5
LCD/external CRT switching
Fn + F6
Fn + F7
Fn + F10
Fn + F11
Brightness down
Brightness up
Decreases the LCD brightness
Increases the LCD brightness
On/Off Battery Low Beep
Toggle Panel on/off
Battery Low Beep
Panel Off/On
Force the computer into either Suspend to HDD or
Suspend to DRAM mode depending on BIOS Setup.
Fn + F12
Suspend to DRAM / HDD
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1.3.2 Power On/Off/Suspend/Resume Button
1.3.2.1 APM Mode
At APM mode, Power button is on/off system power.
1.3.2.2 ACPI Mode
At ACPI mode. Windows power management control panel set power button behavior.
You could set “standby”, “power off” or “hibernate”(must enable hibernate function in power Management) to
power button function.
Continue pushing power button over 4 seconds will force system off at ACPI mode.
1.3.3 Cover Switch
System automatically provides power saving by monitoring Cover Switch. It will save battery power and prolong
the usage time when user closes the notebook cover.
At ACPI mode there are four functions to be chosen at windows power management control panel.
1. None
2. Standby
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3. Off
4. Hibernate (must enable hibernate function in power management)
1.3.4 LED Indicators
1.3.4.1 Three LED Indicators at Front Side:
From left to right that indicate BATTERY POWER, BATTERY STATUS and AC POWER
-- AC POWER:
This LED lights green when the notebook was powered by AC power line, Flashes (on 1 second, off 1
second) when entered suspend to RAM state with AC powered. The LED is off when the notebook is in
power off state or powered by battery.
-- BATTERY POWER
This LED lights green when the notebook is being powered by Battery, and flashes (on 1 second, off 1
second) when entered suspend to RAM state with AC powered. The LED is off when the notebook is in
power off state or powered by AC adapter.
-- BATTERY STATUS:
During normal operation, this LED stays off as long as the battery is charged. When the battery charge
drops to 10% of capacity, the LED lights red, flashes per 1 second and beeps per 2 second. When AC is
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connected, this indicator glows green if the battery pack is fully charged or orange (amber) if the battery is
being charged.
AC POWER: This LED lights green when AC is powering the notebook, and flash (on 1 second, off 1 second)
when Suspend to RAM no matter using AC power or Battery power. The LED is off when the
notebook is off or powered by battery.
BATTERY POWER: This LED lights green when the notebook is being powered by Battery, and flash (on 1
second, off 1 second) when Battery is low. The LED is off when the notebook is off or
powered by AC adaptor.
1.3.4.2 Seven LED Indicators:
System has seven status LED indicators at front side which to display system activity. From left to right that
indicate HARD DISK, CD-ROM, NUM LOCK, CAPS LOCK, SCROLL LOCK, Wireless on/off, Card Reader
Accessing Blue-Tooth.
1.3.5 Battery Status
1.3.5.1 Battery Warning
-- System also provides Battery capacity monitoring and gives users a warning signal to alarm they to
store data before battery dead. This function also protects system from mal-function while battery
capacity is low.
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-- Battery Warning: Capacity below 10%, Battery Capacity LED flashes , and system beeps per 2 seconds.
-- System will Suspend to HDD after 2 Minutes to protect users data.
1.3.5.2 Battery Low State
After Battery Warning State, and battery capacity is below 5%, system will generate beep sound for twice per
second.
1.3.5.3 Battery Dead State
When the battery voltage level reaches 11.5 volts, system will shut down automatically in order to extend the
battery packs' life.
1.3.6 Fan Power On/Off Management
FAN is controlled by W83L950D embedded controller-using ADT7460 to sense CPU and VGA temperature and
PWM control fan speed. Fan speed is depended on CPU and VGA temperature. Higher CPU or VGA temperature
faster Fan Speed.
1.3.7 CMOS Battery
CR2032 3V 220mAh lithium battery
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When AC in or system main battery inside, CMOS battery will consume no power.
AC or main battery not exists, CMOS battery life at less (220mAh/5.8uA) 4 years.
1.3.8 I/O Port
One Power Supply Jack
One External DVI-I Connector For DVI Display
Supports four USB port for all USB devices.
One MODEM RJ-11 phone jack for PSTN line
One RJ-45 for LAN.
One IEEE1394 port
One TV-Out port
Reserve 1 connector on board for USB 2.0 Device
Headphone Out Jack.
Microphone Input Jack.
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Line in Jack
1.3.9 Battery Current Limit and Learning
Implanted H/W current limit and battery learning circuit to enhance protection of battery.
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1.4 Power Management
The 8050MB system has built in several power saving modes to prolong the battery usage for mobile purpose. User
can enable and configure different degrees of power management modes via ROM CMOS setup (booting by pressing
F2 key). Following are the descriptions of the power management modes supported.
1.4.1 System Management Mode
1.4.1.1 Full on Mode
In this mode, each device is running with the maximal speed. CPU clock is up to its maximum.
1.4.1.2 Doze Mode
In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling. This
can save battery power without loosing much computing capability.
The CPU power consumption and temperature is lower in this mode.
1.4.1.3 Standby Mode
For more power saving, it turns of the peripheral components. In this mode, the following is the status of each
device:
-- CPU: Stop grant
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-- LCD: backlight off
-- HDD: spin down
1.4.1.4 Suspend to DRAM
The most chipset of the system is entering power down mode for more power saving. In this mode, the following
is the status of each device:
ꢀ Suspend to DRAM
-- CPU: off
-- Intel 915GM: Partial off
-- VGA: Suspend
-- PCMCIA: Suspend
-- Audio: off
-- SDRAM: self refresh
ꢀ Suspend to HDD
-- All devices are stopped clock and power-down
-- System status is saved in HDD
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-- All system status will be restored when powered on again
1.4.2 Other Power Management Functions
Implanted H/W current limit and battery learning circuit to enhance protection of battery.
1.4.2.1 HDD & Video Access
System has the ability to monitor video and hard disk activity. User can enable monitoring function for video
and/or hard disk individually. When there is no video and/or hard disk activity, system will enter next PMU state
depending on the application. When the VGA activity monitoring is enabled, the performance of the system will
have some impact.
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1.5 Appendix 1: Intel ICH6-M GPIO Definitions (1)
Pin name
Current Define
Power plane
GPIO0
PCI_REQ6#
I
MAIN
GPIO1
GPIO2
MINIPCI_ACT#
PCI_INTE#
PCI_INTF#
PCI_INTG#
PCI_INTH#
PM_BMBUSY#
X
I
I
MAIN
MAIN
GPIO3
I
MAIN
GPIO4
I
MAIN
GPIO5
I
MAIN
GPIO6
I
MAIN
GPIO9
I
RESUME
RESUME
RESUME
MAIN
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO20
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
X
I
SMBALERT#
KBD_US/JP#
WAKE_UP#
X
I
I
I
RESUME
RESUME
RESUME
MAIN
I
X
I
SB_BY_ON#
SCI#
O
I
MAIN
STOP_PCI#
STOP_CPU#
WIRELESS_PD#
SPK_OFF
O
O
O
I/O
I/O
I
MAIN
MAIN
MAIN
RESUME
RESUME
MAIN
PANEL_ID0
X
I/O
RESUME
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1.5 Appendix 1: Intel ICH6-M GPIO Definitions (2)
Continue to previous page
Pin name
Current Define
Power plane
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO40
GPIO41
GPIO48
GPIO49
X
PANEL_ID1
PANEL_ID2
PANEL_ID3
PCLKRUN#
MB_ID0
I/O
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
I
I
I
I/O
I/O
I/O
I
MB_ID1
MXM_DETECT#
CRT_IN#
I
X
O
HPWRGD
OD O
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1.6 Appendix 2: W83L950D KBC Pins Definitions (1)
Port
P0
Pin
0-7
0-7
0-7
0
Function
Implement
KO[0..7]
P1
Scan matrix
KO[8..15]
P3
KI[0..7]
LPC enable
GPIO x1
H8_THRM#
H8_WAKE_UP#
BATT_G#
1
2
SMBUS1 or UART
3
BATT_R#
P2
P4
P5
4
EXTSMI#
5
CAP#
GPIO x4
6
NUM#
7
SCROLL#
0
H8_ENABKL
CHARGING
LEARING
Xcin/cout or PWM 2,3
GPIO x2 (INT1)
1
2
3
H8_SUSB
4
KBRST
A20
H8_HRCIN#
A20GATE
H8_SCI
5
6
GPIO x2
GPIO x1
7
H8_PWRON
SW_VDD3
H8_LIDSW#
BATT_DEAD#
H8_ADEN#
BATT_LED#
KBC_PWRON_VDD3S
BLADJ
0
1
2
GPIO x3 (INT20,30,40)
3
4
GPIO x2
5
6
D/A, PWM 2,3
7
H8_I_CTR
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1.6 Appendix 2: W83L950D KBC Pins Definitions (2)
Continue to previous page
Port
Pin
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Function
Implement
PWRBTN#
KBC_RI#
AC_ POWER#
BATT_V
P6
A/D (INT5-12)
BATT_T
H8_I_LIMIT
H8_PROCHOT#
+BC_CPUCORE
T_DATA
H8_RSMRST
ICH_PWRBTN
T_CLK
PS/2 port x3
SMBUS
P7
H8_PWRON_SUSB#
SUSC#
BAT_DATA
BAT_CLK
PCICLK_KBC
SERIRQ
LAD3
LAD2
P8
LPC interface
LAD1
LAD0
KBC_PCIRST#
LFRAME#
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1.7 Appendix 3: 8050QMA Product Spec (1)
Item
Description
Intel® Pentium® M Processor (Dothan) 90nm, 2M L2, 533 MHz FSB
Intel® Celeron® M processor, 90nm, 512K L2, 400 MHz FSB
- CPU Thermal ceiling: 27W
CPU
Intel 915PM + ICH6M
- Dual Channel Memory Support
- DDR2 400/533
Core logic
Expandable to 2048MB(P)
Inside 512KB Flash EPROM
Include System BIOS, VGA BIOS
System BIOS
ACPI2.0; 2.31 compliants
Boot from USB mass storage device
- 200-pin SO-DIMM DDR2 Memory Slot x2
- Support DDR2 400/533
Memory
- 0MB Memory onboard ; Expandable to 2.0GB(P)
- Type I MXM Interface (max 25W) with 8 cells Vram
- Priority at launch: NV44M + 32MB discrete Vram + Turbo Memory
VGA Controller
12.7mm Optical Drive
- Combo Drive
- DVD Dual
ROM Drive
- DVD Super Multi drive
One 2.5" 9.5 mm height HDD;
- 5400/7200 RPM Serial PATA HDD
- 40/60/80 GB Capacity
HDD
15.4" Wide WXGA TFTLCD
- Resolution: 1280 x 800
Display
- Key pitch: 19mm, Key travel: 3.0mm
- Windows Logo Key x 2
Keyboard
- W/z Hot Key Functions
- Intelligence Glide pad without scroll button
- 2 touch pad buttons
Touch Pad
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1.7 Appendix 3: 8050QMA Product Spec (2)
Continue to previous page
Item
Description
- AC97, support S/PDIF output
- 5.1 channel analog output
Audio/AV Function
Multi Card reader
-
2.1 channel system speaker. two full range speakers(1W*2 Front), one subwoofer(3W)
- Build in microphone
- 4 in 1 Card Reader (SD/MMC/MS/MS Pro)
- 3 LEDs for Power/Battery status (AC In status/Battery status/Reserved Power
- System Status) (on inverter board)
- 2 LEDs for HDD Access, ODD Access
- 3 LEDs for Number lock, Caps lock, Scroll lock
- 1 LED for Wireless on/off
Indicator on board
PC CARD
- 1 LED for Card Reader Accessing
1x Type II PCMCIA Interface without Zoom Video
Support Support 3.3V, 5V device
I/O:
USB (support USB 1.1 and USB 2.0) port x 4
Reserve 1 connector on board for USB 2.0 Device
RJ-11 port x 1 (4Pin)
RJ-45 port x 1
DC input (2.5 * 5.5 * 11mm) x 1
IEEE1394 x 1(4 pin).
Type III B MiniPCI x 1 (For wireless LAN)
I/O Ports
Audio(Normal /5.1Analog output):
Line - out/SPDIF x 1 (5.1 mode: Front 2 channels)
Mic - in x 1 (5.1 mode: LBF/Middle channels)
Line - in x 1 (5.1 mode: Rear 2 channels)
Video
DVI- I x 1
TV-Out x 1 (7 Pin S-Video connector NTSC/PAL)
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1.7 Appendix 3: 8050QMA Product Spec (3)
Continue to previous page
Item
Description
PCI 10/100 LAN MDC 56K, V.90 Modem
802.11g wireless LAN (Mini PCI optional) with built-in Antenna
Communication
6 cell Li-ion (2400mAH/3.7V) Battery pack
Battery Life > 3HRs
Power Supply
AC adapter
Dimensions
Weight
Universal AC adapter 2 Pin 2.5*5.5*11 65W 19V DC output, Input: 100-240V, 50/60Hz AC
35mm x 250mm x 25 ~ 38mm(Max)(P)
2.8KG (TBD)
Manuals
EN, GR , Pan-EU
AC Adapter,
Accessories
Power Cord,
RJ-11 cable, (Option)
SAFETY LOCK
Architecture
Security Lock hole (Kensington Lock)
- Support PC2001 specifications;
- WHQL-certified for Windows XP Professional/Home edition SP2
Europe
USA
Sales Region
Agency
FCC, CE, CB,
CPU
Memory
Wireless Card
Retailer Option Summary HDD
Battery
ODD
MDC
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2. System View and Disassembly
2.1 System View
2.1.1 Front View
ꢄ
1394 Port
ꢀ
ꢁ
ꢂ
ꢄ
ꢃ
ꢅ
Line Out Connector
Line In Connector
MIC In Connector
MS/SD/MMC Card Slot
Top Cover Latch
ꢁ
ꢀ
ꢂ
ꢃ
ꢀ
2.1.2 Left-side View
DVI Port
ꢀ
ꢁ
ꢂ
ꢄ
ꢃ
ꢅ
ꢆ
USB Ports *2
S-Video Port
Ventilation Openings
RJ-11 Connector
RJ-45 Connector
PCMCIA Card Socket
ꢆ
ꢀ
ꢂ
ꢁ
ꢃ
ꢅ
ꢄ
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2.1.3 Right-side View
CD/DVD-ROM Drive
Kensington Lock
ꢀ
ꢁ
ꢀ
ꢁ
2.1.4 Rear View
Lock
ꢀ
ꢁ
ꢂ
AC Power Connector
USB Ports *2
ꢀ
ꢂ
ꢁ
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2.1.5 Bottom View
ꢂ
ꢁ
Hard Disk Drive
CPU
ꢀ
ꢁ
ꢂ
ꢄ
Battery Park
Stereo Speaker Set
ꢁ
ꢀ
2.1.6 Top-open View
LCD Screen
ꢀ
ꢁ
ꢂ
ꢄ
ꢃ
ꢅ
ꢆ
ꢇ
ꢀ
ꢁ
Power Button
Stereo Speaker Set
Keyboard
ꢀ
ꢅ
ꢇ
ꢆ
Internal MIC In
Device LED Indicators
Touch Pad
ꢁ
ꢂ
ꢂ
ꢃ
AC Power Indicator
Battery Charge Indicator
Battery Power Indicator
ꢄ
ꢄ
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2.2 Tools Introduction
1. Minus screw driver with bit size 2mm for notebook assembly & disassembly.
2mm
2mm
2. Auto screw driver for notebook assembly & disassembly.
Bit Size
#0
Screw Size
1. M2.0
Tooling
Tor.
Bit Size
#0
Auto-Screw driver
2.0-2.5 kg/cm2
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2.3 System Disassembly
The section discusses at length each major component for disassembly/reassembly and show corresponding
illustrations.Use the chart below to determine the disassembly sequence for removing components from the
notebook.
NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the
notebook is not turned on or connected to AC power.
2.3.1 Battery Pack
2.3.2 Keyboard
Modular Components
2.3.3 CPU
2.3.4 HDD Module
2.3.5 CD/DVD-ROM Drive
2.3.6 DDR-SDRAM
2.3.7 Modem Card
NOTEBOOK
2.3.8 LCD Assembly
2.3.9 LCD Panel
LCD Assembly Components
Base Unit Components
2.3.10 Inverter Board
2.3.11 System Board
2.3.12 Touch Pad
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2.3.1 Battery Pack
Disassembly
1. Carefully put the notebook upside down.
2. Slide the two release lever outwards to the “unlock” position (ꢀ), while take the battery pack out of the
compartment (ꢁ). (Figure 2-1)
ꢁ
ꢀ
ꢀ
Figure 2-1 Remove the battery pack
Reassembly
1. Replace the battery pack into the compartment. The battery pack should be correctly connected when you hear a
clicking sound.
2. Slide the release lever to the “lock” ( ) position.
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2.3.2 Keyboard
Disassembly
1. Remove the battery pack. (Refer to section 2.3.1 Disassembly)
2. Open the top cover.
3. Loosen the five latches locking the keyboard. (Figure 2-2)
Figure 2-2 Loose the five latches
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4. Slightly lift up the keyboard and disconnect the cable from the system board, then separate the keyboard.
(Figure 2-3)
Figure 2-3 Free the keyboard
Reassembly
1. Reconnect the keyboard cable and fit the keyboard back into place.
2. Replace the keyboard fasten the five latches.
3. Replace the battery pack. (Refer to section 2.3.1 Reassembly)
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2.3.3 CPU
Disassembly
1. Remove the battery pack. (Refer to section 2.3.1 Disassembly)
2. Remove the seven screws fastening the CPU cover. (Figure 2-4)
3. Remove the four spring screws and two screws that secure the heatsink upon the CPU and disconnect the fan’s
power cord from the system board. (Figure 2-5)
Figure 2-4 Remove the seven screws
Figure 2-5 Free the heatsink
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4. To remove the existing CPU, loosen the screw by a flat screwdriver, upraise the CPU socket to unlock the CPU.
(Figure 2-6)
Figure 2-6 Remove the CPU
Reassembly
1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU pins
into the holes. Tighten the screw by a flat screwdriver to locking the CPU.
2. Connect the fan’s power cord to the system board, fit the heatsink upon the CPU, then secure with four spring
screws and two screws.
3. Replace the CPU cover and secure with seven screws.
4. Replace the battery pack. (Refer to section 2.3.1 Reassembly)
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2.3.4 HDD Module
Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.3.1 Disassembly)
2. Remove the two screws fastening the HDD compartment cover. (Figure 2-7)
3. Remove the one screw and slide the HDD module out of the compartment. (Figure 2-8)
Figure 2-7 Remove the HDD compartment
cover
Figure 2-8 Remove HDD module
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4. Remove the four screws to separate the hard disk drive from the bracket, remove the hard disk drive. (Figure 2-9)
Figure 2-9 Remove hard disk drive
Reassembly
1. Attach the bracket to hard disk drive and secure with four screws.
2. Slide the HDD module into the compartment and secure with one screw.
3. Place the HDD compartment cover and secure with two screws.
4. Replace the battery pack. (Refer to section 2.3.1 Reassembly)
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2.3.5 CD/DVD-ROM Drive
Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (See section 2.3.1 Disassembly)
2. Remove the one screw fastening the CD/DVD-ROM drive. (Figure 2-10)
3. Insert a small rod, such as a straightened paper clip, into CD/DVD-ROM drive’s manual eject hole (ꢀ) and
push firmly to release the tray. Then gently pull out the CD/DVD-ROM drive by holding the tray that pops
out (ꢁ).
ꢀ
ꢁ
Figure 2-10 Remove the CD/DVD-ROM drive
Reassembly
1. Push the CD/DVD-ROM drive into the compartment and secure with one screw.
2. Replace the battery pack. (See section 2.3.1 Reassembly)
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2.3.6 DDR-SDRAM
Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (See section 2.3.1 Disassembly)
2. Remove the seven screws fastening the CPU cover. (Refer to the step 2 of section 2.3.3 Disassembly)
Figure 2-11 Remove the SO-DIMM
3. Pull the retaining clips outwards (ꢀ) and remove the SO-DIMM (ꢁ). (Figure 2-11)
Reassembly
1. To install the DDR, match the DDR's notched part with the socket's projected part and firmly insert the
SO-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the DDR into
position.
2. Replace the CPU cover and secure with seven screws. (Refer to the step 3 of section 2.3.3 Reassembly)
3. Replace the battery pack. (See section 2.3.1 Reassembly)
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2.3.7 Modem Card
Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.3.1 Disassembly)
2. Remove seven screws fastening CPU cover. (Refer to step 2 of section 2.3.3 Disassembly)
3. Remove two screws fastening the modem card. (Figure 2-12)
4. Lift up the modem card and disconnect the cord. (Figure 2-13)
Figure 2-12 Remove two screws
Figure 2-13 Disconnect the cord
Reassembly
1. Reconnect the cord and fit the modem card.
2. Fasten the modem card by two screws.
3. Replace the CPU cover by seven screws. (Refer to step 3 of section 2.3.3 Reassembly).
4. Replace the battery pack. (Refer to section 2.3.1 Reassembly)
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2.3.8 LCD ASSY
Disassembly
1. Remove the battery pack, keyboard, CPU, hard disk drive, CD/DVD-ROM drive, DDR and modem card.
(See sections 2.3.1, 2.3.2, 2.3.3, 2.3.4, 2.3.5, 2.3.6 and 2.3.7 Disassembly)
2. Remove the eighteen screws fastening the housing and separate the antenna from the Mini PCI compartment.
(Figure 2-14)
3. Disconnect the touch pad’s cable from the system board and remove the two screws, then free the top cover.
(Figure 2-15)
Figure 2-14 Remove the eighteen screws
and separate the antenna
Figure 2-15 Free the top cover
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4. Remove the seven screws and lift the top shielding up, then free the top shielding. (Figure 2-16)
5. Separate the antenna and disconnect the two cables from the system board. (Figure 2-17)
Figure 2-16 Remove the seven screws
Figure 2-17 Disconnect the two cables
and separate the antenna
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6. Remove the two screws and lift the two hinge covers up, then free the two hinge covers. (Figure 2-18)
7. Remove the four screws, then free the LCD assembly. (Figure 2-19)
Figure 2-18 Free the two hinge covers
Figure 2-19 Free the LCD assembly
Reassembly
1. Attach the LCD assembly to the base unit and secure with four screws.
2. Replace the antenna back into Mini PCI compartment.
3. Reconnect the two cables to the system board.
4. Replace the two hinge covers and secure with two screws.
5. Replace the top shielding and secure with seven screws.
6. Replace the top cover and secure with two screws, then reconnect the touch pad’s cable into the system board.
7. Secure with eighteen screws fasten the housing.
8. Replace the modem card, DDR, CD/DVD-ROM drive, hard disk drive, CPU, keyboard and battery pack.
(Refer to previous section reassembly)
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2.3.9 LCD Panel
Disassembly
1. Remove the battery, keyboard, CPU, hard disk drive, CD/DVD-ROM drive, DDR, modem card and LCD
assembly. (Refer to section 2.3.1, 2.3.2, 2.3.3, 2.3.4, 2.3.5, 2.3.6, 2.3.7 and 2.3.8 Disassembly)
2. Remove the two rubber pads and two screws on the corners of the panel. (Figure 2-20)
3. Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out. Repeat the process
until the cover is completely separated from the housing.
4. Remove the ten screws and disconnect the cable. (Figure 2-21)
Figure 2-20 Remove LCD cover
Figure 2-21 Remove the ten screws and
disconnect the cable
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5. Remove the four screws that secure the LCD brackets. (Figure 2-22)
6. Disconnect the cable to free the LCD panel. (Figure 2-23)
Figure 2-22 Remove the four screws
Figure 2-23 Free the LCD panel
Reassembly
1. Replace the cable to the LCD panel.
2. Attach the LCD panel’s brackets back to LCD panel and secure with four screws.
3. Replace the LCD panel into LCD housing and secure with ten screws.
4. Reconnect one cable to inverter board.
5. Fit the LCD cover and secure with two screws and rubber pads.
6. Replace the LCD assembly, modem card, DDR, CD/DVD-ROM drive, hard disk drive, CPU, keyboard and
battery pack. (Refer to previous section reassembly)
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2.3.10 Inverter Board
Disassembly
1. Remove the battery, keyboard, CPU, hard disk drive, CD/DVD-ROM drive, DDR, modem card, LCD
assembly and LCD panel. (Refer to section 2.3.1, 2.3.2, 2.3.3, 2.3.4, 2.3.5, 2.3.6, 2.3.7, 2.3.8 and 2.3.9
Disassembly)
2. Remove the one screw fastening the inverter board, then free the inverter board. (Figure 2-24)
Figure 2-24 Free the inverter board
Reassembly
1. Fit the inverter board back into place and secure with one screw.
2. Replace the LCD panel, LCD assembly, modem card, DDR, CD/DVD-ROM drive, hard disk drive, CPU
keyboard and battery pack. (Refer to previous section reassembly)
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2.3.11 System Board
Disassembly
1. Remove the battery, keyboard, CPU, hard disk drive, CD/DVD-ROM drive, DDR, modem card and LCD
assembly. (Refer to sections 2.3.1, 2.3.2, 2.3.3, 2.3.4, 2.3.5, 2.3.6, 2.3.7 and 2.3.8 Disassembly)
2. Remove the two screws fastening the housing. (Figure 2-25)
3. Remove the two screws fastening the housing. (Figure 2-26)
Figure 2-25 Remove the two screws
Figure 2-26 Remove the two screws
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4. Disconnect the three speakers’ cables from the system board and separate the (R&L) rear covers. (Figure 2-27)
5. Remove the four screws and lift the system board from the housing. (Figure 2-28)
Figure 2-27 Disconnect the cables and
separate the rear covers
Figure 2-28 Remove the four screws
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6. Remove the two screws and separate the I/O bracket from the system board, then free the system board.
(Figure 2-29)
Figure 2-29 Free the system board
Reassembly
1. Fit the system board into the I/O bracket and secure with two screws.
2. Replace the system board into the housing and secure with four screws.
3. Reconnect the three speakers’ cables into the system board and replace the (R&L) rear covers.
4. Secure with four screws fasten the housing.
5. Replace the LCD assembly, modem card, DDR, CD/DVD-ROM drive, hard disk drive, CPU, keyboard and
battery pack. (Refer to the section 2.3.8, 2.3.7, 2.3.6, 2.3.5, 2.3.4, 2.3.3, 2.3.2 and 2.3.1 Reassembly)
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2.3.12 Touch Pad
Disassembly
1. Remove the battery pack, keyboard, CPU, hard disk drive, CD/DVD-ROM drive, DDR and modem card.
(See sections 2.3.1, 2.3.2, 2.3.3, 2.3.4, 2.3.5, 2.3.6 and 2.3.7 Disassembly)
2. Remove the top cover. (Refer to the steps 1-3 of 2.3.8 section Disassembly)
3. Remove the four screws and lift the shielding, then free the touch pad. (Figure 2-30)
Figure 2-30 Free the touch pad
Reassembly
1. Replace the touch pad, then fit the shielding and secure with two screws.
2. Replace the top cover. (Refer to the step 6 of section 2.3.8 Disassembly)
3. Replace the modem card, DDR, CD/DVD-ROM drive, hard disk drive, CPU, keyboard and battery pack.
(See sections 2.3.8, 2.3.7, 2.3.6, 2.3.5, 2.3.4, 2.3.3, 2.3.2 and 2.3.1 Reassembly)
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3. Definition & Location of Connectors / Switches
3.1 Mother Board (Side A)
ꢇ J1 : Inverter Board Connector
J3
J2
SW2
ꢇ J2 : LCD Panel Connector
ꢇ J3 : Internal Left Speaker Connector
ꢇ J4 : Touch-pad Module Connector
ꢇ J5 : Internal Key-board Connector
ꢇ J7 : Internal Right Speaker Connector
ꢇ J8 : PCMCIA Card Connector
J1
J8
SW3
J5
ꢇ SW2 : Power Button
J4
ꢇ SW3 : Left Button Switch of Touch-pad
ꢇ SW4 : Right Button Switch of Touch-pad
J7
SW4
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3. Definition & Location of Connectors / Switches
3.2 Mother Board (Side B)
ꢀ PJ701 : AC Adaptor Connector
J709
J503
ꢇ J701&J706 : USB Port Connector
ꢇ J702 : DVI Connector
J702 J706 J704
J507
J504
J701
J716
ꢇ J703 : Battery Connector
ꢇ J704 : S-video Connector
PJ701
ꢇ J709 : RJ45 & RJ11 Connector
ꢇ J710 : CD-ROM IDE Connector
ꢇ J713&J714 : DDR SO-DIMM Module Socket
ꢇ J715 : Hard Disk Driver Connector
ꢇ J716 : Mini-PCI Connector
ꢇ J723 : MXM_Connector
J502
J719
J509
J721
J720
ꢇ J501 : Internal Subwoofer Speaker
ꢇ J502 : FAN Connector
J703
J508
J710
J715
J501
ꢇ J504 : FAN Connector
ꢇ J508 : MS/SD/MMC Connector
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4. Definition & Location of Major Components
4.1 Mother Board (Side A)
ꢇ PU2 : +3VS/+5VS Voltage Generator
ꢇ PU3 : Charging Voltage Controller
ꢇ PU5 : CPU_Core Voltage Generator
ꢇ PU6 : +1.5VS/+1.05VS Voltage Generator
ꢇ PU12 : +1.8V_P/0.9VS_P Voltage Generate
ꢇ U7 : CLOCK SYNTHERIZER
PU2
U14
U7
ꢇ U13 : WINBOND KBC Controller
ꢇ U14 : SYSTEM BIOS
U19
PU6
PU3
U18
ꢇ U18 : SUBWOOFER AMP Controller
ꢇ U19 : AUDIO AMPLIFIER
PU5
PU12
U13
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4. Definition & Location of Major Components
4.2 Mother Board (Side B)
ꢀ U709 : Intel ICH6-M South Bridge
U717
U722
ꢀ U710 : Intel 915PM North Bridge
U709
ꢀ U711 : Intel Dothan CPU
ꢀ U717 : LAN-RTL8100CL Controller
ꢀ U722 : IEEE1394 Controller
ꢀ U724 : Serial ATA Bridge 88SA8040
ꢇ U517 : Audio CODEC(ALC655)
U710
U517
U711
U724
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5. Pin Descriptions of Major Components
5.1 Intel 915PM North Bridge(1)
Host Interface Signals
Host Interface Signals (Continued)
Signal Name
Type
Description
Signal Name
Type
Description
HADS#
I/O
Host Address Strobe:
HDRDY#
I/O
Host Data Ready:
AGTL+ The system bus owner asserts HADS# to indicate the first of two
cycles of a request phase. The GMCH can also assert this signal for
snoop cycles and interrupt messages.
AGTL+ Asserted for each cycle that data is transferred.
I/O
Host Address Bus:
AGTL+ HA[31:3]# connects to the CPU address bus. During processor cycles
HA[31:3]#
HBNR#
HBPRI#
I/O
Host Block Next Request:
2X
the HA[31:3]# are inputs. The GMCH drives HA[31:3]# during
snoop cycles on behalf of DMI.
AGTL+ Used to block the current request bus owner from issuing a new
request. This signal is used to dynamically control the CPU bus
pipeline depth.
HA[31:3]# are transferred at 2x rate.
Note that the address is inverted on the CPU bus.
O
Host Bus Priority Request:
HADSTB[1:0]#
I/O
Host Address Strobe:
AGTL+ The GMCH is the only Priority Agent on the system bus. It asserts
this signal to obtain the ownership of the address bus. This signal has
priority over symmetric bus requests and will cause the current
symmetric owner to stop issuing new transactions unless the
HLOCK# signal was asserted.
AGTL+ HA[31:3]# connects to the CPU address bus. During CPU cycles, the
2X
source synchronous strobes are used to transfer HA[31:3]# and
HREQ[4:0]# at the 2x transfer rate.
Strobe
Address Bits
HADSTB[0]#
HADSTB[1]#
Host Data:
HA[16:3]#, HREQ[4:0]#
HA[31:17]#
HBREQ0#
I/O
Host Bus Request 0#:
AGTL+ The GMCH pulls the processor bus HBREQ0# signal low during
HCPURST#. The signal is sampled by the processor on the
active-to-inactive transition of HCPURST#.
HD[63:0]#
I/O
AGTL+ These signals are connected to the CPU data bus. HD[63:0]# are
4X
transferred at 4x rate.
HBREQ0# should be tri-stated after the hold time requirement has
been satisfied.
Note that the data signals are inverted on the CPU bus depending on
the HDINV[3:0]# signals.
HCPURST#
O
Host CPU Reset:
HDSTBP[3:0]#
HDSTBN[3:0]#
I/O
Host Differential Host Data Strobes:
AGTL+ The CPURST# pin is an output from the GMCH. The GMCH asserts
HCPURST# while RSTIN# is asserted and for approximately 1 ms
after RSTIN# is deasserted. HCPURST# allows the processor to
begin execution in a known state.
AGTL+ The differential source synchronous strobes are used to transfer
4X
HD[63:0]# and HDINV[3:0]# at the 4x transfer rate.
Strobe
Data Bits
HDSTBN[3]# HD[63:48]#, HDINV[3]#
HDSTBP[3]#,
HDSTBP[2]#,
HDSTBP[1]#,
HDSTBP[0]#,
Host Hit:
HDBSY#
I/O
Host Data Bus Busy:
HDSTBN[2]# HD[47:32]#, HDINV[2]#
HDSTBN[1]# HD[31:16]#, HDINV[1]#
HDSTBN[0]# HD[15:00]#, HDINV[0]#
AGTL+ Used by the data bus owner to hold the data bus for transfers
requiring more than one cycle.
HDEFER#
HDINV[3:0]#
O
Host Defer:
HHIT#
I/O
AGTL+ Signals that the GMCH will terminate the transaction currently being
snooped with either a deferred response or with a retry response.
AGTL+ Indicates that a caching agent holds an unmodified version of the
requested line.
I/O
Host Dynamic Bus Inversion:
Also, driven in conjunction with HITM# by the target to extend the
snoop window.
AGTL+ Driven along with the HFD[63:0]# signals. Indicates if the associated
signals are inverted or not. HDINVF[3:0]# are asserted such that the
number of data bits driven electrically low (low voltage) within the
corresponding 16-bit group never exceeds 8.
HHITM#
I/O
Host Hit Modified:
AGTL+ Indicates that a caching agent holds a modified version of the
requested line and that this agent assumes responsibility for providing
the line.
HDINV#
Data Bits
HDINV[3]#
HDINV[2]#
HDINV[1]#
HDINV[0]#
HD[63:48]#
HD[47:32]#
HD[31:16]#
HD[15:0]#
Also, driven in conjunction with HIT# to extend the snoop window.
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5.1 Intel 915PM North Bridge(2)
Host Interface Signals (Continued)
Host Interface Reference and Compensation
Signal Name
Type
Description
Signal Name
Type
Description
HLOCK#
I
Host Lock:
HVREF
I
Host Reference Voltage:
AGTL+ All CPU bus cycles sampled with the assertion of HLOCK# and
HADS#, until the negation of HLOCK# must be atomic, i.e. PCI
Express graphics access to System Memory is allowed when
HLOCK# is asserted by the CPU.
A
Reference voltage input for the Data, Address, and Common clock
signals of the Host AGTL+ interface.
Host X RCOMP:
Used to calibrate the Host AGTL+ I/O buffers.
This signal is powered by the Host Interface termination rail (VCCP).
Host X SCOMP:
Slew Rate Compensation for the Host Interface
Host X Voltage Swing:
These signals provide reference voltages used by the HXRCOMP
circuits.
Host Y RCOMP:
Used to calibrate the Host AGTL+ I/O buffers.
Host Y SCOMP:
Slew Rate Compensation for the Host Interface
Host Y Voltage Swing:
These signals provide reference voltages used by the HYRCOMP
HXRCOMP
I/O
A
HREQ[4:0]#
I/O
Host Request Command:
AGTL+ Defines the attributes of the request. HREQ[4:0]# are transferred at
HXSCOMP
HXSWING
I/O
A
I
2X
2x rate.
Asserted by the requesting agent during both halves of the Request
Phase. In the first half the signals define the transaction type to a level
of detail that is sufficient to begin a snoop request. In the second half
the signals carry additional information to define the complete
transaction type.
A
HYRCOMP
HYSCOMP
HYSWING
I/O
A
I/O
A
I
A
HTRDY#
O
Host Target Ready:
AGTL+ Indicates that the target of the processor transaction is able to enter
the data transfer phase.
HRS[2:0]#
O
Host Response Status:
AGTL+ Indicates the type of response according to the following the table:
circuitry.
HRS[2:0]#
000
Response type
Idle state
001
Retry response
010
Deferred response
011
100
101
Reserved (not driven by GMCH)
Hard Failure (not driven by GMCH)
No data response
DMI
110
111
Implicit Write back
Normal data response
Signal Name
Type
Description
DMI_RXP[1:0]
DMI_RXN[1:0]
DMI_TXP[1:0]
DMI_TXN[1:0]
I
DMI input from ICH6-M:
Direct Media Interface receive differential pair
DMI output to ICH6-M:
Direct Media Interface transmit differential pair
HDPWR#
O
Host Data Power:
PCIE
O
PCIE
AGTL+ Used by GMCH to indicate that a data return cycle is pending within
2 HCLK cycles or more. CPU use’s this signal during a read-cycle to
activate the data input buffers in preparation for HDRDY# and the
related data.
DMI x2 is supported for Intel 915GMS chipset
HCPUSLP#
O
Host CPU Sleep:
CMOS When asserted in the Stop-Grant state, causes the processor to enter
the Sleep state. During Sleep state, the processor stops providing
internal clock signals to all units, leaving only the Phase-Locked
Loop (PLL) still operating. Processors in this state will not recognize
snoops or interrupts.
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5.1 Intel 915PM North Bridge(3)
DDR / DDR2 SDRAM Channel A Interface
DDR / DDR2 SDRAM Channel A Interface (Continued)
Signal Name
Type
Description
Signal Name
Type
Description
SA_DQ[63:0]
I/O
Data Bus:
SA_RAS#
O
RAS Control signal:
SSTL1.8/2 DDR / DDR2 Channel A data signal interface to the SDRAM data
SSTL1.8/2 Used with SA_CAS# and SA_WE# (along with SM_CS#) to define
the SDRAM commands.
2x
bus.
Single channel mode: Route to SO-DIMM 0 & SO-DIMM1
Dual channel mode: Route to SO-DIMM A
Data Mask:
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
CAS Control signal:
SA_DM[7:0]
SA_DQS[7:0]
I/O
SA_CAS#
O
SSTL1.8/2 These signals are used to mask individual bytes of data in the case of
SSTL1.8/2 Used with SA_RAS# and SA_WE# (along with SM_CS#) to define
the SDRAM commands.
2x
a partial write, and to interrupt burst writes.
When activated during writes, the corresponding data groups in the
SDRAM are masked. There is one SA_DM[7:0] for every data byte
lane.
Single channel mode: Route to SO-DIMM 0 & SO-DIMM1
Dual channel mode: Route to SO-DIMM A
Data Strobes:
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
Write Enable Control signal:
SA_WE#
O
SSTL1.8/2 Used with SA_RAS# and SA_CAS# (along with SM_CS#) to define
the SDRAM commands.
I/O
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SSTL1.8 DDR: The rising and falling edges of SA_DQS[7:0] are used for
2x
capturing data during read and write transactions.
DDR2: SA_DQS[7:0] and its complement signal group make up a
differential strobe pair. The data is captured at the crossing point of
SA_DQS[7:0] and its SA_DQS[7:0]# during read and write
transactions.
SA_RCVENIN#
O
Clock Input:
SSTL1.8/2 Used to emulate source-synch clocking for reads. Connects internally
to SA_RCVENOUT#.
Leave as No Connect.
Clock Output:
SA_RCVENOUT
#
O
Single channel mode: Route to SO-DIMM 0 & SO-DIMM1
Dual channel mode: Route to SO-DIMM A
SSTL1.8/2 Used to emulate source-synch clocking for reads. Connects internally
to SA_RCVENIN#.
SA_DQS[7:0]#
SA_MA[13:0]
I/O
Data Strobe Complements
Leave as No Connect.
SSTL1.8 DDR1: No Connect. These signals are not used for DDR devices
2x
DDR2 : These are the complementary DDR2 strobe signals.
Single channel mode: Route to SO-DIMM 0 & SO-DIMM1
Dual channel mode: Route to SO-DIMM A
Memory Address:
PCI Express Based Graphics Interface Signals
O
Signal Name
Type
Description
SSTL1.8/2 These signals are used to provide the multiplexed row and column
address to the SDRAM.
EXP_RXN[15:0]
EXP_RXP[15:0]
EXP_TXN[15:0]
EXP_TXP[15:0]
EXP_ICOMPO
I
PCI Express Receive Differential Pair
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
Note: SA_MA13 is for support of 1 Gb devices.
PCIE
O
PCIE
I
A
I
PCI Express Transmit Differential Pair
SA_BS[2:0]
O
Bank Select:
PCI Express Output Current and Resistance Compensation
PCI Express Input Current Compensation
SSTL1.8/2 These signals define which banks are selected within each SDRAM
rank.
EXP_COMPI
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
Note: SA_BS2 is for support for DDR2 only for 8 bank devices.
A
PCI Express Based Graphics is supported for Intel 915GM and Intel 915PM chipsets.
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5.1 Intel 915PM North Bridge(4)
DDR / DDR2 SDRAM Channel B Interface
DDR / DDR2 SDRAM Channel B Interface (Continued)
Signal Name
Type
Description
Signal Name
Type
Description
SB_DQ[63:0]
I/O
Data Lines:
SB_RAS#
O
RAS Control signal:
SSTL1.8/2 DDR / DDR2 Channel B data signal interface to the SDRAM data
SSTL1.8/2 Used with SB_CAS# and SB_WE# (along with SM_CS#) to define
the SDRAM commands.
2x
bus.
Single Channel mode: No connect.
Dual channel mode: Route to SO-DIMM B
NOTE: Signals do not exist in Intel 915GMS.
Data Mask:
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
CAS Control signal:
SB_CAS#
O
SB_DM[7:0]
SB_DQS[7:0]
O
SSTL1.8/2 Used with SB_RAS# and SB_WE# (along with SM_CS#) to define
the SDRAM commands.
SSTL1.8/2 When activated during writes, the corresponding data groups in the
2x
SDRAM are masked. There is one SB_DM[7:0] for every data byte
lane. These signals are used to mask individual bytes of data in the
case of a partial write, and to interrupt burst writes.
Single Channel mode: No connect.
Dual channel mode: Route to SO-DIMM B
NOTE: Signals do not exist in Intel 915GMS.
Data Strobes:
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
Write Enable Control signal:
SB_WE#
O
SSTL1.8/2 Used with SB_RAS# and SB_CAS# (along with SM_CS#) to define
the SDRAM commands.
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
I/O
SSTL1.8/2 DDR: The rising and falling edges of SB_DQS[7:0] are used for
SB_RCVENIN#
I
Clock Input:
2x
capturing data during read and write transactions.
DDR2: SB_DQS[7:0] and its complement signal group make up a
differential strobe pair. The data is captured at the crossing point of
SB_DQS[7:0] and its SB_DQS[7:0]# during read and write
transactions.
SSTL1.8/2 Used to emulate source-synch clocking for reads.
Leave as No Connect.
NOTE: Signals do not exist in Intel 915GMS.
SB_RCVENOUT
#
O
Clock Output:
SSTL1.8/2 Used to emulate source-synch clocking for reads.
Leave as No Connect.
Single Channel mode: No connect.
Dual channel mode: Route to SO-DIMM B
NOTE: Signals do not exist in Intel 915GMS.
Data Strobe Complements (DDR2 only):
NOTE: Signals do not exist in Intel 915GMS.
SB_DQS[7:0]#
SB_MA[13:0]
SB_BS[2:0]
I/O
SSTL1.8 DDR1: No Connect. These signals are not used for DDR devices
2x
DDR2 : These are the complementary DDR2 strobe signals.
Single Channel mode: No connect.
Dual channel mode: Route to SO-DIMM B
NOTE: Signals do not exist in Intel 915GMS.
Memory Address:
DMI
Signal Name
Type
Description
O
DMI_RXP[3:0]
DMI_RXN[3:0]
DMI_TXP[3:0]
DMI_TXN[3:0]
I
DMI input from ICH6-M:
Direct Media Interface receive differential pair
DMI output to ICH6-M:
Direct Media Interface transmit differential pair
SSTL1.8/2 These signals are used to provide the multiplexed row and column
address to the SDRAM.
PCIE
O
PCIE
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
NOTE: SB_MA13 is for support of 1 Gb devices.
DMI x2 or x4 is supported for Intel 915GM, Intel 915PM and Intel 910GML chipsets.
O
Bank Select:
SSTL1.8/2 These signals define which banks are selected within each
SDRAM rank.
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
NOTE: SB_BS2 is for DDR2 support only.
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5.1 Intel 915PM North Bridge(5)
DDR / DDR2 Common Signals
DDR / DDR2 Common Signals (Continued)
Signal Name
Type
Description
Signal Name
Type
Description
SM_ODT[3:0]
O
On Die Termination: Active Termination Control. (DDR2 only)
SM_CK[1:0],
SM_CK[4:3]
O
SDRAM Differential Clock:
SSTL1.8/2 SM_ODT[1:0]:
Single channel mode: Route to SO-DIMM 0
SSTL1.8/2 The crossing of the positive edge of SM_CKx and the negative edge
of its complement SM_CKx# are used to sample the command and
control signals on the SDRAM.
Dual channel mode: Route to SO-DIMM A
Signal Description
SM_CK[0:1] and its complement SM_CK[1:0]# signal make a
differential clock pair output.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SM_CK[4:3] and its complement SM_CK[4:3]# signal make a
differential clock pair output.
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
The crossing of the positive edge of SM_CKx and the negative edge
of its
complement SM_CKx# are used to sample the command and control
SM_CK[0:1] and its complement SM_CK[1:0]# signal make a
differential
SM_CK[4:3] and its complement SM_CK[4:3]# signal make a
differential
NOTE: SM_CK2 and SM_CK5 are reserved and not supported.
These are the complementary Differential DDR2 Clock signals.
NOTE: SM_CK2# and SM_CK5# are reserved and not supported.
These signals select particular SDRAM components during the active
To place all SDRAM ranks into and out of self-refresh during STR.
On Die Termination: Active Termination Control. (DDR2 only)
SM_ODT[3:2]:
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
DDR: Leave as no connects. Not used for DDR devices.
DDR2: On-die termination for DDR2 devices.
NOTE: SM_CK2 and SM_CK5 are reserved and not supported.
SDRAM Inverted Differential Clock:
SSTL1.8/2 These are the complementary Differential DDR2 Clock signals.
NOTE: SM_CK2# and SM_CK5# are reserved and not supported.
Chip Select: (1 per Rank):
SSTL1.8/2 These signals select particular SDRAM components during the active
state. There is one Chip Select for each SDRAM rank
SM_CS[1:0]# :
SM_CK[1:0]#,
SM_CK[4:3]#
O
SM_CS[3:0]#
O
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SM_CS[3:2]# :
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
SM_CKE[3:0]
O
Clock Enable: (1 per Rank):
SSTL1.8/2 SM_CKE[3:0] is used:
.To initialize the SDRAMs during power-up
.To power-down SDRAM ranks
. To place all SDRAM ranks into and out of self-refresh during STR.
SM_CKE[1:0]:
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SM_CKE[3:2]:
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
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5.1 Intel 915PM North Bridge(6)
Analog TV-out Signals
CRT DAC Signals
Signal Name
Type
Description
Signal Name
Type
Description
RED
O
A
RED Analog Video Output:
This signal is a CRT Analog video output from the internal color
palette DAC.
TVDAC_A
O
A
TVDAC Channel A Output:
TVDAC_A supports the following:
Composite: CVBS signal
Component: Chrominance (Pb) analog signal
TVDAC Channel B Output:
TVDAC_B supports the following:
S-Video: Luminance analog signal
Component: Luminance (Y) analog signal
TVDAC Channel C Output:
TVDAC_C supports the following:
S-Video: Chrominance analog signal
Component: Chrominance (Pr) analog signal
Current Return for TVDAC Channel A:
Connect to ground on board
RED#
O
A
RED# Analog Output:
This signal is an analog video output from the internal color palette
DAC. This signal is used to provide noise immunity.
GREEN Analog Video Output:
This signal is a CRT Analog video output from the internal color
palette DAC.
TVDAC_B
TVDAC_C
O
A
GREEN
GREEN#
BLUE
O
A
O
A
O
A
GREEN# Analog Output:
This signal is an analog video output from the internal color palette
DAC. This signal is used to provide noise immunity.
BLUE Analog Video Output:
This signal is a CRT Analog video output from the internal color
palette DAC.
TV_IRTNA
TV_IRTNB
TV_IRTNC
TV_REFSET
O
A
O
A
O
A
O
A
O
A
Current Return for TVDAC Channel B:
Connect to ground on board
Current Return for TVDAC Channel C:
Connect to ground on board
BLUE#
REFSET
O
A
BLUE# Analog Output:
This signal is an analog video output from the internal color palette
DAC. This signal is used to provide noise immunity.
Resistor Set:
Set point resistor for the internal color palette DAC. A 256-Ω ± 1%
resistor is required between REFSET and motherboard ground.
CRT Horizontal Synchronization:
O
A
TV Resistor set:
TV Reference Current uses an external resistor to set internal
reference voltage levels. A 5-k §Ù ± 0.5% resistor is required
between REFSET and motherboard ground.
HSYNC
VSYNC
O
HVCMOS This signal is used as the horizontal sync (polarity is programmable)
or “sync interval”.
CRT Vertical Synchronization:
O
HVCMOS This signal is used as the vertical sync (polarity is programmable).
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5.1 Intel 915PM North Bridge(7)
Display Data Channel (DDC) and GMBUS Support
LVDS Signals
Signal Name
Type
Description
Signal Name
Type
Description
LDVS Channel A
LCTLA_CLK
I/O
COD
I/O
COD
I/O
COD
I/O
COD
I/O
COD
I/O
I2C Based control signal (Clock) for External SSC clock chip
control –
I2C Based control signal (Data) for External SSC clock chip control –
LADATAP[2:0]
LADATAN[2:0]
LACLKP
I/O
LVDS
I/O
LVDS
I/O
LVDS
I/O
LVDS
Channel A differential data output - positive
Channel A differential data output –negative
Channel A differential clock output – positive
Channel A differential clock output – negative
LDVS Channel B
LCTLB_DATA
DDCCLK
CRT DDC clock monitor control support
CRT DDC Data monitor control support
EDID support for flat panel display
DDCDATA
LDDC_CLK
LDDC_DATA
LACLKN
EDID support for flat panel display
LBDATAP[2:0]
LBDATAN[2:0]
LBCLKP
I/O
LVDS
I/O
LVDS
I/O
LVDS
I/O
LVDS
Channel B differential data output – positive
NOTE: Signals do not exist in Intel 915GMS.
Channel B differential data output –negative
NOTE: Signals do not exist in Intel 915GMS.
Channel B differential clock output – positive
NOTE: Signals do not exist in Intel 915GMS.
Channel B differential clock output – negative
NOTE: Signals do not exist in Intel 915GMS.
LFP Panel power and backlight control
COD
SDVOCTRL_CL
K
SDVOCTRL_DA
TA
I/O
COD
I/O
I2C Based control signal (Clock) for SDVO device
I2C Based control signal (Data) for SDVO device
COD
LBCLKN
DDR SDRAM Reference and Compensation
Signal Name
Type
Description
LVDD_EN
O
LVDS panel power enable: Panel power control enable control.
SMRCOMPN
I/O
A
System Memory RCOMP N:
Buffer compensation
HVCMOS This signal is also called VDD_DBL in the CPIS specification and is
used to control the VDC source to the panel logic.
This signal is powered by the System Memory rail (2.5 V for DDR,
1.8 V for DDR2).
LBKLT_EN
LBKLT_CRTL
O
LVDS backlight enable: Panel backlight enable control.
HVCMOS This signal is also called ENA_BL in the CPIS specification and is
used to gate power into the backlight circuitry.
SMRCOMPP
I/O
A
System Memory RCOMP P:
Buffer compensation
O
Panel backlight brightness control: Panel brightness control.
This signal is powered by the System Memory rail
HVCMOS This signal is also called VARY_BL in the CPIS specification and is
used as the PWM Clock input signal.
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT
SMVREF[1:0]
I
X Buffer Slew Rate Input control.
A
O
A
I
A
O
A
I
LVDS Reference signals
X Buffer Slew Rate Output control.
Y Buffer Slew Rate Input control.
Y Buffer Slew Rate Output control.
LIBG
I/O
Ref
I
Ref
I
Ref
O
A
LVDS Reference Current. –
1.5 kΩ Pull down resistor needed
Reserved. - No connect.
LVREFH
LVREFL
LVBG
Reserved. - No connect.
Reserve. - No connect
SDRAM Reference Voltage:
A
Reference voltage inputs for each DQ, DQS, & RCVENIN#.
Also used during ODT RCOMP.
Note: LVDS Channel B interface is not supported and do not exist for Intel 915GMS
SMOCDCOMP[1
:0]
I
A
On-Die DRAM OCD driver compensation
OCD compensation
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5.1 Intel 915PM North Bridge(8)
Serial DVO Interface.
Serial DVO Interface (Continued)
Signal Name
Type
Description
SDVO B Interface
Signal Name
Type
Description
SDVO C Interface
SDVOB_CLKP
SDVOB_CLKN
SDVOB_RED
O
PCIE
O
PCIE
O
PCIE
O
PCIE
O
PCIE
O
PCIE
O
PCIE
O
PCIE
Serial Digital Video B Clock.
SDVOC_CLKP
O
PCIE
Serial Digital Video C Clock.
Multiplexed with EXP_TXP_7.
NOTE: Signals do not exist in Intel 915GMS.
Serial Digital Video C Clock Complement.
Multiplexed with EXP_TXN_7.
Multiplexed with EXP_TXP_3.
Serial Digital Video B Clock Complement.
Multiplexed with EXP_TXN_3.
Serial Digital Video B Red Data.
Multiplexed with EXP_TXP_0.
Serial Digital Video B Red Data Complement.
Multiplexed with EXP_TXN_0.
Serial Digital Video B Green Data.
Multiplexed with EXP_TXP_1.
Serial Digital Video B Green Data Complement.
Multiplexed with EXP_TXN_1.
Serial Digital Video B Blue Data.
Multiplexed with EXP_TXP_2.
Serial Digital Video B Blue Data Complement.
Multiplexed with EXP_TXN_2.
SDVO C Interface
SDVOC_CLKN
O
PCIE
NOTE: Signals do not exist in Intel 915GMS.
SDVO Common Signals
SDVOB_RED#
SDVOB_GREEN
SDVO_TVCLKI
N
SDVO_TVCLKI
N#
SDVO_FLDSTA
LL
SDVO_FLDSTA
LL#
SDVOB_INT
I
Serial Digital Video TVOUT Synchronization Clock.
Multiplexed with EXP_RXP_0.
Serial Digital Video TV-out Synchronization Clock Complement.
Multiplexed with EXP_RXN_0.
Serial Digital Video Field Stall.
Multiplexed with EXP_RXP_2.
Serial Digital Video Field Stall Complement.
Multiplexed with EXP_RXN_2.
Serial Digital Video Input Interrupt.
Multiplexed with EXP_RXP_1.
PCIE
I
PCIE
I
SDVOB_GREEN
#
SDVOB_BLUE
PCIE
I
PCIE
I
SDVOB_BLUE#
PCIE
SDVOB_INT#
SDVOC_INT
SDVOC_INT#
I
Serial Digital Video Input Interrupt Complement.
Multiplexed with EXP_RXN_1.
Serial Digital Video Input Interrupt.
Multiplexed with EXP_RXP_5.
Serial Digital Video Input Interrupt Complement.
Multiplexed with EXP_RXN_5.
SDVOC_RED
O
PCIE
Serial Digital Video C Red Data / SDVO B Alpha.
Multiplexed with EXP_TXP_4.
NOTE: Signals do not exist in Intel 915GMS..
Serial Digital Video C Red Complement / Alpha Complement.
Multiplexed with EXP_TXN_4.
NOTE: Signals do not exist in Intel 915GMS.
Serial Digital Video C Green.
PCIE
I
PCIE
SDVOC_RED#
SDVOC_GREEN
O
PCIE
I
PCIE
O
PCIE
Multiplexed with EXP_TXP_5.
NOTE: Signals do not exist in Intel 915GMS.
Serial Digital Video C Green Complement.
Multiplexed with EXP_TXN_5.
SDVOC_GREEN
#
O
PCIE
NOTE: Signals do not exist in Intel 915GMS.
Serial Digital Video Channel C Blue.
Multiplexed with EXP_TXP_6.
NOTE: Signals do not exist in Intel 915GMS.
Serial Digital Video C Blue Complement.
Multiplexed with EXP_TXN_6.
SDVOC_BLUE
SDVOC_BLUE#
O
PCIE
O
PCIE
NOTE: Signals do not exist in Intel 915GMS.
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5.1 Intel 915PM North Bridge(9)
Reset and Miscellaneous Signals
PLL Signals
Signal Name
Signal Name
Type
Description
Type
Description
RSTIN#
I
Reset In:
HCLKP
I
Differential Host Clock In:
HVCMOS When asserted this signal will asynchronously reset the GMCH logic.
This signal is connected to the PLT_RST# output of the ICH6-M.
This input has a Schmitt trigger to avoid spurious resets. This input
buffer is 3.3-V tolerant.
Diff Clk Differential clock input for the Host PLL. Used for phase cancellation
for FSB transactions. This clock is used by all of the GMCH logic
that is in the Host clock domain. Also used to generate core and
system memory internal clocks. This is a low voltage differential
signal and runs at ¼ the FSB data rate.
PWROK
I
Power OK:
HVCMOS When asserted, PWROK is an indication to the GMCH that core
power has been stable for at least 10 µs.
HCLKN
GCLKP
I
Differential Host Clock Input Complement:
Diff Clk
I
This input buffer is 3.3-V tolerant.
Differential PCI Express based Graphics / DMI Clock In:
H_BSEL [2:0]
(CFG[2:0])
I
Host Bus Speed Select:
Diff Clk These pins receive a differential 100 MHz Serial Reference clock
from the external clock synthesizer. This clock is used to generate the
clocks necessary for the support of PCI Express.
HVCMOS At the deassertion of RSTIN#, the value sampled on these pins
determines the expected frequency of the bus.
External pull-ups are required.
GCLKN
I
Differential PCI Express based Graphics / DMI Clock In
CFG[17:3]
I
HW straps:
AGTL+ CFG [17:3] has internal pull up.
NOTE: Not all CFG Balls are supported for Intel 915GMS.
HW straps:
HVCMOS CFG [20:18] has internal pull down
NOTE: Not all CFG Balls are supported for Intel 915GMS.
GMCH Integrated Graphics Busy:
Diff Clk complement
DREF_CLKP
DREF_CLKN
DREF_SSCLKP
I
Display PLLA Differential Clock In –
Diff Clk Display PLL Differential Clock In, no SSC support –
CFG[20:18]
BM_BUSY#
I
I
Display PLLA Differential Clock In Complement –
Diff Clk Display PLL Differential Clock In Complement - no SSC support
Display PLLB Differential Clock In –
I
O
Diff Clk Optional Display PLL Differential Clock In for SSC support –
NOTE: Differential Clock input for optional SSC support for LVDS
display.
HVCMOS Indicates to the ICH that the integrated graphics engine within the
MCH is busy and transitions to low power states should not be
attempted until that is no longer the case.
DREF_SSCLKN
I
Display PLLB Differential Clock In complement –
THRMTRIP#
O
GMCH Thermal Trip:
Diff Clk Optional Display PLL Differential Clock In Complement for SSC
COD
Assertion of THERMTRIP# (Thermal Trip) indicates the GMCH
junction temperature has reached a level beyond which damage may
occur. Upon assertion of THERMTRIP#, the GMCH will shut off its
internal clocks (thus halting program execution) in an attempt to
reduce the GMCH core junction temperature. To protect GMCH, its
core voltage (Vcc) must be removed following the assertion of
THERMTRIP#. Once activated, THERMTRIP# remains latched
until RSTIN# is asserted. While the assertion of the RSTIN# signal
will deassert THERMTRIP#, if the GMCH’s junction temperature
remains at or above the trip level, THERMTRIP# will again be
asserted.
support
NOTE: Differential Clock input for optional SSC support for LVDS
display.
Note: PLL interfaces signal group are supported the Mobile Intel 915GM/PM/GMS and Intel
910GML Express chipsets, unless otherwise noted.
EXT_TS[1:0]#
I
External Thermal Sensor Input:
HVCMOS If the system temperature reaches a dangerously high value then this
signal can be used to trigger the start of system memory throttling.
NOTE: EXT_TS1# functionality is not supported in 915GMS. A pull
up is required on this pin
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5.1 Intel 915PM North Bridge(10)
Power and Ground
Power and Ground (Continued)
Interface
Ball Name Description
Interface
Ball Name Description
Host
VTT (VCCP) FSB power supply (1.05 V) - (VCCP)
TVDAC
VCCA_TVBG TV DAC Band Gap Power (3.3 V)
VSSA_TVBG TV DAC Band Gap VSS
DRAM
VCCA_SM VCCASM is the Analog power supply for SM data buffers used for
DLL & other logic (1.5 V)
VCCD_TVDA Dedicated Power Supply for TVDAC (1.5 V)
VCCSM
System memory power supply (DDR=2.5 V; DDR2=1.8 V)
C
PCI Express
Based
Graphics /DMI
VCC3G
PCI Express / DMI Analog power supply (1.5 V)
VCCDQ_TVD Power Supply for Digital Quiet TVDAC (1.5 V)
AC
VCCA_3GBG PCI Express / DMI band gap power supply (2.5 V)
VSSA_3GBG PCI Express / DMI band gap ground
VCCA_TVDA Power Supply for TV Out Channel A (3.3 V)
CA
PLL Analog
VCCA_HPLL Power supply for the Host VCO in the host/mem/core PLL (1.5 V)
VCCA_MPLL Power supply for the mem VCO in the host/mem/core PLL (1.5 V)
VCCA_TVDA Power Supply for TV Out Channel B (3.3 V)
CB
VCCA_TVDA Power Supply for TV Out Channel C (3.3 V)
CC
VCCD_HMPL Power Supply for the digital dividers in the HMPLL (1.5 V)
L
Core
VCC
Core VCC – (1.05 V or 1.5 V)
VCCA_3GPLL Power supply for the 3GIO PLL (1.5 V)
Ground
NCTF
VSS
Ground
VCCA_DPLL Display A PLL power supply (1.5 V)
Non-Critical To Function power signals:
A
“NCTF” (Non-Critical To Function) have been designed into the package footprint
to enhance the Solder Joint Reliability of our products by absorbing some of the
stress introduced by the Characteristic Thermal Expansion (CTE) mismatch of the
Die to package interface. It is expected that in some cases, these balls may crack
partially or completely, however, this will have no impact to our product
performance or reliability. Intel has added these balls primarily to serve as sacrificial
stress absorbers.
VCCA_DPLL Display B PLL power supply (1.5 V)
B
High Voltage
Interfaces
CRT DAC
VCCHV
Power supply for the HV buffers (2.5 V)
VCCA_CRTD Analog power supply for the DAC (2.5 V)
AC
VSSA_CRTD Analog ground for the DAC
NOTE: Signals do not exist in Intel 915GMS.
VTT_NCTF NCTF FSB power supply (1.05 V or 1.2 V)
AC
VCC_SYNC Power supply for HSYNC/ VSYNC (2.5 V)
VCC_NCTF NTCF Core VCC – (1.05 V or 1.5 V)
LVDS
VCCD_LVDS Digital power supply (1.5 V)
VCCSM_NCT NTCF System memory power supply (DDR=2.5 V; DDR2=1.8 V)
VCCTX_LVD Data/Clk Tx power supply (2.5 V)
F
S
VSS_NCTF NTCF Ground
VCCA_LVDS LVDS analog power supply (2.5 V)
VSSALVDS LVDS analog VSS
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5.2 Intel ICH6-M South Bridge(1)
PCI Interface Signals
PCI Interface Signals (Continued)
Name
Type Description
Name
Type Description
AD[31:0]
I/O
PCI Address/Data: AD[31:0] is a multiplexed address and data bus.
During the first clock of a transaction, AD[31:0] contain a physical
address (32 bits). During subsequent clocks, AD[31:0] contain data.
The Intel® ICH6 will drive all 0s on AD[31:0] during the address
phase of all PCI Special Cycles.
Bus Command and Byte Enables: The command and byte enable
signals are multiplexed on the same PCI pins. During the address
phase of a transaction,
IRDY#
I/O Initiator Ready: IRDY# indicates the ICH6's ability, as an initiator,
to complete the current data phase of the transaction. It is used in
conjunction with TRDY#. A data phase is completed on any clock
both IRDY# and TRDY# are sampled asserted. During a write,
IRDY# indicates the ICH6 has valid data present on AD[31:0].
During a read, it indicates the ICH6 is prepared to latch data. IRDY#
is an input to the ICH6 when the ICH6 is the target and an output
from the ICH6 when the ICH6 is an initiator. IRDY# remains
tri-stated by the ICH6 until driven by an initiator.
C/BE[3:0]#
I/O
C/BE[3:0]# define the bus command. During the data phase
C/BE[3:0]# define the Byte Enables.
TRDY#
I/O
Target Ready: TRDY# indicates the ICH6's ability as a target to
complete the current data phase of the transaction. TRDY# is used in
conjunction with IRDY#. A data phase is completed when both
TRDY# and IRDY# are sampled asserted.
C/BE[3:0]#
0000b
0001b
0010b
0011b
0110b
0111b
1010b
1011b
1100b
1110b
1111b
Command Type
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
During a read, TRDY# indicates that the ICH6, as a target, has placed
valid data on AD[31:0]. During a write, TRDY# indicates the ICH6,
as a target is prepared to latch data. TRDY# is an input to the ICH6
when the ICH6 is the initiator and an output from the ICH6 when the
ICH6 is a target. TRDY# is tri-stated from the leading edge of
PLTRST#. TRDY# remains tri-stated by the ICH6 until driven by a
target.
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple
Memory Read Line
Memory Write and Invalidate
STOP#
PAR
I/O
I/O
Stop: STOP# indicates that the ICH6, as a target, is requesting the
initiator to stop the current transaction. STOP# causes the ICH6, as an
initiator, to stop the current transaction. STOP# is an output when the
ICH6 is a target and an input when the ICH6 is an initiator.
Calculated/Checked Parity: PAR uses “even” parity calculated on
36 bits, AD[31:0] plus C/BE[3:0]#. “Even” parity means that the
ICH6 counts the number of one within the 36 bits plus PAR and the
sum is always even. The ICH6 always calculates PAR on 36 bits
regardless of the valid byte enables. The ICH6 generates PAR for
address and data phases and only guarantees PAR to be valid one PCI
clock after the corresponding address or data phase. The ICH6 drives
and tri-states PAR identically to the AD[31:0] lines except that the
ICH6 delays PAR by exactly one PCI clock. PAR is an output during
the address phase (delayed one clock) for all ICH6 initiated
transactions. PAR is an output during the data phase (delayed one
clock) when the ICH6 is the initiator of a PCI write transaction, and
when it is the target of a read transaction. ICH6 checks parity when it
is the target of a PCI write transaction. If a parity error is detected, the
ICH6 will set the appropriate internal status bits, and has the option to
generate an NMI# or SMI#.
All command encodings not shown are reserved. The ICH6 does not
decode reserved values, and therefore will not respond if a PCI master
generates a cycle using one of the reserved values.
DEVSEL#
FRAME#
I/O
I/O
Device Select: The ICH6 asserts DEVSEL# to claim a PCI
transaction. As an output, the ICH6 asserts DEVSEL# when a PCI
master peripheral attempts an access to an internal ICH6 address or an
address destined DMI (main memory or graphics). As an input,
DEVSEL# indicates the response to an ICH6-initiated transaction on
the PCI bus. DEVSEL# is tri-stated from the leading edge of
PLTRST#. DEVSEL# remains tri-stated by the ICH6 until driven by
a target device.
Cycle Frame: The current initiator drives FRAME# to indicate the
beginning and duration of a PCI transaction. While the initiator
asserts FRAME#, data transfers continue. When the initiator negates
FRAME#, the transaction is in the final data phase. FRAME# is an
input to the ICH6 when the ICH6 is the target, and FRAME# is an
output from the ICH6 when the ICH6 is the initiator. FRAME#
remains tri-stated by the ICH6 until driven by an initiator.
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5.2 Intel ICH6-M South Bridge(2)
PCI Interface Signals (Continued)
Serial ATA Interface Signals
Name
Type Description
Name
Type Description
PERR#
I/O
Parity Error: An external PCI device drives PERR# when it receives
SATA[0]TXP
SATA[0]TXN
SATA[0]RXP
SATA[0]RXN
SATA[1]TXP
SATA[1]TXN
SATA[1]RXP
SATA[1]RXN
SATA[2]TXP
SATA[2]TXN
SATA[2]RXP
SATA[2]RXN
SATA[3]TXP
SATA[3]TXN
SATA[3]RXP
SATA[3]RXN
SATARBIAS
O
Serial ATA 0 Differential Transmit Pair: These are outbound
high-speed differential signals to Port 0.
Serial ATA 0 Differential Receive Pair: These are inbound
high-speed differential signals from Port 0.
Serial ATA 1 Differential Transmit Pair: These are outbound
high-speed differential signals to Port 1.
Serial ATA 1 Differential Receive Pair: These are inbound
high-speed differential signals from Port 1.
Serial ATA 2 Differential Transmit Pair: These are outbound
high-speed differential signals to Port 2.
Serial ATA 2 Differential Receive Pair: These are inbound
high-speed differential signals from Port 2.
Serial ATA 3 Differential Transmit Pair: These are outbound
high-speed differential signals to Port 3.
Serial ATA 3 Differential Receive Pair: These are inbound
high-speed differential signals from Port 3.
data that has a parity error. The ICH6 drives PERR# when it detects a
parity error. The ICH6 can either generate an NMI# or SMI# upon
detecting a parity error (either detected internally or reported via the
PERR# signal).
PCI Requests: The ICH6 supports up to 7 masters on the PCI bus.
The REQ[4]#, REQ[5]#, and REQ[6]# pins can instead be used as a
GPI.
I
O
I
REQ[0:3]#
I
REQ[4]# / GPI[40]
REQ[5]# / GPI[1]
REQ[6]# / GPI[0]
GNT[0:3]#
GNT[4]# /
GPO[48]
GNT[5]# /
GPO[17]#
GNT[6]# /
GPO[16]#
O
I
O
PCI Grants: The ICH6 supports up to 7 masters on the PCI bus. The
GNT[4]# pin can instead be used as a GPO.
Pull-up resistors are not required on these signals. If pull-ups are
used, they should be tied to the Vcc3_3 power rail.
GNT[5]#/GPO[17] and GNT[6]#/GPO[17] both have an internal
pull-up.
NOTE: GNT[6] is sampled at the rising edge of PWROK as a
functional strap. See Section 2.22.1 for more details. There is a weak,
integrated pull-up resistor on the GNT[6] pin.
PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all
transactions on the PCI Bus.
O
I
O
I
Serial ATA Resistor Bias: These are analog connection points for an
external resistor to ground.
PCICLK
PCIRST#
I
SATARBIAS#
Serial ATA Resistor Bias Complement: These are analog
connection points for an external resistor to ground.
Serial ATA 0 General Purpose: This is an input pin which can be
configured as an interlock switch corresponding to SATA Port 0.
When used as an interlock switch status indication, this signal should
be drive to ‘0’ to indicate that the switch is closed and to ‘1’ to
indicate that the switch is open.
If interlock switches are not required, this pin can be configured as
GPI[26].
NOTE: All SATAxGP pins must be configured with the same
function: as either SATAxGP pins or GPI pins.
Serial ATA 1 General Purpose: Same function as SATA[0]GP,
except for SATA Port 1.
If interlock switches are not required, this pin can be configured as
GPI[29].
Serial ATA 2 General Purpose: Same function as SATA[0]GP,
except for SATA Port 2.
If interlock switches are not required, this pin can be configured as
GPI[30].
O
PCI Reset: This is the Secondary PCI Bus reset signal. It is a logical
OR of the primary interface PLTRST# signal and the state of the
Secondary Bus Reset bit of the Bridge Control register (D30:F0:3Eh,
bit 6).
SATA[0]GP /
GPI[26]
I
NOTE: PCIRST# is in the VccSus3_3 well.
I/O
PCI Lock: This signal indicates an exclusive bus operation and may
require multiple transactions to complete. ICH6 asserts PLOCK#
when it performs non-exclusive transactions on the PCI bus.
PLOCK# is ignored when PCI masters are granted the bus.
PLOCK#
SERR#
PME#
OD I/O System Error: SERR# can be pulsed active by any PCI device that
detects a system error condition. Upon sampling SERR# active, the
ICH6 has the ability to generate an NMI, SMI#, or interrupt.
OD I PCI Power Management Event: PCI peripherals drive PME# to
wake the system from low-power states S1–S5. PME# assertion can
also be enabled to generate an SCI from the S0 state. In some cases
the ICH6 may drive PME# active due to an internal wake event. The
ICH6 will not drive PME# high, but it will be pulled up to VccSus3_3
by an internal pull-up resistor.
SATA[1]GP /
GPI[29]
I
I
SATA[2]GP /
GPI[30]
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5.2 Intel ICH6-M South Bridge(3)
Serial ATA Interface Signals (Continued)
LAN Connect Interface Signals
Name
Type Description
Name
Type Description
SATA[3]GP /
GPI[31]
I
Serial ATA 3 General Purpose: Same function as SATA[0]GP,
except for SATA Port 3.
LAN_CLK
I
LAN I/F Clock: This signal is driven by the LAN Connect
component. The frequency range is 5 MHz to 50 MHz.
If interlock switches are not required, this pin can be configured as
GPI[31].
LAN_RXD[2:0]
I
Received Data: The LAN Connect component uses these signals to
transfer data and control information to the integrated LAN
controller. These signals have integrated weak pull-up resistors.
Transmit Data: The integrated LAN controller uses these signals to
transfer data and control information to the LAN Connect component.
LAN Reset/Sync: The LAN Connect component’s Reset and Sync
signals are multiplexed onto this pin.
SATALED#
OC O
Serial ATA LED: This is an open-collector output pin driven during
SATA command activity. It is to be connected to external circuitry
that can provide the current to drive a platform LED. When active,
the LED is on. When tri-stated, the LED is off. An external pull-up
resistor to Vcc3_3 is required.
LAN_TXD[2:0]
LAN_RSTSYNC
O
O
NOTE: An internal pull-up is enabled only during PLTRST#
assertion.
Other Clocks
Name
Type Description
CLK14
I
I
I
I
Oscillator Clock: This clock is used for 8254 timers. It runs at
14.31818 MHz. This clock is permitted to stop during S3 (or lower)
states.
48 MHz Clock: This clock is used to run the USB controller. IT runs
at 48.000 MHz.
This clock is permitted to stop during S3 (or lower) states.
100 MHz Differential Clock: These signals are used to run the
SATA controller. Runs at 100 MHz. This clock is permitted to stop
during S3 (or lower) states.
Interrupt Signals
CLK48
Name
Type Description
I/O Serial Interrupt Request: This pin implements the serial interrupt
protocol.
OD I PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can
be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described
in the Interrupt Steering section. Each PIRQx# line has a separate
Route Control register.
SERIRQ
SATA_CLKP
SATA_CLKN
PIRQ[D:A]#
DMI_CLKP,
DMI_CLKN
100 MHz Differential Clock: These signals are used to run the
Direct Media Interface. Runs at 100 MHz.
In APIC mode, these signals are connected to the internal I/O APIC in
the following fashion: PIRQA# is connected to IRQ16, PIRQB# to
IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the
legacy interrupts.
LPC Interface Signals
PIRQ[H:E]# /
GPI[5:2]
OD I PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can
be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described
in the Interrupt Steering section. Each PIRQx# line has a separate
Route Control register.
Name
Type Description
LAD[3:0] /
FWH[3:0]
LFRAME# /
FWH[4]
LDRQ[0]#
LDRQ[1]# /
GPI[41]
I/O
O
I
LPC Multiplexed Command, Address, Data: For LAD[3:0],
internal pull-ups are provided.
LPC Frame: LFRAME# indicates the start of an LPC cycle, or an
abort.
LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to
request DMA or bus master access. These signals are typically
connected to external Super I/O device. An internal pull-up resistor is
provided on these signals.
In APIC mode, these signals are connected to the internal I/O APIC in
the following fashion: PIRQE# is connected to IRQ20, PIRQF# to
IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the
legacy interrupts. If not needed for interrupts, these signals can be
used as GPI.
IDEIRQ
I
IDE Interrupt Request: This interrupt input is connected to the IDE
LDRQ[1]# may optionally be used as GPI.
drive.
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5.2 Intel ICH6-M South Bridge(4)
IDE Interface Signals
IDE Interface Signals (Continued)
Name
Type Description
Name
Type Description
DCS1#
O
O
O
IDE Device Chip Selects for 100 Range: For ATA command
register block. This output signal is connected to the corresponding
signal on the IDE connector.
IDE Device Chip Select for 300 Range: For ATA control register
block. This output signal is connected to the corresponding signal on
the IDE connector.
IDE Device Address: These output signals are connected to the
corresponding signals on the IDE connector. They are used to indicate
which byte in either the ATA command block or control block is
being addressed.
DIOW# / (DSTOP)
O Disk I/O Write (PIO and Non-Ultra DMA): This is the command to
the IDE device that it may latch data from the DD lines. Data is
latched by the IDE device on the de-assertion edge of DIOW#. The
IDE device is selected either by the ATA register file chip selects
(DCS1# or DCS3#) and the DA lines, or the IDE DMA acknowledge
(DDAK#).
DCS3#
Disk Stop (Ultra DMA): ICH6 asserts this signal to terminate a burst.
I/O Channel Ready (PIO): This signal will keep the strobe active
(DIOR# on reads, DIOW# on writes) longer than the minimum width.
It adds wait-states to PIO transfers.
DA[2:0]
IORDY / (DRSTB
/ WDMARDY#)
I
Disk Read Strobe (Ultra DMA Reads from Disk): When reading from
disk, ICH6 latches data on rising and falling edges of this signal from
the disk.
Disk DMA Ready (Ultra DMA Writes to Disk): When writing to
disk, this is de-asserted by the disk to pause burst data transfers.
DD[15:0]
DDREQ
I/O
I
IDE Device Data: These signals directly drive the corresponding
signals on the IDE connector. There is a weak internal pull-down
resistor on DD7.
IDE Device DMA Request: This input signal is directly driven from
the DRQ signal on the IDE connector. It is asserted by the IDE device
to request a data transfer, and used in conjunction with the PCI bus
master IDE function and are not associated with any AT compatible
DMA channel. There is a weak internal pull-down resistor on this
signal.
IDE Device DMA Acknowledge: This signal directly drives the
DAK# signal on the IDE connector. DDACK# is asserted by the Intel
ICH6 to indicate to IDE DMA slave devices that a given data transfer
cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle.
This signal is used in conjunction with the PCI bus master IDE
function and are not associated with any AT-compatible DMA
channel.
System Management Interface Signals
Name
Type Description
INTRUDER#
I
Intruder Detect: This signal can be set to disable system if box
detected open.
This signal’s status is readable, so it can be used like a GPI if the
Intruder Detection is not needed.
DDACK#
O
O
SMLINK[1:0]
LINKALERT#
OD I/O System Management Link: SMBus link to optional external system
management ASIC or LAN controller. External pull-ups are required.
Note that SMLINK0 corresponds to an SMBus Clock signal, and
SMLINK1 corresponds to an SMBus Data signal.
OD I/O SMLink Alert: Output of the integrated LAN and input to either the
integrated ASF or an external management controller in order for the
LAN’s SMLINK slave to be serviced.
DIOR# / (DWSTB
/ RDMARDY#)
DIOR# /
Disk I/O Read (PIO and Non-Ultra DMA): This is the command to
the IDE device that it may drive data onto the DD lines. Data is
latched by the ICH6 on the de-assertion edge of DIOR#. The IDE
device is selected either by the ATA register file
chip selects (DCS1# or DCS3#) and the DA lines, or the IDE DMA
acknowledge (DDAK#)
Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write
strobe for writes to disk. When writing to disk, ICH6 drives valid data
on rising and falling edges of DWSTB.
Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA
ready for reads from disk. When reading from disk, ICH6 de-asserts
RDMARDY# to pause burst data transfers.
SM Bus Interface Signals
Name
SMBDATA
SMBCLK
Type Description
OD I/O SMBus Data: External pull-up resistor is required.
OD I/O SMBus Clock: External pull-up resistor is required.
SMBALERT#/
I
SMBus Alert: This signal is used to wake the system or generate
GPI[11]
SMI#. If not used for SMBALERT#, it can be used as a GPI.
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5.2 Intel ICH6-M South Bridge(5)
USB Interface Signals
EEPROM Interface Signals
Name
Type Description
Name
Type Description
USBP[0]P,
I/O
I/O
I/O
I/O
I
Universal Serial Bus Port [1:0] Differential: These differential pairs
are used to transmit Data/Address/Command signals for ports 0 and 1.
These ports can be routed to UHCI controller #1 or the EHCI
controller.
NOTE: No external resistors are required on these signals. The ICH6
integrates 15 KΩ?pull-downs and provides an output driver
EE_SHCLK
O
EEPROM Shift Clock: This signal is the serial shift clock output to
the EEPROM.
EEPROM Data In: This signal transfers data from the EEPROM to
the Intel ® ICH6. This signal has an integrated pull-up resistor.
EEPROM Data Out: This signal transfers data from the ICH6 to the
EEPROM.
USBP[0]N,
USBP[1]P,
USBP[1]N
EE_DIN
EE_DOUT
EE_CS
I
O
O
impedance of 45Ωwhich requires no external series resistor
EEPROM Chip Select: This is the chip select signal to the
EEPROM.
USBP[2]P,
USBP[2]N,
USBP[3]P,
USBP[3]N
Universal Serial Bus Port [3:2] Differential: These differential pairs
are used to transmit data/address/command signals for ports 2 and 3.
These ports can be routed to UHCI controller #2 or the EHCI
controller.
NOTE: No external resistors are required on these signals. The ICH6
integrates 15 KΩ?pull-downs and provides an output driver
Miscellaneous Signals
Name
Type Description
INTVRMEN
I
Internal Voltage Regulator Enable: This signal enables the internal
1.5 V Suspend regulator when connected to VccRTC. When
connected to Vss, the internal regulator is disabled
Speaker: The SPKR signal is the output of counter 2 and is internally
“ANDed” with Port 61h bit 1 to provide Speaker Data Enable. This
signal drives an external speaker driver device that in turn drives the
system speaker. Upon PLTRST#, its output state is 0.
NOTE: SPKR is sampled at the rising edge of PWROK as a
functional strap. See Section 2.22.1 for more details. There is a weak
integrated pull-down resistor on SPKR pin.
RTC Reset: When asserted, this signal resets register bits in the RTC
well.
NOTES:
1. Unless CMOS is being cleared (only to be done in the G3 power
state), the RTCRST# input must always be high when all other
RTC power planes are on.
2. In the case where the RTC battery is dead or missing on the
platform, the RTCRST# pin must rise before the RSMRST# pin.
Test Point 0: This signal must have an external pull-up to
VccSus3_3.
impedance of 45Ωwhich requires no external series resistor
Universal Serial Bus Port [5:4] Differential: These differential pairs
are used to transmit Data/Address/Command signals for ports 4 and 5.
These ports can be routed to UHCI controller #3 or the EHCI
controller.
NOTE: No external resistors are required on these signals. The ICH6
integrates 15 KΩ?pull-downs and provides an output driver
USBP[4]P,
USBP[4]N,
USBP[5]P,
USBP[5]N
SPKR
O
impedance of 45Ωwhich requires no external series resistor
USBP[6]P,
USBP[6]N,
USBP[7]P,
USBP[7]N
Universal Serial Bus Port [7:6] Differential: These differential pairs
are used to transmit Data/Address/Command signals for ports 6 and 7.
These ports can be routed to UHCI controller #4 or the EHCI
controller.
NOTE: No external resistors are required on these signals. The ICH6
integrates 15 KΩ?pull-downs and provides an output driver
RTCRST#
I
impedance of 45Ωwhich requires no external series resistor
OC[3:0]#
Overcurrent Indicators: These signals set corresponding bits in the
USB controllers to indicate that an overcurrent condition has
occurred.
OC[7:4]# may optionally be used as GPIs.
NOTE: OC[7:0]# are not 5 V tolerant.
USB Resistor Bias: Analog connection point for an external resistor.
Used to set transmit currents and internal load resistors.
USB Resistor Bias Complement: Analog connection point for an
external resistor. Used to set transmit currents and internal load
resistors.
OC[4]# / GPI[9]
OC[5]# / GPI[10]
OC[6]# / GPI[14]
OC[7]# / GPI[15]
USBRBIAS
TP[0]
I
TP[1]
TP[2]
TP[3]
TP[4]
O
O
I
Test Point 1: Route signal to a test point.
Test Point 2: Route signal to a test point.
Test Point 3: Route signal to a test point.
Test Point 4: Route signal to a test point.
O
I
USBRBIAS#
O
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5.2 Intel ICH6-M South Bridge(6)
Power Management Interface Signals
Power Management Interface Signals (Continued)
Name
Type Description
Name
Type Description
PWRBTN#
I
Power Button: The Power Button will cause SMI# or SCI to indicate
PLTRST#
O
Platform Reset: The ICH6 asserts PLTRST# to reset devices on the
a system request to go to a sleep state. If the system is already in a
sleep state, this signal will cause a wake event. If PWRBTN# is
pressed for more than 4 seconds, this will cause an unconditional
transition (power button override) to the S5 state. Override will occur
even if the system is in the S1-S4 states. This signal has an internal
pull-up resistor and has an internal 16 ms de-bounce on the input.
Ring Indicate: This signal is an input from a modem. It can be
enabled as a wake event, and this is preserved across power failures.
System Reset: This pin forces an internal reset after being debounced.
The ICH6 will reset immediately if the SMBus is idle; otherwise, it
will wait up to 25 ms ± 2 ms for the SMBus to idle before forcing a
reset on the system.
platform (e.g., SIO, FWH, LAN, (G)MCH, IDE, TPM, etc.). The
ICH6 asserts PLTRST# during power-up and when S/W initiates a
hard reset sequence through the Reset Control register (I/O Register
CF9h). The ICH6 drives PLTRST# inactive a minimum of 1 ms after
both PWROK and VRMPWRGD are driven high. The ICH6 drives
PLTRST# active a minimum of 1 ms when initiated through the Reset
Control register (I/O Register CF9h).
NOTE: PLTRST# is in the VccSus3_3 well.
Thermal Alarm: This is an active low signal generated by external
hardware to generate an SMI# or SCI.
Thermal Trip: When low, this signal indicates that a thermal trip
from the processor occurred, and the ICH6 will immediately
transition to a S5 state. The ICH6 will not wait for the processor stop
grant cycle since the processor has overheated.
S3 Sleep Control: SLP_S3# is for power plane control. This signal
shuts off power to all non-critical systems when in S3 (Suspend To
RAM), S4 (Suspend to Disk), or S5 (Soft Off) states.
S4 Sleep Control: SLP_S4# is for power plane control. This signal
shuts power to all non-critical systems when in the S4 (Suspend to
Disk) or S5 (Soft Off) state.
NOTE: This pin must be used to control the DRAM power in order
to use the ICH6’s DRAM power-cycling feature. Refer to Chapter
5.14.10.2 for details.
S5 Sleep Control: SLP_S5# is for power plane control. This signal is
used to shut power off to all non-critical systems when in the S5 (Soft
Off) states.
RI#
I
I
THRM#
I
I
SYS_RESET#
THRMTRIP#
RSMRST#
LAN_RST#
I
I
Resume Well Reset: This signal is used for resetting the resume
power plane logic.
SLP_S3#
SLP_S4#
O
O
LAN Reset: When asserted, the internal LAN controller will be put
into reset. This signal must be asserted for at least 10 ms after the
resume well power (VccSus3_3 and VccSus1_5) is valid. When
de-asserted, this signal is an indication that the resume well power is
stable.
NOTE: LAN_RST# must de-assert at some point to complete ICH6
power up sequencing.
PCI Express* Wake Event: Sideband wake signal on PCI Express
asserted by components requesting wakeup.
WAKE#
I
I
SLP_S5#
PWROK
O
I
MCH_SYNC#
MCH SYNC: This input is internally ANDed with the PWROK
input.
Connected to the ICH_SYNC# output of (G)MCH.
Suspend Status: This signal is asserted by the ICH6 to indicate that
the system will be entering a low power state soon. This can be
monitored by devices with memory that need to switch from normal
refresh to suspend refresh mode. It can also be used by other
peripherals as an indication that they should isolate their outputs that
may be going to powered-off planes. This signal is called LPCPD# on
the LPC I/F.
Power OK: When asserted, PWROK is an indication to the ICH6
that core power has been stable for at least 99 ms and PCICLK has
been stable for at least 1 mS. An exception to this rule is if the system
is in S3 HOT , in which PWROK may or may notstay asserted even
though PCICLK may be inactive. PWROK can be driven
asynchronously. When PWROK is negated, the ICH6 asserts
PLTRST#.
SUS_STAT# /
LPCPD#
O
NOTE: PWROK must de-assert for a minimum of three RTC clock
periods in order for the ICH6 to fully reset the power and properly
generate the PLTRST# output
SUSCLK
O
I
Suspend Clock: This clock is an output of the RTC generator circuit
to use by other chips for refresh clock.
VRM Power Good: This should be connected to be the processor’s
VRM Power Good signifying the VRM is stable. This signal is
internally ANDed with the PWROK input.
VRMPWRGD
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5.2 Intel ICH6-M South Bridge(7)
Processor Interface Signals
Processor Interface Signals (Continued)
Name
Type Description
Name
Type Description
A20M#
O
O
Mask A20: A20M# will go active based on either setting the
appropriate bit in the Port 92h register, or based on the A20GATE
input being active.
Processor Sleep: This signal puts the processor into a state that saves
substantial power compared to Stop-Grant state. However, during that
time, no snoops occur.
The Intel® ICH6 can optionally assert the CPUSLP# signal when
going to the S1 state, and will always assert it when going to C3 or
C4.
Numeric Coprocessor Error: This signal is tied to the coprocessor
error signal on the processor. FERR# is only used if the ICH6
coprocessor error reporting function is enabled in the OIC.CEN
register (Chipset ConfigurationRegisters:Offset 31FFh: bit 1). If
FERR# is asserted, the ICH6 generates an internal IRQ13 to its
interrupt controller unit. It is also used to gate the IGNNE# signal to
ensure that IGNNE# is not asserted to the processor unless FERR# is
active. FERR# requires an external weak pull-up to ensure a high
level when the coprocessor error function is disabled.
NOTE: FERR# can be used in some states for notification by the
processor of pending interrupt events. This functionality is
independent of the OIC register bit setting.
NMI
O
Non-Maskable Interrupt: NMI is used to force a non-Maskable
interrupt to the processor. The ICH6 can generate an NMI when
either SERR# is asserted or IOCHK# goes active via the SERIRQ#
stream. The processor detects an NMI when it detects a rising edge on
NMI. NMI is reset by setting the corresponding NMI source
enable/disable bit in the NMI Status and Control register (I/O
Register 61h).
System Management Interrupt: SMI# is an active low output
synchronous to PCICLK. It is asserted by the ICH6 in response to one
of many enabled hardware or software events.
Stop Clock Request: STPCLK# is an active low output synchronous
to PCICLK. It is asserted by the ICH6 in response to one of many
hardware or software events.
When the processor samples STPCLK# asserted, it responds by
stopping its internal clock.
Keyboard Controller Reset CPU: The keyboard controller can
generate INIT# to the processor. This saves the external OR gate with
the ICH6’s other sources of INIT#. When the ICH6 detects the
assertion of this signal, INIT# is generated for 16 PCI clocks.
NOTE: The ICH6 will ignore RCIN# assertion during transitions to
the S1, S3, S4, and S5 states.
CPUSLP#
FERR#
SMI#
O
O
I
STPCLK#
RCIN#
I
IGNNE#
O
Ignore Numeric Error: This signal is connected to the ignore error
pin on the processor. IGNNE# is only used if the ICH6 coprocessor
error reporting function is enabled in the OIC.CEN register (Chipset
Configuration Registers:Offset 31FFh: bit 1). If FERR# is active,
indicating a coprocessor error, a write to the Coprocessor Error
register (I/O register F0h) causes the IGNNE# to be asserted.
IGNNE# remains asserted until FERR# is negated. If FERR# is not
asserted when the Coprocessor Error register is written, the IGNNE#
signal is not asserted.
A20GATE
I
A20 Gate: A20GATE is from the keyboard controller. The signal
acts as an alternative method to force the A20M# signal active. It
saves the external OR gate needed with various other chipsets.
Processor Power Good: This signal should be connected to the
processor’s PWRGOOD input to indicate when the processor power
is valid. This is an open- drain output signal (external pull-up resistor
required) that represents a logical AND of the ICH6’s PWROK and
VRMPWRGD signals.
CPUPWRGD /
GPO[49]
OD
O
This signal may optionally be configured as a GPO.
INIT#
O
Initialization: INIT# is asserted by the ICH6 for 16 PCI clocks to
reset the processor.
ICH6 can be configured to support processor Built In Self Test
(BIST).
INIT3_3V#
INTR
O
O
Initialization 3.3 V: This is the identical 3.3 V copy of INIT#
intended for Firmware Hub.
Processor Interrupt: INTR is asserted by the ICH6 to signal the
processor that an interrupt request is pending and needs to be
serviced. It is an asynchronous output and normally driven low.
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5.2 Intel ICH6-M South Bridge(8)
General Purpose I/O Signals 1,2
General Purpose I/O Signals 1,2 (Continued)
Name
Type Tolerance Power Well Description
Name
Type Tolerance Power Well Description
GPO[49]
OD O V_CPU_IO
`Core
This signal is fixed as output only and can
instead be used as CPUPWRGD.
This signal is fixed as output only and can
instead be used as GNT4#.
GPO[18]
O
3.3 V
Core
This signal is fixed as output only.
NOTE: GPO[18] will blink by default
immediately after reset (controllable by
GPO_BLINK (D31:F0:Offset
GPO[48]
O
3.3 V
Core
GPIOBASE+18h:bit 18)).
GPIO[47:42] N/A
N/A
N/A
This signal is not implemented.
GPO[17]
GPO[16]
GPI[15:14]3
GPI[13]3
GPI[12]3
GPI[11]3
GPI[10:9]3
GPI[8]3
O
O
I
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Core
Core
This signal is fixed as output only and can be
used instead as PCI GNT[5]#.
This signal is fixed as output only and can be
used instead as PCI GNT[6]#.
This signal is fixed as input only and can be used
instead as OC[7:6]#
This signal is fixed as input only and is
unmultiplexed.
This signal is fixed as input only and is
unmultiplexed.
This signal is fixed as input only and can be used
instead as SMBALERT#.
This signal is fixed as input only and can be used
instead as OC[5:4]#.
This signal is fixed as input only and is
unmultiplexed.
This signal is fixed as input only and is
unmultiplexed.
GPI[41]
I
3.3 V
Core
This signal is fixed as input only and can be used
instead as LDRQ1#.
This signal is fixed as input only and can be used
instead as REQ4#.
GPI[40]
I
5 V
Core
Resume
Resume
Core
GPIO[39:35] N/A
N/A
N/A
This signal is not implemented.
GPIO[34:33]
I/O
3.3 V
Core
This signal can be input or output and is
unmultiplexed
This signal can be input or output.
I
GPIO[32]
GPI[31]
I/O
I
3.3 V
3.3 V
Core
Core
I
This signal is fixed as input only and can instead
be used for SATA[3]GP.
This signal is fixed as input only and can instead
be used for SATA[2]GP.
This signal is fixed as input only and can instead
be used for SATA[1]GP.
This signal can be input or output and is
unmultiplexed.
This signal is fixed as input only and can instead
be used for SATA[0]GP.
This signal can be input or output and is
unmultiplexed. It is a strap for internal Vcc2_5
regulator. See Section 2.22.1.
This signal can be input or output and is
unmultiplexed.
This signal is fixed as output only.
I
Resume
Resume
Resume
Core
GPI[30]
I
I
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Core
Core
I
GPI[29]
I
GPIO[28:27]
GPI[26]
I/O
I
Resume
Core
GPI[7]3
I
GPI[6]3
I
I
3.3 V
5 V
Core
Core
This signal is fixed as input only.
GPIO[25]
I/O
Resume
GPI[5:2]3
This signal is fixed as input only and can be used
instead as PIRQ[H:E]#.
This signal is fixed as input only and can be used
instead as PCI REQ[6:5]#.
GPI[1:0]3
I
5 V
Core
GPIO[24]
I/O
3.3 V
Resume
NOTES:
GPO[23]
GPIO[22]
GPO[21]
O
N/A
O
3.3 V
N/A
Core
N/A
Core
1.All inputs are sticky. The status bit remains set as long as the input was asserted for two
clocks.GPIs are sampled on PCI clocks in S0/S1. GPIs are sampled on RTC clocks in S3/S4/S5.
2.Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO
signals are not driven high into powered-down planes. Some ICH6 GPIOs may be connected to
pins on devices that exist in the core well. If these GPIOs are outputs, there is a danger that a
loss of core power (PWROK low) or a Power Button Override event will result in the Intel
ICH6 driving a pin to a logic 1 to another device that is powered down.
This signal is not Implemented
3.3 V
This signal is fixed as output only and is
unmultiplexed
This signal is fixed as output only.
GPO[20]
GPO[19]
O
O
3.3 V
3.3 V
Core
Core
This signal is fixed as output only.
NOTE: GPO[19] may be programmed to blink
(controllable by GPO_BLINK (D31:F0:Offset
GPIOBASE+18h:bit 19)).
3.GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either
an SMI# or an SCI, but not both.
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8050QMA N/B Maintenance
5.2 Intel ICH6-M South Bridge(9)
AC ’97/Intel ® High Definition Audio Link Signals
Power and Ground Signals
Name
Type Description
Name
Description
ACZ_RST#
O
AC ’97/Intel ® High Definition Audio Reset: Master hardware reset
to external codec(s).
Vcc3_3
3.3 V supply for core well I/O buffers (22 pins). This power may be shut off in S3,
S4, S5 or G3 states.
ACZ_SYNC
O
AC ’97/Intel High Definition Audio Sync: 48 kHz fixed rate sample
sync to the codec(s). Also used to encode the stream number.
AC ’97 Bit Clock Input: 12.288 MHz serial data clock generated by
the external codec(s). This signal has an integrated pull-down resistor
(see Note below).
Intel High Definition Audio Bit Clock Output: 24.000 MHz serial
data clock generated by the Intel® High Definition Audio controller
(the Intel ICH6). Thissignal has an integrated pull-down resistor so
that ACZ_BIT_CLK does not float when an
Vcc1_5_A
Vcc1_5_B
Vcc2_5
1.5 V supply for core well logic, group A (52 pins). This power may be shut off in
S3, S4, S5 or G3 states.
1.5 V supply for core well logic, group B (45 pins). This power may be shut off in
S3, S4, S5 or G3 states.
2.5V supply for internal logic (2 pins). This power may be shut off in S3, S4, S5 or
G3 states.
NOTE: This voltage may be generated internally (see Section 2.22.1 for strapping
option). If generated internally, these pins should not be connected to an external
supply.
ACZ_BIT_CLK
I/O
Intel High Definition Audio codec (or no codec) is connected but the
signals are temporarily configured as AC ’97.
V5REF
Reference for 5 V tolerance on core well inputs (2 pins). This power may be shut
off in S3, S4, S5 or G3 states.
ACZ_SDOUT
O
I
AC ’97/Intel High Definition Audio Serial Data Out: Serial TDM
data output to the codec(s). This serial output is double-pumped for a
bit rate of 48 Mb/s for Intel High Definition Audio.
VccSus3_3
VccSus1_5
3.3 V supply for resume well I/O buffers (20 pins). This power is not expected to
be shut off unless the system is unplugged.
1.5 V supply for resume well logic (3 pin). This power is not expected to be shut
off unless the system is unplugged.
NOTE: ACZ_SDOUT is sampled at the rising edge of PWROK as a
functional strap. See Section 2.22.1 for more details. There is a weak
integrated pull-down resistor on the ACZ_SDOUT pin.
AC ’97/Intel High Definition Audio Serial Data In [2:0]: Serial
TDM data inputs from the three codecs. The serial input is
single-pumped for a bit rate of 24 Mb/s for Intel High Definition
Audio. These signals have integrated pull-down resistors, which are
always enabled.
This voltage may be generated internally (see Section 2.22.1 for strapping option).
If generated internally, these pins should not be connected to an external supply.
Reference for 5 V tolerance on resume well inputs (1 pin). This power is not
expected to be shut off unless the system is unplugged.
3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well (1 pin). This
power is not expected to be shut off unless the RTC battery is removed or
completely drained.
NOTE: Implementations should not attempt to clear CMOS by using a jumper to
pull VccRTC low. Clearing CMOS in an ICH6-based platform can be done by
using a jumper on RTCRST# or GPI.
ACZ_SDIN[2:0]
NOTES:
V5REF_Sus
VccRTC
1. Some signals have integrated pull-ups or pull-downs. Consult table in Section 3.1 for
details.
2. Intel High Definition Audio mode is selected through D30:F1:40h, bit 0: AZ/AC97#. This
bit selects the mode of the shared Intel High Definition Audio/AC ‘97 signals. When set to 0
AC ’97 mode is selected. When set to 1 Intel High Definition Audio mode is selected. The bit
defaults to 0 (AC ‘97 mode).
VccUSBPLL
VccDMIPLL
1.5 V supply for core well logic (1 pin). This signal is used for the USB PLL. This
power may be shut off in S3, S4, S5 or G3 states. This signal must be powered
even if USB not used.
1.5 V supply for core well logic (1 pins). This signal is used for the DMI PLL. This
power may be shut off in S3, S4, S5 or G3 states.
VccSATAPLL 1.5 V supply for core well logic (1 pins). This signal is used for the SATA PLL.
This power may be shut off in S3, S4, S5 or G3 states. This signal must be
powered even if SATA not used.
Firmware Hub Interface Signals
Name
Type Description
V_CPU_IO
Powered by the same supply as the processor I/O voltage (3 pins). This supply is
used to drive the processor interface signals listed in Table 2-13.
Grounds (172 pins).
FWH[3:0] /
LAD[3:0]
FWH[4] /
LFRAME#
I/O
O
Firmware Hub Signals. These signals are multiplexed with the LPC
address signals.
Firmware Hub Signals. This signal is multiplexed with the LPC
LFRAME# signal.
Vss
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8050QMA N/B Maintenance
5.2 Intel ICH6-M South Bridge(10)
Functional Strap Definitions 1
Functional Strap Definitions 1 (Continued)
Signal
Usage
When Sampled Description
Signal
Usage
When Sampled Description
GNT[6]#/
GPO[16]
Top-Block Swap Rising Edge of The signal has a weak internal pull-up. If the
EE_DOUT
Reserved
This signal has a weak internal pull-up.
NOTE: This signal should not be pulled low.
Rising Edge of Allows entrance to XOR Chain testing when
Override
PWROK
signal is sampled low, this indicates that the
system is strapped to the “top-block swap” mode
(ICH6 inverts A16 for all cycles targeting FWH
BIOS space). The status of this strap is readable
via the Top Swap bit (Chipset Configuration
Registers:Offset 3414h:bit 0). Note that software
will not be able to clear the Top-Swap bit until
the system is rebooted without GNT6# being
pulled down.
ACZ_SDOU
T
XOR Chain
Entrance / PCI
Express* Port
Configu-ration
bit 1
PWROK
TP[3] pulled low at rising edge of PWROK. See
Chapter 24 for XOR Chain functionality
information.
When TP[3] not pulled low at rising edge of
PWROK, sets bit 1 of RPC.PC (Chipset
Configuration Registers:Offset 224h). See
Section 7.1.30 for details.
LINKALERT
Reserved
This signal requires an external pull-up resistor.
This signal has a weak internal pull-down.
#
ACZ_SYNC PCI Express Por Rising Edge of This signal has a weak internal pull-down.
SPKR
No Reboot
Rising Edge
ofPWROK
The signal has a weak internal pull-down. If the
signal is.sampled high, this indicates that the
system is strapped to.the “No Reboot” mode
(ICH6 will disable the TCO Timer. system
reboot feature). The status of this strap is
readable. via the NO REBOOT bit (Chipset
Configuration. Registers:Offset 3410h:bit 5).
This signal enables integrated VccSus1_5 VRM
when.sampled high.
Configu-ration
bit 0
PWROK
Sets bit 0 of RPC.PC (Chipset Configuration
Registers: Off set 224h). See Section 7.1.30 for
details.
This signal has a weak internal pull-down.
NOTE: This signal should not be pulled high.
This signal has a weak internal pull-up enabled
only when PLTRST# is asserted.
TP[1]
Reserved
Reserved
SATALED#
INTVRMEN IntegratedVccSu
1_5VRM
Always
NOTE: This signal should not be pulled low.
REQ[4:1]#
TP[3]
XOR Chain
Selection
XOR Chain
Entrance
Rising Edge of See Chapter 24 for functionality information.
PWROK
Rising Edge of See Chapter 24 for functionality information.
Enable/Disable
Integrated
Vcc2_5 VRM
Enable/ Disable
GPIO[25]
Rising Edge of This signal enables integrated Vcc2_5 VRM
RSMRST#
when sampled low. This signal has a weak
internal pull-up during RSMRST# and is
disabled within 100 ms after RSMRST#
de-asserts.
PWROK
This signal has a weak internal pull-up.
NOTE: This signal should not be pulled low
unless using XOR Chain testing.
EE_CS
Reserved
This signal has a weak internal pull-down.
NOTE: This signal should not be pulled high.
GNT[5]#/
GPO[17]
Boot BIOS
Destination
Selection
Rising Edge of This signal has a weak internal pull-up. Allows
Real Time Clock Interface
PWROK
for select memory ranges to be forwarded out the
PCI Interface as opposed to the Firmware Hub.
When sampled high, destination is LPC. Also
controllable via Boot BIOS Destination bit
(Chipset Configuration Registers:Offset
3410h:bit 3).
Name
Type Description
RTCX1
Special Crystal Input 1: This signal is connected to the 32.768 kHz crystal.
If no external crystal is used, then RTCX1 can be driven with the
desired clock rate.
RTCX2
Special Crystal Input 2: This signal is connected to the 32.768 kHz crystal.
If no external crystal is used, then RTCX2 should be left floating.
NOTE: This functionality intended for
debug/testing only.
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8050QMA N/B Maintenance
6. System Block Diagram
U711
U7
THRMDA/THRMDC
Clock Generator
ICS954226
Intel CPU
Dothan
FSB
MXM_Connector
LVDS Signal
Flat Panel
U710
North Bridge
915PM
RGB Signal
TV Signal
DVI Connector
TV Connector
200 Pins DDR2 SO-DIMM Socket * 2
MINI PCI Slot
DMI
PCI Bus
Mic-in Connector
U19
U517
USB * 4
Internal Speaker
Headphone
Amplifier
TPA0212
U715
Audio Codec
ALC655
U709
IDE
U722
Card Bus
CB712
CD-ROM
IEEE1394
VT6301T
South Bridge
U18
U724
SATA Bridge
Subwoofer Jack
SUBWOOFER AMP
ICH6-M
J507
PATA HDD
RJ-11 Jack
FAN
LPC BUS
M.D.C
U509
J719
1394 port
Power Switch
CP2211A
Power Button
U717
LAN Controller
RTL8110SBL
PCI-E_LAN
U13
FWH BUS
U505
SMBUS
Keyboard BIOS
Winbond
ADT7460
Touch Pad
Keyboard
U14
System BIOS
PCMCIA
Slot
W83L950D
RJ-45 Jack
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8050QMA N/B Maintenance
7. Maintenance Diagnostics
7.1 Introduction
Each time the computer is turned on, the system BIOS runs a series of internal checks on the hardware. This power-
on self test (post) allows the computer to detect problems as early as the power-on stage. Error messages of post can
alert you to the problems of your computer.
If an error is detected during these tests, you will see an error message displayed on the screen. If the error occurs
before the display is initialized, then the screen cannot display the error message. Error codes or system beeps are
used to identify a post error that occurs when the screen is not available.
The value for the diagnostic port is written at the beginning of the test. Therefore, if the test failed, the user can
determine where the problem occurred by reading the last value written to the port-80H by the debug card plug at
MINI PCI slot.
99
8050QMA N/B Maintenance
7.2 Maintenance Diagnostics
7.2.1 Diagnostic Tool for Mini PCI Slot :
P/N:411906900001
Description: PWA; PWA-MPDOG/MINI PCI DOGKILLER CARD
Note: Order it from MIC/TSSC
100
8050QMA N/B Maintenance
7.3 Error Codes-1
Following is a list of error codes in sequent display on the MINI PCI debug board.
Code
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
POST Routine Description
Some Type of Lone Reset
Turn off FAST A20 for Post
Signal Power On Reset
Initialize the Chipset
Code POST Routine Description
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
Test Keyboard
Test Keyboard Controller
Check if CMOS RAM valid
Test Battery Fail & CMOS X-SUM
Test the DMA Controller
Initialize 8237A Controller
Initialize Int Vectors
Search for ISA Bus VGA Adapter
Reset Counter / Timer 1
User Register Config through CMOS
Size Memory
RAM Quick Sizing
Dispatch to RAM Test
Protected Mode Entered Safely
RAM Test Completed
Check sum the ROM
1Ah
1Bh
1Ch
Reset PIC’s
2Ah
2Bh
2Ch
Protected Mode Exit Successful
Setup Shadow
Initialize Video Adapter(s)
Initialize Video (6845Regs)
Going to Initialize Video
1Dh
1Eh
Initialize Color Adapter
2Dh
2Eh
2Fh
Search for Monochrome Adapter
Search for Color Adapter
Initialize Monochrome Adapter
Sign on Messages Displayed
1Fh
Test 8237A Page Registers
101
8050QMA N/B Maintenance
7.3 Error Codes-2
Following is a list of error codes in sequent display on the MINI PCI debug board.
Code
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
POST Routine Description
Special Init of Keyboard Controller
Test if Keyboard Present
Code POST Routine Description
40h
41h
42h
43h
44h
45h
46h
47h
Configure the COMM and LPT ports
Initialize the Floppies
Test Keyboard Interrupt
Initialize the Hard Disk
Test Keyboard Command Byte
Test, Blank and Count all RAM
Protected Mode Entered Safely(2)
RAM Test Complete
Initialize Option ROMs
OEM’s Init of Power Management
Update NUMLOCK Status
Test for Coprocessor Installed
OEM functions before Boot
Protected Mode Exit Successful
Update Output Port
48h
49h
Dispatch to Operate System Boot
Jump into Bootstrap Code
Setup Cache Controller
3Ah
3Bh
3Ch
Test if 18.2Hz Periodic Working
Test for RTC ticking
Initialize the Hardware Vectors
3Dh
3Eh
Search and Init the Mouse
Update NUMLOCK status
3Fh
Special Init of COMM and LPT Ports
102
8050QMA N/B Maintenance
8. Trouble Shooting
ꢀ 8.1 No Power(*1)
ꢀ 8.2 No Display(*2)
ꢀ 8.3 VGA Controller Test Error LCD No Display
ꢀ 8.4 External Monitor No Display
ꢀ 8.5 Memory Test Error
ꢀ 8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error
ꢀ 8.7 Hard Drive Test Error
ꢀ 8.8 CD-ROM Drive Test Error
ꢀ 8.9 USB Port Test Error
ꢀ 8.10 Audio Test Error
ꢀ 8.11 LAN Test Error
ꢀ 8.12 PC Card Socket Test Error
103
8050QMA N/B Maintenance
*1: No Power Definition
Base on ACPI Spec. We define the no power as while we press the power button, the system can’t leave S5 status
or none the PG signal send out from power supply.
Judge condition:
ꢁ Check whether there are any voltage feedback control to turn off the power.
ꢁ Check whether no CPU power will cause system can’t leave S5 status.
If there are not any diagram match these condition, we should stop analyzing the schematic in power supply sending
out the PG signal. If yes, we should add the effected analysis into no power chapter.
*2: No Display Definition
Base on the digital IC three basic working conditions: working power, reset, Clock. We define the no display as
while system leave S5 status but can’t get into S0 status.
Judge condition:
ꢁ Check which power will cause no display.
ꢁ Check which reset signal will cause no display.
ꢁ Check which Clock signal will cause no display
Base on these three conditions to analyze the schematic and edit the no display chapter.
Keyword:
ꢁ S5: Soft Off
ꢁ S0: Working
For detail please refer the ACPI specification
104
8050QMA N/B Maintenance
8.1 No Power-1
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
Check following parts and signals:
No Power
Main Board
Parts Signals
Parts Signals
Board-level
Troubleshooting
Is the
PJ701
PL1
PF1
PQ501
PD502
U513
U515
Q37
Q50
U11
ADINP
+PWR_VDDIN
+DVMAIN
ADINP
No
notebook connected
to power (either AC adaptor
or battery)?
LEARNING
H8_I_LIMIT
SW_VDD3
AC
Power
Where from
power source problem
(first use AC to
power it)?
LEARNING
I_LIMIT
Connect AC adaptor
or battery.
Yes
Try another known good
battery or AC adapter.
Check following parts and signals:
Parts:
Signals:
No
Replace
Motherboard
Power
OK?
PU3
BATT
BAT_T
BAT_V
BAT_CLK
BAT_DATA
PL507
PF501
PQ506
PD505
PL508
PD507
PQ503
Battery
Yes
Replace the faulty AC
adaptor or battery.
105
8050QMA N/B Maintenance
8.1 No Power-2
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
Main Voltage Map
P22
AMPVDD
P14
L73
JS501~
JS504
PU501,PL502
PR527
L503,U502
L504
P27
P25
P26
L64
L49
PU2
PF501,PL506,PQ503
PU3,PL507,PL508,PD507
P32
+5VS_HDD
+5VS_P
+5V
+5VS
P14
J703
PQ506
BATT
+5VS_CDROM
Charge
Discharge
P6
L39
L37
L35
L44
+2.5VS_CRTDAC
P15
PF1 PL1
PL2
P32
P28
P31
L533
P6
PQ501
PD503
+DVDD
P32
POWER IN
ADINP
+DVMAIN
+2.5VS_TXLVDS
P6
P26
P26
PJ701
Q12
U8
PD502
+2.5VS_HV
+2.5V
+2.5VS
P6
P15
L531
+AVDDL
+2.5VS_ALVDS
P32
Discharge
PD505
U504,L509
L501
PU502,PL503
PR508
JS505~
JS507
P14
P26
PWR_VDDIN
P26
P27
P25
L562
U9
+1.8VS_HDD
+1.8VS
+3VS_P
+3V
+3VS
P14
+3VS_HDD
P19
P14
F4,U513
L563
L531
L564
+3VS_HDD_ANALOG
+1394_AVCC
L31
L32
P9
PF502,PL512
PL506,PU5
PU503,PU504
PU506,PU511
PU512
P26
P26
P26
P26
P26
+3VS_CLK
Q37
U515
Q49
U11
+VDD5
+VDD3_AVREF
+VDD3
+VDD3S
+VDD1.5
L40,L33
L41
P6
R711
P30
P23
+3VS_TVDAC[A,B,C]
P11
D34,
+CPU_CORE
+KBC_CPUCORE
Q50
P6
L42
+VDD3_RTC
+3VS_ATVBG
P26
+3V
PR42
PU12
JS6,
JS515
PU509,PU510
PL516
R606
R242
P29
P25
P8
+1.8V_P
+1.8V
+DDR2_VREF
JS517~
JS518
P29
P25
+0.9VS_P
+0.9VS
106
8050QMA N/B Maintenance
8.1 No Power-3
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
Main Voltage Map
JS508~
JS510
P28
P25
P6
PU507,PL514
L50
+1.05VS_P
+VCCP
+VCC_GMCH
P6
L34
+1.5VS_DPLLA
P28
PL514,PL515
PU6
P6
L46
+DVMAIN
+1.5VS_DPLLB
P6
L519
L518
L51
+1.5VS_HPLL
P6
+1.5VS_MPLL
JS511~
JS513
P28
P6
P25
PU508,PL515
+1.5VS_3GPLL
+1.5VS_P
+1.5VS
P6
L43
+1.5VS_QTVDAC
P6
L38
+1.5VS_DLVDS
P6
L63
+1.5VS_DDRDLL
P6
L516
L36
+1.5VS_PCIE
P6
+1.5VS_TVDAC
NOTE :
: Page 25 on M/B Board circuit diagram.
P25
107
8050QMA N/B Maintenance
8.1 No Power-4
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
A
K
+PWR_VDDIN
PL1
120Z/100M
JO502
OPEN-SMT4
PD502
PQ501
ADINP
SCS140P
PD505
SCS140P
AQ4407
PF1
7A/24VDC
PL2
120Z/100M
PR501
.01
8
7
6
5
P31
PJ701
3
2
1
A
K
1
+DVMAIN
POWER IN
2~4
PC528
0.01µ
PC532
1000P
PD504
SBM1040
PC520
0.01µ
PR506
4.7K
PC2
0.01U
PC501
1U
PC502
0.01U
PD501 PR502
RLZ24D 470K
JO2,JO1
SPARKGAP_6
PR503
100K
P23
PU1
U13
4
5
6
3
VCC
RS+
PQ502
2N7002
P31
1
2
Keyboard
BIOS
RS-
GND0
GND1
PC1
0.01U
LEARNING
23
LEARNING
OUT
PR505
1M
PR1
10
MAX4173FEUT-T
I_LIMIT
H8_I_LIMIT
SW_VDD3
76
17
W83L950D
PC3
1U
U515
AMS3107
U513
NTC78L05
+VDD3_AVREF
+VDD3
+VDD5
Q37
AO3413
Q50
AO3413
1
3
3
1
D
S
S
D
INPUT
OUTPUT
+PWR_VDDIN
IN
OUT
P26
P26
+3V
F4
C689
10µ
C767
C327
0.1µ
C389
4.7µ
R397
100K
C324
10µ
2,4
2
3216FF-1
1µ
R340
0
+PWR_VDDIN ꢀ +VDD3
SW_VDD3
Q47
DDTC144WCA
+3Vꢀ +VDD3
108
8050QMA N/B Maintenance
8.1 No Power-5
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
Charge
PQ503
AO4407
PL506
BEAD_120Z/100M
PL508
33µH
PL507
3.0µH
PF501
TR/3216FF-3A
PD507
SSA34
8
7
6
5
3
2
1
BATT
12.65V
ADINP
PR135
2M
P32
PC524
0.01µ
PC525
0.01µ
PC533
10µ
PR45
4.7K
PR46
4.7K
PC534
10µ
PC536
0.01µ
PC535
10µ
PD509
BZV55C15V
PC17
0.1µ
PR27
20K
PD506
SSA34
PJOL1
OPEN-SMT4
PR47
0
PR59
100K
PQ11
MMBT2222A
2IN+
PR136
976K
PR24
13.7K
PR28
287K
PD4
BAS32L
PJOH1
OPEN-SMT4
PQ7
DTA144WK
H8_I_CTRL
P23
PR26
0
From U13
D
S
PQ8
2N7002
CHARGING
G
PQ5
2N7002
CHARGING
8,11
From H8 U13 P23
PC29
0.01µ
C1,C2
2IN+
12
16
2
P32
P23
PR25
124K
From H8 U510
VCC
2IN+
1IN-
13
PU3
OUTPUTCTRL
5
6
PC18
0.01µ
CT
RT
PR12
2.49K
PWM
3
4
FEEDBACK
DTC
TL594C
PJS1
SHORT-SMT3
14
REF
PC21
1000P
PR34
7.5K
+VDD3
+DVMAIN +VDD3
2IN-
15
PC23
0.1µ
PR37
100K
PR35
10K
PC22
0.01µ
BATT_DEAD# P23
PC33
0.01µ
PR36
590K
PR38
1K
GND
To H8 U13
PC30
1µ
1.25V
5
+
BATT_DEAD
7
REF
Q43
DDTC144TCA
PR32
100K
6
_
PU4B
LMV393M
PC25
0.1µ
PC24
0.1µ
PR33
80.6K
PQ6
SCK431CSK-5
PR11
.02
GNDB
GND
109
8050QMA N/B Maintenance
8.1 No Power-6
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
Discharge
Q49
SI2301DS
+VDD3S
+VDD3
BATT
+DVMAIN
S
D
PQ506
AO4407
PC527
0.01µ
PC526
1000P
L81
120Z/100M
+VDD3
8
7
6
5
R378
100K
3
2
1
PD505
SCS140P
RP502
10K
PR512
100K
D20
BAS32L
A
K
ADEN#
+PWR_VDDIN
4
R1
Q40
DDTC144TCA
PR509
226K
PR511
33K
PQ507
DTC144WCA
ADINP
12
14
KBC_PWRON_VDD3S
ADEN#
J703
PC617
1000P
PQ504
2N7002
PL504
120Z/100M
PF701
TR/SFT-10A
PL505
120Z/100M
P31
1,2
+VDD3_AVREF
P23
PC523
0.01µ
PC514
0.01µ
+VDD3_AVREF
U13
PR510
499K
RP4
22*4
D16
BAV70LT1
PR134
4.99K
BAT_T
77
7
8
2
1
5
BAT_V
78
PR8
20K
PC10
0.1µ
Keyboard
BIOS
C332
0.1µ
C333
0.1µ
PC19
0.1µ
PR29
100K
+VDD3
+VDD3
+VDD3
1
1
PD3
PD2
BAV99
W83L950D
BAV99
R385
2.7K
R344
2.7K
PR13
0
BAT_CLK
BAT_C
BAT_D
6
5
3
4
2
3
3
4
BAT_DATA
PR14
0
JO10
JP1
SPARKGAP-6
SPARKGAP-6
110
8050QMA N/B Maintenance
8.1 No Power-7
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
Power Controller
+VDD3
U726
AHC1G08DCK
+DVMAIN
+5VS_P
+3VS_P
P27
18
2
PU2
LTC3728L
H8_PWRON
H8_PWRON
4
+KBC_CPUCORE
+VDD3_AVREF
+VDD3
H8_RESET#
1
P23
C325
10µ
H8_PWRON
P29
+1.8V_P
C326
22P
PU12
SC486
+DVMAIN
29
28
KBC_X-
+0.9VS_P
R328
1M
X2
8MHz
R12
1K
PWRBTN#
1
KBC_X+
+VDD3
U13
+DVMAIN
C330
22P
C7
1000P
+1.5VS_P
P28
PU6
ISL6227
SW2
PWRON_SUSB1#
1
2
TCD010-PSS11CET
+1.05VS_P
U6A
74AHC14_V
Keyboard
BIOS
+VDD3S
+VDD3
+VDD3
+VDD3
R358
10K
+DVMAIN
R435
10K
P30
PU5
+CPU_CORE
H8_RESET#
25
5
H8_PWRON_SUSB#
PWRON_SUSB#
PWRON_SUSB2#
3
4
5
6
MN
RESET
W83L950D
P26
ISL6218
C388
0.01µ
U6B
74AHC14_V
R396
100K
U21
U6C
74AHC14_V
IMP811
VCC
GND
+VDD3
+2.5V
P26
Q12
+2.5VS
+3V
PWRON_SUSB3#
9
8
P26
R69
0
U504
AO3413
R347
0
P11 U709
South
+3VS
+5VS
PWRON_SUSB6#
U6D
74AHC14_V
ICH_PWRBTN
7
ICH_PWRBTN#
AO4419
RSMRST#
Q45
FDV301N
D
+VDD3
Bridge
ICH6-M
+DVMAIN
+5V
P26
U502
R43
0
+1.8V_P
H8_RSMRST
8
G
P29
PU12
SC486
PWRON_SUSB5#
S
PWRON_SUSB4#
10
AO4419
11
+0.9VS_P
U6E
74AHC14_V
111
8050QMA N/B Maintenance
8.2 No Display-1
There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good.
No Display
Monitor
or LCD module
OK?
No
Replace monitor
or LCD.
Board-level
Troubleshooting
Yes
Make sure that CPU module,
DIMM memory are installed
Properly.
Refer to port 378H
error code description
section to find out
which part is causing
the problem.
System
BIOS writes
error code to port
378H?
Yes
Yes
Display
OK?
Correct it.
No
No
Replace
Motherboard
1.Try another known good CPU module,
DIMM module and BIOS.
2.Remove all of I/O device ( HDD,
CD-ROM…….) from motherboard
except LCD or monitor.
Check system clock,
reset circuit and
reference power
1. Replace faulty part.
Yes
Display
2. Connect the I/O device to the M/B
one at a time to find out which part
is causing the problem.
OK?
To be continued
Clock,reset and power checking
No
112
8050QMA N/B Maintenance
8.2 No Display-2
****** System Clock Check ******
L31
120Z/100M
+3VS
+3VS
+VDD3S
+3VS_CLK
+3VS
L32
C80
C78
2.2µ
R206
2.2K
R207
2.2K
120Z/100M
2.2µ
Q14
2N7002
R76
10K
R103
10K
R142
10K
R144
10K
To J714,J713
G
P8
SMB_DATA
SMB_CLK
47 SMBDATA
S
D
G
DREFCLK
14
15
R101
33
33
33
Q13
2N7002
46 SMBCLK
S
D
DREFCLK#
P11
R100
PCICLK_ICH
CLK_USB48
P4
8
DREFSSCLK
R93
R80
33
17
18
31
30
R99
DREFSSCLK#
R87
33
33
12
52
33
U710
CLK_GMCH
CLK_GMCH#
HCLK_MCH
HCLK_MCH#
R111
R113
R125
R124
U709
R131
12.1
14M_ICH
33
33
33
CLK_PCI_STOP#
CLK_CPU_STOP#
STOP_PCI#
55
54
P9
41
40
North Bridge
GMCH
STOP_CPU#
South Bridge
ICH6-M
24
CLK_ICH
R98
R97
33
33
U7
CLK_ICH#
CFG1
FS_B
FS_C
16
53
25
26
R71
R72
1K
1K
CFG2
CLK_SATA
CLK_SATA#
R96
R95
33
33
27
Clock
Generator
CLK_ITP_CPU
36
35
44
43
R123
R122
R127
R126
33
33
33
33
P2
CLK_ITP_CPU#
HCLK_CPU
U711
ICS954226
CPU
HCLK_CPU#
HBSEL0
P18
U715
CB712
PCICLK_CARD
5
R94
33
DOTHAN
C97
56P
HBSEL1
49
FS_C
FS_B
FS_A
H
BCLK Frequency
100 MHz (Default)
133 MHz
R104
33
P15
U717
X1
14.318MHz
28
31
70
PCICLK_LAN
4
3
H
L
L
L
RTL8100CL
C98
56P
H
50
9
R105
33
J716
P24
U14
PCICLK_FWH
PCICLK_KBC
SST49LF004A
R92
33
PCICLK_MINIPCI
R710
0
25
P20
R114
33
39
R136
475
P23
U13
56
W83L950D
113
8050QMA N/B Maintenance
8.2 No Display-3
****** Power Good & Reset Circuit Check ******
+3VS
CARD_GRST#
PCI_PCIRST#
P18
U715
+3VS
JL22
JP_NET10
Card Bus
CB712
PCIRST#
9
10
8
R548
22
14
From PU5
VRMPWRGD
12
13
ICH_VGATE
P30
11
U10D
U10C
74AHC08_V
JL23
JP_NET10
P15
7
U717
LAN_PCIRST#
27
74AHC08_V
P9
LAN Controller
JL25
JP_NET10
MINIPCI_PCIRST#
26
J716
P20
P26
2
PWROK
RESET
U20
+3VS
MINI-PCI Slot
R392
10K
MAX809
VCC
3
U709
JL21
JP_NET10
JL26
JP_NET10
GND
1
C374
0.1µ
GMCH_RST#
LAN_RST#
PLT_RST#
To North Bridge U710
+3VS
South
P24
U14
JL20
JP_NET10
System
BIOS
FWH_PCIRST#
2
4
5
6
Bridge
PWROK
P4 U710
North Bridge
Intel 915PM
U10B
74AHC08_V
JL17
J723
MXM
Connector
JP_NET10
MXM_RST#
+3VS
ICH6-M
P5
+VCCP
U10A
74AHC08_V
JL19
R319
0
P2
JP_NET10
P23
KBC_PCIRST#
U711
CPU
64
HCPURST#
U13
1
2
3
R169
200
W83L950D
HPWRGD
JL18
JP_NET10
Dothan
P14
17
IDE_RST#
U724
88SA8040
J507
MDC
25
P21
+5VS
P21
U517
+5VS
J710
CDROM
Connector
R311
10K
ACRST#
11
Audio Codec
ALC655
R293
10K
Q18
RSTDRV#
5
P14
DDTC144TCA
Q17
DDTC144TCA
114
8050QMA N/B Maintenance
8.3 VGA Controller Test Error LCD No Display-1
There is no display or picture abnormal on LCD although power-on-self-test is passed.
VGA Controller Failure
LCD No Display
Check if
Yes
1. Confirm LCD panel or monitor is good
J1, J2 are cold
Re-soldering.
and check the cable are connected
solder?
properly.
Board-level
2. Try another known good monitor or
Troubleshooting
LCD module.
No
One of the following parts on the mother-board may be
defective, use an oscilloscope to check the following signal or
replace the parts one at a time and test after each replacement.
Yes
Replace faulty
LCD or monitor.
Display
OK?
No
Main Board
Daughter Board
Replace
Motherboard
Parts
Signals
Parts
Signals
Remove all the I/O device & cable from
motherboard except LCD panel or
extended monitor.
U710
U709
U13
J506
J1
+3VS
ENABKL
BLADJ
L10~L13
SW1
R3
C1
R1
LVDS_TX[0..2]+
LVDS_TX[0..2]-
LVDS_CLK+
LVDS_CLK-
LVDS_ENBKL
H8_ENABKL
COVER_SW
J2
J723
Connect the I/O device & cable to
the M/B one at a time to find out
which part is causing the problem.
Yes
Display
OK?
No
115
8050QMA N/B Maintenance
8.3 VGA Controller Test Error LCD No Display-2
There is no display or picture abnormal on LCD although power-on-self-test is passed.
Q4
AO4419
F1
2A
L19
120Z/100M
J2
8
7
6
5
3
2
1
+3VS
1,2
R28
0
S
LVDS_ENVDD
D
C10
1µ
C15
0.22µ
R31
1M
R33
10K
P5
G
From J723
P5
Q5
2N7002
P5
J723
P10
MXM_Connector
IGP_LVDS_CLK
IGP_LVDS_CLK#
IGP_EDID_CLK
IGP_EDID_DATA
IGP_LVDS_TX2
IGP_LVDS_TX2#
IGP_LVDS_TX1
IGP_LVDS_TX1#
LVDS_ENBKL
LVDS_CLK
LVDS_CLK#
EDID_CLK
EDID_DATA
LVDS_TX2
LVDS_TX2#
LVDS_TX1
LVDS_TX1#
13
15
19
21
25
27
U710
North Bridge
Intel 915PM
20
22
LCD
+3VS
+3VS
+3VS
+3VS
R15
20K
R14
20K
R13
20K
R25
20K
P9
PANEL_ID0
PANEL_ID1
PANEL_ID2
PANEL_ID3
17
19
20
U709
South Bridge
ICH6-M
+3VS
Inverter Board
J1
L22
130Z/100M
LVDS_ENBKL
1
2
ENABKL_VGA
3
4
L21
130Z/100M
R3
0
P10
H8_ENABKL
80
11
P23
U13
L23
120Z/100M
BLADJ
+VDD3S
9
+3V
L25
120Z/100M
Keyboard BIOS
W83L950D
SW1
30V/0.1A
+DVMAIN
R1
R511
1K
1,2
470K
16 H8_LIDSW#
C13
0.1µ
C11
1000P
C12
0.1µ
C22
0.01µ
C1
0.1µ
Cover Switch
116
8050QMA N/B Maintenance
8.4 External Monitor No Display-1
There is no display or picture abnormal on CRT monitor, but it is OK for LCD.
External Monitor No Display
1. Confirm monitor is good and check
the cable are connected properly.
Check if
J702
are cold solder?
Yes
Re-soldering.
Board-level
Troubleshooting
2. Try another known good monitor.
No
Yes
Display
OK?
One of the following parts on the mother-board may be
defective, use an oscilloscope to check the following signal or
replace the parts one at a time and test after each replacement.
Replace faulty monitor.
No
Parts:
Signals:
Replace
Motherboard
Remove all the I/O device & cable from
motherboard except monitor.
U710
U2
J702
J723
L11
L2
+3VS
CRT_DDDA
CRT_HSYNC
CRT_VSYNC
CRT_DDCK
CRT_RED
L10
L30
Connect the I/O device & cable
CRT_GREEN
CRG_BLUE
Yes
to the M/B one at a time to find
out which part is causing the
problem.
Display
OK?
No
117
8050QMA N/B Maintenance
8.4 External Monitor No Display-2
There is no display or picture abnormal on CRT monitor, but it is OK for LCD.
+DVMAIN
J723
L30
120Z/100M
MXM_Connector
J702
+3VS
L568
R216
130Z/100M
0
P5
IGP_CRT_DDDA
218
220
141
139
CON_DDDA
CON_DDCK
12
15
P10
DVI_DDDA
DVI_DDCK
CRT_VSYNC
CRT_HSYNC
L569
130Z/100M
R219
0
IGP_CRT_DDCK
IGP_CRT_VSYNC
8
L15
130Z/100M
VCC
CON_VSYNC
CON_HSYNC
14
13
2
5
6
3
1A
2A
1Y
2Y
L14
130Z/100M
IGP_CRT_HSYNC
P10
U710
JO50
JO48
U2
CP1
47P*4
SN74LVC2G125
JO47
JO49
North Bridge
Intel 915PM
GMCH
L2
1
IGP_CRT_RED
IGP_CRT_GREEN
IGP_CRT_BLUE
136 CRT_RED
CON_RED
130OHM/100M
L11
2
3
CRT_GREEN
CRT_BLUE
130OHM/100M
140
144
CON_GREEN
CON_BLUE
L10
130OHM/100M
JO53
JO52
JO51
118
8050QMA N/B Maintenance
8.5 Memory Test Error-1
Extend DDRAM is failure or system hangs up.
Memory Test Error
1. Check if on board SDRAM chips are no cold
solder.
2. Check the extend SDRAM module is installed
properly. ( J713,J714)
3. Confirm the SDRAM socket (J713,J714) is
ok,no band pins.
One of the following components or signals on the motherboard
may be defective ,Use an oscilloscope to check the signals or
replace the parts one at a time and test after each replacement.
Board-level
Troubleshooting
Parts:
Signals:
+1.8V
+3VS
S[A..B]_MA[0..13]
CKE#[0..3]
CS#[0..3]
SMBDATA
SMBCLK
NB_CLK _DDR[0,1,3,4]
NB_CLK _DDR[0,1,3,4]#
U710
U7
Yes
Test
OK?
J713
J714
R691
R692
R606
R242
C285
C604
Correct it.
ODT[0..3]
No
S[A..B]_BS#[0..2]
S[A..B]_CAS#
S[A..B]_RAS#
S[A..B]_WE#
S[A..B]_DQS#[0..7]
S[A..B]_DQS[0..7]
S[A..B]_DM[0..7]
S[A..B]_DQ[0..63]
If your system host bus clock running at
266MHZ then make sure that SO-DIMM
module meet require of PC 266.
Replace
Motherboard
Yes
Test
OK?
Replace the faulty
DDRAM module.
No
119
8050QMA N/B Maintenance
8.5 Memory Test Error-2
Extend DDRAM is failure or system hangs up.
+0.9VS
R243,R263….
56
J713
SA_BS#[0..2], SA_CAS#, SA_RAS#, SA_WE#
S[A..B]_BS#[0..2], S[A..B]_CAS#, S[A..B]_RAS#, S[A..B]_WE#
P8
SA_MA[0..13], CKE#[0..1], CS#[0..1], ODT[0..1]
SA_DQS#[0..7], SA_DQS[0..7]
S[A..B]_A[0..13], CKE#[0..3], CS#[0..3], ODT[0..3]
S[A..B]_DQS#[0..7], S[A..B]_DQS[0..7]
SA_DM[0..7], SA_DQ[0..63]
S[A..B]_DM[0..7], S[A..B]_DQ[0..63]
NB_CLK_DDR[0,1], NB_CLK_DDR[0,1]#
NB_CLK_DDR[0,1,3,4], NB_CLK_DDR[0,1,3,4]#
SMBDATA
SMBCLK
P4
P7
+1.8V
U710
+DDR2_VREF
R606
75
+3VS
R242
75
C285
0.1µ
C604
2.2µ
C304
0.1µ
C295
2.2µ
North Bridge
R692
10K
R691
10K
U7
P9
47
46
SMBDATA
SMBCLK
Clock
J714
Generator
915PM
GMCH
ICS954226
P8
SMBCLK
SMBDATA
SB_BS#[0..2], SB_CAS#, SB_RAS#, SB_WE#
SB_MA[0..13], CKE#[2..3], CS#[2..3], ODT[2..3]
SB_DQS#[0..7], SB_DQS[0..7]
SB_DM[0..7], SB_DQ[0..63]
NB_CLK_DDR[3,4], NB_CLK_DDR[3,4]#
120
8050QMA N/B Maintenance
8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error-1
Error message of keyboard or touch-pad failure is shown or any key does not work.
Keyboard or Touch-Pad
Test Error
Check
J4, J5
Yes
Re-soldering.
Board-level
Troubleshooting
for cold solder?
Is K/B or T/P
cable connected to notebook
properly?
No
Correct it.
No
One of the following parts or signals on the motherboard
may be defective, use an oscilloscope to check the signals
or replace the parts one at a time and test after each
replacement.
Yes
Replace
Motherboard
Try another known good Keyboard
or Touch-pad.
Parts
Signals
U13
U14
U709
X2
SW3
SW4
F2
+3VS
+VDD3
Yes
+KBC_CPUCORE
KI[0..7]
Replace the faulty
Keyboard or Touch-Pad.
Test
Ok?
KO[0..15]
T_CLK
No
T_DATA
J4
J5
L48
121
8050QMA N/B Maintenance
8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error-2
Error message of keyboard or touch-pad failure is shown or any key does not work.
+3VS
74
71
+KBC_CPUCORE
+VDD3
Internal
Keyboard Connector
R146
10K
J4
55~62
39~54
17~24
KI[0..7]
+3VS
P23
KO[0..15]
1~16
25
R704
10K
P11
U709
69
SERIRQ
KBD_US/JP#
P23
KBD_US/JP#
South Bridge
ICH6-M
LFRAME#
LAD[0..3]
U13
+5V
+5VS
F2
L48
J5
R168
0
0.5A/POLYSW 120Z/100MHZ
1,2
Keyboard
BIOS
+5V
R348
10K
R346
10K
13~15,17
LAD[0..3]
65~68
63
P24
P24
L47
130Z/100M TP_CLK
TP_DATA
130Z/100M
6
9
T_CLK
11,12
9,10
T_DATA
L72
23
LFRAME#
W83L950D
SW3
25,27
32,1
SW_LEFT
7,8
5,6
1
3
2
4
5
U14
+3VS
SW_RIGHT
C709
4.7µ
C694
0.1µ
R315
R317
4.7K
4.7K
8
7
SYSTEM
BIOS
C540
47P
C539
47P
C542
47P
C541
47P
C537
0.1µ
28
SW4
R328
1M
1
3
2
4
5
SST49LF004A
29
Touch-Pad
X2
8MHZ
C330
22P
C326
22P
122
8050QMA N/B Maintenance
8.7 Hard Disk Drive Test Error-1
Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing
data to hard disk.
Hard Disk Drive
Test Error
1. Check if BIOS setup is OK?.
2. Try another working drive.
Board-level
Troubleshooting
One of the following parts or signals on the motherboard may
be defective, use an oscilloscope to check the signals or replace
the parts one at a time and test after each replacement.
Yes
Re-boot
OK?
Replace the faulty parts.
Parts:
Signals:
+5VS
U709
U724
J715
X4
L64
D26
C294
C303
C309
C575
C577
C580
C582
No
+5VS_HDD
SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0
DDRQ
DIORDY
DIRQ
DD[0..15]
DA[0..2]
DCS[0..1]#
Replace
Motherboard
Check the system driver for proper
installation.
Yes
Re - Test
OK?
End
No
123
8050QMA N/B Maintenance
8.7 Hard Disk Drive Test Error-2
Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing
data to hard disk.
+5VS_HDD
J715
3,4
+5VS
L64
120Z/100MHZ
C309
0.1µ
C303
0.1µ
C294
22µ
P14
D26
CL-190G
R439
470
R422
0
HDD_LED#
6
+5VS
+3VS
44
+3VS_HDD
P11
41,56
R817
5.6K
R818
4.7K
R819
8.2K
+1.8VS_HDD
60
DDRQ
DIORDY
DIRQ
24
18
C575
3900P
P14
SATA_RXN
31
32
28
27
SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0
55
U709
C577
3900P
53
14
SATA_RXP
SATA_TXN
SATA_TXP
South Bridge
ICH6-M
1~3,5~7…
49~51
47,48
54,58,59,16
DD[0..15]
DA[0..2]
27~42
9,10,12
7,8
C580
3900P
U724
C582
3900P
DCS[0..1]#
88SA8040
DACK#,DIOR#,DIOW#,DRST# 16,20,22,44
23
22
R824
10k
R225
1M
11
R825
470
17
X4
25MHZ
C126
12P
C125
12P
124
8050QMA N/B Maintenance
8.8 CD-ROM Drive Test Error-1
An error message is shown when reading data from CD-ROM drive.
CD-ROM Driver
Test Error
Board-level
Troubleshooting
1. Try another known good compact disk.
2. Check install for correctly.
One of the following parts or signals on the motherboard may
be defective, use an oscilloscope to check the signals or replace
the parts one at a time and test after each replacement.
Yes
Test
OK?
Parts:
Signals:
Replace the faulty parts.
+5VS
U709
J710
L49
+5VS_CDROM
SD_D[0..15]
SDA1
No
D27
IDEIRQ
SDDACK#
SIORDY
SDIOW#
SDDREQ
SDIOR#
SDA0
SDCS1#
SDCS3#
SDA2
Replace
Motherboard
C198
C208
C209
R198
R414
R441
R558
Check the CD-ROM drive for
proper installation.
Yes
Re - Test
End
OK?
No
125
8050QMA N/B Maintenance
8.8 CD-ROM Drive Test Error-2
An error message is shown when reading data from CD-ROM drive.
D27
CL-190G
J710
R441
470
R414
0
CD_LED#
37
+5VS
+5VS
+5VS_CDROM
38~42
P14
L49
120Z/100MHZ
C208
0.1µ
C209
0.1µ
C198
10µ
SD_D[0..15]
SD_D[0..15]
6~21
+3VS
+3VS
P11
RSTDRV#
Refer Section 8.2(No display-3)
R198
8.2K
R558
4.7K
RSTDRV#
5
SDA1
SDA1
31
29
28
27
U709
IDEIRQ
IDEIRQ
SDDACK#
SIORDY
SDDACK#
SIORDY
South Bridge
SDIOW#
SDDREQ
SDIOR#
SDIOW#
SDDREQ
SDIOR#
25
22
24
ICH6-M
SDA0
SDA0
33
35
36
34
SDCS1S#
SDCS3S#
SDA2
SDCS1#
SDCS3#
SDA2
126
8050QMA N/B Maintenance
8.9 USB Test Error-1
An error occurs when a USB I/O device is installed.
USB Test Error
Check if the USB device is installed
properly.
Check the following parts for cold solder or one of the following
parts on the mother-board may be defective, use an oscilloscope
to check the following signal or replace the parts one at a time
and test after each replacement.
Board-level
Troubleshooting
Yes
Test
OK?
Correct it.
No
Parts:
Signals:
U709
U501
U503
J701
J706
L5
L6
L10
L13
USB_OC0#
USB_OC1#
USBP[0..3]+
USBP[0..3]-
+VCC_USB_0
+VCC_USB_1
+VCC_USB_2
+VCC_USB_3
+5V
Replace another known good USB
device.
Replace
Motherboard
Yes
Re-test
OK?
Correct it.
F503
F504
C2
No
SW_VDD3
C501
127
8050QMA N/B Maintenance
8.9 USB Test Error-2
An error occurs when a USB I/O device is installed.
U501
RT9701-CB
L502
120Z/100M
+5V
3
4
1,5
2
VIN
VOUT0,1
R791
22
C503
0.1µ
P14
SW_VDD3
From U13
CE
R502
33K
GND
P23
USB_OC0#
C504
150µ
F503
1.1A
C172
1µ
C505
1000P
R503
47K
J701
+VCC_USB_0
1
3
R179
0
L5
90Z/100M
P11
P14
USBP0+
3
2
1
R180
0
USBP0-
4
2
L501
120Z/100M
+VCC_USB_1 A1
R192
0
L6
90Z/100M
USBP1-
USBP1+
A2
4
3
1
2
R186
0
A3
C502
0.1µ
U709
U503
RT9701-CB
L1
120Z/100M
+5V
3
1,5
2
VIN
VOUT0,1
R792
22
South Bridge
ICH6-M
C4
0.1µ
4
P14
SW_VDD3
From U13
CE
R10
33K
GND
P23
USB_OC1#
C2
150µ
F504
1.1A
C178
1µ
C163
1000P
R159
47K
J706
+VCC_USB_2
1
3
R191
L10
P14
0
90Z/100M
USBP2+
USBP2-
2
3
4
R190
0
1
2
L552
120Z/100M
+VCC_USB_3 A1
R786
0
L13
90Z/100M
USBP3-
USBP3+
A2
1
2
4
3
R787
0
A3
C769
0.1µ
128
8050QMA N/B Maintenance
8.10 Audio Test Error-1
No sound from speaker after audio driver is installed.
Audio Failure
1. Check if speaker cables are
connected properly.
2. Make sure all the drivers are
installed properly.
Board-level
Troubleshooting
Check the following parts for cold solder or one of the following parts on the
motherboard may be defective,use an oscilloscope to check the following signal
or replace parts one at a time and test after each replacement.
1.If no sound cause
of line out, check
the following
2. If no sound cause
of MIC, check
the following
3. If no sound cause
of CD-ROM, check
the following
Yes
Test
OK?
Correct it.
parts & signals:
parts & signals:
parts & signals:
No
Parts:
Signals:
Parts:
Signals:
Parts:
Signals:
Try another known good
speaker, CD-ROM.
U517
U19
U709
J509
J7
AMP_RIGHT
AMP_LEFT
DEVICE_DECT
DECT_HP#OPT
SPDIFOUT
SPK_OFF
U517
U709
U16
+5VS
+3VS
+VA
MIC_VREF
MIC1
U709
U517
J710
R420
R407
R438
R419
R406
R434
CDROM_LEFT
CDROM_RIGHT
CDROM_COMM
Replace
Motherboard
U17
MIC1
J720
J721
L71
L74
D4
L554
L543
L548
J3
MIC2
MIC_EXT
L60
L61
Q48
L20
L18
L73
Q510
EAPD
OPTIN#
Yes
Re-test
OK?
Correct it.
No
129
8050QMA N/B Maintenance
8.10 Audio Test Error-2 (Audio In)
No sound from speaker after audio driver is installed.
MIC1
L62
1
2
P21
R405
0
BEAD_600Z/100M
+
-
1,9
28
MIC_VREF
DVDD1,2
+3VS
L520
BEAD_600Z/100M
C578
0.1µ
C581
10µ
C741
0.1µ
C751
1µ
R412
5.6K
JO517
R784
4.7K
P21
AGND
J720
L543
5
4
BEAD_600Z/100M
U17
RT9167-47CB
+5VS
AGND
+VA
L71
120Z/100M
R783
0
3
6
R785
0
C764
1µ
5
4
25,38
1
2
3
MIC_EXT
MIC
VIN
OUT
21 MIC1
AVDD1,2
2
GND
3
2
4
1
P19
C755
0.1µ
C351
10µ
C725
0.1µ
ADJ
CE
1
L554
BEAD_600Z/100M
C757
1µ
C364
0.01µ
L548
22
MIC2
P21
120OHM/100MHZ
AGND
AGND
External MIC
JO518
CAGND
R420
SPDIFOUT
48
20
18
19
J710
C380
1µ
CAGND
ACSDIN0
R391
22
8
5
To next page
6.8K
P11
CDROM_RIGHT
CDROM_LEFT
CDROM_COMM
2
ACSDOUT
ACSYNC
ACRST#
220
R407
6.8K
C377
1µ
P14
1
U517
CDROM
10
11
6
U709
R438
0
C385
0.22µ
Connector
3
R419
6.8K
R406
6.8K
R434
0
Audio Codec
ALC655
ACBITCLK
L74
R390
22
South Bridge
ICH6-M
SPK_OFF
AGND
R436
0
C763
1µ
L79
J721
BEAD_600Z/100M
To next page
23
24
LINE_IN/L
LINE_IN/R
2
R417
0
L78
C756
1µ
D31
BAV70LT1
2
P21
BEAD_600Z/100M
Line In Jack
3,5
SBSPKR
3
R418
22K
R437
22K
1
C381
100P
C378
J10
J9
100P
+VA
R337
47K
C339
0.1µ
KBC_DEEP
CAGNDCAGNDCAGNDCAGND
To next page
AGND
R758
0
R756
0
P23
U16
NC7S32
From U13
AOUT_R
AOUT_L
36
35
AMP_RIGHT
AMP_LEFT
R767
0
R771
0
5
1
VCC
C335
1µ
A
B
R205
0
R336
10K
CARDSPK
P21
2
U715
P18
4
12
PC_BEEP
Y
31
32
C748
C746
1µ
1µ
R338
47K
C334
100P
R335
1K
PC14510GHK
AGND
130
8050QMA N/B Maintenance
8.10 Audio Test Error-3 (Audio Out)
No sound from speaker after audio driver is installed.
+5VS
+AMPVDD
L73
19
J7
P22
VDD
120Z/100M
R61
R60
BEAD_600Z/100M
BEAD_600Z/100M
21
16
1
2
ROUT+
ROUT-
7,18
Internal Speaker
Connector
PVDD0/PVDD1
R
C342
100µ
C734
0.1µ
C735
0.1µ
J3 P22
Internal Speaker
R18
R20
BEAD_600Z/100M
BEAD_600Z/100M
4
9
1
2
LOUT+
LOUT-
L
Connector
P22
AGND
+VA
C356
1µ
C341
100µ
C354
100µ
AMP_RIGHT
20
23
RHPIN
P22
J509
R381
4.7K
R775
10K
L547
From previous page
BEAD_600Z/100M
RLINEIN
5
C347
1µ
L83
R404
22
L546
0
BEAD_600Z/100M
4
3
AGND
U19
+5VS
+5VS
2
DECT_HP#OPT
L77
BEAD_600Z/100M 1
R365
1.3M
R379
L76
R343
1K
C345
100P
R380
1K
C365
100P
R729
4.7K
22 BEAD_600Z/100M
D514
BAW56
2
Audio
L539
BEAD_600Z/100M
From previous page
SPDIFOUT
LED
Q31
DDTC144TCA
SPK_OFF# 22
7
8
9
3
Amplifier
R73
0
Drive
IC
OPTIN#
1
+VA
AGND
SPK_OFF
R1
R400
10K
L538
BEAD
600Z/100M
From previous page
R208
1K
DEVICE_DECT
15,17
TPA0212
DEVICE_DECT#
AGND
LINE OUT
Q48
DDTC144TCA
GND
GND
Q509
+3VS
AM2301P
D
S
C360
1µ
AMP_LEFT
R754
10K
6
5
LHPIN
LLINEIN
OPTIN#
R741
100K
From previous page
3
2
GAIN1
GAIN0
DECT_HP#OPT
C355
1µ
R1
Q510
DDTC144TCA
DEVICE_DECT#
R362
100K
131
8050QMA N/B Maintenance
8.11 LAN Test Error-1
An error occurs when a LAN device is installed.
LAN Test Error
Check the following parts for cold solder or one of the following
parts on the mother-board may be defective, use an oscilloscope
to check the following signal or replace the parts one at a time and
test after each replacement.
1.Check if the driver is installed properly.
2.Check if the notebook connect with the
LAN properly.
Board-level
Troubleshooting
Parts:
Signals:
U717
U709
U511
J506
+3V
Yes
Test
OK?
Correct it.
ICH_PME#
PCI_C/BE#[0..3]
PCIKRUN#
PCI_DEVESEL#
PMDI[0..3]+
PMDI[0..3]-
EECS
EECK
EEDI
EEDO
PCI_SERR#
U507
X503
L508
L510
L511
L512
R682
R683
R667
R670
No
Check if BIOS setup is ok.
Replace
Motherboard
Yes
Re-test
OK?
Correct it.
No
132
8050QMA N/B Maintenance
8.11 LAN Test Error-2
An error occurs when a LAN device is installed.
+3V
R696
3.6K
+3V
1
2
106
111
109
108
EECS
8
5
CS
SK
VCC
GND
P15
U511
EECK
+AVDDL
+AVDDH
C660
1µ
3
4
EEDI
DI
93C46
EEDO
DO
+DVDD
L512
90Z/100M
J506
1
PMDI0+
PMDI0-
12
11
13 MDI0+
PJTX0+
PJTX0-
1
2
PCI_AD[0..31]
33…
46
3
4
2
1
R508
100
P15
P15
PCI_AD20
P15
2
14 MDI0-
L63
90Z/100M
ICH_PME#
31
5
6
PMDI1+
PMDI1-
9
8
16 MDI1+
PJRX1+
PJRX1-
3
6
P11
3
4
2
1
PCI_C/BE[0..3]
PCLKRUN#
PCI_DEVSEL#
PCI_FRAME#
PCI_GNT3#
PCI_REQ3#
PCI_INTE#
PCI_IRDY#
PCI_TRDY#
PCI_PAR
44…
65
17 MDI1-
U717
L68
90Z/100M
14
15
PMDI2+
PMDI2-
6
5
19 MDI2+
MDO2+
MDO2-
4
5
3
4
2
1
68
20 MDI2-
U507
61
LAN
L67
90Z/100M
U709
18
19
PMDI3+
PMDI3-
3
2
22 MDI3+
MDO3+
MDO3-
7
8
29
NS692408
3
4
2
1
Controller
23 MDI3-
30
R213
R683
49.9
R682
49.9
R670
49.9
R667
49.9
0
South Bridge
ICH6-M
25
MCT1
24
21
18
RTL8100CL
MCT2
C668
0.01µ
C651
0.01µ
63
R202
75
MCT3
67
R204
75
MCT4
15
GND
GND
R20
75
76
R227
75
121 LAN_XTAL1
PCI_PERR#
PCI_SERR#
PCI_STOP#
70
R686
1M
LAN_XTAL2
122
75
C263
1000P
69
X503
25MHZ
GND_45
C681
27P
C682
27P
133
8050QMA N/B Maintenance
8.12 PC Card Socket Test Error-1
An error occurs when a PC card device is installed.
PC Card Socket Failure
1. Check if the PC Card device is installed
properly.
2. Confirm PC Card driver is installed ok.
Board-level
Troubleshooting
Check the following parts for cold solder or one of the following
parts on the mother-board may be defective, use an oscilloscope
to check the following signal or replace the parts one at a time and
test after each replacement.
Yes
Test
OK?
Correct it
Parts:
Signals
No
U715
U709
U509
J8
PCI_REQ0#
PCI_SERR#
PCI_PERR#
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCLKRUN#
PCI_PME#
Try another known good PC
Card or device.
Replace
Motherboard
PCI_GNT0#
PIC_PAR
PCI_AD[0..31]
PCI_C/BE#[0..3]
VCC5_EN#
VCC3_EN#
VPPD0
R625
R604
R240
Yes
Change the faulty
part then end.
Re-test
OK?
VPPD1
No
134
8050QMA N/B Maintenance
8.12 PC Card Socket Test Error-2
An error occurs when a PC card device is installed.
+3VS
+5VS
R625
10K
VCC[1..10]
VCCA1/2
+3VS
16
SHDN
5,6
5VA,B
CARD_VCC
3,4
3.3VA,B
C628
0.1µ
P16
R604
10K
VCC5_EN#
VCC3_EN#
1
2
8
+CARD_VCC +VPPOUT
VCCD0
VCCD1
VDDP0
VDDP1
OC
U509
J8
P18
11-13
10
AVCCC,B,A
VPPD0
VPPD1
15
14
CARD_PCIRST#
Refer Section 7.2(No display-3)
CP2211A
AVPP
P16
C610
0.1µ
C650
0.1µ
C657
0.1µ
C662
0.1µ
C603
0.1µ
+3VS
U715
R240
43.2
PCI_PME#
P11
CPAR, CPERR#, CSERR#
CardBus
PCI_C/BE#[0..3]
CRST#, CCD[1,2]#,CVS[1,2]#
CFRAME#, CIRDY#, CTRDY#,
CREQ#, CGNT#, CINT#
PCI_PAR, PCI_STOP#
PCI_SERR#, PCI_PERR#
PCI_GNT0#, PCI_REQ0#
PCI_FRAME#
Controller
U709
CBLOCK#, CSTOP#, CDEVSEL#
R2_D2, R2_D14, R2_A18
CB712
PCI_TRDY#, PCI_IRDY#
PCI_DEVSEL#
CAUDIO, CSTSCHG
South Bridge
ICH6-M
CAD[0..31], CC/BE[0..3]#
PCLKRUN#
PCI_AD[0..31]
IDSEL
135
Reference Material
™ Intel Pentium-M Processor
Intel, INC
Intel, INC
™ Intel 915PM North Bridge Data Sheet
™ Intel ICH6 South Bridge Data Sheet
™ System Explode View
Intel, INC
Technology.Corp./MiTAC
Technology.Corp./MiTAC
™ 8050QMA Hardware Engineering Specification
SERVICE MANUAL FOR 8050QMA
Sponsoring Editor : Jesse Jan
Author : ZX.Xiao
Assistant Editor : Ping Xie
Publisher : MiTAC International Corp.
Address : 1, R&D Road 2, Hsinchu Science-Based Industrial, Hsinchu, Taiwan, R.O.C.
Tel : 886-3-5779250
Fax : 886-3-5781245
First Edition : Jun. 2005
E-mail : Willy.Chen @ mic.com.tw
Web : http: //www.mitac.com
http: //www.mitacservice.com
|
