Intel Box Core I5 4430 BX80646I54430 User Manual

Desktop 4th Generation Intel® Core™  
Processor Family, Desktop Intel®  
Pentium® Processor Family, and  
Desktop Intel® Celeron® Processor  
Family  
Datasheet – Volume 1 of 2  
December 2013  
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Contents—Processor  
Contents  
2.7 Intel® Flexible Display Interface (Intel® FDI)............................................................37  
3.1 Intel® Virtualization Technology (Intel® VT)............................................................. 39  
3.2 Intel® Trusted Execution Technology (Intel® TXT).....................................................43  
3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)....................................... 44  
3.4 Intel® Turbo Boost Technology 2.0..........................................................................45  
3.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)................................................45  
3.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI).......................46  
3.7 Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-NI).....46  
3.8 Intel® 64 Architecture x2APIC................................................................................ 47  
4.2.1 Enhanced Intel® SpeedStep® Technology Key Features..................................51  
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Processor—Contents  
4.6.1 Intel® Rapid Memory Power Management (Intel® RMPM)................................64  
4.6.3 Intel® Graphics Dynamic Frequency............................................................ 64  
5.9 Intel® Turbo Boost Technology Thermal Considerations..............................................79  
5.9.1 Intel® Turbo Boost Technology Power Control and Reporting.......................... 79  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
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Contents—Processor  
7.3 VCC Voltage Identification (VID)..............................................................................90  
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Processor—Figures  
Figures  
Intel® Flex Memory Technology Operations.................................................................21  
19 Thermal Test Vehicle (TTV) Case Temperature (TCASE) Measurement Location..................71  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
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Tables—Processor  
Tables  
10 DisplayPort and embedded DisplayPort* Resolutions for 1, 2, 4 Lanes – Link Data  
28 Intel® Turbo Boost Technology 2.0 Package Power Control Settings............................... 80  
48 Memory Controller (VDDQ) Supply DC Voltage and Current Specifications.........................99  
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Revision History—Processor  
Revision History  
Revision  
Description  
Date  
001  
Initial Release  
June 2013  
Added Desktop 4th Generation Intel® Corei7-4771, i5-4440,  
i5-4440S, i3-4340, i3-4330, i3-4330T, i3-4130, and i3-4130T  
processors  
Added Desktop Intel® Pentium® G3430, G3420, G3220,  
G3420T, G3220T processors  
002  
September 2013  
Updated Section 4.2.4, Core C-State Rules  
Updated Section 4.2.5, Package C-States  
Minor edits throughout for clarity  
003  
004  
Minor edits throughout for clarity  
November 2013  
December 2013  
Added Desktop Intel® Celeron® G1830, G1820, and G1820T  
processors  
Added Section 4.2.6, "Package C-States and Display  
Resolutions"  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
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Processor—Introduction  
1.0  
Introduction  
The Desktop 4th Generation Intel® Coreprocessor family , Desktop Intel® Pentium®  
processor family, and Desktop Intel® Celeron® processor family are 64-bit, multi-core  
processors built on 22-nanometer process technology.  
The processors are designed for a two-chip platform consisting of a processor and  
Platform Controller Hub (PCH). The processors are designed to be used with the Intel®  
8 Series chipset. See the following figure for an example platform block diagram.  
Throughout this document, the Desktop 4th Generation Intel® Coreprocessor family,  
Desktop Intel® Pentium® processor family, and Desktop Intel® Celeron® processor  
family may be referred to simply as "processor".  
Throughout this document, the Desktop 4th Generation Intel® Coreprocessor family  
refers to the Desktop 4th Generation Intel® Corei7-4771, i7-4770R, i7-4770K,  
i7-4770, i7-4770S, i7-4770T, i7-4765T, i5-4670R, i5-4670K, i5-4670, i5-4670S,  
i5-4670T, i5-4670R, i5-4570R, i5-4570S, i5-4570T, i5-4440, i5-4440S, i5-4430,  
i5-4430S, i3-4340, i3-4330. i3-4330T, i3-4130, and i3-4130T processors.  
Throughout this document, the Desktop Intel® Pentium® processor family refers to  
the Intel® Pentium® G3430, G3420, G3220, G3420T, and G3220T processors.  
Throughout this document, the Desktop Intel® Celeron® processor family refers to the  
Intel® Celeron® G1830, G1820, and G1820T processors.  
Note:  
Some processor features are not available on all platforms. Refer to the processor  
Specification Update document for details.  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
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Introduction—Processor  
Figure 1.  
Platform Block Diagram  
1333 / 1600 MT/s  
2 DIMMs / CH  
PCI Express* 3.0  
CH A  
CH B  
Processor  
Digital Display  
Interface (DDI)  
(3 interfaces)  
System Memory  
Note: 2 DIMMs / CH is not  
supported on all SKUs.  
Intel® Flexible Display  
Interface (Intel® FDI)  
(x2)  
Direct Media Interface 2.0  
(DMI 2.0) (x4)  
USB 3.0  
Analog Display  
(up to 6 Ports)  
(VGA)  
USB 2.0  
(8 Ports)  
Integrated LAN  
Platform Controller  
Hub (PCH)  
SATA, 6 GB/s  
(up to 6 Ports)  
PCI Express* 2.0  
(up to 8 Ports)  
Intel® High  
SPI  
SPI Flash  
Definition Audio  
(Intel® HD Audio)  
LPC  
Trusted Platform  
Module (TPM) 1.2  
SMBus 2.0  
GPIOs  
Super IO / EC  
1.1  
Supported Technologies  
Intel® Virtualization Technology (Intel® VT)  
Intel® Active Management Technology 9.5 (Intel® AMT 9.5 )  
Intel® Trusted Execution Technology (Intel® TXT)  
Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)  
Intel® Hyper-Threading Technology (Intel® HT Technology)  
Intel® 64 Architecture  
Execute Disable Bit  
Intel® Turbo Boost Technology 2.0  
Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)  
Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
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Processor—Introduction  
PCLMULQDQ Instruction  
Intel® Secure Key  
Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-  
NI)  
PAIR – Power Aware Interrupt Routing  
SMEP – Supervisor Mode Execution Protection  
Note:  
The availability of the features may vary between processor SKUs.  
1.2  
Interfaces  
The processor supports the following interfaces:  
DDR3/DDR3L  
Direct Media Interface (DMI)  
Digital Display Interface (DDI)  
PCI Express*  
1.3  
Power Management Support  
Processor Core  
Full support of ACPI C-states as implemented by the following processor C-states:  
— C0, C1, C1E, C3, C6, C7  
Enhanced Intel SpeedStep® Technology  
System  
S0, S3, S4, S5  
Memory Controller  
Conditional self-refresh  
Dynamic power-down  
PCI Express*  
L0s and L1 ASPM power management capability  
DMI  
L0s and L1 ASPM power management capability  
Processor Graphics Controller  
Intel® Rapid Memory Power Management (Intel® RMPM)  
Intel® Smart 2D Display Technology (Intel® S2DDT)  
Graphics Render C-state (RC6)  
Intel® Seamless Display Refresh Rate Switching with eDP port  
Intel® Display Power Saving Technology (Intel® DPST)  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
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Introduction—Processor  
1.4  
Thermal Management Support  
Digital Thermal Sensor  
Adaptive Thermal Monitor  
THERMTRIP# and PROCHOT# support  
On-Demand Mode  
Memory Open and Closed Loop Throttling  
Memory Thermal Throttling  
External Thermal Sensor (TS-on-DIMM and TS-on-Board)  
Render Thermal Throttling  
Fan speed control with DTS  
1.5  
Package Support  
The processor socket type is noted as LGA1150. The package is a 37.5 x 37.5 mm Flip  
Chip Land Grid Array (FCLGA 1150). See the appropriate Processor Thermal  
Mechanical Design Guidelines and LGA1150 Socket Application Guide for complete  
details on the package.  
1.6  
Terminology  
Table 1.  
Terminology  
Term  
Description  
APD  
B/D/F  
BGA  
BLC  
Active Power-down  
Bus/Device/Function  
Ball Grid Array  
Backlight Compensation  
Block Level Transfer  
Bits per pixel  
BLT  
BPP  
CKE  
CLTM  
DDI  
DDR3  
DLL  
Clock Enable  
Closed Loop Thermal Management  
Digital Display Interface  
Third-generation Double Data Rate SDRAM memory technology  
Delay-Locked Loop  
DMA  
DMI  
DP  
Direct Memory Access  
Direct Media Interface  
DisplayPort*  
DTS  
Digital Thermal Sensor  
Digital Visual Interface. DVI* is the interface specified by the DDWG (Digital Display  
Working Group)  
DVI*  
EC  
Embedded Controller  
continued...  
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Processor—Introduction  
Term  
Description  
ECC  
eDP*  
EPG  
EU  
Error Correction Code  
embedded DisplayPort*  
Electrical Power Gating  
Execution Unit  
FMA  
FSC  
Floating-point fused Multiply Add instructions  
Fan Speed Control  
HDCP  
HDMI*  
HFM  
iDCT  
IHS  
High-bandwidth Digital Content Protection  
High Definition Multimedia Interface  
High Frequency Mode  
Inverse Discrete  
Integrated Heat Spreader  
GFX  
GSA  
GUI  
Graphics  
Graphics in System Agent  
Graphical User Interface  
IMC  
Integrated Memory Controller  
64-bit memory extensions to the IA-32 architecture  
Intel® 64  
Technology  
Intel® DPST  
Intel® FDI  
Intel Display Power Saving Technology  
Intel Flexible Display Interface  
Intel® TSX-NI  
Intel® TXT  
Intel Transactional Synchronization Extensions - New Instructions  
Intel Trusted Execution Technology  
Intel Virtualization Technology. Processor virtualization, when used in conjunction  
with Virtual Machine Monitor software, enables multiple, robust independent software  
environments inside a single platform.  
Intel® VT  
Intel Virtualization Technology (Intel VT) for Directed I/O. Intel VT-d is a hardware  
assist, under system software (Virtual Machine Manager or OS) control, for enabling  
I/O device virtualization. Intel VT-d also brings robust security by providing protection  
from errant DMAs by using DMA remapping, a key feature of Intel VT-d.  
Intel® VT-d  
IOV  
ISI  
I/O Virtualization  
Inter-Symbol Interference  
Integrated Trusted Platform Module  
Liquid Crystal Display  
ITPM  
LCD  
Low Frequency Mode. LFM is Pn in the P-state table. It can be read at MSR CEh  
[47:40].  
LFM  
LFP  
Local Flat Panel  
LPDDR3  
MCP  
Low-Power Third-generation Double Data Rate SDRAM memory technology  
Multi-Chip Package  
Minimum Frequency Mode. MFM is the minimum ratio supported by the processor and  
can be read from MSR CEh [55:48].  
MFM  
MLE  
Measured Launched Environment  
continued...  
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Introduction—Processor  
Term  
Description  
MLC  
MSI  
MSL  
MSR  
Mid-Level Cache  
Message Signaled Interrupt  
Moisture Sensitive Labeling  
Model Specific Registers  
Non-Critical to Function. NCTF locations are typically redundant ground or non-critical  
reserved, so the loss of the solder joint continuity at end of life conditions will not  
affect the overall product functionality.  
NCTF  
ODT  
On-Die Termination  
OLTM  
Open Loop Thermal Management  
Platform Compatibility Guide (PCG) (previously known as FMB) provides a design  
target for meeting all planned processor frequency requirements.  
PCG  
PCH  
Platform Controller Hub. The chipset with centralized platform capabilities including  
the main I/O interfaces along with display connectivity, audio features, power  
management, manageability, security, and storage features.  
The Platform Environment Control Interface (PECI) is a one-wire interface that  
provides a communication channel between Intel processor and chipset components  
to external monitoring devices.  
PECI  
Ψ ca  
PEG  
Case-to-ambient thermal characterization parameter (psi). A measure of thermal  
solution performance using total package power. Defined as (TCASE - TLA ) / Total  
Package Power. The heat source should always be specified for Y measurements.  
PCI Express* Graphics. External Graphics using PCI Express* Architecture. It is a  
high-speed serial interface where configuration is software compatible with the  
existing PCI specifications.  
PL1, PL2  
PPD  
Power Limit 1 and Power Limit 2  
Pre-charge Power-down  
Processor  
The 64-bit multi-core component (package)  
The term “processor core” refers to Si die itself, which can contain multiple execution  
cores. Each execution core has an instruction cache, data cache, and 256-KB L2  
cache. All execution cores share the L3 cache.  
Processor Core  
Processor Graphics  
Rank  
Intel Processor Graphics  
A unit of DRAM corresponding to four to eight devices in parallel, ignoring ECC. These  
devices are usually, but not always, mounted on a single side of a SO-DIMM.  
SCI  
SF  
System Control Interrupt. SCI is used in the ACPI protocol.  
Strips and Fans  
SMM  
SMX  
System Management Mode  
Safer Mode Extensions  
A non-operational state. The processor may be installed in a platform, in a tray, or  
loose. Processors may be sealed in packaging or exposed to free air. Under these  
conditions, processor landings should not be connected to any supply voltages, have  
any I/Os biased, or receive any clocks. Upon exposure to “free air” (that is, unsealed  
packaging or a device removed from packaging material), the processor must be  
handled in accordance with moisture sensitivity labeling (MSL) as indicated on the  
packaging material.  
Storage Conditions  
SVID  
TAC  
Serial Voltage Identification  
Thermal Averaging Constant  
continued...  
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Processor—Introduction  
Term  
Description  
TAP  
Test Access Point  
The case temperature of the processor, measured at the geometric center of the top-  
side of the TTV IHS.  
TCASE  
TCC  
Thermal Control Circuit  
TCONTROL is a static value that is below the TCC activation temperature and used as a  
trigger point for fan speed control. When DTS > TCONTROL, the processor must comply  
to the TTV thermal profile.  
TCONTROL  
Thermal Design Power: Thermal solution should be designed to dissipate this target  
power level. TDP is not the maximum power that the processor can dissipate.  
TDP  
TLB  
TTV  
Translation Look-aside Buffer  
Thermal Test Vehicle. A mechanically equivalent package that contains a resistive  
heater in the die to evaluate thermal solutions.  
Thermal Monitor. A power reduction feature designed to decrease temperature after  
the processor has reached its maximum operating temperature.  
TM  
VCC  
VDDQ  
VF  
Processor core power supply  
DDR3/DDR3L power supply.  
Vertex Fetch  
VID  
VS  
Voltage Identification  
Vertex Shader  
VLD  
VMM  
VR  
Variable Length Decoding  
Virtual Machine Monitor  
Voltage Regulator  
VSS  
x1  
Processor ground  
Refers to a Link or Port with one Physical Lane  
Refers to a Link or Port with two Physical Lanes  
Refers to a Link or Port with four Physical Lanes  
Refers to a Link or Port with eight Physical Lanes  
Refers to a Link or Port with sixteen Physical Lanes  
x2  
x4  
x8  
x16  
1.7  
Related Documents  
Table 2.  
Related Documents  
Document  
Document  
Number / Location  
Desktop 4th Generation Intel® Core® Processor Family, Desktop Intel® Pentium®  
Processor Family, and Desktop Intel® Celeron® Processor Family Datasheet, Volume  
2 of 2  
328898  
328899  
Desktop 4th Generation Intel® Core® Processor Family, Desktop Intel® Pentium®  
Processor Family, and Desktop Intel® Celeron® Processor Family Specification  
Update  
Desktop 4th Generation Intel® Core® Processor Family, Desktop Intel® Pentium®  
Processor Family, Desktop Intel® Celeron® Processor Family, and Intel® Xeon®  
Processor E3-1200 v3 Product Family Thermal Mechanical Design Guidelines  
328900  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
Datasheet – Volume 1 of 2  
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Introduction—Processor  
Document  
Document  
Number / Location  
LGA1150 Socket Application Guide  
328999  
328904  
Intel® 8 Series / C220 Series Chipset Family Platform Controller Hub (PCH)  
Datasheet  
Intel® 8 Series / C220 Series Chipset Family Platform Controller Hub (PCH)  
Specification Update  
328905  
328906  
Intel® 8 Series / C220 Series Chipset Family Platform Controller Hub (PCH) Thermal  
Mechanical Specifications and Design Guidelines  
Advanced Configuration and Power Interface 3.0  
PCI Local Bus Specification 3.0  
PCI Express Base Specification, Revision 2.0  
DDR3 SDRAM Specification  
DisplayPort* Specification  
Intel® 64 and IA-32 Architectures Software Developer's Manuals  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
December 2013  
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Processor—Interfaces  
2.0  
Interfaces  
2.1  
System Memory Interface  
Two channels of DDR3/DDR3L Unbuffered Dual In-Line Memory Modules (UDIMM)  
or DDR3/DDR3L Unbuffered Small Outline Dual In-Line Memory Modules (SO-  
DIMM) with a maximum of two DIMMs per channel.  
Single-channel and dual-channel memory organization modes  
Data burst length of eight for all memory organization modes  
Memory data transfer rates of 1333 MT/s and 1600 MT/s  
64-bit wide channels  
DDR3/DDR3L I/O Voltage of 1.5 V for Desktop  
The type of the DIMM modules supported by the processor is dependent on the  
PCH SKU in the target platform:  
— Desktop PCH platforms support non-ECC UDIMMs only  
— All In One platforms (AIO) support SO-DIMMs  
Theoretical maximum memory bandwidth of:  
— 21.3 GB/s in dual-channel mode assuming 1333 MT/s  
— 25.6 GB/s in dual-channel mode assuming 1600 MT/s  
1Gb, 2Gb, and 4Gb DDR3/DDR3L DRAM device technologies are supported  
— Using 4Gb DRAM device technologies, the largest system memory capacity  
possible is 32 GB, assuming Dual Channel Mode with four x8 dual ranked  
DIMM memory configuration  
Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank  
devices)  
Processor on-die VREF generation for DDR DQ Read and Write as well as  
CMD/ADD  
Command launch modes of 1n/2n  
On-Die Termination (ODT)  
Asynchronous ODT  
Intel Fast Memory Access (Intel FMA):  
— Just-in-Time Command Scheduling  
— Command Overlap  
— Out-of-Order Scheduling  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
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Interfaces—Processor  
2.1.1  
System Memory Technology Supported  
The Integrated Memory Controller (IMC) supports DDR3/DDR3L protocols with two  
independent, 64-bit wide channels each accessing one or two DIMMs. The type of  
memory supported by the processor is dependent on the PCH SKU in the target  
platform.  
Note:  
The IMC supports a maximum of two DDR3/DDR3L DIMMs per channel; thus, allowing  
up to four device ranks per channel.  
Note:  
The support of DDR3/DDR3L frequencies and number of DIMMs per channel is SKU  
dependent.  
Table 3.  
Processor DIMM Support by Product  
Processor Cores  
Package  
DIMM per Channel  
1 DPC  
DDR3 / DDR3L  
1333/1600  
Dual Core  
uLGA  
2 DPC  
1333/1600  
1 DPC  
1333/1600  
Quad Core  
uLGA  
2 DPC  
1333/1600  
DDR3/DDR3L Data Transfer Rates:  
1333 MT/s (PC3-10600)  
1600 MT/s (PC3-12800)  
AIO platform DDR3/DDR3L SO-DIMM Modules:  
Raw Card B – Single Ranked x8 unbuffered non-ECC  
Raw Card F – Dual Ranked x8 (planar) unbuffered non-ECC  
Desktop platform UDIMM Modules:  
Raw Card A – Single Ranked x8 unbuffered non-ECC  
Raw Card B – Dual Ranked x8 unbuffered non-ECC  
Standard 1Gb, 2Gb, and 4Gb technologies and addressing are supported for x8  
devices. There is no support for memory modules with different technologies or  
capacities on opposite sides of the same memory module. If one side of a memory  
module is populated, the other side is either identical or empty.  
Table 4.  
Supported UDIMM Module Configurations  
Raw  
Card  
Version  
DIMM  
Capacity  
DRAM  
Device  
Technology  
DRAM  
Organization  
# of  
DRAM  
Devices  
# of  
# of  
Row / Col  
Address  
Bits  
# of  
Page Size  
Physical  
Devices  
Ranks  
Banks  
Inside  
DRAM  
Desktop Platforms  
Unbuffered / Non-ECC Supported DIMM Module Configurations  
1 Gb 128 M X 8 14/10  
A
1 GB  
8
1
8
8K  
continued...  
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Processor—Interfaces  
Raw  
Card  
Version  
DIMM  
Capacity  
DRAM  
Device  
Technology  
DRAM  
Organization  
# of  
DRAM  
Devices  
# of  
# of  
Row / Col  
Address  
Bits  
# of  
Page Size  
Physical  
Devices  
Ranks  
Banks  
Inside  
DRAM  
2 GB  
4 GB  
4 GB  
8 GB  
1 Gb  
2 Gb  
4 Gb  
4 Gb  
128 M X 8  
256 M X 8  
512 M X 8  
512 M X 8  
16  
16  
8
2
2
1
2
14/10  
15/10  
15/10  
16/10  
8
8
8
8
8K  
8K  
8K  
8K  
B
16  
Note:  
Table 5.  
DIMM module support is based on availability and is subject to change.  
Supported SO-DIMM Module Configurations (AIO Only)  
Raw Card  
Version  
DIMM  
Capacity  
DRAM  
Organization  
# of DRAM  
Devices  
# of Row/Col  
Address Bits  
# of Banks  
Inside DRAM  
Page Size  
1 GB  
2 GB  
4 GB  
2 GB  
4 GB  
8 GB  
128 M x 8  
256 M x 8  
512 M x 8  
128 M x 8  
256 M x 8  
512 M x 8  
8
8
14/10  
15/10  
16/10  
14/10  
15/10  
16/10  
8
8
8
8
8
8
8K  
8K  
8K  
8K  
8K  
8K  
B
8
16  
16  
16  
F
Note:  
System memory configurations are based on availability and are subject to change.  
2.1.2  
System Memory Timing Support  
The IMC supports the following DDR3/DDR3L Speed Bin, CAS Write Latency (CWL),  
and command signal mode timings on the main memory interface:  
tCL = CAS Latency  
tRCD = Activate Command to READ or WRITE Command delay  
tRP = PRECHARGE Command Period  
CWL = CAS Write Latency  
Command Signal modes = 1N indicates a new command may be issued every  
clock and 2N indicates a new command may be issued every 2 clocks. Command  
launch mode programming depends on the transfer rate and memory  
configuration.  
Table 6.  
DDR3 / DDR3L System Memory Timing Support  
Segment  
Transfer Rate  
(MT/s)  
tCL (tCK)  
tRCD  
(tCK)  
tRP  
(tCK)  
CWL  
(tCK)  
DPC  
CMD  
Mode  
1
2
1
2
1N/2N  
2N  
1333  
1600  
8/9  
8/9  
8/9  
7
8
All segments  
1N/2N  
2N  
10/11  
10/11  
10/11  
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Note:  
System memory timing support is based on availability and is subject to change.  
2.1.3  
System Memory Organization Modes  
The Integrated Memory Controller (IMC) supports two memory organization modes –  
single-channel and dual-channel. Depending upon how the DIMM Modules are  
populated in each memory channel, a number of different configurations can exist.  
Single-Channel Mode  
In this mode, all memory cycles are directed to a single-channel. Single-channel mode  
is used when either Channel A or Channel B DIMM connectors are populated in any  
order, but not both.  
Dual-Channel Mode – Intel® Flex Memory Technology Mode  
The IMC supports Intel Flex Memory Technology Mode. Memory is divided into  
symmetric and asymmetric zones. The symmetric zone starts at the lowest address in  
each channel and is contiguous until the asymmetric zone begins or until the top  
address of the channel with the smaller capacity is reached. In this mode, the system  
runs with one zone of dual-channel mode and one zone of single-channel mode,  
simultaneously, across the whole memory array.  
Note:  
Channels A and B can be mapped for physical channel 0 and 1 respectively or vice  
versa; however, channel A size must be greater or equal to channel B size.  
Figure 2.  
Intel® Flex Memory Technology Operations  
TOM  
Non interleaved  
access  
C
B
C
Dual channel  
interleaved access  
B
B
B
CH A  
CH B  
CH A and CH B can be configured to be physical channels 0 or 1  
B – The largest physical memory amount of the smaller size memory module  
C – The remaining physical memory amount of the larger size memory module  
Dual-Channel Symmetric Mode  
Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum  
performance on real world applications. Addresses are ping-ponged between the  
channels after each cache line (64-byte boundary). If there are two requests, and the  
second request is to an address on the opposite channel from the first, that request  
can be sent before data from the first request has returned. If two consecutive cache  
lines are requested, both may be retrieved simultaneously, since they are ensured to  
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be on opposite channels. Use Dual-Channel Symmetric mode when both Channel A  
and Channel B DIMM connectors are populated in any order, with the total amount of  
memory in each channel being the same.  
When both channels are populated with the same memory capacity and the boundary  
between the dual channel zone and the single channel zone is the top of memory, the  
IMC operates completely in Dual-Channel Symmetric mode.  
Note:  
The DRAM device technology and width may vary from one channel to the other.  
2.1.3.1  
System Memory Frequency  
In all modes, the frequency of system memory is the lowest frequency of all memory  
modules placed in the system, as determined through the SPD registers on the  
memory modules. The system memory controller supports one or two DIMM  
connectors per channel. The usage of DIMM modules with different latencies is  
allowed, but in that case, the worst latency (among two channels) will be used. For  
dual-channel modes, both channels must have a DIMM connector populated and for  
single-channel mode only a single channel may have one or both DIMM connectors  
populated.  
Note:  
In a two-DIMM Per Channel (2DPC) layout memory configuration, the furthest DIMM  
from the processor of any given channel must always be populated first.  
2.1.3.2  
Intel® Fast Memory Access (Intel® FMA) Technology Enhancements  
The following sections describe the Just-in-Time Scheduling, Command Overlap, and  
Out-of-Order Scheduling Intel FMA technology enhancements.  
Just-in-Time Command Scheduling  
The memory controller has an advanced command scheduler where all pending  
requests are examined simultaneously to determine the most efficient request to be  
issued next. The most efficient request is picked from all pending requests and issued  
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,  
instead of having all memory access requests go individually through an arbitration  
mechanism forcing requests to be executed one at a time, the requests can be started  
without interfering with the current request allowing for concurrent issuing of  
requests. This allows for optimized bandwidth and reduced latency while maintaining  
appropriate command spacing to meet system memory protocol.  
Command Overlap  
Command Overlap allows the insertion of the DRAM commands between the Activate,  
Pre-charge, and Read/Write commands normally used, as long as the inserted  
commands do not affect the currently executing command. Multiple commands can be  
issued in an overlapping manner, increasing the efficiency of system memory protocol.  
Out-of-Order Scheduling  
While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,  
the IMC continuously monitors pending requests to system memory for the best use of  
bandwidth and reduction of latency. If there are multiple requests to the same open  
page, these requests would be launched in a back-to-back manner to make optimum  
use of the open memory page. This ability to reorder requests on the fly allows the  
IMC to further reduce latency and increase bandwidth efficiency.  
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2.1.3.3  
Data Scrambling  
The system memory controller incorporates a Data Scrambling feature to minimize the  
impact of excessive di/dt on the platform system memory VRs due to successive 1s  
and 0s on the data bus. Past experience has demonstrated that traffic on the data bus  
is not random and can have energy concentrated at specific spectral harmonics  
creating high di/dt, which is generally limited by data patterns that excite resonance  
between the package inductance and on die capacitances. As a result, the system  
memory controller uses a data scrambling feature to create pseudo-random patterns  
on the system memory data bus to reduce the impact of any excessive di/dt.  
2.2  
PCI Express* Interface  
This section describes the PCI Express* interface capabilities of the processor. See the  
PCI Express Base* Specification 3.0 for details on PCI Express*.  
2.2.1  
PCI Express* Support  
The PCI Express* lanes (PEG[15:0] TX and RX) are fully-compliant to the PCI Express  
Base Specification, Revision 3.0.  
The 4th Generation Intel® Coreprocessor Desktop with Desktop PCH supports the  
configurations shown in the following table (may vary depending on PCH SKUs).  
Table 7.  
PCI Express* Supported Configurations in Desktop Products  
Configuration  
1x8, 2x4  
2x8  
Desktop  
GFX, I/O  
GFX, I/O  
GFX, I/O  
1x16  
The port may negotiate down to narrower widths.  
— Support for x16/x8/x4/x2/x1 widths for a single PCI Express* mode.  
2.5 GT/s, 5.0 GT/s and 8 GT/s PCI Express* bit rates are supported.  
Gen1 Raw bit-rate on the data pins of 2.5 GT/s, resulting in a real bandwidth per  
pair of 250 MB/s given the 8b/10b encoding used to transmit data across this  
interface. This also does not account for packet overhead and link maintenance.  
Maximum theoretical bandwidth on the interface of 4 GB/s in each direction  
simultaneously, for an aggregate of 8 GB/s when x16 Gen 1.  
Gen 2 Raw bit-rate on the data pins of 5.0 GT/s, resulting in a real bandwidth per  
pair of 500 MB/s given the 8b/10b encoding used to transmit data across this  
interface. This also does not account for packet overhead and link maintenance.  
Maximum theoretical bandwidth on the interface of 8 GB/s in each direction  
simultaneously, for an aggregate of 16 GB/s when x16 Gen 2.  
Gen 3 raw bit-rate on the data pins of 8.0 GT/s, resulting in a real bandwidth per  
pair of 984 MB/s using 128b/130b encoding to transmit data across this interface.  
This also does not account for packet overhead and link maintenance. Maximum  
theoretical bandwidth on the interface of 16 GB/s in each direction simultaneously,  
for an aggregate of 32 GB/s when x16 Gen 3.  
Hierarchical PCI-compliant configuration mechanism for downstream devices.  
Traditional PCI style traffic (asynchronous snooped, PCI ordering).  
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PCI Express* extended configuration space. The first 256 bytes of configuration  
space aliases directly to the PCI Compatibility configuration space. The remaining  
portion of the fixed 4-KB block of memory-mapped space above that (starting at  
100h) is known as extended configuration space.  
PCI Express* Enhanced Access Mechanism. Accessing the device configuration  
space in a flat memory mapped fashion.  
Automatic discovery, negotiation, and training of link out of reset.  
Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering).  
Peer segment destination posted write traffic (no peer-to-peer read traffic) in  
Virtual Channel 0: DMI -> PCI Express* Port 0  
64-bit downstream address format, but the processor never generates an address  
above 64 GB (Bits 63:36 will always be zeros).  
64-bit upstream address format, but the processor responds to upstream read  
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are  
nonzero) with an Unsupported Request response. Upstream write transactions to  
addresses above 64 GB will be dropped.  
Re-issues Configuration cycles that have been previously completed with the  
Configuration Retry status.  
PCI Express* reference clock is 100-MHz differential clock.  
Power Management Event (PME) functions.  
Dynamic width capability.  
Message Signaled Interrupt (MSI and MSI-X) messages.  
Polarity inversion  
Note:  
The processor does not support PCI Express* Hot-Plug.  
2.2.2  
PCI Express* Architecture  
Compatibility with the PCI addressing model is maintained to ensure that all existing  
applications and drivers operate unchanged.  
The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-  
and-Play specification. The processor PCI Express* ports support Gen 3. At 8 GT/s,  
Gen 3 operation results in twice as much bandwidth per lane as compared to Gen 2  
operation. The 16 lanes PEG can operate at 2.5 GT/s, 5 GT/s, or 8 GT/s.  
Gen 3 PCI Express* uses a 128b/130b encoding that is about 23% more efficient than  
the 8b/10b encoding used in Gen 1 and Gen 2.  
The PCI Express* architecture is specified in three layers – Transaction Layer, Data  
Link Layer, and Physical Layer. See the PCI Express Base Specification 3.0 for details  
of PCI Express* architecture.  
2.2.3  
PCI Express* Configuration Mechanism  
The PCI Express* (external graphics) link is mapped through a PCI-to-PCI bridge  
structure.  
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Figure 3.  
PCI Express* Related Register Structures in the Processor  
PCI-PCI  
Bridge  
representing  
root PCI  
Express ports  
(Device 1 and  
Device 6)  
PCI  
PCI  
Express*  
Device  
Compatible  
Host Bridge  
Device  
PEG0  
(Device 0)  
DMI  
PCI Express* extends the configuration space to 4096 bytes per-device/function, as  
compared to 256 bytes allowed by the conventional PCI specification. PCI Express*  
configuration space is divided into a PCI-compatible region (that consists of the first  
256 bytes of a logical device's configuration space) and an extended PCI Express*  
region (that consists of the remaining configuration space). The PCI-compatible region  
can be accessed using either the mechanisms defined in the PCI specification or using  
the enhanced PCI Express* configuration access mechanism described in the PCI  
Express* Enhanced Configuration Mechanism section.  
The PCI Express* Host Bridge is required to translate the memory-mapped PCI  
Express* configuration space accesses from the host processor to PCI Express*  
configuration cycles. To maintain compatibility with PCI configuration addressing  
mechanisms, it is recommended that system software access the enhanced  
configuration space using 32-bit operations (32-bit aligned) only. See the PCI Express  
Base Specification for details of both the PCI-compatible and PCI Express* Enhanced  
configuration mechanisms and transaction rules.  
PCI Express* Port  
The PCI Express* interface on the processor is a single, 16-lane (x16) port that can  
also be configured at narrower widths. The PCI Express* port is being designed to be  
compliant with the PCI Express Base Specification, Revision 3.0.  
PCI Express* Lanes Connection  
The following figure demonstrates the PCIe* lane mapping.  
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Figure 4.  
PCI Express* Typical Operation 16 Lanes Mapping  
Lane 0  
Lane 1  
Lane 2  
Lane 3  
Lane 4  
Lane 5  
Lane 6  
Lane 7  
Lane 8  
Lane 9  
Lane 10  
Lane 11  
Lane 12  
Lane 13  
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
8
9
9
10  
11  
12  
13  
14  
15  
10  
11  
12  
13  
14  
15  
0
1
2
3
Lane 14  
Lane 15  
2.3  
Direct Media Interface (DMI)  
Direct Media Interface (DMI) connects the processor and the PCH. Next generation  
DMI2 is supported.  
Note:  
Only DMI x4 configuration is supported.  
DMI 2.0 support.  
Compliant to Direct Media Interface Second Generation (DMI2).  
Four lanes in each direction.  
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5 GT/s point-to-point DMI interface to PCH is supported.  
Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of  
500 MB/s given the 8b/10b encoding used to transmit data across this interface.  
Does not account for packet overhead and link maintenance.  
Maximum theoretical bandwidth on interface of 2 GB/s in each direction  
simultaneously, for an aggregate of 4 GB/s when DMI x4.  
Shares 100-MHz PCI Express* reference clock.  
64-bit downstream address format, but the processor never generates an address  
above 64 GB (Bits 63:36 will always be zeros).  
64-bit upstream address format, but the processor responds to upstream read  
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are  
nonzero) with an Unsupported Request response. Upstream write transactions to  
addresses above 64 GB will be dropped.  
Supports the following traffic types to or from the PCH:  
— DMI -> DRAM  
— DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs  
only)  
— Processor core -> DMI  
APIC and MSI interrupt messaging support:  
— Message Signaled Interrupt (MSI and MSI-X) messages  
Downstream SMI, SCI and SERR error indication.  
Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port  
DMA, floppy drive, and LPC bus masters.  
DC coupling – no capacitors between the processor and the PCH.  
Polarity inversion.  
PCH end-to-end lane reversal across the link.  
Supports Half Swing “low-power/low-voltage”.  
DMI Error Flow  
DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or  
GPE. Any DMI related SERR activity is associated with Device 0.  
DMI Link Down  
The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to  
data link down, after the link was up, then the DMI link hangs the system by not  
allowing the link to retrain to prevent data corruption. This link behavior is controlled  
by the PCH.  
Downstream transactions that had been successfully transmitted across the link prior  
to the link going down may be processed as normal. No completions from  
downstream, non-posted transactions are returned upstream over the DMI link after a  
link down event.  
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2.4  
Processor Graphics  
The processor graphics contains a generation 7.5 graphics core architecture. This  
enables substantial gains in performance and lower power consumption over previous  
generations. Up to 20 Execution Units are supported depending on the processor SKU.  
Next Generation Intel Clear Video Technology HD Support is a collection of video  
playback and enhancement features that improve the end user’s viewing  
experience  
— Encode / transcode HD content  
— Playback of high definition content including Blu-ray Disc*  
— Superior image quality with sharper, more colorful images  
— Playback of Blu-ray* disc S3D content using HDMI (1.4a specification  
compliant with 3D)  
DirectX* Video Acceleration (DXVA) support for accelerating video processing  
— Full AVC/VC1/MPEG2 HW Decode  
Advanced Scheduler 2.0, 1.0, XPDM support  
Windows* 8, Windows* 7, OSX, Linux* operating system support  
DirectX* 11.1, DirectX* 11, DirectX* 10.1, DirectX* 10, DirectX* 9 support.  
OpenGL* 4.0, support  
Switchable Graphics support on AIO platforms with MxM solutions only  
2.5  
Processor Graphics Controller (GT)  
The New Graphics Engine Architecture includes 3D compute elements, Multi-format  
HW assisted decode/encode pipeline, and Mid-Level Cache (MLC) for superior high  
definition playback, video quality, and improved 3D performance and media.  
The Display Engine handles delivering the pixels to the screen. GSA (Graphics in  
System Agent) is the primary channel interface for display memory accesses and  
“PCI-like” traffic in and out.  
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Figure 5.  
Processor Graphics Controller Unit Block Diagram  
2.5.1  
3D and Video Engines for Graphics Processing  
The Gen 7.5 3D engine provides the following performance and power-management  
enhancements.  
3D Pipeline  
The 3D graphics pipeline architecture simultaneously operates on different primitives  
or on different portions of the same primitive. All the cores are fully programmable,  
increasing the versatility of the 3D Engine.  
3D Engine Execution Units  
Supports up to 20 EUs. The EUs perform 128-bit wide execution per clock.  
Support SIMD8 instructions for vertex processing and SIMD16 instructions for  
pixel processing.  
Vertex Fetch (VF) Stage  
The VF stage executes 3DPRIMITIVE commands. Some enhancements have been  
included to better support legacy D3D APIs as well as SGI OpenGL*.  
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Vertex Shader (VS) Stage  
The VS stage performs shading of vertices output by the VF function. The VS unit  
produces an output vertex reference for every input vertex reference received from  
the VF unit, in the order received.  
Geometry Shader (GS) Stage  
The GS stage receives inputs from the VS stage. Compiled application-provided GS  
programs, specifying an algorithm to convert the vertices of an input object into some  
output primitives. For example, a GS shader may convert lines of a line strip into  
polygons representing a corresponding segment of a blade of grass centered on the  
line. Or it could use adjacency information to detect silhouette edges of triangles and  
output polygons extruding out from the edges.  
Clip Stage  
The Clip stage performs general processing on incoming 3D objects. However, it also  
includes specialized logic to perform a Clip Test function on incoming objects. The Clip  
Test optimizes generalized 3D Clipping. The Clip unit examines the position of  
incoming vertices, and accepts/rejects 3D objects based on its Clip algorithm.  
Strips and Fans (SF) Stage  
The SF stage performs setup operations required to rasterize 3D objects. The outputs  
from the SF stage to the Windower stage contain implementation-specific information  
required for the rasterization of objects and also supports clipping of primitives to  
some extent.  
Windower / IZ (WIZ) Stage  
The WIZ unit performs an early depth test, which removes failing pixels and  
eliminates unnecessary processing overhead.  
The Windower uses the parameters provided by the SF unit in the object-specific  
rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of  
pixels. The Windower is also capable of performing dithering, whereby the illusion of a  
higher resolution when using low-bpp channels in color buffers is possible. Color  
dithering diffuses the sharp color bands seen on smooth-shaded objects.  
Video Engine  
The Video Engine handles the non-3D (media/video) applications. It includes support  
for VLD and MPEG2 decode in hardware.  
2D Engine  
The 2D Engine contains BLT (Block Level Transfer) functionality and an extensive set  
of 2D instructions. To take advantage of the 3D during engine’s functionality, some  
BLT functions make use of the 3D renderer.  
Processor Graphics VGA Registers  
The 2D registers consists of original VGA registers and others to support graphics  
modes that have color depths, resolutions, and hardware acceleration features that go  
beyond the original VGA standard.  
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Logical 128-Bit Fixed BLT and 256 Fill Engine  
This BLT engine accelerates the GUI of Microsoft Windows* operating systems. The  
128-bit BLT engine provides hardware acceleration of block transfers of pixel data for  
many common Windows operations. The BLT engine can be used for the following:  
Move rectangular blocks of data between memory locations  
Data alignment  
To perform logical operations (raster ops)  
The rectangular block of data does not change, as it is transferred between memory  
locations. The allowable memory transfers are between: cacheable system memory  
and frame buffer memory, frame buffer memory and frame buffer memory, and within  
system memory. Data to be transferred can consist of regions of memory, patterns, or  
solid color fills. A pattern is always 8 x 8 pixels wide and may be 8, 16, or 32 bits per  
pixel.  
The BLT engine expands monochrome data into a color depth of 8, 16, or 32 bits.  
BLTs can be either opaque or transparent. Opaque transfers move the data specified  
to the destination. Transparent transfers compare destination color to source color and  
write according to the mode of transparency selected.  
Data is horizontally and vertically aligned at the destination. If the destination for the  
BLT overlaps with the source memory location, the BLT engine specifies which area in  
memory to begin the BLT transfer. Hardware is included for all 256 raster operations  
(source, pattern, and destination) defined by Microsoft*, including transparent BLT.  
The BLT engine has instructions to invoke BLT and stretch BLT operations, permitting  
software to set up instruction buffers and use batch processing. The BLT engine can  
perform hardware clipping during BLTs.  
2.5.2  
Multi Graphics Controllers Multi-Monitor Support  
The processor supports simultaneous use of the Processor Graphics Controller (GT)  
and a x16 PCI Express* Graphics (PEG) device. The processor supports a maximum of  
2 displays connected to the PEG card in parallel with up to 2 displays connected to the  
processor and PCH.  
Note:  
When supporting Multi Graphics Multi Monitors, "drag and drop" between monitors and  
the 2x8PEG is not supported.  
2.6  
Digital Display Interface (DDI)  
The processor supports:  
— Three Digital Display (x4 DDI) interfaces that can be configured as  
DisplayPort*, HDMI*, or DVI. DisplayPort* can be configured to use 1, 2, or 4  
lanes depending on the bandwidth requirements and link data rate of RBR  
(1.62 GT/s), HBR (2.7 GT/s) and HBR2 (5.4 GT/s). When configured as  
HDMI*, DDIx4 port can support 2.97 GT/s. In addition, Digital Port D ( x4  
DDI) interface can also be configured to carry embedded DisplayPort*  
(eDPx4). Built-in displays are only supported on Digital Port D.  
— One dedicated Intel FDI Port for legacy VGA support on the PCH.  
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The HDMI* interface supports HDMI with 3D, 4K, Deep Color, and x.v.Color. The  
DisplayPort* interface supports the VESA DisplayPort* Standard Version 1,  
Revision 2.  
The processor supports High-bandwidth Digital Content Protection (HDCP) for  
high-definition content playback over digital interfaces.  
The processor also integrates dedicated a Mini HD audio controller to drive audio  
on integrated digital display interfaces, such as HDMI* and DisplayPort*. The HD  
audio controller on the PCH would continue to support down CODECs, and so on.  
The processor Mini HD audio controller supports two High-Definition Audio streams  
simultaneously on any of the three digital ports.  
The processor supports streaming any 3 independent and simultaneous display  
combination of DisplayPort*/HDMI*/DVI/eDP*/VGA monitors with the exception of  
3 simultaneous display support of HDMI*/DVI . In the case of 3 simultaneous  
displays, two High Definition Audio streams over the digital display interfaces are  
supported.  
Each digital port is capable of driving resolutions up to 3840x2160 at 60 Hz  
through DisplayPort* and 4096x2304 at 24 Hz/2560x1600 at 60 Hz using HDMI*.  
DisplayPort* Aux CH, DDC channel, Panel power sequencing, and HPD are  
supported through the PCH.  
Figure 6.  
Processor Display Architecture  
DP  
Aux  
Transcoder eDP*  
DP encoder  
eDP* Mux  
Timing, VDIP  
DPT, SRID  
Display  
Pipe A  
Transcoder A  
DP / HDMI  
Timing, VDIP  
FDI  
RX  
FDI  
DP /  
HDMI /  
DVI  
B
C
D
Transcoder B  
DP / HDMI  
Timing, VDIP  
Display  
Pipe B  
DP /  
HDMI /  
DVI  
Transcoder C  
DP / HDMI  
Timing, VDIP  
DP /  
HDMI /  
DVI / eDP  
Display  
Pipe C  
HD Audio  
Controller  
Audio  
Codec  
Display is the presentation stage of graphics. This involves:  
Pulling rendered data from memory  
Converting raw data into pixels  
Blending surfaces into a frame  
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Organizing pixels into frames  
Optionally scaling the image to the desired size  
Re-timing data for the intended target  
Formatting data according to the port output standard  
DisplayPort*  
DisplayPort* is a digital communication interface that uses differential signaling to  
achieve a high-bandwidth bus interface designed to support connections between PCs  
and monitors, projectors, and TV displays. DisplayPort* is also suitable for display  
connections between consumer electronics devices, such as high-definition optical disc  
players, set top boxes, and TV displays.  
A DisplayPort* consists of a Main Link, Auxiliary channel, and a Hot-Plug Detect signal.  
The Main Link is a unidirectional, high-bandwidth, and low latency channel used for  
transport of isochronous data streams such as uncompressed video and audio. The  
Auxiliary Channel (AUX CH) is a half-duplex bidirectional channel used for link  
management and device control. The Hot-Plug Detect (HPD) signal serves as an  
interrupt request for the sink device.  
The processor is designed in accordance with the VESA DisplayPort* Standard Version  
1.2a. The processor supports VESA DisplayPort* PHY Compliance Test Specification  
1.2a and VESA DisplayPort* Link Layer Compliance Test Specification 1.2a.  
Figure 7.  
DisplayPort* Overview  
Source Device  
DisplayPort Tx  
Sink Device  
DisplayPort Rx  
Main Link  
(Isochronous Streams)  
AUX CH  
(Link/Device Managemet)  
Hot-Plug Detect  
(Interrupt Request)  
High-Definition Multimedia Interface (HDMI*)  
The High-Definition Multimedia Interface* (HDMI*) is provided for transmitting  
uncompressed digital audio and video signals from DVD players, set-top boxes, and  
other audiovisual sources to television sets, projectors, and other video displays. It  
can carry high quality multi-channel audio data and all standard and high-definition  
consumer electronics video formats. The HDMI display interface connecting the  
processor and display devices uses transition minimized differential signaling (TMDS)  
to carry audiovisual information through the same HDMI cable.  
HDMI includes three separate communications channels — TMDS, DDC, and the  
optional CEC (consumer electronics control). CEC is not supported on the processor.  
As shown in the following figure, the HDMI cable carries four differential pairs that  
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make up the TMDS data and clock channels. These channels are used to carry video,  
audio, and auxiliary data. In addition, HDMI carries a VESA DDC. The DDC is used by  
an HDMI Source to determine the capabilities and characteristics of the Sink.  
Audio, video, and auxiliary (control/status) data is transmitted across the three TMDS  
data channels. The video pixel clock is transmitted on the TMDS clock channel and is  
used by the receiver for data recovery on the three data channels. The digital display  
data signals driven natively through the PCH are AC coupled and needs level shifting  
to convert the AC coupled signals to the HDMI compliant digital signals.  
The processor HDMI interface is designed in accordance with the High-Definition  
Multimedia Interface with 3D, 4K, Deep Color, and x.v.Color.  
Figure 8.  
HDMI* Overview  
HDMI Sink  
HDMI Source  
HDMI Tx  
HDMI Rx  
TMDS Data Channel 0  
l 1  
TMDS Data Channe  
TMDS Data Channel 2  
TMDS Clock Channel  
Hot-Plug Detect  
Display Data Channel (DDC)  
CEC Line (optional)  
Digital Video Interface  
The processor Digital Ports can be configured to drive DVI-D. DVI uses TMDS for  
transmitting data from the transmitter to the receiver, which is similar to the HDMI  
protocol except for the audio and CEC. Refer to the HDMI section for more information  
on the signals and data transmission. To drive DVI-I through the back panel the VGA  
DDC signals are connected along with the digital data and clock signals from one of  
the Digital Ports. When a system has support for a DVI-I port, then either VGA or the  
DVI-D through a single DVI-I connector can be driven, but not both simultaneously.  
The digital display data signals driven natively through the processor are AC coupled  
and need level shifting to convert the AC coupled signals to the HDMI compliant digital  
signals.  
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embedded DisplayPort*  
embedded DisplayPort* (eDP*) is an embedded version of the DisplayPort standard  
oriented towards applications such as notebook and All-In-One PCs. Digital Port D can  
be configured as eDP. Like DisplayPort, embedded DisplayPort also consists of a Main  
Link, Auxiliary channel, and an optional Hot-Plug Detect signal.  
The eDP on the processor can be configured for 2 or 4 lanes.  
The processor supports embedded DisplayPort* (eDP*) Standard Version 1.2 and  
VESA embedded DisplayPort* Standard Version 1.2.  
Integrated Audio  
HDMI and display port interfaces carry audio along with video.  
Processor supports two DMA controllers to output two High Definition audio  
streams on two digital ports simultaneously.  
Supports only the internal HDMI and DP CODECs.  
Table 8.  
Processor Supported Audio Formats over HDMI*and DisplayPort*  
Audio Formats  
HDMI*  
Yes  
DisplayPort*  
AC-3 Dolby* Digital  
Dolby Digital Plus  
DTS-HD*  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
LPCM, 192 kHz/24 bit, 8 Channel  
Yes  
Dolby TrueHD, DTS-HD Master Audio*  
(Lossless Blu-Ray Disc* Audio Format)  
Yes  
Yes  
The processor will continue to support Silent stream. Silent stream is an integrated  
audio feature that enables short audio streams, such as system events to be heard  
over the HDMI and DisplayPort monitors. The processor supports silent streams over  
the HDMI and DisplayPort interfaces at 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,  
176.4 kHz, and 192 kHz sampling rates.  
Multiple Display Configurations  
The following multiple display configuration modes are supported (with appropriate  
driver software):  
Single Display is a mode with one display port activated to display the output to  
one display device.  
Intel Display Clone is a mode with up to three display ports activated to drive the  
display content of same color depth setting but potentially different refresh rate  
and resolution settings to all the active display devices connected.  
Extended Desktop is a mode with up to three display ports activated to drive the  
content with potentially different color depth, refresh rate, and resolution settings  
on each of the active display devices connected.  
The digital ports on the processor can be configured to support DisplayPort*/HDMI/  
DVI. For Desktop designs, digital port D can be configured as eDPx4 in addition to  
dedicated x2 port for Intel FDI for VGA. The following table shows examples of valid  
three display configurations through the processor.  
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Table 9.  
Valid Three Display Configurations through the Processor  
Display 1  
Display 2  
Display 3  
Maximum  
Resolution Display  
1
Maximum  
Resolution  
Display 2  
Maximum  
Resolution Display  
3
4096x2304 @ 24 Hz  
HDMI  
HDMI  
DP  
3840x2160 @ 60 Hz  
3840x2160 @ 60 Hz  
2560x1600 @ 60 Hz  
DVI  
DP  
DVI  
DP  
DP  
DP  
1920x1200 @ 60 Hz  
3840x2160 @ 60 Hz  
4096x2304 @ 24 Hz  
2560x1600 @ 60 Hz  
3840x2160 @  
60 Hz  
VGA  
DP  
HDMI  
1920x1200 @ 60 Hz  
4096x2304 @ 24 Hz  
2560x1600 @ 60 Hz  
3840x2160 @  
60 Hz  
eDP  
eDP  
eDP  
DP  
DP  
HDMI  
DP  
3840x2160 @ 60 Hz  
3840x2160 @ 60 Hz  
3840x2160 @ 60 Hz  
3840x2160 @ 60 Hz  
4096x2304 @ 24 Hz  
2560x1600 @ 60 Hz  
HDMI  
HDMI  
Notes: 1. Requires support of 2 channel DDR3/DDR3L 1600 MT/s configuration for driving 3 simultaneous  
3840x2160 @ 60 Hz display resolutions  
2. DP and eDP resolutions in the above table are supported for 4 lanes with link data rate HBR2.  
The following table shows the DP/eDP resolutions supported for 1, 2, or 4 lanes  
depending on link data rate of RBR, HBR, and HBR2.  
Table 10.  
DisplayPort and embedded DisplayPort* Resolutions for 1, 2, 4 Lanes – Link  
Data Rate of RBR, HBR, and HBR2  
Link Data Rate  
Lane Count  
2
1
4
RBR  
HBR  
1064x600  
1280x960  
1920x1200  
1400x1050  
1920x1200  
2880x1800  
2240x1400  
2880x1800  
3840x2160  
HBR2  
Any 3 displays can be supported simultaneously using the following rules:  
Maximum of 2 HDMIs  
Maximum of 2 DVIs  
Maximum of 1 HDMI and 1 DVI  
Any 3 DisplayPort  
One VGA  
One eDP  
High-bandwidth Digital Content Protection (HDCP)  
HDCP is the technology for protecting high-definition content against unauthorized  
copy or unreceptive between a source (computer, digital set top boxes, and so on)  
and the sink (panels, monitor, and TVs). The processor supports HDCP 1.4 for content  
protection over wired displays (HDMI*, DVI, and DisplayPort*).  
The HDCP 1.4 keys are integrated into the processor and customers are not required  
to physically configure or handle the keys.  
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2.7  
Intel® Flexible Display Interface (Intel® FDI)  
The Intel Flexible Display Interface (Intel FDI) passes display data from the  
processor (source) to the PCH (sink) for display through a display interface on the  
PCH.  
Intel FDI supports 2 lanes at 2.7 GT/s fixed frequency. This can be configured to 1  
or 2 lanes depending on the bandwidth requirements.  
Intel FDI supports 8 bits per color only.  
Side band sync pin (FDI_CSYNC).  
Side band interrupt pin (DISP_INT). This carries combined interrupt for HPDs of all  
the ports, AUX and I2C completion events, and so on.  
Intel FDI is not encrypted as it drives only VGA and content protection is not  
supported on VGA.  
2.8  
Platform Environmental Control Interface (PECI)  
PECI is an Intel proprietary interface that provides a communication channel between  
Intel processors and external components, like Super I/O (SIO) and Embedded  
Controllers (EC), to provide processor temperature, Turbo, TDP, and memory  
throttling control mechanisms and many other services. PECI is used for platform  
thermal management and real time control and configuration of processor features  
and performance.  
2.8.1  
PECI Bus Architecture  
The PECI architecture is based on a wired-OR bus that the clients (as processor PECI)  
can pull up high (with strong drive).  
The idle state on the bus is near zero.  
The following figure demonstrates PECI design and connectivity. While the host/  
originator can be a third party PECI host, one of the PECI clients is a processor PECI  
device.  
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Figure 9.  
PECI Host-Clients Connection Example  
VTT  
VTT  
Q3  
nX  
Q1  
nX  
PECI  
Q2  
1X  
CPECI  
<10pF/Node  
PECI Client  
Host / Originator  
Additional  
PECI Clients  
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3.0  
Technologies  
This chapter provides a high-level description of Intel technologies implemented in the  
processor.  
The implementation of the features may vary between the processor SKUs.  
Details on the different technologies of Intel processors and other relevant external  
notes are located at the Intel technology web site: http://www.intel.com/technology/  
3.1  
Intel® Virtualization Technology (Intel® VT)  
Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple  
independent systems to software. This allows multiple, independent operating systems  
to run simultaneously on a single system. Intel VT comprises technology components  
to support virtualization of platforms based on Intel architecture microprocessors and  
chipsets.  
Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel®  
Architecture (Intel® VT-x) added hardware support in the processor to improve the  
virtualization performance and robustness. Intel® Virtualization Technology for  
Directed I/O (Intel VT-d) extends Intel® VT-x by adding hardware assisted support to  
improve I/O device virtualization performance.  
Intel® VT-x specifications and functional descriptions are included in the Intel® 64 and  
IA-32 Architectures Software Developer’s Manual, Volume 3B and is available at:  
The Intel VT-d specification and other Intel VT documents can be referenced at:  
Intel® VT-x Objectives  
Intel VT-x provides hardware acceleration for virtualization of IA platforms. Virtual  
Machine Monitor (VMM) can use Intel VT-x features to provide an improved reliable  
virtualized platform. By using Intel VT-x, a VMM is:  
Robust: VMMs no longer need to use paravirtualization or binary translation. This  
means that off-the-shelf operating systems and applications can be run without  
any special steps.  
Enhanced: Intel VT enables VMMs to run 64-bit guest operating systems on IA  
x86 processors.  
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More reliable: Due to the hardware support, VMMs can now be smaller, less  
complex, and more efficient. This improves reliability and availability and reduces  
the potential for software conflicts.  
More secure: The use of hardware transitions in the VMM strengthens the  
isolation of VMs and further prevents corruption of one VM from affecting others  
on the same system.  
Intel® VT-x Features  
The processor supports the following Intel VT-x features:  
Extended Page Table (EPT) Accessed and Dirty Bits  
— EPT A/D bits enabled VMMs to efficiently implement memory management and  
page classification algorithms to optimize VM memory operations, such as de-  
fragmentation, paging, live migration, and check-pointing. Without hardware  
support for EPT A/D bits, VMMs may need to emulate A/D bits by marking EPT  
paging-structures as not-present or read-only, and incur the overhead of EPT  
page-fault VM exits and associated software processing.  
Extended Page Table Pointer (EPTP) switching  
— EPTP switching is a specific VM function. EPTP switching allows guest software  
(in VMX non-root operation, supported by EPT) to request a different EPT  
paging-structure hierarchy. This is a feature by which software in VMX non-  
root operation can request a change of EPTP without a VM exit. Software can  
choose among a set of potential EPTP values determined in advance by  
software in VMX root operation.  
Pause loop exiting  
— Support VMM schedulers seeking to determine when a virtual processor of a  
multiprocessor virtual machine is not performing useful work. This situation  
may occur when not all virtual processors of the virtual machine are currently  
scheduled and when the virtual processor in question is in a loop involving the  
PAUSE instruction. The new feature allows detection of such loops and is thus  
called PAUSE-loop exiting.  
The processor core supports the following Intel VT-x features:  
Extended Page Tables (EPT)  
— EPT is hardware assisted page table virtualization.  
— It eliminates VM exits from the guest operating system to the VMM for shadow  
page-table maintenance.  
Virtual Processor IDs (VPID)  
— Ability to assign a VM ID to tag processor core hardware structures (such as  
TLBs).  
— This avoids flushes on VM transitions to give a lower-cost VM transition time  
and an overall reduction in virtualization overhead.  
Guest Preemption Timer  
— Mechanism for a VMM to preempt the execution of a guest operating system  
after an amount of time specified by the VMM. The VMM sets a timer value  
before entering a guest.  
— The feature aids VMM developers in flexibility and Quality of Service (QoS)  
guarantees.  
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Descriptor-Table Exiting  
— Descriptor-table exiting allows a VMM to protect a guest operating system  
from an internal (malicious software based) attack by preventing relocation of  
key system data structures like IDT (interrupt descriptor table), GDT (global  
descriptor table), LDT (local descriptor table), and TSS (task segment  
selector).  
— A VMM using this feature can intercept (by a VM exit) attempts to relocate  
these data structures and prevent them from being tampered by malicious  
software.  
Intel® VT-d Objectives  
The key Intel VT-d objectives are domain-based isolation and hardware-based  
virtualization. A domain can be abstractly defined as an isolated environment in a  
platform to which a subset of host physical memory is allocated. Intel VT-d provides  
accelerated I/O performance for a virtualized platform and provides software with the  
following capabilities:  
I/O device assignment and security: for flexibly assigning I/O devices to VMs and  
extending the protection and isolation properties of VMs for I/O operations.  
DMA remapping: for supporting independent address translations for Direct  
Memory Accesses (DMA) from devices.  
Interrupt remapping: for supporting isolation and routing of interrupts from  
devices and external interrupt controllers to appropriate VMs.  
Reliability: for recording and reporting to system software DMA and interrupt  
errors that may otherwise corrupt memory or impact VM isolation.  
Intel VT-d accomplishes address translation by associating a transaction from a given  
I/O device to a translation table associated with the Guest to which the device is  
assigned. It does this by means of the data structure in the following illustration. This  
table creates an association between the device's PCI Express* Bus/Device/Function  
(B/D/F) number and the base address of a translation table. This data structure is  
populated by a VMM to map devices to translation tables in accordance with the device  
assignment restrictions above, and to include a multi-level translation table (VT-d  
Table) that contains Guest specific address translations.  
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Figure 10.  
Device to Domain Mapping Structures  
(Dev 31, Func 7)  
Context entry 255  
(Dev 0, Func 1)  
(Dev 0, Func 0)  
Context entry 0  
Context entry Table  
For bus N  
Address Translation  
Structures for Domain A  
(Bus 255)  
(Bus N)  
Root entry 255  
Root entry N  
(Bus 0)  
Root entry 0  
Root entry table  
Context entry 255  
Context entry 0  
Address Translation  
Structures for Domain B  
Context entry Table  
For bus 0  
Intel VT-d functionality, often referred to as an Intel VT-d Engine, has typically been  
implemented at or near a PCI Express host bridge component of a computer system.  
This might be in a chipset component or in the PCI Express functionality of a processor  
with integrated I/O. When one such Intel VT-d engine receives a PCI Express  
transaction from a PCI Express bus, it uses the B/D/F number associated with the  
transaction to search for an Intel VT-d translation table. In doing so, it uses the B/D/F  
number to traverse the data structure shown in the above figure. If it finds a valid  
Intel VT-d table in this data structure, it uses that table to translate the address  
provided on the PCI Express bus. If it does not find a valid translation table for a given  
translation, this results in an Intel VT-d fault. If Intel VT-d translation is required, the  
Intel VT-d engine performs an N-level table walk.  
For more information, refer to Intel® Virtualization Technology for Directed I/O  
Intel® VT-d Features  
The processor supports the following Intel VT-d features:  
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Memory controller and processor graphics comply with the Intel VT-d 1.2  
Specification  
Two Intel VT-d DMA remap engines  
— iGFX DMA remap engine  
— Default DMA remap engine (covers all devices except iGFX)  
Support for root entry, context entry, and default context  
39-bit guest physical address and host physical address widths  
Support for 4 KB page sizes  
Support for register-based fault recording only (for single entry only) and support  
for MSI interrupts for faults  
Support for both leaf and non-leaf caching  
Support for boot protection of default page table  
Support for non-caching of invalid page table entries  
Support for hardware-based flushing of translated but pending writes and pending  
reads, on IOTLB invalidation  
Support for Global, Domain specific, and Page specific IOTLB invalidation  
MSI cycles (MemWr to address FEEx_xxxxh) not translated  
— Translation faults result in cycle forwarding to VBIOS region (byte enables  
masked for writes). Returned data may be bogus for internal agents; PEG/DMI  
interfaces return unsupported request status  
Interrupt remapping is supported  
Queued invalidation is supported  
Intel VT-d translation bypass address range is supported (Pass Through)  
The processor supports the following added new Intel VT-d features:  
4-level Intel VT-d Page walk: Both default Intel VT-d engine, as well as the IGD  
Intel VT-d engine, are upgraded to support 4-level Intel VT-d tables (adjusted  
guest address width 48 bits)  
Intel VT-d superpage: support of Intel VT-d superpage (2 MB, 1 GB) for the  
default Intel VT-d engine (that covers all devices except IGD)  
IGD Intel VT-d engine does not support superpage and BIOS should disable  
superpage in default Intel VT-d engine when iGFX is enabled.  
Note:  
Intel VT-d Technology may not be available on all SKUs.  
3.2  
Intel® Trusted Execution Technology (Intel® TXT)  
Intel Trusted Execution Technology (Intel TXT) defines platform-level enhancements  
that provide the building blocks for creating trusted platforms.  
The Intel TXT platform helps to provide the authenticity of the controlling environment  
such that those wishing to rely on the platform can make an appropriate trust  
decision. The Intel TXT platform determines the identity of the controlling environment  
by accurately measuring and verifying the controlling software.  
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Another aspect of the trust decision is the ability of the platform to resist attempts to  
change the controlling environment. The Intel TXT platform will resist attempts by  
software processes to change the controlling environment or bypass the bounds set by  
the controlling environment.  
Intel TXT is a set of extensions designed to provide a measured and controlled launch  
of system software that will then establish a protected environment for itself and any  
additional software that it may execute.  
These extensions enhance two areas:  
The launching of the Measured Launched Environment (MLE).  
The protection of the MLE from potential corruption.  
The enhanced platform provides these launch and control interfaces using Safer Mode  
Extensions (SMX).  
The SMX interface includes the following functions:  
Measured/Verified launch of the MLE.  
Mechanisms to ensure the above measurement is protected and stored in a secure  
location.  
Protection mechanisms that allow the MLE to control attempts to modify itself.  
The processor also offers additional enhancements to System Management Mode  
(SMM) architecture for enhanced security and performance. The processor provides  
new MSRs to:  
Enable a second SMM range  
Enable SMM code execution range checking  
Select whether SMM Save State is to be written to legacy SMRAM or to MSRs  
Determine if a thread is going to be delayed entering SMM  
Determine if a thread is blocked from entering SMM  
Targeted SMI, enable/disable threads from responding to SMIs both VLWs and IPI  
For the above features, BIOS must test the associated capability bit before attempting  
to access any of the above registers.  
For more information, refer to the Intel® Trusted Execution Technology Measured  
3.3  
Intel® Hyper-Threading Technology (Intel® HT  
Technology)  
The processor supports Intel Hyper-Threading Technology (Intel HT Technology) that  
allows an execution core to function as two logical processors. While some execution  
resources, such as caches, execution units, and buses are shared, each logical  
processor has its own architectural state with its own set of general-purpose registers  
and control registers. This feature must be enabled using the BIOS and requires  
operating system support.  
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Intel recommends enabling Intel HT Technology with Microsoft Windows* 8 and  
Microsoft Windows* 7 and disabling Intel HT Technology using the BIOS for all  
previous versions of Windows* operating systems. For more information on Intel HT  
3.4  
Intel® Turbo Boost Technology 2.0  
The Intel Turbo Boost Technology 2.0 allows the processor core to opportunistically  
and automatically run faster than its rated operating frequency/render clock, if it is  
operating below power, temperature, and current limits. The Intel Turbo Boost  
Technology 2.0 feature is designed to increase performance of both multi-threaded  
and single-threaded workloads.  
Maximum frequency is dependant on the SKU and number of active cores. No special  
hardware support is necessary for Intel Turbo Boost Technology 2.0. BIOS and the  
operating system can enable or disable Intel Turbo Boost Technology 2.0.  
Compared with previous generation products, Intel Turbo Boost Technology 2.0 will  
increase the ratio of application power to TDP. Thus, thermal solutions and platform  
cooling that are designed to less than thermal design guidance might experience  
thermal and performance issues since more applications will tend to run at the  
maximum power limit for significant periods of time.  
Note:  
Intel Turbo Boost Technology 2.0 may not be available on all SKUs.  
Intel® Turbo Boost Technology 2.0 Frequency  
The processor rated frequency assumes that all execution cores are running an  
application at the thermal design power (TDP). However, under typical operation, not  
all cores are active. Therefore, most applications are consuming less than the TDP at  
the rated frequency. To take advantage of the available thermal headroom, the active  
cores can increase their operating frequency.  
To determine the highest performance frequency amongst active cores, the processor  
takes the following into consideration:  
The number of cores operating in the C0 state.  
The estimated core current consumption.  
The estimated package prior and present power consumption.  
The package temperature.  
Any of these factors can affect the maximum frequency for a given workload. If the  
power, current, or thermal limit is reached, the processor will automatically reduce the  
frequency to stay within its TDP limit. Turbo processor frequencies are only active if  
the operating system is requesting the P0 state. For more information on P-states and  
C-states, see Power Management on page 49.  
3.5  
Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)  
Intel Advanced Vector Extensions 2.0 (Intel AVX2) is the latest expansion of the Intel  
instruction set. Intel AVX2 extends the Intel Advanced Vector Extensions (Intel AVX)  
with 256-bit integer instructions, floating-point fused multiply add (FMA) instructions,  
and gather operations. The 256-bit integer vectors benefit math, codec, image, and  
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digital signal processing software. FMA improves performance in face detection,  
professional imaging, and high performance computing. Gather operations increase  
vectorization opportunities for many applications. In addition to the vector extensions,  
this generation of Intel processors adds new bit manipulation instructions useful in  
compression, encryption, and general purpose software.  
For more information on Intel AVX, see http://www.intel.com/software/avx  
3.6  
Intel® Advanced Encryption Standard New Instructions  
(Intel® AES-NI)  
The processor supports Intel Advanced Encryption Standard New Instructions (Intel  
AES-NI) that are a set of Single Instruction Multiple Data (SIMD) instructions that  
enable fast and secure data encryption and decryption based on the Advanced  
Encryption Standard (AES). Intel AES-NI are valuable for a wide range of  
cryptographic applications, such as applications that perform bulk encryption/  
decryption, authentication, random number generation, and authenticated encryption.  
AES is broadly accepted as the standard for both government and industry  
applications, and is widely deployed in various protocols.  
Intel AES-NI consists of six Intel SSE instructions. Four instructions, AESENC,  
AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES encryption  
and decryption. The other two, AESIMC and AESKEYGENASSIST, support the AES key  
expansion procedure. Together, these instructions provide a full hardware for  
supporting AES; offering security, high performance, and a great deal of flexibility.  
PCLMULQDQ Instruction  
The processor supports the carry-less multiplication instruction, PCLMULQDQ.  
PCLMULQDQ is a Single Instruction Multiple Data (SIMD) instruction that computes the  
128-bit carry-less multiplication of two, 64-bit operands without generating and  
propagating carries. Carry-less multiplication is an essential processing component of  
several cryptographic systems and standards. Hence, accelerating carry-less  
multiplication can significantly contribute to achieving high speed secure computing  
and communication.  
Intel® Secure Key  
The processor supports Intel® Secure Key (formerly known as Digital Random Number  
Generator (DRNG)), a software visible random number generation mechanism  
supported by a high quality entropy source. This capability is available to  
programmers through the RDRAND instruction. The resultant random number  
generation capability is designed to comply with existing industry standards in this  
regard (ANSI X9.82 and NIST SP 800-90).  
Some possible usages of the RDRAND instruction include cryptographic key generation  
as used in a variety of applications, including communication, digital signatures,  
secure storage, and so on.  
3.7  
Intel® Transactional Synchronization Extensions - New  
Instructions (Intel® TSX-NI)  
Intel Transactional Synchronization Extensions - New Instructions (Intel TSX-NI). Intel  
TSX-NI provides a set of instruction extensions that allow programmers to specify  
regions of code for transactional synchronization. Programmers can use these  
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extensions to achieve the performance of fine-grain locking while actually  
programming using coarse-grain locks. Details on Intel TSX-NI are in the Intel®  
Architecture Instruction Set Extensions Programming Reference.  
3.8  
Intel® 64 Architecture x2APIC  
The x2APIC architecture extends the xAPIC architecture that provides key  
mechanisms for interrupt delivery. This extension is primarily intended to increase  
processor addressability.  
Specifically, x2APIC:  
Retains all key elements of compatibility to the xAPIC architecture:  
— Delivery modes  
— Interrupt and processor priorities  
— Interrupt sources  
— Interrupt destination types  
Provides extensions to scale processor addressability for both the logical and  
physical destination modes  
Adds new features to enhance performance of interrupt delivery  
Reduces complexity of logical destination mode interrupt delivery on link based  
architectures  
The key enhancements provided by the x2APIC architecture over xAPIC are the  
following:  
Support for two modes of operation to provide backward compatibility and  
extensibility for future platform innovations:  
— In xAPIC compatibility mode, APIC registers are accessed through memory  
mapped interface to a 4K-Byte page, identical to the xAPIC architecture.  
— In x2APIC mode, APIC registers are accessed through Model Specific Register  
(MSR) interfaces. In this mode, the x2APIC architecture provides significantly  
increased processor addressability and some enhancements on interrupt  
delivery.  
Increased range of processor addressability in x2APIC mode:  
— Physical xAPIC ID field increases from 8 bits to 32 bits, allowing for interrupt  
processor addressability up to 4G–1 processors in physical destination mode.  
A processor implementation of x2APIC architecture can support fewer than 32-  
bits in a software transparent fashion.  
— Logical xAPIC ID field increases from 8 bits to 32 bits. The 32-bit logical  
x2APIC ID is partitioned into two sub-fields – a 16-bit cluster ID and a 16-bit  
logical ID within the cluster. Consequently, ((2^20) – 16) processors can be  
addressed in logical destination mode. Processor implementations can support  
fewer than 16 bits in the cluster ID sub-field and logical ID sub-field in a  
software agnostic fashion.  
More efficient MSR interface to access APIC registers:  
— To enhance inter-processor and self-directed interrupt delivery as well as the  
ability to virtualize the local APIC, the APIC register set can be accessed only  
through MSR-based interfaces in x2APIC mode. The Memory Mapped IO  
(MMIO) interface used by xAPIC is not supported in x2APIC mode.  
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The semantics for accessing APIC registers have been revised to simplify the  
programming of frequently-used APIC registers by system software. Specifically,  
the software semantics for using the Interrupt Command Register (ICR) and End  
Of Interrupt (EOI) registers have been modified to allow for more efficient delivery  
and dispatching of interrupts.  
The x2APIC extensions are made available to system software by enabling the  
local x2APIC unit in the “x2APIC” mode. To benefit from x2APIC capabilities, a  
new operating system and a new BIOS are both needed, with special support for  
x2APIC mode.  
The x2APIC architecture provides backward compatibility to the xAPIC architecture  
and forward extendible for future Intel platform innovations.  
Note:  
Intel x2APIC Technology may not be available on all SKUs.  
For more information, see the Intel® 64 Architecture x2APIC Specification at http://  
3.9  
Power Aware Interrupt Routing (PAIR)  
The processor includes enhanced power-performance technology that routes  
interrupts to threads or cores based on their sleep states. As an example, for energy  
savings, it routes the interrupt to the active cores without waking the deep idle cores.  
For performance, it routes the interrupt to the idle (C1) cores without interrupting the  
already heavily loaded cores. This enhancement is mostly beneficial for high-interrupt  
scenarios like Gigabit LAN, WLAN peripherals, and so on.  
3.10  
3.11  
Execute Disable Bit  
The Execute Disable Bit allows memory to be marked as executable when combined  
with a supporting operating system. If code attempts to run in non-executable  
memory, the processor raises an error to the operating system. This feature can  
prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities  
and can thus help improve the overall security of the system. See the Intel® 64 and  
IA-32 Architectures Software Developer's Manuals for more detailed information.  
Supervisor Mode Execution Protection (SMEP)  
The processor introduces a new mechanism that provides the next level of system  
protection by blocking malicious software attacks from user mode code when the  
system is running in the highest privilege level. This technology helps to protect from  
virus attacks and unwanted code from harming the system. For more information,  
refer to Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A  
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4.0  
Power Management  
This chapter provides information on the following power management topics:  
Advanced Configuration and Power Interface (ACPI) States  
Processor Core  
Integrated Memory Controller (IMC)  
PCI Express*  
Direct Media Interface (DMI)  
Processor Graphics Controller  
Figure 11.  
Processor Power States  
G0 - Working  
S0 Processor Fully powered on (full on mode / connected standby mode)  
C0 Active mode  
P0  
Pn  
C1 Auto Halt  
C1E Auto Halt, Low freq, low voltage  
C3 L1/L2 caches flush, clocks off  
C6 Save core states before shutdown  
C7 Similar to C6, L3 flush  
G1 Sleeping  
S3 Cold Sleep Suspend to Ram (STR)  
S4 Hibernate Suspend to Disk (STD), Wakeup on PCH  
S5 Soft Off no power, Wakeup on PCH  
G3 Mechanical OFF  
Note: Power states availability may vary between the different SKUs  
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4.1  
Advanced Configuration and Power Interface (ACPI)  
States Supported  
This section describes the ACPI states supported by the processor.  
System States  
Table 11.  
State  
Description  
G0/S0  
Full On Mode.  
Suspend-to-RAM (STR). Context saved to memory (S3-Hot state is not supported by the  
processor).  
G1/S3-Cold  
G1/S4  
G2/S5  
G3  
Suspend-to-Disk (STD). All power lost (except wakeup on PCH).  
Soft off. All power lost (except wakeup on PCH). Total reboot.  
Mechanical off. All power removed from system.  
Table 12.  
Processor Core / Package State Support  
State  
Description  
Active mode, processor executing code.  
C0  
C1  
AutoHALT state.  
C1E  
AutoHALT state with lowest frequency and voltage operating point.  
Execution cores in C3 state flush their L1 instruction cache, L1 data cache, and L2 cache  
to the L3 shared cache. Clocks are shut off to each core.  
C3  
C6  
Execution cores in this state save their architectural state before removing core voltage.  
Execution cores in this state behave similarly to the C6 state. If all execution cores  
request C7 state, L3 cache ways are flushed until it is cleared. If the entire L3 cache is  
flushed, voltage will be removed from the L3 cache. Power removal to SA, Cores and L3  
will reduce power consumption. C7 may not be available on all SKUs.  
C7  
Table 13.  
Integrated Memory Controller States  
State  
Description  
Power up  
CKE asserted. Active mode.  
Pre-charge  
Power-down  
CKE de-asserted (not self-refresh) with all banks closed.  
CKE de-asserted (not self-refresh) with minimum one bank active.  
CKE de-asserted using device self-refresh.  
Active Power-  
down  
Self-Refresh  
Table 14.  
PCI Express* Link States  
State  
Description  
L0  
L0s  
L1  
Full on – Active transfer state.  
First Active Power Management low-power state – Low exit latency.  
Lowest Active Power Management – Longer exit latency.  
Lowest power state (power-off) – Longest exit latency.  
L3  
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Table 15.  
Direct Media Interface (DMI) States  
State  
L0  
Description  
Full on – Active transfer state.  
L0s  
L1  
First Active Power Management low-power state – Low exit latency.  
Lowest Active Power Management – Longer exit latency.  
Lowest power state (power-off) – Longest exit latency.  
L3  
Table 16.  
G, S, and C Interface State Combinations  
Global  
(G)  
State  
Sleep (S)  
State  
Processor  
Package (C)  
State  
Processor  
State  
System Clocks  
Description  
G0  
G0  
G0  
S0  
S0  
S0  
C0  
C1/C1E  
C3  
Full On  
Auto-Halt  
Deep Sleep  
On  
On  
On  
Full On  
Auto-Halt  
Deep Sleep  
Deep Power-  
down  
G0  
S0  
C6/C7  
On  
Deep Power-down  
G1  
G1  
G2  
G3  
S3  
S4  
S5  
NA  
Power off  
Power off  
Power off  
Power off  
Off, except RTC  
Off, except RTC  
Off, except RTC  
Power off  
Suspend to RAM  
Suspend to Disk  
Soft Off  
Hard off  
Table 17.  
D, S, and C Interface State Combination  
Graphics  
Adapter (D)  
State  
Sleep (S)  
State  
Package (C)  
State  
Description  
D0  
D0  
D0  
D0  
D3  
D3  
D3  
S0  
S0  
S0  
S0  
S0  
S3  
S4  
C0  
C1/C1E  
C3  
Full On, Displaying.  
Auto-Halt, Displaying.  
Deep sleep, Displaying.  
Deep Power-down, Displaying.  
Not displaying.  
C6/C7  
Any  
N/A  
Not displaying, Graphics Core is powered off.  
Not displaying, suspend to disk.  
N/A  
4.2  
Processor Core Power Management  
While executing code, Enhanced Intel SpeedStep® Technology optimizes the  
processor’s frequency and core voltage based on workload. Each frequency and  
voltage operating point is defined by ACPI as a P-state. When the processor is not  
executing code, it is idle. A low-power idle state is defined by ACPI as a C-state. In  
general, deeper power C-states have longer entry and exit latencies.  
4.2.1  
Enhanced Intel® SpeedStep® Technology Key Features  
The following are the key features of Enhanced Intel SpeedStep Technology:  
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Multiple frequency and voltage points for optimal performance and power  
efficiency. These operating points are known as P-states.  
Frequency selection is software controlled by writing to processor MSRs. The  
voltage is optimized based on the selected frequency and the number of active  
processor cores.  
— Once the voltage is established, the PLL locks on to the target frequency.  
— All active processor cores share the same frequency and voltage. In a multi-  
core processor, the highest frequency P-state requested among all active  
cores is selected.  
— Software-requested transitions are accepted at any time. If a previous  
transition is in progress, the new transition is deferred until the previous  
transition is completed.  
The processor controls voltage ramp rates internally to ensure glitch-free  
transitions.  
Because there is low transition latency between P-states, a significant number of  
transitions per-second are possible.  
4.2.2  
Low-Power Idle States  
When the processor is idle, low-power idle states (C-states) are used to save power.  
More power savings actions are taken for numerically higher C-states. However,  
higher C-states have longer exit and entry latencies. Resolution of C-states occur at  
the thread, processor core, and processor package level. Thread-level C-states are  
available if Intel Hyper-Threading Technology is enabled.  
Caution:  
Long term reliability cannot be assured unless all the Low-Power Idle States are  
enabled.  
Figure 12.  
Idle Power Management Breakdown of the Processor Cores  
Thread 0  
Thread 1  
Thread 0  
Thread 1  
Core 0 State  
Core N State  
Processor Package State  
Entry and exit of the C-states at the thread and core level are shown in the following  
figure.  
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Figure 13.  
Thread and Core C-State Entry and Exit  
C0  
MWAIT(C1), HLT  
MWAIT(C1), HLT  
MWAIT(C7),  
P_LVL4 I/O Read  
MWAIT(C6),  
P_LVL3 I/O Read  
(C1E Enabled)  
MWAIT(C3),  
P_LVL2 I/O Read  
C1  
C1E  
C3  
C6  
C7  
While individual threads can request low-power C-states, power saving actions only  
take place once the core C-state is resolved. Core C-states are automatically resolved  
by the processor. For thread and core C-states, a transition to and from C0 is required  
before entering any other C-state.  
Table 18.  
Coordination of Thread Power States at the Core Level  
Processor Core C-State  
Thread 1  
C3  
C0  
C0  
C0  
C0  
C0  
C0  
C1  
C0  
C6  
C0  
C11  
C3  
C6  
C6  
C7  
C0  
C11  
C3  
C6  
C7  
C0  
C1  
C0  
C11  
C11  
C11  
C11  
C11  
C3  
Thread 0  
C3  
C6  
C7  
C3  
C3  
Note: 1. If enabled, the core C-state will be C1E if all cores have resolved a core C1 state or higher.  
4.2.3  
Requesting Low-Power Idle States  
The primary software interfaces for requesting low-power idle states are through the  
MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).  
However, software may make C-state requests using the legacy method of I/O reads  
from the ACPI-defined processor clock control registers, referred to as P_LVLx. This  
method of requesting C-states provides legacy support for operating systems that  
initiate C-state transitions using I/O reads.  
For legacy operating systems, P_LVLx I/O reads are converted within the processor to  
the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result  
in I/O reads to the system. The feature, known as I/O MWAIT redirection, must be  
enabled in the BIOS.  
The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict  
the range of I/O addresses that are trapped and emulate MWAIT like functionality.  
Any P_LVLx reads outside of this range do not cause an I/O redirection to MWAIT(Cx)  
like request. The reads fall through like a normal I/O instruction.  
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Note:  
When P_LVLx I/O instructions are used, MWAIT sub-states cannot be defined. The  
MWAIT sub-state is always zero if I/O MWAIT redirection is used. By default, P_LVLx  
I/O redirections enable the MWAIT 'break on EFLAGS.IF’ feature that triggers a  
wakeup on an interrupt, even if interrupts are masked by EFLAGS.IF.  
4.2.4  
Core C-State Rules  
The following are general rules for all core C-states, unless specified otherwise:  
A core C-state is determined by the lowest numerical thread state (such as Thread  
0 requests C1E state while Thread 1 requests C3 state, resulting in a core C1E  
state). See the G, S, and C Interface State Combinations table.  
A core transitions to C0 state when:  
— An interrupt occurs  
— There is an access to the monitored address if the state was entered using an  
MWAIT/Timed MWAIT instruction  
— The deadline corresponding to the Timed MWAIT instruction expires  
An interrupt directed toward a single thread wakes only that thread.  
If any thread in a core is in active (in C0 state), the core's C-state will resolve to  
C0 state.  
Any interrupt coming into the processor package may wake any core.  
A system reset re-initializes all processor cores.  
Core C0 State  
The normal operating state of a core where code is being executed.  
Core C1/C1E State  
C1/C1E is a low power state entered when all threads within a core execute a HLT or  
MWAIT(C1/C1E) instruction.  
A System Management Interrupt (SMI) handler returns execution to either Normal  
state or the C1/C1E state. See the Intel® 64 and IA-32 Architectures Software  
Developer’s Manual for more information.  
While a core is in C1/C1E state, it processes bus snoops and snoops from other  
threads. For more information on C1E state, see Package C-States on page 55.  
Core C3 State  
Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to  
the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its  
L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while  
maintaining its architectural state. All core clocks are stopped at this point. Because  
the core’s caches are flushed, the processor does not wake any core that is in the C3  
state when either a snoop is detected or when another core accesses cacheable  
memory.  
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Core C6 State  
Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or  
an MWAIT(C6) instruction. Before entering core C6 state, the core will save its  
architectural state to a dedicated SRAM. Once complete, a core will have its voltage  
reduced to zero volts. During exit, the core is powered on and its architectural state is  
restored.  
Core C7 State  
Individual threads of a core can enter the C7 state by initiating a P_LVL4 I/O read to  
the P_BLK or by an MWAIT(C7) instruction. The core C7 state exhibits the same  
behavior as the core C6 state.  
Note:  
C7 state may not be available on all SKUs.  
C-State Auto-Demotion  
In general, deeper C-states, such as C6 state, have long latencies and have higher  
energy entry/exit costs. The resulting performance and energy penalties become  
significant when the entry/exit frequency of a deeper C-state is high. Therefore,  
incorrect or inefficient usage of deeper C-states have a negative impact on idle power.  
To increase residency and improve idle power in deeper C-states, the processor  
supports C-state auto-demotion.  
There are two C-state auto-demotion options:  
C7/C6 to C3 state  
C7/C6/C3 To C1 state  
The decision to demote a core from C6/C7 to C3 or C3/C6/C7 to C1 state is based on  
each core’s immediate residency history and interrupt rate . If the interrupt rate  
experienced on a core is high and the residence in a deep C-state between such  
interrupts is low, the core can be demoted to a C3 or C1 state. A higher interrupt  
pattern is required to demote a core to C1 state as compared to C3 state.  
This feature is disabled by default. BIOS must enable it in the  
PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by  
this register.  
4.2.5  
Package C-States  
The processor supports C0, C1/C1E, C3, C6, and C7 (on some SKUs) power states.  
The following is a summary of the general rules for package C-state entry. These  
apply to all package C-states, unless specified otherwise:  
A package C-state request is determined by the lowest numerical core C-state  
amongst all cores.  
A package C-state is automatically resolved by the processor depending on the  
core idle power states and the status of the platform components.  
— Each core can be at a lower idle power state than the package if the platform  
does not grant the processor permission to enter a requested package C-state.  
— The platform may allow additional power savings to be realized in the  
processor.  
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— For package C-states, the processor is not required to enter C0 state before  
entering any other C-state.  
— Entry into a package C-state may be subject to auto-demotion – that is, the  
processor may keep the package in a deeper package C-state than requested  
by the operating system if the processor determines, using heuristics, that the  
deeper C-state results in better power/performance.  
The processor exits a package C-state when a break event is detected. Depending on  
the type of break event, the processor does the following:  
If a core break event is received, the target core is activated and the break event  
message is forwarded to the target core.  
— If the break event is not masked, the target core enters the core C0 state and  
the processor enters package C0 state.  
— If the break event is masked, the processor attempts to re-enter its previous  
package state.  
If the break event was due to a memory access or snoop request,  
— But the platform did not request to keep the processor in a higher package C-  
state, the package returns to its previous C-state.  
— And the platform requests a higher power C-state, the memory access or  
snoop request is serviced and the package remains in the higher power C-  
state.  
The following table shows package C-state resolution for a dual-core processor. The  
following figure summarizes package C-state transitions.  
Table 19.  
Coordination of Core Power States at the Package Level  
Package C-State  
Core 1  
C3  
C0  
C0  
C0  
C0  
C0  
C0  
C1  
C0  
C6  
C0  
C11  
C3  
C6  
C6  
C7  
C0  
C11  
C3  
C6  
C7  
C0  
C1  
C0  
C11  
C3  
C11  
C11  
C11  
C11  
Core 0  
C3  
C6  
C7  
C3  
C3  
Note: 1. If enabled, the package C-state will be C1E if all cores have resolved a core C1 state or higher.  
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Figure 14.  
Package C-State Entry and Exit  
C0  
C3  
C6  
C1  
C7  
Package C0 State  
This is the normal operating state for the processor. The processor remains in the  
normal state when at least one of its cores is in the C0 or C1 state or when the  
platform has not granted permission to the processor to go into a low-power state.  
Individual cores may be in lower power idle states while the package is in C0 state.  
Package C1/C1E State  
No additional power reduction actions are taken in the package C1 state. However, if  
the C1E sub-state is enabled, the processor automatically transitions to the lowest  
supported core clock frequency, followed by a reduction in voltage.  
The package enters the C1 low-power state when:  
At least one core is in the C1 state.  
The other cores are in a C1 or deeper power state.  
The package enters the C1E state when:  
All cores have directly requested C1E using MWAIT(C1) with a C1E sub-state hint.  
All cores are in a power state deeper than C1/C1E state; however, the package  
low-power state is limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR.  
All cores have requested C1 state using HLT or MWAIT(C1) and C1E auto-  
promotion is enabled in IA32_MISC_ENABLES.  
No notification to the system occurs upon entry to C1/C1E state.  
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Package C2 State  
Package C2 state is an internal processor state that cannot be explicitly requested by  
software. A processor enters Package C2 state when:  
All cores and graphics have requested a C3 or deeper power state; however,  
constraints (LTR, programmed timer events in the near future, and so on) prevent  
entry to any state deeper than C 2 state. Or,  
All cores and graphics are in the C3 or deeper power states, and a memory access  
request is received. Upon completion of all outstanding memory requests, the  
processor transitions back into a deeper package C-state.  
Package C3 State  
A processor enters the package C3 low-power state when:  
At least one core is in the C3 state.  
The other cores are in a C3 state or deeper power state and the processor has  
been granted permission by the platform.  
The platform has not granted a request to a package C6 or deeper state, however,  
has allowed a package C6 state.  
In package C3 state, the L3 shared cache is valid.  
Package C6 State  
A processor enters the package C6 low-power state when:  
At least one core is in the C6 state.  
The other cores are in a C6 or deeper power state and the processor has been  
granted permission by the platform.  
If the cores are requesting C7 state, but the platform is limiting to a package C6  
state, the last level cache in this case can be flushed.  
In package C6 state all cores have saved their architectural state and have had their  
core voltages reduced to zero volts. It is possible the L3 shared cache is flushed and  
turned off in package C6 state. If at least one core is requesting C6 state, the L3  
cache will not be flushed.  
Package C7 State  
The processor enters the package C7 low-power state when all cores are in the C7  
state. In package C7, the processor will take action to remove power from portions of  
the system agent.  
Core break events are handled the same way as in package C3 or C6 state.  
C7 state may not be available on all SKUs.  
Note:  
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Note:  
Package C6 state is the deepest C-state supported on discrete graphics systems with  
PCI Express Graphics (PEG).  
Package C7 state is the deepest C-state supported on integrated graphics systems (or  
switchable graphics systems during integrated graphics mode). However, in most  
configurations, package C6 will be more energy efficient than package C7 state. As a  
result, package C7 state residency is expected to be very low or zero in most  
scenarios where the display is enabled. Logic internal to the processor will determine  
whether package C6 or package C7 state is the most efficient. There is no need to  
make changes in BIOS or system software to prioritize package C6 state over package  
C7 state.  
4.2.6  
Package C-States and Display Resolutions  
The integrated graphics engine has the frame buffer located in system memory. When  
the display is updated, the graphics engine fetches display data from system memory.  
Different screen resolutions and refresh rates have different memory latency  
requirements. These requirements may limit the deepest Package C-state the  
processor can enter. Other elements that may affect the deepest Package C-state  
available are the following:  
Display is on or off  
Single or multiple displays  
Native or non-native resolution  
Panel Self Refresh (PSR) technology  
Note:  
Display resolution is not the only factor influencing the deepest Package C-state the  
processor can get into. Device latencies, interrupt response latencies, and core C-  
states are among other factors that influence the final package C-state the processor  
can enter.  
The following table lists display resolutions and deepest available package C-State.  
The display resolutions are examples using common values for blanking and pixel  
rate. Actual results will vary. The table shows the deepest possible Package C-state.  
System workload, system idle, and AC or DC power also affect the deepest possible  
Package C-state.  
Table 20.  
Deepest Package C-State Available  
Number of Displays 1  
Native Resolution  
Deepest Available Package C-  
State  
Single  
Single  
Single  
Single  
Single  
Single  
Single  
Single  
Single  
800x600 60 Hz  
1024x768 60 Hz  
1280x1024 60 Hz  
1920x1080 60 Hz  
1920x1200 60 Hz  
1920x1440 60 Hz  
2048x1536 60 Hz  
2560x1600 60 Hz  
2560x1920 60 Hz  
PC6  
PC6  
PC6  
PC6  
PC6  
PC6  
PC6  
PC6  
PC3  
continued...  
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Number of Displays 1  
Native Resolution  
Deepest Available Package C-  
State  
Single  
Single  
2880x1620 60 Hz  
2880x1800 60 Hz  
3200x1800 60 Hz  
3200x2000 60 Hz  
3840x2160 60 Hz  
3840x2160 30 Hz  
4096x2160 24 Hz  
800x600 60 Hz  
PC3  
PC3  
PC3  
PC3  
PC3  
PC3  
PC3  
PC6  
PC6  
PC6  
PC3  
PC3  
PC3  
PC3  
PC2  
PC2  
PC2  
PC2  
PC2  
PC2  
PC2  
PC2  
PC2  
Single  
Single  
Single  
Single  
Single  
Multiple  
Multiple  
Multiple  
Multiple  
Multiple  
Multiple  
Multiple  
Multiple  
Multiple  
Multiple  
Multiple  
Multiple  
Multiple  
Multiple  
Multiple  
Multiple  
1024x768 60 Hz  
1280x1024 60 Hz  
1920x1080 60 Hz  
1920x1200 60 Hz  
1920x1440 60 Hz  
2048x1536 60 Hz  
2560x1600 60 Hz  
2560x1920 60 Hz  
2880x1620 60 Hz  
2880x1800 60 Hz  
3200x1800 60 Hz  
3200x2000 60 Hz  
3840x2160 60 Hz  
3840x2160 30 Hz  
4096x2160 24 Hz  
Notes: 1. For multiple display cases, the resolution listed is the highest native resolution of all enabled  
displays, and PSR is internally disabled; that is, dual display with one 800x600 60 Hz display and  
one 2560x1600 60 Hz display will result in a deepest available package C-state of PC2.  
2. Microcode Update rev 00000010 or newer must be used.  
4.3  
Integrated Memory Controller (IMC) Power Management  
The main memory is power managed during normal operation and in low-power ACPI  
Cx states.  
4.3.1  
Disabling Unused System Memory Outputs  
Any system memory (SM) interface signal that goes to a memory module connector in  
which it is not connected to any actual memory devices (such as SO-DIMM connector  
is unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM  
signals are:  
Reduced power consumption.  
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Reduced possible overshoot/undershoot signal quality issues seen by the  
processor I/O buffer receivers caused by reflections from potentially un-  
terminated transmission lines.  
When a given rank is not populated, the corresponding chip select and CKE signals are  
not driven.  
At reset, all rows must be assumed to be populated, until it can be determined that  
the rows are not populated. This is due to the fact that when CKE is tri-stated with an  
SO-DIMM present, the SO-DIMM is not ensured to maintain data integrity.  
CKE tristate should be enabled by BIOS where appropriate, since at reset all rows  
must be assumed to be populated.  
4.3.2  
DRAM Power Management and Initialization  
The processor implements extensive support for power management on the SDRAM  
interface. There are four SDRAM operations associated with the Clock Enable (CKE)  
signals, which the SDRAM controller supports. The processor drives four CKE pins to  
perform these operations.  
The CKE is one of the power-save means. When CKE is off, the internal DDR clock is  
disabled and the DDR power is reduced. The power-saving differs according to the  
selected mode and the DDR type used. For more information, refer to the IDD table in  
the DDR specification.  
The processor supports three different types of power-down modes in package C0.  
The different power-down modes can be enabled through configuring  
"PM_PDWN_config_0_0_0_MCHBAR". The type of CKE power-down can be configured  
through PDWN_mode (bits 15:12) and the idle timer can be configured through  
PDWN_idle_counter (bits 11:0). The different power-down modes supported are:  
No power-down (CKE disable)  
Active power-down (APD): This mode is entered if there are open pages when  
de-asserting CKE. In this mode the open pages are retained. Power-saving in this  
mode is the lowest. Power consumption of DDR is defined by IDD3P. Exiting this  
mode is defined by tXP – small number of cycles. For this mode, DRAM DLL must  
be on.  
PPD/DLL-off: In this mode the data-in DLLs on DDR are off. Power-saving in this  
mode is the best among all power modes. Power consumption is defined by  
IDD2P1. Exiting this mode is defined by tXP, but also tXPDLL (10–20 according to  
DDR type) cycles until first data transfer is allowed. For this mode, DRAM DLL  
must be off.  
The CKE is determined per rank, whenever it is inactive. Each rank has an idle-  
counter. The idle-counter starts counting as soon as the rank has no accesses, and if  
it expires, the rank may enter power-down while no new transactions to the rank  
arrives to queues. The idle-counter begins counting at the last incoming transaction  
arrival.  
It is important to understand that since the power-down decision is per rank, the IMC  
can find many opportunities to power down ranks, even while running memory  
intensive applications; the savings are significant (may be few Watts, according to the  
DDR specification). This is significant when each channel is populated with more  
ranks.  
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Selection of power modes should be according to power-performance or thermal  
trade-offs of a given system:  
When trying to achieve maximum performance and power or thermal  
consideration is not an issue – use no power-down  
In a system which tries to minimize power-consumption, try using the deepest  
power-down mode possible – PPD/DLL-off with a low idle timer value  
In high-performance systems with dense packaging (that is, tricky thermal  
design) the power-down mode should be considered in order to reduce the heating  
and avoid DDR throttling caused by the heating.  
The default value that BIOS configures in "PM_PDWN_config_0_0_0_MCHBAR" is  
6080h – that is, PPD/DLL-off mode with idle timer of 80h, or 128 DCLKs. This is a  
balanced setting with deep power-down mode and moderate idle timer value.  
The idle timer expiration count defines the # of DCKLs that a rank is idle that causes  
entry to the selected powermode. As this timer is set to a shorter time, the IMC will  
have more opportunities to put DDR in power-down. There is no BIOS hook to set this  
register. Customers choosing to change the value of this register can do it by  
changing it in the BIOS. For experiments, this register can be modified in real time if  
BIOS does not lock the IMC registers.  
4.3.2.1  
4.3.2.2  
Initialization Role of CKE  
During power-up, CKE is the only input to the SDRAM that has its level recognized  
(other than the DDR3/DDR3L reset pin) once power is applied. It must be driven LOW  
by the DDR controller to make sure the SDRAM components float DQ and DQS during  
power-up. CKE signals remain LOW (while any reset is active) until the BIOS writes to  
a configuration register. Using this method, CKE is ensured to remain inactive for  
much longer than the specified 200 micro-seconds after power and clocks to SDRAM  
devices are stable.  
Conditional Self-Refresh  
During S0 idle state, system memory may be conditionally placed into self-refresh  
state when the processor is in package C3 or deeper power state. Refer to Intel®  
Rapid Memory Power Management (Intel® RMPM) for more details on conditional self-  
refresh with Intel HD Graphics enabled.  
When entering the S3 – Suspend-to-RAM (STR) state or S0 conditional self-refresh,  
the processor core flushes pending cycles and then enters SDRAM ranks that are not  
used by Intel graphics memory into self-refresh. The CKE signals remain LOW so the  
SDRAM devices perform self-refresh.  
The target behavior is to enter self-refresh for package C3 or deeper power states as  
long as there are no memory requests to service. The target usage is shown in the  
following table.  
4.3.2.3  
Dynamic Power-Down  
Dynamic power-down of memory is employed during normal operation. Based on idle  
conditions, a given memory rank may be powered down. The IMC implements  
aggressive CKE control to dynamically put the DRAM devices in a power-down state.  
The processor core controller can be configured to put the devices in active power-  
down (CKE de-assertion with open pages) or pre-charge power-down (CKE de-  
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assertion with all pages closed). Pre-charge power-down provides greater power  
savings, but has a bigger performance impact since all pages will first be closed before  
putting the devices in power-down mode.  
If dynamic power-down is enabled, all ranks are powered up before doing a refresh  
cycle and all ranks are powered down at the end of refresh.  
4.3.2.4  
DRAM I/O Power Management  
Unused signals should be disabled to save power and reduce electromagnetic  
interference. This includes all signals associated with an unused memory channel.  
Clocks, CKE, ODE, and CS signals are controlled per DIMM rank and will be powered  
down for unused ranks.  
The I/O buffer for an unused signal should be tri-stated (output driver disabled), the  
input receiver (differential sense-amp) should be disabled, and any DLL circuitry  
related ONLY to unused signals should be disabled. The input path must be gated to  
prevent spurious results due to noise on the unused signals (typically handled  
automatically when input receiver is disabled).  
4.3.3  
4.3.4  
DRAM Running Average Power Limitation (RAPL)  
RAPL is a power and time constant pair. DRAM RAPL defines an average power  
constraint for the DRAM domain. Constraint is controlled by the PCU. Platform entities  
(PECI or in-band power driver) can specify a power limit for the DRAM domain. PCU  
continuously monitors the extant of DRAM throttling due to the power limit and  
rebudgets the limit between DIMMs.  
DDR Electrical Power Gating (EPG)  
The DDR I/O of the processor supports Electrical Power Gating (DDR-EPG) while the  
processor is at C3 or deeper power state.  
In C3 or deeper power state, the processor internally gates VDDQ for the majority of  
the logic to reduce idle power while keeping all critical DDR pins such as  
SM_DRAMRST#, CKE and VREF in the appropriate state.  
In C7, the processor internally gates VCCIO_TERM for all non-critical state to reduce idle  
power.  
In S3 or C-state transitions, the DDR does not go through training mode and will  
restore the previous training information.  
4.4  
4.5  
PCI Express* Power Management  
Active power management is supported using L0s, and L1 states.  
All inputs and outputs disabled in L2/L3 Ready state.  
Direct Media Interface (DMI) Power Management  
Active power management is supported using L0s/L1 state.  
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4.6  
Graphics Power Management  
4.6.1  
Intel® Rapid Memory Power Management (Intel® RMPM)  
Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory  
into self-refresh when the processor is in package C3 or deeper power state to allow  
the system to remain in the lower power states longer for memory not reserved for  
graphics memory. Intel RMPM functionality depends on graphics/display state  
(relevant only when processor graphics is being used), as well as memory traffic  
patterns generated by other connected I/O devices.  
4.6.2  
4.6.3  
Graphics Render C-State  
Render C-state (RC6) is a technique designed to optimize the average power to the  
graphics render engine during times of idleness. RC6 is entered when the graphics  
render engine, blitter engine, and the video engine have no workload being currently  
worked on and no outstanding graphics memory transactions. When the idleness  
condition is met, the processor graphics will program the graphics render engine  
internal power rail into a low voltage state.  
Intel® Graphics Dynamic Frequency  
Intel Graphics Dynamic Frequency Technology is the ability of the processor and  
graphics cores to opportunistically increase frequency and/or voltage above the  
guaranteed processor and graphics frequency for the given part. Intel Graphics  
Dynamic Frequency Technology is a performance feature that makes use of unused  
package power and thermals to increase application performance. The increase in  
frequency is determined by how much power and thermal budget is available in the  
package, and the application demand for additional processor or graphics  
performance. The processor core control is maintained by an embedded controller.  
The graphics driver dynamically adjusts between P-States to maintain optimal  
performance, power, and thermals. The graphics driver will always try to place the  
graphics engine in the most energy efficient P-state.  
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5.0  
Thermal Management  
This chapter provides both component-level and system-level thermal management.  
Topics covered include processor thermal specifications, thermal profiles, thermal  
metrology, fan speed control, adaptive thermal monitor, THERMTRIP# signal, Digital  
Thermal Sensor (DTS), Intel Turbo Boost Technology, package power control, power  
plane control, and turbo time parameter.  
The processor requires a thermal solution to maintain temperatures within its  
operating limits. Any attempt to operate the processor outside these operating limits  
may result in permanent damage to the processor and potentially other components  
within the system. Maintaining the proper thermal environment is key to reliable,  
long-term system operation.  
A complete solution includes both component and system level thermal management  
features. Component level thermal solutions can include active or passive heatsinks  
attached to the processor integrated heat spreader (IHS).  
To allow the optimal operation and long-term reliability of Intel processor-based  
systems, the processor must remain within the minimum and maximum case  
temperature (TCASE) specifications as defined by the applicable thermal profile.  
Thermal solutions not designed to provide this level of thermal capability may affect  
the long-term reliability of the processor and system.  
The processors implement a methodology for managing processor temperatures that  
is intended to support acoustic noise reduction through fan speed control and to  
assure processor reliability. Selection of the appropriate fan speed is based on the  
relative temperature data reported by the processor’s Digital Temperature Sensor  
(DTS). The DTS can be read using the Platform Environment Control Interface (PECI)  
as described in Processor Temperature on page 74. Alternatively, when PECI is  
monitored by the PCH, the processor temperature can be read from the PCH using the  
SMBus protocol defined in Embedded Controller Support Provided by the PCH. The  
temperature reported over PECI is always a negative value and represents a delta  
below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT#  
(see Processor Temperature on page 74). Systems that implement fan speed control  
must be designed to use this data. Systems that do not alter the fan speed only need  
to ensure the case temperature meets the thermal profile specifications.  
Analysis indicates that real applications are unlikely to cause the processor to  
consume maximum power dissipation for sustained time periods. Intel recommends  
that complete thermal solution designs target the Thermal Design Power (TDP),  
instead of the maximum processor power consumption. The Adaptive Thermal Monitor  
feature is intended to help protect the processor in the event that an application  
exceeds the TDP recommendation for a sustained time period. For more details on this  
feature, see Adaptive Thermal Monitor on page 75. To ensure maximum flexibility  
for future processors, systems should be designed to the Thermal Solution Capability  
guidelines, even if a processor with lower power dissipation is currently planned.  
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Table 21.  
Desktop Processor Thermal Specifications  
Product  
PCG8  
Max  
Power  
Packag  
e C1E  
Max  
Power  
Packag  
e C3  
Min  
Power  
Max  
Power  
Packag  
e C6  
Max  
Min  
Power  
Package  
C6/C7  
(W)9  
TTV  
Min  
TCASE  
(°C)  
Max  
TTV  
TCASE  
(°C)  
Power  
Package  
Thermal  
Design  
Power  
Package  
C3 (W)9  
C7 (W) 1,  
4, 5, 9  
(W) 1, 2, (W) 1, 3,  
(W) 1, 4,  
(W) 6, 7,  
5, 9  
5, 9  
5, 9  
10  
on page  
67  
Quad  
Core  
Processor  
with  
Graphics  
2013D  
2013C  
2013B  
26  
20  
1.0  
1.0  
1.0  
3.5  
3.5  
3.5  
3.4  
3.4  
3.4  
0
0
0
84  
65  
45  
5
5
5
on page  
68  
Quad  
Core  
Processor  
with  
Graphics  
23  
18  
17  
11  
on page  
69  
Quad  
Core  
Processor  
with  
Graphics  
Quad  
Core  
Processor  
with  
on page  
70  
16  
16  
16  
16  
1.0  
1.0  
3.5  
3.5  
3.4  
3.4  
0
0
35  
35  
5
5
Graphics  
2013A  
Dual Core  
Processor  
with  
Graphics  
Notes: 1. The package C-state power is the worst case power in the system configured as follows:  
a. Memory configured for DDR3 1333 and populated with two DIMMs per channel.  
b. DMI and PCIe links are at L1.  
2. Specification at DTS = 50 °C and minimum voltage loadline.  
3. Specification at DTS = 50 °C and minimum voltage loadline.  
4. Specification at DTS = 35 °C and minimum voltage loadline.  
5. These DTS values in Notes 2 – 4 are based on the TCC Activation MSR having a value of 100, see Processor  
Temperature on page 74.  
6. These values are specified at VCC_MAX and VNOM for all other voltage rails for all processor frequencies. Systems  
must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCCP  
exceeds VCCP_MAX at specified ICCP. See the loadline specifications.  
7. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the  
maximum power that the processor can dissipate. TDP is measured at DTS = -1. TDP is achieved with the Memory  
configured for DDR3 1333 and 2 DIMMs per channel.  
8. Platform Compatibility Guide (PCG) (previously known as FMB) provides a design target for meeting all planned  
processor frequency requirements.  
9. Not 100% tested. Specified by design characterization.  
5.1  
Desktop Processor Thermal Profiles  
This section provides thermal profiles for the Desktop processor families.  
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5.1.1  
Processor (PCG 2013D) Thermal Profile  
Figure 15.  
Thermal Test Vehicle Thermal Profile for Processor (PCG 2013D)  
80  
75  
TCASE = 0.33 * Power + 45.0  
70  
65  
60  
55  
50  
45  
40  
0
20  
40  
60  
80  
100  
TTV Power (W)  
See the following table for discrete points that constitute the thermal profile.  
Table 22.  
Thermal Test Vehicle Thermal Profile for Processor (PCG 2013D)  
Power (W)  
TCASE_MAX  
(°C)  
Power (W)  
TCASE_MAX  
(°C)  
Power (W)  
TCASE_MAX  
(°C)  
Y = 0.33 * Power + 45  
28  
54.24  
58  
64.14  
0
45.00  
45.66  
46.32  
46.98  
47.64  
48.30  
48.96  
49.62  
50.28  
50.94  
51.60  
52.26  
52.92  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
54.90  
55.56  
56.22  
56.88  
57.54  
58.20  
58.86  
59.52  
60.18  
60.84  
61.50  
62.16  
62.82  
60  
62  
64  
66  
68  
70  
72  
74  
76  
78  
80  
82  
84  
64.80  
65.46  
66.12  
66.78  
67.44  
68.10  
68.76  
69.42  
70.08  
70.74  
71.40  
72.06  
72.72  
2
4
6
8
10  
12  
14  
16  
18  
20  
22  
24  
26  
53.58  
63.48  
continued...  
continued...  
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5.1.2  
Processor (PCG 2013C) Thermal Profile  
Figure 16.  
Thermal Test Vehicle Thermal Profile for Processor (PCG 2013C)  
See the following table for discrete points that constitute the thermal profile.  
Table 23.  
Thermal Test Vehicle Thermal Profile for Processor (PCG 2013C)  
Power (W)  
TCASE_MAX (°C)  
Power (W)  
TCASE_MAX (°C)  
Y = 0.41 * Power + 44.7  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
57.00  
57.82  
58.64  
59.46  
60.28  
61.10  
61.92  
62.74  
63.56  
64.38  
65.20  
66.02  
66.84  
67.66  
68.48  
69.30  
0
44.7  
2
45.52  
46.34  
47.16  
47.98  
48.80  
49.62  
50.44  
51.26  
52.08  
52.90  
53.72  
54.54  
55.36  
56.18  
4
6
8
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
continued...  
continued...  
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Power (W)  
TCASE_MAX (°C)  
62  
64  
65  
70.12  
70.94  
71.35  
5.1.3  
Processor (PCG 2013B) Thermal Profile  
Figure 17.  
Thermal Test Vehicle Thermal Profile for Processor (PCG 2013B)  
See the following table for discrete points that constitute the thermal profile.  
Table 24.  
Thermal Test Vehicle Thermal Profile for Processor (PCG 2013B)  
Power (W)  
TCASE_MAX (°C)  
Power (W)  
TCASE_MAX (°C)  
58.70  
Power (W)  
TCASE_MAX (°C)  
69.92  
Y = 0.51 * Power + 48.5  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
45  
0
48.50  
49.52  
50.54  
51.56  
52.58  
53.60  
54.62  
55.64  
56.66  
57.68  
59.72  
70.94  
2
60.74  
71.45  
4
61.76  
6
62.78  
8
63.80  
10  
12  
14  
16  
18  
64.82  
65.84  
66.86  
67.88  
68.90  
continued...  
continued...  
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5.1.4  
Processor (PCG 2013A) Thermal Profile  
Figure 18.  
Thermal Test Vehicle Thermal Profile for Processor (PCG 2013A)  
See the following table for discrete points that constitute the thermal profile.  
Table 25.  
Thermal Test Vehicle Thermal Profile for Processor (PCG 2013A)  
Power (W)  
TCASE_MAX (°C)  
Power (W)  
TCASE_MAX (°C)  
63.80  
Y = 0.51 * Power + 48.5  
30  
32  
34  
35  
0
48.50  
49.52  
50.54  
51.56  
52.58  
53.60  
54.62  
55.64  
56.66  
57.68  
58.70  
59.72  
60.74  
61.76  
62.78  
64.82  
2
65.84  
4
66.35  
6
8
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
continued...  
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5.2  
Thermal Metrology  
The maximum Thermal Test Vehicle (TTV) case temperatures (TCASE-MAX) can be  
derived from the data in the appropriate TTV thermal profile earlier in this chapter.  
The TTV TCASE is measured at the geometric top center of the TTV integrated heat  
spreader (IHS). The following figure illustrates the location where TCASE temperature  
measurements should be made.  
Figure 19.  
Thermal Test Vehicle (TTV) Case Temperature (TCASE) Measurement Location  
Measure TCASE at  
the geometric  
center of the  
package  
37.5  
Note:  
THERM-X OF CALIFORNIA can machine the groove and attach a thermocouple to the  
IHS. The supplier is subject to change without notice. THERM-X OF CALIFORNIA, 1837  
Whipple Road, Hayward, Ca 94544. Ernesto B Valencia +1-510-441-7566 Ext. 242  
[email protected]. The vendor part number is XTMS1565.  
5.3  
Fan Speed Control Scheme with Digital Thermal Sensor  
(DTS) 1.1  
To correctly use DTS 1.1, the designer must first select a worst case scenario TAMBIENT  
and ensure that the Fan Speed Control (FSC) can provide a ΨCA that is equivalent or  
greater than the ΨCA specification.  
,
The DTS 1.1 implementation consists of two points: a ΨCA at TCONTROL and a ΨCA at  
DTS = -1.  
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The ΨCA point at DTS = -1 defines the minimum ΨCA required at TDP considering the  
worst case system design TAMBIENT design point:  
ΨCA = (TCASE-MAX – TAMBIENT-TARGET) / TDP  
For example, for a 95 W TDP part, the Tcase maximum is 72.6 °C and at a worst case  
design point of 40 °C local ambient this will result in:  
ΨCA = (72.6 – 40) / 95 = 0.34 °C/W  
Similarly for a system with a design target of 45 °C ambient, the ΨCA at DTS = -1  
needed will be 0.29 °C/W.  
The second point defines the thermal solution performance (ΨCA) at TCONTROL. The  
following table lists the required ΨCA for the various TDP processors.  
These two points define the operational limits for the processor for DTS 1.1  
implementation. At TCONTROL the fan speed must be programmed such that the  
resulting ΨCA is better than or equivalent to the required ΨCA listed in the following  
table. Similarly, the fan speed should be set at DTS = -1 such that the thermal  
solution performance is better than or equivalent to the ΨCA requirements at TAMBIENT-  
MAX. The fan speed controller must linearly ramp the fan speed from processor DTS =  
TCONTROL to processor DTS = -1.  
Figure 20.  
Digital Thermal Sensor (DTS) 1.1 Definition Points  
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Table 26.  
Digital Thermal Sensor (DTS) 1.1 Thermal Solution Performance Above  
TCONTROL  
Processor  
TDP  
ΨCA at DTS =  
TCONTROL  
ΨCA at DTS = -1  
ΨCA at DTS = -1  
ΨCA at DTS = -1  
1, 2  
At System  
TAMBIENT-MAX  
= 40 °C  
At System  
TAMBIENT-MAX  
= 45 °C  
At System TAMBIENT-  
MAX = 50 °C  
At System TAMBIENT-  
MAX = 30 °C  
84 W  
65 W  
45 W  
35 W  
0.627  
0.793  
1.207  
1.406  
0.390  
0.482  
0.699  
0.753  
0.330  
0.405  
0.588  
0.610  
0.270  
0.328  
0.477  
0.467  
Notes: 1. ΨCA at "DTS = TCONTROL" is applicable to systems that have an internal TRISE (TROOM temperature  
to Processor cooling fan inlet) of less than 10 °C. In case the expected TRISE is greater than 10  
°C, a correction factor should be used as explained below. For each 1 °C TRISE above 10 °C, the  
correction factor (CF) is defined as CF = 1.7 / (processor TDP)  
2. Example: A chassis TRISE assumption is 12 °C for a 95 W TDP processor:  
CF = 1.7 / 95 W = 0.018 /W  
For TRISE > 10 °C  
ΨCA at TCONTROL = (Value provide in Column 2) – (TRISE – 10) * CF  
ΨCA = 0.627 – (12 – 10) * 0.018 = 0.591 °C/W  
In this case, the fan speed should be set slightly higher, equivalent to ΨCA = 0.591 °C/W  
5.4  
Fan Speed Control Scheme with Digital Thermal Sensor  
(DTS) 2.0  
To simplify processor thermal specification compliance, the processor calculates the  
DTS Thermal Profile from TCONTROL Offset, TCC Activation Temperature, TDP, and the  
Thermal Margin Slope provided in the following table.  
Note:  
TCC Activation Offset is 0 for the processors.  
Using the DTS Thermal Profile, the processor can calculate and report the Thermal  
Margin, where a value less than 0 indicates that the processor needs additional  
cooling, and a value greater than 0 indicates that the processor is sufficiently cooled.  
Refer to the processor Thermal Mechanical Design Guidelines (TMDG) for additional  
information (see Related Documents).  
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Figure 21.  
Digital Thermal Sensor (DTS) Thermal Profile Definition  
Table 27.  
Thermal Margin Slope  
PCG  
Die  
TDP (W)  
TCC Activation  
Temperature (°C)  
Temperature  
Control Offset  
Thermal  
Margin  
Slope  
Configuration  
(Native)  
MSR 1A2h 23:16  
MSR 1A2h 15:8  
(°C / W)  
Core + GT  
4+2 (4+2)  
4+0 (4+2)  
4+2 (4+2)  
2+2 (2+2)  
2+1 (2+2)  
4+2 (4+2)  
4+2 (4+2)  
2+2 (4+2)  
2+2 (2+2)  
2+1 (2+2)  
84  
82  
65  
54  
53  
45  
35  
35  
35  
35  
100  
100  
92  
20  
20  
6
0.654  
0.671  
0.722  
1.031  
1.051  
0.806  
0.806  
1.016  
1.021  
1.141  
2013D  
2013C  
2013B  
100  
100  
85  
20  
20  
6
75  
6
85  
6
2013A  
85  
6
90  
6
5.5  
Processor Temperature  
A software readable field in the TEMPERATURE_TARGET register that contains the  
minimum temperature at which the TCC will be activated and PROCHOT# will be  
asserted. The TCC activation temperature is calibrated on a part-by-part basis and  
normal factory variation may result in the actual TCC activation temperature being  
higher than the value listed in the register. TCC activation temperatures may change  
based on processor stepping, frequency or manufacturing efficiencies.  
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5.6  
Adaptive Thermal Monitor  
The Adaptive Thermal Monitor feature provides an enhanced method for controlling  
the processor temperature when the processor silicon exceeds the Thermal Control  
Circuit (TCC) activation temperature. Adaptive Thermal Monitor uses TCC activation to  
reduce processor power using a combination of methods. The first method (Frequency  
control, similar to Thermal Monitor 2 (TM2) in previous generation processors)  
involves the processor reducing its operating frequency (using the core ratio  
multiplier) and internal core voltage. This combination of lower frequency and core  
voltage results in a reduction of the processor power consumption. The second  
method (clock modulation, known as Thermal Monitor 1 or TM1 in previous generation  
processors) reduces power consumption by modulating (starting and stopping) the  
internal processor core clocks. The processor intelligently selects the appropriate TCC  
method to use on a dynamic basis. BIOS is not required to select a specific method  
(as with previous-generation processors supporting TM1 or TM2). The temperature at  
which Adaptive Thermal Monitor activates the Thermal Control Circuit is factory  
calibrated and is not user configurable. Snooping and interrupt processing are  
performed in the normal manner while the TCC is active.  
When the TCC activation temperature is reached, the processor will initiate TM2 in  
attempt to reduce its temperature. If TM2 is unable to reduce the processor  
temperature, TM1 will be also be activated. TM1 and TM2 will work together (clocks  
will be modulated at the lowest frequency ratio) to reduce power dissipation and  
temperature.  
With a properly designed and characterized thermal solution, it is anticipated that the  
TCC will only be activated for very short periods of time when running the most power  
intensive applications. The processor performance impact due to these brief periods of  
TCC activation is expected to be so minor that it would be immeasurable. An under-  
designed thermal solution that is not able to prevent excessive activation of the TCC in  
the anticipated ambient environment may cause a noticeable performance loss, and in  
some cases may result in a TCASE that exceeds the specified maximum temperature  
and may affect the long-term reliability of the processor. In addition, a thermal  
solution that is significantly under designed may not be capable of cooling the  
processor even when the TCC is active continuously. See the appropriate processor  
Thermal Mechanical Design Guidelines for information on designing a compliant  
thermal solution.  
The Thermal Monitor does not require any additional hardware, software drivers, or  
interrupt handling routines. The following sections provide more details on the  
different TCC mechanisms used by the processor.  
Frequency Control  
When the Digital Temperature Sensor (DTS) reaches a value of 0 (DTS temperatures  
reported using PECI may not equal zero when PROCHOT# is activated), the TCC will  
be activated and the PROCHOT# signal will be asserted if configured as bi-directional.  
This indicates the processor temperature has met or exceeded the factory calibrated  
trip temperature and it will take action to reduce the temperature.  
Upon activation of the TCC, the processor will stop the core clocks, reduce the core  
ratio multiplier by 1 ratio and restart the clocks. All processor activity stops during this  
frequency transition that occurs within 2 us. Once the clocks have been restarted at  
the new lower frequency, processor activity resumes while the core voltage is reduced  
by the internal voltage regulator. Running the processor at the lower frequency and  
voltage will reduce power consumption and should allow the processor to cool off. If  
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after 1 ms the processor is still too hot (the temperature has not dropped below the  
TCC activation point, DTS still = 0 and PROCHOT is still active), then a second  
frequency and voltage transition will take place. This sequence of temperature  
checking and frequency and voltage reduction will continue until either the minimum  
frequency has been reached or the processor temperature has dropped below the TCC  
activation point.  
If the processor temperature remains above the TCC activation point even after the  
minimum frequency has been reached, then clock modulation (described below) at  
that minimum frequency will be initiated.  
There is no end user software or hardware mechanism to initiate this automated TCC  
activation behavior.  
A small amount of hysteresis has been included to prevent rapid active/inactive  
transitions of the TCC when the processor temperature is near the TCC activation  
temperature. Once the temperature has dropped below the trip temperature and the  
hysteresis timer has expired, the operating frequency and voltage transition back to  
the normal system operating point using the intermediate VID/frequency points.  
Transition of the VID code will occur first, to insure proper operation as the frequency  
is increased.  
Clock Modulation  
Clock modulation is a second method of thermal control available to the processor.  
Clock modulation is performed by rapidly turning the clocks off and on at a duty cycle  
that should reduce power dissipation by about 50% (typically a 30–50% duty cycle).  
Clocks often will not be off for more than 32 microseconds when the TCC is active.  
Cycle times are independent of processor frequency. The duty cycle for the TCC, when  
activated by the Thermal Monitor, is factory configured and cannot be modified.  
It is possible for software to initiate clock modulation with configurable duty cycles.  
A small amount of hysteresis has been included to prevent rapid active/inactive  
transitions of the TCC when the processor temperature is near its maximum operating  
temperature. Once the temperature has dropped below the maximum operating  
temperature and the hysteresis timer has expired, the TCC goes inactive and clock  
modulation ceases.  
Immediate Transition to Combined TM1 and TM2  
When the TCC is activated, the processor will sequentially step down the ratio  
multipliers and VIDs in an attempt to reduce the silicon temperature. If the  
temperature continues to increase and exceeds the TCC activation temperature by  
approximately 5 °C before the lowest ratio/VID combination has been reached, the  
processor will immediately transition to the combined TM1/TM2 condition. The  
processor remains in this state until the temperature has dropped below the TCC  
activation point. Once below the TCC activation temperature, TM1 will be discontinued  
and TM2 will be exited by stepping up to the appropriate ratio/VID state.  
Critical Temperature Flag  
If TM2 is unable to reduce the processor temperature, then TM1 will be also be  
activated. TM1 and TM2 will then work together to reduce power dissipation and  
temperature. It is expected that only a catastrophic thermal solution failure would  
create a situation where both TM1 and TM2 are active.  
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If TM1 and TM2 have both been active for greater than 20 ms and the processor  
temperature has not dropped below the TCC activation point, the Critical Temperature  
Flag in the IA32_THERM_STATUS MSR will be set. This flag is an indicator of a  
catastrophic thermal solution failure and that the processor cannot reduce its  
temperature. Unless immediate action is taken to resolve the failure, the processor  
will probably reach the Thermtrip temperature (see Testability Signals on page 87)  
within a short time. To prevent possible permanent silicon damage, Intel recommends  
removing power from the processor within ½ second of the Critical Temperature Flag  
being set.  
PROCHOT# Signal  
An external signal, PROCHOT# (processor hot), is asserted when the processor core  
temperature has exceeded its specification. If Adaptive Thermal Monitor is enabled (it  
must be enabled for the processor to be operating within specification), the TCC will  
be active when PROCHOT# is asserted.  
The processor can be configured to generate an interrupt upon the assertion or de-  
assertion of PROCHOT#.  
By default, the PROCHOT# signal is set to bi-directional. However, it is recommended  
to configure the signal as an input only. When configured as an input or bi-directional  
signal, PROCHOT# can be used for thermally protecting other platform components  
should they overheat as well. When PROCHOT# is driven by an external device:  
The package will immediately transition to the minimum operation points (voltage  
and frequency) supported by the processor and graphics cores. This is contrary to  
the internally-generated Adaptive Thermal Monitor response.  
Clock modulation is not activated.  
The TCC will remain active until the system de-asserts PROCHOT#. The processor can  
be configured to generate an interrupt upon assertion and de-assertion of the  
PROCHOT# signal. Refer to the appropriate Platform Thermal Mechanical Design  
Guidelines (see Related Doucments section) for details on implementing the bi-  
directional PROCHOT# feature.  
Note:  
Note:  
Toggling PROCHOT# more than once in 1.5 ms period will result in constant Pn state  
of the processor.  
A corner case exists for PROCHOT# configured as a bi-directional signal that can  
cause several milliseconds of delay to a system assertion of PROCHOT# when the  
output function is asserted.  
As an output, PROCHOT# (Processor Hot) will go active when the processor  
temperature monitoring sensor detects that one or more cores has reached its  
maximum safe operating temperature. This indicates that the processor Thermal  
Control Circuit (TCC) has been activated, if enabled. As an input, assertion of  
PROCHOT# by the system will activate the TCC for all cores. TCC activation when  
PROCHOT# is asserted by the system will result in the processor immediately  
transitioning to the minimum frequency and corresponding voltage (using Frequency  
control). Clock modulation is not activated in this case. The TCC will remain active  
until the system de-asserts PROCHOT#.  
Use of PROCHOT# in input or bi-directional mode can allow VR thermal designs to  
target maximum sustained current instead of maximum current. Systems should still  
provide proper cooling for the Voltage Regulator (VR), and rely on PROCHOT# only as  
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a backup in case of system cooling failure. The system thermal design should allow  
the power delivery circuitry to operate within its temperature specification even while  
the processor is operating at its Thermal Design Power.  
5.7  
5.8  
THERMTRIP# Signal  
Regardless of whether or not Adaptive Thermal Monitor is enabled, in the event of a  
catastrophic cooling failure, the processor will automatically shut down when the  
silicon has reached an elevated temperature (refer to the THERMTRIP# definition in  
Error and Thermal Protection Signals on page 88). THERMTRIP# activation is  
independent of processor activity. The temperature at which THERMTRIP# asserts is  
not user configurable and is not software visible.  
Digital Thermal Sensor  
Each processor execution core has an on-die Digital Thermal Sensor (DTS) that  
detects the core's instantaneous temperature. The DTS is the preferred method of  
monitoring processor die temperature because:  
It is located near the hottest portions of the die.  
It can accurately track the die temperature and ensure that the Adaptive Thermal  
Monitor is not excessively activated.  
Temperature values from the DTS can be retrieved through:  
A software interface using processor Model Specific Register (MSR).  
A processor hardware interface as described in Platform Environmental Control  
Interface (PECI) on page 37.  
When temperature is retrieved by the processor MSR, it is the instantaneous  
temperature of the given core. When temperature is retrieved using PECI, it is the  
average of the highest DTS temperature in the package over a 256 ms time window.  
Intel recommends using the PECI reported temperature for platform thermal control  
that benefits from averaging, such as fan speed control. The average DTS  
temperature may not be a good indicator of package Adaptive Thermal Monitor  
activation or rapid increases in temperature that triggers the Out of Specification  
status bit within the PACKAGE_THERM_STATUS MSR 1B1h and IA32_THERM_STATUS  
MSR 19Ch.  
Code execution is halted in C1 or deeper C-states. Package temperature can still be  
monitored through PECI in lower C-states.  
Unlike traditional thermal devices, the DTS outputs a temperature relative to the  
maximum supported operating temperature of the processor (TjMAX), regardless of  
TCC activation offset. It is the responsibility of software to convert the relative  
temperature to an absolute temperature. The absolute reference temperature is  
readable in the TEMPERATURE_TARGET MSR 1A2h. The temperature returned by the  
DTS is an implied negative integer indicating the relative offset from TjMAX. The DTS  
does not report temperatures greater than TjMAX. The DTS-relative temperature  
readout directly impacts the Adaptive Thermal Monitor trigger point. When a package  
DTS indicates that it has reached the TCC activation (a reading of 0h, except when the  
TCC activation offset is changed), the TCC will activate and indicate an Adaptive  
Thermal Monitor event. A TCC activation will lower both IA core and graphics core  
frequency, voltage, or both. Changes to the temperature can be detected using two  
programmable thresholds located in the processor thermal MSRs. These thresholds  
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have the capability of generating interrupts using the core's local APIC. Refer to the  
Intel® 64 and IA-32 Architectures Software Developer’s Manual for specific register  
and programming details.  
5.8.1  
5.9  
Digital Thermal Sensor Accuracy (Taccuracy)  
The error associated with DTS measurements will not exceed ±5 °C within the entire  
operating range.  
Intel® Turbo Boost Technology Thermal Considerations  
Intel Turbo Boost Technology allows processor cores and integrated graphics cores to  
run faster than the baseline frequency. During a turbo event, the processor can  
exceed its TDP power for brief periods. Turbo is invoked opportunistically and  
automatically as long as the processor is conforming to its temperature, power  
delivery, and current specification limits. Thus, thermal solutions and platform cooling  
that are designed to less than thermal design guidance may experience thermal and  
performance issues since more applications will tend to run at or near the maximum  
power limit for significant periods of time.  
5.9.1  
Intel® Turbo Boost Technology Power Control and Reporting  
Package processor core and internal graphics core powers are self monitored and  
correspondingly reported out.  
With the processor turbo disabled, rolling average power over 5 seconds will not  
exceed the TDP rating of the part for typical applications.  
With turbo enabled (see Figure 22 on page 81)  
— For the PL1: Package rolling average of the power set in POWER_LIMIT_1  
(TURBO_POWER_LIMIT MSR 0610h bits [14:0]) over time window set in  
POWER_LIMIT_1_TIME (TURBO_POWER_LIMIT MSR 0610h bits [23:17]) must  
be less than or equal to the TDP package power as read from the  
PACKAGE_POWER_SKU MSR 0614h for typical applications. Power control is  
valid only when the processor is operating in turbo. PL1 lower than the  
package TDP is not guaranteed.  
— For the PL2: Package power will be controlled to a value set in  
POWER_LIMIT_2 (TURBO_POWER_LIMIT MSR 0610h bits [46:32]). Occasional  
brief power excursions may occur for periods of less than 10 ms over PL2.  
The processor monitors its own power consumption to control turbo behavior,  
assuming the following:  
The power monitor is not 100% tested across all processors.  
The Power Limit 2 (PL2) control is only valid for power levels set at or above TDP  
and under workloads with similar activity ratios as the product TDP workload. This  
also assumes the processor is working within other product specifications.  
Setting power limits (PL1 or PL2) below TDP are not ensured to be followed, and  
are not characterized for accuracy.  
Under unknown work loads and unforeseen applications the average processor  
power may exceed Power Limit 1 (PL1).  
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Uncharacterized workloads may exist that could result in higher turbo frequencies  
and power. If that were to happen, the processor Thermal Control Circuitry (TCC)  
would protect the processor. The TCC protection must be enabled by the platform  
for the product to be within specification.  
An illustration of Intel Turbo Boost Technology power control is shown in the following  
sections and figures. Multiple controls operate simultaneously allowing for  
customization for multiple system thermal and power limitations. These controls  
provide turbo optimizations within system constraints.  
5.9.2  
Package Power Control  
The package power control allows for customization to implement optimal turbo within  
platform power delivery and package thermal solution limitations.  
Table 28.  
Intel® Turbo Boost Technology 2.0 Package Power Control Settings  
MSR:  
MSR_TURBO_POWER_LIMIT  
610h  
Address:  
Control  
Bit  
Default  
Description  
This value sets the average power limit over a long time  
period. This is normally aligned to the TDP of the part and  
steady-state cooling capability of the thermal solution. The  
default value is the TDP for the SKU.  
PL1 limit may be set lower than TDP in real time for specific  
needs, such as responding to a thermal event. If it is set  
lower than TDP, the processor may require to use frequencies  
below the guaranteed P1 frequency to control the low-power  
limits. The PL1 Clamp bit [16] should be set to enable the  
processor to use frequencies below P1 to control the set-  
power limit.  
POWER_LIMIT_1 (PL1)  
14:0  
SKU TDP  
PL1 limit may be set higher than TDP. If set higher than TDP,  
the processor could stay at that power level continuously and  
cooling solution improvements may be required.  
This value is a time parameter that adjusts the algorithm  
behavior to maintain time averaged power at or below PL1. The  
hardware default value is 1 second; however, 28 seconds is  
recommended for most mobile applications.  
POWER_LIMIT_1_TIME  
(Turbo Time Parameter)  
23:17  
46:32  
1 sec  
PL2 establishes the upper power limit of turbo operation above  
TDP, primarily for platform power supply considerations. Power  
may exceed this limit for up to 10 ms. The default for this limit is  
1.25 x TDP; however, the BIOS may reprogram the default value  
to maximize the performance within platform power supply  
considerations. Setting this limit to TDP will limit the processor to  
only operate up to the TDP. It does not disable turbo because  
turbo is opportunistic and power/temperature dependent. Many  
workloads will allow some turbo frequencies for powers at or  
below TDP.  
POWER_LIMIT_2 (PL2)  
1.25 x TDP  
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Thermal Management—Processor  
Figure 22.  
Package Power Control  
5.9.3  
Turbo Time Parameter  
Turbo Time Parameter is a mathematical parameter (units in seconds) that controls  
the Intel Turbo Boost Technology algorithm using an average of energy usage. During  
a maximum power turbo event of about 1.25 x TDP, the processor could sustain  
Power_Limit_2 for up to approximately 1.5 the Turbo Time Parameter. See the  
appropriate processor Thermal Mechanical Design Guidelines for more information  
(see Related Documents section). If the power value and/or Turbo Time Parameter is  
changed during runtime, it may take a period of time (possibly up to approximately 3  
to 5 times the Turbo Time Parameter, depending on the magnitude of the change and  
other factors) for the algorithm to settle at the new control limits.  
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Processor—Signal Description  
6.0  
Signal Description  
This chapter describes the processor signals. The signals are arranged in functional  
groups according to the associated interface or category. The following notations are  
used to describe the signal type.  
Notation  
Signal Type  
I
Input pin  
O
Output pin  
I/O  
Bi-directional Input/Output pin  
The signal description also includes the type of buffer used for the particular signal  
(see the following table).  
Table 29.  
Signal Description Buffer Types  
Signal  
Description  
PCI Express* interface signals. These signals are compatible with PCI Express 3.0  
Signaling Environment AC Specifications and are AC coupled. The buffers are not 3.3 V-  
tolerant. See the PCI Express Base Specification 3.0.  
PCI Express*  
Direct Media Interface signals. These signals are compatible with PCI Express 2.0  
Signaling Environment AC Specifications, but are DC coupled. The buffers are not 3.3 V-  
tolerant.  
DMI  
CMOS  
CMOS buffers. 1.05V- tolerant  
DDR3/DDR3L  
DDR3/DDR3L buffers: 1.5 V- tolerant  
Analog reference or output. May be used as a threshold voltage or for buffer  
compensation  
A
GTL  
Gunning Transceiver Logic signaling technology  
Voltage reference signal  
Ref  
1
Asynchronous  
Signal has no timing relationship with any reference clock.  
1. Qualifier for a buffer type.  
6.1  
System Memory Interface Signals  
Table 30.  
Memory Channel A Signals  
Signal Name  
SA_BS[2:0]  
SA_WE#  
Description  
Direction / Buffer  
Type  
Bank Select: These signals define which banks are selected  
O
within each SDRAM rank.  
DDR3/DDR3L  
Write Enable Control Signal: This signal is used with  
SA_RAS# and SA_CAS# (along with SA_CS#) to define the  
SDRAM Commands.  
O
DDR3/DDR3L  
continued...  
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Signal Description—Processor  
Signal Name  
Description  
Direction / Buffer  
Type  
RAS Control Signal: This signal is used with SA_CAS# and  
SA_WE# (along with SA_CS#) to define the SRAM Commands.  
O
SA_RAS#  
SA_CAS#  
DDR3/DDR3L  
CAS Control Signal: This signal is used with SA_RAS# and  
SA_WE# (along with SA_CS#) to define the SRAM Commands.  
O
DDR3/DDR3L  
Data Strobes: SA_DQS[8:0] and its complement signal group  
make up a differential strobe pair. The data is captured at the  
crossing point of SA_DQS[8:0] and SA_DQS#[8:0] during read  
and write transactions.  
I/O  
SA_DQS[8:0]  
SA_DQSN[8:0]  
DDR3/DDR3L  
Data Bus: Channel A data signal interface to the SDRAM data  
bus.  
I/O  
SA_DQ[63:0]  
SA_MA[15:0]  
DDR3/DDR3L  
Memory Address: These signals are used to provide the  
multiplexed row and column address to the SDRAM.  
O
DDR3/DDR3L  
SDRAM Differential Clock: These signals are Channel A  
SDRAM Differential clock signal pairs. The crossing of the  
positive edge of SA_CK and the negative edge of its complement  
SA_CK# are used to sample the command and control signals on  
the SDRAM.  
O
SA_CK[3:0]  
DDR3/DDR3L  
Clock Enable: (1 per rank). These signals are used to:  
Initialize the SDRAMs during power-up  
Power-down SDRAM ranks  
O
SA_CKE[3:0]  
DDR3/DDR3L  
Place all SDRAM ranks into and out of self-refresh during STR  
Chip Select: (1 per rank). These signals are used to select  
particular SDRAM components during the active state. There is  
one Chip Select for each SDRAM rank.  
O
SA_CS#[3:0]  
SA_ODT[3:0]  
DDR3/DDR3L  
On Die Termination: Active Termination Control.  
O
DDR3/DDR3L  
Table 31.  
Memory Channel B Signals  
Signal Name  
SB_BS[2:0]  
SB_WE#  
Description  
Direction / Buffer  
Type  
Bank Select: These signals define which banks are selected  
O
within each SDRAM rank.  
DDR3/DDR3L  
Write Enable Control Signal: This signal is used with  
SB_RAS# and SB_CAS# (along with SB_CS#) to define the  
SDRAM Commands.  
O
DDR3/DDR3L  
RAS Control Signal: This signal is used with SB_CAS# and  
SB_WE# (along with SB_CS#) to define the SRAM Commands.  
O
SB_RAS#  
SB_CAS#  
DDR3/DDR3L  
CAS Control Signal: This signal is used with SB_RAS# and  
SB_WE# (along with SB_CS#) to define the SRAM Commands.  
O
DDR3/DDR3L  
Data Strobes: SB_DQS[8:0] and its complement signal group  
make up a differential strobe pair. The data is captured at the  
crossing point of SB_DQS[8:0] and its SB_DQS#[8:0] during  
read and write transactions.  
I/O  
SB_DQS[8:0]  
SB_DQSN[8:0]  
DDR3/DDR3L  
Data Bus: Channel B data signal interface to the SDRAM data  
bus.  
I/O  
SB_DQ[63:0]  
SB_MA[15:0]  
DDR3/DDR3L  
Memory Address: These signals are used to provide the  
multiplexed row and column address to the SDRAM.  
O
DDR3/DDR3L  
continued...  
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Signal Name  
Description  
Direction / Buffer  
Type  
SDRAM Differential Clock: Channel B SDRAM Differential  
clock signal pair. The crossing of the positive edge of SB_CK  
and the negative edge of its complement SB_CK# are used to  
sample the command and control signals on the SDRAM.  
O
SB_CK[3:0]  
DDR3/DDR3L  
Clock Enable: (1 per rank). These signals are used to:  
Initialize the SDRAMs during power-up.  
Power-down SDRAM ranks.  
O
SB_CKE[3:0]  
DDR3/DDR3L  
Place all SDRAM ranks into and out of self-refresh during  
STR.  
Chip Select: (1 per rank). These signals are used to select  
particular SDRAM components during the active state. There is  
one Chip Select for each SDRAM rank.  
O
SB_CS#[3:0]  
SB_ODT[3:0]  
DDR3/DDR3L  
On Die Termination: Active Termination Control.  
O
DDR3/DDR3L  
6.2  
Memory Reference and Compensation Signals  
Table 32.  
Memory Reference and Compensation Signals  
Signal Name  
SM_RCOMP[2:0]  
SM_VREF  
Description  
Direction /  
Buffer Type  
System Memory Impedance Compensation:  
I
A
DDR3/DDR3L Reference Voltage: This signal is used as  
a reference voltage to the DDR3/DDR3L controller and is  
defined as VDDQ/2  
O
DDR3/DDR3L  
Memory Channel A/B DIMM DQ Voltage Reference:  
The output pins are connected to the DIMMs, and holds  
VDDQ/2 as reference voltage.  
O
SA_DIMM_VREFDQ  
SB_DIMM_VREFDQ  
DDR3/DDR3L  
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6.3  
Reset and Miscellaneous Signals  
Table 33.  
Reset and Miscellaneous Signals  
Signal Name  
Description  
Direction /  
Buffer Type  
Configuration Signals: The CFG signals have a default value of  
'1' if not terminated on the board.  
CFG[1:0]: Reserved configuration lane. A test point may be  
placed on the board for these lanes.  
CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.  
— 1 = Normal operation  
— 0 = Lane numbers reversed.  
CFG[3]: MSR Privacy Bit Feature  
— 1 = Debug capability is determined by  
IA32_Debug_Interface_MSR (C80h) bit[0] setting  
I/O  
CFG[19:0]  
— 0 = IA32_Debug_Interface_MSR (C80h) bit[0] default  
setting overridden  
GTL  
CFG[4]: Reserved configuration lane. A test point may be  
placed on the board for this lane.  
CFG[6:5]: PCI Express* Bifurcation: 1  
— 00 = 1 x8, 2 x4 PCI Express*  
— 01 = reserved  
— 10 = 2 x8 PCI Express*  
— 11 = 1 x16 PCI Express*  
CFG[19:7]: Reserved configuration lanes. A test point may  
be placed on the board for these lands.  
Configuration resistance compensation. Use a 49.9 Ω ±1%  
resistor to ground.  
CFG_RCOMP  
FC_x  
FC (Future Compatibility) signals are signals that are available for  
compatibility with other processors. A test point may be placed  
on the board for these lands.  
Power Management Sync: A sideband signal to communicate  
power management status from the platform to the processor.  
I
PM_SYNC  
CMOS  
Signal is for debug.  
I
PWR_DEBUG#  
IST_TRIGGER  
Asynchronous  
CMOS  
Signal is for IFDIM testing only.  
I
CMOS  
Signal is for debug. If both THERMTRIP# and this signal are  
simultaneously asserted, the processor has encountered an  
unrecoverable power delivery fault and has engaged automatic  
shutdown as a result.  
O
IVR_ERROR  
RESET#  
CMOS  
Platform Reset pin driven by the PCH.  
I
CMOS  
RESERVED: All signals that are RSVD and RSVD_NCTF must be  
left unconnected on the board. Intel recommends that all  
RSVD_TP signals have via test points.  
No Connect  
Test Point  
RSVD  
RSVD_TP  
RSVD_NCTF  
Non-Critical to  
Function  
DRAM Reset: Reset signal from processor to DRAM devices. One  
signal common to all channels.  
O
SM_DRAMRST#  
TESTLO_x  
CMOS  
TESTLO should be individually connected to VSS through a  
resistor.  
Note: 1. PCIe bifurcation support varies with the processor and PCH SKUs used.  
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6.4  
PCI Express*-Based Interface Signals  
Table 34.  
PCI Express* Graphics Interface Signals  
Signal Name  
Description  
Direction / Buffer Type  
PCI Express Resistance Compensation  
I
PEG_RCOMP  
A
PEG_RXP[15:0]  
PEG_RXN[15:0]  
PCI Express Receive Differential Pair  
PCI Express Transmit Differential Pair  
I
PCI Express  
PEG_TXP[15:0]  
PEG_TXN[15:0]  
O
PCI Express  
6.5  
Display Interface Signals  
Table 35.  
Display Interface Signals  
Signal Name  
Description  
Direction / Buffer  
Type  
FDI_TXP[1:0]  
FDI_TXN[1:0]  
Intel Flexible Display Interface Transmit Differential Pair  
Digital Display Interface Transmit Differential Pair  
Digital Display Interface Transmit Differential Pair  
Digital Display Interface Transmit Differential Pair  
Intel Flexible Display Interface Sync  
O
FDI  
DDIB_TXP[3:0]  
DDIB_TXN[3:0]  
O
FDI  
DDIC_TXP[3:0]  
DDIC_TXN[3:0]  
O
FDI  
DDID_TXP[3:0]  
DDID_TXN[3:0]  
O
FDI  
I
FDI_CSYNC  
DISP_INT  
CMOS  
Intel Flexible Display Interface Hot-Plug Interrupt  
I
Asynchronous  
CMOS  
6.6  
Direct Media Interface (DMI)  
Table 36.  
Direct Media Interface (DMI) – Processor to PCH Serial Interface  
Signal Name  
Description  
Direction / Buffer  
Type  
DMI_RXP[3:0]  
DMI Input from PCH: Direct Media Interface receive  
differential pair.  
I
DMI_RXN[3:0]  
DMI  
DMI_TXP[3:0]  
DMI_TXN[3:0]  
DMI Output to PCH: Direct Media Interface transmit  
differential pair.  
O
DMI  
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Signal Description—Processor  
6.7  
Phase Locked Loop (PLL) Signals  
Table 37.  
Phase Locked Loop (PLL) Signals  
Signal Name  
Description  
Direction / Buffer  
Type  
BCLKP  
BCLKN  
Differential bus clock input to the processor  
I
Diff Clk  
DPLL_REF_CLKP  
DPLL_REF_CLKN  
Embedded Display Port PLL Differential Clock In:  
135 MHz  
I
Diff Clk  
SSC_DPLL_REF_CLKP  
SSC_ DPLL_REF_CLKN  
Spread Spectrum Embedded DisplayPort PLL  
Differential Clock In: 135 MHz  
I
Diff Clk  
6.8  
Testability Signals  
Table 38.  
Testability Signals  
Signal Name  
Description  
Direction / Buffer  
Type  
Breakpoint and Performance Monitor Signals:  
Outputs from the processor that indicate the status of  
breakpoints and programmable counters used for  
monitoring processor performance.  
I/O  
BPM#[7:0]  
DBR#  
CMOS  
Debug Reset: This signal is used only in systems where  
no debug port is implemented on the system board.  
DBR# is used by a debug port interposer so that an in-  
target probe can drive system reset.  
O
Processor Ready: This signal is a processor output  
used by debug tools to determine processor debug  
readiness.  
O
PRDY#  
PREQ#  
Asynchronous CMOS  
Processor Request: This signal is used by debug tools  
to request debug operation of the processor.  
I
Asynchronous CMOS  
Test Clock: This signal provides the clock input for the  
processor Test Bus (also known as the Test Access  
Port). This signal must be driven low or allowed to float  
during power on Reset.  
I
TCK  
TDI  
GTL  
Test Data In: This signal transfers serial test data into  
the processor. This signal provides the serial input  
needed for JTAG specification support.  
I
GTL  
Test Data Out: This signal transfers serial test data out  
of the processor. This signal provides the serial output  
needed for JTAG specification support.  
O
TDO  
Open Drain  
Test Mode Select: This is a JTAG specification  
supported signal used by debug tools.  
I
TMS  
GTL  
Test Reset: This signal resets the Test Access Port  
(TAP) logic. This signal must be driven low during power  
on Reset.  
I
TRST#  
GTL  
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6.9  
Error and Thermal Protection Signals  
Table 39.  
Error and Thermal Protection Signals  
Signal Name  
Description  
Direction / Buffer  
Type  
Catastrophic Error: This signal indicates that the system has  
experienced a catastrophic error and cannot continue to  
operate. The processor will set this for non-recoverable  
machine check errors or other unrecoverable internal errors.  
CATERR# is used for signaling the following types of errors:  
Legacy MCERRs, CATERR# is asserted for 16 BCLKs. Legacy  
IERRs, CATERR# remains asserted until warm or cold reset.  
O
CATERR#  
GTL  
Platform Environment Control Interface: A serial  
sideband interface to the processor, it is used primarily for  
thermal, power, and error management.  
I/O  
PECI  
Asynchronous  
Processor Hot: PROCHOT# goes active when the processor  
temperature monitoring sensor(s) detects that the processor  
has reached its maximum safe operating temperature. This  
indicates that the processor Thermal Control Circuit (TCC) has  
been activated, if enabled. This signal can also be driven to  
the processor to activate the TCC.  
GTL Input  
Open-Drain Output  
PROCHOT#  
Thermal Trip: The processor protects itself from catastrophic  
overheating by use of an internal thermal sensor. This sensor  
is set well above the normal operating temperature to ensure  
that there are no false trips. The processor will stop all  
execution when the junction temperature exceeds  
approximately 130 °C. This is signaled to the system by the  
THERMTRIP# pin.  
O
Asynchronous OD  
Asynchronous CMOS  
THERMTRIP#  
6.10  
Power Sequencing Signals  
Table 40.  
Power Sequencing Signals  
Signal Name  
Description  
Direction / Buffer  
Type  
SM_DRAMPWROK Processor Input: This signal  
connects to the PCH DRAMPWROK.  
I
SM_DRAMPWROK  
PWRGOOD  
Asynchronous CMOS  
The processor requires this input signal to be a clean  
indication that the VCC and VDDQ power supplies are  
stable and within specifications. This requirement  
applies regardless of the S-state of the processor.  
'Clean' implies that the signal will remain low (capable  
of sinking leakage current), without glitches, from the  
time that the power supplies are turned on until the  
supplies come within specification. The signal must  
then transition monotonically to a high state.  
I
Asynchronous CMOS  
SKTOCC# (Socket Occupied)/PROC_DETECT#:  
(Processor Detect): This signal is pulled down  
directly (0 Ohms) on the processor package to ground.  
There is no connection to the processor silicon for this  
signal. System board designers may use this signal to  
determine if the processor is present.  
SKTOCC#  
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6.11  
Processor Power Signals  
Table 41.  
Processor Power Signals  
Signal Name  
Description  
Direction / Buffer  
Type  
VCC  
Processor core power rail.  
Ref  
Ref  
Ref  
Ref  
VCCIO_OUT  
VDDQ  
Processor power reference for I/O.  
Processor I/O supply voltage for DDR3.  
Processor power reference for PEG/Display RCOMP.  
VCOMP_OUT  
VIDALERT#, VIDSCLK, and VIDSCLK comprise a three  
signal serial synchronous interface used to transfer  
power management information between the  
processor and the voltage regulator controllers.  
Input GTL/ Output Open  
Drain  
VIDSOUT  
VIDSCLK  
Output Open Drain  
Input CMOS  
VIDALERT#  
6.12  
Sense Signals  
Table 42.  
Sense Signals  
Signal Name  
Description  
Direction /  
Buffer Type  
VCC_SENSE and VSS_SENSE provide an isolated, low-  
impedance connection to the processor input VCC voltage  
and ground. The signals can be used to sense or measure  
voltage near the silicon.  
VCC_SENSE  
VSS_SENSE  
O
A
6.13  
Ground and Non-Critical to Function (NCTF) Signals  
Table 43.  
Ground and Non-Critical to Function (NCTF) Signals  
Signal Name  
Description  
Direction /  
Buffer Type  
VSS  
VSS_NCTF  
Processor ground node  
GND  
Non-Critical to Function: These pins are for package  
mechanical reliability.  
6.14  
Processor Internal Pull-Up / Pull-Down Terminations  
Table 44.  
Processor Internal Pull-Up / Pull-Down Terminations  
Signal Name  
BPM[7:0]  
Pull Up / Pull Down  
Pull Up  
Rail  
Value  
VCCIO_TERM  
VCCIO_TERM  
VCCIO_TERM  
VCCIO_TERM  
VCCIO_OUT  
VCCIO_TERM  
40–60 Ω  
40–60 Ω  
30–70 Ω  
30–70 Ω  
5–8 kΩ  
PREQ#  
TDI  
Pull Up  
Pull Up  
TMS  
Pull Up  
CFG[17:0]  
CATERR#  
Pull Up  
Pull Up  
30–70 Ω  
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Processor—Electrical Specifications  
7.0  
Electrical Specifications  
This chapter provides the processor electrical specifications including integrated  
voltage regulator (VR), VCC Voltage Identification (VID), reserved and unused signals,  
signal groups, Test Access Points (TAP), and DC specifications.  
7.1  
Integrated Voltage Regulator  
A new feature to the processor is the integration of platform voltage regulators into  
the processor. Due to this integration, the processor has one main voltage rail (VCC)  
and a voltage rail for the memory interface (VDDQ) , compared to six voltage rails on  
previous processors. The VCC voltage rail will supply the integrated voltage regulators  
which in turn will regulate to the appropriate voltages for the cores, cache, system  
agent, and graphics. This integration allows the processor to better control on-die  
voltages to optimize between performance and power savings. The processor VCC rail  
will remain a VID-based voltage with a loadline similar to the core voltage rail (also  
called VCC) in previous processors.  
7.2  
7.3  
Power and Ground Lands  
The processor has VCC, VDDQ, and VSS (ground) lands for on-chip power distribution.  
All power lands must be connected to their respective processor power planes; all VSS  
lands must be connected to the system ground plane. Use of multiple power and  
ground planes is recommended to reduce I*R drop. The VCC lands must be supplied  
with the voltage determined by the processor Serial Voltage IDentification (SVID)  
interface. Table 45 on page 91 specifies the voltage level for the various VIDs.  
VCC Voltage Identification (VID)  
The processor uses three signals for the serial voltage identification interface to  
support automatic selection of voltages. The following table specifies the voltage level  
corresponding to the 8-bit VID value transmitted over serial VID. A ‘1’ in this table  
refers to a high voltage level and a ‘0’ refers to a low voltage level. If the voltage  
regulation circuit cannot supply the voltage that is requested, the voltage regulator  
must disable itself. VID signals are CMOS push/pull drivers. See Table 53 on page  
102 for the DC specifications for these signals. The VID codes will change due to  
temperature and/or current load changes to minimize the power of the part. A voltage  
range is provided in Voltage and Current Specifications on page 98. The  
specifications are set so that one voltage regulator can operate with all supported  
frequencies.  
Individual processor VID values may be set during manufacturing so that two devices  
at the same core frequency may have different default VID settings. This is shown in  
the VID range values in Voltage and Current Specifications on page 98. The  
processor provides the ability to operate while transitioning to an adjacent VID and its  
associated voltage. This will represent a DC shift in the loadline.  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
Datasheet – Volume 1 of 2  
90  
December 2013  
Order No.: 328897-004  
       
Electrical Specifications—Processor  
Table 45.  
Voltage Regulator (VR) 12.5 Voltage Identification  
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7
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7
6
5
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3
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1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
00h  
0.0000  
0.5000  
0.5100  
0.5200  
0.5300  
0.5400  
0.5500  
0.5600  
0.5700  
0.5800  
0.5900  
0.6000  
0.6100  
0.6200  
0.6300  
0.6400  
0.6500  
0.6600  
0.6700  
0.6800  
0.6900  
0.7000  
0.7100  
0.7200  
0.7300  
0.7400  
0.7500  
0.7600  
0.7700  
0.7800  
0.7900  
0.8000  
0.8100  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
21h  
0.8200  
0.8300  
0.8400  
0.8500  
0.8600  
0.8700  
0.8800  
0.8900  
0.9000  
0.9100  
0.9200  
0.9300  
0.9400  
0.9500  
0.9600  
0.9700  
0.9800  
0.9900  
1.0000  
1.0100  
1.0200  
1.0300  
1.0400  
1.0500  
1.0600  
1.0700  
1.0800  
1.0900  
1.1000  
1.1100  
1.1200  
1.1300  
1.1400  
01h  
02h  
03h  
04h  
05h  
06h  
07h  
08h  
09h  
0Ah  
0Bh  
0Ch  
0Dh  
0Eh  
0Fh  
10h  
11h  
12h  
13h  
14h  
15h  
16h  
17h  
18h  
19h  
1Ah  
1Bh  
1Ch  
1Dh  
1Eh  
1Fh  
20h  
22h  
23h  
24h  
25h  
26h  
27h  
28h  
29h  
2Ah  
2Bh  
2Ch  
2Dh  
2Eh  
2Fh  
30h  
31h  
32h  
33h  
34h  
35h  
36h  
37h  
38h  
39h  
3Ah  
3Bh  
3Ch  
3Dh  
3Eh  
3Fh  
40h  
41h  
continued...  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
December 2013  
Order No.: 328897-004  
Datasheet – Volume 1 of 2  
91  
 
Processor—Electrical Specifications  
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0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
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1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
42h  
1.1500  
1.1600  
1.1700  
1.1800  
1.1900  
1.2000  
1.2100  
1.2200  
1.2300  
1.2400  
1.2500  
1.2600  
1.2700  
1.2800  
1.2900  
1.3000  
1.3100  
1.3200  
1.3300  
1.3400  
1.3500  
1.3600  
1.3700  
1.3800  
1.3900  
1.4000  
1.4100  
1.4200  
1.4300  
1.4400  
1.4500  
1.4600  
1.4700  
1.4800  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64h  
1.4900  
1.5000  
1.5100  
1.5200  
1.5300  
1.5400  
1.5500  
1.5600  
1.5700  
1.5800  
1.5900  
1.6000  
1.6100  
1.6200  
1.6300  
1.6400  
1.6500  
1.6600  
1.6700  
1.6800  
1.6900  
1.7000  
1.7100  
1.7200  
1.7300  
1.7400  
1.7500  
1.7600  
1.7700  
1.7800  
1.7900  
1.8000  
1.8100  
1.8200  
43h  
44h  
45h  
46h  
47h  
48h  
49h  
4Ah  
4Bh  
4Ch  
4Dh  
4Eh  
4Fh  
50h  
51h  
52h  
53h  
54h  
55h  
56h  
57h  
58h  
59h  
5Ah  
5Bh  
5Ch  
5Dh  
5Eh  
5Fh  
60h  
61h  
62h  
63h  
65h  
66h  
67h  
68h  
69h  
6Ah  
6Bh  
6Ch  
6Dh  
6Eh  
6Fh  
70h  
71h  
72h  
73h  
74h  
75h  
76h  
77h  
78h  
79h  
7Ah  
7Bh  
7Ch  
7Dh  
7Eh  
7Fh  
80h  
81h  
82h  
83h  
84h  
85h  
continued...  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
Datasheet – Volume 1 of 2  
92  
December 2013  
Order No.: 328897-004  
Electrical Specifications—Processor  
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1
0
1
1
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1
1
1
1
1
1
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1
1
1
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1
1
1
1
1
1
1
1
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1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
86h  
1.8300  
1.8400  
1.8500  
1.8600  
1.8700  
1.8800  
1.8900  
1.9000  
1.9100  
1.9200  
1.9300  
1.9400  
1.9500  
1.9600  
1.9700  
1.9800  
1.9900  
2.0000  
2.0100  
2.0200  
2.0300  
2.0400  
2.0500  
2.0600  
2.0700  
2.0800  
2.0900  
2.1000  
2.1100  
2.1200  
2.1300  
2.1400  
2.1500  
2.1600  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A8h  
2.1700  
2.1800  
2.1900  
2.2000  
2.2100  
2.2200  
2.2300  
2.2400  
2.2500  
2.2600  
2.2700  
2.2800  
2.2900  
2.3000  
2.3100  
2.3200  
2.3300  
2.3400  
2.3500  
2.3600  
2.3700  
2.3800  
2.3900  
2.4000  
2.4100  
2.4200  
2.4300  
2.4400  
2.4500  
2.4600  
2.4700  
2.4800  
2.4900  
2.5000  
87h  
88h  
89h  
8Ah  
8Bh  
8Ch  
8Dh  
8Eh  
8Fh  
90h  
91h  
92h  
93h  
94h  
95h  
96h  
97h  
98h  
99h  
9Ah  
9Bh  
9Ch  
9Dh  
9Eh  
9Fh  
A0h  
A1h  
A2h  
A3h  
A4h  
A5h  
A6h  
A7h  
A9h  
AAh  
ABh  
ACh  
ADh  
AEh  
AFh  
B0h  
B1h  
B2h  
B3h  
B4h  
B5h  
B6h  
B7h  
B8h  
B9h  
BAh  
BBh  
BCh  
BDh  
BEh  
BFh  
C0h  
C1h  
C2h  
C3h  
C4h  
C5h  
C6h  
C7h  
C8h  
C9h  
continued...  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
December 2013  
Order No.: 328897-004  
Datasheet – Volume 1 of 2  
93  
Processor—Electrical Specifications  
B
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t
B
i
t
B
i
t
B
i
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B
i
t
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Hex  
VCC  
B
i
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B
i
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B
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B
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Hex  
VCC  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CAh  
2.5100  
2.5200  
2.5300  
2.5400  
2.5500  
2.5600  
2.5700  
2.5800  
2.5900  
2.6000  
2.6100  
2.6200  
2.6300  
2.6400  
2.6500  
2.6600  
2.6700  
2.6800  
2.6900  
2.7000  
2.7100  
2.7200  
2.7300  
2.7400  
2.7500  
2.7600  
2.7700  
2.7800  
2.7900  
2.8000  
2.8100  
2.8200  
2.8300  
2.8400  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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0
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1
1
1
1
1
1
1
1
1
1
1
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1
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1
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1
1
0
0
0
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1
1
1
1
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1
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1
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0
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0
0
0
1
1
1
1
0
0
1
1
0
0
1
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0
0
1
1
0
0
1
1
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0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ECh  
2.8500  
2.8600  
2.8700  
2.8800  
2.8900  
2.9000  
2.9100  
2.9200  
2.9300  
2.9400  
2.9500  
2.9600  
2.9700  
2.9800  
2.9900  
3.0000  
3.0100  
3.0200  
3.0300  
3.0400  
CBh  
CCh  
CDh  
CEh  
CFh  
D0h  
D1h  
D2h  
D3h  
D4h  
D5h  
D6h  
D7h  
D8h  
D9h  
DAh  
DBh  
DCh  
DDh  
DEh  
DFh  
E0h  
E1h  
E2h  
E3h  
E4h  
E5h  
E6h  
E7h  
E8h  
E9h  
EAh  
EBh  
EDh  
EEh  
EFh  
F0h  
F1h  
F2h  
F3h  
F4h  
F5h  
F6h  
F7h  
F8h  
F9h  
FAh  
FBh  
FCh  
FDh  
FEh  
FFh  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
Datasheet – Volume 1 of 2  
94  
December 2013  
Order No.: 328897-004  
Electrical Specifications—Processor  
7.4  
Reserved or Unused Signals  
The following are the general types of reserved (RSVD) signals and connection  
guidelines:  
RSVD – these signals should not be connected  
RSVD_TP – these signals should be routed to a test point  
RSVD_NCTF – these signals are non-critical to function and may be left un-  
connected  
Arbitrary connection of these signals to VCC, VDDQ, VSS, or to any other signal  
(including each other) may result in component malfunction or incompatibility with  
future processors. See Signal Description on page 82 for a pin listing of the processor  
and the location of all reserved signals.  
For reliable operation, always connect unused inputs or bi-directional signals to an  
appropriate signal level. Unused active high inputs should be connected through a  
resistor to ground (VSS). Unused outputs maybe left unconnected; however, this may  
interfere with some Test Access Port (TAP) functions, complicate debug probing, and  
prevent boundary scan testing. A resistor must be used when tying bi-directional  
signals to power or ground. When tying any signal to power or ground, a resistor will  
also allow for system testability.  
7.5  
Signal Groups  
Signals are grouped by buffer type and similar characteristics as listed in the following  
table. The buffer type indicates which signaling technology and specifications apply to  
the signals. All the differential signals and selected DDR3/DDR3L and Control Sideband  
signals have On-Die Termination (ODT) resistors. Some signals do not have ODT and  
need to be terminated on the board.  
Note:  
All Control Sideband Asynchronous signals are required to be asserted/de-asserted for  
at least 10 BCLKs with maximum Trise/Tfall of 6 ns for the processor to recognize the  
proper signal state. See the DC Specifications section and AC Specifications section.  
Table 46.  
Signal Groups  
Signal Group  
Type  
Signals  
System Reference Clock  
Differential  
CMOS Input  
BCLKP, BCLKN, DPLL_REF_CLKP, DPLL_REF_CLKN,  
SSC_DPLL_REF_CLKP, SSC_DPLL_REF_CLKN  
DDR3 / DDR3L Reference Clocks 2  
Differential  
DDR3/DDR3L  
Output  
SA_CKP[3:0], SA_CKN[3:0], SB_CKP[3:0], SB_CKN[3:0]  
DDR3 / DDR3L Command Signals 2  
Single ended  
DDR3/DDR3L  
Output  
SA_BS[2:0], SB_BS[2:0], SA_WE#, SB_WE#, SA_RAS#,  
SB_RAS#, SA_CAS#, SB_CAS#, SA_MA[15:0], SB_MA[15:0]  
DDR3 / DDR3L Control Signals 2  
Single ended  
DDR3/DDR3L  
Output  
SA_CKE[3:0], SB_CKE[3:0], SA_CS#[3:0], SB_CS#[3:0],  
SA_ODT[3:0], SB_ODT[3:0]  
Single ended  
CMOS Output  
SM_DRAMRST#  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
December 2013  
Order No.: 328897-004  
Datasheet – Volume 1 of 2  
95  
     
Processor—Electrical Specifications  
Signal Group  
Type  
Signals  
DDR3 / DDR3L Data Signals 2  
Single ended  
Differential  
DDR3/DDR3L Bi-  
directional  
SA_DQ[63:0], SB_DQ[63:0]  
DDR3/DDR3L Bi-  
directional  
SA_DQSP[7:0], SA_DQSN[7:0], SB_DQSP[7:0], SB_DQSN[7:0]  
DDR3 / DDR3L Compensation  
Analog Input  
SM_RCOMP[2:0]  
DDR3 / DDR3L Reference Voltage Signals  
DDR3/DDR3L  
Output  
SM_VREF, SA_DIMM_VREFDQ, SB_DIMM_VREFDQ  
Testability (ITP/XDP)  
Single ended  
Single ended  
Single ended  
Single ended  
Single ended  
Single ended  
Control Sideband  
Single ended  
CMOS Input  
GTL  
TCK, TDI, TMS, TRST#  
TDO  
Output  
GTL  
DBR#  
BPM#[7:0]  
PREQ#  
GTL  
GTL  
PRDY#  
GTL Input/Open  
Drain Output  
PROCHOT#  
Single ended  
Asynchronous  
CMOS Output  
THERMTRIP#, IVR_ERROR  
Single ended  
Single ended  
GTL  
CATERR#  
Asynchronous  
CMOS Input  
PM_SYNC,RESET#, PWRGOOD, PWR_DEBUG#  
Single ended  
Asynchronous Bi-  
directional  
PECI  
Single ended  
Single ended  
Voltage Regulator  
Single ended  
Single ended  
Single ended  
Single ended  
GTL Bi-directional  
Analog Input  
CFG[19:0]  
SM_RCOMP[2:0]  
CMOS Input  
VR_READY  
VIDALERT#  
VIDSCLK  
CMOS Input  
Open Drain Output  
GTL Input/Open  
Drain Output  
VIDSOUT  
Differential  
Analog Output  
VCC_SENSE, VSS_SENSE  
Power / Ground / Other  
Single ended Power  
VCC, VDDQ  
Ground  
VSS, VSS_NCTF 3  
No Connect  
RSVD, RSVD_NCTF  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
Datasheet – Volume 1 of 2  
96  
December 2013  
Order No.: 328897-004  
Electrical Specifications—Processor  
Signal Group  
Type  
Test Point  
Other  
PCI Express* Graphics  
Signals  
RSVD_TP  
SKTOCC#,  
Differential  
Differential  
Single ended  
PCI Express Input  
PEG_RXP[15:0], PEG_RXN[15:0]  
PCI Express Output PEG_TXP[15:0], PEG_TXN[15:0]  
Analog Input  
PEG_RCOMP  
Digital Media Interface (DMI)  
Differential  
Differential  
DMI Input  
DMI_RXP[3:0], DMI_RXN[3:0]  
DMI_TXP[3:0], DMI_TXN[3:0]  
DMI Output  
Digital Display Interface  
Differential  
DDI Output  
DDIB_TXP[3:0], DDIB_TXN[3:0], DDIC_TXP[3:0],  
DDIC_TXN[3:0], DDID_TXP[3:0], DDID_TXN[3:0]  
Intel® FDI  
Single ended  
Single ended  
CMOS Input  
FDI_CSYNC  
DISP_INT  
Asynchronous  
CMOS Input  
Differential  
FDI Output  
FDI_TXP[1:0], FDI_TXN[1:0]  
Notes: 1. See Signal Description on page 82 for signal description details.  
2. SA and SB refer to DDR3/DDR3L Channel A and DDR3/DDR3L Channel B.  
7.6  
Test Access Port (TAP) Connection  
Due to the voltage levels supported by other components in the Test Access Port  
(TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any  
other components within the system. A translation buffer should be used to connect to  
the rest of the chain unless one of the other components is capable of accepting an  
input of the appropriate voltage. Two copies of each signal may be required with each  
driving a different voltage level.  
The processor supports Boundary Scan (JTAG) IEEE 1149.1-2001 and IEEE  
1149.6-2003 standards. A few of the I/O pins may support only one of those  
standards.  
7.7  
DC Specifications  
The processor DC specifications in this section are defined at the processor pins,  
unless noted otherwise. See Signal Description on page 82 for the processor pin  
listings and signal definitions.  
The DC specifications for the DDR3/DDR3L signals are listed in the Voltage and  
Current Specifications section.  
The Voltage and Current Specifications section lists the DC specifications for the  
processor and are valid only while meeting specifications for junction temperature,  
clock frequency, and input voltages. Read all notes associated with each  
parameter.  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
December 2013  
Order No.: 328897-004  
Datasheet – Volume 1 of 2  
97  
   
Processor—Electrical Specifications  
AC tolerances for all DC rails include dynamic load currents at switching  
frequencies up to 1 MHz.  
7.8  
Voltage and Current Specifications  
Table 47.  
Processor Core Active and Idle Mode DC Voltage and Current Specifications  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Note1  
2013D: 1.75  
2013C: 1.75  
2013B: 1.75  
2013A: 1.75  
Operational  
VID  
VID Range  
1.65  
1.86  
V
2
Idle VID  
(package  
C6/C7)  
VID Range  
1.5  
1.6  
1.65  
V
2
Loadline  
slope within  
the VR  
regulation  
loop  
2013D PCG: -1.5  
2013C PCG: -1.5  
2013B PCG: -1.5  
2013A PCG: -1.5  
R_DC_LL  
mΩ  
3, 5, 6, 8  
capability  
Loadline  
slope in  
response to  
dynamic load  
increase  
2013D PCG: -2.4  
2013C PCG: -2.4  
2013B PCG: -2.4  
2013A PCG: -2.4  
R_AC_LL  
mΩ  
mΩ  
events  
Loadline  
slope in  
response to  
dynamic load  
release  
2013D PCG: -3.0  
2013C PCG: -3.0  
2013B PCG: -3.0  
2013A PCG: -3.0  
R_AC_LL_OS  
events  
Overshoot  
time  
T_OVS  
V_OVS  
500  
50  
uS  
Overshoot  
mV  
VCC  
Tolerance  
Band  
VCC TOB  
± 20 (PS0, PS1, PS2, PS3)  
mV  
mV  
3, 5, 6, 7, 8  
3, 5, 6, 7, 8  
Ripple  
± 10 (PS0)  
± 15 (PS1)  
VCC Ripple  
+50/-15 (PS2)  
+60/-15 (PS3)  
Default VCC  
voltage for  
initial power  
up  
VCC,BOOT  
1.70  
V
2013D PCG  
ICC  
ICC  
ICC  
ICC  
95  
75  
58  
A
A
A
4, 8  
4, 8  
2013C PCG  
ICC  
2013B PCG  
ICC  
4, 8  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
Datasheet – Volume 1 of 2  
98  
December 2013  
Order No.: 328897-004  
   
Electrical Specifications—Processor  
Symbol  
ICC  
Parameter  
Min  
Typ  
Max  
48  
Unit  
A
Note1  
4, 8  
9
2013A PCG  
ICC  
2013D PCG  
PMAX  
153  
W
PMAX  
PMAX  
PMAX  
PMAX  
2013C PCG  
PMAX  
121  
99  
W
W
W
9
9
9
2013B PCG  
PMAX  
2013A PCG  
PMAX  
83  
Notes: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or  
empirical data.  
2. Each processor is programmed with a maximum valid voltage identification value (VID) that is  
set at manufacturing and cannot be altered. Individual maximum VID values are calibrated  
during manufacturing such that two processors at the same frequency may have different  
settings within the VID range. This differs from the VID employed by the processor during a  
power management event (Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or  
Low-Power States).  
3. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands  
at the socket with a 20-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-  
MΩ minimum impedance. The maximum length of ground wire on the probe should be less than  
5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.  
4. ICC_MAX specification is based on the VCC loadline at worst case (highest) tolerance and ripple.  
5. The VCC specifications represent static and transient limits.  
6. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE  
lands. Voltage regulation feedback for voltage regulator circuits must also be taken from  
processor VCC_SENSE and VSS_SENSE lands.  
7. PSx refers to the voltage regulator power state as set by the SVID protocol.  
8. PCG is Platform Compatibility Guide (previously known as FMB). These guidelines are for  
estimation purposes only.  
9. PMAX is the maximum power the processor will dissipate as measured at VCC_SENSE and  
VSS_SENSE lands. The processor may draw this power for up to 10 ms before it regulates to  
PL2.  
Table 48.  
Memory Controller (VDDQ) Supply DC Voltage and Current Specifications  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Note  
Processor I/O supply  
voltage for DDR3/DDR3L  
(DC + AC specification)  
VDDQ (DC+AC)  
DDR3/DDR3L  
Typ-5%  
1.5  
Typ+5%  
V
2, 3, 5  
Processor I/O supply  
voltage for DDR3L (DC +  
AC specification)  
VDDQ (DC+AC)  
DDR3/DDR3L  
Typ-5%  
1.35  
Typ+5%  
V
2, 3  
IccMAX_VDDQ (DDR3/  
DDR3L)  
Max Current for VDDQ Rail  
2.5  
20  
A
1
4
Average Current for VDDQ  
Rail during Standby  
12  
mA  
ICCAVG_VDDQ (Standby)  
Notes: 1. The current supplied to the SO-DIMM modules is not included in this specification.  
2. Includes AC and DC error, where the AC noise is bandwidth limited to under 20 MHz.  
3. No requirement on the breakdown of AC versus DC noise.  
4. Measured at 50 °C  
5. This specification applies to desktop processors  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
December 2013  
Order No.: 328897-004  
Datasheet – Volume 1 of 2  
99  
 
Processor—Electrical Specifications  
Table 49.  
VCCIO_OUT, VCOMP_OUT, and VCCIO_TERM  
Symbol  
Parameter  
Typ  
Max  
Units  
Notes  
Termination  
Voltage  
VCCIO_OUT  
1.0  
V
Maximum  
External Load  
ICCIO_OUT  
VCOMP_OUT  
VCCIO_TERM  
300  
mA  
V
Termination  
Voltage  
1.0  
1.0  
1
2
Termination  
Voltage  
V
Notes: 1. VCOMP_OUT may only be used to connect to PEG_RCOMP and DP_RCOMP.  
2. Internal processor power for signal termination.  
Table 50.  
DDR3 / DDR3L Signal Group DC Specifications  
Symbol  
Parameter  
Input Low Voltage  
Input High Voltage  
Min  
Typ  
Max  
0.43*VDDQ  
Units  
Notes1  
VIL  
VDDQ/2  
VDDQ/2  
V
V
2, 4, 11  
3, 11  
VIH  
0.57*VDDQ  
Input Low Voltage  
(SM_DRAMPWROK)  
VIL  
0.15*VDDQ  
1.0  
V
V
Input High Voltage  
(SM_DRAMPWROK)  
VIH  
0.45*VDDQ  
10, 12  
DDR3/DDR3L Data  
Buffer pull-up  
Resistance  
RON_UP(DQ)  
20  
20  
26  
32  
Ω
5, 11  
DDR3/DDR3L Data  
Buffer pull-down  
Resistance  
RON_DN(DQ)  
26  
50  
32  
62  
Ω
Ω
5, 11  
11  
DDR3/DDR3L On-die  
termination equivalent  
resistance for data  
signals  
RODT(DQ)  
38  
DDR3/DDR3L On-die  
termination DC working  
point (driver set to  
receive mode)  
VODT(DC)  
0.45*VDDQ  
0.5*VDDQ  
0.55*VDDQ  
V
11  
DDR3/DDR3L Clock  
Buffer pull-up  
Resistance  
5, 11,  
13  
RON_UP(CK)  
RON_DN(CK)  
RON_UP(CMD)  
RON_DN(CMD)  
RON_UP(CTL)  
20  
20  
15  
15  
19  
26  
26  
20  
20  
25  
32  
32  
25  
25  
31  
Ω
Ω
Ω
Ω
Ω
DDR3/DDR3L Clock  
Buffer pull-down  
Resistance  
5, 11,  
13  
DDR3/DDR3L Command  
Buffer pull-up  
Resistance  
5, 11,  
13  
DDR3/DDR3L Command  
Buffer pull-down  
Resistance  
5, 11,  
13  
DDR3/DDR3L Control  
Buffer pull-up  
Resistance  
5, 11,  
13  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
Datasheet – Volume 1 of 2  
100  
December 2013  
Order No.: 328897-004  
   
Electrical Specifications—Processor  
Symbol  
Parameter  
Min  
Typ  
Max  
Units  
Notes1  
DDR3/DDR3L Control  
Buffer pull-down  
Resistance  
5, 11,  
13  
RON_DN(CTL)  
19  
25  
31  
Ω
DDR3/DDR3L Reset  
Buffer pull-up  
Resistance  
RON_UP(RST)  
40  
40  
80  
80  
130  
130  
Ω
Ω
DDR3/DDR3L Reset  
Buffer pull-up  
Resistance  
RON_DN(RST)  
Input Leakage Current  
(DQ, CK)  
0V  
ILI  
0.7  
mA  
0.2*VDDQ  
0.8*VDDQ  
Input Leakage Current  
(CMD, CTL)  
0V  
ILI  
1.0  
mA  
Ω
8
0.2*VDDQ  
0.8*VDDQ  
Command COMP  
Resistance  
SM_RCOMP0  
99  
100  
101  
74.25  
99  
SM_RCOMP1  
SM_RCOMP2  
Data COMP Resistance  
ODT COMP Resistance  
75  
75.75  
101  
Ω
Ω
8
8
100  
Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.  
2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a  
logical low value.  
3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a  
logical high value.  
4. VIH and VOH may experience excursions above VDDQ. However, input signal drivers must comply  
with the signal quality specifications.  
5. This is the pull up/down driver resistance.  
6. RTERM is the termination on the DIMM and in not controlled by the processor.  
7. The minimum and maximum values for these signals are programmable by BIOS to one of the  
two sets.  
8. SM_RCOMPx resistance must be provided on the system board with 1% resistors. SM_RCOMPx  
resistors are to VSS  
.
9. SM_DRAMPWROK rise and fall time must be < 50 ns measured between VDDQ *0.15 and VDDQ  
*0.47.  
10.SM_VREF is defined as VDDQ/2.  
11.Maximum-minimum range is correct; however, center point is subject to change during MRC  
boot training.  
12.Processor may be damaged if VIH exceeds the maximum voltage for extended periods.  
13.The MRC during boot training might optimize RON outside the range specified.  
Table 51.  
Digital Display Interface Group DC Specifications  
Symbol  
VIL  
Parameter  
HPD Input Low Voltage  
Min  
Typ  
Max  
0.8  
Units  
V
V
VIH  
HPD Input High Voltage  
2.25  
3.6  
Aux peak-to-peak voltage at transmitting  
device  
Vaux(Tx)  
0.39  
0.32  
1.38  
1.36  
V
V
Aux peak-to-peak voltage at receiving  
device  
Vaux(Rx)  
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Processor—Electrical Specifications  
Table 52.  
embedded DisplayPort* (eDP*) Group DC Specifications  
Symbol  
Parameter  
Min  
0.02  
Typ  
Max  
0.21  
1.05  
Units  
VIL  
HPD Input Low Voltage  
V
V
V
V
Ω
Ω
VIH  
VOL  
VOH  
RUP  
HPD Input High Voltage  
0.84  
eDP_DISP_UTIL Output Low Voltage  
eDP_DISP_UTIL Output High Voltage  
eDP_DISP_UTIL Internal pull-up  
eDP_DISP_UTIL Internal pull-down  
0.1*VCC  
0.9*VCC  
100  
RDOWN  
100  
Aux peak-to-peak voltage at  
transmitting device  
Vaux(Tx)  
0.39  
0.32  
1.38  
1.36  
V
V
Ω
Aux peak-to-peak voltage at receiving  
device  
Vaux(Rx)  
eDP_RCOMP  
DP_RCOMP  
COMP Resistance  
24.75  
25  
25.25  
Note: 1. COMP resistance is to VCOMP_OUT.  
Table 53.  
CMOS Signal Group DC Specifications  
Symbol  
Parameter  
Min  
Max  
Units  
Notes1  
2
VIL  
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
Output High Voltage  
Buffer on Resistance  
VCCIO_OUT* 0.3  
V
V
V
V
Ω
VIH  
VOL  
VOH  
RON  
VCCIO_OUT* 0.7  
2, 4  
2
VCCIO_OUT * 0.9  
23  
VCCIO_OUT * 0.1  
2, 4  
73  
Input Leakage  
Current  
ILI  
±150  
μA  
3
Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.  
2. The VCCIO_OUT referred to in these specifications refers to instantaneous VCCIO_OUT.  
3. For VIN between “0” V and VCCIO_OUT. Measured when the driver is tri-stated.  
4. VIH and VOH may experience excursions above VCCIO_OUT. However, input signal drivers must  
comply with the signal quality specifications.  
Table 54.  
GTL Signal Group and Open Drain Signal Group DC Specifications  
Symbol  
Parameter  
Min  
Max  
Units  
Notes1  
Input Low Voltage (TAP, except  
TCK)  
VIL  
VCCIO_TERM * 0.6  
V
2
Input High Voltage (TAP, except  
TCK)  
VIH  
VCCIO_TERM * 0.72  
V
2, 4  
VIL  
Input Low Voltage (TCK)  
Input High Voltage (TCK)  
Hysteresis Voltage  
VCCIO_TERM * 0.4  
V
V
V
Ω
V
2
2, 4  
VIH  
VCCIO_TERM * 0.8  
VHYSTERESIS  
RON  
VCCIO_TERM * 0.2  
28  
Buffer on Resistance (TDO)  
Input Low Voltage (other GTL)  
12  
VIL  
VCCIO_TERM * 0.6  
2
continued...  
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Electrical Specifications—Processor  
Symbol  
Parameter  
Min  
Max  
Units  
V
Notes1  
VIH  
RON  
RON  
ILI  
Input High Voltage (other GTL)  
Buffer on Resistance (CFG/BPM)  
Buffer on Resistance (other GTL)  
Input Leakage Current  
VCCIO_TERM * 0.72  
2, 4  
16  
12  
24  
Ω
28  
Ω
±150  
μA  
3
Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.  
2. The VCCIO_OUT referred to in these specifications refers to instantaneous VCCIO_OUT.  
3. For VIN between 0 V and VCCIO_TERM. Measured when the driver is tri-stated.  
4. VIH and VOH may experience excursions above VCCIO_TERM. However, input signal drivers must  
comply with the signal quality specifications.  
Table 55.  
PCI Express* DC Specifications  
Symbol  
Parameter  
Min  
Typ  
Max  
Units  
Notes1  
DC Differential Tx Impedance (Gen 1  
Only)  
ZTX-DIFF-DC  
80  
120  
Ω
1, 6  
DC Differential Tx Impedance (Gen 2 and  
Gen 3)  
ZTX-DIFF-DC  
ZRX-DC  
40  
120  
60  
Ω
Ω
Ω
Ω
1, 6  
1, 4, 5  
1
DC Common Mode Rx Impedance  
DC Differential Rx Impedance (Gen1  
Only)  
ZRX-DIFF-DC  
80  
120  
PEG_RCOMP Comp Resistance  
24.75  
25  
25.25  
2, 3  
Notes: 1. See the PCI Express Base Specification for more details.  
2. PEG_RCOMP should be connected to VCOMP_OUT through a 25 Ω ±1% resistor.  
3. Intel allows using 24.9 Ω ±1% resistors.  
4. DC impedance limits are needed to ensure Receiver detect.  
5. The Rx DC Common Mode Impedance must be present when the Receiver terminations are first  
enabled to ensure that the Receiver Detect occurs properly. Compensation of this impedance can  
start immediately and the 15 Rx Common Mode Impedance (constrained by RLRX-CM to 50 Ω  
±20%) must be within the specified range by the time Detect is entered.  
6. Low impedance defined during signaling. Parameter is captured for 5.0 GHz by RLTX-DIFF.  
7.8.1  
Platform Environment Control Interface (PECI) DC  
Characteristics  
The PECI interface operates at a nominal voltage set by VCCIO_TERM. The set of DC  
electrical specifications shown in the following table is used with devices normally  
operating from a VCCIO_TERM interface supply.  
VCCIO_TERM nominal levels will vary between processor families. All PECI devices will  
operate at the VCCIO_TERM level determined by the processor installed in the system.  
Table 56.  
Platform Environment Control Interface (PECI) DC Electrical Limits  
Symbol  
Definition and Conditions  
Internal pull up resistance  
Input Voltage Range  
Min  
Max  
Units  
Notes1  
Rup  
Vin  
15  
45  
Ω
3
VCCIO_TERM  
0.15  
+
-0.15  
V
V
Hysteresis  
0.1 *  
VCCIO_TERM  
Vhysteresis  
N/A  
continued...  
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Processor—Electrical Specifications  
Symbol  
Definition and Conditions  
Min  
Max  
Units  
Notes1  
Negative-Edge Threshold  
Voltage  
0.500  
0.275 *  
VCCIO_TERM  
Vn  
Vp  
V
* VCCIO_TERM  
Positive-Edge Threshold  
Voltage  
0.550 *  
VCCIO_TERM  
0.725 *  
VCCIO_TERM  
V
Cbus  
Cpad  
Bus Capacitance per Node  
Pad Capacitance  
N/A  
0.7  
10  
1.8  
0.6  
pF  
pF  
Ileak000  
Ileak025  
leakage current at 0 V  
mA  
leakage current at 0.25*  
VCCIO_TERM  
0.4  
0.2  
mA  
mA  
mA  
mA  
leakage current at 0.50*  
VCCIO_TERM  
Ileak050  
Ileak075  
Ileak100  
leakage current at 0.75*  
VCCIO_TERM  
0.13  
0.10  
leakage current at  
VCCIO_TERM  
Notes: 1. VCCIO_TERM supplies the PECI interface. PECI behavior does not affect VCCIO_TERM minimum /  
maximum specifications.  
2. The leakage specification applies to powered devices on the PECI bus.  
3. The PECI buffer internal pull-up resistance measured at 0.75* VCCIO_TERM  
.
7.8.2  
Input Device Hysteresis  
The input buffers in both client and host models must use a Schmitt-triggered input  
design for improved noise immunity. Use the following figure as a guide for input  
buffer design.  
Figure 23.  
Input Device Hysteresis  
VTTD  
Maximum VP  
Minimum VP  
PECI High Range  
Minimum  
Valid Input  
Hysteresis  
Signal Range  
Maximum VN  
Minimum VN  
PECI Ground  
PECI Low Range  
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Package Mechanical Specifications—Processor  
8.0  
Package Mechanical Specifications  
The processor is packaged in a Flip-Chip Land Grid Array package that interfaces with  
the motherboard using the LGA1150 socket. The package consists of a processor  
mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to  
the package substrate and core and serves as the mating surface for processor  
thermal solutions, such as a heatsink. The following figure shows a sketch of the  
processor package components and how they are assembled together.  
The package components shown in the following figure include the following:  
1. Integrated Heat Spreader (IHS)  
2. Thermal Interface Material (TIM)  
3. Processor core (die)  
4. Package substrate  
5. Capacitors  
Figure 24.  
Processor Package Assembly Sketch  
8.1  
8.2  
Processor Component Keep-Out Zone  
The processor may contain components on the substrate that define component keep-  
out zone requirements. A thermal and mechanical solution design must not intrude  
into the required keep-out zones. Decoupling capacitors are typically mounted to the  
land-side of the package substrate. Refer to the LGA1150 Socket Application Guide for  
keep-out zones. The location and quantity of package capacitors may change due to  
manufacturing efficiencies but will remain within the component keep-in. This keep-in  
zone includes solder paste and is a post reflow maximum height for the components.  
Package Loading Specifications  
The following table provides dynamic and static load specifications for the processor  
package. These mechanical maximum load limits should not be exceeded during  
heatsink assembly, shipping conditions, or standard use condition. Also, any  
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Processor—Package Mechanical Specifications  
mechanical system or component testing should not exceed the maximum limits. The  
processor package substrate should not be used as a mechanical reference or load-  
bearing surface for thermal and mechanical solution.  
Table 57.  
Processor Loading Specifications  
Parameter  
Minimum  
Maximum  
Notes  
1, 2, 3  
1, 3, 4  
Static Compressive Load  
600 N [135 lbf]  
712 N [160 lbf]  
Dynamic Compressive  
Load  
Notes: 1. These specifications apply to uniform compressive loading in a direction normal to the processor,  
IHS.  
2. This is the maximum static force that can be applied by the heatsink and retention solution to  
maintain the heatsink and processor interface.  
3. These specifications are based on limited testing for design characterization. Loading limits are  
for the package only and do not include the limits of the processor socket.  
4. Dynamic loading is defined as an 50g shock load, 2X Dynamic Acceleration Factor with a 500g  
maximum thermal solution.  
8.3  
Package Handling Guidelines  
The following table includes a list of guidelines on package handling in terms of  
recommended maximum loading on the processor IHS relative to a fixed substrate.  
These package handling loads may be experienced during heatsink removal.  
Table 58.  
Package Handling Guidelines  
Parameter  
Shear  
Maximum Recommended  
311 N [70 lbf]  
Notes  
1, 4  
Tensile  
111 N [25 lbf]  
2, 4  
Torque  
3.95 N-m [35 lbf-in]  
3, 4  
Notes: 1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.  
2. A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS  
surface.  
3. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the  
IHS top surface.  
4. These guidelines are based on limited testing for design characterization.  
8.4  
Package Insertion Specifications  
The processor can be inserted into and removed from an LGA1150 socket 15 times.  
The socket should meet the LGA1150 socket requirements detailed in the LGA1150  
Socket Application Guide.  
8.5  
8.6  
Processor Mass Specification  
The typical mass of the processor is 27.0 g (0.95 oz). This mass [weight] includes all  
the components that are included in the package.  
Processor Materials  
The following table lists some of the package components and associated materials.  
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Package Mechanical Specifications—Processor  
Table 59.  
Processor Materials  
Component  
Material  
Integrated Heat Spreader (IHS)  
Substrate  
Nickel Plated Copper  
Fiber Reinforced Resin  
Gold Plated Copper  
Substrate Lands  
8.7  
Processor Markings  
The following figure shows the top-side markings on the processor. This diagram aids  
in the identification of the processor.  
Figure 25.  
Processor Top-Side Markings  
8.8  
Processor Land Coordinates  
The following figure shows the bottom view of the processor package.  
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Processor—Package Mechanical Specifications  
Figure 26.  
Processor Package Land Coordinates  
8.9  
Processor Storage Specifications  
The following table includes a list of the specifications for device storage in terms of  
maximum and minimum temperatures and relative humidity. These conditions should  
not be exceeded in storage or transportation.  
Table 60.  
Processor Storage Specifications  
Parameter  
Description  
Minimum  
Maximum  
Notes  
The non-operating device storage  
temperature. Damage (latent or  
otherwise) may occur when subjected to  
for any length of time.  
Tabsolute storage  
-55 °C  
125 °C  
1, 2, 3  
The ambient storage temperature limit  
(in shipping media) for a sustained  
period of time.  
Tsustained storage  
-5 °C  
40 °C  
4, 5  
continued...  
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Package Mechanical Specifications—Processor  
Parameter  
Description  
Minimum  
Maximum  
Notes  
The maximum device storage relative  
humidity for a sustained period of time.  
RHsustained storage  
60% @ 24 °C  
5, 6  
A prolonged or extended period of time;  
typically associated with customer shelf  
life.  
TIMEsustained storage  
0 Months  
6 Months  
6
Notes: 1. Refers to a component device that is not assembled in a board or socket that is not to be  
electrically connected to a voltage reference or I/O signals.  
2. Specified temperatures are based on data collected. Exceptions for surface mount reflow are  
specified in by applicable JEDEC standard. Non-adherence may affect processor reliability.  
3. TABSOLUTE storage applies to the unassembled component only and does not apply to the shipping  
media, moisture barrier bags, or desiccant.  
4. Intel branded board products are certified to meet the following temperature and humidity limits  
that are given as an example only (Non-Operating Temperature Limit: -40 °C to 70 °C,  
Humidity: 50% to 90%, non-condensing with a maximum wet bulb of 28 °C). Post board attach  
storage temperature limits are not specified for non-Intel branded boards.  
5. The JEDEC, J-JSTD-020 moisture level rating and associated handling practices apply to all  
moisture sensitive devices removed from the moisture barrier bag.  
6. Nominal temperature and humidity conditions and durations are given and tested within the  
constraints imposed by Tsustained storage and customer shelf life in applicable Intel box and bags.  
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Processor—Processor Ball and Signal Information  
9.0  
Processor Ball and Signal Information  
This chapter provides processor ball information. The following table provides the ball  
list by signal name.  
Note:  
References to SA_ECC_CB[7:0] and SB_ECC_CB[7:0] are for processor SKUs that  
support ECC. These signals are reserved on the Desktop 4th Generation Intel® Core™  
processor family.  
Table 61.  
Processor Ball List by Signal Name  
Signal Name  
BCLKN  
BCLKP  
Ball #  
V4  
Signal Name  
CFG3  
Ball #  
W38  
V39  
U39  
U40  
V38  
T40  
Y35  
G40  
F17  
Signal Name  
DDID_TXDN1  
DDID_TXDN2  
DDID_TXDN3  
DDID_TXDP0  
DDID_TXDP1  
DDID_TXDP2  
DDID_TXDP3  
DISP_INT  
Ball #  
B16  
C17  
B18  
B15  
A16  
B17  
A18  
D18  
T3  
V5  
CFG4  
BPM#0  
BPM#1  
BPM#2  
BPM#3  
BPM#4  
BPM#5  
BPM#6  
BPM#7  
CATERR#  
CFG_RCOMP  
CFG0  
G39  
J39  
CFG5  
CFG6  
G38  
H37  
H38  
J38  
CFG7  
CFG8  
CFG9  
DBR#  
K39  
K37  
M36  
H40  
AA37  
Y38  
AA34  
V37  
Y34  
U38  
W34  
V35  
Y37  
Y36  
W36  
V36  
DDIB_TXBN0  
DDIB_TXBN1  
DDIB_TXBN2  
DDIB_TXBN3  
DDIB_TXBP0  
DDIB_TXBP1  
DDIB_TXBP2  
DDIB_TXBP3  
DDIC_TXCN0  
DDIC_TXCN1  
DDIC_TXCN2  
DDIC_TXCN3  
DDIC_TXCP0  
DDIC_TXCP1  
DDIC_TXCP2  
DDIC_TXCP3  
DDID_TXDN0  
DMI_RXN0  
DMI_RXN1  
DMI_RXN2  
DMI_RXN3  
DMI_RXP0  
DMI_RXP1  
DMI_RXP2  
DMI_RXP3  
DMI_TXN0  
DMI_TXN1  
DMI_TXN2  
DMI_TXN3  
DMI_TXP0  
G18  
H19  
G20  
E17  
F18  
V1  
V2  
W3  
U3  
CFG1  
U1  
CFG10  
G19  
F20  
W2  
CFG11  
Y3  
CFG12  
E19  
D20  
E21  
D22  
D19  
C20  
D21  
C22  
AA5  
AB4  
AC4  
AC2  
AA4  
AB3  
AC5  
AC1  
CFG13  
CFG14  
CFG15  
CFG16  
CFG17  
DMI_TXP1  
CFG18  
DMI_TXP2  
CFG19  
DMI_TXP3  
CFG2  
AA36  
C15  
DP_RCOMP  
R4  
continued...  
continued...  
continued...  
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Processor Ball and Signal Information—Processor  
Signal Name  
DPLL_REF_CLKN  
DPLL_REF_CLKP  
EDP_DISP_UTIL  
FC_K9  
Ball #  
W6  
W5  
E16  
K9  
Signal Name  
PEG_RXP14  
PEG_RXP15  
PEG_RXP2  
PEG_RXP3  
PEG_RXP4  
PEG_RXP5  
PEG_RXP6  
PEG_RXP7  
PEG_RXP8  
PEG_RXP9  
PEG_TXN0  
PEG_TXN1  
PEG_TXN10  
PEG_TXN11  
PEG_TXN12  
PEG_TXN13  
PEG_TXN14  
PEG_TXN15  
PEG_TXN2  
PEG_TXN3  
PEG_TXN4  
PEG_TXN5  
PEG_TXN6  
PEG_TXN7  
PEG_TXN8  
PEG_TXN9  
PEG_TXP0  
PEG_TXP1  
PEG_TXP10  
PEG_TXP11  
PEG_TXP12  
PEG_TXP13  
PEG_TXP14  
PEG_TXP15  
PEG_TXP2  
PEG_TXP3  
Ball #  
K5  
Signal Name  
PEG_TXP4  
PEG_TXP5  
PEG_TXP6  
PEG_TXP7  
PEG_TXP8  
PEG_TXP9  
PM_SYNC  
PRDY#  
PREQ#  
PROCHOT#  
PWR_DEBUG  
PWRGOOD  
RESET#  
RSVD  
Ball #  
C8  
L4  
B7  
E13  
D12  
E11  
F10  
E9  
A6  
B5  
FC_Y7  
Y7  
E1  
FDI_CSYNC  
FDI0_TX0N0  
FDI0_TX0N1  
FDI0_TX0P0  
FDI0_TX0P1  
IST_TRIGGER  
IVR_ERROR  
PECI  
D16  
B14  
C13  
A14  
B13  
C39  
R36  
N37  
P3  
F2  
P36  
F8  
L39  
D3  
E4  
L37  
K38  
B12  
C11  
G2  
H3  
N40  
AB35  
M39  
AB33  
AB36  
AB8  
PEG_RCOMP  
PEG_RXN0  
PEG_RXN1  
PEG_RXN10  
PEG_RXN11  
PEG_RXN12  
PEG_RXN13  
PEG_RXN14  
PEG_RXN15  
PEG_RXN2  
PEG_RXN3  
PEG_RXN4  
PEG_RXN5  
PEG_RXN6  
PEG_RXN7  
PEG_RXN8  
PEG_RXN9  
PEG_RXP0  
F15  
E14  
F6  
J2  
RSVD  
K3  
RSVD  
M3  
L2  
RSVD  
AC8  
G5  
RSVD  
AK20  
AL20  
AT40  
AU1  
AU27  
AU39  
AV2  
H6  
D10  
C9  
RSVD  
J5  
RSVD  
K6  
D8  
C7  
RSVD  
L5  
RSVD  
F13  
E12  
F11  
G10  
F9  
B6  
RSVD  
C5  
RSVD  
E2  
RSVD  
AV20  
AV24  
AV29  
AW12  
AW23  
AW24  
AW27  
AY18  
H12  
F3  
RSVD  
A12  
B11  
G1  
H2  
RSVD  
G8  
RSVD  
D4  
RSVD  
E5  
RSVD  
E15  
D14  
F5  
J1  
RSVD  
PEG_RXP1  
K2  
RSVD  
PEG_RXP10  
PEG_RXP11  
PEG_RXP12  
PEG_RXP13  
M2  
L1  
RSVD  
G4  
RSVD  
H14  
H5  
C10  
RSVD  
H15  
J4  
B9  
RSVD  
J15  
continued...  
continued...  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
December 2013  
Order No.: 328897-004  
Datasheet – Volume 1 of 2  
111  
Processor—Processor Ball and Signal Information  
Signal Name  
RSVD  
Ball #  
J17  
J40  
J9  
Signal Name  
RSVD_TP  
SA_BS0  
Ball #  
P37  
Signal Name  
SA_DQ20  
SA_DQ21  
SA_DQ22  
SA_DQ23  
SA_DQ24  
SA_DQ25  
SA_DQ26  
SA_DQ27  
SA_DQ28  
SA_DQ29  
SA_DQ3  
Ball #  
AM37  
AM38  
AP37  
AP40  
AV37  
AW37  
AU35  
AV35  
AT37  
AU37  
AF39  
AT35  
AW35  
AY6  
RSVD  
AV12  
AY11  
AT21  
AU9  
RSVD  
SA_BS1  
RSVD  
L10  
L12  
M10  
M11  
M38  
N35  
P33  
R33  
R34  
T34  
T35  
T8  
SA_BS2  
RSVD  
SA_CAS#  
SA_CK0  
RSVD  
AY15  
AW15  
AV14  
AW13  
AV22  
AT23  
AU22  
AU23  
AY16  
AV15  
AW14  
AY13  
AU14  
AV9  
RSVD  
SA_CK1  
RSVD  
SA_CK2  
RSVD  
SA_CK3  
RSVD  
SA_CKE0  
SA_CKE1  
SA_CKE2  
SA_CKE3  
SA_CKN0  
SA_CKN1  
SA_CKN2  
SA_CKN3  
SA_CS#0  
SA_CS#1  
SA_CS#2  
SA_CS#3  
RSVD  
RSVD  
SA_DQ30  
SA_DQ31  
SA_DQ32  
SA_DQ33  
SA_DQ34  
SA_DQ35  
SA_DQ36  
SA_DQ37  
SA_DQ38  
SA_DQ39  
SA_DQ4  
RSVD  
RSVD  
RSVD  
AU6  
RSVD  
U8  
AV4  
RSVD  
W8  
Y8  
AU4  
RSVD  
AW6  
AV6  
RSVD_TP  
RSVD_TP  
RSVD_TP  
RSVD_TP  
RSVD_TP  
RSVD_TP  
RSVD_TP  
RSVD_TP  
RSVD_TP  
RSVD_TP  
RSVD_TP  
RSVD_TP  
RSVD_TP  
RSVD_TP  
RSVD_TP  
RSVD_TP  
RSVD_TP  
RSVD_TP  
A4  
AV1  
AW2  
B3  
AU10  
AW8  
AW4  
AY4  
SA_DIMM_VREF  
DQ  
AB39  
AD37  
AR1  
C2  
SA_DQ40  
SA_DQ41  
SA_DQ42  
SA_DQ43  
SA_DQ44  
SA_DQ45  
SA_DQ46  
SA_DQ47  
SA_DQ48  
SA_DQ49  
SA_DQ5  
SA_DQ0  
AD38  
AD39  
AK38  
AK39  
AH37  
AH38  
AK37  
AK40  
AM40  
AM39  
AP38  
AP39  
D1  
AR4  
SA_DQ1  
H16  
J10  
J12  
J13  
J16  
J8  
AN3  
SA_DQ10  
SA_DQ11  
SA_DQ12  
SA_DQ13  
SA_DQ14  
SA_DQ15  
SA_DQ16  
SA_DQ17  
SA_DQ18  
SA_DQ19  
SA_DQ2  
AN4  
AR2  
AR3  
AN2  
AN1  
K11  
K12  
K13  
K8  
AL1  
AL4  
AD40  
AJ3  
SA_DQ50  
SA_DQ51  
SA_DQ52  
N36  
AJ4  
AF38  
N38  
AL2  
continued...  
continued...  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
Datasheet – Volume 1 of 2  
112  
December 2013  
Order No.: 328897-004  
Processor Ball and Signal Information—Processor  
Signal Name  
SA_DQ53  
Ball #  
AL3  
Signal Name  
SA_ECC_CB3  
SA_ECC_CB4  
SA_ECC_CB5  
SA_ECC_CB6  
SA_ECC_CB7  
SA_MA0  
Ball #  
AV31  
AT33  
AU33  
AT31  
AW31  
AU13  
AV16  
AW11  
AV19  
AU19  
AY10  
AT20  
AU21  
AU16  
AW17  
AU17  
AW18  
AV17  
AT18  
AU18  
AT19  
AW10  
AY8  
Signal Name  
SB_CKE1  
SB_CKE2  
SB_CKE3  
SB_CKN0  
SB_CKN1  
SB_CKN2  
SB_CKN3  
SB_CS#0  
SB_CS#1  
SB_CS#2  
SB_CS#3  
Ball #  
AY29  
AU28  
AU29  
AM21  
AP21  
AN21  
AP20  
AP17  
AN15  
AN17  
AL15  
AB40  
SA_DQ54  
AJ2  
SA_DQ55  
AJ1  
SA_DQ56  
AG1  
SA_DQ57  
AG4  
SA_DQ58  
AE3  
SA_DQ59  
AE4  
SA_MA1  
SA_DQ6  
AF37  
AG2  
SA_MA10  
SA_MA11  
SA_MA12  
SA_MA13  
SA_MA14  
SA_MA15  
SA_MA2  
SA_DQ60  
SA_DQ61  
AG3  
SA_DQ62  
AE2  
SA_DQ63  
AE1  
SB_DIMM_VREF  
DQ  
SA_DQ7  
AF40  
AH40  
AH39  
AE38  
AJ38  
AN38  
AU36  
AW5  
AP2  
SB_DQ0  
AE34  
AE35  
AK31  
AL31  
AK34  
AK35  
AK32  
AL32  
AN34  
AP34  
AN31  
AP31  
AG35  
AN35  
AP35  
AN32  
AP32  
AM29  
AM28  
AR29  
AR28  
AL29  
SA_DQ8  
SB_DQ1  
SA_DQ9  
SA_MA3  
SB_DQ10  
SB_DQ11  
SB_DQ12  
SB_DQ13  
SB_DQ14  
SB_DQ15  
SB_DQ16  
SB_DQ17  
SB_DQ18  
SB_DQ19  
SB_DQ2  
SA_DQSN0  
SA_DQSN1  
SA_DQSN2  
SA_DQSN3  
SA_DQSN4  
SA_DQSN5  
SA_DQSN6  
SA_DQSN7  
SA_DQSN8  
SA_DQSP0  
SA_DQSP1  
SA_DQSP2  
SA_DQSP3  
SA_DQSP4  
SA_DQSP5  
SA_DQSP6  
SA_DQSP7  
SA_DQSP8  
SA_ECC_CB0  
SA_ECC_CB1  
SA_ECC_CB2  
SA_MA4  
SA_MA5  
SA_MA6  
SA_MA7  
SA_MA8  
SA_MA9  
AK2  
SA_ODT0  
SA_ODT1  
SA_ODT2  
SA_ODT3  
SA_RAS#  
SA_WE#  
SB_BS0  
AF2  
AU32  
AE39  
AJ39  
AN39  
AV36  
AV5  
AW9  
AU8  
AU12  
AU11  
AK17  
AL18  
AW28  
AP16  
AM20  
AP22  
AN20  
AP19  
SB_DQ20  
SB_DQ21  
SB_DQ22  
SB_DQ23  
SB_DQ24  
SB_DQ25  
SB_DQ26  
SB_DQ27  
SB_DQ28  
SB_DQ29  
SB_BS1  
AP3  
SB_BS2  
AK3  
SB_CAS#  
SB_CK0  
AF3  
AV32  
AW33  
AV33  
SB_CK1  
SB_CK2  
SB_CK3  
AL28  
AU31  
SB_CKE0  
AW29  
continued...  
continued...  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
December 2013  
Order No.: 328897-004  
Datasheet – Volume 1 of 2  
113  
Processor—Processor Ball and Signal Information  
Signal Name  
SB_DQ3  
Ball #  
AH35  
AP29  
AP28  
AR12  
AP12  
AL13  
AL12  
AR13  
AP13  
AM13  
AM12  
AD34  
AR9  
Signal Name  
SB_DQ62  
Ball #  
AF6  
Signal Name  
SB_MA13  
SB_MA14  
SB_MA15  
SB_MA2  
Ball #  
AR15  
AV27  
AY28  
AM22  
AM23  
AP23  
AL23  
AY24  
AV25  
AU26  
AW25  
AM17  
AL16  
AM16  
AK15  
AM18  
AK16  
D38  
SB_DQ30  
SB_DQ31  
SB_DQ32  
SB_DQ33  
SB_DQ34  
SB_DQ35  
SB_DQ36  
SB_DQ37  
SB_DQ38  
SB_DQ39  
SB_DQ4  
SB_DQ63  
AF7  
SB_DQ7  
AH34  
AL34  
AL35  
AF35  
AL33  
AP33  
AN28  
AN12  
AP8  
SB_DQ8  
SB_DQ9  
SB_MA3  
SB_DQS0  
SB_MA4  
SB_DQS1  
SB_MA5  
SB_DQS2  
SB_MA6  
SB_DQS3  
SB_MA7  
SB_DQS4  
SB_MA8  
SB_DQS5  
SB_MA9  
SB_DQS6  
AL8  
SB_ODT0  
SB_ODT1  
SB_ODT2  
SB_ODT3  
SB_RAS#  
SB_WE#  
SKTOCC#  
SB_DQ40  
SB_DQ41  
SB_DQ42  
SB_DQ43  
SB_DQ44  
SB_DQ45  
SB_DQ46  
SB_DQ47  
SB_DQ48  
SB_DQ49  
SB_DQ5  
SB_DQS7  
AG7  
AP9  
SB_DQS8  
AN25  
AF34  
AK33  
AN33  
AN29  
AN13  
AR8  
AR6  
SB_DQSN0  
SB_DQSN1  
SB_DQSN2  
SB_DQSN3  
SB_DQSN4  
SB_DQSN5  
SB_DQSN6  
SB_DQSN7  
SB_DQSN8  
SB_ECC_CB0  
SB_ECC_CB1  
SB_ECC_CB2  
SB_ECC_CB3  
SB_ECC_CB4  
SB_ECC_CB5  
SB_ECC_CB6  
SB_ECC_CB7  
SB_MA0  
AP6  
AR10  
AP10  
AR7  
SM_DRAMPWRO  
K
AK21  
AP7  
SM_DRAMRST#  
SM_RCOMP0  
SM_RCOMP1  
SM_RCOMP2  
SM_VREF  
AK22  
R1  
AM9  
AL9  
AM8  
AG6  
P1  
AD35  
AL6  
AN26  
AM26  
AM25  
AP25  
AP26  
AL26  
AL25  
AR26  
AR25  
AL19  
AK23  
AP18  
AY25  
R2  
SB_DQ50  
SB_DQ51  
SB_DQ52  
SB_DQ53  
SB_DQ54  
SB_DQ55  
SB_DQ56  
SB_DQ57  
SB_DQ58  
SB_DQ59  
SB_DQ6  
AB38  
U5  
AL7  
SSC_DPLL_REF_  
CLKN  
AM10  
AL10  
AM6  
AM7  
AH6  
SSC_DPLL_REF_  
CLKP  
U6  
TCK  
D39  
F38  
F39  
N5  
TDI  
TDO  
AH7  
TESTLO_N5  
TESTLO_P6  
THERMTRIP#  
TMS  
AE6  
P6  
AE7  
SB_MA1  
F37  
E39  
AG34  
AJ6  
SB_MA10  
SB_DQ60  
SB_DQ61  
SB_MA11  
TRST#  
E37  
AJ7  
SB_MA12  
AV26  
continued...  
continued...  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
Datasheet – Volume 1 of 2  
114  
December 2013  
Order No.: 328897-004  
Processor Ball and Signal Information—Processor  
Signal Name  
VCC  
Ball #  
A24  
A25  
A26  
A27  
A28  
A29  
A30  
B25  
B27  
B29  
B31  
B33  
B35  
C24  
C25  
C26  
C27  
C28  
C29  
C30  
C31  
C32  
C33  
C34  
C35  
D25  
D27  
D29  
D31  
D33  
D35  
E24  
E25  
E26  
E27  
Signal Name  
VCC  
Ball #  
E29  
E30  
E31  
E32  
E33  
E34  
E35  
F23  
F25  
F27  
F29  
F31  
F33  
F35  
G22  
G23  
G24  
G25  
G26  
G27  
G28  
G29  
G30  
G31  
G32  
G33  
G34  
G35  
H23  
H25  
H27  
H29  
H31  
H33  
H35  
Signal Name  
VCC  
Ball #  
J22  
J23  
J24  
J25  
J26  
J27  
J28  
J29  
J30  
J31  
J32  
J33  
J34  
J35  
K19  
K21  
K23  
K25  
K27  
K29  
K31  
K33  
K35  
L15  
L16  
L17  
L18  
L19  
L20  
L21  
L22  
L23  
L24  
L25  
L26  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
E28  
J21  
L27  
continued...  
continued...  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
December 2013  
Order No.: 328897-004  
Datasheet – Volume 1 of 2  
115  
Processor—Processor Ball and Signal Information  
Signal Name  
VCC  
Ball #  
L28  
Signal Name  
VDDQ  
Ball #  
AU20  
AU24  
AV10  
AV11  
AV13  
AV18  
AV23  
AV8  
Signal Name  
VSS  
Ball #  
AC34  
AC35  
AC36  
AC37  
AC38  
AC39  
AC40  
AC6  
VCC  
L29  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VIDALERT#  
VIDSCLK  
VIDSOUT  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VCC  
L30  
VCC  
L31  
VCC  
L32  
VCC  
L33  
VCC  
L34  
VCC  
M13  
M15  
M17  
M19  
M21  
M23  
M25  
M27  
M29  
M33  
M8  
VCC  
AW16  
AY12  
AY14  
AY9  
AC7  
VCC  
AD1  
VCC  
AD2  
VCC  
AD3  
VCC  
B37  
AD33  
AD36  
AD4  
VCC  
C38  
VCC  
C37  
VCC  
A11  
AD5  
VCC  
VSS  
A13  
AD6  
VCC  
VSS  
A15  
AD7  
VCC  
P8  
VSS  
A17  
AD8  
VCC_SENSE  
VCCIO_OUT  
VCOMP_OUT  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
E40  
VSS  
A23  
AE33  
AE36  
AE37  
AE40  
AE5  
L40  
VSS  
A5  
P4  
VSS  
A7  
AJ12  
AJ13  
AJ15  
AJ17  
AJ20  
AJ21  
AJ24  
AJ25  
AJ28  
AJ29  
AJ9  
VSS  
AA3  
VSS  
AA33  
AA35  
AA38  
AA6  
VSS  
AE8  
VSS  
AF1  
VSS  
AF33  
AF36  
AF4  
VSS  
AA7  
VSS  
AA8  
VSS  
AB34  
AB37  
AB5  
AF5  
VSS  
AF8  
VSS  
AG33  
AG36  
AG37  
AG38  
VSS  
AB6  
AT17  
AT22  
VSS  
AB7  
VSS  
AC3  
AU15  
VSS  
AC33  
AG39  
continued...  
continued...  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
Datasheet – Volume 1 of 2  
116  
December 2013  
Order No.: 328897-004  
Processor Ball and Signal Information—Processor  
Signal Name  
VSS  
Ball #  
AG40  
AG5  
Signal Name  
VSS  
Ball #  
AK14  
AK18  
AK19  
AK24  
AK25  
AK26  
AK27  
AK28  
AK29  
AK30  
AK36  
AK4  
Signal Name  
VSS  
Ball #  
AM2  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
AM24  
AM27  
AM3  
AG8  
AH1  
AH2  
AM30  
AM31  
AM32  
AM33  
AM34  
AM35  
AM36  
AM4  
AH3  
AH33  
AH36  
AH4  
AH5  
AH8  
AJ11  
AJ14  
AJ16  
AJ18  
AJ19  
AJ22  
AJ23  
AJ26  
AJ27  
AJ30  
AJ31  
AJ32  
AJ33  
AJ34  
AJ35  
AJ36  
AJ37  
AJ40  
AJ5  
AK5  
AM5  
AK6  
AN10  
AN11  
AN14  
AN16  
AN18  
AN19  
AN22  
AN23  
AN24  
AN27  
AN30  
AN36  
AN37  
AN40  
AN5  
AK7  
AK8  
AK9  
AL11  
AL14  
AL17  
AL21  
AL22  
AL24  
AL27  
AL30  
AL36  
AL37  
AL38  
AL39  
AL40  
AL5  
AN6  
AN7  
AJ8  
AN8  
AK1  
AM1  
AN9  
AK10  
AK11  
AK12  
AM11  
AM14  
AM15  
AP1  
AP11  
AP14  
AK13  
AM19  
AP15  
continued...  
continued...  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
December 2013  
Order No.: 328897-004  
Datasheet – Volume 1 of 2  
117  
Processor—Processor Ball and Signal Information  
Signal Name  
VSS  
Ball #  
AP24  
AP27  
AP30  
AP36  
AP4  
Signal Name  
VSS  
Ball #  
AT15  
AT16  
AT2  
Signal Name  
VSS  
Ball #  
AV7  
AW26  
AW3  
AW30  
AW32  
AW34  
AW36  
AW7  
AY17  
AY23  
AY26  
AY27  
AY30  
AY5  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
AT24  
AT25  
AT26  
AT27  
AT28  
AT29  
AT3  
AP5  
AR11  
AR14  
AR16  
AR17  
AR18  
AR19  
AR20  
AR21  
AR22  
AR23  
AR24  
AR27  
AR30  
AR31  
AR32  
AR33  
AR34  
AR35  
AR36  
AR37  
AR38  
AR39  
AR40  
AR5  
AT30  
AT32  
AT34  
AT36  
AT38  
AT39  
AT4  
AY7  
B10  
B23  
AT5  
B24  
AT6  
B26  
AT7  
B28  
AT8  
B30  
AT9  
B32  
AU2  
B34  
AU25  
AU3  
B36  
B4  
AU30  
AU34  
AU38  
AU5  
B8  
C12  
C14  
C16  
AU7  
C18  
AT1  
AV21  
AV28  
AV3  
C19  
AT10  
AT11  
AT12  
AT13  
C21  
C23  
AV30  
AV34  
C3  
C36  
AT14  
AV38  
C4  
continued...  
continued...  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
Datasheet – Volume 1 of 2  
118  
December 2013  
Order No.: 328897-004  
Processor Ball and Signal Information—Processor  
Signal Name  
VSS  
Ball #  
C6  
Signal Name  
VSS  
Ball #  
F22  
F24  
F26  
F28  
F30  
F32  
F34  
F36  
F4  
Signal Name  
VSS  
Ball #  
H30  
H32  
H34  
H36  
H39  
H4  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
D11  
D13  
D15  
D17  
D2  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
D23  
D24  
D26  
D28  
D30  
D32  
D34  
D36  
D37  
D5  
H7  
H8  
H9  
F7  
J11  
J14  
J18  
J19  
J20  
J3  
G11  
G12  
G13  
G14  
G15  
G16  
G17  
G21  
G3  
J36  
J37  
J6  
D6  
D7  
D9  
J7  
E10  
E18  
E20  
E22  
E23  
E3  
G36  
G37  
G6  
K1  
K10  
K14  
K15  
K16  
K17  
K18  
K20  
K22  
K24  
K26  
K28  
K30  
K32  
K34  
K36  
G7  
G9  
H1  
E36  
E38  
E6  
H10  
H11  
H13  
H17  
H18  
H20  
H21  
H22  
H24  
H26  
E7  
E8  
F1  
F12  
F14  
F16  
F19  
F21  
H28  
K4  
continued...  
continued...  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
December 2013  
Order No.: 328897-004  
Datasheet – Volume 1 of 2  
119  
Processor—Processor Ball and Signal Information  
Signal Name  
VSS  
Ball #  
K40  
K7  
Signal Name  
VSS  
Ball #  
N3  
Signal Name  
VSS  
Ball #  
T7  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
N33  
N34  
N39  
N4  
VSS  
U2  
L11  
L13  
L14  
L3  
VSS  
U33  
U34  
U35  
U36  
U37  
U4  
VSS  
VSS  
N6  
VSS  
L35  
L36  
L38  
L6  
N7  
VSS  
N8  
VSS  
P2  
VSS  
U7  
P34  
P35  
P38  
P39  
P40  
P5  
VSS  
V3  
L7  
VSS  
V33  
V34  
V40  
V6  
L8  
VSS  
L9  
VSS  
M1  
VSS  
M12  
M14  
M16  
M18  
M20  
M22  
M24  
M26  
M28  
M30  
M32  
M34  
M35  
M37  
M4  
VSS  
V7  
P7  
VSS  
V8  
R3  
VSS  
W1  
R35  
R37  
R38  
R39  
R40  
R5  
VSS  
W33  
W35  
W37  
W4  
VSS  
VSS  
VSS  
VSS  
W7  
VSS  
Y33  
Y4  
R6  
VSS  
R7  
VSS  
Y5  
R8  
VSS  
Y6  
T1  
VSS_NCTF  
VSS_NCTF  
VSS_NCTF  
VSS_NCTF  
VSS_NCTF  
VSS_NCTF  
VSS_NCTF  
VSS_NCTF  
VSS_SENSE  
AU40  
AV39  
AW38  
AY3  
B38  
B39  
C40  
D40  
F40  
T2  
T33  
T36  
T37  
T38  
T39  
T4  
M40  
M5  
M6  
M7  
M9  
N1  
T5  
N2  
T6  
continued...  
continued...  
Desktop 4th Generation Intel® CoreProcessor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®  
Processor Family  
Datasheet – Volume 1 of 2  
120  
December 2013  
Order No.: 328897-004  

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