Intel 80C186EA User Manual
80C186EA/80C188EA AND 80L186EA/80L188EA  
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS  
Y
80C186 Upgrade for Power Critical Applications  
Y
Fully Static Operation  
Y
True CMOS Inputs and Outputs  
Y
Y
Integrated Feature Set  
Ð Static 186 CPU Core  
Ð Power Save, Idle and Powerdown  
Modes  
Ð Clock Generator  
Ð 2 Independent DMA Channels  
Ð 3 Programmable 16-Bit Timers  
Ð Dynamic RAM Refresh Control Unit  
Ð Programmable Memory and  
Peripheral Chip Select Logic  
Ð Programmable Wait State Generator  
Ð Local Bus Controller  
Speed Versions Available (3V):  
Ð 13 MHz (80L186EA13/80L188EA13)  
Ð 8 MHz (80L186EA8/80L188EA8)  
Y
Y
Y
Direct Addressing Capability to  
1 Mbyte Memory and 64 Kbyte I/O  
Supports 80C187 Numeric Coprocessor  
Interface (80C186EA only)  
Available in the Following Packages:  
Ð 68-Pin Plastic Leaded Chip Carrier  
(PLCC)  
Ð 80-Pin EIAJ Quad Flat Pack (QFP)  
Ð 80-Pin Shrink Quad Flat Pack (SQFP)  
Ð System-Level Testing Support  
(High Impedance Test Mode)  
Y
Available in Extended Temperature  
Y
Speed Versions Available (5V):  
b
Range ( 40 C to 85 C)  
a
§
§
Ð 25 MHz (80C186EA25/80C188EA25)  
Ð 20 MHz (80C186EA20/80C188EA20)  
Ð 13 MHz (80C186EA13/80C188EA13)  
The 80C186EA is a CHMOS high integration embedded microprocessor. The 80C186EA includes all of the  
features of an ‘‘Enhanced Mode’’ 80C186 while adding the additional capabilities of Idle and Powerdown  
Modes. In Numerics Mode, the 80C186EA interfaces directly with an 80C187 Numerics Coprocessor.  
272432–1  
*Other brands and names are the property of their respective owners.  
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or  
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make  
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.  
October 1995  
COPYRIGHT INTEL CORPORATION, 1995  
Order Number: 272432-003  
©
1
80C186EA/80C188EA, 80L186EA/80L188EA  
NOTE:  
Pin names in parentheses apply to the 80C186EA/80L188EA  
Figure 1. 80C186EA/80C188EA Block Diagram  
3
3
80C186EA/80C188EA, 80L186EA/80L188EA  
INTRODUCTION  
80C186EA CORE ARCHITECTURE  
Bus Interface Unit  
Unless specifically noted, all references to the  
80C186EA apply to the 80C188EA, 80L186EA, and  
80L188EA. References to pins that differ between  
the 80C186EA/80L186EA and the 80C188EA/  
80L188EA are given in parentheses. The ‘‘L’’ in the  
part number denotes low voltage operation. Physi-  
cally and functionally, the ‘‘C’’ and ‘‘L’’ devices are  
identical.  
The 80C186EA core incorporates a bus controller  
that generates local bus control signals. In addition,  
it employs a HOLD/HLDA protocol to share the local  
bus with other bus masters.  
The bus controller is responsible for generating 20  
bits of address, read and write strobes, bus cycle  
status information and data (for write operations) in-  
formation. It is also responsible for reading data off  
the local bus during a read operation. SRDY and  
ARDY input pins are provided to extend a bus cycle  
beyond the minimum four states (clocks).  
The 80C186EA is the second product in a new gen-  
eration of low-power, high-integration microproces-  
sors. It enhances the existing 80C186XL family by  
offering new features and operating modes. The  
80C186EA is object code compatible with the  
80C186XL embedded processor.  
The local bus controller also generates two control  
signals (DEN and DT/R) when interfacing to exter-  
nal transceiver chips. This capability allows the addi-  
tion of transceivers for simple buffering of the mulit-  
plexed address/data bus.  
The 80L186EA is the 3V version of the 80C186EA.  
The 80L186EA is functionally identical to the  
80C186EA  
embedded  
processor.  
Current  
80C186EA customers can easily upgrade their de-  
signs to use the 80L186EA and benefit from the re-  
duced power consumption inherent in 3V operation.  
The feature set of the 80C186EA/80L186EA meets  
the needs of low-power, space-critical applications.  
Low-power applications benefit from the static de-  
sign of the CPU core and the integrated peripherals  
as well as low voltage operation. Minimum current  
consumption is achieved by providing a Powerdown  
Mode that halts operation of the device, and freezes  
the clock circuits. Peripheral design enhancements  
ensure that non-initialized peripherals consume little  
current.  
Clock Generator  
The processor provides an on-chip clock generator  
for both internal and external clock generation. The  
clock generator features a crystal oscillator, a divide-  
by-two counter, and two low-power operating  
modes.  
The oscillator circuit is designed to be used with ei-  
ther a parallel resonant fundamental or third-over-  
tone mode crystal network. Alternatively, the oscilla-  
tor circuit may be driven from an external clock  
source. Figure 2 shows the various operating modes  
of the oscillator circuit.  
Space-critical applications benefit from the inte-  
gration of commonly used system peripherals. Two  
flexible DMA channels perform CPU-independent  
data transfers. A flexible chip select unit simplifies  
memory and peripheral interfacing. The interrupt unit  
provides sources for up to 128 external interrupts  
and will prioritize these interrupts with those generat-  
ed from the on-chip peripherals. Three general pur-  
pose timer/counters round out the feature set of the  
80C186EA.  
The crystal or clock frequency chosen must be twice  
the required processor operating frequency due to  
the internal divide-by-two counter. This counter is  
used to drive all internal phase clocks and the exter-  
nal CLKOUT signal. CLKOUT is a 50% duty cycle  
processor clock and can be used to drive other sys-  
tem components. All AC timings are referenced to  
CLKOUT.  
Figure 1 shows a block diagram of the 80C186EA/  
80C188EA. The Execution Unit (EU) is an enhanced  
8086 CPU core that includes: dedicated hardware to  
speed up effective address calculations, enhance  
execution speed for multiple-bit shift and rotate in-  
structions and for multiply and divide instructions,  
string move instructions that operate at full bus  
bandwidth, ten new instructions, and static opera-  
tion. The Bus Interface Unit (BIU) is the same as that  
found on the original 80C186 family products. An  
independent internal bus is used to allow communi-  
cation between the BIU and internal peripherals.  
The following parameters are recommended when  
choosing a crystal:  
Temperature Range:  
ESR (Equivalent Series Resistance):  
C0 (Shunt Capacitance of Crystal):  
Application Specific  
60X max  
7.0 pF max  
g
20 pF 2 pF  
2 mW max  
C
Drive Level:  
(Load Capacitance):  
L
4
4
80C186EA/80C188EA, 80L186EA/80L188EA  
272432–4  
272432–3  
(A) Crystal Connection  
(B) Clock Connection  
NOTE:  
The L C network is only required when using a third-overtone crystal.  
1
1
Figure 2. Clock Configurations  
80C186EA PERIPHERAL  
ARCHITECTURE  
Interrupt Control Unit  
The 80C186EA can receive interrupts from a num-  
ber of sources, both internal and external. The Inter-  
rupt Control Unit (ICU) serves to merge these re-  
quests on a priority basis, for individual service by  
the CPU. Each interrupt source can be independent-  
ly masked by the Interrupt Control Unit or all inter-  
rupts can be globally masked by the CPU.  
The 80C186EA has integrated several common sys-  
tem peripherals with a CPU core to create a com-  
pact, yet powerful system. The integrated peripher-  
als are designed to be flexible and provide logical  
interconnections between supporting units (e.g., the  
interrupt control unit supports interrupt requests  
from the timer/counters or DMA channels).  
Internal interrupt sources include the Timers and  
DMA channels. External interrupt sources come  
from the four input pins INT3:0. The NMI interrupt  
pin is not controlled by the ICU and is passed direct-  
ly to the CPU. Although the timers only have one  
request input to the ICU, separate vector types are  
generated to service individual interrupts within the  
Timer Unit.  
The list of integrated peripherals include:  
4-Input Interrupt Control Unit  
#
3-Channel Timer/Counter Unit  
#
2-Channel DMA Unit  
#
13-Output Chip-Select Unit  
#
Refresh Control Unit  
#
Power Management logic  
#
Timer/Counter Unit  
The registers associated with each integrated peri-  
heral are contained within a 128 x 16 register file  
called the Peripheral Control Block (PCB). The PCB  
can be located in either memory or I/O space on  
any 256 byte address boundary.  
The 80C186EA Timer/Counter Unit (TCU) provides  
three 16-bit programmable timers. Two of these are  
highly flexible and are connected to external pins for  
control or clocking. A third timer is not connected to  
any external pins and can only be clocked internally.  
However, it can be used to clock the other two timer  
channels. The TCU can be used to count external  
events, time external events, generate non-repeti-  
tive waveforms, generate timed interrupts, etc.  
Figure 3 provides a list of the registers associated  
with the PCB when the processor’s Interrupt Control  
Unit is in Master Mode. In Slave Mode, the defini-  
tions of some registers change. Figure 4 provides  
register definitions specific to Slave Mode.  
5
5
80C186EA/80C188EA, 80L186EA/80L188EA  
PCB  
PCB  
PCB  
PCB  
Function  
Function  
Function  
Function  
Offset  
Offset  
Offset  
Offset  
00H  
02H  
04H  
06H  
08H  
0AH  
0CH  
0EH  
10H  
12H  
14H  
16H  
18H  
1AH  
1CH  
1EH  
20H  
22H  
24H  
26H  
28H  
2AH  
2CH  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
End of Interrupt  
Poll  
40H  
42H  
44H  
46H  
48H  
4AH  
4CH  
4EH  
50H  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Timer 0 Count  
80H  
82H  
84H  
86H  
88H  
8AH  
8CH  
8EH  
90H  
92H  
94H  
96H  
98H  
9AH  
9CH  
9EH  
A0H  
A2H  
A4H  
A6H  
A8H  
AAH  
ACH  
AEH  
B0H  
B2H  
B4H  
B6H  
B8H  
BAH  
BCH  
BEH  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
UMCS  
C0H  
C2H  
C4H  
C6H  
C8H  
CAH  
CCH  
CEH  
D0H  
D2H  
D4H  
D6H  
D8H  
DAH  
DCH  
DEH  
E0H  
E2H  
E4H  
E6H  
E8H  
EAH  
ECH  
EEH  
F0H  
F2H  
F4H  
F6H  
F8H  
FAH  
FCH  
FEH  
DMA0 Src. Lo  
DMA0 Src. Hi  
DMA0 Dest. Lo  
DMA0 Dest. Hi  
DMA0 Count  
DMA0 Control  
Reserved  
Reserved  
DMA1 Src. Lo  
DMA1 Src. Hi  
DMA1 Dest. Lo  
DMA1 Dest. Hi  
DMA1 Count  
DMA1 Control  
Reserved  
52H Timer 0 Compare A  
54H Timer 0 Compare B  
56H  
58H  
Timer 0 Control  
Timer 1 Count  
5AH Timer 1 Compare A  
5CH Timer 1 Compare B  
5EH  
60H  
Timer 1 Control  
Timer 2 Count  
Reserved  
Refresh Base  
Refresh Time  
Refresh Control  
Reserved  
62H Timer 2 Compare  
LMCS  
64H  
66H  
68H  
6AH  
6CH  
6EH  
70H  
72H  
74H  
76H  
78H  
7AH  
7CH  
7EH  
Reserved  
Timer 2 Control  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
PACS  
Poll Status  
Interrupt Mask  
Priority Mask  
In-Service  
MMCS  
MPCS  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
2EH Interrupt Request  
Reserved  
30H  
32H  
Interrupt Status  
Timer Control  
Power-Save  
Power Control  
Reserved  
34H DMA0 Int. Control  
36H DMA1 Int. Control  
Step ID  
38H  
3AH  
3CH  
3EH  
INT0 Control  
INT1 Control  
INT2 Control  
INT3 Control  
Reserved  
Reserved  
Reserved  
Relocation  
Figure 3. Peripheral Control Block Registers  
6
6
80C186EA/80C188EA, 80L186EA/80L188EA  
Chip-Select Unit  
PCB  
Function  
Offset  
The 80C186EA Chip-Select Unit integrates logic  
which provides up to 13 programmable chip-selects  
to access both memories and peripherals. In addi-  
tion, each chip-select can be programmed to auto-  
matically terminate a bus cycle independent of the  
condition of the SRDY and ARDY input pins. The  
chip-select lines are available for all memory and  
I/O bus cycles, whether they are generated by the  
CPU, the DMA unit, or the Refresh Control Unit.  
20H  
22H  
24H  
26H  
28H  
2AH  
2C  
Interrupt Vector  
Specific EOI  
Reserved  
Reserved  
Interrupt Mask  
Priority Mask  
In-Service  
Refresh Control Unit  
2E  
Interrupt Request  
Interrupt Status  
TMR0 Interrupt Control  
DMA0 Interrupt Control  
DMA1 Interrupt Control  
TMR1 Interrupt Control  
TMR2 Interrupt Control  
Reserved  
The Refresh Control Unit (RCU) automatically gen-  
erates a periodic memory read bus cycle to keep  
dynamic or pseudo-static memory refreshed. A 9-bit  
counter controls the number of clocks between re-  
fresh requests.  
30  
32  
34  
36  
A 9-bit address generator is maintained by the RCU  
with the address presented on the A9:1 address  
lines during the refresh bus cycle. Address bits  
A19:13 are programmable to allow the refresh ad-  
dress block to be located on any 8 Kbyte boundary.  
38  
3A  
3C  
3E  
Reserved  
Figure 4. 80C186EA Slave Mode Peripheral  
Control Block Registers  
Power Management  
The 80C186EA has three operational modes to con-  
trol the power consumption of the device. They are  
Power Save Mode, Idle Mode, and Powerdown  
Mode.  
DMA Control Unit  
The 80C186EA DMA Contol Unit provides two inde-  
pendent high-speed DMA channels. Data transfers  
can occur between memory and I/O space in any  
combination: memory to memory, memory to I/O,  
I/O to I/O or I/O to memory. Data can be trans-  
ferred either in bytes or words. Transfers may pro-  
ceed to or from either even or odd addresses, but  
even-aligned word transfers proceed at a faster rate.  
Each data transfer consumes two bus cycles (a mini-  
mum of eight clocks), one cycle to fetch data and  
the other to store data. The chip-select/ready logic  
may be programmed to point to the memory or I/O  
space subject to DMA transfers in order to provide  
hardware chip select lines. DMA cycles run at higher  
priority than general processor execution cycles.  
Power Save Mode divides the processor clock by a  
programmable value to take advantage of the fact  
that current is linearly proportional to frequency. An  
unmasked interrupt, NMI, or reset will cause the  
80C186EA to exit Power Save Mode.  
Idle Mode freezes the clocks of the Execution Unit  
and the Bus Interface Unit at a logic zero state while  
all peripherals operate normally.  
Powerdown Mode freezes all internal clocks at a  
logic zero level and disables the crystal oscillator. All  
internal registers hold their values provided V  
is  
CC  
maintained. Current consumption is reduced to tran-  
sistor leakage only.  
7
7
80C186EA/80C188EA, 80L186EA/80L188EA  
80C187 Interface (80C186EA Only)  
The 80-lead QFP (EIAJ) pinouts are different be-  
tween the 80C186XL and the 80C186EA. In addition  
to the PDTMR pin, the 80C186EA has more power  
and ground pins and the overall arrangement of pins  
was shifted. A new circuit board layout for the  
80C186EA is required.  
The 80C187 Numerics Coprocessor may be used to  
extend the 80C186EA instruction set to include  
floating point and advanced integer instructions.  
Connecting the 80C186EA RESOUT and TEST/  
BUSY pins to the 80C187 enables Numerics Mode  
operation. In Numerics Mode, three of the four Mid-  
Range Chip Select (MCS) pins become handshaking  
pins for the interface. The exchange of data and  
control information proceeds through four dedicated  
I/O ports.  
Operating Modes  
The 80C186XL has two operating modes, Compati-  
ble and Enhanced. Compatible Mode is a pin-to-pin  
replacement for the NMOS 80186, except for nu-  
merics coprocessing. In Enhanced Mode, the proc-  
essor has a Refresh Control Unit, the Power-Save  
feature and an interface to the 80C187 Numerics  
Coprocessor. The MCS0, MCS1, and MCS3 pins  
change their functions to constitute handshaking  
pins for the 80C187.  
If an 80C187 is not present, the 80C186EA config-  
ures itself for regular operation at reset.  
NOTE:  
The 80C187 is not specified for 3V operation and  
therefore does not interface directly to the  
80L186EA.  
The 80C186EA allows all non-80C187 users to use  
all the MCS pins for chip-selects. In regular opera-  
tion, all 80C186EA features (including those of the  
Enhanced Mode 80C186) are present except for the  
interface to the 80C187. Numerics Mode disables  
the three chip-select pins and reconfigures them for  
connection to the 80C187.  
ONCE Test Mode  
To facilitate testing and inspection of devices when  
fixed into a target system, the 80C186EA has a test  
mode available which forces all output and input/  
output pins to be placed in the high-impedance  
state. ONCE stands for ‘‘ON Circuit Emulation’’. The  
ONCE mode is selected by forcing the UCS and LCS  
pins LOW (0) during a processor reset (these pins  
are weakly held to a HIGH (1) level) while RESIN is  
active.  
TTL vs CMOS Inputs  
The inputs of the 80C186EA are rated for CMOS  
switching levels for improved noise immunity, but the  
80C186XL inputs are rated for TTL switching levels.  
In particular, the 80C186EA requires a minimum V  
IH  
of 3.5V to recognize a logic one while the 80C186XL  
requires a minimum V of only 1.9V (assuming 5.0V  
IH  
operation). The solution is to drive the 80C186EA  
with true CMOS devices, such as those from the HC  
and AC logic families, or to use pullup resistors  
where the added current draw is not a problem.  
DIFFERENCES BETWEEN THE  
80C186XL AND THE 80C186EA  
The 80C186EA is intended as a direct functional up-  
grade for 80C186XL designs. In many cases, it will  
be possible to replace an existing 80C186XL with  
little or no hardware redesign. The following sections  
describe differences in pinout, operating modes, and  
AC and DC specifications to keep in mind.  
Timing Specifications  
80C186EA timing relationships are expressed in a  
simplified format over the 80C186XL. The AC per-  
formance of an 80C186EA at a specified frequency  
will be very close to that of an 80C186XL at the  
same frequency. Check the timings applicable to  
your design prior to replacing the 80C186XL.  
Pinout Compatibility  
The 80C186EA requires a PDTMR pin to time the  
processor’s exit from Powerdown Mode. The original  
pin arrangement for the 80C186XL in the PLCC  
package did not have any spare leads to use for  
PDTMR, so the DT/R pin was sacrificed. The ar-  
rangement of all the other leads in the 68-lead PLCC  
is identical between the 80C186XL and the  
80C186EA. DT/R may be synthesized by latching  
the S1 status output. Therefore, upgrading a PLCC  
80C186XL to PLCC 80C186EA is straightforward.  
8
8
80C186EA/80C188EA, 80L186EA/80L188EA  
input/output (I/O). Some pins have multiplexed  
functions (for example, A19/S6). Additional symbols  
indicate additional characteristics for each pin. Table  
3 lists all the possible symbols for this column.  
PACKAGE INFORMATION  
This section describes the pins, pinouts, and thermal  
characteristics for the 80C186EA in the Plastic  
Leaded Chip Carrier (PLCC) package, Shrink Quad  
Flat Pack (SQFP), and Quad Flat Pack (QFP) pack-  
age. For complete package specifications and infor-  
mation, see the Intel Packaging Outlines and Dimen-  
sions Guide (Order Number: 231369).  
The Input Type column indicates the type of input  
(asynchronous or synchronous).  
Asynchronous pins require that setup and hold times  
be met only in order to guarantee recognition at a  
particular clock edge. Synchronous pins require that  
setup and hold times be met to guarantee proper  
operation. For example, missing the setup or hold  
time for the SRDY pin (a synchronous input) will re-  
sult in a system failure or lockup. Input pins may also  
be edge- or level-sensitive. The possible character-  
istics for input pins are S(E), S(L), A(E) and A(L).  
With the extended temperature range operational  
characteristics are guaranteed over a temperature  
b
range corresponding to 40 C to 85 C ambient.  
Package types are identified by a two-letter prefix to  
a
§
§
the part number. The prefixes are listed in Table 1.  
Table 1. Prefix Identification  
Package  
Type  
Temperature  
Range  
The Output States column indicates the output  
state as a function of the device operating mode.  
Output states are dependent upon the current activi-  
ty of the processor. There are four operational  
states that are different from regular operation: bus  
hold, reset, Idle Mode and Powerdown Mode. Ap-  
propriate characteristics for these states are also in-  
dicated in this column, with the legend for all possi-  
ble characteristics in Table 2.  
Prefix Note  
TN  
TS  
PLCC  
Extended  
QFP (EIAJ) Extended  
SB  
N
1
1
1
SQFP  
PLCC  
Extended/Commercial  
Commercial  
S
QFP (EIAJ) Commercial  
The Pin Description column contains a text de-  
scription of each pin.  
NOTE:  
1. The 25 MHz version is only available in commercial tem-  
a
perature range corresponding to 0 C to 70 C ambient.  
§
§
As an example, consider AD15:0. I/O signifies the  
pins are bidirectional. S(L) signifies that the input  
function is synchronous and level-sensitive. H(Z)  
signifies that, as outputs, the pins are high-imped-  
ance upon acknowledgement of bus hold. R(Z) sig-  
nifies that the pins float during reset. P(X) signifies  
that the pins retain their states during Powerdown  
Mode.  
Pin Descriptions  
Each pin or logical set of pins is described in Table  
3. There are three columns for each entry in the Pin  
Description Table.  
The Pin Name column contains a mnemonic that  
describes the pin function. Negation of the signal  
name (for example, RESIN) denotes a signal that is  
active low.  
The Pin Type column contains two kinds of informa-  
tion. The first symbol indicates whether a pin is pow-  
er (P), ground (G), input only (I), output only (O) or  
9
9
80C186EA/80C188EA, 80L186EA/80L188EA  
Table 2. Pin Description Nomenclature  
Description  
Symbol  
a
Ground (Connect to V  
P
Power Pin (Apply  
V Voltage)  
CC  
)
SS  
G
I
Input Only Pin  
Output Only Pin  
Input/Output Pin  
O
I/O  
S(E)  
S(L)  
A(E)  
A(L)  
Synchronous, Edge Sensitive  
Synchronous, Level Sensitive  
Asynchronous, Edge Sensitive  
Asynchronous, Level Sensitive  
H(1)  
H(0)  
H(Z)  
H(Q)  
H(X)  
Output Driven to V during Bus Hold  
CC  
Output Driven to V during Bus Hold  
SS  
Output Floats during Bus Hold  
Output Remains Active during Bus Hold  
Output Retains Current State during Bus Hold  
R(WH)  
R(1)  
R(0)  
Output Weakly Held at V during Reset  
CC  
Output Driven to V during Reset  
CC  
Output Driven to V during Reset  
SS  
Output Floats during Reset  
R(Z)  
R(Q)  
R(X)  
Output Remains Active during Reset  
Output Retains Current State during Reset  
I(1)  
I(0)  
I(Z)  
I(Q)  
I(X)  
Output Driven to V during Idle Mode  
CC  
Output Driven to V during Idle Mode  
SS  
Output Floats during Idle Mode  
Output Remains Active during Idle Mode  
Output Retains Current State during Idle Mode  
P(1)  
P(0)  
P(Z)  
P(Q)  
P(X)  
Output Driven to V during Powerdown Mode  
CC  
Output Driven to V during Powerdown Mode  
SS  
Output Floats during Powerdown Mode  
Output Remains Active during Powerdown Mode  
Output Retains Current State during Powerdown Mode  
10  
10  
80C186EA/80C188EA, 80L186EA/80L188EA  
Table 3. Pin Descriptions  
Pin  
Name  
Pin Input Output  
Type Type States  
Description  
V
V
P
POWER connections consist of six pins which must be shorted  
externally to a V board plane.  
CC  
CC  
G
GROUND connections consist of five pins which must be shorted  
externally to a V board plane.  
SS  
SS  
CLKIN  
I
A(E)  
CLocK INput is an input for an external clock. An external  
oscillator operating at two times the required processor operating  
frequency can be connected to CLKIN. For crystal operation,  
CLKIN (along with OSCOUT) are the crystal connections to an  
internal Pierce oscillator.  
OSCOUT  
O
H(Q)  
R(Q)  
P(Q)  
OSCillator OUTput is only used when using a crystal to generate  
the external clock. OSCOUT (along with CLKIN) are the crystal  
connections to an internal Pierce oscillator. This pin is not to be  
used as 2X clock output for non-crystal applications (i.e., this pin is  
N.C. for non-crystal applications). OSCOUT does not float in  
ONCE mode.  
CLKOUT  
RESIN  
O
I
H(Q)  
R(Q)  
P(Q)  
CLocK OUTput provides a timing reference for inputs and outputs  
of the processor, and is one-half the input clock (CLKIN)  
frequency. CLKOUT has a 50% duty cycle and transistions every  
falling edge of CLKIN.  
A(L)  
RESet IN causes the processor to immediately terminate any bus  
cycle in progress and assume an initialized state. All pins will be  
driven to a known state, and RESOUT will also be driven active.  
The rising edge (low-to-high) transition synchronizes CLKOUT with  
CLKIN before the processor begins fetching opcodes at memory  
location 0FFFF0H.  
RESOUT  
PDTMR  
O
H(0)  
R(1)  
P(0)  
RESet OUTput that indicates the processor is currently in the  
reset state. RESOUT will remain active as long as RESIN remains  
active. When tied to the TEST/BUSY pin, RESOUT forces the  
80C186EA into Numerics Mode.  
I/O  
A(L)  
H(WH) Power-Down TiMeR pin (normally connected to an external  
capacitor) that determines the amount of time the processor waits  
after an exit from power down before resuming normal operation.  
The duration of time required will depend on the startup  
characteristics of the crystal oscillator.  
R(Z)  
P(1)  
NMI  
I
I
A(E)  
A(E)  
Non-Maskable Interrupt input causes a Type 2 interrupt to be  
serviced by the CPU. NMI is latched internally.  
TEST/BUSY  
(TEST)  
TEST/BUSY is sampled upon reset to determine whether the  
80C186EA is to enter Numerics Mode. In regular operation, the pin  
is TEST. TEST is used during the execution of the WAIT  
instruction to suspend CPU operation until the pin is sampled  
active (low). In Numerics Mode, the pin is BUSY. BUSY notifies the  
80C186EA of 80C187 Numerics Coprocessor activity.  
AD15:0  
(AD7:0)  
I/O  
S(L)  
H(Z)  
R(Z)  
P(X)  
These pins provide a multiplexed Address and Data bus. During  
the address phase of the bus cycle, address bits 0 through 15 (0  
through 7 on the 8-bit bus versions) are presented on the bus and  
can be latched using ALE. 8- or 16-bit data information is  
transferred during the data phase of the bus cycle.  
NOTE:  
Pin names in parentheses apply to the 80C188EA and 80L188EA.  
11  
11  
80C186EA/80C188EA, 80L186EA/80L188EA  
Table 3. Pin Descriptions (Continued)  
Input Output  
Pin  
Pin  
Description  
Name  
Type Type  
States  
A18:16  
A19/S6–A16  
(A19–A8)  
O
H(Z)  
R(Z)  
P(X)  
These pins provide multiplexed Address during the address  
phase of the bus cycle. Address bits 16 through 19 are  
presented on these pins and can be latched using ALE.  
A18:16 are driven to a logic 0 during the data phase of the bus  
cycle. On the 8-bit bus versions, A15–A8 provide valid address  
information for the entire bus cycle. Also during the data  
phase, S6 is driven to a logic 0 to indicate a CPU-initiated bus  
cycle or logic 1 to indicate a DMA-initiated bus cycle or a  
refresh cycle.  
S2:0  
O
H(Z)  
R(Z)  
P(1)  
Bus cycle Status are encoded on these pins to provide bus  
transaction information. S2:0 are encoded as follows:  
S2 S1  
S0  
Bus Cycle Initiated  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge  
Read I/O  
Write I/O  
Processor HALT  
Queue Instruction Fetch  
Read Memory  
Write Memory  
Passive (no bus activity)  
ALE/QS0  
O
O
H(0)  
R(0)  
P(0)  
Address Latch Enable output is used to strobe address  
information into a transparent type latch during the address  
phase of the bus cycle. In Queue Status Mode, QS0 provides  
queue status information along with QS1.  
BHE  
(RFSH)  
H(Z)  
R(Z)  
P(X)  
Byte High Enable output to indicate that the bus cycle in  
progress is transferring data over the upper half of the data  
bus. BHE and A0 have the following logical encoding:  
A0  
BHE Encoding (For 80C186EA/80L186EA Only)  
0
0
1
1
0
1
0
1
Word Transfer  
Even Byte Transfer  
Odd Byte Transfer  
Refresh Operation  
On the 80C188EA/80L188EA, RFSH is asserted low to  
indicate a Refresh bus cycle.  
RD/QSMD  
O
H(Z)  
R(WH)  
P(1)  
ReaD output signals that the accessed memory or I/O device  
must drive data information onto the data bus. Upon reset, this  
pin has an alternate function. As QSMD, it enables Queue  
Status Mode when grounded. In Queue Status Mode, the  
ALE/QS0 and WR/QS1 pins provide the following information  
about processor/instruction queue interaction:  
QS1  
QS0  
Queue Operation  
No Queue Operation  
0
0
1
1
0
1
1
0
First Opcode Byte Fetched from the Queue  
Subsequent Byte Fetched from the Queue  
Empty the Queue  
NOTE:  
Pin names in parentheses apply to the 80C188EA and 80L188EA.  
12  
12  
80C186EA/80C188EA, 80L186EA/80L188EA  
Table 3. Pin Descriptions (Continued)  
Pin  
Name  
Pin Input Output  
Type Type States  
Description  
WR/QS1  
O
I
H(Z)  
R(Z)  
P(1)  
WRite output signals that data available on the data bus are to be  
written into the accessed memory or I/O device. In Queue Status  
Mode, QS1 provides queue status information along with QS0.  
ARDY  
A(L)  
S(L)  
Asychronous ReaDY is an input to signal for the end of a bus cycle.  
ARDY is asynchronous on rising CLKOUT and synchronous on falling  
CLKOUT. ARDY or SRDY must be active to terminate any processor  
bus cycle, unless they are ignored due to correct programming of the  
Chip Select Unit.  
SRDY  
I
S(L)  
Synchronous ReaDY is an input to signal for the end of a bus cycle.  
ARDY or SRDY must be active to terminate any processor bus cycle,  
unless they are ignored due to correct programming of the Chip Select  
Unit.  
DEN  
O
O
O
H(Z)  
R(Z)  
P(1)  
Data ENable output to control the enable of bidirectional transceivers  
when buffering a system. DEN is active only when data is to be  
transferred on the bus.  
DT/R  
LOCK  
H(Z)  
R(Z)  
P(X)  
Data Transmit/Receive output controls the direction of a bi-  
directional buffer in a buffered system. DT/R is only available on the  
QFP (EIAJ) package and the SQFP package.  
H(Z)  
R(WH)  
P(1)  
LOCK output indicates that the bus cycle in progress is not to be  
interrupted. The processor will not service other bus requests (such  
as HOLD) while LOCK is active. This pin is configured as a weakly  
held high input while RESIN is active and must not be driven low.  
HOLD  
HLDA  
UCS  
I
A(L)  
HOLD request input to signal that an external bus master wishes to  
gain control of the local bus. The processor will relinquish control of  
the local bus between instruction boundaries not conditioned by a  
LOCK prefix.  
O
O
H(1)  
R(0)  
P(0)  
HoLD Acknowledge output to indicate that the processor has  
relinquished control of the local bus. When HLDA is asserted, the  
processor will (or has) floated its data bus and control signals allowing  
another bus master to drive the signals directly.  
H(1)  
R(1)  
P(1)  
Upper Chip Select will go active whenever the address of a memory  
or I/O bus cycle is within the address limitations programmed by the  
user. After reset, UCS is configured to be active for memory accesses  
between 0FFC00H and 0FFFFFH. During a processor reset, UCS and  
LCS are used to enable ONCE Mode.  
LCS  
O
H(1)  
R(1)  
P(1)  
Lower Chip Select will go active whenever the address of a memory  
bus cycle is within the address limitations programmed by the user.  
LCS is inactive after a reset. During a processor reset, UCS and LCS  
are used to enable ONCE Mode.  
NOTE:  
Pin names in parentheses apply to the 80C188EA and 80L188EA.  
13  
13  
80C186EA/80C188EA, 80L186EA/80L188EA  
Table 3. Pin Descriptions (Continued)  
Input Output  
Pin  
Pin  
Type Type  
Description  
Name  
States  
MCS0/PEREQ  
MCS1/ERROR  
MCS2  
I/O  
A(L)  
H(1)  
R(1)  
P(1)  
These pins provide a multiplexed function. If enabled,  
these pins normally comprise a block of Mid-Range Chip  
Select outputs which will go active whenever the address  
of a memory bus cycle is within the address limitations  
programmed by the user. In Numerics Mode (80C186EA  
only), three of the pins become handshaking pins for the  
80C187. The CoProcessor REQuest input signals that a  
data transfer is pending. ERROR is an input which  
indicates that the previous numerics coprocessor  
operation resulted in an exception condition. An interrupt  
Type 16 is generated when ERROR is sampled active at  
the beginning of a numerics operation. Numerics  
Coprocessor Select is an output signal generated when  
the processor accesses the 80C187.  
MCS3/NCS  
PCS4:0  
O
O
H(1)  
R(1)  
P(1)  
Peripheral Chip Selects go active whenever the address  
of a memory or I/O bus cycle is within the address  
limitations programmed by the user.  
PCS5/A1  
PCS6/A2  
H(1)/H(X) These pins provide a multiplexed function. As additional  
Peripheral Chip Selects, they go active whenever the  
address of a memory or I/O bus cycle is within the  
address limitations by the user. They may also be  
programmed to provide latched Address A2:1 signals.  
R(1)  
P(1)  
T0OUT  
T1OUT  
O
H(Q)  
R(1)  
P(Q)  
Timer OUTput pins can be programmed to provide a  
single clock or continuous waveform generation,  
depending on the timer mode selected.  
T0IN  
T1IN  
I
I
I
A(L)  
A(E)  
Timer INput is used either as clock or control signals,  
depending on the timer mode selected.  
DRQ0  
DRQ1  
A(L)  
DMA ReQuest is asserted by an external request when it  
is prepared for a DMA transfer.  
INT0  
INT1/SELECT  
A(E,L)  
Maskable INTerrupt input will cause a vector to a specific  
Type interrupt routine. To allow interrupt expansion, INT0  
and/or INT1 can be used with INTA0 and INTA1 to  
interface with an external slave controller. INT1 becomes  
SELECT when the ICU is configured for Slave Mode.  
INT2/INTA0  
INT3/INTA1/IRQ  
I/O  
A(E,L)  
H(1)  
R(Z)  
P(1)  
These pins provide multiplexed functions. As inputs, they  
provide a maskable INTerrupt that will cause the CPU to  
vector to a specific Type interrupt routine. As outputs,  
each is programmatically controlled to provide an  
INTerrupt Acknowledge handshake signal to allow  
interrupt expansion. INT3/INTA1 becomes IRQ when the  
ICU is configured for Slave Mode.  
N.C.  
No Connect. For compatibility with future products, do not  
connect to these pins.  
NOTE:  
Pin names in parentheses apply to the 80C188EA and 80L188EA.  
14  
14  
80C186EA/80C188EA, 80L186EA/80L188EA  
80C186EA/80C188EA (EIAJ QFP package) as  
viewed from the top side of the component (i.e., con-  
tacts facing down).  
80C186EA PINOUT  
Tables 4 and 5 list the 80C186EA pin names with  
package location for the 68-pin Plastic Leaded Chip  
Carrier (PLCC) component. Figure 9 depicts the  
complete 80C186EA/80L186EA pinout (PLCC pack-  
age) as viewed from the top side of the component  
(i.e., contacts facing down).  
Tables 8 and 9 list the 80C186EA/80C188EA pin  
names with package location for the 80-pin Shrink  
Quad Flat Pack (SQFP) component. Figure 7 depicts  
the complete 80C186EA/80C188EA (SQFP) as  
viewed from the top side of the component (i.e., con-  
tacts facing down).  
Tables 6 and 7 list the 80C186EA pin names with  
package location for the 80-pin Quad Flat Pack  
(EIAJ) component. Figure 6 depicts the complete  
Table 4. PLCC Pin Names with Package Location  
Bus Control Processor Control  
Name Location  
Address/Data Bus  
I/O  
Name  
AD0  
Location  
Name  
Location  
Name  
Location  
17  
15  
13  
11  
8
ALE/QS0  
61  
64  
RESIN  
24  
57  
UCS  
LCS  
34  
33  
38  
37  
36  
35  
AD1  
BHE (RFSH)  
RESOUT  
AD2  
MCS0/PEREQ  
MCS1/ERROR  
MCS2  
S0  
S1  
S2  
52  
53  
54  
CLKIN  
59  
58  
56  
AD3  
OSCOUT  
CLKOUT  
AD4  
AD5  
6
MCS3/NCS  
RD/QSMD  
WR/QS1  
62  
63  
TEST/BUSY  
PDTMR  
47  
40  
AD6  
4
PCS0  
25  
27  
28  
29  
30  
31  
32  
AD7  
2
PCS1  
ARDY  
SRDY  
55  
49  
NMI  
46  
45  
44  
42  
41  
AD8 (A8)  
AD9 (A9)  
AD10 (A10)  
AD11 (A11)  
AD12 (A12)  
AD13 (A13)  
AD14 (A14)  
AD15 (A15)  
16  
14  
12  
10  
7
PCS2  
INT0  
PCS3  
DEN  
39  
48  
INT1/SELECT  
INT2/INTA0  
INT3/INTA1/  
IRQ  
PCS4  
LOCK  
PCS5/A1  
PCS6/A2  
HOLD  
HLDA  
50  
51  
5
T0OUT  
T0IN  
22  
20  
23  
21  
3
1
Power  
T1OUT  
T1IN  
A16  
68  
67  
66  
65  
Name  
Location  
A17  
DRQ0  
DRQ1  
18  
19  
V
V
26, 60  
9, 43  
SS  
A18  
A19/S6  
CC  
NOTE:  
Pin names in parentheses apply to the 80C188EA/80L188EA.  
15  
15  
80C186EA/80C188EA, 80L186EA/80L188EA  
Table 5. PLCC Package Location with Pin Names  
Location  
Name  
Location  
Name  
Location  
Name  
Location  
Name  
1
2
AD15 (A15)  
AD7  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
DRQ0  
35  
36  
37  
38  
39  
40  
41  
MCS3/NCS  
MCS2  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
S0  
S1  
S2  
DRQ1  
T0IN  
3
AD14 (A14)  
AD6  
MCS1/ERROR  
MCS0/PEREQ  
DEN  
4
T1IN  
ARDY  
5
AD13 (A13)  
AD5  
T0OUT  
T1OUT  
RESIN  
PCS0  
CLKOUT  
RESOUT  
OSCOUT  
CLKIN  
6
PDTMR  
7
AD12 (A12)  
AD4  
INT3/INTA1/  
IRQ  
8
9
V
V
SS  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
INT2/INTA0  
V
SS  
CC  
10  
11  
12  
13  
14  
15  
16  
17  
AD11 (A11)  
AD3  
PCS1  
V
CC  
ALE/QS0  
RD/QSMD  
WR/QS1  
BHE (RFSH)  
A19/S6  
A18  
PCS2  
INT1/SELECT  
INT0  
AD10 (A10)  
AD2  
PCS3  
PCS4  
NMI  
AD9 (A9)  
AD1  
PCS5/A1  
PCS6/A2  
LCS  
TEST/BUSY  
LOCK  
AD8 (A8)  
AD0  
SRDY  
A17  
UCS  
HOLD  
A16  
HLDA  
NOTE:  
Pin names in parentheses apply to the 80C186EA/80L188EA.  
NOTES:  
1. The nine-character alphanumeric code (XXXXXXXXD) underneath the product number is the Intel FPO number.  
2. Pin names in parentheses apply to the 80C186EA/80L188EA.  
272432–5  
Figure 5. 68-Lead PLCC Pinout Diagram  
16  
16  
80C186EA/80C188EA, 80L186EA/80L188EA  
Table 6. QFP (EIAJ) Pin Names with Package Location  
Bus Control Processor Control  
Name Location  
RESIN  
Address/Data Bus  
I/O  
Name  
Location  
Name  
Location  
Name  
Location  
AD0  
64  
66  
68  
70  
74  
76  
78  
80  
65  
67  
69  
71  
75  
77  
79  
1
ALE/QS0  
BHE (RFSH)  
S0  
10  
7
55  
18  
16  
17  
19  
29  
38  
30  
31  
32  
35  
36  
UCS  
LCS  
45  
46  
40  
41  
42  
43  
54  
52  
51  
50  
49  
48  
47  
57  
59  
56  
58  
61  
60  
AD1  
RESOUT  
CLKIN  
AD2  
23  
22  
21  
9
MCS0/PEREQ  
MCS1/ERROR  
MCS2  
AD3  
S1  
OSCOUT  
CLKOUT  
TEST/BUSY  
PDTMR  
NMI  
AD4  
S2  
AD5  
RD/QSMD  
WR/QS1  
ARDY  
SRDY  
DT/R  
MCS3/NCS  
PCS0  
AD6  
8
AD7  
20  
27  
37  
39  
28  
26  
25  
PCS1  
AD8 (A8)  
AD9 (A9)  
AD10 (A10)  
AD11 (A11)  
AD12 (A12)  
AD13 (A13)  
AD14 (A14)  
AD15 (A15)  
A16  
INT0  
PCS2  
INT1/SELECT  
INT2/INTA0  
INT3/INTA1/  
IRQ  
PCS3  
DEN  
PCS4  
LOCK  
HOLD  
HLDA  
PCS5/A1  
PCS6/A2  
T0OUT  
T0IN  
N.C.  
11, 14,  
15, 63  
T1OUT  
T1IN  
3
Power  
A17  
4
DRQ0  
A18  
5
DRQ1  
Name  
Location  
A19/S6  
6
V
V
12, 13, 24,  
53,62  
SS  
2, 33, 34,  
44, 72, 73  
CC  
NOTE:  
Pin names in parentheses apply to the 80C186EA/80L188EA.  
17  
17  
80C186EA/80C188EA, 80L186EA/80L188EA  
Table 7. QFP (EIAJ) Package Location with Pin Names  
Location  
Name  
Location  
Name  
Location  
Name  
Location  
Name  
DRQ0  
1
2
AD15 (A15)  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
S2  
S1  
S0  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
MCS1/ERROR  
MCS2  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
V
V
SS  
CC  
3
A16  
MCS3/NCS  
N.C.  
4
A17  
V
V
AD0  
SS  
CC  
5
A18  
HLDA  
UCS  
AD8 (A8)  
AD1  
6
A19/S6  
BHE (RFSH)  
WR/QS1  
RD/QSMD  
ALE/QS0  
N.C.  
HOLD  
LCS  
7
SRDY  
PCS6/A2  
PCS5/A1  
PCS4  
AD9 (A9)  
AD2  
8
LOCK  
9
TEST/BUSY  
NMI  
AD10 (A10)  
AD3  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
PCS3  
INT0  
PCS2  
AD11 (A11)  
V
V
INT1/SELECT  
PCS1  
V
V
SS  
CC  
V
V
V
SS  
SS  
CC  
CC  
CC  
N.C.  
PCS0  
RESIN  
T1OUT  
T0OUT  
T1IN  
AD4  
N.C.  
INT2/INTA0  
INT3/INTA1/  
IRQ  
AD12 (A12)  
AD5  
CLKIN  
OSCOUT  
RESOUT  
CLKOUT  
ARDY  
AD13 (A13)  
AD6  
37  
38  
39  
40  
DT/R  
PDTMR  
T0IN  
AD14 (A14)  
AD7  
DEN  
DRQ1  
MCS0/PEREQ  
NOTE:  
Pin names in parentheses apply to the 80C186EA/80L188EA.  
NOTES:  
1. The nine-character alphanumeric code (XXXXXXXXD) underneath the product number is the Intel FPO number.  
2. Pin names in parentheses apply to the 80C186EA/80L188EA.  
272432–6  
Figure 6. Quad Flat Pack (EIAJ) Pinout Diagram  
18  
18  
80C186EA/80C188EA, 80L186EA/80L188EA  
Table 8. SQFP Pin Functions with Package Location  
Bus Control Processor Control  
ALE/QS0  
AD Bus  
I/O  
AD0  
AD1  
AD2  
AD3  
AD4  
AD5  
AD6  
AD7  
1
3
29  
26  
40  
39  
38  
28  
27  
37  
44  
56  
54  
45  
43  
42  
RESIN  
73  
UCS  
LCS  
62  
63  
BHE/(RFSH)  
S0  
RESOUT  
CLKIN  
34  
32  
33  
36  
46  
47  
48  
49  
52  
53  
55  
6
8
S1  
OSCOUT  
CLKOUT  
TEST/BUSY  
NMI  
MCS0/PEREQ  
MCS1/ERROR  
MCS2  
57  
58  
59  
60  
12  
14  
16  
18  
2
S2  
RD/QSMD  
WR/QS1  
ARDY  
SRDY  
DEN  
MCS3/NPS  
INT0  
AD8 (A8)  
AD9 (A9)  
AD10 (A10)  
AD11 (A11)  
AD12 (A12)  
AD13 (A13)  
AD14 (A14)  
AD15 (A15)  
A16/S3  
INT1/SELECT  
INT2/INTA0  
INT3/INTA1  
PDTMR  
PCS0  
PCS1  
PCS2  
PCS3  
71  
69  
68  
67  
66  
65  
64  
5
7
DT/R  
9
LOCK  
HOLD  
HLDA  
13  
15  
17  
19  
21  
22  
23  
24  
PCS4  
PCS5/A1  
PCS6/A2  
Power and Ground  
V
V
V
V
V
V
V
V
V
V
V
10  
11  
20  
50  
51  
61  
30  
31  
41  
70  
80  
CC  
CC  
CC  
CC  
CC  
CC  
SS  
SS  
SS  
SS  
SS  
No Connection  
TMR IN 0  
TMR IN 1  
TMR OUT 0  
TMR OUT 1  
77  
76  
75  
74  
N.C.  
4
A17/S4  
N.C.  
N.C.  
N.C.  
25  
35  
72  
A18/S5  
A19/S6  
DRQ0  
DRQ1  
79  
78  
NOTE:  
Pin names in parentheses apply to the 80C186EA/80L188EA.  
Table 9. SQFP Pin Locations with Pin Names  
1
2
AD0  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
A16/S3  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
V
HLDA  
HOLD  
SRDY  
LOCK  
TEST/BUSY  
NMI  
INT0  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
V
CC  
UCS  
LCS  
PCS6/A2  
PCS5/A1  
PCS4  
PCS3  
PCS2  
PCS1  
V
SS  
PCS0  
N.C.  
RES  
TMR OUT 1  
TMR OUT 0  
TMR IN 1  
TMR IN 0  
DRQ1  
SS  
AD8 (A8)  
AD1  
A17/S4  
3
A18/S5  
4
N.C.  
A19/S6  
5
AD9 (A9)  
AD2  
N.C.  
6
BHE/(RFSH)  
WR/QS1  
RD/QSMD  
ALE/QS0  
7
AD10 (A10)  
AD3  
8
9
AD11 (A11)  
INT1/SELECT  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
V
V
V
V
V
V
CC  
CC  
SS  
CC  
CC  
SS  
AD4  
X1  
INT2/INTA0  
INT3/INTA1  
DT/R  
PDTMR  
DEN  
MCS0/PEREQ  
MCS1/ERROR  
MCS2  
AD12 (A12)  
AD5  
X2  
RESET  
N.C.  
CLKOUT  
ARDY  
S2  
AD13 (A13)  
AD6  
AD14 (A14)  
AD7  
AD15 (A15)  
S1  
DRQ0  
V
SS  
V
S0  
MCS3/NPS  
CC  
NOTE:  
Pin names in parentheses apply to the 80C186EA/80L188EA.  
19  
19  
80C186EA/80C188EA, 80L186EA/80L188EA  
272432–7  
Figure 7. Shrink Quad Flat Pack (SQFP) Pinout Diagram  
NOTES:  
1. XXXXXXXXD indicates the Intel FPO number.  
2. Pin names in parentheses apply to the 80C188EA.  
T
(the ambient temperature) can be calculated  
A
PACKAGE THERMAL  
SPECIFICATIONS  
from i (thermal resistance from the case to ambi-  
CA  
ent) with the following equation:  
The 80C186EA/80L186EA is specified for operation  
when T (the case temperature) is within the range  
C
e
c
T
A
T
C
- P  
i
CA  
of 0 C to 85 C (PLCC package) or 0 C to 106 C  
§
§
§
§
Typical values for i  
in Table 10.  
at various airflows are given  
CA  
(QFP-EIAJ) package. T may be measured in any  
C
environment to determine whether the processor is  
within the specified operating range. The case tem-  
perature must be measured at the center of the top  
surface.  
P (the maximum power consumption, specified in  
watts) is calculated by using the maximum ICC as  
tabulated in the DC specifications and V  
of 5.5V.  
CC  
Table 10. Thermal Resistance (i ) at Various Airflows (in C/Watt)  
§
CA  
Airflow Linear ft/min (m/sec)  
0
200  
400  
600  
800 1000  
(0) (1.01) (2.03) (3.04) (4.06) (5.07)  
i
i
i
(PLCC)  
(QFP)  
29 25  
66 63  
70  
21  
19  
59  
17  
58  
16.5  
57  
CA  
CA  
CA  
60.5  
(SQFP)  
20  
20  
80C186EA/80C188EA, 80L186EA/80L188EA  
ELECTRICAL SPECIFICATIONS  
NOTICE: This data sheet contains preliminary infor-  
mation on new products in production. It is valid for  
the devices indicated in the revision history. The  
specifications are subject to change without notice.  
Absolute Maximum Ratings*  
b
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C  
a
*WARNING: Stressing the device beyond the ‘‘Absolute  
Maximum Ratings’’ may cause permanent damage.  
These are stress ratings only. Operation beyond the  
‘‘Operating Conditions’’ is not recommended and ex-  
tended exposure beyond the ‘‘Operating Conditions’’  
may affect device reliability.  
§
§
b
a
Case Temperature under Bias ÀÀÀ 65 C to 150 C  
§
§
Supply Voltage with Respect  
b
a
to V ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 0.5V to 6.5V  
SS  
Voltage on Other Pins with Respect  
to V  
b
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 0.5V to V  
a
0.5V  
SS  
CC  
itors is application and board layout dependent. The  
processor can cause transient power surges when  
its output buffers transition, particularly when con-  
nected to large capacitive loads.  
Recommended Connections  
Power and ground connections must be made to  
multiple V and V pins. Every 80C186EA based  
CC SS  
circuit board should contain separate power (V  
)
CC  
and ground (V ) planes. All V and V pins must  
Always connect any unused input pins to an appro-  
priate signal level. In particular, unused interrupt pins  
(NMI, INT3:0) should be connected to V to avoid  
SS  
CC  
SS  
be connected to the appropriate plane. Pins identi-  
fied as ‘‘N.C.’’ must not be connected in the system.  
Decoupling capacitors should be placed near the  
processor. The value and type of decoupling capac-  
SS  
unwanted interrupts. Leave any unused output pin  
or any ‘‘N.C.’’ pin unconnected.  
21  
21  
80C186EA/80C188EA, 80L186EA/80L188EA  
DC SPECIFICATIONS (80C186EA/80C188EA)  
Symbol  
Parameter  
Supply Voltage  
Min  
Max  
Units  
V
Conditions  
V
V
V
V
V
V
4.5  
5.5  
CC  
IL  
b
Input Low Voltage for All Pins  
Input High Voltage for All Pins  
Output Low Voltage  
0.5  
0.3 V  
V
CC  
a
0.7 V  
V
CC  
0.5  
V
IH  
CC  
e
0.45  
V
I
I
3 mA (min)  
OL  
OH  
HYR  
OL  
b
e b  
2 mA (min)  
Output High Voltage  
V
0.5  
V
CC  
OH  
Input Hysterisis on RESIN  
0.30  
V
s
s
g
g
I
Input Leakage Current (except  
RD/QSMD, UCS, LCS, MCS0/PEREQ,  
MCS1/ERROR, LOCK and TEST/BUSY)  
10  
mA  
0V  
V
V
CC  
IL1  
IN  
b
e
(Note 1)  
I
Input Leakage Current  
(RD/QSMD, UCS, LCS, MCS0/PEREQ,  
MCS1, ERROR, LOCK and TEST/BUSY  
275  
mA  
V
0.7 V  
CC  
IL2  
IN  
s
s
I
I
Output Leakage Current  
0.45  
(Note 2)  
V
V
CC  
OL  
CC  
OUT  
10  
mA  
Supply Current Cold (RESET)  
80C186EA25/80C188EA25  
80C186EA20/80C188EA20  
80C186EA13/80C188EA13  
105  
90  
mA (Notes 3, 5)  
mA  
mA  
65  
I
I
Supply Current In Idle Mode  
80C186EA25/80C188EA25  
80C186EA20/80C188EA20  
80C186EA13/80C188EA13  
ID  
90  
70  
46  
mA (Note 5)  
mA  
mA  
Supply Current In Powerdown Mode  
80C186EA25/80C188EA25  
80C186EA20/80C188EA20  
80C186EA13/80C188EA13  
PD  
100  
100  
100  
mA  
mA  
mA  
(Note 5)  
e
e
C
C
Output Pin Capacitance  
Input Pin Capacitance  
0
0
15  
15  
pF  
pF  
T
T
1 MHz (Note 4)  
1 MHz  
OUT  
F
F
IN  
NOTES:  
1. RD/QSMD, UCS, LCS, MCS0/PEREQ, MCS1/ERROR, LOCK and TEST/BUSY have internal pullups that are only acti-  
e
b
vated during RESET. Loading these pins above I  
operation.  
275 mA will cause the processor to enter alternate modes of  
OL  
2. Output pins are floated using HOLD or ONCE Mode.  
3. Measured at worst case temperature and V with all outputs loaded as specified in the AC Test Conditions, and with the  
CC  
device in RESET (RESIN held low). RESET is worst case for I  
.
CC  
4. Output capacitance is the capacitive load of a floating output pin.  
a
5. Operating conditions for 25 MHz are 0 C to 70 C, V  
e
g
5.0V 10%.  
§
§
CC  
22  
22  
80C186EA/80C188EA, 80L186EA/80L188EA  
DC SPECIFICATIONS (80L186EA/80L188EA)  
Symbol  
Parameter  
Supply Voltage  
Min  
Max  
Units  
V
Conditions  
V
V
V
V
V
V
2.7  
5.5  
CC  
b
Input Low Voltage for All Pins  
Input High Voltage for All Pins  
Output Low Voltage  
0.5  
0.3 V  
V
IL  
CC  
a
0.7 V  
V
CC  
0.5  
V
IH  
CC  
e
0.45  
V
I
I
1.6 mA (min)  
OL  
OH  
HYR  
OL  
b
e b  
1 mA (min)  
Output High Voltage  
V
0.5  
V
CC  
OH  
Input Hysterisis on RESIN  
0.30  
V
s
s
g
g
I
Input Leakage Current (except  
RD/QSMD, UCS, LCS, MCS0/PEREQ,  
MCS1, LOCK and TEST)  
10  
mA  
0V  
V
V
CC  
IL1  
IN  
b
e
(Note 1)  
I
Input Leakage Current  
(RD/QSMD, UCS, LCS, MCS0,  
MCS1, LOCK and TEST)  
275  
mA  
V
0.7 V  
CC  
IL2  
IN  
s
s
I
I
Output Leakage Current  
0.45  
(Note 2)  
V
V
CC  
OL  
OUT  
10  
mA  
Supply Current (RESET, 5.5V)  
80L186EA-13  
80L186EA-8  
CC5  
65  
40  
mA  
mA  
(Note 3)  
(Note 3)  
I
I
I
I
I
Supply Current (RESET, 2.7V)  
80L186EA-13  
80L186EA-8  
CC3  
ID5  
34  
20  
mA  
mA  
(Note 3)  
(Note 3)  
Supply Current Idle (5.5V)  
80L186EA-13  
80L186EA-8  
46  
28  
mA  
mA  
Supply Current Idle (2.7V)  
80L186EA-13  
80L186EA-8  
ID5  
24  
14  
mA  
mA  
Supply Current Powerdown (5.5V)  
80L186EA-13  
80L186EA-8  
PD5  
PD3  
100  
100  
mA  
mA  
Supply Current Powerdown (2.7V)  
80L186EA-13  
80L186EA-8  
50  
50  
mA  
mA  
e
e
C
C
Output Pin Capacitance  
Input Pin Capacitance  
0
0
15  
15  
pF  
pF  
T
T
1 MHz (Note 4)  
1 MHz  
OUT  
F
F
IN  
NOTES:  
1. RD/QSMD, UCS, LCS, MCS0, MCS1, LOCK and TEST have internal pullups that are only activated during RESET.  
e b  
Loading these pins above I  
275 mA will cause the processor to enter alternate modes of operation.  
OL  
2. Output pins are floated using HOLD or ONCE Mode.  
3. Measured at worst case temperature and V with all outputs loaded as specified in the AC Test Conditions, and with the  
CC  
device in RESET (RESIN held low).  
4. Output capacitance is the capacitive load of a floating output pin.  
23  
23  
80C186EA/80C188EA, 80L186EA/80L188EA  
I
CC  
VERSUS FREQUENCY AND VOLTAGE  
PDTMR PIN DELAY CALCULATION  
The current (I ) consumption of the processor is  
and  
The PDTMR pin provides a delay between the as-  
sertion of NMI and the enabling of the internal  
clocks when exiting Powerdown. A delay is required  
only when using the on-chip oscillator to allow the  
crystal or resonator circuit time to stabilize.  
CC  
essentially composed of two components; I  
PD  
I
.
CCS  
I
is the quiescent current that represents internal  
PD  
device leakage, and is measured with all inputs or  
floating outputs at GND or V (no clock applied to  
the device). I  
NOTE:  
CC  
is equal to the Powerdown current  
The PDTMR pin function does not apply when  
RESIN is asserted (i.e., a device reset during Pow-  
erdown is similar to a cold reset and RESIN must  
remain active until after the oscillator has stabi-  
lized).  
PD  
and is typically less than 50 mA.  
I
is the switching current used to charge and  
CCS  
discharge parasitic device capacitance when chang-  
ing logic levels. Since I is typically much greater  
than I , I can often be ignored when calculating  
CCS  
To calculate the value of capacitor required to pro-  
vide a desired delay, use the equation:  
PD PD  
I
.
CC  
c
e
440  
t
C
(5V, 25 C)  
§
desired delay in seconds  
PD  
I is related to the voltage and frequency at which  
CCS  
the device is operating. It is given by the formula:  
e
Where: t  
e
C
PD  
capacitive load on PDTMR in mi-  
crofarads  
2
e
c
e
c
c
Power  
.
V
I
V
C
f
DEV  
C
e
e
e
c
c
. . I  
I
I
V
f
CC  
CCS  
DEV  
e
Where: V  
Device operating voltage (V  
)
CC  
EXAMPLE: To get a delay of 30b0 ms, a capacitor  
value of C 440 (300 10 0.132 mF is  
PD  
required. Round up to standard (available) capaci-  
tive values.  
6
e
c
c
e
)
e
C
f
Device capacitance  
Device operating frequency  
DEV  
e
e
e
I
I
Device current  
CCS  
CC  
NOTE:  
Measuring C  
on a device like the 80C186EA  
The above equation applies to delay times greater  
than 10 ms and will compute the TYPICAL capaci-  
tance needed to achieve the desired delay. A delay  
DEV  
would be difficult. Instead, C  
is calculated using  
the above formula by measuring I at a known V  
DEV  
CC  
and frequency (see Table 11). Using this C  
CC  
val-  
a
b
variance of  
temperature, voltage, and device process ex-  
tremes. In general, higher V and/or lower tem-  
50% or  
25% can occur due to  
DEV  
ue, I can be calculated at any voltage and fre-  
CC  
quency within the specified operating range.  
CC  
perature will decrease delay time, while lower V  
CC  
and/or higher temperature will increase delay time.  
EXAMPLE: Calculate the typical I when operating  
CC  
at 20 MHz, 4.8V.  
e
e
c
c
4.8 0.515 20  
&
I
I
49 mA  
Table 11. C  
CC  
CCS  
Values  
DEV  
Parameter  
Typ  
Max  
Units  
Notes  
C
(Device in Reset)  
(Device in Idle)  
0.515  
0.391  
0.905  
0.635  
mA/V*MHz  
mA/V*MHz  
1, 2  
DEV  
C
DEV  
1, 2  
b
1. Max C  
is calculated at 40 C, all floating outputs driven to V  
or GND, and all  
§
DEV  
outputs loaded to 50 pF (including CLKOUT and OSCOUT).  
2. Typical C is calculated at 25 C with all outputs loaded to 50 pF except CLKOUT and  
CC  
§
DEV  
OSCOUT, which are not loaded.  
24  
24  
80C186EA/80C188EA, 80L186EA/80L188EA  
AC SPECIFICATIONS  
AC CharacteristicsÐ80C186EA25/80C186EA20/80C186EA13  
Symbol  
Parameter  
Min  
Max  
Min  
Max  
Min  
Max Units Notes  
(12)  
INPUT CLOCK  
25 MHz  
20 MHz  
13 MHz  
T
T
T
T
T
T
CLKIN Frequency  
CLKIN Period  
CLKIN High Time  
CLKIN Low Time  
CLKIN Rise Time  
CLKIN Fall Time  
0
20  
10  
10  
1
50  
%
%
%
8
8
0
25  
10  
10  
1
40  
%
%
%
8
8
0
38.5  
12  
12  
1
26 MHz  
%
1
1
1, 2  
1, 2  
1, 3  
1, 3  
F
ns  
ns  
C
%
CH  
CL  
CR  
CF  
%
ns  
8
8
ns  
ns  
1
1
1
OUTPUT CLOCK  
T
T
T
T
T
T
CLKIN to CLKOUT Delay  
CLKOUT Period  
CLKOUT High Time  
CLKOUT Low Time  
CLKOUT Rise Time  
CLKOUT Fall Time  
0
15  
2T  
0
17  
2*T  
0
23  
2*T  
C
ns  
ns  
ns  
ns  
ns  
ns  
1, 4  
1
1
1
1, 5  
1, 5  
CD  
C
C
b
b
b
b
b
b
(T/2)  
(T/2)  
5
5
(T/2)  
(T/2)  
5
5
(T/2)  
(T/2)  
5
5
PH  
PL  
PR  
PF  
1
1
6
6
1
1
6
6
1
1
6
6
OUTPUT DELAYS  
T
T
T
ALE, S2:0, DEN, DT/R,  
BHE, (RFSH), LOCK, A19:16  
3
3
3
20  
25  
20  
3
3
3
22  
27  
22  
3
3
3
25  
30  
25  
ns 1, 4, 6, 7  
ns 1, 4, 6, 8  
CHOV1  
CHOV2  
CLOV1  
MCS3:0, LCS, UCS, PCS6:0,  
NCS, RD, WR  
BHE (RFSH), DEN, LOCK,  
RESOUT, HLDA,  
T0OUT, T1OUT, A19:16  
ns  
ns  
1, 4, 6  
1, 4, 6  
T
RD, WR, MCS3:0, LCS,  
UCS, PCS6:0, AD15:0  
(A15:8, AD7:0),  
3
25  
3
27  
3
30  
CLOV2  
NCS, INTA1:0, S2:0  
T
T
RD, WR, BHE (RFSH), DT/R,  
LOCK, S2:0, A19:16  
0
0
25  
25  
0
0
25  
25  
0
0
25  
25  
ns  
ns  
1
1
CHOF  
CLOF  
DEN, AD15:0 (A15:8, AD7:0)  
25  
25  
80C186EA/80C188EA, 80L186EA/80L188EA  
AC SPECIFICATIONS (Continued)  
AC CharacteristicsÐ80C186EA25/80C186EA20/80C186EA13  
Symbol  
Parameter  
Min  
Max  
(12)  
Min  
Max  
Min  
Max  
Units  
Notes  
SYNCHRONOUS INPUTS  
25 MHz  
20 MHz  
13 MHz  
T
T
T
T
T
T
TEST, NMI, INT3:0,  
T1:0IN, ARDY  
8
10  
10  
3
ns  
ns  
ns  
ns  
ns  
ns  
1, 9  
1, 9  
CHIS  
CHIH  
CLIS  
CLIH  
CLIS  
CLIH  
TEST, NMI, INT3:0,  
T1:0IN, ARDY  
3
10  
3
3
AD15:0 (AD7:0), ARDY,  
SRDY, DRQ1:0  
10  
3
10  
3
1, 10  
1, 10  
1, 9  
AD15:0 (AD7:0), ARDY,  
SRDY, DRQ1:0  
HOLD, PEREQ, ERROR  
(80C186EA Only)  
10  
3
10  
3
10  
3
HOLD, PEREQ, ERROR  
(80C186EA Only)  
1, 9  
T
T
RESIN (to CLKIN)  
10  
3
10  
3
10  
3
ns  
ns  
1, 9  
1, 9  
CLIS  
CLIH  
RESIN (from CLKIN)  
NOTES:  
1. See AC Timing Waveforms, for waveforms and definition.  
2. Measured at V for high time, V for low time.  
IH IL  
3. Only required to guarantee I . Maximum limits are bounded by T , T  
CC  
and T  
.
CL  
C
CH  
4. Specified for a 50 pF load, see Figure 13 for capacitive derating information.  
5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.  
6. See Figure 14 for rise and fall times.  
7. T  
8. T  
applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.  
applies to RD and WR only after a HOLD release.  
CHOV1  
CHOV2  
9. Setup and Hold are required to guarantee recognition.  
10. Setup and Hold are required for proper operation.  
11. T  
applies to BHE (RFSH) and A19:16 only after a HOLD release.  
a
CHOVS  
12. Operating conditions for 25 MHz are 0 C to 70 C, V  
e
g
5.0V 10%.  
§
§
CC  
Pin names in parentheses apply to the 80C188EA/80L188EA.  
26  
26  
80C186EA/80C188EA, 80L186EA/80L188EA  
AC SPECIFICATIONS  
AC CharacteristicsÐ80L186EA13/80L186EA8  
Symbol  
Parameter  
Min  
13 MHz  
Max  
Min  
8 MHz  
Max  
Units  
Notes  
INPUT CLOCK  
T
T
T
T
T
T
CLKIN Frequency  
CLKIN Period  
CLKIN High Time  
CLKIN Low Time  
CLKIN Rise Time  
CLKIN Fall Time  
0
38.5  
12  
12  
1
26  
%
%
%
8
8
0
62.5  
12  
12  
1
16  
%
%
%
8
8
MHz  
ns  
ns  
ns  
ns  
ns  
1
1
1, 2  
1, 2  
1, 3  
1, 3  
F
C
CH  
CL  
CR  
CF  
1
1
OUTPUT CLOCK  
T
T
T
T
T
T
CLKIN to CLKOUT Delay  
CLKOUT Period  
CLKOUT High Time  
CLKOUT Low Time  
CLKOUT Rise Time  
CLKOUT Fall Time  
0
45  
2*T  
0
95  
2*T  
ns  
ns  
ns  
ns  
ns  
ns  
1, 4  
1
1
1
1, 5  
1, 5  
CD  
C
C
b
b
b
b
(T/2)  
(T/2)  
5
5
(T/2)  
(T/2)  
5
5
PH  
PL  
PR  
PF  
1
1
12  
12  
1
1
12  
12  
OUTPUT DELAYS  
T
T
ALE, LOCK  
3
3
27  
32  
3
3
27  
32  
ns  
ns  
1, 4, 6, 7  
CHOV1  
CHOV2  
MCS3:0, LCS, UCS,  
PCS6:0, RD, WR  
1, 4,  
6, 8  
T
T
T
S2:0 (DEN), DT/R,  
BHE (RFSH), A19:16  
3
3
3
30  
27  
32  
3
3
3
30  
27  
35  
ns  
ns  
ns  
1
CHOV3  
CLOV1  
CLOV2  
LOCK, RESOUT, HLDA,  
T0OUT, T1OUT  
1, 4, 6  
1, 4, 6  
RD, WR, MCS3:0, LCS,  
UCS, PCS6:0, INTA1:0  
T
T
T
T
BHE (RFSH), DEN, A19:16  
AD15:0 (A15:8, AD7:0)  
S2:0  
3
3
3
0
30  
34  
38  
27  
3
3
3
0
30  
35  
40  
27  
ns  
ns  
ns  
ns  
1, 4, 6  
1, 4, 6  
1, 4, 6  
1
CLOV3  
CLOV4  
CLOV5  
CHOF  
RD, WR, BHE (RFSH),  
DT/R, LOCK,  
S2:0, A19:16  
T
DEN, AD15:0  
(A15:8, AD7:0)  
CLOF  
0
27  
0
27  
ns  
1
NOTES:  
1. See AC Timing Waveforms, for waveforms and definition.  
2. Measured at V for high time, V for low time.  
IH IL  
3. Only required to guarantee I . Maximum limits are bounded by T , T  
CC  
and T  
.
CL  
C
CH  
4. Specified for a 50 pF load, see Figure 13 for capacitive derating information.  
5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.  
6. See Figure 14 for rise and fall times.  
7. T  
8. T  
applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.  
applies to RD and WR only after a HOLD release.  
CHOV1  
CHOV2  
9. Setup and Hold are required to guarantee recognition.  
10. Setup and Hold are required for proper operation.  
11. T  
applies to BHE (RFSH) and A19:16 only after a HOLD release.  
CHOVS  
12. Pin names in parentheses apply to the 80C188EA/80L188EA.  
27  
27  
80C186EA/80C188EA, 80L186EA/80L188EA  
AC SPECIFICATIONS  
AC CharacteristicsÐ80L186EA13/80L186EA8  
Symbol  
Parameter  
Min  
Max  
Min  
Max  
Units  
Notes  
SYNCHRONOUS INPUTS  
13 MHz  
8 MHz  
T
T
T
T
T
T
T
T
TEST, NMI, INT3:0, T1:0IN, ARDY  
TEST, NMI, INT3:0, T1:0IN, ARDY  
AD15:0 (AD7:0), ARDY, SRDY, DRQ1:0  
AD15:0 (AD7:0), ARDY, SRDY, DRQ1:0  
HOLD  
22  
3
22  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1, 9  
1, 9  
CHIS  
CHIH  
CLIS  
CLIH  
CLIS  
CLIH  
CLIS  
CLIH  
22  
3
22  
3
1, 10  
1, 10  
1, 9  
22  
3
22  
3
HOLD  
1, 9  
RESIN (to CLKIN)  
22  
3
22  
3
1, 9  
RESIN (from CLKIN)  
1, 9  
NOTES:  
1. See AC Timing Waveforms, for waveforms and definition.  
2. Measured at V for high time, V for low time.  
IH IL  
3. Only required to guarantee I . Maximum limits are bounded by T , T  
CC  
and T  
.
CL  
C
CH  
4. Specified for a 50 pF load, see Figure 13 for capacitive derating information.  
5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF.  
6. See Figure 14 for rise and fall times.  
7. T  
8. T  
applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.  
applies to RD and WR only after a HOLD release.  
CHOV1  
CHOV2  
9. Setup and Hold are required to guarantee recognition.  
10. Setup and Hold are required for proper operation.  
11. T  
applies to BHE (RFSH) and A19:16 only after a HOLD release.  
CHOVS  
12. Pin names in parentheses apply to the 80C188EA/80L188EA.  
28  
28  
80C186EA/80C188EA, 80L186EA/80L188EA  
AC SPECIFICATIONS (Continued)  
Relative Timings (80C186EA25/20/13, 80L186EA13/8)  
Symbol  
Parameter  
Min  
Max  
Unit  
Notes  
RELATIVE TIMINGS  
b
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
ALE Rising to ALE Falling  
T
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
LHLL  
b
Address Valid to ALE Falling  
Chip Selects Valid to ALE Falling  
Address Hold from ALE Falling  
ALE Falling to WR Falling  
(/2T  
(/2T  
(/2T  
(/2T  
(/2T  
(/2T  
(/2T  
10  
10  
10  
15  
15  
10  
10  
AVLL  
b
b
b
b
b
b
0
1
PLLL  
LLAX  
1
1
1
1
LLWL  
LLRL  
ALE Falling to RD Falling  
RD Rising to ALE Rising  
RHLH  
WHLH  
AFRL  
RLRH  
WLWH  
RHAV  
WHDX  
WHDEX  
WHPH  
RHPH  
PHPL  
DXDL  
OVRH  
RHOX  
WR Rising to ALE Rising  
Address Float to RD Falling  
RD Falling to RD Rising  
b
(2*T)  
5
5
2
2
b
WR Falling to WR Rising  
(2*T)  
b
b
RD Rising to Address Active  
Output Data Hold after WR Rising  
WR Rising to DEN Rising  
T
T
15  
15  
b
b
b
b
0
(/2T  
(/2T  
(/2T  
(/2T  
10  
10  
10  
10  
1
1, 4  
1, 4  
1
WR Rising to Chip Select Rising  
RD Rising to Chip Select Rising  
CS Inactive to CS Active  
DEN Inactive to DT/R Low  
ONCE (UCS, LCS) Active to RESIN Rising  
ONCE (UCS, LCS) to RESIN Rising  
5
T
3
T
3
NOTES:  
1. Assumes equal loading on both pins.  
2. Can be extended using wait states.  
3. Not tested.  
4. Not applicable to latched A2:1. These signals change only on falling T .  
1
5. For write cycle followed by read cycle.  
6. Operating conditions for 25 MHz are 0 C to 70 C, V  
a
e
g
5.0V 10%.  
§
§
CC  
29  
29  
80C186EA/80C188EA, 80L186EA/80L188EA  
AC TEST CONDITIONS  
The AC specifications are tested with the 50 pF load  
shown in Figure 8. See the Derating Curves section  
to see how timings vary with load capacitance.  
272432–8  
e
C
L
50 pF for all signals.  
Figure 8. AC Test Load  
Specifications are measured at the V /2 crossing  
CC  
point, unless otherwise specified. See AC Timing  
Waveforms, for AC specification definitions, test  
pins, and illustrations.  
AC TIMING WAVEFORMS  
272432–9  
Figure 9. Input and Output Clock Waveform  
30  
30  
80C186EA/80C188EA, 80L186EA/80L188EA  
272432–10  
NOTE:  
20% V  
k
k
Float  
80% V  
CC  
CC  
Figure 10. Output Delay and Float Waveform  
272432–11  
NOTE:  
RESIN measured to CLKIN, not CLKOUT  
Figure 11. Input Setup and Hold  
31  
31  
80C186EA/80C188EA, 80L186EA/80L188EA  
272432–12  
NOTES:  
1. T  
for write cycle followed by read cycle.  
DXDL  
2. Pin names in parentheses apply to tthe 80C188EA.  
Figure 12. Relative Signal Waveform  
32  
32  
80C186EA/80C188EA, 80L186EA/80L188EA  
DERATING CURVES  
272432–14  
272432–13  
Figure 14. Typical Rise and Fall Variations  
Versus Load Capacitance  
Figure 13. Typical Output Delay Variations  
Versus Load Capacitance  
must ensure that the ramp time for V is not so  
long that RESIN is never really sampled at a logic  
CC  
RESET  
low level when V  
conditions.  
reaches minimum operating  
The processor performs a reset operation any time  
the RESIN pin is active. The RESIN pin is actually  
synchronized before it is presented internally, which  
means that the clock must be operating before a  
reset can take effect. From a power-on state, RESIN  
must be held active (low) in order to guarantee cor-  
rect initialization of the processor. Failure to pro-  
vide RESIN while the device is powering up will  
result in unspecified operation of the device.  
CC  
Figure 16 shows the timing sequence when RESIN  
is applied after V is stable and the device has  
CC  
been operating. Note that a reset will terminate all  
activity and return the processor to a known operat-  
ing state. Any bus operation that is in progress at the  
time RESIN is asserted will terminate immediately  
(note that most control signals will be driven to their  
inactive state first before floating).  
Figure 15 shows the correct reset sequence when  
first applying power to the processor. An external  
clock connected to CLKIN must not exceed the V  
While RESIN is active, signals RD/QSMD, UCS,  
LCS, MCS0/PEREQ, MCS1/ERROR, LOCK, and  
TEST/BUSY are configured as inputs and weakly  
held high by internal pullup transistors. Forcing UCS  
and LCS low selects ONCE Mode. Forcing QSMD  
low selects Queue Status Mode. Forcing TEST/  
BUSY high at reset and low four clocks later enables  
Numerics Mode. Forcing LOCK low is prohibited and  
results in unspecified operation.  
CC  
threshold being applied to the processor. This is nor-  
mally not a problem if the clock driver is supplied  
with the same V  
that supplies the processor.  
When attaching a crystal to the device, RESIN must  
CC  
remain active until both V and CLKOUT are stable  
CC  
(the length of time is application specific and de-  
pends on the startup characteristics of the crystal  
circuit). The RESIN pin is designed to operate cor-  
rectly using an RC reset circuit, but the designer  
33  
33  
80C186EA/80C188EA, 80L186EA/80L188EA  
Figure 15. Powerup Reset Waveforms  
34  
34  
80C186EA/80C188EA, 80L186EA/80L188EA  
Figure 16. Warm Reset Waveforms  
35  
35  
80C186EA/80C188EA, 80L186EA/80L188EA  
BUS CYCLE WAVEFORMS  
Figures 17 through 23 present the various bus cycles that are generated by the processor. What is shown in  
the figure is the relationship of the various bus signals to CLKOUT. These figures along with the information  
present in AC Specifications allow the user to determine all the critical timing analysis needed for a given  
application.  
272432-17  
NOTES:  
1. During the data phase of the bus cycle, A19/S6 is driven high for a DMA or refresh cycle.  
2. Pin names in parentheses apply to the 80C188EA.  
Figure 17. Read, Fetch and Refresh Cycle Waveform  
36  
36  
80C186EA/80C188EA, 80L186EA/80L188EA  
272432-18  
NOTES:  
1. During the data phase of the bus cycle, A19/S6 is driven high for a DMA cycle.  
2. Pin names in parentheses apply to the 80C188EA.  
Figure 18. Write Cycle Waveform  
37  
37  
80C186EA/80C188EA, 80L186EA/80L188EA  
272432–19  
NOTES:  
1. The processor drives these pins to 0 during Idle and Powerdown Modes.  
2. Pin names in parentheses apply to the 80C188EA.  
Figure 19. Halt Cycle Waveform  
38  
38  
80C186EA/80C188EA, 80L186EA/80L188EA  
NOTES:  
1. INTA occurs one clock later in Slave Mode.  
2. Pin names in parentheses apply to the 80C188EA.  
272432–20  
Figure 20. INTA Cycle Waveform  
39  
39  
80C186EA/80C188EA, 80L186EA/80L188EA  
272432–21  
NOTE:  
1. Pin names in parentheses apply to the 80C188EA.  
Figure 21. HOLD/HLDA Waveform  
40  
40  
80C186EA/80C188EA, 80L186EA/80L188EA  
272432–22  
NOTE:  
1. Pin names in parentheses apply to the 80C188EA.  
Figure 22. DRAM Refresh Cycle During Hold Acknowledge  
41  
41  
80C186EA/80C188EA, 80L186EA/80L188EA  
272432–23  
NOTES:  
1. Generalized diagram for READ or WRITE.  
2. ARDY low by either edge causes a wait state. Only rising ARDY is fully synchronized.  
3. SRDY low causes a wait state. SRDY must meet setup and hold times to ensure correct device operation.  
4. Either ARDY or SRDY active high will terminate a bus cycle.  
5. Pin names in parentheses apply to the 80C188EA.  
Figure 23. Ready Waveform  
42  
42  
80C186EA/80C188EA, 80L186EA/80L188EA  
All instructions which involve memory accesses can  
require one or two additional clocks above the mini-  
mum timings shown due to the asynchronous hand-  
shake between the bus interface unit (BIU) and exe-  
cution unit.  
80C186EA/80C188EA EXECUTION  
TIMINGS  
A determination of program exeuction timing must  
consider the bus cycles necessary to prefetch in-  
structions as well as the number of execution unit  
cycles necessary to execute instructions. The fol-  
lowing instruction timings represent the minimum  
execution time in clock cycle for each instruction.  
The timings given are based on the following as-  
sumptions:  
With a 16-bit BIU, the 80C186EA has sufficient bus  
performance to endure that an adequate number of  
prefetched bytes will reside in the queue (6 bytes)  
most of the time. Therefore, actual program exeuc-  
tion time will not be substanially greater than that  
derived from adding the instruction timings shown.  
The opcode, along with any data or displacement  
#
required for execution of a particular instruction,  
has been prefetched and resides in the queue at  
the time it is needed.  
The 80C188EA 8-bit BIU is limited in its performance  
relative to the execution unit. A sufficient number of  
prefetched bytes may not reside in the prefetch  
queue (4 bytes) much of the time. Therefore, actual  
program execution time will be substantially greater  
than that derived from adding the instruction timings  
shown.  
No wait states or bus HOLDs occur.  
#
All word-data is located on even-address bound-  
aries. (80C186EA only)  
#
All jumps and calls include the time required to fetch  
the opcode of the next instruction at the destination  
address.  
43  
43  
80C186EA/80C188EA, 80L186EA/80L188EA  
INSTRUCTION SET SUMMARY  
80C186EA 80C188EA  
Function  
Format  
Comments  
Clock  
Clock  
Cycles  
Cycles  
DATA TRANSFER  
e
MOV  
Move:  
Register to Register/Memory  
Register/memory to register  
Immediate to register/memory  
Immediate to register  
1 0 0 0 1 0 0 w  
1 0 0 0 1 0 1 w  
1 1 0 0 0 1 1 w  
1 0 1 1 w reg  
1 0 1 0 0 0 0 w  
1 0 1 0 0 0 1 w  
1 0 0 0 1 1 1 0  
1 0 0 0 1 1 0 0  
mod reg r/m  
mod reg r/m  
mod 000 r/m  
data  
2/12  
2/9  
12–13  
3–4  
8
2/12*  
2/9  
e
data  
data if w  
1
12–13  
3–4  
8*  
8/16-bit  
8/16-bit  
e
data if w  
1
Memory to accumulator  
addr-low  
addr-high  
addr-high  
Accumulator to memory  
addr-low  
9
9*  
Register/memory to segment register  
Segment register to register/memory  
mod 0 reg r/m  
mod 0 reg r/m  
2/9  
2/11  
2/13  
2/15  
e
PUSH  
Push:  
Memory  
Register  
1 1 1 1 1 1 1 1  
0 1 0 1 0 reg  
0 0 0 reg 1 1 0  
0 1 1 0 1 0 s 0  
mod 1 1 0 r/m  
16  
10  
9
20  
14  
13  
14  
Segment register  
Immediate  
e
data  
data if s  
0
10  
e
PUSHA  
Push All  
Pop:  
Memory  
0 1 1 0 0 0 0 0  
36  
68  
e
POP  
1 0 0 0 1 1 1 1  
0 1 0 1 1 reg  
0 0 0 reg 1 1 1  
mod 0 0 0 r/m  
(regi01)  
20  
10  
8
24  
14  
12  
Register  
Segment register  
e
e
POPA  
Pop All  
0 1 1 0 0 0 0 1  
51  
83  
XCHG  
Exchange:  
Register/memory with register  
Register with accumulator  
1 0 0 0 0 1 1 w  
1 0 0 1 0 reg  
mod reg r/m  
4/17  
3
4/17*  
3
e
IN  
Input from:  
Fixed port  
1 1 1 0 0 1 0 w  
1 1 1 0 1 1 0 w  
port  
port  
10  
8
10*  
Variable port  
7*  
e
OUT  
Output to:  
Fixed port  
1 1 1 0 0 1 1 w  
1 1 1 0 1 1 1 w  
1 1 0 1 0 1 1 1  
1 0 0 0 1 1 0 1  
1 1 0 0 0 1 0 1  
1 1 0 0 0 1 0 0  
1 0 0 1 1 1 1 1  
1 0 0 1 1 1 1 0  
1 0 0 1 1 1 0 0  
1 0 0 1 1 1 0 1  
9
7
9*  
7*  
15  
6
Variable port  
e
XLAT  
Translate byte to AL  
11  
6
e
LEA  
LDS  
LES  
Load EA to register  
Load pointer to DS  
Load pointer to ES  
mod reg r/m  
mod reg r/m  
mod reg r/m  
(modi11)  
(modi11)  
18  
18  
2
26  
26  
2
e
e
e
LAHF  
SAHF  
Load AH with flags  
Store AH into flags  
e
3
3
e
PUSHF  
Push flags  
Pop flags  
9
13  
12  
e
POPF  
8
Shaded areas indicate instructions not available in 8086/8088 microsystems.  
NOTE:  
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.  
44  
44  
80C186EA/80C188EA, 80L186EA/80L188EA  
INSTRUCTION SET SUMMARY (Continued)  
80C186EA 80C188EA  
Function  
Format  
Comments  
Clock  
Clock  
Cycles  
Cycles  
DATA TRANSFER (Continued)  
e
SEGMENT  
Segment Override:  
CS  
0 0 1 0 1 1 1 0  
0 0 1 1 0 1 1 0  
0 0 1 1 1 1 1 0  
0 0 1 0 0 1 1 0  
2
2
2
2
2
2
2
2
SS  
DS  
ES  
ARITHMETIC  
e
ADD  
Add:  
*
*
Reg/memory with register to either  
Immediate to register/memory  
Immediate to accumulator  
0 0 0 0 0 0 d w  
1 0 0 0 0 0 s w  
0 0 0 0 0 1 0 w  
mod reg r/m  
mod 0 0 0 r/m  
data  
3/10  
4/16  
3/4  
3/10  
4/16  
3/4  
e
data if s w 01  
data  
e
e
data if w  
1
1
8/16-bit  
8/16-bit  
e
ADC  
Add with carry:  
*
*
Reg/memory with register to either  
Immediate to register/memory  
Immediate to accumulator  
0 0 0 1 0 0 d w  
1 0 0 0 0 0 s w  
0 0 0 1 0 1 0 w  
mod reg r/m  
mod 0 1 0 r/m  
data  
3/10  
4/16  
3/4  
3/10  
4/16  
3/4  
e
data if s w 01  
data  
data if w  
e
INC  
Increment:  
*
Register/memory  
Register  
1 1 1 1 1 1 1 w  
0 1 0 0 0 reg  
mod 0 0 0 r/m  
3/15  
3
3/15  
3
e
SUB  
Subtract:  
*
*
Reg/memory and register to either  
Immediate from register/memory  
Immediate from accumulator  
0 0 1 0 1 0 d w  
1 0 0 0 0 0 s w  
0 0 1 0 1 1 0 w  
mod reg r/m  
mod 1 0 1 r/m  
data  
3/10  
4/16  
3/4  
3/10  
4/16  
3/4  
e
data if s w 01  
data  
e
e
data if w  
1
1
8/16-bit  
8/16-bit  
e
SBB  
Subtract with borrow:  
*
*
Reg/memory and register to either  
Immediate from register/memory  
Immediate from accumulator  
0 0 0 1 1 0 d w  
1 0 0 0 0 0 s w  
0 0 0 1 1 1 0 w  
mod reg r/m  
mod 0 1 1 r/m  
data  
3/10  
4/16  
3/4  
3/10  
4/16  
e
data if s w 01  
data  
*
data if w  
3/4  
e
DEC  
Decrement  
*
Register/memory  
Register  
1 1 1 1 1 1 1 w  
0 1 0 0 1 reg  
mod 0 0 1 r/m  
3/15  
3
3/15  
3
e
CMP  
Compare:  
*
*
*
Register/memory with register  
Register with register/memory  
Immediate with register/memory  
Immediate with accumulator  
0 0 1 1 1 0 1 w  
0 0 1 1 1 0 0 w  
1 0 0 0 0 0 s w  
0 0 1 1 1 1 0 w  
1 1 1 1 0 1 1 w  
0 0 1 1 0 1 1 1  
0 0 1 0 0 1 1 1  
0 0 1 1 1 1 1 1  
0 0 1 0 1 1 1 1  
mod reg r/m  
mod reg r/m  
mod 1 1 1 r/m  
data  
3/10  
3/10  
3/10  
3/4  
3/10  
3/10  
3/10  
3/4  
3/10  
8
e
data if s w 01  
data  
e
data if w  
1
8/16-bit  
*
*
e
e
e
e
e
NEG  
AAA  
DAA  
AAS  
DAS  
Change sign register/memory  
ASCII adjust for add  
mod 0 1 1 r/m  
3/10  
8
4
7
4
Decimal adjust for add  
4
ASCII adjust for subtract  
Decimal adjust for subtract  
7
4
e
MUL  
Multiply (unsigned):  
1 1 1 1 0 1 1 w  
mod 100 r/m  
Register-Byte  
Register-Word  
Memory-Byte  
Memory-Word  
26–28  
35–37  
32–34  
41–43  
26–28  
35–37  
32–34  
*
41–48  
Shaded areas indicate instructions not available in 8086/8088 microsystems.  
NOTE:  
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.  
45  
45  
80C186EA/80C188EA, 80L186EA/80L188EA  
INSTRUCTION SET SUMMARY (Continued)  
80C186EA 80C188EA  
Function  
Format  
Comments  
Clock  
Clock  
Cycles  
Cycles  
ARITHMETIC (Continued)  
e
IMUL  
Integer multiply (signed):  
1 1 1 1 0 1 1 w  
mod 1 0 1 r/m  
Register-Byte  
Register-Word  
Memory-Byte  
Memory-Word  
25–28  
34–37  
31–34  
40–43  
25–28  
34–37  
32–34  
40–43*  
e
(signed)  
e
0
IMUL  
Integer Immediate multiply  
0 1 1 0 1 0 s 1  
1 1 1 1 0 1 1 w  
mod reg r/m  
data  
data if s  
22–25  
29–32  
22-25  
29–32  
e
DIV  
Divide (unsigned):  
mod 1 1 0 r/m  
Register-Byte  
Register-Word  
Memory-Byte  
Memory-Word  
29  
38  
35  
44  
29  
38  
35  
*
44  
e
IDIV  
Integer divide (signed):  
1 1 1 1 0 1 1 w  
mod 1 1 1 r/m  
Register-Byte  
Register-Word  
Memory-Byte  
Memory-Word  
44–52  
53–61  
50–58  
59–67  
44–52  
53–61  
50–58  
59–67*  
e
e
e
e
AAM  
AAD  
CBW  
CWD  
ASCII adjust for multiply  
ASCII adjust for divide  
Convert byte to word  
1 1 0 1 0 1 0 0  
1 1 0 1 0 1 0 1  
1 0 0 1 1 0 0 0  
1 0 0 1 1 0 0 1  
0 0 0 0 1 0 1 0  
0 0 0 0 1 0 1 0  
19  
15  
2
19  
15  
2
Convert word to double word  
4
4
LOGIC  
Shift/Rotate Instructions:  
Register/Memory by 1  
1 1 0 1 0 0 0 w  
1 1 0 1 0 0 1 w  
1 1 0 0 0 0 0 w  
mod TTT r/m  
mod TTT r/m  
2/15  
2/15  
a
a
a
a
Register/Memory by CL  
5
5
n/17  
n/17  
n
n
5
5
n/17  
n/17  
n
n
a
a
a
a
Register/Memory by Count  
mod TTT r/m  
count  
TTT Instruction  
0 0 0  
0 0 1  
0 1 0  
0 1 1  
ROL  
ROR  
RCL  
RCR  
1 0 0 SHL/SAL  
1 0 1  
1 1 1  
SHR  
SAR  
e
AND  
And:  
Reg/memory and register to either  
Immediate to register/memory  
Immediate to accumulator  
0 0 1 0 0 0 d w  
1 0 0 0 0 0 0 w  
0 0 1 0 0 1 0 w  
mod reg r/m  
mod 1 0 0 r/m  
data  
3/10  
4/16  
3/4  
3/10*  
4/16*  
3/4*  
e
e
e
data  
data if w  
data if w  
data if w  
1
1
1
e
data if w  
1
1
1
8/16-bit  
8/16-bit  
8/16-bit  
e
TEST And function to flags, no result:  
*
3/10  
Register/memory and register  
1 0 0 0 0 1 0 w  
1 1 1 1 0 1 1 w  
1 0 1 0 1 0 0 w  
mod reg r/m  
mod 0 0 0 r/m  
data  
3/10  
4/10  
3/4  
Immediate data and register/memory  
Immediate data and accumulator  
data  
4/10*  
e
e
data if w  
3/4  
e
OR Or:  
Reg/memory and register to either  
Immediate to register/memory  
Immediate to accumulator  
0 0 0 0 1 0 d w  
1 0 0 0 0 0 0 w  
0 0 0 0 1 1 0 w  
mod reg r/m  
mod 0 0 1 r/m  
data  
3/10  
4/16  
3/4  
3/10*  
*
data  
4/16  
data if w  
3/4*  
Shaded areas indicate instructions not available in 8086/8088 microsystems.  
NOTE:  
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.  
46  
46  
80C186EA/80C188EA, 80L186EA/80L188EA  
INSTRUCTION SET SUMMARY (Continued)  
80C186EA 80C188EA  
Function  
Format  
Comments  
Clock  
Clock  
Cycles  
Cycles  
LOGIC (Continued)  
e
XOR  
Exclusive or:  
Reg/memory and register to either  
Immediate to register/memory  
Immediate to accumulator  
0 0 1 1 0 0 d w  
1 0 0 0 0 0 0 w  
0 0 1 1 0 1 0 w  
1 1 1 1 0 1 1 w  
mod reg r/m  
mod 1 1 0 r/m  
data  
3/10  
4/16  
3/4  
3/10*  
4/16*  
3/4  
e
1
data  
data if w  
e
data if w  
1
8/16-bit  
e
NOT  
Invert register/memory  
mod 0 1 0 r/m  
3/10  
3/10*  
STRING MANIPULATION  
e
e
e
e
e
MOVS  
CMPS  
SCAS  
LODS  
STOS  
Move byte/word  
1 0 1 0 0 1 0 w  
1 0 1 0 0 1 1 w  
1 0 1 0 1 1 1 w  
1 0 1 0 1 1 0 w  
1 0 1 0 1 0 1 w  
0 1 1 0 1 1 0 w  
0 1 1 0 1 1 1 w  
14  
22  
15  
12  
10  
14  
14  
14*  
22*  
15*  
12*  
10*  
14  
Compare byte/word  
Scan byte/word  
Load byte/wd to AL/AX  
Store byte/wd from AL/AX  
e
INS  
Input byte/wd from DX port  
e
OUTS  
Output byte/wd to DX port  
14  
Repeated by count in CX (REP/REPE/REPZ/REPNE/REPNZ)  
*
e
e
e
e
e
a
a
a
MOVS  
CMPS  
SCAS  
LODS  
STOS  
Move string  
Compare string  
Scan string  
Load string  
1 1 1 1 0 0 1 0  
1 1 1 1 0 0 1 z  
1 1 1 1 0 0 1 z  
1 1 1 1 0 0 1 0  
1 1 1 1 0 0 1 0  
1 1 1 1 0 0 1 0  
1 0 1 0 0 1 0 w  
1 0 1 0 0 1 1 w  
1 0 1 0 1 1 1 w  
1 0 1 0 1 1 0 w  
1 0 1 0 1 0 1 w  
0 1 1 0 1 1 0 w  
8
8n  
8
8n  
a
5
5
6
22n  
15n  
11n  
5
22n  
a
a
a
15n*  
5
6
a
11n*  
a
a
9n*  
Store string  
6
9n  
8n  
6
e
a
a
a
a
INS  
Input string  
8
8
8
8
8n*  
e
OUTS  
Output string  
1 1 1 1 0 0 1 0  
0 1 1 0 1 1 1 w  
8n  
8n*  
CONTROL TRANSFER  
e
CALL  
Call:  
Direct within segment  
1 1 1 0 1 0 0 0  
1 1 1 1 1 1 1 1  
disp-low  
disp-high  
15  
19  
Register/memory  
mod 0 1 0 r/m  
13/19  
17/27  
indirect within segment  
Direct intersegment  
1 0 0 1 1 0 1 0  
1 1 1 1 1 1 1 1  
segment offset  
segment selector  
23  
31  
i
(mod 11)  
Indirect intersegment  
mod 0 1 1 r/m  
38  
54  
e
JMP  
Unconditional jump:  
Short/long  
1 1 1 0 1 0 1 1  
1 1 1 0 1 0 0 1  
1 1 1 1 1 1 1 1  
disp-low  
disp-low  
14  
14  
14  
14  
Direct within segment  
disp-high  
Register/memory  
mod 1 0 0 r/m  
11/17  
11/21  
indirect within segment  
Direct intersegment  
Indirect intersegment  
1 1 1 0 1 0 1 0  
segment offset  
segment selector  
14  
26  
14  
34  
i
(mod 11)  
1 1 1 1 1 1 1 1  
mod 1 0 1 r/m  
Shaded areas indicate instructions not available in 8086/8088 microsystems.  
NOTE:  
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.  
47  
47  
80C186EA/80C188EA, 80L186EA/80L188EA  
INSTRUCTION SET SUMMARY (Continued)  
80C186EA  
Clock  
80C188EA  
Clock  
Function  
Format  
Comments  
Cycles  
Cycles  
CONTROL TRANSFER (Continued)  
e
RET  
Return from CALL:  
Within segment  
1 1 0 0 0 0 1 1  
1 1 0 0 0 0 1 0  
1 1 0 0 1 0 1 1  
1 1 0 0 1 0 1 0  
0 1 1 1 0 1 0 0  
0 1 1 1 1 1 0 0  
0 1 1 1 1 1 1 0  
0 1 1 1 0 0 1 0  
0 1 1 1 0 1 1 0  
0 1 1 1 1 0 1 0  
0 1 1 1 0 0 0 0  
0 1 1 1 1 0 0 0  
0 1 1 1 0 1 0 1  
0 1 1 1 1 1 0 1  
0 1 1 1 1 1 1 1  
0 1 1 1 0 0 1 1  
0 1 1 1 0 1 1 1  
0 1 1 1 1 0 1 1  
0 1 1 1 0 0 0 1  
0 1 1 1 1 0 0 1  
1 1 1 0 0 0 1 1  
1 1 1 0 0 0 1 0  
1 1 1 0 0 0 0 1  
1 1 1 0 0 0 0 0  
16  
20  
Within seg adding immed to SP  
Intersegment  
data-low  
data-high  
data-high  
18  
22  
22  
30  
Intersegment adding immediate to SP  
data-low  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
disp  
25  
33  
e
JE/JZ  
Jump on equal/zero  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
5/15  
6/16  
6/16  
6/16  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
4/13  
5/15  
6/16  
6/16  
6/16  
JMP not  
taken/JMP  
taken  
e
e
e
e
JL/JNGE  
JLE/JNG  
JB/JNAE  
JBE/JNA  
Jump on less/not greater or equal  
Jump on less or equal/not greater  
Jump on below/not above or equal  
Jump on below or equal/not above  
e
JP/JPE  
Jump on parity/parity even  
Jump on overflow  
Jump on sign  
e
e
JO  
JS  
e
e
e
e
e
e
JNE/JNZ  
JNL/JGE  
JNLE/JG  
JNB/JAE  
JNBE/JA  
JNP/JPO  
Jump on not equal/not zero  
Jump on not less/greater or equal  
Jump on not less or equal/greater  
Jump on not below/above or equal  
Jump on not below or equal/above  
Jump on not par/par odd  
e
e
JNO  
JNS  
Jump on not overflow  
Jump on not sign  
e
JCXZ  
LOOP  
Jump on CX zero  
Loop CX times  
e
LOOP not  
taken/LOOP  
taken  
e
LOOPZ/LOOPE  
LOOPNZ/LOOPNE  
Loop while zero/equal  
e
Loop while not zero/equal  
e
ENTER  
Enter Procedure  
1 1 0 0 1 0 0 0  
data-low  
data-high  
L
e
e
l
L
L
L
0
1
1
15  
25  
19  
29  
a
b
a
b
22 16(n 1) 26 20(n 1)  
e
LEAVE  
Leave Procedure  
1 1 0 0 1 0 0 1  
8
8
e
INT  
Interrupt:  
Type specified  
Type 3  
1 1 0 0 1 1 0 1  
1 1 0 0 1 1 0 0  
1 1 0 0 1 1 1 0  
type  
47  
45  
47  
45  
if INT. taken/  
if INT. not  
taken  
e
INTO  
Interrupt on overflow  
48/4  
48/4  
e
IRET  
Interrupt return  
1 1 0 0 1 1 1 1  
0 1 1 0 0 0 1 0  
28  
28  
e
BOUND  
Detect value out of range  
mod reg r/m  
33–35  
33–35  
Shaded areas indicate instructions not available in 8086/8088 microsystems.  
NOTE:  
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.  
48  
48  
80C186EA/80C188EA, 80L186EA/80L188EA  
INSTRUCTION SET SUMMARY (Continued)  
80C186EA 80C188EA  
Function  
Format  
Comments  
Clock  
Clock  
Cycles  
Cycles  
PROCESSOR CONTROL  
e
e
e
e
e
CLC  
CMC  
STC  
CLD  
STD  
Clear carry  
1 1 1 1 1 0 0 0  
1 1 1 1 0 1 0 1  
1 1 1 1 1 0 0 1  
1 1 1 1 1 1 0 0  
1 1 1 1 1 1 0 1  
1 1 1 1 1 0 1 0  
1 1 1 1 1 0 1 1  
1 1 1 1 0 1 0 0  
1 0 0 1 1 0 1 1  
1 1 1 1 0 0 0 0  
2
2
2
2
2
2
2
2
6
2
3
2
2
2
2
2
2
2
2
6
2
3
Complement carry  
Set carry  
Clear direction  
Set direction  
e
CLI  
STI  
Clear interrupt  
Set interrupt  
e
e
HLT  
Halt  
e
e
WAIT  
LOCK  
Wait  
if TEST  
0
e
Bus lock prefix  
e
NOP  
No Operation  
1 0 0 1 0 0 0 0  
(TTT LLL are opcode to processor extension)  
Shaded areas indicate instructions not available in 8086/8088 microsystems.  
NOTE:  
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.  
The Effective Address (EA) of the memory operand  
is computed according to the mod and r/m fields:  
reg is assigned according to the following:  
Segment  
e
e
if mod  
if mod  
11 then r/m is treated as a REG field  
e
reg  
00  
01  
10  
11  
Register  
ES  
CS  
00 then DISP  
high are absent  
0*, disp-low and disp-  
e
e
tended to 16-bits, disp-high is absent  
if mod  
01 then DISP  
disp-low sign-ex-  
SS  
DS  
e
e
e
e
e
e
e
e
e
e
if mod  
if r/m  
if r/m  
if r/m  
if r/m  
if r/m  
if r/m  
if r/m  
if r/m  
10 then DISP  
disp-high: disp-low  
e
a
a
a
a
a
a
a
a
000 then EA  
001 then EA  
010 then EA  
011 then EA  
100 then EA  
101 then EA  
110 then EA  
111 then EA  
(BX)  
(SI)  
(DI)  
(SI)  
(DI)  
DISP  
DISP  
DISP  
DISP  
e
e
e
e
e
e
e
REG is assigned according to the following table:  
e
(BX)  
(BP)  
(BP)  
e
16-Bit (w  
1)  
8-Bit (w  
000 AL  
0)  
000 AX  
001 CX  
010 DX  
011 BX  
100 SP  
101 BP  
110 SI  
a
(SI)  
DISP  
001 CL  
010 DL  
011 BL  
100 AH  
101 CH  
110 DH  
111 BH  
a
(DI)  
(BP)  
(BX)  
DISP  
DISP*  
DISP  
a
a
DISP follows 2nd byte of instruction (before data if  
required)  
111 DI  
e
e
e
*except if mod  
disp-high: disp-low.  
00 and r/m  
110 then EA  
The physical addresses of all operands addressed  
by the BP register are computed using the SS seg-  
ment register. The physical addresses of the desti-  
nation operands of the string primitive operations  
(those addressed by the DI register) are computed  
using the ES segment, which may not be overridden.  
EA calculation time is 4 clock cycles for all modes,  
and is included in the execution times given whenev-  
er appropriate.  
Segment Override Prefix  
0
0
1
reg  
1
1
0
49  
49  
80C186EA/80C188EA, 80L186EA/80L188EA  
REVISION HISTORY  
ERRATA  
Intel 80C186EA/80L186EA devices are marked with  
a 9-character alphanumeric Intel FPO number un-  
derneath the product number. This data sheet up-  
date is valid for devices with an ‘‘A’’, ‘‘B’’, ‘‘C’’, ‘‘D’’,  
or ‘‘E’’ as the ninth character in the FPO number, as  
illustrated in Figure 5 for the 68-lead PLCC package,  
Figure 6 for the 84-lead QFP (EIAJ) package, and  
Figure 7 for the 80-lead SQFP device. Such devices  
may also be identified by reading a value of 01H,  
02H, 03H from the STEPID register.  
An 80C186EA/80L186EA with a STEPID value of  
01H or 02H has the following known errata. A device  
with a STEPID of 01H or 02H can be visually identi-  
fied by noting the presence of an ‘‘A’’, ‘‘B’’, or ‘‘C’’  
alpha character, next to the FPO number. The FPO  
number location is shown in Figures 5, 6, and 7.  
1. An internal condition with the interrupt controller  
can cause no acknowledge cycle on the INTA1  
line in response to INT1. This errata only occurs  
when Interrupt 1 is configured in cascade mode  
and a higher priority interrupt exists. This errata  
will not occur consistantly, it is dependent on in-  
terrupt timing.  
This data sheet replaces the following data sheets:  
272019-002Ð80C186EA  
272020-002Ð80C188EA  
272021-002Ð80L186EA  
272022-002Ð80L188EA  
272307-001ÐSB80C186EA/SB80L186EA  
272308-001ÐSB80C188EA/SB80L188EA  
An 80C186EA/80L186EA with a STEPID value of  
03H has no known errata. A device with a STEPID of  
03H can be visually identified by noting the presence  
of a ‘‘D’’ or ‘‘E’’ alpha character next to the FPO  
number. The FPO number location is shown in Fig-  
ures 5, 6, and 7.  
50  
50  

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