Cypress Perform CY7C1526KV18 User Manual

CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

72-Mbit QDR™-II SRAM 4-Word

Burst Architecture

Features

Configurations

■ Separate Independent Read and Write Data Ports

❐ Supports concurrent transactions

CY7C1511KV18 – 8M x 8

CY7C1526KV18 – 8M x 9

CY7C1513KV18 – 4M x 18

CY7C1515KV18 – 2M x 36

■ 333 MHz Clock for High Bandwidth

■ 4-word Burst for Reducing Address Bus Frequency

■ Double Data Rate (DDR) Interfaces on both Read and Write

Ports (data transferred at 666 MHz) at 333 MHz

Functional Description

The CY7C1511KV18, CY7C1526KV18, CY7C1513KV18, and

CY7C1515KV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR-II architecture. QDR-II architecture consists

of two separate ports: the read port and the write port to access

the memory array. The read port has dedicated data outputs to

support read operations and the write port has dedicated data

inputs to support write operations. QDR-II architecture has

separate data inputs and data outputs to completely eliminate

the need to “turnaround” the data bus that exists with common

IO devices. Each port can be accessed through a common

address bus. Addresses for read and write addresses are

latched on alternate rising edges of the input (K) clock. Accesses

to the QDR-II read and write ports are independent of one

another. To maximize data throughput, both read and write ports

are equipped with DDR interfaces. Each address location is

associated with four 8-bit words (CY7C1511KV18), 9-bit words

(CY7C1526KV18), 18-bit words (CY7C1513KV18), or 36-bit

words (CY7C1515KV18) that burst sequentially into or out of the

device. Because data can be transferred into and out of the

device on every rising edge of both input clocks (K and K and C

and C), memory bandwidth is maximized while simplifying

system design by eliminating bus “turnarounds”.

■ Two Input Clocks (K and K) for precise DDR Timing

❐ SRAM uses rising edges only

■ Two Input Clocks for Output Data (C and C) to minimize Clock

Skew and Flight Time mismatches

■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

■ Single Multiplexed Address Input Bus latches Address Inputs

for Read and Write Ports

■ Separate Port Selects for Depth Expansion

■ Synchronous Internally Self-timed Writes

■ QDR™-II operates with 1.5 Cycle Read Latency when DOFF

is asserted HIGH

■ Operates similar to QDR-I Device with 1 Cycle Read Latency

when DOFF is asserted LOW

■ Available in x8, x9, x18, and x36 Configurations

■ Full Data Coherency, providing Most Current Data

■ Core V = 1.8V (±0.1V); IO V

= 1.4V to V

DDQ

❐ Supports both 1.5V and 1.8V IO supply

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

■ Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free Packages

■ Variable Drive HSTL Output Buffers

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

■ JTAG 1149.1 Compatible Test Access Port

■ Phase Locked Loop (PLL) for Accurate Data Placement

Table 1. Selection Guide

Description

333 MHz

333

300 MHz

300

250 MHz

250

200 MHz

200

167 MHz

167

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

600

560

490

430

380

600

560

490

430

380

x18

x36

620

570

500

440

390

850

790

680

580

510

Cypress Semiconductor Corporation

Document Number: 001-00435 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 30, 2009

[+] Feedback

CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Logic Block Diagram (CY7C1513KV18)

[17:0]

Write Write Write Write

Address

Reg

(19:0)

Address

(19:0)

RPS

Control

Logic

CLK

Gen.

DOFF

Read Data Reg.

REF

Reg.

Control

Logic

WPS

BWS

[17:0]

[1:0]

Logic Block Diagram (CY7C1515KV18)

[35:0]

Write Write Write Write

Address

Reg

(18:0)

Address

(18:0)

RPS

Control

Logic

CLK

Gen.

DOFF

Read Data Reg.

144

REF

Reg.

Control

Logic

WPS

BWS

[35:0]

[3:0]

Document Number: 001-00435 Rev. *E

Page 3 of 31

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CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Pin Configuration

[1]

The pin configurations for CY7C1511KV18, CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18 follow.

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1511KV18 (8M x 8)

DOFF

TDO

WPS

RPS

TDI

NWS

NC/144M

NC/288M

NWS

DDQ

REF

DDQ

TCK

TMS

CY7C1526KV18 (8M x 9)

DOFF

TDO

TDI

WPS

NC/144M

RPS

NC/288M

BWS

DDQ

REF

DDQ

TCK

TMS

Note

1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.

Document Number: 001-00435 Rev. *E

Page 4 of 31

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CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Pin Configuration (continued)

[1]

The pin configurations for CY7C1511KV18, CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18 follow.

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1513KV18 (4M x 18)

DOFF

TDO

NC/144M

WPS

BWS

RPS

TDI

NC/288M

BWS

D10

Q10

Q11

D12

Q13

D11

DDQ

Q12

D13

REF

DDQ

D14

Q14

D15

D16

Q16

Q17

Q15

D17

TCK

TMS

CY7C1515KV18 (2M x 36)

NC/288M

Q18

BWS

NC/144M

Q17

TDI

WPS

RPS

Q27

D27

D28

Q29

Q30

D30

DOFF

D31

Q32

Q33

D33

D34

Q35

TDO

D18

D19

Q19

Q20

D21

Q22

D17

D16

Q16

Q15

D14

Q13

Q28

D20

D15

D29

DDQ

Q21

Q14

D22

D13

REF

DDQ

Q31

D32

Q24

Q34

D26

D35

TCK

D23

D12

Q23

D24

D25

Q25

Q26

Q12

D11

D10

Q10

Q11

TMS

Document Number: 001-00435 Rev. *E

Page 5 of 31

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CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Pin Definitions

Pin Name

I/O

Pin Description

Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active.

Input-

[x:0]

Synchronous CY7C1511KV18 − D

[7:0]

CY7C1526KV18 − D

[8:0]

CY7C1513KV18 − D

CY7C1515KV18 − D

[17:0]

[35:0]

WPS

Input-

Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a

Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D

[x:0]

NWS ,

Input-

Nibble Write Select 0, 1 − Active LOW (CY7C1511KV18 Only). Sampled on the rising edge of the K

. Used to select which nibble is written into the device

during

Synchronous and K clocks

NWS ,

when write operations are active

NWS controls D

and NWS controls D .

the current portion of the write operations.

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

ignores the corresponding nibble of data and it is not written into the device

[3:0]

[7:4]

BWS ,

Input-

Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks when

BWS ,

Synchronous write operations are active. Used to select which byte is written into the device during the current portion

of the write operations. Bytes not written remain unaltered.

BWS ,

BWS

CY7C1526KV18 − BWS controls D

[8:0]

CY7C1513KV18 − BWS controls D

and BWS controls D

[17:9].

CY7C1515KV18 − BWS controls D

, BWS controls D

[17:9]

BWS controls D

and BWS controls D

[26:18]

[35:27].

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

ignores the corresponding byte of data and it is not written into the device

Input-

Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These

Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as

8M x 8 (4 arrays each of 2M x 8) for CY7C1511KV18, 8M x 9 (4 arrays each of 2M x 9) for CY7C1526KV18,

4M x 18 (4 arrays each of 1M x 18) for CY7C1513KV18 and 2M x 36 (4 arrays each of 512K x 36) for

CY7C1515KV18. Therefore, only 21 address inputs are needed to access the entire memory array of

CY7C1511KV18 and CY7C1526KV18, 20 address inputs for CY7C1513KV18 and 19 address inputs for

CY7C1515KV18. These inputs are ignored when the appropriate port is deselected.

Outputs-

Data Output Signals. These pins drive out the requested data when the read operation is active. Valid

[x:0]

Synchronous data is driven out on the rising edge of the C and C clocks during read operations, or K and K when in

single clock mode. On deselecting the read port, Q

are automatically tristated.

[x:0]

CY7C1511KV18 − Q

[7:0]

CY7C1526KV18 − Q

[8:0]

CY7C1513KV18 − Q

CY7C1515KV18 − Q

[17:0]

[35:0]

RPS

Input-

Read Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a

Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is

allowed to complete and the output drivers are automatically tristated following the next rising edge of the

C clock. Each read access consists of a burst of four sequential transfers.

Input Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from

the device. C and C can be used together to deskew the flight times of various devices on the board back

to the controller. See Application Example on page 10 for further details.

Input Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from

the device. C and C can be used together to deskew the flight times of various devices on the board back

to the controller. See Application Example on page 10 for further details.

Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

and to drive out data through Q

when in single clock mode. All accesses are initiated on the rising

[x:0]

edge of K.

Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and

to drive out data through Q when in single clock mode.

[x:0]

Document Number: 001-00435 Rev. *E

Page 6 of 31

[+] Feedback

CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Pin Definitions (continued)

Pin Name

I/O

Pin Description

Echo Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings

for the echo clocks are shown in the Switching Characteristics on page 24.

Echo Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings

for the echo clocks are shown in the Switching Characteristics on page 24.

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

impedance. CQ, CQ, and Q output impedance are set to 0.2 x RQ, where RQ is a resistor connected

[x:0]

between ZQ and ground. Alternatively, this pin can be connected directly to V

, which enables the

DDQ

minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

DOFF

Input

PLL Turn Off − Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings

in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin

is connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in QDR-I mode

when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz

with QDR-I timing.

TDO

Output

Input

N/A

TDO for JTAG.

TCK

TCK Pin for JTAG.

TDI

TDI Pin for JTAG.

TMS

TMS Pin for JTAG.

Not Connected to the Die. Can be tied to any voltage level.

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC

NC/144M

NC/288M

N/A

Input-

REF

Reference measurement points.

Power Supply Power Supply Inputs to the Core of the Device.

Ground

Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

DDQ

Document Number: 001-00435 Rev. *E

Page 7 of 31

[+] Feedback

CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

from the rising edge of the output clock (C or C, or K or K when

in single clock mode). To maintain the internal logic, each read

access must be allowed to complete. Each read access consists

of four 18-bit data words and takes two clock cycles to complete.

Therefore, read accesses to the device cannot be initiated on

two consecutive K clock rises. The internal logic of the device

ignores the second read request. Read accesses can be initiated

on every other K clock rise. Doing so pipelines the data flow such

that data is transferred out of the device on every rising edge of

the output clocks (C and C, or K and K when in single clock

mode).

Functional Overview

The CY7C1511KV18, CY7C1526KV18, CY7C1513KV18,

CY7C1515KV18 are synchronous pipelined Burst SRAMs with a

read port and a write port. The read port is dedicated to read

operations and the write port is dedicated to write operations.

Data flows into the SRAM through the write port and flows out

through the read port. These devices multiplex the address

inputs to minimize the number of address pins required. By

having separate read and write ports, the QDR-II completely

eliminates the need to turn around the data bus and avoids any

possible data contention, thereby simplifying system design.

Each access consists of four 8-bit data transfers in the case of

CY7C1511KV18, four 9-bit data transfers in the case of

CY7C1526KV18, four 18-bit data transfers in the case of

CY7C1513KV18, and four 36-bit data transfers in the case of

CY7C1515KV18 in two clock cycles.

When the read port is deselected, the CY7C1513KV18 first

completes the pending read transactions. Synchronous internal

circuitry automatically tristates the outputs following the next

rising edge of the positive output clock (C). This enables a

seamless transition between devices without the insertion of wait

states in a depth expanded memory.

This device operates with a read latency of one and half cycles

when DOFF pin is tied HIGH. When DOFF pin is set LOW or

Write Operations

connected to V then device behaves in QDR-I mode with a

read latency of one clock cycle.

Write operations are initiated by asserting WPS active at the

rising edge of the positive input clock (K). On the following K

clock rise the data presented to D

the lower 18-bit write data register, provided BWS

asserted active. On the subsequent rising edge of the negative

input clock (K) the information presented to D

is latched and stored into

Accesses for both ports are initiated on the positive input clock

(K). All synchronous input timing is referenced from the rising

edge of the input clocks (K and K) and all output timing is refer-

enced to the output clocks (C and C, or K and K when in single

clock mode).

[17:0]

are both

[1:0]

is also stored

[17:0]

into the write data register, provided BWS

are both asserted

[1:0]

active. This process continues for one more cycle until four 18-bit

words (a total of 72 bits) of data are stored in the SRAM. The 72

bits of data are then written into the memory array at the specified

location. Therefore, write accesses to the device cannot be

initiated on two consecutive K clock rises. The internal logic of

the device ignores the second write request. Write accesses can

be initiated on every other rising edge of the positive input clock

(K). Doing so pipelines the data flow such that 18 bits of data can

be transferred into the device on every rising edge of the input

clocks (K and K).

All synchronous data inputs (D

controlled by the input clocks (K and K). All synchronous data

) pass through input registers

[x:0]

outputs (Q ) pass through output registers controlled by the

[x:0]

rising edge of the output clocks (C and C, or K and K when in

single clock mode).

All synchronous control (RPS, WPS, BWS

through input registers controlled by the rising edge of the input

clocks (K and K).

) inputs pass

[x:0]

CY7C1513KV18 is described in the following sections. The

same basic descriptions apply to CY7C1511KV18,

CY7C1526KV18 and CY7C1515KV18.

When deselected, the write port ignores all inputs after the

pending write operations are completed.

Read Operations

Byte Write Operations

The CY7C1513KV18 is organized internally as four arrays of 1M

x 18. Accesses are completed in a burst of four sequential 18-bit

data words. Read operations are initiated by asserting RPS

active at the rising edge of the positive input clock (K). The

address presented to the address inputs is stored in the read

address register. Following the next K clock rise, the corre-

sponding lowest order 18-bit word of data is driven onto the

Byte write operations are supported by the CY7C1513KV18. A

write operation is initiated as described in the Write Operations

section. The bytes that are written are determined by BWS and

BWS , which are sampled with each set of 18-bit data words.

Asserting the appropriate Byte Write Select input during the data

portion of a write latches the data being presented and writes it

into the device. Deasserting the Byte Write Select input during

the data portion of a write enables the data stored in the device

for that byte to remain unaltered. This feature is used to simplify

read, modify, or write operations to a byte write operation.

using C as the output timing reference. On the subse-

[17:0]

quent rising edge of C, the next 18-bit data word is driven onto

the Q . This process continues until all four 18-bit data words

[17:0]

are driven out onto Q

. The requested data is valid 0.45 ns

[17:0]

Document Number: 001-00435 Rev. *E

Page 8 of 31

[+] Feedback

CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Single Clock Mode

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin

The CY7C1511KV18 is used with a single clock that controls

both the input and output registers. In this mode the device

recognizes only a single pair of input clocks (K and K) that control

both the input and output registers. This operation is identical to

the operation if the device had zero skew between the K/K and

C/C clocks. All timing parameters remain the same in this mode.

To use this mode of operation, the user must tie C and C HIGH

at power on. This function is a strap option and not alterable

during device operation.

on the SRAM and V to allow the SRAM to adjust its output

driver impedance. The value of RQ must be 5X the value of the

intended line impedance driven by the SRAM, the allowable

range of RQ to guarantee impedance matching with a tolerance

of ±15% is between 175Ω and 350Ω, with V

= 1.5V. The

DDQ

output impedance is adjusted every 1024 cycles upon power up

to account for drifts in supply voltage and temperature.

Echo Clocks

Concurrent Transactions

Echo clocks are provided on the QDR-II to simplify data capture

on high speed systems. Two echo clocks are generated by the

QDR-II. CQ is referenced with respect to C and CQ is referenced

with respect to C. These are free running clocks and are synchro-

nized to the output clock of the QDR-II. In the single clock mode,

CQ is generated with respect to K and CQ is generated with

respect to K. The timing for the echo clocks is shown in the

Switching Characteristics on page 24.

The read and write ports on the CY7C1513KV18 operate

independently of one another. As each port latches the address

inputs on different clock edges, the user can read or write to any

location, regardless of the transaction on the other port. If the

ports access the same location when a read follows a write in

successive clock cycles, the SRAM delivers the most recent

information associated with the specified address location. This

includes forwarding data from a write cycle that was initiated on

the previous K clock rise.

PLL

These chips use a PLL that is designed to function between

120 MHz and the specified maximum clock frequency. During

power up, when the DOFF is tied HIGH, the PLL is locked after

20 μs of stable clock. The PLL can also be reset by slowing or

stopping the input clocks K and K for a minimum of 30 ns.

However, it is not necessary to reset the PLL to lock to the

desired frequency. The PLL automatically locks 20 μs after a

stable clock is presented. The PLL may be disabled by applying

ground to the DOFF pin. When the PLL is turned off, the device

behaves in QDR-I mode (with one cycle latency and a longer

access time).

Read access and write access must be scheduled such that one

transaction is initiated on any clock cycle. If both ports are

selected on the same K clock rise, the arbitration depends on the

previous state of the SRAM. If both ports are deselected, the

read port takes priority. If a read was initiated on the previous

cycle, the write port takes priority (as read operations cannot be

initiated on consecutive cycles). If a write was initiated on the

previous cycle, the read port takes priority (as write operations

cannot be initiated on consecutive cycles). Therefore, asserting

both port selects active from a deselected state results in alter-

nating read or write operations being initiated, with the first

access being a read.

Depth Expansion

The CY7C1513KV18 has a port select input for each port. This

enables for easy depth expansion. Both port selects are sampled

on the rising edge of the positive input clock only (K). Each port

select input can deselect the specified port. Deselecting a port

does not affect the other port. All pending transactions (read and

write) are completed before the device is deselected.

Document Number: 001-00435 Rev. *E

Page 9 of 31

[+] Feedback

CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Application Example

Figure 1 shows four QDR-II used in an application.

Figure 1. Application Example

SRAM #1

R = 250ohms

SRAM #4

R = 250ohms

CQ/CQ#

R W

C# K K#

DATA IN

DATA OUT

Address

RPS#

BUS

MASTER

(CPU

WPS#

BWS#

CLKIN/CLKIN#

Source K

Source K#

ASIC)

Delayed K

Delayed K#

R = 50ohms

Vt = Vddq/2

Truth Table

[2, 3, 4, 5, 6, 7]

The truth table for CY7C1511KV18, CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18 follows.

Operation

Write Cycle:

RPS WPS

[8]

[9]

L-H

D(A) at K(t + 1)↑ D(A + 1) at K(t + 1)↑ D(A + 2) at K(t + 2)↑ D(A + 3) at K(t + 2)↑

Load address on the rising

edge of K; input write data

on two consecutive K and

K rising edges.

[9]

Read Cycle:

L-H

Q(A) at C(t + 1)↑ Q(A + 1) at C(t + 2)↑ Q(A + 2) at C(t + 2)↑ Q(A + 3) at C(t + 3)↑

Load address on the rising

edge of K; wait one and a

half cycle; read data on

two consecutive C and C

rising edges.

NOP: No Operation

L-H

D = X

Q = High-Z

D = X

Q = High-Z

D = X

Q = High-Z

D = X

Q = High-Z

Standby: Clock Stopped Stopped

Previous State

Notes

^{2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,}↑represents rising edge.

3. Device powers up deselected with the outputs in a tristate condition.

4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.

5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.

6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging

symmetrically.

8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.

9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the

second read or write request.

Document Number: 001-00435 Rev. *E

Page 10 of 31

[+] Feedback

CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Write Cycle Descriptions

The write cycle description table for CY7C1511KV18 and CY7C1513KV18 follows.

[2, 10]

BWS / BWS /

Comments

NWS

L–H

–

During the data portion of a write sequence:

CY7C1511KV18 − both nibbles (D

) are written into the device.

[7:0]

CY7C1513KV18 − both bytes (D

) are written into the device.

[17:0]

–

L–H

–

L-H During the data portion of a write sequence:

CY7C1511KV18 − both nibbles (D

) are written into the device.

[7:0]

CY7C1513KV18 − both bytes (D

) are written into the device.

[17:0]

–

During the data portion of a write sequence:

CY7C1511KV18 − only the lower nibble (D

) is written into the device, D

remains unaltered.

[3:0]

[7:4]

[17:9]

CY7C1513KV18 − only the lower byte (D

[8:0]

L–H During the data portion of a write sequence:

CY7C1511KV18 − only the lower nibble (D

) is written into the device, D

remains unaltered.

[3:0]

[7:4]

CY7C1513KV18 − only the lower byte (D

[8:0]

[17:9]

L–H

–

During the data portion of a write sequence:

CY7C1511KV18 − only the upper nibble (D

) is written into the device, D

remains unaltered.

[3:0]

[7:4]

CY7C1513KV18 − only the upper byte (D

remains unaltered.

[17:9]

[8:0]

L–H During the data portion of a write sequence:

CY7C1511KV18 − only the upper nibble (D

) is written into the device, D

remains unaltered.

[7:4]

[3:0]

[8:0]

CY7C1513KV18 − only the upper byte (D

[17:9]

L–H

–

No data is written into the devices during this portion of a write operation.

L–H No data is written into the devices during this portion of a write operation.

Write Cycle Descriptions

The write cycle description table for CY7C1526KV18 follows.

[2, 10]

BWS

L–H

–

During the data portion of a write sequence, the single byte (D

) is written into the device.

[8:0]

L–H During the data portion of a write sequence, the single byte (D

[8:0]

L–H

–

No data is written into the device during this portion of a write operation.

L–H No data is written into the device during this portion of a write operation.

Note

10. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS , NWS , BWS , BWS , BWS , and BWS can be altered on

different portions of a write cycle, as long as the setup and hold requirements are achieved.

Document Number: 001-00435 Rev. *E

Page 11 of 31

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CY7C1513KV18, CY7C1515KV18

Write Cycle Descriptions

The write cycle description table for CY7C1515KV18 follows.

[2 , 10]

BWS

Comments

L–H

–

During the data portion of a write sequence, all four bytes (D

the device.

) are written into

[35:0]

–

L–H

–

L–H During the data portion of a write sequence, all four bytes (D

the device.

[35:0]

–

During the data portion of a write sequence, only the lower byte (D

) is written

[8:0]

into the device. D

remains unaltered.

[35:9]

L–H During the data portion of a write sequence, only the lower byte (D

into the device. D remains unaltered.

[35:9]

L–H

–

During the data portion of a write sequence, only the byte (D

) is written into

[17:9]

the device. D

and D

remains unaltered.

[8:0]

[35:18]

L–H During the data portion of a write sequence, only the byte (D

the device. D and D remains unaltered.

[17:9]

[8:0]

[35:18]

L–H

–

During the data portion of a write sequence, only the byte (D

) is written into

[26:18]

[35:27]

the device. D

and D

remains unaltered.

[17:0]

[35:27]

L–H During the data portion of a write sequence, only the byte (D

the device. D and D remains unaltered.

[17:0]

[35:27]

L–H

–

During the data portion of a write sequence, only the byte (D

the device. D remains unaltered.

[26:0]

L–H During the data portion of a write sequence, only the byte (D

the device. D remains unaltered.

[26:0]

L–H

–

No data is written into the device during this portion of a write operation.

L–H No data is written into the device during this portion of a write operation.

Document Number: 001-00435 Rev. *E

Page 12 of 31

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CY7C1513KV18, CY7C1515KV18

Instruction Register

IEEE 1149.1 Serial Boundary Scan (JTAG)

Three-bit instructions are serially loaded into the instruction

and TDO pins, as shown in TAP Controller Block Diagram on

page 16. Upon power up, the instruction register is loaded with

the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state, as described

in the previous section.

These SRAMs incorporate a serial boundary scan Test Access

Port (TAP) in the FBGA package. This part is fully compliant with

IEEE Standard #1149.1-2001. The TAP operates using JEDEC

standard 1.8V IO logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

When the TAP controller is in the Capture-IR state, the two least

significant bits are loaded with a binary “01” pattern to allow for

fault isolation of the board level serial test path.

(V ) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternatively

be connected to V through a pull up resistor. TDO must be left

unconnected. Upon power up, the device comes up in a reset

state, which does not interfere with the operation of the device.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

TDO pins. This enables shifting of data through the SRAM with

minimal delay. The bypass register is set LOW (V ) when the

BYPASS instruction is executed.

Test Access Port—Test Clock

The test clock is used only with the TAP controller. All inputs are

captured on the rising edge of TCK. All outputs are driven from

the falling edge of TCK.

Boundary Scan Register

Test Mode Select (TMS)

The boundary scan register is connected to all of the input and

output pins on the SRAM. Several No Connect (NC) pins are also

included in the scan register to reserve pins for higher density

devices.

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. This pin may be left

unconnected if the TAP is not used. The pin is pulled up inter-

nally, resulting in a logic HIGH level.

The boundary scan register is loaded with the contents of the

RAM input and output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and TDO

pins when the controller is moved to the Shift-DR state. The

EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions are

used to capture the contents of the input and output ring.

Test Data-In (TDI)

The TDI pin is used to serially input information into the registers

and can be connected to the input of any of the registers. The

is loaded into the TAP instruction register. For information about

loading the instruction register, see the TAP Controller State

Diagram on page 15. TDI is internally pulled up and can be

unconnected if the TAP is unused in an application. TDI is

connected to the most significant bit (MSB) on any register.

The Boundary Scan Order on page 19 shows the order in which

the bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected to

TDI, and the LSB is connected to TDO.

Identification (ID) Register

Test Data-Out (TDO)

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired into

the SRAM and can be shifted out when the TAP controller is in

the Shift-DR state. The ID register has a vendor code and other

information described in Identification Register Definitions on

page 18.

The TDO output pin is used to serially clock data out from the

registers. The output is active, depending upon the current state

of the TAP state machine (see Instruction Codes on page 18).

The output changes on the falling edge of TCK. TDO is

connected to the least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (V ) for five rising

TAP Instruction Set

edges of TCK. This Reset does not affect the operation of the

SRAM and can be performed when the SRAM is operating. At

power up, the TAP is reset internally to ensure that TDO comes

up in a high-Z state.

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in Instruction

Codes on page 18. Three of these instructions are listed as

RESERVED and must not be used. The other five instructions

are described in this section in detail.

TAP Registers

Instructions are loaded into the TAP controller during the Shift-IR

state when the instruction register is placed between TDI and

TDO. During this state, instructions are shifted through the

instruction register through the TDI and TDO pins. To execute

the instruction after it is shifted in, the TAP controller must be

moved into the Update-IR state.

Registers are connected between the TDI and TDO pins to scan

the data in and out of the SRAM test circuitry. Only one register

can be selected at a time through the instruction registers. Data

is serially loaded into the TDI pin on the rising edge of TCK. Data

is output on the TDO pin on the falling edge of TCK.

Document Number: 001-00435 Rev. *E

Page 13 of 31

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IDCODE

PRELOAD places an initial data pattern at the latched parallel

outputs of the boundary scan register cells before the selection

of another boundary scan test operation.

The IDCODE instruction loads a vendor-specific, 32-bit code into

the instruction register. It also places the instruction register

between the TDI and TDO pins and shifts the IDCODE out of the

device when the TAP controller enters the Shift-DR state. The

IDCODE instruction is loaded into the instruction register at

power up or whenever the TAP controller is supplied a

Test-Logic-Reset state.

The shifting of data for the SAMPLE and PRELOAD phases can

occur concurrently when required, that is, while the data

captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register

and the TAP is placed in a Shift-DR state, the bypass register is

placed between the TDI and TDO pins. The advantage of the

BYPASS instruction is that it shortens the boundary scan path

when multiple devices are connected together on a board.

SAMPLE Z

The SAMPLE Z instruction connects the boundary scan register

between the TDI and TDO pins when the TAP controller is in a

Shift-DR state. The SAMPLE Z command puts the output bus

into a High-Z state until the next command is supplied during the

Update IR state.

EXTEST

The EXTEST instruction drives the preloaded data out through

the system output pins. This instruction also connects the

boundary scan register for serial access between the TDI and

TDO in the Shift-DR controller state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the input and output pins is captured

in the boundary scan register.

EXTEST OUTPUT BUS TRISTATE

IEEE Standard 1149.1 mandates that the TAP controller be able

to put the output bus into a tristate mode.

The TAP controller clock can only operate at a frequency up to

20 MHz, while the SRAM clock operates more than an order of

magnitude faster. Because there is a large difference in the clock

frequencies, it is possible that during the Capture-DR state, an

input or output undergoes a transition. The TAP may then try to

capture a signal while in transition (metastable state). This does

not harm the device, but there is no guarantee as to the value

that is captured. Repeatable results may not be possible.

The boundary scan register has a special bit located at bit #108.

When this scan cell, called the “extest output bus tristate,” is

latched into the preload register during the Update-DR state in

the TAP controller, it directly controls the state of the output

(Q-bus) pins, when the EXTEST is entered as the current

instruction. When HIGH, it enables the output buffers to drive the

output bus. When LOW, this bit places the output bus into a

High-Z condition.

To guarantee that the boundary scan register captures the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture setup plus hold

times (t and t ). The SRAM clock input might not be captured

This bit is set by entering the SAMPLE/PRELOAD or EXTEST

command, and then shifting the desired bit into that cell, during

the Shift-DR state. During Update-DR, the value loaded into that

shift-register cell latches into the preload register. When the

EXTEST instruction is entered, this bit directly controls the output

Q-bus pins. Note that this bit is preset HIGH to enable the output

when the device is powered up, and also when the TAP controller

is in the Test-Logic-Reset state.

correctly if there is no way in a design to stop (or slow) the clock

during a SAMPLE/PRELOAD instruction. If this is an issue, it is

still possible to capture all other signals and simply ignore the

value of the CK and CK captured in the boundary scan register.

After the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the boundary

scan register between the TDI and TDO pins.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

Document Number: 001-00435 Rev. *E

Page 14 of 31

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CY7C1513KV18, CY7C1515KV18

TAP Controller State Diagram

The state diagram for the TAP controller follows.

[11]

TEST-LOGIC

RESET

SELECT

TEST-LOGIC/

SELECT

IR-SCAN

IDLE

DR-SCAN

CAPTURE-DR

CAPTURE-IR

SHIFT-DR

SHIFT-IR

EXIT1-DR

EXIT1-IR

PAUSE-DR

PAUSE-IR

EXIT2-DR

EXIT2-IR

UPDATE-IR

UPDATE-DR

Note

11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document Number: 001-00435 Rev. *E

Page 15 of 31

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TAP Controller Block Diagram

Bypass Register

Selection

TDI

Selection

Circuitry

TDO

Instruction Register

Circuitry

31 30

Identification Register

108

Boundary Scan Register

TCK

TMS

TAP Controller

TAP Electrical Characteristics

[12, 13, 14]

Over the Operating Range

Parameter

Description

Output HIGH Voltage

Test Conditions

= −2.0 mA

Min

1.4

1.6

Max

Unit

OH1

OH2

OL1

OL2

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

= −100 μA

= 2.0 mA

0.4

0.2

= 100 μA

0.65V

+ 0.3

Input LOW Voltage

–0.3

–5

0.35V

Input and Output Load Current

GND ≤ V ≤ V

μA

Notes

12. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.

13. Overshoot: V (AC) < V + 0.85V (Pulse width less than t /2).

/2), Undershoot: V (AC) > −1.5V (Pulse width less than t

DDQ

CYC

14. All voltage referenced to Ground.

Document Number: 001-00435 Rev. *E

Page 16 of 31

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TAP AC Switching Characteristics

[15, 16]

Over the Operating Range

Parameter

Description

Min

Max

Unit

TCK Clock Cycle Time

TCK Clock Frequency

TCK Clock HIGH

TCYC

MHz

TCK Clock LOW

Setup Times

TMS Setup to TCK Clock Rise

TDI Setup to TCK Clock Rise

Capture Setup to TCK Rise

TMSS

TDIS

Hold Times

TMS Hold after TCK Clock Rise

TDI Hold after Clock Rise

TMSH

TDIH

Capture Hold after Clock Rise

Output Times

TCK Clock LOW to TDO Valid

TCK Clock LOW to TDO Invalid

TDOV

TDOX

TAP Timing and Test Conditions

Figure 2 shows the TAP timing and test conditions.

[16]

Figure 2. TAP Timing and Test Conditions

0.9V

ALL INPUT PULSES

1.8V

50Ω

0.9V

TDO

Z = 50

C = 20 pF

GND

(a)

Test Clock

TCK

TCYC

TMSH

TMSS

Test Mode Select

TMS

TDIS

TDIH

Test Data In

TDI

Test Data Out

TDO

TDOV

TDOX

Notes

15. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.

16. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.

Document Number: 001-00435 Rev. *E

Page 17 of 31

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CY7C1513KV18, CY7C1515KV18

Identification Register Definitions

Value

Instruction Field

Description

CY7C1511KV18

CY7C1526KV18

000

CY7C1513KV18

000

CY7C1515KV18

Revision Number

(31:29)

000

Version number.

Cypress Device ID 11010011011000100 11010011011001100 11010011011010100 11010011011100100 Defines the type of

(28:12)

SRAM.

Cypress JEDEC ID

(11:1)

00000110100

Allows unique

identification of

SRAM vendor.

ID Register

Presence (0)

Indicates the

presence of an ID

Scan Register Sizes

Bit Size

Instruction

Bypass

109

Boundary Scan

Instruction Codes

Instruction

EXTEST

Code

000

Description

Captures the input and output ring contents.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

SAMPLE Z

010

Captures the input and output contents. Places the boundary scan register between TDI and

TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED

011

100

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

Captures the input and output ring contents. Places the boundary scan register between TDI

and TDO. Does not affect the SRAM operation.

RESERVED

BYPASS

101

110

111

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operation.

Document Number: 001-00435 Rev. *E

Page 18 of 31

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Boundary Scan Order

Bit #

Bump ID

Bit #

Bump ID

10G

Bit #

Bump ID

Bit #

Bump ID

11F

11G

10F

11E

10E

10D

11P

10P

10N

10C

11D

10M

11N

11B

11C

100

101

102

103

104

105

106

107

108

11L

11M

10B

11A

10A

10L

11K

10K

Internal

10J

11J

11H

Document Number: 001-00435 Rev. *E

Page 19 of 31

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PLL Constraints

Power Up Sequence in QDR-II SRAM

■ PLL uses K clock as its synchronizing input. The input must

have low phase jitter, which is specified as t

QDR-II SRAMs must be powered up and initialized in a

predefined manner to prevent undefined operations.

KC Var

■ The PLL functions at frequencies down to 120 MHz.

Power Up Sequence

■ If the input clock is unstable and the PLL is enabled, then the

PLL may lock onto an incorrect frequency, causing unstable

SRAM behavior. To avoid this, provide 20 μs of stable clock to

relock to the desired clock frequency.

■ Apply power and drive DOFF either HIGH or LOW (All other

inputs can be HIGH or LOW).

❐ Apply V before V

DDQ

❐ Apply V

before V

or at the same time as V

DDQ

REF

❐ Drive DOFF HIGH.

■ Provide stable DOFF (HIGH), power and clock (K, K) for 20 μs

to lock the PLL.

Figure 3. Power Up Waveforms

Unstable Clock

> 20Ps Stable clock

Stable)

DDQ

Start Normal

Operation

Clock Start (Clock Starts after V

Stable (< +/- 0.1V DC per 50ns )

V_DDQ

V_DD

DDQ

Fix HIGH (or tie to V

)

DDQ

DOFF

Document Number: 001-00435 Rev. *E

Page 20 of 31

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CY7C1513KV18, CY7C1515KV18

Current into Outputs (LOW) ........................................ 20 mA

Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V

Latch up Current.................................................... > 200 mA

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with Power Applied.. –55°C to +125°C

Operating Range

Ambient

[17]

Supply Voltage on V Relative to GND........–0.5V to +2.9V

Range

Commercial

Industrial

Temperature (T )

DDQ

Supply Voltage on V

Relative to GND.......–0.5V to +V

0°C to +70°C

1.8 ± 0.1V

1.4V to

DDQ

DC Applied to Outputs in High-Z ........ –0.5V to V

+ 0.3V

–40°C to +85°C

DDQ

[13]

DC Input Voltage

.............................. –0.5V to V + 0.3V

Electrical Characteristics

DC Electrical Characteristics

[14]

Over the Operating Range

Parameter

Description

Power Supply Voltage

IO Supply Voltage

Test Conditions

Min

1.7

1.4

Typ

Max

Unit

1.8

1.5

1.9

DDQ

Output HIGH Voltage

Output LOW Voltage

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Note 18

Note 19

/2 – 0.12

– 0.2

/2 + 0.12

DDQ

= −0.1 mA, Nominal Impedance

OH(LOW)

OL(LOW)

DDQ

= 0.1 mA, Nominal Impedance

0.2

+ 0.1

+ 0.3

REF

DDQ

–0.3

– 0.1

REF

Input Leakage Current

Output Leakage Current

Input Reference Voltage

GND ≤ V ≤ V

−5

μA

DDQ

GND ≤ V ≤ V

Output Disabled

DDQ,

[20]

Typical Value = 0.75V

0.68

0.75

0.95

600

620

850

560

570

790

490

500

680

REF

[21]

Operating Supply

= Max,

333 MHz

300 MHz

250 MHz

(x8)

(x9)

= 0 mA,

OUT

f = f

= 1/t

MAX

CYC

(x18)

(x36)

(x8)

(x9)

(x18)

(x36)

(x8)

(x9)

(x18)

(x36)

Notes

17. Power up: Assumes a linear ramp from 0V to V (min) within 200 ms. During this time V < V and V

< V .

DDQ

18. Output are impedance controlled. I = −(V

/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

DDQ

19. Output are impedance controlled. I = (V

20. V

(min) = 0.68V or 0.46V

, whichever is larger, V

(max) = 0.95V or 0.54V

, whichever is smaller.

REF

DDQ

REF

DDQ

21. The operation current is calculated with 50% read cycle and 50% write cycle.

Document Number: 001-00435 Rev. *E

Page 21 of 31

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Electrical Characteristics (continued)

DC Electrical Characteristics

[14]

Over the Operating Range

Parameter

Description

Test Conditions

200 MHz

Min

Typ

Max

430

440

580

380

390

510

290

280

270

250

Unit

[21]

Operating Supply

= Max,

(x8)

(x9)

= 0 mA,

OUT

f = f

= 1/t

MAX

CYC

(x18)

(x36)

(x8)

167 MHz

333 MHz

300 MHz

250 MHz

200 MHz

167 MHz

(x9)

(x18)

(x36)

(x8)

Automatic Power Down

Current

Max V

SB1

Both Ports Deselected,

(x9)

≥ V or V ≤ V

f = f

Inputs Static

= 1/t

(x18)

(x36)

(x8)

MAX

CYC

(x9)

(x18)

(x36)

(x8)

(x9)

(x18)

(x36)

(x8)

(x9)

(x18)

(x36)

(x8)

(x9)

(x18)

(x36)

AC Electrical Characteristics

[13]

Over the Operating Range

Parameter

Description

Input HIGH Voltage

Input LOW Voltage

Test Conditions

Min

+ 0.2

REF

Typ

–

Max

Unit

–

– 0.2

REF

Document Number: 001-00435 Rev. *E

Page 22 of 31

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Capacitance

Tested initially and after any design or process change that may affect these parameters.

Parameter

Description

Input Capacitance

Output Capacitance

Test Conditions

Max

Unit

T = 25°C, f = 1 MHz, V = 1.8V, V

= 1.5V

DDQ

Thermal Resistance

Tested initially and after any design or process change that may affect these parameters.

165 FBGA

Package

Parameter

Description

Test Conditions

Unit

Thermal Resistance

(Junction to Ambient)

Test conditions follow standard test methods and

procedures for measuring thermal impedance, in

accordance with EIA/JESD51.

13.7

°C/W

Thermal Resistance

(Junction to Case)

3.73

°C/W

Figure 4. AC Test Loads and Waveforms

_REF= 0.75V

0.75V

V_REF

0.75V

R = 50Ω

OUTPUT

[22]

ALL INPUT PULSES

1.25V

Z = 50Ω

OUTPUT

Device

Under

Test

R = 50Ω

0.75V

Device

Under

0.25V

5 pF

V_REF= 0.75V

Slew Rate = 2 V/ns

Test

RQ =

250Ω

INCLUDING

JIG AND

SCOPE

(a)

(b)

Note

22. Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, V

= 1.5V, input

DDQ

pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC T e st Loads and Waveforms.

OL OH

Document Number: 001-00435 Rev. *E

Page 23 of 31

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Switching Characteristics

[22, 23]

Over the Operating Range

333 MHz

300 MHz

250 MHz

200 MHz

167 MHz

Cypress Consortium

Parameter Parameter

Description

(Typical) to the First Access

Unit

Min Max Min Max Min Max Min Max Min Max

[24]

POWER

CYC

K Clock and C Clock Cycle Time

Input Clock (K/K; C/C) HIGH

Input Clock (K/K; C/C) LOW

3.0 8.4 3.3 8.4 4.0 8.4 5.0 8.4 6.0 8.4

KHKH

KHKL

KLKH

KHKH

1.20

1.35

–

1.32

1.49

–

1.6

1.8

–

2.0

2.2

–

2.4

2.7

–

K Clock Rise to K Clock Rise and C

to C Rise (rising edge to rising edge)

KHKH

1.30

1.45

1.8

2.2

2.7

K/K Clock Rise to C/C Clock Rise

(rising edge to rising edge)

KHCH

Setup Times

Address Setup to K Clock Rise

0.4

–

0.4

–

0.5

–

0.6

–

0.7

–

AVKH

IVKH

Control Setup to K Clock Rise

(RPS, WPS)

Double Data Rate Control Setup to 0.3

Clock (K/K) Rise

–

0.3

–

0.35

–

0.4

–

0.5

–

SCDDR

IVKH

(BWS , BWS , BWS , BWS )

0.3

Setup to Clock (K/K) Rise

DVKH

[X:0]

Hold Times

0.4

–

0.4

–

0.5

–

0.6

–

0.7

–

Address Hold after K Clock Rise

KHAX

KHIX

Control Hold after K Clock Rise

(RPS, WPS)

Double Data Rate Control Hold after 0.3

Clock (K/K) Rise

–

0.3

–

0.35

–

0.4

–

0.5

–

HCDDR

KHIX

(BWS , BWS , BWS , BWS )

0.3

Hold after Clock (K/K) Rise

KHDX

[X:0]

Notes

23. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is operated

and outputs data with the output timings of that frequency range.

24. This part has a voltage regulator internally; t

is the time that the power must be supplied above V minimum initially before a read or write operation is initiated.

POWER

Document Number: 001-00435 Rev. *E

Page 24 of 31

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Switching Characteristics (continued)

[22, 23]

Over the Operating Range

333 MHz

300 MHz

250 MHz

200 MHz

167 MHz

Cypress Consortium

Description

Unit

Parameter Parameter

Min Max Min Max Min Max Min Max Min Max

Output Times

–

0.45

–

0.45

–

0.45

–

0.45

–

0.50 ns

C/C Clock Rise (or K/K in single

clock mode) to Data Valid

CHQV

–0.45

–0.50

–

Data Output Hold after Output C/C

Clock Rise (Active to Active)

DOH

CHQX

–

0.45

–

0.45

–

0.45

–

0.45

–

0.50 ns

C/C Clock Rise to Echo Clock Valid

CCQO

CQOH

CHCQV

CHCQX

–0.45

–0.50

–

Echo Clock Hold after C/C Clock

Rise

Echo Clock High to Data Valid

Echo Clock High to Data Invalid

0.25

0.27

0.30

0.35

0.40 ns

CQD

CQHQV

CQHQX

CQHCQL

CQHCQH

–0.25

1.25

–

–0.27

1.4

–

–0.30

1.75

–

–0.35

2.25

–

–0.40

2.75

–

CQDOH

CQH

[25]

Output Clock (CQ/CQ) HIGH

CQ Clock Rise to CQ Clock Rise

1.4

CQHCQH

[25]

(rising edge to rising edge)

–

0.45

–

0.45

–

0.45

–

0.45

–

0.50 ns

Clock (C/C) Rise to High-Z

(Active to High-Z)

CHZ

CHQZ

[26, 27]

–0.45

–0.50

–

Clock (C/C) Rise to Low-Z

CLZ

CHQX1

PLL Timing

Clock Phase Jitter

–

0.20

–

0.20

–

0.20

–

0.20

–

0.20 ns

KC Var

PLL Lock Time (K, C)

K Static to PLL Reset

–

μs

KC lock

KC Reset

KC lock

KC Reset

Notes

25. These parameters are extrapolated from the input timing parameters (t

/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by

CYC

design and are not tested in production

26. t

, t

, are specified with a load capacitance of 5 pF as in (b) of AC T e st Loads and Waveforms. Transition is measured ± 100 mV from steady-state voltage.

CHZ CLZ

27. At any voltage and temperature t

is less than t

and t

less than t

CHZ

CLZ

CHZ

Document Number: 001-00435 Rev. *E

Page 25 of 31

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Switching Waveforms

[28, 29, 30]

Figure 5. Read/Write/Deselect Sequence

NOP

WRITE

READ

WRITE

READ

KHKH

CYC

RPS

WPS

D13

D30

D31

D12

D32

D33

D10

Q00

D11

Q20

CQDOH

Q21

Q22

Q01

Q02

Q03

Q23

CHZ

KHCH

CLZ

KHCH

DOH

CQD

KHKH

CYC

CCQO

CQOH

CQH

CCQO

CQHCQH

CQOH

DON’T CARE

UNDEFINED

Notes

28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.

29. Outputs are disabled (High-Z) one clock cycle after a NOP.

30. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note

applies to the whole diagram.

Document Number: 001-00435 Rev. *E

Page 26 of 31

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Ordering Information

The following table lists all possible speed, package, and temperature range options supported for these devices. Note that some

options listed may not be available for order entry. To verify the availability of a specific option, visit the Cypress website at

www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales

representative for the status of availability of parts.

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office

closest to you, visit us at http://app.cypress.com/portal/serve r .pt?space=CommunityPage&control=SetCommunity&CommunityID=

201&PageID=230.

Table 2. Ordering Information

Speed

(MHz)

Package

Diagram

Operating

Range

Ordering Code

Package Type

333 CY7C1511KV18-333BZC

CY7C1526KV18-333BZC

CY7C1513KV18-333BZC

CY7C1515KV18-333BZC

CY7C1511KV18-333BZXC

CY7C1526KV18-333BZXC

CY7C1513KV18-333BZXC

CY7C1515KV18-333BZXC

CY7C1511KV18-333BZI

CY7C1526KV18-333BZI

CY7C1513KV18-333BZI

CY7C1515KV18-333BZI

CY7C1511KV18-333BZXI

CY7C1526KV18-333BZXI

CY7C1513KV18-333BZXI

CY7C1515KV18-333BZXI

300 CY7C1511KV18-300BZC

CY7C1526KV18-300BZC

CY7C1513KV18-300BZC

CY7C1515KV18-300BZC

CY7C1511KV18-300BZXC

CY7C1526KV18-300BZXC

CY7C1513KV18-300BZXC

CY7C1515KV18-300BZXC

CY7C1511KV18-300BZI

CY7C1526KV18-300BZI

CY7C1513KV18-300BZI

CY7C1515KV18-300BZI

CY7C1511KV18-300BZXI

CY7C1526KV18-300BZXI

CY7C1513KV18-300BZXI

CY7C1515KV18-300BZXI

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

Commercial

Industrial

Commercial

Industrial

Document Number: 001-00435 Rev. *E

Page 27 of 31

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Table 2. Ordering Information (continued)

Speed

(MHz)

Package

Diagram

Operating

Range

Ordering Code

Package Type

250 CY7C1511KV18-250BZC

CY7C1526KV18-250BZC

CY7C1513KV18-250BZC

CY7C1515KV18-250BZC

CY7C1511KV18-250BZXC

CY7C1526KV18-250BZXC

CY7C1513KV18-250BZXC

CY7C1515KV18-250BZXC

CY7C1511KV18-250BZI

CY7C1526KV18-250BZI

CY7C1513KV18-250BZI

CY7C1515KV18-250BZI

CY7C1511KV18-250BZXI

CY7C1526KV18-250BZXI

CY7C1513KV18-250BZXI

CY7C1515KV18-250BZXI

200 CY7C1511KV18-200BZC

CY7C1526KV18-200BZC

CY7C1513KV18-200BZC

CY7C1515KV18-200BZC

CY7C1511KV18-200BZXC

CY7C1526KV18-200BZXC

CY7C1513KV18-200BZXC

CY7C1515KV18-200BZXC

CY7C1511KV18-200BZI

CY7C1526KV18-200BZI

CY7C1513KV18-200BZI

CY7C1515KV18-200BZI

CY7C1511KV18-200BZXI

CY7C1526KV18-200BZXI

CY7C1513KV18-200BZXI

CY7C1515KV18-200BZXI