CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
18-Mbit (512K x 36/1M x 18)
Pipelined SRAM
Features
Functional Description
[1]
■ Supports bus operation up to 250 MHz
■ Available speed grades are 250, 200, and 167 MHz
■ Registered inputs and outputs for pipelined operation
■ 3.3V core power supply
The
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive edge triggered clock
input (CLK). The synchronous inputs include all addresses, all
data inputs, address-pipelining chip enable (CE ),
■ 2.5V or 3.3V I/O power supply
1
depth-expansion chip enables (CE and CE
), burst control
2
3
■ Fast clock-to-output times
inputs (ADSC, ADSP, and ADV), write enables (BW , and BWE),
X
❐ 2.6 ns (for 250 MHz device)
and global write (GW). Asynchronous inputs include the output
enable (OE) and the ZZ pin.
■ Provides high performance 3-1-1-1 access rate
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as they are controlled by the advance pin
(ADV).
®
■ User selectable burst counter supporting Intel Pentium inter-
leaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
for further details). Write cycles can be one to two or four bytes
wide as controlled by the byte write control inputs. GW when
active LOW causes all bytes to be written.
■ Asynchronous output enable
■ Single cycle chip deselect
■ CY7C1380D/CY7C1382D is available in JEDEC-standard
Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA
package; CY7C1380F/CY7C1382F is available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non
Pb-free 119-ball BGA and 165-ball FBGA package
The
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
operates from a +3.3V core power supply while all outputs
operate with a +2.5 or +3.3V power supply. All inputs and outputs
are JEDEC-standard and JESD8-5-compatible.
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ ZZ sleep mode option
Selection Guide
Description
Maximum Access Time
250 MHz
200 MHz
3.0
167 MHz
3.4
Unit
ns
2.6
350
70
Maximum Operating Current
300
275
mA
mA
Maximum CMOS Standby Current
70
70
Notes
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.
2. CE CE are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.
3,
2
Cypress Semiconductor Corporation
Document #: 38-05543 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 12, 2009
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Pin Configurations
100-Pin TQFP Pinout (3-Chip Enable)
Figure 1. CY7C1380D, CY7C1380F(512K X 36)
Figure 2. CY7C1382D, CY7C1382F (1M X 18)
Document #: 38-05543 Rev. *F
Page 3 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
119-Ball BGA Pinout
Figure 3. CY7C1380F (512K X 36)
1
2
3
4
5
6
7
V
A
A
A
A
V
DDQ
A
ADSP
ADSC
DDQ
B
C
NC/288M
NC/144M
A
A
A
A
A
A
A
A
NC/576M
NC/1G
V
DD
DQ
DQP
V
NC
CE
V
DQP
DQ
D
E
F
C
C
SS
SS
SS
SS
SS
SS
B
B
DQ
DQ
DQ
V
V
V
V
DQ
DQ
DQ
B
C
C
1
B
V
V
DDQ
OE
ADV
GW
DDQ
C
B
DQ
DQ
DQ
V
BW
V
BW
V
DQ
DQ
V
DQ
G
H
J
C
C
C
C
B
B
B
B
DQ
DQ
C
SS
SS
B
V
NC
V
NC
V
DDQ
DDQ
DD
DD
DD
DQ
DQ
V
CLK
NC
V
DQ
DQ
K
D
D
D
SS
SS
A
A
A
L
M
N
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
BW
BW
D
D
D
A
A
A
D
A
V
V
V
V
V
V
DDQ
BWE
A1
DDQ
SS
SS
SS
SS
DQ
DQ
D
A
P
R
DQ
DQP
A
V
A0
V
DQP
A
DQ
D
D
SS
SS
A
NC
NC
MODE
V
NC
A
NC
DD
T
NC/72M
TMS
A
A
A
NC/36M
NC
ZZ
U
V
TDI
TCK
TDO
V
DDQ
DDQ
Figure 4. CY7C1382F (1M X 18)
2
A
1
3
A
A
A
4
5
A
A
A
6
A
A
A
7
A
B
C
D
E
F
V
V
DDQ
ADSP
ADSC
DDQ
NC/288M
A
NC/576M
NC/1G
NC
NC/144M
A
V
DD
DQ
NC
DQ
V
NC
CE
V
DQP
A
B
SS
SS
SS
SS
SS
SS
NC
V
V
V
V
NC
DQ
DQ
B
A
1
V
NC
DQ
V
OE
ADV
GW
DDQ
A
DDQ
G
H
J
NC
NC
NC
DQ
DQ
BW
V
B
A
B
DQ
NC
V
NC
V
DDQ
B
SS
SS
A
V
V
NC
V
NC
V
DDQ
DD
DD
DD
NC
DQ
V
CLK
NC
V
NC
DQ
DQ
K
L
B
SS
SS
A
DQ
NC
DQ
NC
NC
BW
B
A
A
V
V
V
V
V
NC
DQ
V
DDQ
M
N
P
BWE
A1
DDQ
B
SS
SS
SS
SS
DQ
NC
V
NC
DQ
B
SS
A
NC
DQP
V
A0
NC
B
SS
A
NC
A
A
MODE
A
V
NC
A
A
A
NC
ZZ
R
T
DD
NC/72M
NC/36M
TCK
U
V
TMS
TDI
TDO
NC
V
DDQ
DDQ
Document #: 38-05543 Rev. *F
Page 4 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
165-Ball FBGA Pinout (3-Chip Enable)
Figure 5. CY7C1380D/CY7C1380F (512K x 36)
1
2
3
4
5
6
7
8
9
10
A
11
NC
NC/288M
NC/144M
DQPC
A
B
C
D
CE1
BWC
BWD
VSS
VDD
BWB
BWA
VSS
VSS
CE
ADSC
OE
A
BWE
GW
VSS
VSS
ADV
ADSP
VDDQ
VDDQ
3
A
CE2
VDDQ
VDDQ
CLK
VSS
VSS
A
NC/576M
DQPB
DQB
NC
VSS
VDD
NC/1G
DQB
DQC
DQC
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
NC/72M
TDI
A1
TDO
A0
MODE NC/36M
A
A
TMS
TCK
A
A
A
A
R
Figure 6. CY7C1382D/CY7C1382F (1M x 18)
1
2
A
3
4
5
NC
6
7
8
9
10
A
11
A
NC/288M
NC/144M
NC
A
BWB
NC
CE
CE1
CE2
BWE
GW
VSS
VSS
ADSC
OE
ADV
ADSP
VDDQ
VDDQ
3
NC/576M
A
BWA
VSS
VSS
CLK
VSS
VSS
A
B
C
D
NC
VDDQ
VDDQ
VSS
VDD
VSS
NC/1G
NC
DQPA
DQA
NC
DQB
VDD
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
DQA
DQA
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
NC/72M
TDI
A1
TDO
MODE NC/36M
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05543 Rev. *F
Page 5 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Table 1. Pin Definitions
Name
A , A , A
I/O
Description
Address inputs used to select one of the address locations. Sampled at the rising edge of
Input-
0
1
[2]
Synchronous the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE
are sampled active. A1: A0
1
2
3
are fed to the two-bit counter.
.
BW , BW
Input-
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
A
B
BW , BW
Synchronous Sampled on the rising edge of CLK.
C
D
GW
Input- Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a
Synchronous global write is conducted (all bytes are written, regardless of the values on BW and BWE).
X
BWE
CLK
Input-
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
Input-
Clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
CE
Input-
Synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with
1
CE and CE to select or deselect the device. ADSP is ignored
CE is sampled
if CE is HIGH.
2
3
1
1
only when a new external address is loaded.
CE
CE
Input-
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
2
Synchronous with CE and CE to select or deselect the device. CE is sampled only when a new external
1
3
2
address is loaded.
Input-
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
3
Synchronous CE and CE to select or deselect the device. CE is sampled only when a new external address
1
2
3
is loaded.
Input-
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
OE
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act
as input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
ADV
Input-
Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
Synchronous automatically increments the address in a burst cycle.
ADSP
ADSC
ZZ
Input- Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE is deasserted HIGH.
1
Input-
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
Input-
ZZ sleep input. This active HIGH input places the device in a non-time critical sleep condition
Asynchronous with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull down.
I/O-
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle.
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
DQs, DQP
X
The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP are placed in a tri-state condition.
X
V
V
V
V
Power Supply Power supply inputs to the core of the device.
DD
Ground
Ground for the core of the device.
SS
I/O Ground Ground for the I/O circuitry.
SSQ
DDQ
I/O Power
Supply
Power supply for the I/O circuitry.
Document #: 38-05543 Rev. *F
Page 6 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Table 1. Pin Definitions (continued)
MODE
TDO
TDI
Input-Static Selects burst order. When tied to GND selects linear burst sequence. When tied to V or left
DD
floating selects interleaved burst sequence. This is a strap pin and must remain static during
device operation. Mode pin has an internal pull up.
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
output
feature is not being utilized, this pin must be disconnected. This pin is not available on TQFP
Synchronous packages.
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
input
not being utilized, this pin can be disconnected or connected to V . This pin is not available on
DD
Synchronous TQFP packages.
TMS
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
input
not being utilized, this pin can be disconnected or connected to V . This pin is not available on
DD
Synchronous TQFP packages.
TCK
NC
JTAG-
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be
connected to V . This pin is not available on TQFP packages.
SS
–
No Connects. 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not
internally connected to the die.
Document #: 38-05543 Rev. *F
Page 7 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Single Write Accesses Initiated by ADSP
This access is initiated when both the following conditions are
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
satisfied at clock rise: (1) ADSP is asserted LOW and (2) CE ,
1
CE , and CE are all asserted active. The address presented to
2
3
A is loaded into the address register and the address
advancement logic while being delivered to the memory array.
access delay from the clock rise (t ) is 2.6 ns (250 MHz device).
CO
The
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
The write signals (GW, BWE, and BW ) and ADV inputs are
X
supports secondary cache in systems using a linear or inter-
leaved burst sequence. The interleaved burst order supports
Pentium and i486™ processors. The linear burst sequence suits
processors that use a linear burst sequence. The burst order is
user selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the processor address
strobe (ADSP) or the controller address strobe (ADSC). Address
advancement through the burst sequence is controlled by the
ADV input. A two-bit on-chip wraparound burst counter captures
the first address in a burst sequence and automatically incre-
ments the address for the rest of the burst access.
ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
then the write operation is controlled by BWE and BW signals.
X
The
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
provides byte write capability that is described in the write cycle
descriptions table. Asserting the byte write enable input (BWE)
with the selected byte write (BW ) input, selectively writes to only
X
Byte write operations are qualified with the byte write enable
the desired bytes. Bytes not selected during a byte write
operation remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
(BWE) and byte write select (BW ) inputs. A global write enable
X
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a
common I/O device, the output enable (OE) must be deserted
HIGH before presenting data to the DQs inputs. Doing so
tri-states the output drivers. As a safety precaution, DQs are
automatically tri-stated whenever a write cycle is detected,
regardless of the state of OE.
Three synchronous chip selects (CE , CE , CE ) and an
1
2
3
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE is
1
HIGH.
Single Read Accesses
Single Write Accesses Initiated by ADSC
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted
HIGH, (3) CE , CE , and CE are all asserted active, and (4) the
(2)
CE , CE , CE are all asserted active, and (3) the write
1
2
3
1
2
3
appropriate combination of the write inputs (GW, BWE, and
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
BW ) are asserted active to conduct a write to the desired
X
CE is HIGH. The address presented to the address inputs (A)
1
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a byte write is conducted, only the selected bytes
are written. Bytes not selected during a byte write operation
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
is stored into the address advancement logic and the address
register while being presented to the memory array. The corre-
sponding data is enabled to propagate to the input of the output
registers. At the rising edge of the next clock, the data is enabled
to propagate through the output register and onto the data bus
within 2.6 ns (250 MHz device) if OE is active LOW. The only
exception occurs when the SRAM is emerging from a deselected
state to a selected state; its outputs are always tri-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE signal. Consecutive single
read cycles are supported. Once the SRAM is deselected at
clock rise by the chip select and either ADSP or ADSC signals,
its output tri-states immediately.
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a
common I/O device, the output enable (OE) must be deserted
HIGH before presenting data to the DQs inputs. Doing so
tri-states the output drivers. As a safety precaution, DQs are
automatically tri-stated whenever a write cycle is detected,
regardless of the state of OE.
Document #: 38-05543 Rev. *F
Page 8 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Table 2. Interleaved Burst Address Table (MODE = Floating
or VDD)
Burst Sequences
The
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
provides a two-bit wraparound counter, fed by A1: A0, that imple-
ments an interleaved or a linear burst sequence. The interleaved
burst sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
Table 3. Linear Burst Address Table (MODE = GND)
Sleep Mode
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
deselected prior to entering the sleep mode. CE , CE , CE ,
1
2
3
ADSP, and ADSC must remain inactive for the duration of t
ZZREC
after the ZZ input returns LOW.
Table 4. ZZ Mode Electrical Characteristics
Parameter
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
Min
Max
80
Unit
mA
ns
I
t
t
t
t
ZZ > V – 0.2V
DD
DDZZ
ZZ > V – 0.2V
2t
ZZS
DD
CYC
ZZ recovery time
ZZ < 0.2V
2t
ns
ZZREC
ZZI
CYC
ZZ Active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2t
ns
CYC
0
ns
RZZI
Document #: 38-05543 Rev. *F
Page 9 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Truth Table
The Truth Table for this data sheet follows.
Operation
Add. Used CE
CE
X
L
CE
X
X
H
X
H
X
L
ZZ ADSP ADSC ADV WRITE OE CLK
DQ
1
2
3
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Sleep Mode, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
None
None
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L
L
None
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
L
X
X
X
L
X
Tri-State
Q
External
External
External
External
External
Next
L-H
L
L
L
H
X
L
L-H Tri-State
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
L
L
L
H
H
H
H
H
H
L
L
L
L
H
L
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H Tri-State
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H Tri-State
L-H
L-H Tri-State
Q
H
X
X
L-H
L-H
D
D
L
Notes
4. X = Don't Care, H = Logic HIGH, L = Logic LOW.
5. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
6. The DQ pins are controlled by the current cycle and the signal. is asynchronous and is not sampled with the clock.
OE
OE
must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks
X
after the
or with the assertion of
. As a result,
ADSC
is a
OE
OE
ADSP
don't care for the remainder of the write cycle.
8.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when
is
OE
OE
.
is active (LOW)
inactive or when the device is deselected, and all data bits behave as output when
OE
Document #: 38-05543 Rev. *F
Page 10 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Function (CY7C1380D/CY7C1380F)
GW
BWE
BW
BW
BW
BW
A
D
C
B
Read
Read
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
H
H
H
H
H
H
H
H
L
X
H
H
H
H
L
X
H
H
L
X
H
L
Write Byte A – (DQ and DQP )
A
A
Write Byte B – (DQ and DQP )
H
L
B
B
Write Bytes B, A
Write Byte C – (DQ and DQP )
L
H
H
L
H
L
C
C
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
L
L
H
L
L
L
Write Byte D – (DQ and DQP )
H
H
H
H
L
H
H
L
H
L
D
D
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
L
L
H
L
L
L
L
H
H
L
H
L
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
L
L
L
L
H
L
L
L
L
Write All Bytes
X
X
X
X
Function (CY7C1382D/CY7C1382F)
GW
BWE
BW
BW
A
B
Read
Read
H
H
H
H
H
H
L
H
L
L
L
L
L
X
X
H
H
L
X
H
L
Write Byte A – (DQ and DQP )
A
A
Write Byte B – (DQ and DQP )
H
L
B
B
Write Bytes B, A
Write All Bytes
Write All Bytes
L
L
L
X
X
Note
9. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write is done based on which byte write is active.
X
Document #: 38-05543 Rev. *F
Page 11 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Test Data-In (TDI)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an appli-
cation. TDI is connected to the most significant bit (MSB) of any
The CY7C1380D/CY7C1382D incorporates a serial boundary
scan test access port (TAP).This part is fully compliant with
1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V
I/O logic levels.
The CY7C1380D/CY7C1382D contains a TAP controller,
instruction register, boundary scan register, bypass register, and
ID register.
Test Data-Out (TDO)
Disabling the JTAG Feature
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V ) to prevent clocking of the device. TDI and TMS are inter-
SS
nally pulled up and may be unconnected. They may alternately
be connected to V through a pull up resistor. TDO must be left
unconnected. Upon power up, the device comes up in a reset
state which does not interfere with the operation of the device.
DD
TAP Controller Block Diagram
0
TAP Controller State Diagram
Bypass Register
TEST-LOGIC
1
2
1
0
0
0
RESET
0
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
election
S
TDI
TDO
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
Circuitr
y
.
.
.
2
1
0
0
1
1
CAPTURE-DR
CAPTURE-IR
x
.
.
.
.
.
2
1
0
0
Boundary Scan Register
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
TCK
EXIT1-DR
EXIT1-IR
TMS
TAP CONTROLLER
0
0
PAUSE-DR
1
0
PAUSE-IR
1
0
0
0
Performing a TAP Reset
EXIT2-DR
1
EXIT2-IR
1
A Reset is performed by forcing TMS HIGH (V ) for five rising
DD
edges of TCK. This Reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
UPDATE-DR
UPDATE-IR
1
0
1
0
At power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
The 0 or 1 next to each state represents the value of TMS at the
rising edge of TCK.
Registers are connected between the TDI and TDO balls and
enable data to be scanned in and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
Upon power up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Document #: 38-05543 Rev. *F
Page 12 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board-level serial test data path.
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This enables data to be shifted through the
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. The SAMPLE Z command places
all SRAM outputs into a High-Z state.
SRAM with minimal delay. The bypass register is set LOW (V
when the BYPASS instruction is executed.
)
SS
Boundary Scan Register
SAMPLE/PRELOAD
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The TAP controller clock can only operate at a frequency up to
20 MHz, while the SRAM clock operates more than an order of
magnitude faster. As there is a large difference in the clock
frequencies, it is possible that during the Capture-DR state, an
input or output undergoes a transition. The TAP may then try to
capture a signal while in transition (metastable state). This does
not harm the device, but there is no guarantee as to the value
that is captured. Repeatable results may not be possible.
The boundary scan order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
The ID register is loaded with a vendor-specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the “Identification Register Definitions”
times (t and t ). The SRAM clock input might not be captured
CS
CH
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK# captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
TAP Instruction Set
Overview
PRELOAD enables an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in “Identification
RESERVED and must not be used. The other five instructions
are described in detail in this section.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required; that is, while data captured is
shifted out, the preloaded data is shifted in.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller must be
moved into the Update-IR state.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the Shift-DR controller state.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at Bit #85
(for 119-BGA package) or Bit #89 (for 165-fBGA package). When
this scan cell, called the “extest output bus tri-state,” is latched
into the preload register during the Update-DR state in the TAP
controller, it directly controls the state of the output (Q-bus) pins,
IDCODE
The IDCODE instruction causes a vendor-specific 32-bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and enables
Document #: 38-05543 Rev. *F
Page 13 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
when the EXTEST is entered as the current instruction. When
HIGH, it enables the output buffers to drive the output bus. When
LOW, this bit places the output bus into a High-Z condition.
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
Test Clock
(TCK)
t
t
t
TH
CYC
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range
Parameter
Clock
Description
Min
Max
Unit
t
t
t
t
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
TCYC
TF
20
20
20
TH
ns
TL
Output Times
t
t
TCK Clock LOW to TDO Valid
10
ns
ns
TDOV
TCK Clock LOW to TDO Invalid
0
TDOX
Setup Times
t
t
t
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
ns
ns
ns
TMSS
TDIS
CS
Hold Times
t
t
t
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
TMSH
TDIH
CH
Capture Hold after Clock Rise
Notes
10. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
11. Test conditions are specified using the load in TAP AC test conditions. t /t = 1ns.
R
F
Document #: 38-05543 Rev. *F
Page 14 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels.................................................V to 3.3V
Input pulse levels.................................................V to 2.5V
SS
SS
Input rise and fall times....................................................1 ns
Input timing reference levels...........................................1.5V
Output reference levels ..................................................1.5V
Test load termination supply voltage ..............................1.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels................... ......................1.25V
Output reference levels .................. ..............................1.25V
Test load termination supply voltage .................... ........1.25V
Figure 7. 3.3V TAP AC Output Load Equivalent
Figure 8. 2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50 Ω
20pF
ZO= 50 Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; V = 3.3V ±0.165V unless otherwise noted)
DD
Parameter
Description
Test Conditions
Min
2.4
2.0
2.9
2.1
Max
Unit
V
V
V
V
V
V
V
Output HIGH Voltage
I
I
I
= –4.0 mA, V
= –1.0 mA, V
= –100 µA
= 3.3V
= 2.5V
OH1
OH
OH
OH
DDQ
DDQ
V
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
V
OH2
OL1
OL2
IH
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
I
I
= 8.0 mA
= 100 µA
0.4
0.4
0.2
0.2
V
OL
OL
V
V
V
2.0
1.7
V
V
+ 0.3
V
DD
DD
+ 0.3
V
–0.3
–0.3
–5
0.8
V
IL
0.7
5
V
I
GND < V < V
DDQ
µA
X
IN
Note
12. All voltages referenced to VSS (GND).
Document #: 38-05543 Rev. *F
Page 15 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Identification Register Definitions
CY7C1380D/CY7C1380F CY7C1382D/CY7C1382F
Instruction Field
Description
(512K x 36)
(1 Mbit x 18)
Revision Number (31:29)
000
000
Describes the version number.
Reserved for internal use.
Device Depth (28:24)
01011
01011
Device Width (23:18) 119-BGA
Device Width (23:18) 165-FBGA
101000
101000
Defines the memory type and
architecture.
000000
000000
Defines the memory type and
architecture.
Cypress Device ID (17:12)
100101
010101
Defines the width and density.
Cypress JEDEC ID Code (11:1)
00000110100
00000110100
Allows unique identification of
SRAM vendor.
ID Register Presence Indicator (0)
1
1
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Instruction
Bypass
ID
3
3
1
1
32
85
89
32
85
89
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball FBGA package)
Identification Codes
Instruction
EXTEST
Code
Description
000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011 Do Not Use. This instruction is reserved for future use.
SAMPLE/PRELOAD
100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101 Do Not Use. This instruction is reserved for future use.
110 Do Not Use. This instruction is reserved for future use.
111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
13. Bit #24 is 1 in the register definitions for both 2.5v and 3.3v versions of this device.
Document #: 38-05543 Rev. *F
Page 16 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Bit #
1
Ball ID
Bit #
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Ball ID
F6
Bit #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Ball ID
G4
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
Bit #
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Ball ID
L1
H4
T4
T5
T6
R5
L5
R6
U6
R7
T7
P6
N7
M6
L7
K6
P7
N6
L6
K7
J5
2
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
B6
D4
B4
F4
M2
N1
3
4
P1
5
K1
6
L2
7
N2
P2
8
9
R3
10
11
12
13
14
15
16
17
18
19
20
21
22
T1
R1
T2
L3
R2
G1
H2
D1
E2
G2
H1
J3
T3
L4
N4
P4
M4
A5
K4
E4
Internal
H6
G7
2K
Notes
14. Balls which are NC (No Connect) are pre-set LOW.
15. Bit# 85 is pre-set HIGH.
Document #: 38-05543 Rev. *F
Page 17 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Bit #
1
Ball ID
N6
Bit #
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Ball ID
D10
C11
A11
B11
A10
B10
A9
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
G1
D2
E2
2
N7
3
N10
P11
P8
4
F2
5
G2
H1
H3
J1
6
R8
7
R9
8
P9
B9
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
C10
A8
K1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
L1
B8
M1
J2
A7
B7
K2
B6
L2
A6
M2
N1
N2
P1
B5
A5
A4
B4
R1
R2
P3
B3
A3
A2
R3
P2
H10
G11
F11
E11
D11
G10
F10
E10
B2
C2
R4
P4
B1
A1
N5
P6
C1
D1
R6
Internal
E1
F1
Note
16. Bit# 89 is pre-set HIGH.
Document #: 38-05543 Rev. *F
Page 18 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
DC Input Voltage ................................... –0.5V to V + 0.5V
Maximum Ratings
DD
Current into Outputs (LOW)......................................... 20 mA
Exceeding the maximum ratings may impair the useful life of the
device. For user guidelines, not tested.
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-up Current..................................................... >200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Supply Voltage on V Relative to GND ........–0.3V to +4.6V
DD
Ambient
Range
V
V
DDQ
DD
Temperature
Supply Voltage on V
Relative to GND...... –0.3V to +V
DD
DDQ
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5%
DC Voltage Applied to Outputs
in Tri-State ...........................................–0.5V to V
to V
+ 0.5V
DD
Industrial
–40°C to +85°C
DDQ
Electrical Characteristics Over the Operating Range
Parameter
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min
3.135
3.135
2.375
2.4
Max
Unit
V
V
3.6
DD
V
V
V
V
V
I
for 3.3V I/O
for 2.5V I/O
V
V
DDQ
DD
2.625
V
Output HIGH Voltage
Output LOW Voltage
for 3.3V I/O, I = –4.0 mA
V
OH
OL
IH
OH
for 2.5V I/O, I = –1.0 mA
2.0
V
OH
for 3.3V I/O, I = 8.0 mA
0.4
0.4
V
OL
for 2.5V I/O, I = 1.0 mA
V
OL
Input HIGH Voltage
Input LOW Voltage
for 3.3V I/O
for 2.5V I/O
for 3.3V I/O
for 2.5V I/O
GND ≤ V ≤ V
2.0
1.7
V
V
+ 0.3V
V
DD
+ 0.3V
V
DD
–0.3
–0.3
–5
0.8
V
IL
0.7
5
V
Input Leakage Current
except ZZ and MODE
μA
X
I
DDQ
Input Current of MODE Input = V
Input = V
–30
–5
μA
μA
μA
μA
μA
SS
DD
SS
DD
5
Input Current of ZZ
Input = V
Input = V
30
5
I
I
Output Leakage Current GND ≤ V ≤ V
Output Disabled
–5
OZ
I
DDQ,
V
Operating Supply
V
f = f
= Max., I
= 0 mA,
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speeds
350
300
275
160
150
140
70
mA
mA
mA
mA
mA
mA
mA
DD
DD
DD
OUT
= 1/t
MAX CYC
Current
I
Automatic CE
Power Down
Current—TTL Inputs
V = Max, Device Deselected,
DD
SB1
V
≥ V or V ≤ V
IN
IH
IN
IL
f = f
= 1/t
MAX CYC
I
I
Automatic CE Power
Down Current-CMOS
Inputs
V = Max, Device Deselected,
DD
SB2
V
≤ 0.3V or V > V – 0.3V, f = 0
IN
IN
DDQ
Automatic CE
Power Down
Current—CMOS Inputs f = f
V
V
= Max, Device Deselected, or 4.0-ns cycle, 250 MHz
135
130
125
80
mA
mA
mA
mA
SB3
DD
≤ 0.3V or V > V
– 0.3V
IN
IN
DDQ
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speeds
= 1/t
MAX
CYC
I
Automatic CE
V = Max, Device Deselected,
DD
SB4
Power Down
Current—TTL Inputs
V
≥ V or V ≤ V , f = 0
IN
IH IN IL
Notes
17. Overshoot: V (AC) < V +1.5V (pulse width less than t
/2), undershoot: V (AC) > –2V (pulse width less than t /2).
CYC
IH
DD
CYC
IL
18. TPower up: Assumes a linear ramp from 0v to V (min.) within 200 ms. During this time V < V and V
< V
.
DD
IH
DD
DDQ
DD
Document #: 38-05543 Rev. *F
Page 19 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Capacitance [19]
100 TQFP
Package
119 BGA
Package
165 FBGA
Package
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Unit
C
Input Capacitance
5
5
5
8
8
8
9
9
9
pF
pF
pF
IN
A
V
= 3.3V.
= 2.5V
DD
C
C
Clock Input Capacitance
Input/Output Capacitance
CLK
IO
V
DDQ
Thermal Resistance [19]
100 TQFP
Package
119 BGA
Package
165 FBGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, in accordance with
EIA/JESD51.
28.66
23.8
20.7
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
4.08
6.2
4.0
°C/W
Document #: 38-05543 Rev. *F
Page 20 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Figure 9. AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
R = 317Ω
3.3V
ALL INPUT PULSES
VDDQ
OUTPUT
90%
Z = 50Ω
90%
0
R = 50Ω
10%
10%
≤ 1 ns
L
GND
5 pF
R = 351Ω
≤ 1 ns
V = 1.5V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R = 1538Ω
≤ 1 ns
≤ 1 ns
V = 1.25V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note
19. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05543 Rev. *F
Page 21 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Switching Characteristics Over the Operating Range
250 MHz
200 MHz
167 MHz
Min Max
Description
Parameter
Unit
Min
Max
Min
Max
t
V
(Typical) to the first Access
1
1
1
ms
POWER
DD
Clock
t
t
t
Clock Cycle Time
Clock HIGH
4.0
1.7
1.7
5
6
ns
ns
ns
CYC
CH
2.0
2.0
2.2
2.2
Clock LOW
CL
Output Times
t
t
t
t
t
t
t
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
2.6
3.0
3.4
ns
ns
ns
ns
ns
ns
ns
CO
1.0
1.0
1.3
1.3
1.3
1.3
DOH
CLZ
Clock to Low-Z
Clock to High-Z
2.6
2.6
3.0
3.0
3.4
3.4
CHZ
OEV
OELZ
OEHZ
OE LOW to Output Valid
OE LOW to Output Low-Z
OE HIGH to Output High-Z
0
0
0
2.6
3.0
3.4
Setup Times
t
t
t
t
t
t
Address Setup Before CLK Rise
ADSC, ADSP Setup Before CLK Rise
ADV Setup Before CLK Rise
1.2
1.2
1.2
1.2
1.2
1.2
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
AS
ADS
ADVS
WES
DS
GW, BWE, BW Setup Before CLK Rise
X
Data Input Setup Before CLK Rise
Chip Enable SetUp Before CLK Rise
CES
Hold Times
t
t
t
t
t
t
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
AH
ADH
ADVH
WEH
DH
GW, BWE, BW Hold After CLK Rise
X
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
CEH
Notes
20. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
22. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially before a read or write operation
POWER
DD
can be initiated.
23. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of “AC Test Loads and Waveforms” on page 21. Transition is measured ± 200
CHZ CLZ OELZ
OEHZ
mV from steady-state voltage.
24. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
25. This parameter is sampled and not 100% tested.
Document #: 38-05543 Rev. *F
Page 22 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Switching Waveforms
Figure 10. Read Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,
BWx
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV
suspends
burst.
t
t
OEV
CO
t
t
OEHZ
t
t
CHZ
OELZ
DOH
t
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
26. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05543 Rev. *F
Page 23 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Switching Waveforms (continued)
Figure 11. Write Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
ADDRESS
BWE,
t
t
AH
AS
A1
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BW
X
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
Data In (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
ata Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Note
27.
.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW
X
Document #: 38-05543 Rev. *F
Page 24 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Switching Waveforms (continued)
Figure 12. Read/Write Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
BWE,
t
t
WEH
WES
BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
D(A3)
D(A5)
D(A6)
t
t
CLZ
OEHZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
High-Z
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
Notes
28. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
29. GW is HIGH.
Document #: 38-05543 Rev. *F
Page 25 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Switching Waveforms (continued)
Figure 13. ZZ Mode Timing
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
30. Device must be deselected when entering ZZ mode. See “Truth Table” on page 10 for all possible signal conditions to deselect the device.
31. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05543 Rev. *F
Page 26 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Ordering Information
The following table lists all speed, package and temperature range options. Please note that some options listed below may not
be available for order entry. To verify the availability of a specific option, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products, or contact your local sales representative for the status of
availability of parts.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the
office closest to you, visit us at http://app.cypress.com/portal/server.pt?space=CommunityPage&control=SetCom-
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
CY7C1380D-250AXC
CY7C1382D-250AXC
CY7C1380F-250AXC
CY7C1382F-250AXC
CY7C1380F-250BGC
CY7C1382F-250BGC
250
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1380F-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1382F-250BGXC
CY7C1380D-250BZC
CY7C1382D-250BZC
CY7C1380F-250BZC
CY7C1382F-250BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1380D-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1382D-250BZXC
CY7C1380F-250BZXC
CY7C1382F-250BZXC
CY7C1380D-250AXI
CY7C1382D-250AXI
CY7C1380F-250AXI
CY7C1382F-250AXI
CY7C1380F-250BGI
CY7C1382F-250BGI
CY7C1380F-250BGXI
CY7C1382F-250BGXI
CY7C1380D-250BZI
CY7C1382D-250BZI
CY7C1380F-250BZI
CY7C1382F-250BZI
CY7C1380D-250BZXI
CY7C1382D-250BZXI
CY7C1380F-250BZXI
CY7C1382F-250BZXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Industrial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Document #: 38-05543 Rev. *F
Page 27 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Speed
(MHz)
Package
Diagram
Operating
Part and Package Type
Ordering Code
CY7C1380D-200AXC
CY7C1382D-200AXC
CY7C1380F-200AXC
CY7C1382F-200AXC
CY7C1380F-200BGC
CY7C1382F-200BGC
Range
200
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1380F-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1382F-200BGXC
CY7C1380D-200BZC
CY7C1382D-200BZC
CY7C1380F-200BZC
CY7C1382F-200BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1380D-200BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1382D-200BZXC
CY7C1380F-200BZXC
CY7C1382F-200BZXC
CY7C1380D-200AXI
CY7C1382D-200AXI
CY7C1380F-200AXI
CY7C1382F-200AXI
CY7C1380F-200BGI
CY7C1382F-200BGI
CY7C1380F-200BGXI
CY7C1382F-200BGXI
CY7C1380D-200BZI
CY7C1382D-200BZI
CY7C1380F-200BZI
CY7C1382F-200BZI
CY7C1380D-200BZXI
CY7C1382D-200BZXI
CY7C1380F-200BZXI
CY7C1382F-200BZXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Industrial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Document #: 38-05543 Rev. *F
Page 28 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Speed
(MHz)
Package
Diagram
Operating
Part and Package Type
Ordering Code
CY7C1380D-167AXC
CY7C1382D-167AXC
CY7C1380F-167AXC
CY7C1382F-167AXC
CY7C1380F-167BGC
CY7C1382F-167BGC
Range
167
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1380F-167BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1382F-167BGXC
CY7C1380D-167BZC
CY7C1382D-167BZC
CY7C1380F-167BZC
CY7C1382F-167BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1380D-167BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1382D-167BZXC
CY7C1380F-167BZXC
CY7C1382F-167BZXC
CY7C1380D-167AXI
CY7C1382D-167AXI
CY7C1380F-167AXI
CY7C1382F-167AXI
CY7C1380F-167BGI
CY7C1382F-167BGI
CY7C1380F-167BGXI
CY7C1382F-167BGXI
CY7C1380D-167BZI
CY7C1382D-167BZI
CY7C1380F-167BZI
CY7C1382F-167BZI
CY7C1380D-167BZXI
CY7C1382D-167BZXI
CY7C1380F-167BZXI
CY7C1382F-167BZXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Industrial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Document #: 38-05543 Rev. *F
Page 29 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Package Diagrams
Figure 14. 100-Pin Thin Plastic Quad Flat Pack (14 x 20 x 1.4 mm) (51-85050)
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
1.00 REF.
0.20 MIN.
51-85050-*B
DETAIL
A
Document #: 38-05543 Rev. *F
Page 30 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Package Diagrams (continued)
Figure 15. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
Document #: 38-05543 Rev. *F
Page 31 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Package Diagrams (continued)
Figure 16. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)
BOTTOM VIEW
PIN 1 CORNER
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
-0.06
Ø0.50
(165X)
+0.14
1
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
A
B
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00
5.00
10.00
13.00 0.10
B
B
13.00 0.10
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDECREFERENCE: MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
SEATING PLANE
C
51-85180-*A
Document #: 38-05543 Rev. *F
Page 32 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Document History Page
Document Title: CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F, 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
Document Number: 38-05543
Submission Orig. of
REV. ECN NO.
Description of Change
Date
Change
**
254515
288531
See ECN
See ECN
RKF
New data sheet
*A
SYT
Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
non-compliance with 1149.1
Removed 225MHz and 133 MHz Speed Bins
Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA Packages
Added comment of ‘Pb-free BG packages availability’ below the Ordering Infor-
mation
*B
326078
See ECN
PCI
Address expansion pins/balls in the pinouts for all packages are modified as per
JEDEC standard
Added description on EXTEST Output Bus Tri-State
Changed description on the Tap Instruction Set Overview and Extest
Changed Device Width (23:18) for 119-BGA from 000000 to 101000
Added separate row for 165 -FBGA Device Width (23:18)
Changed Θ and Θ for TQFP Package from 31 and 6 °C/W to 28.66 and 4.08
JA
JC
°C/W respectively
Changed Θ and Θ for BGA Package from 45 and 7 °C/W to 23.8 and 6.2 °C/W
JA
JC
respectively
Changed Θ and Θ for FBGA Package from 46 and 3 °C/W to 20.7 and 4.0 °C/W
JA
JC
respectively
Modified V
V
test conditions
OL, OH
Removed comment of ‘Pb-free BG packages availability’ below the Ordering Infor-
mation
Updated Ordering Information Table
*C
416321
See ECN
NXR
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Changed the description of I from Input Load Current to Input Leakage Current on
X
page# 18
Changed the I current values of MODE on page # 18 from –5 μA and 30 μA
X
to –30 μA and 5 μA
Changed the I current values of ZZ on page # 18 from –30 μA and 5 μA
X
to –5 μA and 30 μA
Changed V < V to V < V on page # 18
IH
DD
IH
DD
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
*D
475009
See ECN
VKN
VKN
Added the Maximum Rating for Supply Voltage on V
Relative to GND
DDQ
Changed t , t from 25 ns to 20 ns and t
from 5 ns to 10 ns in TAP AC
TH TL
TDOV
Switching Characteristics table.
Updated the Ordering Information table.
*E
*F
776456
See ECN
01/27/09
Added Part numbers CY7C1380F and CY7C1382F and its related information
Added footnote# 3 regarding Chip Enable
Updated Ordering Information table
2648065
VKN/PYRS Modified note on top of the Ordering information table
Updated Ordering Information table to include CY7C1380F/CY7C1382F in 100-Pin
TSOP and 165 BGA package
Document #: 38-05543 Rev. *F
Page 33 of 34
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05543 Rev. *F
Revised January 12, 2009
Page 34 of 34
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