Cypress NoBL CY7C1460AV25 User Manual

CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

36-Mbit (1M x 36/2M x 18/512K x 72)

Pipelined SRAM with NoBL™ Architecture

Functional Description

Features

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states

— Available speed grades are 250, 200 and 167 MHz

The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are

2.5V, 1M x 36/2M x 18/512 x 72 Synchronous pipelined burst

SRAMs with No Bus Latency™ (NoBL™) logic, respectively.

They are designed to support unlimited true back-to-back

Read/Write operations with no wait states. The

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

CY7C1460AV25/CY7C1462AV25/CY7C1464AV25

are

equipped with the advanced (NoBL) logic required to enable

consecutive Read/Write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data in systems that require frequent

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write capability

• 2.5V core power supply

Write/Read

transitions.

The

CY7C1460AV25/CY7C1462AV25/CY7C1464AV25

pin-compatible and functionally equivalent to ZBT devices.

are

• 2.5V/1.8V I/O power supply

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which when deasserted suspends operation and extends the

previous clock cycle. Write operations are controlled by the

• CY7C1460AV25, CY7C1462AV25 available in

JEDEC-standard lead-free 100-pin TQFP package,

lead-free and non-lead-free 165-ball FBGA package.

CY7C1464AV25 available in lead-free and non-lead-free

209-ball FBGA package

Byte Write Selects (BW –BW

for CY7C1464AV25,

BW –BW

for CY7C1460AV25 and BW –BW for

CY7C1462AV25) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst capability—linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

Three synchronous Chip Enables (CE , CE , CE ) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Logic Block Diagram–CY7C1460AV25 (1M x 36)

ADDRESS

A0, A1, A

A1'

A0'

BURST

LOGIC

MODE

ADV/LD

CLK

CEN

WRITE ADDRESS

ADV/LD

BWa

BWb

BWc

BWd

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

MEMORY

ARRAY

DQs

WRITE

DRIVERS

DQP^a

DQPb

DQPc

DQPd

INPUT

READ LOGIC

CE1

CE2

CE3

SLEEP

CONTROL

Cypress Semiconductor Corporation

Document #: 38-05354 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 22, 2006

[+] Feedback

CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Pin Configurations

100-pin TQFP Pinout

DQPc

DQc

DDQ

DQPb

DQb

DDQ

DQP

DQa

DDQ

DQc

DQb

DQc

DDQ

DQa

DDQ

DQc

DQb

CY7C1460AV25

(1M × 36)

CY7C1462AV25

(2M × 18)

DQa

DQd

DQb

DQa

DQd

DDQ

DQa

DDQ

DQd

DQa

DQb

DQa DQPb

DQa

DDQ

DQd

DQPd

DQa

DQPa

Document #: 38-05354 Rev. *D

Page 3 of 27

[+] Feedback

CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Pin Configurations (continued)

165-ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1460AV25 (1M × 36)

NC/576M

NC/1G

DQP_c

ADV/LD

CE₁

CE2

BW_c

BW_d

V_SS

V_DD

BW_b

BW_a

V_SS

CEN

CLK

V_SS

V_DD

DQ_c

V_DDQ

V_SS

V_DDQ

DQ_b

DQP_b

DQ_b

DQ_c

V_DDQ

V_DD

V_SS

V_DD

V_DDQ

DQ_b

DQ_d

V_DDQ

DQ_a

DQ_d

V_DDQ

V_DD

V_SS

V_DD

V_SS

V_DDQ

DQ_a

DQP_a

DQP_d

NC/144M NC/72M

TDI

TDO

NC/288M

MODE

TMS

TCK

CY7C1462AV25 (2M × 18)

NC/576M

NC/1G

CE₁

CE2

BW_b

CEN

ADV/LD

BW_a

V_SS

CLK

V_SS

V_DD

DQ_b

V_DDQ

V_SS

V_DD

V_DDQ

DQP_a

DQ_a

DQ_b

V_DDQ

V_DD

V_SS

V_DD

V_DDQ

DQ_a

DQ_b

V_DDQ

DQ_a

DQ_b

V_DDQ

V_DD

V_SS

V_DD

V_SS

V_DDQ

DQ_a

DQP_b

NC/144M NC/72M

TDI

TDO

NC/288M

MODE

TMS

TCK

Document #: 38-05354 Rev. *D

Page 4 of 27

[+] Feedback

CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Pin Configurations (continued)

209-ball FBGA (14 x 22 x 1.76 mm) Pinout

CY7C1464AV25 (512K x 72)

DQb

DQg

ADV/LD

DQb

DQPb

DQf

BWS

DQb

BWS

DQg

DQPc

DQc

DQg

NC/576M

BWS

NC/1G

DQb

DQPg

DQc

DDQ

DQPf

DQf

CEN

DQc

DDQ

DQf

DDQ

DQf

DDQ

DQc

DQf

DQc

DDQ

DQf

CLK

DQh

DDQ

DQa

DDQ

DQh

DQa

DDQ

DQh

DQPd

DQd

DDQ

DQa

DQPa

DQe

DQPh

DQd

DDQ

DQPe

DQe

MODE

NC/72M

NC/288M

NC/144M

DQd

DQe

TDI

TDO

TCK

TMS

Pin Definitions

Pin Name

I/O Type

Pin Description

Input-

Synchronous

Address Inputs used to select one of the address locations. Sampled at the rising edge of

the CLK.

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.

Sampled on the rising edge of CLK. BW controls DQ and DQP , BW controls DQ and DQP ,

BW controls DQ and DQP , BW controls DQ and DQP , BW controls DQ and DQP BW

e, f

controls DQ and DQP BW controls DQ and DQP BW controls DQ and DQP .

f, g,

Input-

Synchronous

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This

signal must be asserted LOW to initiate a write sequence.

ADV/LD

Input-

Synchronous

Advance/Load Input used to advance the on-chip address counter or load a new address.

When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a

new address can be loaded into the device for an access. After being deselected, ADV/LD should

be driven LOW in order to load a new address.

CLK

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.

CLK is only recognized if CEN is active LOW.

Document #: 38-05354 Rev. *D

Page 5 of 27

[+] Feedback

CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Pin Definitions (continued)

Pin Name

I/O Type

Pin Description

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE and CE to select/deselect the device.

Input-

Synchronous

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

CE and CE to select/deselect the device.

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE and CE to select/deselect the device.

Input-

Output Enable, active LOW. Combined with the synchronous logic block inside the device to

Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.

When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during

the data portion of a write sequence, during the first clock when emerging from a deselected state

and when the device has been deselected.

CEN

Input-

Synchronous

Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the

SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not

deselect the device, CEN can be used to extend the previous cycle when required.

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by A during the previous clock rise of the read cycle. The direction of the pins is

controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave

as outputs. When HIGH, DQ –DQ are placed in a tri-state condition. The outputs are automati-

cally tri-stated during the data portion of a write sequence, during the first clock when emerging

from a deselected state, and when the device is deselected, regardless of the state of OE.

DQP

I/O-

Synchronous

Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ

. During

[31:0]

write sequences, DQP is controlled by BW , DQP is controlled by BW , DQP is controlled by

BW , and DQP is controlled by BW , DQP is controlled by BW , DQP is controlled by BW ,

DQP is controlled by BW , DQP is controlled by BW .

DQP

MODE

Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.

Pulled LOW selects the linear burst order. MODE should not change states during operation.

When left floating MODE will default HIGH, to an interleaved burst order.

TDO

TDI

JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

Synchronous

JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.

Synchronous

TMS

Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.

Synchronous

TCK

JTAG-Clock

Clock input to the JTAG circuitry.

Power Supply Power supply inputs to the core of the device.

I/O Power Supply Power supply for the I/O circuitry.

DDQ

Ground

N/A

Ground for the device. Should be connected to ground of the system.

No connects. This pin is not connected to the die.

NC/72M

N/A

Not connected to the die. Can be tied to any voltage level.

NC/144M

NC/288M

NC/576M

NC/1G

N/A

Not connected to the die. Can be tied to any voltage level.

N/A

Not connected to the die. Can be tied to any voltage level.

N/A

Not connected to the die. Can be tied to any voltage level.

Input-

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition

Asynchronous with data integrity preserved. During normal operation, this pin has to be LOW or left floating.

ZZ pin has an internal pull-down.

Document #: 38-05354 Rev. *D

Page 6 of 27

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CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Functional Overview

the internal burst counter regardless of the state of chip

enables inputs or WE. WE is latched at the beginning of a burst

cycle. Therefore, the type of access (Read or Write) is

maintained throughout the burst sequence.

The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are

synchronous-pipelined Burst NoBL SRAMs designed specifi-

cally to eliminate wait states during Write/Read transitions. All

synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock signal is qualified with

the Clock Enable input signal (CEN). If CEN is HIGH, the clock

signal is not recognized and all internal states are maintained.

All synchronous operations are qualified with CEN. All data

outputs pass through output registers controlled by the rising

edge of the clock. Maximum access delay from the clock rise

Single Write Accesses

Write access are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,

and CE are ALL asserted active, and (3) the write signal WE

is asserted LOW. The address presented to the address inputs

is loaded into the Address Register. The write signals are

latched into the Control Logic block.

(t ) is 2.6 ns (250-MHz device).

On the subsequent clock rise the data lines are automatically

three-stated regardless of the state of the OE input signal. This

allows the external logic to present the data on DQ and DQP

Accesses can be initiated by asserting all three Chip Enables

(CE , CE , CE ) active at the rising edge of the clock. If Clock

Enable (CEN) is active LOW and ADV/LD is asserted LOW,

the address presented to the device will be latched. The

access can either be a read or write operation, depending on

(DQ

/DQP

for

for CY7C1460AV25 and DQ /DQP

a,b

CY7C1464AV25,

a,b,c,d,e,f,g,h

/DQP

a,b,c,d

a,b

for CY7C1462AV25). In addition, the address for the subse-

quent access (Read/Write/Deselect) is latched into the

Address Register (provided the appropriate control signals are

asserted).

the status of the Write Enable (WE). BW can be used to

[x]

conduct byte write operations.

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self-timed write

circuitry.

On the next clock rise the data presented to DQ and DQP

(DQ

/DQP

for

for CY7C1460AV25 and DQ /DQP

a,b

CY7C1464AV25,

a,b,c,d,e,f,g,h

Three synchronous Chip Enables (CE , CE , CE ) and an

/DQP

a,b,c,d

a,b

asynchronous Output Enable (OE) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD should be driven LOW once the device has been

deselected in order to load a new address for the next

operation.

for CY7C1462AV25) (or a subset for byte write operations, see

Write Cycle Description table for details) inputs is latched into

the device and the write is complete.

The data written during the Write operation is controlled by BW

(BW

for

CY7C1464AV25,

for

a,b,c,d,e,f,g,h

a,b,c,d

Single Read Accesses

CY7C1460AV25 and BW for CY7C1462AV25) signals. The

a,b

CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 provides

byte write capability that is described in the Write Cycle

Description table. Asserting the Write Enable input (WE) with

the selected Byte Write Select (BW) input will selectively write

to only the desired bytes. Bytes not selected during a byte

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,

and CE are ALL asserted active, (3) the Write Enable input

signal WE is deasserted HIGH, and (4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the Address Register and presented to the memory core

and control logic. The control logic determines that a read

access is in progress and allows the requested data to

propagate to the input of the output register. At the rising edge

of the next clock the requested data is allowed to propagate

through the output register and onto the data bus within 2.6 ns

(200-MHz device) provided OE is active LOW. After the first

clock of the read access the output buffers are controlled by

OE and the internal control logic. OE must be driven LOW in

order for the device to drive out the requested data. During the

second clock, a subsequent operation (Read/Write/Deselect)

can be initiated. Deselecting the device is also pipelined.

Therefore, when the SRAM is deselected at clock rise by one

of the chip enable signals, its output will three-state following

the next clock rise.

write operation will remain unaltered.

synchronous

self-timed write mechanism has been provided to simplify the

write operations. Byte write capability has been included in

order to greatly simplify Read/Modify/Write sequences, which

can be reduced to simple byte write operations.

Because the CY7C1460AV25/CY7C1462AV25/CY7C1464AV25

are common I/O devices, data should not be driven into the

device while the outputs are active. The Output Enable (OE)

can be deasserted HIGH before presenting data to the DQ and

DQP (DQ

/DQP

for CY7C1464AV25,

a,b,c,d,e,f,g,h

/DQP

for CY7C1460AV25 and DQ /DQP

a,b,c,d

a,b,c,d a,b a,b

for CY7C1462AV25) inputs. Doing so will three-state the

output drivers. As a safety precaution, DQ and DQP

(DQ

/DQP

for

for CY7C1460AV25 and DQ /DQP

a,b

CY7C1464AV25,

a,b,c,d,e,f,g,h

/DQP

a,b,c,d

a,b

for CY7C1462AV25) are automatically three-stated during the

data portion of a write cycle, regardless of the state of OE.

Burst Read Accesses

The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 have

an on-chip burst counter that allows the user the ability to

supply a single address and conduct up to four Reads without

reasserting the address inputs. ADV/LD must be driven LOW

in order to load a new address into the SRAM, as described in

the Single Read Access section above. The sequence of the

burst counter is determined by the MODE input signal. A LOW

input on MODE selects a linear burst mode, a HIGH selects an

interleaved burst sequence. Both burst counters use A0 and

A1 in the burst sequence, and will wrap-around when incre-

mented sufficiently. A HIGH input on ADV/LD will increment

Burst Write Accesses

The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 has

an on-chip burst counter that allows the user the ability to

supply a single address and conduct up to four WRITE opera-

tions without reasserting the address inputs. ADV/LD must be

driven LOW in order to load the initial address, as described

in the Single Write Access section above. When ADV/LD is

driven HIGH on the subsequent clock rise, the chip enables

(CE , CE , and CE ) and WE inputs are ignored and the burst

counter is incremented. The correct BW (BW

for

a,b,c,d,e,f,g,h

Document #: 38-05354 Rev. *D

Page 7 of 27

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CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

CY7C1460AV25, BW

CY7C1462AV25) inputs must be driven in each cycle of the

burst write in order to write the correct bytes of data.

for CY7C1460AV25 and BW for

a,b

a,b,c,d

Interleaved Burst Address Table

(MODE = Floating or V_DD

)

First

Address

Second

Address

Third

Address

Fourth

Address

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

A1,A0

the “sleep” mode. CE , CE , and CE , must remain inactive

Linear Burst Address Table (MODE = GND)

for the duration of t

after the ZZ input returns LOW.

ZZREC

First

Second

Address

Third

Address

Fourth

Address

A1,A0

ZZ Mode Electrical Characteristics

Parameter

Description

Sleep mode standby current

Device operation to ZZ

ZZ recovery time

Test Conditions

Min.

Max.

100

Unit

ZZ > V − 0.2V

DDZZ

ZZ > V − 0.2V

ZZS

CYC

ZZ < 0.2V

ZZREC

ZZI

CYC

ZZ active to sleep current

ZZ Inactive to exit sleep current

This parameter is sampled

CYC

RZZI

Truth Table^{[1, 2, 3, 4, 5, 6, 7]}

Address

Used

Operation

Deselect Cycle

ADV/LD

OE CEN CLK

None

L-H

Tri-State

Continue Deselect Cycle

Read Cycle (Begin Burst)

Read Cycle (Continue Burst)

NOP/Dummy Read (Begin Burst)

Dummy Read (Continue Burst)

Write Cycle (Begin Burst)

Write Cycle (Continue Burst)

NOP/WRITE ABORT (Begin Burst)

WRITE ABORT (Continue Burst)

IGNORE CLOCK EDGE (Stall)

Sleep MODE

None

External

L-H Data Out (Q)

External

L-H

Tri-State

External

L-H Data In (D)

None

L-H

Tri-State

–

Current

None

Tri-State

Notes:

1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid

signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

2. Write is defined by WE and BW . See Write Cycle Description table for details.

3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.

4. The DQ and DQP pins are controlled by the current cycle and the OE signal.

5. CEN = H inserts wait states.

6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.

7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ and DQP = Three-state when

OE is inactive or when the device is deselected, and DQ =data when OE is active.

Document #: 38-05354 Rev. *D

Page 8 of 27

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CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Partial Write Cycle Description^{[1, 2, 3, 8]}

Function (CY7C1460AV25)

Read

Write – No bytes written

Write Byte a – (DQ and DQP )

Write Byte b – (DQ and DQP )

Write Bytes b, a

Write Byte c – (DQ and DQP )

Write Bytes c, a

Write Bytes c, b

Write Bytes c, b, a

Write Byte d – (DQ and DQP )

Write Bytes d, a

Write Bytes d, b

Write Bytes d, b, a

Write Bytes d, c

Write Bytes d, c, a

Write Bytes d, c, b

Write All Bytes

Function (CY7C1462AV25)

Read

Write – No Bytes Written

Write Byte a – (DQ and DQP )

Write Byte b – (DQ and DQP )

Write Both Bytes

Function (CY7C1464AV25)

Read

Write – No Bytes Written

Write Byte X − (DQ and DQP

Write All Bytes

All BW = L

Note:

8. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.

Document #: 38-05354 Rev. *D

Page 9 of 27

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CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Test Data-In (TDI)

IEEE 1149.1 Serial Boundary Scan (JTAG)

The TDI ball is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. TDI

is internally pulled up and can be unconnected if the TAP is

unused in an application. TDI is connected to the most signif-

icant bit (MSB) of any register. (See Tap Controller Block

Diagram.)

The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 incor-

porates a serial boundary scan test access port (TAP). This

part is fully compliant with 1149.1. The TAP operates using

JEDEC-standard 2.5V/1.8V I/O logic level.

The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 contains

a TAP controller, instruction register, boundary scan register,

bypass register, and ID register.

Disabling the JTAG Feature

Test Data-Out (TDO)

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied

LOW(VSS) to prevent clocking of the device. TDI and TMS are

internally pulled up and may be unconnected. They may alter-

nately be connected to VDD through a pull-up resistor. TDO

should be left unconnected. Upon power-up, the device will

come up in a reset state which will not interfere with the

operation of the device.

The TDO output ball is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine. The output changes on the

falling edge of TCK. TDO is connected to the least significant

bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller Block Diagram

TAP Controller State Diagram

Bypass Register

TEST-LOGIC

RESET

Selection

Circuitry

Instruction Register

31 30 29

Identification Register

Selection

Circuitry

TDI

TDO

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

CAPTURE-IR

Boundary Scan Register

SHIFT-DR

SHIFT-IR

EXIT1-DR

EXIT1-IR

TCK

TMS

TAP CONTROLLER

PAUSE-DR

PAUSE-IR

EXIT2-DR

EXIT2-IR

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (V ) for five

rising edges of TCK. This RESET does not affect the operation

of the SRAM and may be performed while the SRAM is

operating.

UPDATE-DR

UPDATE-IR

At power-up, the TAP is reset internally to ensure that TDO

comes up in a High-Z state.

The 0/1 next to each state represents the value of TMS at the

rising edge of TCK.

TAP Registers

Registers are connected between the TDI and TDO balls and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time through

the instruction register. Data is serially loaded into the TDI ball

on the rising edge of TCK. Data is output on the TDO ball on

the falling edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

Instruction Register

Test MODE SELECT (TMS)

Three-bit instructions can be serially loaded into the instruction

TDI and TDO balls as shown in the Tap Controller Block

Diagram. Upon power-up, the instruction register is loaded

with the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this ball unconnected if the TAP is not used. The ball is

pulled up internally, resulting in a logic HIGH level.

Document #: 38-05354 Rev. *D

Page 10 of 27

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When the TAP controller is in the Capture-IR state, the two

least significant bits are loaded with a binary “01” pattern to

allow for fault isolation of the board-level serial test data path.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO pins when the TAP

controller is in a Shift-DR state. The SAMPLE Z command puts

the output bus into a High-Z state until the next command is

given during the “Update IR” state.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

TDI and TDO balls. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1-mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

(V ) when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and

bidirectional balls on the SRAM. The length of the Boundary

Scan Register for the SRAM in different packages is listed in

the Scan Register Sizes table.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is

possible that during the Capture-DR state, an input or output

will undergo a transition. The TAP may then try to capture a

signal while in transition (metastable state). This will not harm

the device, but there is no guarantee as to the value that will

be captured. Repeatable results may not be possible.

The boundary scan register is loaded with the contents of the

RAM I/O ring when the TAP controller is in the Capture-DR

state and is then placed between the TDI and TDO balls when

the controller is moved to the Shift-DR state. The EXTEST,

SAMPLE/PRELOAD and SAMPLE Z instructions can be used

to capture the contents of the I/O ring.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture set-up plus

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI, and the LSB is connected to TDO.

hold times (t and t ). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE/PRELOAD instruction. If this

is an issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK# captured in the

boundary scan register.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the

boundary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells

prior to the selection of another boundary scan test operation.

TAP Instruction Set

The shifting of data for the SAMPLE and PRELOAD phases

can occur concurrently when required—that is, while data

captured is shifted out, the preloaded data can be shifted in.

Overview

Eight different instructions are possible with the three bit

instruction register. All combinations are listed in the

Instruction Codes table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

BYPASS

When the BYPASS instruction is loaded in the instruction

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO balls.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

EXTEST

The EXTEST instruction enables the preloaded data to be

driven out through the system output pins. This instruction also

selects the boundary scan register to be connected for serial

access between the TDI and TDO in the shift-DR controller

state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO balls and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state.

EXTEST Output Bus Tri-State

IEEE Standard 1149.1 mandates that the TAP controller be

able to put the output bus into a tri-state mode.

The IDCODE instruction is loaded into the instruction register

upon power-up or whenever the TAP controller is given a test

logic reset state.

The boundary scan register has a special bit located at bit #89

(for 165-FBGA package) or bit #138 (for 209 FBGA package).

Document #: 38-05354 Rev. *D

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When this scan cell, called the “extest output bus tri-state,” is

latched into the preload register during the “Update-DR” state

in the TAP controller, it will directly control the state of the

output (Q-bus) pins, when the EXTEST is entered as the

current instruction. When HIGH, it will enable the output

buffers to drive the output bus. When LOW, this bit will place

the output bus into a High-Z condition.

loaded into that shift-register cell will latch into the preload

directly control the output Q-bus pins. Note that this bit is

preset HIGH to enable the output when the device is

powered-up, and also when the TAP controller is in the

“Test-Logic-Reset” state.

Reserved

This bit can be set by entering the SAMPLE/PRELOAD or

EXTEST command, and then shifting the desired bit into that

cell, during the “Shift-DR” state. During “Update-DR,” the value

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

TAP Timing

Test Clock

(TCK)

CYC

TMSS

TDIS

TMSH

Test Mode Select

(TMS)

TDIH

Test Data-In

(TDI)

TDOV

TDOX

Test Data-Out

(TDO)

DON’T CARE

UNDEFINED

[9, 10]

TAP AC Switching Characteristics Over the Operating Range

Parameter

Clock

Description

Min.

Max.

Unit

TCK Clock Cycle Time

TCK Clock Frequency

TCK Clock HIGH time

TCK Clock LOW time

MHz

TCYC

Output Times

TCK Clock LOW to TDO Valid

TCK Clock LOW to TDO Invalid

TDOV

TDOX

Set-up Times

TMS Set-up to TCK Clock Rise

TDI Set-up to TCK Clock Rise

Capture Set-up to TCK Rise

TMSS

TDIS

Hold Times

TMS Hold after TCK Clock Rise

TDI Hold after Clock Rise

TMSH

TDIH

Capture Hold after Clock Rise

Notes:

9. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.

10. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.

Document #: 38-05354 Rev. *D

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2.5V TAP AC Test Conditions

1.8V TAP AC Test Conditions

Input pulse levels ............................................... V to 2.5V

Input pulse levels..................................... 0.2V to V

– 0.2

DDQ

Input rise and fall time .................................................... 1 ns

Input timing reference levels.........................................1.25V

Output reference levels.................................................1.25V

Test load termination supply voltage.............................1.25V

Input rise and fall time .....................................................1 ns

Input timing reference levels........................................... 0.9V

Output reference levels .................................................. 0.9V

Test load termination supply voltage .............................. 0.9V

2.5V TAP AC Output Load Equivalent

1.8V TAP AC Output Load Equivalent

1.25V

0.9V

50Ω

TDO

Z_O= 50Ω

20pF

TAP DC Electrical Characteristics And Operating Conditions

[11]

(0°C < TA < +70°C; V = 2.5V ±0.125V unless otherwise noted)

Parameter

Description

Test Conditions

Min.

1.7

Max.

Unit

Output HIGH Voltage

= –1.0 mA

= 2.5V

= 1.8V

= 2.5V

= 1.8V

= 2.5V

= 1.8V

= 2.5V

= 1.8V

OH1

DDQ

= –100 µA

2.1

OH2

1.6

Output LOW Voltage

= 1.0 mA

0.4

0.2

OL1

= 100 µA

OL2

Input HIGH Voltage

Input LOW Voltage

Input Load Current

1.7

1.26

–0.3

–5

+ 0.3

0.7

0.36

GND ≤ V ≤ V

DDQ

µA

Identification Register Definitions

CY7C1460AV25 CY7C1462AV25 CY7C1464AV25

Instruction Field

Revision Number (31:29)

Device Depth (28:24)

(1M ×36)

(2M ×18)

(512K ×72)

Description

000

Describes the version number

Reserved for Internal Use

01011

001000

01011

001000

01011

Architecture/Memory Type(23:18)

001000

Defines memory type and archi-

tecture

Bus Width/Density(17:12)

100111

010111

110111

Defines width and density

Cypress JEDEC ID Code (11:1)

00000110100

00000110100 Allows unique identification of

SRAM vendor

ID Register Presence Indicator (0)

Indicates the presence of an ID

Note:

11. All voltages referenced to V (GND).

Document #: 38-05354 Rev. *D

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Scan Register Sizes

Bit Size (x36)

Bit Size (x18)

Bit Size (x72)

Instruction

Bypass

–

Boundary Scan Order (165-ball FBGA package)

Boundary Scan Order (209-ball FBGA package)

–

138

Identification Codes

Instruction

EXTEST

Code

Description

000

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM outputs to High-Z state.

IDCODE

001

010

Loads the ID register with the vendor ID code and places the register between TDI and

TDO. This operation does not affect SRAM operations.

SAMPLE Z

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED

011

100

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation.

RESERVED

BYPASS

101

110

111

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

Document #: 38-05354 Rev. *D

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165-ball FBGA Boundary Scan Order^[12]

CY7C1460AV25 (1M x 36), CY7C1462AV25 (2M x 18)

Bit#

Ball ID

Bit#

Ball ID

E11

D11

G10

F10

E10

D10

C11

A11

B11

A10

B10

Bit#

Ball ID

Bit#

Ball ID

N10

P11

P10

R10

R11

H11

N11

M11

L11

K11

J11

M10

L10

K10

J10

C10

Internal

H10

G11

F11

Note:

12. Bit# 89 is preset HIGH.

Document #: 38-05354 Rev. *D

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209-ball FBGA Boundary Scan Order ^{[12, 13]}

CY7C1464AV25 (512K x 72)

Bit#

Ball ID

Bit#

Ball ID

Bit#

Ball ID

Bit#

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

Ball ID

K10

J11

J10

H11

H10

G11

G10

F11

F10

E10

E11

D11

D10

C11

C10

B11

B10

A11

A10

W11

W10

V11

V10

U11

U10

T11

T10

R11

R10

P11

P10

N11

N10

M11

M10

L11

L10

K11

100

101

102

103

104

105

Internal

Note:

13. Bit# 138 is preset HIGH.

Document #: 38-05354 Rev. *D

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Current into Outputs (LOW)......................................... 20 mA

Maximum Ratings

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Latch-up Current.................................................... > 200 mA

Storage Temperature .................................–65°C to +150°C

Operating Range

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Ambient

Supply Voltage on V Relative to GND........ –0.5V to +3.6V

Range

Temperature

DDQ

Supply Voltage on V

Relative to GND ......–0.5V to +V

Commercial 0°C to +70°C 2.5V –5%/+5% 1.7V to V

DDQ

DC to Outputs in Tri-State................... –0.5V to V

+ 0.5V

Industrial

–40°C to +85°C

DDQ

DC Input Voltage....................................–0.5V to V + 0.5V

[14, 15]

Electrical Characteristics Over the Operating Range

DC Electrical Characteristics Over the Operating Range

Parameter

Description

Power Supply Voltage

I/O Supply Voltage

Test Conditions

Min.

2.375

1.7

Max.

Unit

2.625

for 2.5V I/O

for 1.8V I/O

DDQ

1.9

Output HIGH Voltage

Output LOW Voltage

for 2.5V I/O, I = −1.0 mA

2.0

for 1.8V I/O, I = –100 µA

1.6

for 2.5V I/O, I = 1.0 mA

0.4

0.2

for 1.8V I/O, I = 100 µA,

[14]

Input HIGH Voltage

for 2.5V I/O

for 1.8V I/O

for 2.5V I/O

for 1.8V I/O

1.7

1.26

–0.3

–5

+ 0.3V

[14]

Input LOW Voltage

0.7

0.36

Input Leakage Current GND ≤ V ≤ V

except ZZ and MODE

µA

DDQ

Input Current of MODE Input = V

–30

–5

µA

Input = V

Input Current of ZZ

Input = V

µA

Output Leakage Current GND ≤ V ≤ V

Output Disabled

–5

µA

DDQ,

Operating Supply

f = f

= Max., I

= 0 mA,

4-ns cycle, 250 MHz

5-ns cycle, 200 MHz

6-ns cycle, 167 MHz

435

385

335

185

OUT

= 1/t

CYC

MAX

Automatic CE

Power-down

Current—TTL Inputs

Max. V , Device Deselected, All speed grades

SB1

SB2

SB3

SB4

≥ V or V ≤ V , f = f

MAX

1/t

CYC

Automatic CE

Power-down

Current—CMOS Inputs f = 0

Max. V , Device Deselected, All speed grades

120

160

135

≤ 0.3V or V > V

− 0.3V,

DDQ

Automatic CE

Power-down

Current—CMOS Inputs f = f

Max. V , Device Deselected, All speed grades

≤ 0.3V or V > V

− 0.3V,

CYC

DDQ

= 1/t

MAX

Automatic CE

Max. V , Device Deselected, All speed grades

Power-down

Current—TTL Inputs

≥ V or V ≤ V , f = 0

Notes:

14. Overshoot: V (AC) < V +1.5V (Pulse width less than t

/2), undershoot: V (AC)> –2V (Pulse width less than t /2).

CYC

15. T

: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V

< V

Power-up

DDQ

Document #: 38-05354 Rev. *D

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Capacitance^[16]

100 TQFP

Max.

165 FBGA

209 FBGA

Max.

Parameter

Description

Test Conditions

T = 25°C, f = 1 MHz,

Max.

Unit

Input Capacitance

6.5

= 2.5V V

= 2.5V

DDQ

Clock Input Capacitance

Input/Output Capacitance

CLK

I/O

5.5

Thermal Resistance^[16]

100 TQFP

Package

165 FBGA

Package

209 FBGA

Package

Parameters

Description

Test Conditions

Unit

Thermal Resistance

(Junction to Ambient)

Testconditionsfollowstandard

test methods and procedures

for measuring thermal

25.21

20.8

25.31

°C/W

Thermal Resistance

(Junction to Case)

2.58

3.2

4.48

°C/W

impedance, per EIA/JESD51.

AC Test Loads and Waveforms

3.3V I/O Test Load

R = 317Ω

3.3V

OUTPUT

ALL INPUT PULSES

90%

V_DDQ

GND

90%

10%

Z = 50Ω

R = 50Ω

10%

5 pF

R = 351Ω

INCLUDING

JIG AND

SCOPE

≤ 1ns

V = 1.5V

(a)

(b)

(c)

2.5V I/O Test Load

R = 1667Ω

2.5V

OUTPUT

R = 50Ω

OUTPUT

ALL INPUT PULSES

90%

V_DDQ

90%

10%

Z = 50Ω

10%

GND

5 pF

R = 1538Ω

INCLUDING

JIG AND

SCOPE

≤ 1ns

V = 1.25V

(a)

(b)

(c)

Note:

16. Tested initially and after any design or process change that may affect these parameters.

Document #: 38-05354 Rev. *D

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[21, 22]

Switching Characteristics Over the Operating Range

–250

Max.

–200

Max.

–167

Parameter

Description

Min.

Max.

Unit

[17]

(typical) to the first access read or write

Power

Clock

Clock Cycle Time

Maximum Operating Frequency

Clock HIGH

4.0

5.0

6.0

MHz

CYC

250

200

167

MAX

1.5

2.0

2.4

Clock LOW

Output Times

Data Output Valid After CLK Rise

OE LOW to Output Valid

2.6

3.2

3.0

3.4

EOV

DOH

CHZ

CLZ

Data Output Hold After CLK Rise

1.0

1.5

1.3

1.5

[18, 19, 20]

Clock to High-Z

2.6

3.0

3.4

[18, 19, 20]

Clock to Low-Z

[18, 19, 20]

OE HIGH to Output High-Z

EOHZ

EOLZ

[18, 19, 20]

OE LOW to Output Low-Z

Set-up Times

Address Set-up Before CLK Rise

Data Input Set-up Before CLK Rise

CEN Set-up Before CLK Rise

1.2

1.4

1.5

CENS

WES

ALS

CES

WE, BW Set-up Before CLK Rise

ADV/LD Set-up Before CLK Rise

Chip Select Set-up

Hold Times

Address Hold After CLK Rise

Data Input Hold After CLK Rise

CEN Hold After CLK Rise

0.3

0.4

0.5

CENH

WEH

ALH

CEH

WE, BW Hold After CLK Rise

ADV/LD Hold after CLK Rise

Chip Select Hold After CLK Rise

Notes:

17. This part has a voltage regulator internally; t

is the time power needs to be supplied above V minimum initially, before a Read or Write operation can be

power

initiated.

18. t

, t

, and t

are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

CHZ CLZ EOLZ

EOHZ

19. At any given voltage and temperature, t

is less than t

and t

is less than t

to eliminate bus contention between SRAMs when sharing the same

EOHZ

EOLZ

CHZ

CLZ

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

20. This parameter is sampled and not 100% tested.

21. Timing reference is 1.25V when V

= 2.5V and 0.9V when V

= 1.8V.

DDQ

22. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

Document #: 38-05354 Rev. *D

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Switching Waveforms

[23, 24, 25]

Read/Write/Timing

CYC

CLK

CENS CENH

CEN

CES

CEH

ADV/LD

BWx

ADDRESS

DOH

OEV

CLZ

CHZ

Data

D(A1)

D(A2)

D(A2+1)

Q(A3)

Q(A4)

Q(A4+1)

D(A5)

Q(A6)

In-Out (DQ)

OEHZ

DOH

OELZ

WRITE

D(A1)

WRITE

D(A2)

BURST

WRITE

READ

Q(A3)

READ

Q(A4)

BURST

READ

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

D(A2+1)

Q(A4+1)

DON’T CARE

UNDEFINED

[23, 24, 26]

NOP, STALL and DESELECT Cycles

CLK

CEN

ADV/LD

BWx

ADDRESS

CHZ

D(A4)

D(A1)

Q(A2)

Q(A3)

STALL

Q(A5)

Data

In-Out (DQ)

WRITE

D(A1)

READ

Q(A2)

STALL

READ

Q(A3)

WRITE

D(A4)

NOP

READ

Q(A5)

DESELECT

CONTINUE

DESELECT

DON’T CARE

UNDEFINED

Notes:

23. For this waveform ZZ is tied low.

24. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH,CE is HIGH or CE is LOW or CE is HIGH.

25. Order of the Burst sequence is determined by the status of the MODE (0=Linear, 1=Interleaved).Burst operations are optional.

26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.

Document #: 38-05354 Rev. *D

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Switching Waveforms (continued)

[27, 28]

ZZ Mode Timing

CLK

ZZREC

ZZI

SUPPLY

DDZZ

RZZI

ALL INPUTS

(except ZZ)

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

Notes:

27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.

28. I/Os are in High-Z when exiting ZZ sleep mode.

Document #: 38-05354 Rev. *D

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Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz)

Package

Diagram

Operating

Range

Ordering Code

Part and Package Type

167 CY7C1460AV25-167AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

CY7C1462AV25-167AXC

Commercial

CY7C1460AV25-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1462AV25-167BZC

CY7C1460AV25-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free

CY7C1462AV25-167BZXC

CY7C1464AV25-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1464AV25-167BGXC

CY7C1460AV25-167AXI

CY7C1462AV25-167AXI

CY7C1460AV25-167BZI

CY7C1462AV25-167BZI

209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free

51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

lndustrial

51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1460AV25-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free

CY7C1462AV25-167BZXI

CY7C1464AV25-167BGI

CY7C1464AV25-167BGXI

51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free

200 CY7C1460AV25-200AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

CY7C1462AV25-200AXC

Commercial

CY7C1460AV25-200BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1462AV25-200BZC

CY7C1460AV25-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free

CY7C1462AV25-200BZXC

CY7C1464AV25-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1464AV25-200BGXC

CY7C1460AV25-200AXI

CY7C1462AV25-200AXI

CY7C1460AV25-200BZI

CY7C1462AV25-200BZI

209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free

51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

lndustrial

51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1460AV25-200BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free

CY7C1462AV25-200BZXI

CY7C1464AV25-200BGI

CY7C1464AV25-200BGXI

51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free

Document #: 38-05354 Rev. *D

Page 22 of 27

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CY7C1462AV25

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Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz)

Package

Diagram

Operating

Range

Ordering Code

Part and Package Type

250 CY7C1460AV25-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

CY7C1462AV25-250AXC

Commercial

CY7C1460AV25-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1462AV25-250BZC

CY7C1460AV25-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free

CY7C1462AV25-250BZXC

CY7C1464AV25-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1464AV25-250BGXC

CY7C1460AV25-250AXI

CY7C1462AV25-250AXI

CY7C1460AV25-250BZI

CY7C1462AV25-250BZI

209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free

51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1460AV25-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free

CY7C1462AV25-250BZXI

CY7C1464AV25-250BGI

CY7C1464AV25-250BGXI

51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free

Document #: 38-05354 Rev. *D

Page 23 of 27

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CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Package Diagrams

100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)

16.00 0.20

1.40 0.05

14.00 0.10

100

0.30 0.08

0.65

TYP.

12° 1°

(8X)

SEE DETAIL

0.20 MAX.

1.60 MAX.

R 0.08 MIN.

0.20 MAX.

0° MIN.

SEATING PLANE

STAND-OFF

0.05 MIN.

0.15 MAX.

NOTE:

0.25

1. JEDEC STD REF MS-026

GAUGE PLANE

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

R 0.08 MIN.

0.20 MAX.

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

0°-7°

0.60 0.15

0.20 MIN.

51-85050-*B

1.00 REF.

DETAIL

Document #: 38-05354 Rev. *D

Page 24 of 27

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CY7C1462AV25

CY7C1464AV25

Package Diagrams (continued)

165-ball FBGA (15 x 17 x 1.4 mm) (51-85165)

PIN 1 CORNER

BOTTOM VIEW

TOP VIEW

Ø0.05 M C

PIN 1 CORNER

Ø0.25 M C A B

Ø0.45 0.05(165X)

11 10

1.00

5.00

10.00

15.00 0.10

0.15(4X)

51-85165-*A

SEATING PLANE

Document #: 38-05354 Rev. *D

Page 25 of 27

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CY7C1462AV25

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Package Diagrams (continued)

209-ball FBGA (14 x 22 x 1.76 mm) (51-85167)

51-85167-**

ZBT is a registered trademark of Integrated Device Technology, Inc. No Bus Latency and NoBL are trademarks of Cypress

Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective

holders.

Document #: 38-05354 Rev. *D

Page 26 of 27

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Document History Page

Document Title: CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 36-Mbit (1-Mbit x 36/2-Mbit x 18/512K x 72) Pipelined

SRAM with NoBL™ Architecture

Document Number: 38-05354

Orig. of

Change

REV.

ECN No.

Issue Date

Description of Change

254911

See ECN

SYT

New data sheet

Part number changed from previous revision (new and old part number

differ by the letter “A”)

303533

See ECN

SYT

Changed H9 pin from V

FBGA on Page # 5

to V on the Pin Configuration table for 209

SSQ SS

Changed the test condition from V = Min. to V = Max for V in the

Electrical Characteristics table

^ReplacedΘ_JAand Θ_JCfrom TBD to respective Thermal Values for All

Packages on the Thermal Resistance Table

Changed I from 450, 400 & 350 mA to 435, 385 & 335 mA for 250, 200

and 167 Mhz respectively

Changed I

from 190, 180 and 170 mA to 185 mA for 250, 200 and 167

SB1

Mhz respectively

Changed I

from 80 mA to 100 mA for all frequencies

from 180, 170 & 160 mA to 160 mA for 250, 200 and 167

SB2

SB3

Mhz respectively

Changed I from 100 mA to 110 mA for all frequencies

SB4

Changed C , C

and C to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for

I/O

CLK

TQFP Package

Changed t from 3.0 to 3.2 ns and t

from 1.3 ns to 1.5 ns for 200 Mhz

DOH

Speed Bin

Added lead-free information for 100 TQFP, 165 FBGA and 209 FBGA

packages

331778

See ECN

SYT

Modified Address Expansion balls in the pinouts for 165 FBGA and 209

FBGA Package as per JEDEC standards and updated the Pin Definitions

accordingly

Modified V

Changed C , C

test conditions

OL, OH

and C to 7, 7and 6 pF from 5, 5 and 7 pF for 165

I/O

CLK

FBGA Package

Added Industrial Temperature Grade

Changed I

tively

and I

from 100 and 110 mA to 120 and 135 mA respec-

SB2

SB4

Updated the Ordering Information by Shading and Unshading MPNs as per

availability

417547

See ECN

RXU

Converted from Preliminary to Final

Changed address of Cypress Semiconductor Corporation on Page# 1 from

“3901 North First Street” to “198 Champion Court”

Modified test condition from V

< V to V

≤ V

DDQ

DDQ DD

Changed I current value in MODE from –5 & 30 µA to –30 & 5 µA respec-

tively and also Changed I current value in ZZ from –30 & 5 µA to –5 & 30

µA respectively on page# 19

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in

the Electrical Characteristics Table

Replaced Package Name column with Package Diagram in the Ordering

Information table

Replaced Package Diagram of 51-85050 from *A to *B

473650

See ECN

VKN

Added the Maximum Rating for Supply Voltage on V

Relative to GND.

DDQ

Changed t , t from 25 ns to 20 ns and t

from 5 ns to 10 ns in TAP

TH TL

TDOV

AC Switching Characteristics table.

Updated the Ordering Information table.

Document #: 38-05354 Rev. *D

Page 27 of 27

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