Cypress ISR 37000 CPLD User Manual
Ultra37000 CPLD Family  
5V, 3.3V, ISR™ High-Performance CPLDs  
Features  
General Description  
• In-System Reprogrammable™ (ISR™) CMOS CPLDs  
— JTAG interface for reconfigurability  
— Design changes do not cause pinout changes  
— Design changes do not cause timing changes  
• High density  
The Ultra37000™ family of CMOS CPLDs provides a range of  
high-density programmable logic solutions with unparalleled  
system performance. The Ultra37000 family is designed to  
bring the flexibility, ease of use, and performance of the 22V10  
to high-density CPLDs. The architecture is based on a number  
of logic blocks that are connected by a Programmable Inter-  
connect Matrix (PIM). Each logic block features its own  
product term array, product term allocator, and 16 macrocells.  
The PIM distributes signals from the logic block outputs and all  
input pins to the logic block inputs.  
— 32 to 512 macrocells  
— 32 to 264 I/O pins  
— Five dedicated inputs including four clock pins  
• Simple timing model  
All of the Ultra37000 devices are electrically erasable and  
In-System Reprogrammable (ISR), which simplifies both  
design and manufacturing flows, thereby reducing costs. The  
ISR feature provides the ability to reconfigure the devices  
without having design changes cause pinout or timing  
changes. The Cypress ISR function is implemented through a  
JTAG-compliant serial interface. Data is shifted in and out  
through the TDI and TDO pins, respectively. Because of the  
superior routability and simple timing model of the Ultra37000  
devices, ISR allows users to change existing logic designs  
while simultaneously fixing pinout assignments and  
maintaining system performance.  
— No fanout delays  
— No expander delays  
— No dedicated vs. I/O pin delays  
— No additional delay through PIM  
— No penalty for using full 16 product terms  
— No delay for steering or sharing product terms  
• 3.3V and 5V versions  
[1]  
• PCI-compatible  
The entire family features JTAG for ISR and boundary scan,  
and is compatible with the PCI Local Bus specification,  
meeting the electrical and timing requirements. The  
Ultra37000 family features user programmable bus-hold  
capabilities on all I/Os.  
• Programmable bus-hold capabilities on all I/Os  
• Intelligent product term allocator provides:  
— 0 to 16 product terms to any macrocell  
— Product term steering on an individual basis  
— Product term sharing among local macrocells  
• Flexible clocking  
Ultra37000 5.0V Devices  
The Ultra37000 devices operate with a 5V supply and can  
support 5V or 3.3V I/O levels. V  
connections provide the  
CCO  
capability of interfacing to either a 5V or 3.3V bus. By  
connecting the V pins to 5V the user insures 5V TTL levels  
— Four synchronous clocks per device  
— Product term clocking  
CCO  
on the outputs. If V  
is connected to 3.3V the output levels  
CCO  
— Clock polarity control per logic block  
• Consistent package/pinout offeringacrossall densities  
— Simplifies design migration  
meet 3.3V JEDEC standard CMOS levels and are 5V tolerant.  
These devices require 5V ISR programming.  
Ultra37000V 3.3V Devices  
— Same pinout for 3.3V and 5.0V devices  
• Packages  
Devices operating with a 3.3V supply require 3.3V on all V  
CCO  
pins, reducing the device’s power consumption. These  
devices support 3.3V JEDEC standard CMOS output levels,  
and are 5V-tolerant. These devices allow 3.3V ISR  
programming.  
— 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP,  
BGA, and Fine-Pitch BGA packages  
— Lead (Pb)-free packages available  
Note:  
1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V , PCI V = 2V.  
CC  
IH  
Cypress Semiconductor Corporation  
Document #: 38-03007 Rev. *E  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised March 7, 2004  
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Ultra37000 CPLD Family  
Speed Bins  
Device  
200  
167  
154  
143  
X
125  
100  
X
83  
66  
CY37032V  
CY37064V  
CY37128V  
CY37192V  
CY37256V  
CY37384V  
CY37512V  
X
X
X
X
X
X
X
X
X
X
X
X
Device-Package Offering and I/O Count  
Device  
CY37032V  
CY37064V  
CY37128V  
CY37192V  
CY37256V  
CY37384V  
CY37512V  
37  
37  
37  
37  
37  
69  
69  
69  
85  
69  
133  
125  
133  
133  
165  
165  
165  
197  
197  
197  
197  
165  
269  
269  
Logic Block  
Architecture Overview of Ultra37000 Family  
The logic block is the basic building block of the Ultra37000  
architecture. It consists of a product term array, an intelligent  
product-term allocator, 16 macrocells, and a number of I/O  
cells. The number of I/O cells varies depending on the device  
used. Refer to Figure 1 for the block diagram.  
Programmable Interconnect Matrix  
The PIM consists of a completely global routing matrix for  
signals from I/O pins and feedbacks from the logic blocks. The  
PIM provides extremely robust interconnection to avoid fitting  
and density limitations.  
Product Term Array  
The inputs to the PIM consist of all I/O and dedicated input pins  
and all macrocell feedbacks from within the logic blocks. The  
number of PIM inputs increases with pin count and the number  
of logic blocks. The outputs from the PIM are signals routed to  
the appropriate logic blocks. Each logic block receives 36  
inputs from the PIM and their complements, allowing for 32-bit  
operations to be implemented in a single pass through the  
device. The wide number of inputs to the logic block also  
improves the routing capacity of the Ultra37000 family.  
Each logic block features a 72 x 87 programmable product  
term array. This array accepts 36 inputs from the PIM, which  
originate from macrocell feedbacks and device pins. Active  
LOW and active HIGH versions of each of these inputs are  
generated to create the full 72-input field. The 87 product  
terms in the array can be created from any of the 72 inputs.  
Of the 87 product terms, 80 are for general-purpose use for  
the 16 macrocells in the logic block. Four of the remaining  
seven product terms in the logic block are output enable (OE)  
product terms. Each of the OE product terms controls up to  
eight of the 16 macrocells and is selectable on an individual  
macrocell basis. In other words, each I/O cell can select  
between one of two OE product terms to control the output  
buffer. The first two of these four OE product terms are  
available to the upper half of the I/O macrocells in a logic block.  
The other two OE product terms are available to the lower half  
of the I/O macrocells in a logic block.  
An important feature of the PIM is its simple timing. The propa-  
gation delay through the PIM is accounted for in the timing  
specifications for each device. There is no additional delay for  
traveling through the PIM. In fact, all inputs travel through the  
PIM. As a result, there are no route-dependent timing param-  
eters on the Ultra37000 devices. The worst-case PIM delays  
are incorporated in all appropriate Ultra37000 specifications.  
Routing signals through the PIM is completely invisible to the  
user. All routing is accomplished by software—no hand routing  
®
The next two product terms in each logic block are dedicated  
asynchronous set and asynchronous reset product terms. The  
final product term is the product term clock. The set, reset, OE  
and product term clock have polarity control to realize OR  
functions in a single pass through the array.  
is necessary. Warp and third-party development packages  
automatically route designs for the Ultra37000 family in a  
matter of minutes. Finally, the rich routing resources of the  
Ultra37000 family accommodate last minute logic changes  
while maintaining fixed pin assignments.  
Document #: 38-03007 Rev. *E  
Page 3 of 64  
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Ultra37000 CPLD Family  
3
2
2
0−16  
I/O  
CELL  
0
MACRO-  
CELL  
0
PRODUCT  
TERMS  
7
MACRO-  
CELL  
1
0−16  
to cells  
2, 4, 6 8, 10, 12  
PRODUCT  
TERMS  
FROM  
PIM  
36  
80  
72 x 87  
PRODUCT TERM  
ARRAY  
PRODUCT  
TERM  
ALLOCATOR  
MACRO-  
CELL  
14  
I/O  
CELL  
14  
0−16  
PRODUCT  
TERMS  
MACRO-  
CELL  
15  
0−16  
TO  
PIM  
PRODUCT  
TERMS  
16  
8
Figure 1. Logic Block with 50% Buried Macrocells  
Low-Power Option  
variable fashion. The software automatically takes advantage  
of this capability—the user does not have to intervene.  
Each logic block can operate in high-speed mode for critical  
path performance, or in low-power mode for power conser-  
vation. The logic block mode is set by the user on a logic block  
by logic block basis.  
Note that neither product term sharing nor product term  
steering have any effect on the speed of the product. All  
worst-case steering and sharing configurations have been  
incorporated in the timing specifications for the Ultra37000  
devices.  
Product Term Allocator  
Through the product term allocator, software automatically  
distributes product terms among the 16 macrocells in the logic  
block as needed. A total of 80 product terms are available from  
the local product term array. The product term allocator  
provides two important capabilities without affecting perfor-  
mance: product term steering and product term sharing.  
Ultra37000 Macrocell  
Within each logic block there are 16 macrocells. Macrocells  
can either be I/O Macrocells, which include an I/O Cell which  
is associated with an I/O pin, or buried Macrocells, which do  
not connect to an I/O. The combination of I/O Macrocells and  
buried Macrocells varies from device to device.  
Product Term Steering  
Buried Macrocell  
Product term steering is the process of assigning product  
terms to macrocells as needed. For example, if one macrocell  
requires ten product terms while another needs just three, the  
product term allocator will “steer” ten product terms to one  
macrocell and three to the other. On Ultra37000 devices,  
product terms are steered on an individual basis. Any number  
between 0 and 16 product terms can be steered to any  
macrocell. Note that 0 product terms is useful in cases where  
a particular macrocell is unused or used as an input register.  
Figure 2 displays the architecture of buried macrocells. The  
buried macrocell features a register that can be configured as  
combinatorial, a D flip-flop, a T flip-flop, or a level-triggered  
latch.  
The register can be asynchronously set or asynchronously  
reset at the logic block level with the separate set and reset  
product terms. Each of these product terms features program-  
mable polarity. This allows the registers to be set or reset  
based on an AND expression or an OR expression.  
Product Term Sharing  
Clocking of the register is very flexible. Four global  
synchronous clocks and a product term clock are available to  
clock the register. Furthermore, each clock features program-  
mable polarity so that registers can be triggered on falling as  
well as rising edges (see the Clocking section). Clock polarity  
is chosen at the logic block level.  
Product term sharing is the process of using the same product  
term among multiple macrocells. For example, if more than  
one output has one or more product terms in its equation that  
are common to other outputs, those product terms are only  
programmed once. The Ultra37000 product term allocator  
allows sharing across groups of four output macrocells in a  
Document #: 38-03007 Rev. *E  
Page 4 of 64  
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Ultra37000 CPLD Family  
The buried macrocell also supports input register capability.  
The buried macrocell can be configured to act as an input  
register (D-type or latch) whose input comes from the I/O pin  
associated with the neighboring macrocell. The output of all  
buried macrocells is sent directly to the PIM regardless of its  
configuration.  
Bus Hold Capabilities on all I/Os  
Bus-hold, which is an improved version of the popular internal  
pull-up resistor, is a weak latch connected to the pin that does  
not degrade the device’s performance. As a latch, bus-hold  
maintains the last state of a pin when the pin is placed in a  
high-impedance state, thus reducing system noise in  
bus-interface applications. Bus-hold additionally allows  
unused device pins to remain unconnected on the board,  
which is particularly useful during prototyping as designers can  
route new signals to the device without cutting trace connec-  
I/O Macrocell  
Figure 2 illustrates the architecture of the I/O macrocell. The  
I/O macrocell supports the same functions as the buried  
macrocell with the addition of I/O capability. At the output of the  
macrocell, a polarity control mux is available to select active  
LOW or active HIGH signals. This has the added advantage  
of allowing significant logic reduction to occur in many appli-  
cations.  
tions to V or GND. For more information, see the application  
CC  
note Understanding Bus-Hold—A Feature of Cypress CPLDs.  
Programmable Slew Rate Control  
Each output has a programmable configuration bit, which sets  
the output slew rate to fast or slow. For designs concerned with  
meeting FCC emissions standards the slow edge provides for  
lower system noise. For designs requiring very high perfor-  
mance the fast edge rate provides maximum system perfor-  
mance.  
The Ultra37000 macrocell features a feedback path to the PIM  
separate from the I/O pin input path. This means that if the  
macrocell is buried (fed back internally only), the associated  
I/O pin can still be used as an input.  
I/O MACROCELL  
FAST  
FROM PTM  
0
1
SLEW  
C26  
SLOW  
0−16  
PRODUCT  
TERMS  
C25  
I/O CELL  
0
1
O
O
0
1
P
D/T/L  
Q
0
1
2
3
4
“0”  
“1”  
0
O
R
C4  
1
2
3
O
DECODE  
C2 C3  
C0 C1C24  
C6 C5  
1
0
BURIED MACROCELL  
FROM PTM  
0
1
0−16  
PRODUCT  
TERMS  
C25  
0
1
0
O
O
P
D/T/L  
1
Q
0
1
Q
2
3
C7  
R
4
DECODE  
C2 C3  
C0 C1C24  
1
0
FEEDBACK TO PIM  
FEEDBACK TO PIM  
FEEDBACK TO PIM  
ASYNCHRONOUS  
BLOCK RESET  
ASYNCHRONOUS  
4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)  
1 ASYNCHRONOUS CLOCK(PTCLK)  
OE0  
OE1  
BLOCK PRESET  
Figure 2. I/O and Buried Macrocells  
Document #: 38-03007 Rev. *E  
Page 5 of 64  
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Ultra37000 CPLD Family  
INPUT PIN  
0
1
O
TO PIM  
2
3
D
D
0
1
2
3
Q
Q
Q
FROM CLOCK  
O
POLARITY MUXES  
C12 C13  
C10 C11  
D
LE  
Figure 3. Input Macrocell  
0
TO CLOCK MUX ON  
ALL INPUT MACROCELLS  
O
1
INPUT/CLOCK PIN  
C12  
0
O
1
TO CLOCK MUX  
IN EACH  
LOGIC BLOCK  
C13, C14, C15  
OR C16  
0
1
2
O
TO PIM  
CLOCK POLARITY MUX  
ONE PER LOGIC BLOCK  
FOR EACH CLOCK INPUT  
D
D
D
3
0
1
2
3
Q
Q
Q
FROM CLOCK  
POLARITY INPUT  
CLOCK PINS  
O
C10C11  
C8  
C9  
LE  
Figure 4. Input/Clock Macrocell  
Timing Model  
Clocking  
Each I/O and buried macrocell has access to four synchronous  
clocks (CLK0, CLK1, CLK2 and CLK3) as well as an  
asynchronous product term clock PTCLK. Each input  
macrocell has access to all four synchronous clocks.  
One of the most important features of the Ultra37000 family is  
the simplicity of its timing. All delays are worst case and  
system performance is unaffected by the features used.  
Figure 5 illustrates the true timing model for the 167-MHz  
devices in high speed mode. For combinatorial paths, any  
input to any output incurs a 6.5-ns worst-case delay regardless  
of the amount of logic used. For synchronous systems, the  
input set-up time to the output macrocells for any input is 3.5  
ns and the clock to output time is also 4.0 ns. These measure-  
ments are for any output and synchronous clock, regardless  
of the logic used.  
Dedicated Inputs/Clocks  
Five pins on each member of the Ultra37000 family are desig-  
nated as input-only. There are two types of dedicated inputs  
on Ultra37000 devices: input pins and input/clock pins.  
Figure 3 illustrates the architecture for input pins. Four input  
options are available for the user: combinatorial, registered,  
double-registered, or latched. If a registered or latched option  
is selected, any one of the input clocks can be selected for  
control.  
The Ultra37000 features:  
• No fanout delays  
• No expander delays  
Figure 4 illustrates the architecture for the input/clock pins.  
Like the input pins, input/clock pins can be combinatorial,  
registered, double-registered, or latched. In addition, these  
pins feed the clocking structures throughout the device. The  
clock path at the input has user-configurable polarity.  
• No dedicated vs. I/O pin delays  
• No additional delay through PIM  
• No penalty for using 0–16 product terms  
• No added delay for steering product terms  
• No added delay for sharing product terms  
• No routing delays  
Product Term Clocking  
In addition to the four synchronous clocks, the Ultra37000  
family also has a product term clock for asynchronous  
clocking. Each logic block has an independent product term  
clock which is available to all 16 macrocells. Each product term  
clock also supports user configurable polarity selection.  
• No output bypass delays  
The simple timing model of the Ultra37000 family eliminates  
unexpected performance penalties.  
Document #: 38-03007 Rev. *E  
Page 6 of 64  
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Ultra37000 CPLD Family  
resources for pinout flexibility, and a simple timing model for  
consistent system performance.  
COMBINATORIAL SIGNAL  
PD = 6.5 ns  
t
INPUT  
Development Software Support  
OUTPUT  
OUTPUT  
Warp  
REGISTERED SIGNAL  
Warp is a state-of-the-art compiler and complete CPLD design  
tool. For design entry, Warp provides an IEEE-STD-1076/1164  
VHDL text editor, an IEEE-STD-1364 Verilog text editor, and a  
graphical finite state machine editor. It provides optimized  
synthesis and fitting by replacing basic circuits with ones  
pre-optimized for the target device, by implementing logic in  
unused memory and by perfect communication between fitting  
and synthesis. To facilitate design and debugging, Warp  
provides graphical timing simulation and analysis.  
tS = 3.5 ns  
t
CO = 4.5 ns  
D,T,L  
O
INPUT  
CLOCK  
Figure 5. Timing Model for CY37128  
JTAG and PCI Standards  
Warp Professional™  
PCI Compliance  
Warp Professional contains several additional features. It  
provides an extra method of design entry with its graphical  
block diagram editor. It allows up to 5 ms timing simulation  
instead of only 2 ms. It allows comparison of waveforms before  
and after design changes.  
5V operation of the Ultra37000 is fully compliant with the PCI  
Local Bus Specification published by the PCI Special Interest  
Group. The 3.3V products meet all PCI requirements except  
for the output 3.3V clamp, which is in direct conflict with 5V  
tolerance. The Ultra37000 family’s simple and predictable  
timing model ensures compliance with the PCI AC specifica-  
tions independent of the design.  
Warp Enterprise™  
Warp Enterprise provides even more features. It provides  
unlimited timing simulation and source-level behavioral  
simulation as well as a debugger. It has the ability to generate  
graphical HDL blocks from HDL text. It can even generate  
testbenches.  
IEEE 1149.1-compliant JTAG  
The Ultra37000 family has an IEEE 1149.1 JTAG interface for  
both Boundary Scan and ISR.  
Warp is available for PC and UNIX platforms. Some features  
are not available in the UNIX version. For further information  
see the Warp for PC, Warp for UNIX, Warp Professional and  
Warp Enterprise data sheets on Cypress’s web site  
(www.cypress.com).  
Boundary Scan  
The Ultra37000 family supports Bypass, Sample/Preload,  
Extest, Idcode, and Usercode boundary scan instructions. The  
JTAG interface is shown in Figure 6.  
Third-Party Software  
Instruction Register  
Although Warp is a complete CPLD development tool on its  
own, it interfaces with nearly every third party EDA tool. All  
major third-party software vendors provide support for the  
Ultra37000 family of devices. Refer to the third-party software  
data sheet or contact your local sales office for a list of  
currently supported third-party vendors.  
TDI  
TDO  
Bypass Reg.  
JTAG  
TMS  
TAP  
CONTROLLER  
Boundary Scan  
idcode  
TCK  
Programming  
There are four programming options available for Ultra37000  
devices. The first method is to use a PC with the 37000  
UltraISR programming cable and software. With this method,  
the ISR pins of the Ultra37000 devices are routed to a  
connector at the edge of the printed circuit board. The 37000  
UltraISR programming cable is then connected between the  
parallel port of the PC and this connector. A simple configu-  
ration file instructs the ISR software of the programming  
operations to be performed on each of the Ultra37000 devices  
in the system. The ISR software then automatically completes  
all of the necessary data manipulations required to accomplish  
the programming, reading, verifying, and other ISR functions.  
For more information on the Cypress ISR Interface, see the  
ISR Programming Kit data sheet (CY3700i).  
Usercode  
ISR Prog.  
Data Registers  
Figure 6. JTAG Interface  
In-System Reprogramming (ISR)  
In-System Reprogramming is the combination of the capability  
to program or reprogram a device on-board, and the ability to  
support design changes without changing the system timing  
or device pinout. This combination means design changes  
during debug or field upgrades do not cause board respins.  
The Ultra37000 family implements ISR by providing a JTAG  
compliant interface for on-board programming, robust routing  
The second method for programming Ultra37000 devices is on  
automatic test equipment (ATE). This is accomplished through  
a file created by the ISR software. Check the Cypress website  
for the latest ISR software download information.  
Document #: 38-03007 Rev. *E  
Page 7 of 64  
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Ultra37000 CPLD Family  
The third programming option for Ultra37000 devices is to  
utilize the embedded controller or processor that already  
exists in the system. The Ultra37000 ISR software assists in  
this method by converting the device JEDEC maps into the  
ISR serial stream that contains the ISR instruction information  
and the addresses and data of locations to be programmed.  
The embedded controller then simply directs this ISR stream  
to the chain of Ultra37000 devices to complete the desired  
reconfiguring or diagnostic operations. Contact your local  
sales office for information on availability of this option.  
The fourth method for programming Ultra37000 devices is to  
use the same programmer that is currently being used to  
program FLASH370i devices.  
For all pinout, electrical, and timing requirements, refer to  
device data sheets. For ISR cable and software specifications,  
refer to the UltraISR kit data sheet (CY3700i).  
Third-Party Programmers  
As with development software, Cypress support is available on  
a wide variety of third-party programmers. All major third-party  
programmers (including BP Micro, Data I/O, and SMS) support  
the Ultra37000 family.  
Document #: 38-03007 Rev. *E  
Page 8 of 64  
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Ultra37000 CPLD Family  
Logic Block Diagrams  
CY37032/CY37032V  
Clock/  
Input  
Input  
1
TDI  
TCK  
TMS  
JTAG Tap  
Controller  
TDO  
4
JTAG  
EN  
4
4
36  
16  
36  
16  
LOGIC  
BLOCK  
A
LOGIC  
BLOCK  
B
16 I/Os  
16 I/Os  
15  
PIM  
I/O −I/O  
I/O −I/O  
16  
31  
0
16  
16  
Clock/  
Input  
CY37064/CY37064V  
Input  
4
1
4
4
36  
36  
LOGIC  
BLOCK  
A
LOGIC  
BLOCK  
D
16 I/Os  
16 I/Os  
16 I/Os  
I/O -I/O  
0
I/O -I/O  
48  
15  
16  
36  
16  
16  
36  
63  
PIM  
16 I/Os  
LOGIC  
BLOCK  
B
LOGIC  
BLOCK  
C
I/O -I/O  
32  
I/O -I/O  
16  
16  
47  
31  
32  
32  
TDI  
JTAG Tap  
Controller  
TCK  
TMS  
TDO  
Document #: 38-03007 Rev. *E  
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Ultra37000 CPLD Family  
Logic Block Diagrams (continued)  
TDI  
JTAG Tap  
CY37128/CY37128V  
CLOCK  
INPUTS  
TCK  
TMS  
TDO  
INPUTS  
1
Controller  
4
INPUT/CLOCK  
MACROCELLS  
JTAG  
EN  
INPUT  
MACROCELL  
4
4
16 I/Os  
LOGIC  
BLOCK  
A
LOGIC  
BLOCK  
H
16 I/Os  
I/O0–I/O15  
36  
16  
36  
16  
I/O112–I/O127  
I/O96–I/O111  
I/O80–I/O95  
I/O64–I/O79  
PIM  
LOGIC  
BLOCK  
B
LOGIC  
BLOCK  
G
16 I/Os  
16 I/Os  
16 I/Os  
36  
16  
36  
16  
I/O16–I/O31  
16 I/Os  
LOGIC  
BLOCK  
C
LOGIC  
BLOCK  
F
36  
16  
36  
16  
I/O32–I/O47  
16 I/Os  
LOGIC  
BLOCK  
D
LOGIC  
BLOCK  
E
16 I/Os  
36  
16  
36  
16  
I/O28–I/O63  
64  
64  
Clock/  
Input  
CY37192/CY37192V  
Input  
4
1
4
4
36  
36  
LOGIC  
LOGIC  
BLOCK  
L
10 I/Os  
I/O –I/O  
10 I/Os  
9
BLOCK  
A
16  
36  
16  
36  
16  
36  
I/O –I/O  
110  
119  
0
10 I/Os  
I/O –I/O  
10 I/Os  
LOGIC  
BLOCK  
B
LOGIC  
BLOCK  
K
16  
36  
16  
36  
16  
I/O –I/O  
10  
100  
109  
19  
10 I/Os  
I/O –I/O  
10 I/Os  
LOGIC  
BLOCK  
C
LOGIC  
BLOCK  
J
I/O –I/O  
20  
16  
36  
16  
36  
16  
90  
99  
29  
PIM  
10 I/Os  
I/O –I/O  
10 I/Os  
39  
LOGIC  
BLOCK  
D
LOGIC  
BLOCK  
I
I/O –I/O  
30  
80  
89  
36  
16  
36  
10 I/Os  
I/O –I/O  
10 I/Os  
49  
LOGIC  
BLOCK  
E
LOGIC  
BLOCK  
H
I/O –I/O  
40  
70  
79  
69  
36  
16  
10 I/Os  
I/O –I/O  
10 I/Os  
LOGIC  
BLOCK  
F
LOGIC  
BLOCK  
G
I/O –I/O  
50  
16  
60  
59  
60  
60  
TDI  
TCK  
TMS  
JTAG Tap  
Controller  
TDO  
Document #: 38-03007 Rev. *E  
Page 10 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Logic Block Diagrams (continued)  
Clock/  
Input  
Input  
1
CY37256/CY37256V  
4
4
4
36  
16  
36  
16  
36  
36  
LOGIC  
BLOCK  
A
LOGIC  
BLOCK  
P
12 I/Os  
11  
12 I/Os  
I/O −I/O  
16  
36  
I/O −I/O  
180  
191  
179  
0
12 I/Os  
I/O −I/O  
12 I/Os  
LOGIC  
BLOCK  
B
LOGIC  
BLOCK  
O
16  
36  
16  
36  
16  
I/O −I/O  
168  
12  
23  
12 I/Os  
I/O −I/O  
12 I/Os  
LOGIC  
BLOCK  
C
LOGIC  
BLOCK  
N
I/O −I/O  
16  
36  
16  
36  
16  
156  
167  
155  
24  
35  
12 I/Os  
I/O −I/O  
12 I/Os  
47  
LOGIC  
BLOCK  
D
LOGIC  
BLOCK  
M
I/O −I/O  
144  
36  
PIM  
36  
16  
36  
12 I/Os  
I/O −I/O  
12 I/Os  
59  
LOGIC  
BLOCK  
E
LOGIC  
BLOCK  
L
I/O −I/O  
48  
132  
143  
131  
36  
16  
12 I/Os  
I/O −I/O  
12 I/Os  
LOGIC  
BLOCK  
F
LOGIC  
BLOCK  
K
I/O −I/O  
16  
36  
16  
120  
60  
71  
36  
16  
36  
12 I/Os  
I/O −I/O  
12 I/Os  
83  
LOGIC  
BLOCK  
G
LOGIC  
BLOCK  
J
I/O −I/O  
72  
108  
119  
36  
16  
12 I/Os  
I/O −I/O  
12 I/Os  
LOGIC  
BLOCK  
H
LOGIC  
BLOCK  
I
16  
I/O −I/O  
96  
107  
84  
95  
TDI  
TCK  
TMS  
96  
96  
JTAG Tap  
Controller  
TDO  
Document #: 38-03007 Rev. *E  
Page 11 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Logic Block Diagrams (continued)  
Clock/  
Input  
CY37384/CY37384V  
Input  
1
4
4
4
36  
16  
36  
16  
36  
16  
36  
16  
36  
LOGIC  
BLOCK  
AA  
LOGIC  
BLOCK  
BL  
12 I/Os  
I/O0−I/O11  
16  
36  
12 I/Os  
I/O168−I/O191  
12 I/Os  
I/O12−I/O23  
LOGIC  
BLOCK  
AB  
LOGIC  
BLOCK  
BK  
16  
36  
16  
36  
16  
36  
12 I/Os  
I/O156−I/O179  
12 I/Os  
I/O24−I/O35  
LOGIC  
BLOCK  
AC  
LOGIC  
BLOCK  
BJ  
12 I/Os  
I/O144−I/O167  
LOGIC  
BLOCK  
AD  
LOGIC  
BLOCK  
BI  
36  
16  
PIM  
12 I/Os  
I/O36−I/O47  
LOGIC  
BLOCK  
AE  
LOGIC  
BLOCK  
BH  
16  
36  
16  
36  
16  
12 I/Os  
I/O132−I/O155  
LOGIC  
BLOCK  
AF  
LOGIC  
BLOCK  
BG  
36  
16  
36  
16  
36  
16  
36  
16  
12 I/Os  
I/O48−I/O59  
LOGIC  
BLOCK  
AG  
LOGIC  
BLOCK  
BF  
36  
16  
12 I/Os  
I/O120−I/O143  
12 I/Os  
I/O60−I/O71  
LOGIC  
BLOCK  
AH  
LOGIC  
BLOCK  
BE  
36  
16  
12 I/Os  
I/O108−I/O131  
12 I/Os  
I/O72−I/O83  
LOGIC  
BLOCK  
AI  
LOGIC  
BLOCK  
BD  
36  
16  
36  
16  
12 I/Os  
I/O96−I/O119  
LOGIC  
BLOCK  
AJ  
LOGIC  
BLOCK  
BC  
36  
16  
36  
16  
12 I/Os  
I/O84−I/O95  
LOGIC  
BLOCK  
AK  
LOGIC  
BLOCK  
BB  
36  
16  
36  
16  
12 I/Os  
I/O96−I/O107  
LOGIC  
BLOCK  
AL  
LOGIC  
BLOCK  
BA  
TDI  
TCK  
TMS  
JTAG Tap  
Controller  
96  
96  
TDO  
Document #: 38-03007 Rev. *E  
Page 12 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Logic Block Diagrams (continued)  
CY37512/CY37512V  
Input  
Clock/ Input  
4
1
4
4
36  
36  
LOGIC  
BLOCK  
AA  
LOGIC  
BLOCK  
BP  
12 I/Os  
I/O0−I/O11  
16  
36  
16  
36  
16  
36  
16  
36  
16  
16  
36  
12 I/Os  
12 I/Os  
LOGIC  
BLOCK  
AB  
LOGIC  
BLOCK  
BO  
16  
36  
16  
36  
16  
I/O252−I/O263  
I/O12−I/O23  
12 I/Os  
12 I/Os  
LOGIC  
BLOCK  
AC  
LOGIC  
BLOCK  
BN  
I/O24−I/O35  
I/O240−I/O251  
12 I/Os  
LOGIC  
BLOCK  
AD  
LOGIC  
BLOCK  
BM  
I/O228−I/O239  
36  
16  
36  
16  
LOGIC  
BLOCK  
AE  
LOGIC  
BLOCK  
BL  
12 I/Os  
I/O36−I/O47  
36  
16  
12 I/Os  
LOGIC  
BLOCK  
AF  
LOGIC  
BLOCK  
BK  
I/O216−I/O227  
36  
16  
36  
16  
36  
LOGIC  
BLOCK  
AG  
LOGIC  
BLOCK  
BJ  
12 I/Os  
I/O48−I/O59  
36  
12 I/Os  
LOGIC  
BLOCK  
AH  
LOGIC  
BLOCK  
BI  
I/O204−I/O215  
16  
36  
16  
36  
PIM  
12 I/Os  
I/O60−I/O71  
LOGIC  
BLOCK  
AI  
LOGIC  
BLOCK  
BH  
16  
36  
16  
36  
12 I/Os  
LOGIC  
BLOCK  
AJ  
LOGIC  
BLOCK  
BG  
I/O192−I/O203  
16  
36  
16  
36  
12 I/Os  
I/O72−I/O83  
LOGIC  
BLOCK  
AK  
LOGIC  
BLOCK  
BF  
16  
36  
16  
36  
12 I/Os  
12 I/Os  
I/O84−I/O95  
LOGIC  
BLOCK  
AL  
LOGIC  
BLOCK  
BE  
I/O180−I/O191  
16  
36  
16  
36  
12 I/Os  
LOGIC  
BLOCK  
AM  
LOGIC  
BLOCK  
BD  
12 I/Os  
I/O96−I/O107  
I/O168−I/O179  
16  
36  
16  
36  
12 I/Os  
12 I/Os  
I/O108−I/O119  
LOGIC  
BLOCK  
AN  
LOGIC  
BLOCK  
BC  
I/O156−I/O167  
16  
36  
16  
36  
12 I/Os  
12 I/Os  
I/O120−I/O131  
LOGIC  
BLOCK  
AO  
LOGIC  
BLOCK  
BB  
I/O144−I/O155  
16  
36  
16  
36  
12 I/Os  
LOGIC  
BLOCK  
AP  
LOGIC  
BLOCK  
BA  
I/O132−I/O143  
16  
16  
132  
132  
TDI  
TCK  
TMS  
JTAG Tap  
Controller  
TDO  
Document #: 38-03007 Rev. *E  
Page 13 of 64  
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Ultra37000 CPLD Family  
DC Voltage Applied to Outputs  
5.0V Device Characteristics  
Maximum Ratings  
in High-Z State................................................–0.5V to +7.0V  
DC Input Voltage ............................................–0.5V to +7.0V  
DC Program Voltage............................................. 4.5 to 5.5V  
Current into Outputs .................................................... 16 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Storage Temperature .................................–65°C to +150°C  
Static Discharge Voltage...........................................> 2001V  
(per MIL-STD-883, Method 3015)  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Latch-up Current.....................................................> 200 mA  
Supply Voltage to Ground Potential............... –0.5V to +7.0V  
Operating Range[2]  
[2]  
Range  
Ambient Temperature  
Junction Temperature Output Condition  
V
V
CCO  
CC  
Commercial  
0°C to +70°C  
0°C to +90°C  
–40°C to +105°C  
–55°C to +130°C  
5V  
3.3V  
5V  
5V ± 0.25V  
5V ± 0.25V  
5V ± 0.5V  
5V ± 0.5V  
5V ± 0.5V  
5V ± 0.5V  
5V ± 0.25V  
3.3V ± 0.3V  
5V ± 0.5V  
Industrial  
–40°C to +85°C  
–55°C to +125°C  
3.3V  
5V  
3.3V ± 0.3V  
5V ± 0.5V  
[3]  
Military  
3.3V  
3.3V ± 0.3V  
5.0V Device Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Test Conditions  
Min. Typ. Max. Unit  
[4]  
V
Output HIGH Voltage  
V
= Min.  
I = –3.2 mA (Com’l/Ind)  
OH  
2.4  
2.4  
V
V
OH  
CC  
CC  
[4]  
I
I
I
I
I
I
I
= –2.0 mA (Mil)  
OH  
OH  
OH  
OH  
OH  
OL  
OL  
[6]  
V
Output HIGH Voltage with  
V
= Max.  
= 0 µA (Com’l)  
4.2  
4.5  
3.6  
3.6  
0.5  
0.5  
V
OHZ  
[5]  
Output Disabled  
[6]  
= 0 µA (Ind/Mil)  
V
[6]  
= –100 µA (Com’l)  
V
[6]  
= –150 µA (Ind/Mil)  
V
[4]  
V
Output LOW Voltage  
V
= Min.  
= 16 mA (Com’l/Ind)  
V
OL  
CC  
[4]  
= 12 mA (Mil)  
V
[7]  
V
V
I
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
Output Leakage Current  
Guaranteed Input Logical HIGH Voltage for all Inputs  
2.0  
–0.5  
–10  
V
V
IH  
CCmax  
[7]  
Guaranteed Input Logical LOW Voltage for all Inputs  
V = GND OR V , Bus-Hold Disabled  
0.8  
V
IL  
10  
50  
µA  
µA  
IX  
I
CC  
I
I
I
V
V
V
= GND or V , Output Disabled, Bus-Hold Disabled –50  
CC  
OZ  
O
[5, 8]  
OutputShortCircuitCurrent  
= Max., V = 0.5V  
OUT  
–30  
+75  
–160 mA  
OS  
CC  
CC  
Input Bus-Hold LOW  
Sustaining Current  
= Min., V = 0.8V  
µA  
BHL  
IL  
I
I
I
Input Bus-Hold HIGH  
Sustaining Current  
V
V
V
= Min., V = 2.0V  
–75  
µA  
+500 µA  
–500 µA  
BHH  
CC  
CC  
CC  
IH  
Input Bus-Hold LOW  
Overdrive Current  
= Max.  
= Max.  
BHLO  
BHHO  
Input Bus-Hold HIGH  
Overdrive Current  
Notes:  
2. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the  
Ultra37000 Family devices, please refer to the Application Note titled “An Introduction to In System Reprogramming with the Ultra37000.”  
3. T is the “Instant On” case temperature.  
A
4. I = –2 mA, I = 2 mA for TDO.  
OH  
OL  
5. Tested initially and after any design or process changes that may affect these parameters.  
6. When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to above 3.6V if no leakage current is allowed. Note that all I/Os are output disabled  
during ISR programming. Refer to the application note “Understanding Bus-Hold” for additional information.  
7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.  
8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V  
problems caused by tester ground degradation.  
= 0.5V has been chosen to avoid test  
OUT  
Document #: 38-03007 Rev. *E  
Page 14 of 64  
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Ultra37000 CPLD Family  
Inductance[5]  
44-Lead 44-Lead 44-Lead 84-Lead 84-Lead 100-Lead 160-Lead 208-Lead  
Parameter Description Test Conditions TQFP PLCC CLCC PLCC CLCC TQFP  
TQFP  
PQFP Unit  
L
MaximumPin V = 5.0V  
Inductance at f = 1 MHz  
2
5
2
8
5
8
9
11 nH  
IN  
Capacitance[5]  
Parameter  
Description  
Test Conditions  
= 5.0V at f = 1 MHz at T = 25°C  
Max.  
Unit  
C
C
C
Input/Output Capacitance  
Clock Signal Capacitance  
V
V
V
10  
12  
16  
pF  
pF  
pF  
I/O  
IN  
IN  
IN  
A
= 5.0V at f = 1 MHz at T = 25°C  
CLK  
DP  
A
[9]  
Dual-Function Pins  
= 5.0V at f = 1 MHz at T = 25°C  
A
Endurance Characteristics[5]  
Parameter  
Description  
Minimum Reprogramming Cycles  
Test Conditions  
Min.  
1,000  
Typ.  
Unit  
Cycles  
[2]  
N
Normal Programming Conditions  
10,000  
DC Voltage Applied to Outputs  
3.3V Device Characteristics  
Maximum Ratings  
in High-Z State................................................–0.5V to +7.0V  
DC Input Voltage ............................................–0.5V to +7.0V  
DC Program Voltage............................................. 3.0 to 3.6V  
Current into Outputs ...................................................... 8 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Storage Temperature .................................–65°C to +150°C  
Static Discharge Voltage...........................................> 2001V  
(per MIL-STD-883, Method 3015)  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Latch-up Current.....................................................> 200 mA  
Supply Voltage to Ground Potential............... –0.5V to +4.6V  
Operating Range[2]  
[2]  
[10]  
Range  
Ambient Temperature  
0°C to +70°C  
Junction Temperature  
0°C to +90°C  
V
CC  
Commercial  
Industrial  
3.3V ± 0.3V  
3.3V ± 0.3V  
3.3V ± 0.3V  
–40°C to +85°C  
–55°C to +125°C  
–40°C to +105°C  
–55°C to +130°C  
[3]  
Military  
3.3V Device Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Output HIGH Voltage  
Test Conditions  
Min.  
Max.  
Unit  
[4]  
V
V
V
V
= Min.  
= Min.  
I
I
I
I
= –4 mA (Com’l)  
2.4  
V
OH  
CC  
OH  
OH  
OL  
OL  
[4]  
= –3 mA (Mil)  
[4]  
Output LOW Voltage  
= 8 mA (Com’l)  
0.5  
V
OL  
CC  
[4]  
= 6 mA (Mil)  
V
V
I
Input HIGH Voltage  
Input LOW Voltage  
Guaranteed Input Logical HIGH Voltage for  
all Inputs  
2.0  
5.5  
0.8  
V
V
IH  
[7]  
Guaranteed Input Logical LOW Voltage for  
–0.5  
IL  
[7]  
all Inputs  
Input Load Current  
V = GND OR V , Bus-Hold Disabled  
–10  
–50  
10  
50  
µA  
IX  
I
CC  
I
Output Leakage Current  
V
= GND or V , Output Disabled,  
µA  
OZ  
O
CC  
Bus-Hold Disabled  
[5, 8]  
I
I
I
I
I
Output Short Circuit Current  
V
= Max., V  
= 0.5V  
OUT  
–30  
+75  
–75  
–160  
mA  
µA  
µA  
µA  
µA  
OS  
CC  
Input Bus-Hold LOW Sustaining Current V = Min., V = 0.8V  
BHL  
CC  
IL  
Input Bus-Hold HIGH Sustaining Current V = Min., V = 2.0V  
BHH  
BHLO  
BHHO  
CC  
CC  
IH  
Input Bus-Hold LOW Overdrive Current  
V
= Max.  
+500  
–500  
Input Bus-Hold HIGH Overdrive Current V = Max.  
CC  
Notes:  
9. Dual pins are I/O with JTAG pins.  
10. For CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143BAC; Operating Range: V is 3.3V± 0.16V.  
CC  
Document #: 38-03007 Rev. *E  
Page 15 of 64  
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Ultra37000 CPLD Family  
Inductance[5]  
44-  
44-  
44-  
84-  
84-  
100-  
160-  
208-  
Lead  
Lead  
Lead  
Lead  
Lead  
Lead  
Lead  
Lead  
Parameter Description Test Conditions  
TQFP PLCC CLCC PLCC CLCC TQFP TQFP PQFP Unit  
L
Maximum Pin V = 3.3V  
2
5
2
8
5
8
9
11  
nH  
IN  
Inductance  
at f = 1 MHz  
Capacitance[5]  
Parameter  
Description  
Test Conditions  
= 3.3V at f = 1 MHz at T = 25°C  
Max.  
8
Unit  
C
C
C
Input/Output Capacitance  
Clock Signal Capacitance  
V
V
V
pF  
pF  
pF  
I/O  
IN  
IN  
IN  
A
= 3.3V at f = 1 MHz at T = 25°C  
12  
CLK  
DP  
A
[9]  
Dual Functional Pins  
= 3.3V at f = 1 MHz at T = 25°C  
16  
A
Endurance Characteristics[5]  
Parameter  
Description  
Minimum Reprogramming Cycles  
Test Conditions  
Min.  
Typ.  
10,000  
Unit  
Cycles  
[2]  
N
Normal Programming Conditions  
1,000  
AC Characteristics  
5.0V AC Test Loads and Waveforms  
238Ω (COM'L)  
319Ω (MIL)  
3.0V  
238Ω (COM'L)  
319Ω (MIL)  
ALL INPUT PULSES  
5V  
5V  
90%  
10%  
90%  
10%  
OUTPUT  
OUTPUT  
170Ω (COM'L)  
236Ω (MIL)  
170Ω (COM'L)  
236Ω (MIL)  
GND  
<2 ns  
35 pF  
5 pF  
<2 ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
(a)  
(b)  
(c)  
Equivalent to:  
THÉVENIN EQUIVALENT  
99Ω (COM'L)  
136Ω (MIL)  
2.08V (COM'L)  
2.13V (MIL)  
OUTPUT  
5 OR 35 pF  
3.3V AC Test Loads and Waveforms  
295Ω (COM'L)  
393Ω (MIL)  
295Ω (COM'L)  
ALL INPUT PULSES  
393Ω (MIL)  
3.3V  
3.3V  
OUTPUT  
3.0V  
GND  
90%  
10%  
90%  
10%  
OUTPUT  
340Ω (COM'L)  
453Ω (MIL)  
340Ω (COM'L)  
453Ω (MIL)  
35 pF  
5 pF  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
<2 ns  
<2 ns  
(a)  
(b)  
(c)  
Equivalent to:  
THÉVENIN EQUIVALENT  
158Ω (COM’L)  
270Ω (MIL)  
1.77V (COM'L)  
1.77V (MIL)  
OUTPUT  
5 OR 35 pF  
Document #: 38-03007 Rev. *E  
Page 16 of 64  
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Ultra37000 CPLD Family  
[11]  
Parameter  
V
Output Waveform—Measurement Level  
X
t
1.5V  
2.6V  
1.5V  
ER(–)  
V
OH  
0.5V  
0.5V  
V
V
X
X
t
ER(+)  
V
V
OL  
X
t
EA(+)  
EA(–)  
V
OH  
0.5V  
t
V
the  
V
X
0.5V  
V
OL  
(d) Test Waveforms  
[12]  
Switching Characteristics Over the Operating Range  
Parameter  
Description  
Unit  
Combinatorial Mode Parameters  
[13, 14, 15]  
t
t
t
t
t
Input to Combinatorial Output  
ns  
ns  
ns  
ns  
ns  
PD  
[13, 14, 15]  
[13, 14, 15]  
Input to Output Through Transparent Input or Output Latch  
Input to Output Through Transparent Input and Output Latches  
Input to Output Enable  
PDL  
PDLL  
[13, 14, 15]  
EA  
ER  
[11, 13]  
Input to Output Disable  
Input Register Parameters  
[8]  
t
t
t
t
t
t
Clock or Latch Enable Input LOW Time  
ns  
ns  
ns  
ns  
ns  
ns  
WL  
WH  
IS  
[8]  
Clock or Latch Enable Input HIGH Time  
Input Register or Latch Set-up Time  
Input Register or Latch Hold Time  
IH  
[13, 14, 15]  
[13, 14, 15]  
Input Register Clock or Latch Enable to Combinatorial Output  
Input Register Clock or Latch Enable to Output Through Transparent Output Latch  
ICO  
ICOL  
Synchronous Clocking Parameters  
[14, 15]  
t
t
t
t
Synchronous Clock (CLK , CLK , CLK , or CLK ) or Latch Enable to Output  
ns  
ns  
ns  
CO  
0
1
2
3
[13]  
Set-Up Time from Input to Sync. Clk (CLK , CLK , CLK , or CLK ) or Latch Enable  
S
0
1
2
3
Register or Latch Data Hold Time  
H
[13, 14, 15]  
[13]  
Output Synchronous Clock (CLK , CLK , CLK , or CLK ) or Latch Enable to Combinatorial Output ns  
CO2  
0
1
2
3
Delay (Through Logic Array)  
t
t
t
Output Synchronous Clock (CLK , CLK , CLK , or CLK ) or Latch Enable to Output Synchronous  
ns  
ns  
ns  
SCS  
0
1
2
3
Clock (CLK , CLK , CLK , or CLK ) or Latch Enable (Through Logic Array)  
0
1
2
3
[13]  
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK  
SL  
0
CLK , CLK , or CLK ) or Latch Enable  
1
2
3
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK ,  
HL  
0
CLK , CLK , or CLK ) or Latch Enable  
1
2
3
Notes:  
11. t measured with 5-pF AC Test Load and t measured with 35-pF AC Test Load.  
ER  
EA  
12. All AC parameters are measured with two outputs switching and 35-pF AC Test Load.  
13. Logic Blocks operating in Low-Power Mode, add t to this spec.  
LP  
14. Outputs using Slow Output Slew Rate, add t  
to this spec.  
SLEW  
15. When V  
= 3.3V, add t  
to this spec.  
CCO  
3.3IO  
Document #: 38-03007 Rev. *E  
Page 17 of 64  
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Ultra37000 CPLD Family  
[12]  
Switching Characteristics Over the Operating Range (continued)  
Parameter  
Description  
Unit  
Product Term Clocking Parameters  
[13, 14, 15]  
t
t
t
t
Product Term Clock or Latch Enable (PTCLK) to Output  
ns  
COPT  
SPT  
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)  
Register or Latch Data Hold Time  
ns  
ns  
ns  
HPT  
[13]  
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or  
Latch Enable (PTCLK)  
ISPT  
t
t
Buried Register Used as an Input Register or Latch Data Hold Time  
ns  
ns  
IHPT  
[13, 14, 15]  
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)  
CO2PT  
Pipelined Mode Parameters  
[13]  
t
Input Register Synchronous Clock (CLK , CLK , CLK , or CLK ) to Output Register Synchronous  
ns  
ICS  
0
1
2
3
Clock (CLK , CLK , CLK , or CLK )  
0
1
2
3
Operating Frequency Parameters  
[5]  
f
f
Maximum Frequency with Internal Feedback (Lesser of 1/t  
, 1/(t + t ), or 1/t )  
CO  
MHz  
MHz  
MAX1  
MAX2  
SCS  
S
H
Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(t + t ),  
WL  
WH  
[5]  
1/(t + t ), or 1/t )  
S
H
CO  
[5]  
f
f
Maximum Frequency with External Feedback (Lesser of 1/(t + t ) or 1/(t + t  
)
MHz  
MAX3  
CO  
S
WL  
WH  
Maximum Frequency in Pipelined Mode (Lesser of 1/(t + t ), 1/t , 1/(t + t ), 1/(t + t ), MHz  
MAX4  
CO  
IS  
ICS  
WL  
WH  
IS  
IH  
[5]  
or 1/t  
)
SCS  
Reset/Preset Parameters  
[5]  
t
t
t
t
t
t
Asynchronous Reset Width  
ns  
ns  
ns  
ns  
ns  
ns  
RW  
[13]  
[5]  
Asynchronous Reset Recovery Time  
Asynchronous Reset to Output  
RR  
[13, 14, 15]  
RO  
[5]  
Asynchronous Preset Width  
PW  
[13]  
[5]  
Asynchronous Preset Recovery Time  
Asynchronous Preset to Output  
PR  
PO  
[13, 14, 15]  
User Option Parameters  
t
t
t
Low Power Adder  
ns  
ns  
ns  
LP  
Slow Output Slew Rate Adder  
SLEW  
3.3IO  
[5]  
3.3V I/O Mode Timing Adder  
JTAG Timing Parameters  
[5]  
t
t
t
f
Set-up Time from TDI and TMS to TCK  
ns  
ns  
ns  
ns  
S JTAG  
H JTAG  
CO JTAG  
JTAG  
[5]  
Hold Time on TDI and TMS  
[5]  
Falling Edge of TCK to TDO  
[5]  
Maximum JTAG Tap Controller Frequency  
Document #: 38-03007 Rev. *E  
Page 18 of 64  
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Ultra37000 CPLD Family  
[12]  
Switching Characteristics Over the Operating Range  
200 MHz 167 MHz 154 MHz 143 MHz  
125 MHz  
100 MHz  
83 MHz  
66 MHz  
Parameter  
Unit  
Combinatorial Mode Parameters  
[13, 14, 15]  
t
t
t
t
t
6
11  
12  
8
6.5  
12.5  
13.5  
8.5  
7.5  
14.5  
15.5  
11  
8.5  
16  
17  
13  
13  
10  
12  
15  
20  
22  
24  
24  
24  
ns  
ns  
ns  
ns  
ns  
PD  
[13, 14, 15]  
[13, 14, 15]  
16.5  
17.5  
14  
17  
18  
16  
16  
19  
20  
19  
19  
PDL  
PDLL  
[13, 14, 15]  
EA  
ER  
[11, 13]  
8
8.5  
11  
14  
Input Register Parameters  
t
t
t
t
t
t
2.5  
2.5  
2
2.5  
2.5  
2
2.5  
2.5  
2
2.5  
2.5  
2
3
3
2
2
3
4
4
3
3
5
ns  
ns  
ns  
ns  
ns  
ns  
WL  
WH  
IS  
3
5
2.5  
2.5  
4
2
2
2
2
4
IH  
[13, 14, 15]  
[13, 14, 15]  
11  
12  
11  
12  
11  
12  
12.5  
14  
12.5  
16  
16  
18  
19  
21  
24  
26  
ICO  
ICOL  
Synchronous Clocking Parameters  
[14, 15]  
[16]  
[17]  
[18]  
t
t
t
t
t
t
t
4
4
4.5  
11  
6
6.5  
6.5  
8
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CO  
[13]  
[16]  
[17]  
[18]  
4
0
4
0
5
0
5
0
5.5  
6
8
10  
0
S
0
0
0
H
[13, 14, 15]  
[13]  
9.5  
10  
12  
14  
13  
19  
16  
13  
21  
19  
15  
24  
24  
15  
15  
0
CO2  
[16]  
5
7.5  
0
6
7.5  
0
6.5  
8.5  
0
7
9
0
8
10  
12  
0
12  
15  
0
SCS  
[13]  
10  
0
SL  
HL  
Product Term Clocking Parameters  
[13, 14, 15]  
t
t
t
t
t
t
7
10  
14  
10  
15  
13  
19  
20  
ns  
ns  
ns  
ns  
ns  
ns  
COPT  
SPT  
2.5  
2.5  
0
2.5  
2.5  
0
2.5  
2.5  
0
3
3
5
5
0
9
5.5  
5.5  
0
6
6
7
7
HPT  
[13]  
0
0
0
ISPT  
6
6.5  
6.5  
7.5  
11  
14  
19  
30  
IHPT  
[13, 14,  
12  
CO2PT  
15]  
Pipelined Mode Parameters  
[13]  
[16]  
t
5
6
6
7
8
10  
12  
83  
15  
ns  
ICS  
Operating Frequency Parameters  
[16]  
f
f
f
f
200  
200  
125  
167  
167  
200  
125  
167  
154  
200  
105  
154  
143  
167  
91  
125  
154  
100  
66  
100  
50  
MHz  
MHz  
MHz  
MHz  
MAX1  
MAX2  
MAX3  
MAX4  
[17]  
[18]  
153  
125  
[17]  
83  
80  
100  
62.5  
83  
125  
118  
66  
Reset/Preset Parameters  
t
t
8
8
8
8
10  
12  
12  
14  
15  
17  
20  
22  
ns  
ns  
RW  
[13]  
RR  
10  
10  
10  
10  
Notes:  
16. The following values correspond to the CY37512 and CY37384 devices: t = 5 ns, t = 6.5 ns, t  
= 8.5 ns, t  
= 8.5 ns, f  
= 118 MHz.  
CO  
S
SCS  
ICS  
MAX1  
17. The following values correspond to the CY37192V and CY37256V devices: t = 6 ns, t = 7 ns, f  
= 143 MHz, f  
= 77 MHz, and f = 100 MHz; and  
CO  
S
MAX2  
MAX3  
MAX4  
for the CY37512 devices: t = 7 ns.  
S
18. The following values correspond to the CY37512V and CY37384V devices: t = 6.5 ns, t = 9.5 ns, and f = 105 MHz.  
CO  
S
MAX2  
Document #: 38-03007 Rev. *E  
Page 19 of 64  
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Ultra37000 CPLD Family  
[12]  
Switching Characteristics Over the Operating Range (continued)  
200 MHz 167 MHz 154 MHz 143 MHz 125 MHz  
100 MHz  
83 MHz  
66 MHz  
Parameter  
Unit  
ns  
[13, 14, 15]  
t
t
t
t
12  
13  
13  
13  
13  
14  
14  
15  
18  
21  
26  
20  
RO  
PW  
8
8
8
8
10  
12  
12  
14  
15  
17  
ns  
[13]  
10  
10  
10  
10  
22  
ns  
PR  
PO  
[13, 14, 15]  
12  
15  
18  
21  
26  
ns  
User Option Parameters  
t
t
t
2.5  
3
2.5  
3
2.5  
3
2.5  
3
2.5  
3
2.5  
3
2.5  
3
2.5 ns  
ns  
LP  
3
SLEW  
[19]  
0.3  
0.3  
0.3  
0.3  
0.3  
0.3  
0.3  
0.3 ns  
3.3IO  
JTAG Timing Parameters  
t
t
t
f
0
0
0
0
0
0
0
0
ns  
ns  
S JTAG  
H JTAG  
CO JTAG  
JTAG  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
ns  
20 MHz  
Switching Waveforms  
Combinatorial Output  
INPUT  
tPD  
COMBINATORIAL  
OUTPUT  
Registered Output with Synchronous Clocking  
INPUT  
tS  
tH  
SYNCHRONOUS  
CLOCK  
tCO  
REGISTERED  
OUTPUT  
tCO2  
REGISTERED  
OUTPUT  
tWH  
tWL  
SYNCHRONOUS  
CLOCK  
Note:  
19. Only applicable to the 5V devices.  
Document #: 38-03007 Rev. *E  
Page 20 of 64  
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Ultra37000 CPLD Family  
Switching Waveforms (continued)  
Registered Output with Product Term Clocking Input Going Through the Array  
INPUT  
tSPT  
tHPT  
PRODUCT TERM  
CLOCK  
tCOPT  
REGISTERED  
OUTPUT  
Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register  
INPUT  
tISPT  
tIHPT  
PRODUCT TERM  
CLOCK  
tCO2PT  
REGISTERED  
OUTPUT  
Latched Output  
INPUT  
tSL  
tHL  
LATCH ENABLE  
tPDL  
tCO  
LATCHED  
OUTPUT  
Document #: 38-03007 Rev. *E  
Page 21 of 64  
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Ultra37000 CPLD Family  
Switching Waveforms (continued)  
Registered Input  
REGISTERED  
INPUT  
tIS  
tIH  
INPUT REGISTER  
CLOCK  
tICO  
COMBINATORIAL  
OUTPUT  
tWH  
tWL  
CLOCK  
Clock to Clock  
INPUT REGISTER  
CLOCK  
tICS  
tSCS  
OUTPUT  
REGISTER CLOCK  
Latched Input  
LATCHED INPUT  
tIS  
tIH  
LATCH ENABLE  
tPDL  
tICO  
COMBINATORIAL  
OUTPUT  
tWH  
tWL  
LATCH ENABLE  
Document #: 38-03007 Rev. *E  
Page 22 of 64  
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Ultra37000 CPLD Family  
Switching Waveforms (continued)  
Latched Input and Output  
LATCHED INPUT  
tPDLL  
LATCHED  
OUTPUT  
tICOL  
tSL  
tHL  
INPUT LATCH  
ENABLE  
tICS  
OUTPUT LATCH  
ENABLE  
tWH  
tWL  
LATCH ENABLE  
Asynchronous Reset  
tRW  
INPUT  
tRO  
REGISTERED  
OUTPUT  
tRR  
CLOCK  
Asynchronous Preset  
tPW  
INPUT  
tPO  
REGISTERED  
OUTPUT  
tPR  
CLOCK  
Output Enable/Disable  
INPUT  
tER  
tEA  
OUTPUTS  
Document #: 38-03007 Rev. *E  
Page 23 of 64  
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Ultra37000 CPLD Family  
Power Consumption  
Typical 5.0V Power Consumption  
CY37032  
60  
50  
40  
30  
20  
10  
High Speed  
Low Power  
0
0
50  
100  
150  
200  
250  
Frequency (M Hz)  
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.  
V
= 5.0V, T = Room Temperature  
A
CC  
CY37064  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
High Speed  
Low Power  
0
20  
40  
60  
80  
100  
120  
140  
160  
180  
Frequency (M Hz)  
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.  
= 5.0V, T = Room Temperature  
V
CC  
A
Document #: 38-03007 Rev. *E  
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Ultra37000 CPLD Family  
Typical 5.0V Power Consumption (continued)  
CY37128  
160  
140  
120  
100  
80  
High Speed  
Low Power  
60  
40  
20  
0
0
20  
40  
60  
80  
100  
120  
140  
160  
180  
Frequency (M Hz)  
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.  
V
= 5.0V, T = Room Temperature  
A
CC  
CY37192  
300  
250  
200  
150  
100  
50  
High Speed  
Low Power  
0
0
20  
40  
60  
80  
100  
120  
140  
160  
180  
Frequency (M Hz)  
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.  
= 5.0V, T = Room Temperature  
V
CC  
A
Document #: 38-03007 Rev. *E  
Page 25 of 64  
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Ultra37000 CPLD Family  
Typical 5.0V Power Consumption (continued)  
CY37256  
300  
High Speed  
250  
200  
150  
100  
50  
Low Power  
0
0
20  
40  
60  
80  
100  
120  
140  
160  
180  
Frequency (M Hz)  
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.  
V
= 5.0V, T = Room Temperature  
A
CC  
CY37384  
500  
450  
400  
350  
300  
250  
200  
150  
100  
50  
High Speed  
Low Power  
0
0
20  
40  
60  
80  
100  
120  
140  
160  
Frequency (MHz)  
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.  
= 5.0V, T = Room Temperature  
V
CC  
A
Document #: 38-03007 Rev. *E  
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Ultra37000 CPLD Family  
Typical 5.0V Power Consumption (continued)  
CY37512  
600  
High Speed  
500  
400  
300  
200  
100  
0
Low Power  
0
20  
40  
60  
80  
100  
120  
140  
160  
Frequency (M Hz)  
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.  
V
= 5.0V, T = Room Temperature  
A
CC  
Typical 3.3V Power Consumption  
CY37032V  
30  
High Speed  
25  
20  
15  
10  
5
Low Power  
0
0
20  
40  
60  
80  
100  
120  
140  
160  
Frequency (MHz)  
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.  
= 3.3V, T = Room Temperature  
V
CC  
A
Document #: 38-03007 Rev. *E  
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Ultra37000 CPLD Family  
Typical 3.3V Power Consumption (continued)  
CY37064V  
45  
40  
35  
30  
25  
20  
15  
10  
5
High Speed  
Low Power  
0
0
20  
40  
60  
80  
100  
120  
140  
Frequency (MHz)  
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.  
V
= 3.3V, T = Room Temperature  
A
CC  
CY37128V  
80  
70  
60  
50  
40  
30  
20  
10  
0
H igh S peed  
Low P ow er  
0
20  
40  
60  
80  
100  
120  
140  
F re q u en c y (M H z)  
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.  
= 3.3V, T = Room Temperature  
V
CC  
A
Document #: 38-03007 Rev. *E  
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Ultra37000 CPLD Family  
Typical 3.3V Power Consumption (continued)  
CY37192V  
1 2 0  
1 0 0  
8 0  
6 0  
4 0  
2 0  
0
H ig h S p e e d  
L o w P o w e r  
0
2 0  
4 0  
6 0  
F re q u e n c y (M H z)  
8 0  
1 0 0  
1 2 0  
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.  
V
= 3.3V, T = Room Temperature  
A
CC  
CY37256V  
1 4 0  
1 2 0  
1 0 0  
8 0  
H ig h S p e e d  
L o w P o w e r  
6 0  
4 0  
2 0  
0
0
2 0  
4 0  
6 0  
8 0  
1 0 0  
1 2 0  
F re q u e n c y (M H z )  
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.  
= 3.3V, T = Room Temperature  
V
CC  
A
Document #: 38-03007 Rev. *E  
Page 29 of 64  
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Ultra37000 CPLD Family  
Typical 3.3V Power Consumption (continued)  
CY37384V  
200  
180  
160  
140  
120  
100  
80  
H igh S peed  
Low P ow er  
60  
40  
20  
0
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
F req u e n cy (M H z)  
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.  
= 3.3V, T = Room Temperature  
V
CC  
A
CY37512V  
2 5 0  
2 0 0  
1 5 0  
1 0 0  
5 0  
H ig h S p e e d  
L o w P o w e r  
0
0
1 0  
2 0  
3 0  
4 0  
5 0  
6 0  
7 0  
8 0  
9 0  
F re q u e n c y (M H z )  
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.  
= 3.3V, T = Room Temperature  
V
CC  
A
Document #: 38-03007 Rev. *E  
Page 30 of 64  
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Ultra37000 CPLD Family  
Pin Configurations[20]  
44-pin TQFP (A44)  
Top View  
44 43 42 41 40 39 38 37 36 35 34  
I/O /TDI  
27  
1
I/O /TCK  
5
33  
I/O  
6
I/O  
26  
32  
31  
2
3
4
5
6
I/O  
7
I/O  
25  
I/O  
24  
CLK /I  
30  
29  
28  
27  
2
0
JTAG  
CLK /I  
EN  
GND  
4
1
GND  
I
3
CLK /I  
7
1
8
0
CLK /I  
I/O  
26  
25  
24  
23  
8
9
3
2
I/O  
23  
I/O  
22  
I/O  
9
I/O  
10  
I/O  
11  
10  
11  
I/O  
21  
12 13 14 15 16 17 18 19 20 21 22  
44-pin PLCC (J67) / CLCC (Y67)  
Top View  
6
5
4
3
2
1
44 43 42 41 40  
I/O /TDI  
27  
I/O  
26  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
I/O /TCK  
5
7
I/O  
6
8
9
10  
11  
12  
I/O  
25  
I/O  
24  
I/O  
7
CLK2/I0  
JTAGEN  
CLK /I  
4
1
GND  
I
3
GND  
CLK /I  
13  
14  
15  
16  
17  
1
0
CLK3/I2  
I/O  
8
I/O  
23  
I/O  
9
I/O  
I/O  
22  
I/O  
I/O  
10  
11  
21  
18 19 20 21 22 23 24 25 26 27 28  
Document #: 38-03007 Rev. *E  
Page 31 of 64  
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Ultra37000 CPLD Family  
Pin Configurations[20] (continued)  
48-ball Fine-Pitch BGA (BA50)  
Top View  
1
2
3
4
5
6
7
8
A
B
C
D
E
F
I/O5  
VCC  
I/O4  
I/O7  
I/O8  
I/O12  
VCC  
I/O3  
I/O2  
I/O6  
I/O9  
I/O11  
I/O14  
I/O1  
I/O31  
I/O29  
GND  
GND  
I/O16  
I/O17  
I/O30  
I/O28  
I/O25  
I/O22  
I/O20  
I/O18  
VCC  
I/O26  
I/O24  
I/O23  
I/O21  
VCC  
I/O27  
TDI  
TCK  
VCC  
I/O0  
CLK1/ I4  
CLK2/ I0  
JTAGEN  
CLK0/ I1  
GND  
GND  
I/O10  
I/O15  
I3  
CLK3/ I2  
VCC  
I/O13  
TMS  
I/O19  
TDO  
Note:  
20. For 3.3V versions (Ultra37000V), V  
= V  
.
CC  
CCO  
84-lead PLCC (J83) / CLCC (Y84)  
Top View  
11 10  
9
8
7
6
5
4
3
2
84 83 82 81 80 79 78 77 76 75  
1
GND  
74  
I/O  
I/O  
12  
8
9
73  
I/O  
55  
13  
14  
15  
16  
17  
/TDI  
72  
71  
70  
69  
68  
67  
I/O  
I/O  
I/O  
54  
53  
52  
/TCK  
I/O  
I/O  
10  
11  
I/O  
12  
I/O  
I/O  
I/O  
I/O  
51  
50  
49  
48  
I/O  
I/O  
I/O  
13  
14  
18  
19  
20  
21  
15  
66  
CLK /I  
0
0
CLK /I  
3
4
3
65  
64  
V
CCO  
GND  
GND  
22  
23  
V
63  
62  
61  
60  
59  
58  
CCO  
CLK /I  
1
1
CLK /I  
2
I/O  
16  
24  
25  
I/O  
47  
I/O  
I/O  
17  
I/O  
46  
18  
26  
27  
28  
I/O  
45  
I/O  
I/O  
I/O  
19  
20  
21  
I/O  
44  
I/O  
43  
57  
56  
55  
54  
29  
I/O  
42  
I/O  
I/O  
22  
23  
30  
31  
32  
I/O  
41  
I/O  
40  
33  
36 37  
40 41 42  
46 47 48 49 50 51 52 53  
43 44 45  
GND  
34 35  
38 39  
Note:  
21. This pin is a N/C, but Cypress recommends that you connect it to V to ensure future compatibility.  
CC  
Document #: 38-03007 Rev. *E  
Page 32 of 64  
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Ultra37000 CPLD Family  
Pin Configurations[20] (continued)  
100-lead TQFP (A100)  
Top View  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76  
TDI  
TCK  
75  
74  
73  
1
GND  
V
CCO  
2
3
4
I/O  
I/O  
I/O  
8
55  
54  
I/O  
I/O  
9
72  
71  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
10  
11  
53  
52  
51  
50  
49  
48  
5
6
7
8
I/O  
70  
69  
I/O  
I/O  
I/O  
I/O  
12  
13  
14  
15  
68  
9
67  
66  
10  
11  
12  
13  
CLK /I  
3
CLK /I  
4
3
0
0
65  
64  
GND  
NC  
V
CCO  
N/C  
GND  
CLK  
63  
62  
V
CCO  
14  
15  
16  
17  
CLK /I  
2
/I  
1
1
61  
60  
59  
I/O  
I/O  
I O  
16  
/
47  
46  
I/O  
17  
18  
I/O  
I/O  
45  
18  
19  
20  
21  
58  
I/O  
I/O  
I/O  
I/O  
I/O  
19  
20  
21  
44  
43  
57  
56  
55  
54  
53  
I/O  
I/O  
42  
41  
I/O  
I/O  
22  
23  
22  
23  
I/O  
40  
GND  
NC  
V
CCO  
NC  
24  
25  
52  
51  
26 27 28 29 30 31 32 33 34 35 36  
38 39 40 41 42 43 44 45 46 47 48 49 50  
37  
Document #: 38-03007 Rev. *E  
Page 33 of 64  
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Ultra37000 CPLD Family  
Pin Configurations[20] (continued)  
100-ball Fine-Pitch BGA (BB100) for CY37064V  
Top View  
1
2
3
4
5
6
7
8
9
10  
I/O  
A
B
C
D
E
F
NC  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
7
5
4
2
1
62  
60  
58  
59  
57  
55  
56  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
NC  
9
8
6
63  
CC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
TCK  
NC  
V
NC  
NC  
I/O  
I/O  
I/O  
V
TDI  
I/O  
10  
11  
14  
17  
22  
23  
CC  
3
61  
51  
48  
CC  
54  
53  
50  
47  
43  
41  
40  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
CLK / I/O  
12  
15  
13  
0
52  
49  
3
I
4
CLK / I/O  
NC  
GND  
GND  
GND  
GND  
CLK / I/O  
0
2
I
I
0
3
NC  
NC  
I/O  
I/O  
I/O  
NC  
NC  
I
I/O  
I/O  
I/O  
I/O  
16  
19  
20  
2
G
H
J
CLK / I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
1
21  
18  
46  
32  
33  
34  
45  
42  
35  
36  
44  
I
1
TMS  
V
NC  
V
TDO  
CC  
CC  
NC  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
39  
26  
25  
28  
27  
31  
30  
37  
38  
K
I/O  
I/O  
NC  
NC  
24  
29  
100-ball Fine-Pitch BGA (BB100) for CY37128V  
Top View  
1
NC  
2
3
4
5
6
7
8
9
10  
I/O  
A
B
C
D
E
F
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
9
8
6
5
3
2
1
0
76  
77  
78  
79  
74  
72  
73  
71  
68  
67  
70  
69  
66  
65  
62  
57  
53  
51  
50  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
I/O  
I/O  
11  
12  
14  
17  
22  
27  
28  
29  
30  
10  
7
CC  
V
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
CC  
13  
CC  
4
75  
63  
60  
59  
55  
52  
43  
44  
TCK  
TDI  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CLK / I/O  
15  
18  
16  
19  
20  
24  
25  
CC  
64  
61  
3
I
4
CLK / I/O  
GND  
GND  
GND  
GND  
CLK / I/O  
0
2
I
I
0
3
JTAG  
EN  
I/O  
I
I/O  
I/O  
I/O  
I/O  
21  
58  
2
G
H
J
CLK / I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
1
26  
23  
39  
38  
37  
56  
40  
41  
42  
54  
I
1
I/O  
V
V
I/O  
47  
TDO  
33  
CC  
CC  
TMS  
I/O  
I/O  
I/O  
I/O  
V
I/O  
I/O  
I/O  
32  
31  
35  
34  
45  
46  
48  
49  
K
I/O  
I/O  
NC  
36  
Document #: 38-03007 Rev. *E  
Page 34 of 64  
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Ultra37000 CPLD Family  
Pin Configurations[20] (continued)  
160-Lead TQFP (A160) / CQFP (U162)  
for CY37128(V) and CY37256(V)  
Top View  
GND  
1
V
120  
119  
118  
117  
CCO  
I/O  
16  
2
I/O  
111  
I/O  
17  
3
I/O  
I/O  
I/O /TDI  
108  
110  
4
I/O  
18  
109  
I/O  
5
19  
116  
115  
I/O /TCK  
20  
6
I/O  
107  
I/O  
21  
7
I/O  
106  
114  
113  
112  
I/O  
22  
8
I/O  
105  
I/O  
23  
9
I/O  
104  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
GND  
GND  
111  
110  
I/O  
24  
I/O  
103  
I/O  
102  
I/O  
25  
109  
108  
107  
106  
I/O  
26  
I/O  
101  
I/O  
27  
I/O  
100  
I/O  
28  
I/O  
99  
I/O  
29  
105  
104  
I/O  
98  
I/O  
97  
I/O  
96  
I/O  
30  
I/O  
31  
103  
102  
101  
100  
CLK /I  
3
CLK /I  
4
3
0
0
V
GND  
CCO  
GND  
V
CCO  
CLK /I  
CLK /I  
2
I/O  
95  
99  
98  
1
1
32  
33  
34  
35  
36  
37  
38  
39  
I/O  
I/O  
94  
97  
96  
95  
94  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
93  
I/O  
92  
I/O  
91  
I/O  
90  
93  
92  
I/O  
89  
I/O  
88  
91  
90  
89  
GND  
GND  
I/O  
40  
I/O  
87  
I/O  
86  
88  
87  
I/O  
41  
I/O  
85  
I/O  
84  
I/O  
42  
86  
85  
84  
I/O  
43  
I/O  
83  
I/O  
82  
I/O  
44  
I/O  
I/O  
I/O  
45  
46  
47  
83  
82  
81  
I/O  
I/O  
81  
80  
GND  
V
CCO  
Document #: 38-03007 Rev. *E  
Page 35 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Pin Configurations[20] (continued)  
160-Lead TQFP (A160) for CY37192(V)  
Top View  
GND  
NC  
1
V
120  
119  
118  
117  
CCO  
2
I/O  
104  
I/O  
16  
3
I/O  
I/O  
TDI  
I/O  
103  
4
I/O  
17  
102  
I/O  
5
18  
116  
115  
TCK  
6
101  
I/O  
19  
7
I/O  
I/O  
I/O  
114  
113  
112  
100  
99  
I/O  
20  
8
I/O  
21  
9
98  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
GND  
GND  
111  
110  
I/O  
22  
I/O  
97  
I/O  
96  
I/O  
23  
109  
108  
107  
106  
I/O  
24  
I/O  
95  
I/O  
25  
I/O  
94  
I/O  
26  
I/O  
93  
I/O  
27  
105  
104  
I/O  
92  
I/O  
91  
I/O  
90  
I/O  
28  
I/O  
29  
103  
102  
101  
100  
CLK /I  
3
CLK /I  
4
3
0
0
V
GND  
CCO  
GND  
V
CCO  
CLK /I  
CLK /I  
2
I/O  
89  
99  
98  
1
1
30  
31  
32  
33  
34  
35  
36  
37  
I/O  
I/O  
88  
97  
96  
95  
94  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
87  
I/O  
86  
I/O  
85  
I/O  
84  
93  
92  
I/O  
83  
I/O  
82  
91  
90  
89  
GND  
GND  
I/O  
38  
I/O  
81  
I/O  
80  
88  
87  
I/O  
39  
I/O  
79  
I/O  
78  
I/O  
40  
86  
85  
84  
I/O  
41  
I/O  
77  
I/O  
76  
I/O  
42  
I/O  
I/O  
I/O  
43  
44  
45  
83  
82  
81  
I/O  
75  
NC  
GND  
V
CCO  
Document #: 38-03007 Rev. *E  
Page 36 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Pin Configurations[20] (continued)  
208-Lead PQFP (N208) / CQFP (U208)  
Top View  
156  
155  
154  
153  
152  
151  
150  
149  
148  
147  
146  
145  
144  
143  
142  
141  
140  
139  
138  
137  
136  
135  
134  
133  
132  
131  
130  
129  
128  
127  
126  
125  
124  
123  
122  
121  
120  
119  
118  
117  
116  
115  
114  
113  
112  
111  
110  
109  
108  
107  
106  
105  
V
GND  
I/O  
20  
I/O  
21  
I/O  
22  
I/O  
23  
I/O  
24  
TCK  
I/O  
25  
I/O  
26  
I/O  
27  
I/O  
28  
I/O  
29  
GND  
I/O  
30  
I/O  
31  
I/O  
32  
I/O  
33  
I/O  
34  
NC  
I/O  
35  
I/O  
36  
I/O  
37  
I/O  
38  
I/O  
39  
1
2
3
4
5
6
7
8
CCO  
I/O  
I/O  
I/O  
I/O  
I/O  
TDI  
I/O  
I/O  
I/O  
I/O  
I/O  
139  
138  
137  
136  
135  
134  
9
133  
132  
131  
130  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
GND  
I/O  
129  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CLK /I  
3
V
GND  
V
GND  
CLK /I  
2
I/O  
119  
I/O  
118  
I/O  
117  
I/O  
116  
I/O  
115  
NC  
128  
127  
126  
125  
124  
123  
122  
121  
120  
4
CLK /I  
CC  
0
0
V
CCO  
GND  
NC  
CCO  
CLK /I  
3
1
I/O  
1
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
114  
I/O  
113  
I/O  
112  
I/O  
111  
I/O  
GND  
I/O  
109  
GND  
40  
41  
42  
110  
I/O  
I/O  
I/O  
I/O  
I/O  
50  
51  
52  
53  
54  
I/O  
108  
I/O  
43  
44  
107  
I/O  
106  
45  
I/O  
105  
I/O  
I/O  
103  
I/O  
NC  
46  
47  
48  
49  
I/O  
104  
55  
56  
57  
58  
59  
I/O  
I/O  
I/O  
I/O  
V
102  
I/O  
101  
I/O  
100  
GND  
50  
51  
52  
CC0  
Document #: 38-03007 Rev. *E  
Page 37 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Pin Configurations[20] (continued)  
292-Ball PBGA (BG292)  
Top View  
1
2
3
4
5
6
7
I/O  
I/O  
8
9
10  
11  
12  
13  
14  
NC  
NC  
15  
16  
17  
18  
19  
20  
A
B
C
D
E
F
GND  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
NC  
I/O  
I/O  
A
B
C
D
E
F
21  
20  
16  
12  
15  
17  
9
7
8
4
5
6
0
1
2
3
190  
189  
187  
188  
CC  
186  
185  
184  
183  
182  
181  
180  
178  
175  
174  
173  
169  
168  
166  
162  
160  
156  
154  
152  
149  
145  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
23  
19  
18  
11  
191  
171  
170  
167  
164  
161  
158  
155  
151  
147  
NC  
NC  
I/O  
NC  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
165  
22  
14  
10  
13  
179  
176  
172  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
NC  
GND  
NC  
NC  
V
GND  
NC  
V
GND I/O  
V
NC  
GND I/O  
TDI  
24  
27  
30  
33  
35  
39  
42  
43  
47  
49  
52  
54  
57  
61  
64  
68  
71  
CCO  
177  
CCO  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
159  
26  
25  
28  
31  
34  
37  
41  
45  
163  
TCK  
V
V
NC  
CCO  
CCO  
G
H
J
I/O  
I/O  
I/O  
I/O  
G
H
J
32  
29  
157  
153  
150  
146  
NC  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
38  
40  
44  
36  
148  
144  
CC  
K
L
V
CLK /I  
4
NC  
NC  
K
L
CC  
3
I/O  
I/O  
V
CLK /I I/O  
NC  
46  
2
3
143  
141  
137  
134  
M
N
P
R
T
CLK /I CLK /I  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
M
N
P
R
T
0
0
1
1
48  
139  
140  
136  
133  
130  
127  
123  
117  
115  
142  
138  
135  
132  
129  
126  
125  
120  
119  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
GND I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
50  
53  
56  
60  
63  
67  
70  
73  
51  
55  
59  
62  
66  
69  
72  
77  
I/O  
I/O  
I/O  
I/O  
I/O  
58  
131  
V
V
NC  
CCO  
CCO  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
65  
124  
128  
122  
121  
118  
116  
U
V
W
Y
GND  
I/O  
I/O  
I/O  
I/O  
V
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
V
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND I/O  
V
NC  
TDO  
NC  
GND I/O  
U
V
W
Y
76  
78  
79  
80  
CCO  
82  
85  
86  
87  
91  
92  
93  
94  
CC  
98  
97  
96  
102  
101  
100  
112  
109  
107  
106  
CCO  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
114  
I/O  
I/O  
75  
81  
83  
84  
88  
89  
90  
2
105  
104  
103  
113  
110  
108  
I/O  
NC  
74  
95  
TMS  
4
NC  
NC  
I/O  
I/O  
NC  
17  
NC  
99  
111  
1
2
3
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
18  
19  
20  
Document #: 38-03007 Rev. *E  
Page 38 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Pin Configurations[20] (continued)  
256-Ball Fine-Pitch BGA (BB256)  
Top View  
1
2
3
4
5
6
7
8
9
10  
11  
12  
I/O  
13  
I/O  
14  
15  
16  
A
B
C
D
E
F
GND  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
I/O  
GND  
GND I/O  
GND I/O  
V
I/O  
GND  
GND  
26  
24  
23  
22  
20  
19  
18  
17  
16  
CC  
11  
186  
185  
184  
183  
CC  
CC  
177  
176  
175  
174  
173  
172  
171  
170  
169  
168  
154  
150  
146  
142  
136  
132  
117  
167  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
27  
28  
31  
34  
38  
42  
25  
15  
10  
181  
180  
179  
178  
CC  
166  
165  
163  
161  
158  
156  
152  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
29  
32  
14  
9
4
3
2
1
0
191  
190  
189  
188  
187  
164  
162  
159  
CC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
30  
33  
37  
41  
47  
51  
55  
59  
61  
64  
13  
8
160  
157  
155  
151  
147  
143  
137  
133  
129  
126  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
35  
21  
36  
40  
46  
50  
54  
58  
72  
73  
74  
75  
76  
12  
7
V
TCK  
V
I/O  
I/O  
V
TDI  
V
CC  
CC  
6
182  
148  
144  
140  
101  
102  
103  
104  
105  
106  
107  
G
H
J
I/O  
V
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CLK  
I/O  
153  
43  
CC  
39  
5
149  
145  
141  
135  
CC  
3
/I  
4
GND  
GND  
GND  
GND  
CLK  
I/O  
I/O  
I/O  
I/O  
GND  
GND  
GND I/O  
GND I/O  
CLK  
/I  
GND  
GND  
GND  
GND  
0
1
45  
44  
48  
52  
86  
CC  
2
/I  
0
3
NC  
I
2
49  
K
L
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CLK  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
57  
56  
60  
62  
65  
67  
69  
53  
91  
92  
93  
94  
95  
96  
97  
CC  
138  
134  
130  
127  
124  
123  
139  
/I  
1
V
TMS  
V
V
TDO I/O  
V
CC  
CC  
CC  
M
N
P
R
T
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
63  
66  
68  
77  
82  
83  
98  
108  
109  
110  
112  
113  
114  
115  
116  
131  
128  
125  
I/O  
I/O  
I/O  
I/O  
NC  
78  
87  
88  
89  
90  
99  
NC  
I/O79 I/O  
I/O  
I/O  
I/O  
I/O  
NC  
84  
100  
118  
119  
120  
GND  
GND  
I/O  
I/O  
I/O  
GND  
GND  
GND I/O  
GND I/O  
I/O  
I/O  
GND  
GND  
70  
71  
80  
81  
85  
111  
121  
122  
GND  
I/O  
I/O  
V
V
I/O  
GND  
CC  
CC  
Document #: 38-03007 Rev. *E  
Page 39 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Pin Configurations[20] (continued)  
388-Lead PBGA (BG388)  
Top View  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
A
B
C
D
E
F
GND GND I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND GND  
19  
18  
37  
36  
41  
43  
46  
51  
54  
57  
58  
15  
17  
16  
13  
14  
12  
34  
35  
33  
21  
31  
32  
30  
20  
28  
29  
25  
26  
10  
11  
7
8
6
4
5
3
1
263  
260  
261  
259  
257  
258  
256  
254  
255  
253  
239  
237  
232  
231  
233  
236  
229  
228  
230  
243  
250  
249  
251  
248  
246  
247  
244  
245  
225  
226  
GND NC I/O  
I/O  
I/O  
V
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
2
CC  
252  
234  
240  
224  
222  
221  
218  
215  
212  
209  
206  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
23  
39  
42  
45  
48  
49  
52  
55  
38  
40  
27  
24  
9
0
262  
238  
235  
227  
223  
220  
217  
214  
213  
210  
207  
197  
202  
199  
198  
195  
192  
175  
172  
169  
168  
189  
186  
182  
154  
NC  
NC I/O  
V
V
NC GND GND  
V
V
GND GND NC  
V
V
NC  
NC I/O  
CCO  
CCO  
CCO  
CCO  
CCO  
CCO  
TCK I/O  
NC  
NC  
TDI I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
44  
47  
22  
63  
242  
219  
216  
211  
208  
205  
204  
G
H
J
I/O  
I/O  
241  
V
V
V
V
50  
CCO  
CCO  
CCO  
53  
CCO  
K
L
NC  
NC I/O  
GND I/O  
56  
I0  
GND  
GND  
GND GND GND GND GND GND  
GND GND GND GND GND GND  
GND GND GND GND GND GND  
GND GND GND GND GND GND  
GND GND GND GND GND GND  
GND GND GND GND GND GND  
I4 I/O  
59  
M
N
P
R
T
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I1  
GND  
I3 I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
61  
64  
65  
68  
71  
88  
91  
94  
95  
74  
77  
81  
109  
60  
203  
200  
CC  
V
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
V
V
V
I/O  
I/O  
I/O  
CC  
62  
67  
70  
85  
86  
89  
92  
73  
76  
79  
108  
CCO  
CCO  
CCO  
201  
196  
193  
178  
177  
174  
171  
190  
187  
184  
155  
180  
148  
149  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
66  
69  
84  
87  
90  
93  
72  
75  
78  
80  
82  
CCO  
GND  
GND  
NC  
GND I/O  
GND I/O  
NC I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
194  
179  
176  
173  
170  
191  
188  
185  
183  
181  
U
V
W
Y
V
V
V
V
I/O  
I/O  
I/O  
I/O  
CCO  
CCO  
CCO  
CCO  
I/O  
I/O  
I/O  
I/O  
110  
153  
152  
AA I/O  
AB I/O  
AC I/O  
111  
N/C  
NC I/O  
NC I/O  
I/O  
N/C  
NC I/O  
I/O  
I/O  
I/O  
V
V
NC GND GND  
V
V
GND GND NC  
V
V
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
112  
113  
102  
101  
CCO  
CCO  
CCO  
CCO  
CCO  
CCO  
150  
161  
162  
151  
163  
165  
164  
AD I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I2 I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
83  
117  
116  
118  
97  
100  
105  
103  
104  
120  
106  
107  
123  
121  
122  
126  
124  
125  
129  
127  
128  
133  
130  
132  
136  
134  
135  
139  
137  
138  
142  
140  
141  
157  
143  
156  
159  
160  
158  
166  
144  
167  
146  
147  
145  
AE GND NC I/O  
AF GND GND I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
CC  
I/O  
I/O  
I/O  
I/O  
NC GND  
GND GND  
115  
114  
119  
98  
99  
I/O  
TMS I/O  
I/O  
TDO I/O  
96  
131  
Document #: 38-03007 Rev. *E  
Page 40 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Pin Configurations[20] (continued)  
400-Ball Fine-Pitch BGA (BB400)  
Top View  
A
B
C
D
E
F
GND GND  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
V
V
I/O  
GND GND I/O  
GND GND I/O  
GND GND I/O  
GND GND I/O  
V
V
V
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
230  
NC  
GND GND  
17  
16  
15  
20  
19  
14  
13  
12  
18  
35  
29  
28  
27  
26  
34  
33  
37  
CC  
CC  
CC  
11  
257  
256  
255  
254  
253  
252  
CC  
CC  
CC  
CC  
239  
238  
237  
236  
250  
247  
217  
233  
231  
228  
251  
248  
220  
218  
216  
204  
200  
196  
174  
180  
182  
232  
229  
245  
244  
GND GND GND  
NC  
I/O  
NC  
GND GND GND  
10  
NC  
GND GND GND I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND GND GND  
NC  
9
I/O  
NC  
GND I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
NC  
I/O  
44  
21  
22  
41  
50  
49  
56  
25  
24  
8
235  
234  
249  
246  
CC  
243  
241  
240  
212  
211  
206  
227  
226  
224  
215  
CC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
46  
43  
23  
42  
7
4
3
2
1
0
263  
262  
261  
259  
258  
242  
222  
213  
CC  
225  
223  
214  
CC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
47  
45  
40  
39  
48  
55  
65  
69  
85  
90  
75  
77  
32  
6
221  
219  
210  
205  
201  
197  
175  
168  
183  
184  
G
H
J
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
53  
52  
51  
38  
36  
54  
64  
68  
84  
72  
74  
76  
116  
119  
31  
5
V
V
V
TCK  
V
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
TDI  
V
V
V
CC  
CC  
CC  
CC  
30  
60  
61  
66  
70  
128  
CC  
260  
202  
198  
193  
192  
162  
137  
138  
139  
140  
141  
142  
143  
I/O  
I/O  
I/O  
V
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CLK  
/I  
I/O  
I/O  
I/O  
209  
59  
58  
57  
CC  
62  
203  
199  
195  
194  
CC  
3
2
207  
208  
4
K
L
GND GND GND GND I/O  
GND GND GND GND I/O  
CLK  
GND GND I/O  
GND GND I/O  
CLK  
/I  
GND GND GND GND  
GND GND GND GND  
0
63  
/I  
0
3
NC  
I
2
67  
M
N
P
R
T
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CLK  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
89  
88  
87  
86  
1
71  
126  
127  
129  
130  
131  
132  
133  
134  
135  
136  
CC  
176  
169  
170  
185  
154  
153  
177  
178  
179  
/I  
1
V
V
V
TMS  
V
I/O  
V
TDO I/O  
V
V
V
CC  
CC  
CC  
91  
CC  
CC  
CC  
CC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
V
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
95  
80  
82  
83  
94  
79  
81  
93  
78  
92  
73  
114  
117  
102  
103  
CC  
163  
164  
156  
157  
CC  
181  
165  
166  
158  
159  
160  
161  
171  
186  
155  
172  
189  
187  
173  
191  
190  
188  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
108  
109  
111  
115  
118  
104  
105  
106  
107  
120  
121  
122  
123  
124  
125  
I/O  
NC  
I/O  
I/O  
I/O  
I/O  
NC  
110  
167  
150  
U
V
W
Y
NC  
GND I/O  
I/O  
GND GND I/O  
GND GND I/O  
GND GND I/O  
GND GND I/O  
I/O  
GND  
NC  
112  
113  
151  
152  
147  
148  
NC  
GND GND GND I/O  
I/O  
I/O  
V
V
V
V
V
V
I/O14 I/O  
4
GND GND GND  
NC  
96  
99  
GND GND GND  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
NC  
GND GND GND  
97  
CC  
CC  
145  
146  
GND GND  
NC  
I/O  
I/O  
I/O  
I/O  
149  
NC  
GND GND  
98  
100  
101  
CC  
CC  
Document #: 38-03007 Rev. *E  
Page 41 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Ordering Information  
C Y 3 7 5 1 2 V P 4 0 0 - 8 3 B B X C  
Cypress Semiconductor ID  
Operating Conditions  
Family Type  
Commercial  
0°C to +70°C  
37 = Ultra37000 Family  
Industrial -40°C to +85°C  
Military  
-55°C to +125°C  
Lead Free  
X
Macrocell Density  
32 = 32 Macrocells 256 = 256 Macrocells  
64 = 64 Macrocells 384 = 384 Macrocells  
Lead Free  
Package Type  
A
U
N
= Thin Quad Flat Pack (TQFP)  
= Ceramic Quad Flat Pack (CQFP)  
= Plastic Quad Flat Pack (PQFP)  
128 = 128 Macrocells  
Macrocells  
512 = 512  
192 = 192 Macrocells  
Operating Reference Voltage  
NT = Thermally Enhanced Plastic Quad Flat Pack  
(EQFP)  
J
V = 3.3V Supply Voltage  
(5.0V if not specified)  
= Plastic Leaded Chip Carrier (PLCC)  
= Ceramic Leaded Chip Carrier (CLCC)  
Y
Pin Count  
BG = Plastic Ball Grid Array (PBGA)  
BA = Fine-Pitch Ball Grid Array (FBGA)  
0.8mm Lead Pitch  
BB = Fine-Pitch Ball Grid Array (FBGA)  
1.0mm Lead Pitch  
P44 = 44 Leads  
P48 = 48 Leads  
P84 = 84 Leads  
P100 = 100 Leads  
P160 = 160 Leads  
P208 = 208 Leads  
P256 = 256 Leads  
P352 = 352 Leads  
P400 = 400 Leads  
Speed  
125 = 125 MHz  
200 = 200 MHz  
167 = 167 MHz  
154 = 154 MHz  
143 = 143 MHz  
100 = 100 MHz  
83 = 83 MHz  
66 = 66 MHz  
5.0V Ordering Information  
Speed  
Macrocells (MHz)  
Package  
Name  
Operating  
Range  
Ordering Code  
Package Type  
32  
200 CY37032P44-200AC  
A44  
A44  
J67  
J67  
A44  
J67  
A44  
A44  
J67  
J67  
A44  
A44  
J67  
J67  
A44  
J67  
A44  
A44  
J67  
J67  
J83  
A100  
A100  
44-Lead Thin Quad Flat Pack  
Commercial  
CY37032P44-200AXC  
CY37032P44-200JC  
CY37032P44-200JXC  
154 CY37032P44-154AC  
CY37032P44-154JC  
CY37032P44-154AI  
44-Lead Lead Free Thin Quad Flat Pack  
44-Lead Plastic Leaded Chip Carrier  
44-Lead Lead Free Plastic Leaded Chip Carrier  
44-Lead Thin Quad Flat Pack  
Commercial  
Industrial  
44-Lead Plastic Leaded Chip Carrier  
44-Lead Thin Quad Flat Pack  
CY37032P44-154AXI  
CY37032P44-154JI  
44-Lead Lead Free Thin Quad Flat Pack  
44-Lead Plastic Leaded Chip Carrier  
44-Lead Lead Free Plastic Leaded Chip Carrier  
44-Lead Thin Quad Flat Pack  
CY37032P44-154JXI  
125 CY37032P44-125AC  
CY37032P44-125AXC  
CY37032P44-125JC  
CY37032P44-125JXC  
CY37032P44-125AI  
Commercial  
44-Lead Lead Free Thin Quad Flat Pack  
44-Lead Plastic Leaded Chip Carrier  
44-Lead Lead Free Plastic Leaded Chip Carrier  
44-Lead Thin Quad Flat Pack  
Industrial  
CY37032P44-125JI  
44-Lead Plastic Leaded Chip Carrier  
44-Lead Thin Quad Flat Pack  
64  
200 CY37064P44-200AC  
CY37064P44-200AXC  
CY37064P44-200JC  
CY37064P44-200JXC  
CY37064P84-200JC  
CY37064P100-200AC  
CY37064P100-200AXC  
Commercial  
44-Lead Lead Free Thin Quad Flat Pack  
44-Lead Plastic Leaded Chip Carrier  
44-Lead Lead Free Plastic Leaded Chip Carrier  
84-Lead Plastic Leaded Chip Carrier  
100-Lead Thin Quad Flat Pack  
100-Lead Lead Free Thin Quad Flat Pack  
Document #: 38-03007 Rev. *E  
Page 42 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
5.0V Ordering Information (continued)  
Speed  
Macrocells (MHz)  
Package  
Name  
Operating  
Range  
Ordering Code  
Package Type  
64  
154 CY37064P44-154AC  
CY37064P44-154JC  
CY37064P84-154JC  
CY37064P100-154AC  
CY37064P44-154AI  
CY37064P44-154AXI  
CY37064P44-154JI  
CY37064P44-154JXI  
CY37064P84-154JI  
CY37064P100-154AI  
5962-9951902QYA  
A44  
J67  
44-Lead Thin Quad Flat Pack  
Commercial  
44-Lead Plastic Leaded Chip Carrier  
84-Lead Plastic Leaded Chip Carrier  
100-Lead Thin Quad Flat Pack  
J83  
A100  
A44  
A44  
J67  
44-Lead Thin Quad Flat Pack  
Industrial  
44-Lead Lead Free Thin Quad Flat Pack  
44-Lead Plastic Leaded Chip Carrier  
44-Lead Lead Free Plastic Leaded Chip Carrier  
84-Lead Plastic Leaded Chip Carrier  
100-Lead Thin Quad Flat Pack  
J67  
J83  
A100  
Y67  
A44  
A44  
J67  
44-Lead Ceramic Leadless Chip Carrier  
44-Lead Thin Quad Flat Pack  
Military  
125 CY37064P44-125AC  
CY37064P44-125AXC  
CY37064P44-125JC  
CY37064P44-125JXC  
CY37064P84-125JC  
CY37064P100-125AC  
CY37064P100-125AXC  
CY37064P44-125AI  
CY37064P44-125AXI  
CY37064P44-125JI  
CY37064P84-125JI  
CY37064P100-125AI  
CY37064P100-125AXI  
5962-9951901QYA  
Commercial  
44-Lead Lead Free Thin Quad Flat Pack  
44-Lead Plastic Leaded Chip Carrier  
44-Lead Lead Free Plastic Leaded Chip Carrier  
84-Lead Plastic Leaded Chip Carrier  
100-Lead Thin Quad Flat Pack  
J67  
J83  
A100  
A100  
A44  
A44  
J67  
100-Lead Lead Free Thin Quad Flat Pack  
44-Lead Thin Quad Flat Pack  
Industrial  
44-Lead Lead Free Thin Quad Flat Pack  
44-Lead Plastic Leaded Chip Carrier  
84-Lead Plastic Leaded Chip Carrier  
100-Lead Thin Quad Flat Pack  
J83  
A100  
A100  
Y67  
100-Lead Lead Free Thin Quad Flat Pack  
44-Lead Ceramic Leadless Chip Carrier  
Military  
Document #: 38-03007 Rev. *E  
Page 43 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
5.0V Ordering Information (continued)  
Speed  
Macrocells (MHz)  
Package  
Name  
Operating  
Range  
Ordering Code  
Package Type  
128  
167 CY37128P84-167JC  
CY37128P84-167JXC  
CY37128P100-167AC  
CY37128P100-167AXC  
CY37128P160-167AC  
CY37128P160-167AXC  
125 CY37128P84-125JC  
CY37128P84-125JXC  
CY37128P100-125AC  
CY37128P100-125AXC  
CY37128P160-125AC  
CY37128P160-125AXC  
CY37128P84-125JI  
J83  
J83  
84-Lead Plastic Leaded Chip Carrier  
84-Lead Lead Free Plastic Leaded Chip Carrier  
100-Lead Thin Quad Flat Pack  
Commercial  
A100  
A100  
A160  
A160  
J83  
100-Lead Lead Free Thin Quad Flat Pack  
160-Lead Thin Quad Flat Pack  
160-Lead Lead Free Thin Quad Flat Pack  
84-Lead Plastic Leaded Chip Carrier  
84-Lead Lead Free Plastic Leaded Chip Carrier  
100-Lead Thin Quad Flat Pack  
Commercial  
J83  
A100  
A100  
A160  
A160  
J83  
100-Lead Lead Free Thin Quad Flat Pack  
160-Lead Thin Quad Flat Pack  
160-Lead Lead Free Thin Quad Flat Pack  
84-Lead Plastic Leaded Chip Carrier  
84-Lead Lead Free Plastic Leaded Chip Carrier  
100-Lead Thin Quad Flat Pack  
Industrial  
CY37128P84-125JXI  
CY37128P100-125AI  
CY37128P100-125AXI  
CY37128P160-125AI  
CY37128P160-125AXI  
5962-9952102QYA  
J83  
A100  
A100  
A160  
A160  
Y84  
100-Lead Lead Free Thin Quad Flat Pack  
160-Lead Thin Quad Flat Pack  
160-Lead Lead Free Thin Quad Flat Pack  
84-Lead Ceramic Leaded Chip Carrier  
84-Lead Plastic Leaded Chip Carrier  
84-Lead Lead Free Plastic Leaded Chip Carrier  
100-Lead Thin Quad Flat Pack  
Military  
100 CY37128P84-100JC  
CY37128P84-100JXC  
CY37128P100-100AC  
CY37128P100-100AXC  
CY37128P160-100AC  
CY37128P160-100AXC  
CY37128P84-100JI  
J83  
Commercial  
J83  
A100  
A100  
A160  
A160  
J83  
100-Lead Lead Free Thin Quad Flat Pack  
160-Lead Thin Quad Flat Pack  
160-Lead Lead Free Thin Quad Flat Pack  
84-Lead Plastic Leaded Chip Carrier  
100-Lead Thin Quad Flat Pack  
Industrial  
CY37128P100-100AI  
CY37128P100-100AXI  
CY37128P160-100AI  
5962-9952101QYA  
A100  
A100  
A160  
Y84  
100-Lead Lead Free Thin Quad Flat Pack  
160-Lead Thin Quad Flat Pack  
84-Lead Ceramic Leaded Chip Carrier  
160-Lead Thin Quad Flat Pack  
Military  
192  
154 CY37192P160-154AC  
CY37192P160-154AXC  
125 CY37192P160-125AC  
CY37192P160-125AXC  
CY37192P160-125AI  
CY37192P160-125AXI  
A160  
A160  
A160  
A160  
A160  
A160  
A160  
A160  
A160  
A160  
Commercial  
160-Lead Lead Free Thin Quad Flat Pack  
160-Lead Thin Quad Flat Pack  
Commercial  
Industrial  
160-Lead Lead Free Thin Quad Flat Pack  
160-Lead Thin Quad Flat Pack  
160-Lead Lead Free Thin Quad Flat Pack  
160-Lead Thin Quad Flat Pack  
83  
CY37192P160-83AC  
CY37192P160-83AXC  
CY37192P160-83AI  
CY37192P160-83AXI  
Commercial  
Industrial  
160-Lead Lead Free Thin Quad Flat Pack  
160-Lead Thin Quad Flat Pack  
160-Lead Lead Free Thin Quad Flat Pack  
Document #: 38-03007 Rev. *E  
Page 44 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
5.0V Ordering Information (continued)  
Speed  
Macrocells (MHz)  
Package  
Name  
Operating  
Range  
Ordering Code  
Package Type  
256  
154 CY37256P160-154AC  
CY37256P160-154AXC  
CY37256P208-154NC  
CY37256P256-154BGC  
125 CY37256P160-125AC  
CY37256P160-125AXC  
CY37256P208-125NC  
CY37256P256-125BGC  
CY37256P160-125AI  
A160  
A160  
N208  
160-Lead Thin Quad Flat Pack  
Commercial  
160-Lead Lead Free Thin Quad Flat Pack  
208-Lead Plastic Quad Flat Pack  
BG292 292-Ball Plastic Ball Grid Array  
A160  
A160  
N208  
160-Lead Thin Quad Flat Pack  
Commercial  
Industrial  
160-Lead Lead Free Thin Quad Flat Pack  
208-Lead Plastic Quad Flat Pack  
BG292 292-Ball Plastic Ball Grid Array  
A160  
A160  
N208  
160-Lead Thin Quad Flat Pack  
CY37256P160-125AXI  
CY37256P208-125NI  
160-Lead Lead Free Thin Quad Flat Pack  
208-Lead Plastic Quad Flat Pack  
CY37256P256-125BGI  
5962-9952302QZC  
BG292 292-Ball Plastic Ball Grid Array  
U162  
A160  
A160  
N208  
160-Lead Ceramic Quad Flat Pack  
160-Lead Thin Quad Flat Pack  
Military  
83  
CY37256P160-83AC  
CY37256P160-83AXC  
CY37256P208-83NC  
CY37256P256-83BGC  
CY37256P160-83AI  
CY37256P160-83AXI  
CY37256P208-83NI  
CY37256P256-83BGI  
5962-9952301QZC  
Commercial  
160-Lead Lead Free Thin Quad Flat Pack  
208-Lead Plastic Quad Flat Pack  
BG292 292-Ball Plastic Ball Grid Array  
A160  
A160  
N208  
160-Lead Thin Quad Flat Pack  
Industrial  
160-Lead Lead Free Thin Quad Flat Pack  
208-Lead Plastic Quad Flat Pack  
BG292 292-Ball Plastic Ball Grid Array  
U162  
N208  
160-Lead Ceramic Quad Flat Pack  
208-Lead Plastic Quad Flat Pack  
Military  
384  
125 CY37384P208-125NC  
CY37384P256-125BGC  
Commercial  
BG292 292-Ball Plastic Ball Grid Array  
N208 208-Lead Plastic Quad Flat Pack  
BG292 292-Ball Plastic Ball Grid Array  
N208 208-Lead Plastic Quad Flat Pack  
BG292 292-Ball Plastic Ball Grid Array  
83  
CY37384P208-83NC  
CY37384P256-83BGC  
CY37384P208-83NI  
CY37384P256-83BGI  
Commercial  
Industrial  
Document #: 38-03007 Rev. *E  
Page 45 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
5.0V Ordering Information (continued)  
Speed  
Package  
Name  
Operating  
Macrocells (MHz)  
Ordering Code  
Package Type  
208-Lead Plastic Quad Flat Pack  
Range  
512  
125 CY37512P208-125NC  
CY37512P256-125BGC  
CY37512P352-125BGC  
100 CY37512P208-100NC  
CY37512P256-100BGC  
CY37512P352-100BGC  
CY37512P208-100NI  
N208  
Commercial  
BG292 292-Ball Plastic Ball Grid Array  
BG388 388-Ball Plastic Ball Grid Array  
N208  
208-Lead Plastic Quad Flat Pack  
Commercial  
Industrial  
BG292 292-Ball Plastic Ball Grid Array  
BG388 388-Ball Plastic Ball Grid Array  
N208  
208-Lead Plastic Quad Flat Pack  
CY37512P256-100BGI  
CY37512P352-100BGI  
5962-9952502QZC  
BG292 292-Ball Plastic Ball Grid Array  
BG388 388-Ball Plastic Ball Grid Array  
U208  
N208  
208-Lead Ceramic Quad Flat Pack  
208-Lead Plastic Quad Flat Pack  
Military  
83  
CY37512P208-83NC  
CY37512P256-83BGC  
CY37512P352-83BGC  
CY37512P208-83NI  
CY37512P256-83BGI  
CY37512P352-83BGI  
5962-9952501QZC  
Commercial  
BG292 292-Ball Plastic Ball Grid Array  
BG388 388-Ball Plastic Ball Grid Array  
N208  
208-Lead Plastic Quad Flat Pack  
Industrial  
Military  
BG292 292-Ball Plastic Ball Grid Array  
BG388 388-Ball Plastic Ball Grid Array  
U208  
208-Lead Ceramic Quad Flat Pack  
3.3V Ordering Information  
Speed  
Package  
Name  
Operating  
Range  
Macrocells (MHz)  
Ordering Code  
Package Type  
44-Lead Thin Quad Flat Pack  
32  
143 CY37032VP44-143AC  
A44  
A44  
Commercial  
Commercial  
Industrial  
CY37032VP44-143AXC  
CY37032VP48-143BAC  
100 CY37032VP44-100AC  
CY37032VP44-100AXC  
CY37032VP48-100BAC  
CY37032VP44-100AI  
44-Lead Lead Free Thin Quad Flat Pack  
48-Ball Fine Pitch Ball Grid Array  
44-Lead Thin Quad Flat Pack  
BA50  
A44  
A44  
44-Lead Lead Free Thin Quad Flat Pack  
48-Ball Fine Pitch Ball Grid Array  
44-Lead Thin Quad Flat Pack  
BA50  
A44  
CY37032VP44-100AXI  
CY37032VP48-100BAI  
CY37032VP44-100JI  
A44  
44-Lead Lead Free Thin Quad Flat Pack  
48-Ball Fine Pitch Ball Grid Array  
44-Lead Plastic Leaded Chip Carrier  
44-Lead Lead Free Plastic Leaded Chip Carrier  
BA50  
J67  
CY37032VP44-100JXI  
J67  
Document #: 38-03007 Rev. *E  
Page 46 of 64  
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Ultra37000 CPLD Family  
3.3V Ordering Information (continued)  
Speed  
Macrocells (MHz)  
Package  
Name  
Operating  
Range  
Ordering Code  
Package Type  
64  
143 CY37064VP44-143AC  
CY37064VP44-143AXC  
CY37064VP48-143BAC  
CY37064VP100-143AC  
CY37064VP100-143AXC  
CY37064VP100-143BBC  
100 CY37064VP44-100AC  
CY37064VP44-100AXC  
CY37064VP48-100BAC  
CY37064VP100-100AC  
CY37064VP100-100AXC  
CY37064VP100-100BBC  
CY37064VP44-100AI  
A44  
A44  
44-Lead Thin Quad Flatpack  
Commercial  
44-Lead Lead Free Thin Quad Flatpack  
48-Ball Fine-Pitch Ball Grid Array  
100-Lead Thin Quad Flatpack  
BA50  
A100  
A100  
100-Lead Lead Free Thin Quad Flatpack  
BB100 100-Ball Fine-Pitch Ball Grid Array  
A44  
A44  
44-Lead Thin Quad Flatpack  
Commercial  
44-Lead Lead Free Thin Quad Flatpack  
48-Ball Fine-Pitch Ball Grid Array  
100-Lead Thin Quad Flatpack  
BA50  
A100  
A100  
100-Lead Lead Free Thin Quad Flatpack  
BB100 100-Ball Fine-Pitch Ball Grid Array  
A44  
A44  
44-Lead Thin Quad Flatpack  
Industrial  
CY37064VP44-100AXI  
CY37064VP48-100BAI  
CY37064VP100-100BBI  
CY37064VP100-100AI  
CY37064VP100-100AXI  
5962-9952001QYA  
44-Lead Lead Free Thin Quad Flatpack  
48-Ball Fine-Pitch Ball Grid Array  
BA50  
BB100 100-Ball Fine-Pitch Ball Grid Array  
A100  
A100  
Y67  
100-Lead Thin Quad Flatpack  
100-Lead Lead Free Thin Quad Flatpack  
44-Lead Ceramic Leaded Chip Carrier  
100-Lead Thin Quad Flat Pack  
Military  
128  
125 CY37128VP100-125AC  
CY37128VP100-125AXC  
CY37128VP100-125BBC  
CY37128VP160-125AC  
CY37128VP160-125AXC  
CY37128VP160-125AI  
CY37128VP160-125AXI  
A100  
A100  
Commercial  
100-Lead Lead Free Thin Quad Flat Pack  
BB100 100-Ball Fine-Pitch Ball Grid Array  
A160  
A160  
A160  
A160  
A100  
A100  
160-Lead Thin Quad Flat Pack  
160-Lead Lead Free Thin Quad Flat Pack  
160-Lead Thin Quad Flat Pack  
Industrial  
160-Lead Lead Free Thin Quad Flat Pack  
100-Lead Thin Quad Flat Pack  
83  
CY37128VP100-83AC  
CY37128VP100-83AXC  
CY37128VP100-83BBC  
CY37128VP160-83AC  
CY37128VP160-83AXC  
CY37128VP100-83AI  
CY37128VP100-83AXI  
CY37128VP100-83BBI  
CY37128VP160-83AI  
CY37128VP160-83AXI  
5962-9952201QYA  
Commercial  
100-Lead Lead Free Thin Quad Flat Pack  
BB100 100-Ball Fine-Pitch Ball Grid Array  
A160  
A160  
A100  
A100  
160-Lead Thin Quad Flat Pack  
160-Lead Lead Free Thin Quad Flat Pack  
100-Lead Thin Quad Flat Pack  
Industrial  
100-Lead Lead Free Thin Quad Flat Pack  
BB100 100-Ball Fine-Pitch Ball Grid Array  
A160  
A160  
Y84  
160-Lead Thin Quad Flat Pack  
160-Lead Lead Free Thin Quad Flat Pack  
84-Lead Ceramic Leaded Chip Carrier  
160-Lead Thin Quad Flat Pack  
Military  
192  
100 CY37192VP160-100AC  
CY37192VP160-100AXC  
A160  
A160  
A160  
A160  
A160  
Commercial  
160-Lead Lead Free Thin Quad Flat Pack  
160-Lead Thin Quad Flat Pack  
66  
CY37192VP160-66AC  
CY37192VP160-66AXC  
CY37192VP160-66AI  
Commercial  
Industrial  
160-Lead Lead Free Thin Quad Flat Pack  
160-Lead Thin Quad Flat Pack  
Document #: 38-03007 Rev. *E  
Page 47 of 64  
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Ultra37000 CPLD Family  
3.3V Ordering Information (continued)  
Speed  
Macrocells (MHz)  
Package  
Name  
Operating  
Range  
Ordering Code  
Package Type  
256  
100 CY37256VP160-100AC  
CY37256VP160-100AXC  
CY37256VP208-100NC  
A160  
A160  
N208  
160-Lead Thin Quad Flat Pack  
Commercial  
160-Lead Lead Free Thin Quad Flat Pack  
208-Lead Plastic Quad Flat Pack  
CY37256VP256-100BGC BG292 292-Ball Plastic Ball Grid Array  
CY37256VP256-100BBC  
CY37256VP160-100AI  
CY37256VP160-100AXI  
CY37256VP160-66AC  
CY37256VP160-66AXC  
CY37256VP208-66NC  
CY37256VP256-66BGC  
CY37256VP256-66BBC  
CY37256VP160-66AI  
CY37256VP256-66BGI  
CY37256VP256-66BBI  
5962-9952401QZC  
BB256 256-Ball Fine-Pitch Ball Grid Array  
A160  
A160  
A160  
A160  
N208  
160-Lead Thin Quad Flat Pack  
Industrial  
160-Lead Lead Free Thin Quad Flat Pack  
160-Lead Thin Quad Flat Pack  
66  
Commercial  
160-Lead Lead Free Thin Quad Flat Pack  
208-Lead Plastic Quad Flat Pack  
BG292 292-Ball Plastic Ball Grid Array  
BB256 256-Ball Fine-Pitch Ball Grid Array  
A160  
160-Lead Thin Quad Flat Pack  
Industrial  
BG292 292-Ball Plastic Ball Grid Array  
BB256 256-Ball Fine-Pitch Ball Grid Array  
U162  
N208  
160-Lead Ceramic Quad Flat Pack  
208-Lead Plastic Quad Flat Pack  
Military  
384  
512  
83  
66  
CY37384VP208-83NC  
CY37384VP256-83BGC  
CY37384VP208-66NC  
CY37384VP256-66BGC  
CY37384VP208-66NI  
CY37384VP256-66BGI  
CY37512VP208-83NC  
CY37512VP256-83BGC  
CY37512VP352-83BGC  
CY37512VP400-83BBC  
CY37512VP208-66NC  
CY37512VP256-66BGC  
CY37512VP352-66BGC  
CY37512VP400-66BBC  
CY37512VP208-66NI  
CY37512VP256-66BGI  
CY37512VP352-66BGI  
CY37512VP400-66BBI  
5962-9952601QZC  
Commercial  
BG292 292-Ball Plastic Ball Grid Array  
N208 208-Lead Plastic Quad Flat Pack  
BG292 292-Ball Plastic Ball Grid Array  
N208 208-Lead Plastic Quad Flat Pack  
BG292 292-Ball Plastic Ball Grid Array  
N208 208-Lead Plastic Quad Flat Pack  
Commercial  
Industrial  
83  
66  
Commercial  
BG292 292-Ball Plastic Ball Grid Array  
BG388 388-Ball Plastic Ball Grid Array  
BB400 400-Ball Fine-Pitch Ball Grid Array  
N208  
208-Lead Plastic Quad Flat Pack  
Commercial  
Industrial  
Military  
BG292 292-Ball Plastic Ball Grid Array  
BG388 388-Ball Plastic Ball Grid Array  
BB400 400-Ball Fine-Pitch Ball Grid Array  
N208  
208-Lead Plastic Quad Flat Pack  
BG292 292-Ball Plastic Ball Grid Array  
BG388 388-Ball Plastic Ball Grid Array  
BB400 400-Ball Fine-Pitch Ball Grid Array  
U208  
208-Lead Ceramic Quad Flat Pack  
Document #: 38-03007 Rev. *E  
Page 48 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Package Diagrams  
44-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack A44  
51-85064-*B  
44-Lead Lead (Pb)-Free Plastic Leaded Chip Carrier J67  
51-85003-*A  
Document #: 38-03007 Rev. *E  
Page 49 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Package Diagrams (continued)  
44-Lead Ceramic Leaded Chip Carrier Y67  
51-80014-**  
Document #: 38-03007 Rev. *E  
Page 50 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Package Diagrams (continued)  
48-Ball (7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch) Thin BGA BA48D  
51-85109-*C  
84-Lead Lead (Pb)-Free Plastic Leaded Chip Carrier J83  
51-85006-*A  
Document #: 38-03007 Rev. *E  
Page 51 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Package Diagrams (continued)  
84-Lead Ceramic Leaded Chip Carrier Y84  
51-80095-*A  
Document #: 38-03007 Rev. *E  
Page 52 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Package Diagrams (continued)  
100-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack (TQFP) A100  
51-85048-*B  
Document #: 38-03007 Rev. *E  
Page 53 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Package Diagrams (continued)  
100-Ball Thin Ball Grid Array (11 x 11 x 1.4 mm) BB100  
51-85107-*B  
Document #: 38-03007 Rev. *E  
Page 54 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Package Diagrams (continued)  
160-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack (24 x 24 x 1.4 mm) (TQFP) A160  
51-85049-*B  
Document #: 38-03007 Rev. *E  
Page 55 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Package Diagrams (continued)  
160-Lead Ceramic Quad Flatpack (Cavity Up) U162  
25.35 0.10  
(.998 .004)  
TYP.  
DIMENSION IN MM (INCH)  
REFERENCE JEDEC: N/A  
PKG. WEIGHT: 6-7gms  
PIN 1  
0.650(.0256)  
TYP.  
0.300(.012)  
TYP.  
R 0.13(.005)  
MIN.  
0°-7°  
28.00 0.10  
(1.102 .004)  
SQ.  
0.20 MIN.  
(.008 MIN.)  
0° MIN.  
31.20 0.25  
(1.228 .010)  
SQ.  
DETAIL A  
SEE DETAIL A  
0.15 0.02  
SEATING PLANE  
2.03(.080)  
2.79(.110)  
(.006 .001)  
0.050(.002)  
0.500(.020)  
0.51 0.20  
(.020 .008)  
51-80106-*A  
Document #: 38-03007 Rev. *E  
Page 56 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Package Diagrams (continued)  
208-Lead Plastic Quad Flatpack N208  
51-85069-*B  
Document #: 38-03007 Rev. *E  
Page 57 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Package Diagrams (continued)  
208-Lead Ceramic Quad Flatpack (Cavity Up) U208  
DIMENSIONS IN MM (INCH)  
REFERENCE JEDEC: N/A  
PKG. WEIGHT: 6-7gms  
PIN 1  
0.50(.0197)  
TYP.  
0.20(.008)  
TYP.  
R 0.13(.005)  
MIN.  
0°-7°  
28.00 0.10  
(1.102 .008)  
SQ.  
0.20 MIN.  
(.008 MIN.)  
31.22 0.25  
(1.229 .010)  
SQ.  
0° MIN.  
DETAIL A  
SEE DETAIL A  
3.43(.135)  
3.94(.155)  
SEATING PLANE  
0.15 0.02  
(.006 .001)  
0.050(.002)  
0.500(.020)  
0.51 0.20  
(.020 .008)  
51-80105-*B  
Document #: 38-03007 Rev. *E  
Page 58 of 64  
[+] Feedback  
Ultra37000 CPLD Family  
Package Diagrams (continued)  
256-Ball FBGA (17 x 17 mm) BB256  
TOP VIEW  
BOTTOM VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
PIN 1 CORNER  
Ø0.45 0.05(256X)-CPLD DEVICES (37K & 39K)  
PIN 1 CORNER  
+0.10  
Ø0.50 (256X)-ALL OTHER DEVICES  
-0.05  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16  
16 15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
T
M
N
P
R
T
1.00  
B
7.50  
15.00  
A
17.00 0.10  
A
SEATING PLANE  
0.20(4X)  
A1  
C
REFERENCE JEDEC MO-192  
A1 0.36 0.56  
1.40 MAX. 1.70 MAX.  
A
51-85108-*F  
Document #: 38-03007 Rev. *E  
Page 59 of 64  
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Ultra37000 CPLD Family  
Package Diagrams (continued)  
292-Ball Plastic Ball Grid Array PBGA (27 x 27 x 2.33 mm) BG292  
51-85097-*B  
Document #: 38-03007 Rev. *E  
Page 60 of 64  
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Ultra37000 CPLD Family  
Package Diagrams (continued)  
388-Ball Plastic Ball Grid Array PBGA (35 x 35 x 2.33 mm) BG388  
51-85103-*C  
Document #: 38-03007 Rev. *E  
Page 61 of 64  
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Ultra37000 CPLD Family  
Package Diagrams (continued)  
400-Ball FBGA (21 x 21 x 1.4 mm) BB400  
51-85111-*A  
ViewDraw and SpeedWave are trademarks of ViewLogic. Windows is a registered trademark of Microsoft Corporation. Warp is  
a registered trademark, and In-System Reprogrammable, ISR, Warp Professional, Warp Enterprise, and Ultra37000 are trade-  
marks, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks  
of their respective holders.  
Document #: 38-03007 Rev. *E  
Page 62 of 64  
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
[+] Feedback  
Ultra37000 CPLD Family  
Addendum  
3.3V Operating Range  
(CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143BAC)  
[2]  
Range  
Ambient Temperature  
Junction Temperature  
V
CC  
Commercial  
0°C to +70°C  
0°C to +90°C  
3.3V ± 0.16V  
Document #: 38-03007 Rev. *E  
Page 63 of 64  
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Ultra37000 CPLD Family  
Document History Page  
Document Title: Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs  
Document Number: 38-03007  
Issue  
Date  
Orig. of  
Change  
REV. ECN NO.  
Description of Change  
**  
106272  
124942  
04/18/01  
03/21/03  
SZV  
Change from Spec number: 38-00475 to 38-03007  
*A  
OOR  
Updated 3.3V V requirements for –144 speeds  
CC  
Added an Addendum  
*B  
*C  
126262  
128125  
05/09/03  
07/16/03  
TEH  
Changed pinout for CY37128V BB100 package  
HOM  
Obsoleted following 3.3V PLCC packaged devices:  
CY37032VP44-143JC  
CY37032VP44-100JC  
CY37032VP44-100JI  
CY37064VP44-143JC  
CY37064VP84-143JC  
CY37064VP44-100JC  
CY37064VP84-100JC  
CY37064VP44-100JI  
CY37064VP84-100JI  
CY37128VP84-125JC  
CY37128VP84-83JC  
CY37128VP84-83JI  
*D  
282709  
See ECN  
YDT  
Changed package diagrams and labels for consistency  
Added Lead (Pb)-free logo on first page, as well as a note in Features  
Added Lead (Pb)-free package diagram labels  
Added Lead-free Parts to Ordering Information  
CY37032P44-200AXC, CY37032P44-200JXC, CY37032P44-154AXI,  
CY37032P44-154JXI, CY37032P44-125AXC, CY37032P44-125JXC,  
CY37064P44-200AXC, CY37064P44-200JXC, CY37064P100-200AXC,  
CY37064P44-154AXI, CY37064P44-154JXI, CY37064P44-125AXC,  
CY37064P44-125JXC, CY37064P100-125AXC, CY37064P44-125AXI,  
CY37064P100-125AXI, CY37128P84-167JXC, CY37128P100-167AXC,  
CY37128P160-167AXC, CY37128P84-125JXC, CY37128P100-125AXC,  
CY37128P160-125AXC, CY37128P84-125JXI, CY37128P100-125AXI,  
CY37128P160-125AXI, CY37128P84-100JXC, CY37128P100-100AXC,  
CY37128P160-100AXC, CY37128P100-100AXI, CY37192P160-154AXC,  
CY37192P160-125AXC, CY37192P160-125AXI, CY37192P160-83AXC,  
CY37192P160-83AXI, CY37256P160-154AXC, CY37256P160-125AXC,  
CY37256P160-125AXI, CY37256P160-83AXC, CY37256P160-83AXI,  
CY37032VP44-143AXC, CY37032VP44-100AXC, CY37032VP44-100AXI,  
CY37032VP44-100JXI, CY37064VP44-143AXC, CY37064VP100-143AXC,  
CY37064VP44-100AXC, CY37064VP100-100AXC, CY37064VP44-100AXI,  
CY37064VP100-100AXI, CY37128VP100-125AXC, CY37128VP160-125AXC,  
CY37128VP160-125AXI, CY37128VP100-83AXC, CY37128VP160-83AXC,  
CY37128VP100-83AXI, CY37128VP160-83AXI, CY37192VP160-100AXC,  
CY37192VP160-66AXC, CY37256VP160-100AXC, CY37256VP160-100AXI,  
CY37256VP160-66AXC  
*E  
321635  
See ECN  
PCX  
Added Package Diagram BG292  
Updated all PBGA package type information (BG292 & BG388)  
Document #: 38-03007 Rev. *E  
Page 64 of 64  
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