CY8C24223A, CY8C24423A
PSoC® Programmable System-on-Chip™
■ Additional System Resources
❐ I C™ Slave, Master, and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
Features
2
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 12 MHz
❐ 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ On-Chip Precision Voltage Reference
❐ 4.75V to 5.25V Operating Voltage
❐ Extended Temperature Range: -40°C to +125°C
■ Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full-Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
■ Advanced Peripherals (PSoC Blocks)
❐ Six Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
❐ Complex Breakpoint Structure
• Up to 9-Bit DACs
❐ 128K Bytes Trace Memory
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
Logic Block Diagram
Analog
Port 2 Port 1 Port 0
Drivers
PSoC CORE
• Full-Duplex UART
• Multiple SPI™ Masters or Slaves
• Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
System Bus
Global Digital Interconnect
Global Analog Interconnect
■ Precision, Programmable Clocking
❐ Internal ± 4% 24 MHz Oscillator
SRAM
256 Bytes
SROM
Flash 4K
❐ High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
Sleep and
Watchdog
CPUCore(M8C)
Interrupt
Controller
■ Flexible On-Chip Memory
Multiple Clock Sources
(IncludesIMO,ILO,PLL,andECO)
❐ 4K Bytes Flash Program Storage 100 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref
Analog
Digital
❐ Flexible Protection Modes
Block
Array
Block Array
■ Programmable Pin Configurations
(1 Row,
4 Blocks)
(2 Columns,
6 Blocks)
Analog
Input
Muxing
❐ 25 mA Sink on All GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐ Up to Ten Analog Inputs on GPIO
❐ Two 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on All GPIO
POR and LVD
System Resets
Internal
Voltage
Ref.
Digital
Clocks
Multiply
Accum .
I2C
Decimator
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 3-12029 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 11, 2008
CY8C24223A, CY8C24423A
Figure 2. Analog System Block Diagram
Analog System
The Analog System is composed of six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are:
P0[7]
P0[5]
P0[6]
P0[4]
P0[3]
P0[1]
P0[2]
P0[0]
■ Analog-to-digital converters (up to two, with 6 to 14-bit
resolution, selectable as Incremental, Delta Sigma, and SAR)
P2[6]
P2[4]
■ Filters (two and four pole band-pass, low-pass, and notch)
■ Amplifiers (up to two, with selectable gain to 48x)
■ Instrumentation amplifiers (one with selectable gain to 93x)
■ Comparators (up to two, with 16 selectable thresholds)
■ DACs (up to two, with 6 to 9-bit resolution)
P2[3]
P2[1]
P2[2]
P2[0]
■ Multiplying DACs (up to two, with 6 to 9-bit resolution)
■ High current output drivers (two with 30 mA drive as a PSoC
Core resource)
Array Input Configuration
■ 1.3V reference (as a System Resource)
■ DTMF Dialer
ACI0[1:0]
ACI1[1:0]
■ Modulators
■ Correlators
Block Array
■ Peak Detectors
ACB00
ASC10
ASD20
ACB01
■ Many other topologies possible
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
ASD11
ASC21
Analog Reference
Interface to
Digital System
Reference
Generators
Ref Hi
Ref Lo
AGND
AGNDIn
Ref In
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 3-12029 Rev. *E
Page 3 of 31
CY8C24223A, CY8C24423A
Additional System Resources
Getting Started
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Brief
statements describing the merits of each system resource follow:
The quickest path to understanding the PSoC silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications. For in-depth information, along with
detailed programming information, refer the PSoC Program-
mable Sytem-on-Chip Technical Reference Manual.
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
For up-to-date Ordering, Packaging, and Electrical Specification
information, refer the latest PSoC device data sheets on the web
■ A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math as well
as digital filters.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com, click the Online Store shopping cart
icon at the bottom of the web page, and click PSoC (Program-
mable System-on-Chip) to view a current list of available items.
■ The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■ TheI2Cmoduleprovides100and400kHzcommunicationover
two wires. Slave, master, and multi-master modes are all
supported.
■ Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
Technical Training
Free PSoC technical training is available for beginners and is
taught by a marketing or application engineer over the phone.
PSoC training classes cover designing, debugging, advanced
analog, and application-specific classes covering topics, such as
Design Support located on the left side of the web page, and
select Technical Training for more details.
■ An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources available
for specific PSoC device groups. The PSoC device covered by
this data sheet is highlighted.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
Support located on the left side of the web page, and select
CYPros Consultants.
Table 1. PSoC Device Characteristics
Technical Support
PSoC Part
Number
PSoC application engineers take pride in fast and accurate
response. They can be reached with a four-hour guaranteed
CY8C29x66
CY8C27x43
up to 4
64
16 12
4
4
4
4
12 2K
32K
16K
Application Notes
up to 2
44
8
12
12 256
Bytes
A long list of application notes can assist you in every aspect of
your design effort. To view the PSoC application notes, go to the
http://www.cypress.com web site and select Application Notes
under the Design Resources list located in the center of the web
page. Application notes are listed by date as default.
CY8C24x94
CY8C24x23
49
1
4
4
48
12
2
2
2
2
6
6
1K
16K
4K
up to 1
24
256
Bytes
CY8C24x23A up to 1
24
4
4
4
12
28
8
2
0
0
2
2
2
6
256
Bytes
4K
8K
4K
CY8C21x34
up to 1
28
4a 512
Bytes
4a 256
Bytes
CY8C21x23
16
1
a. Limited analog functionality.
Document Number: 3-12029 Rev. *E
Page 4 of 31
CY8C24223A, CY8C24423A
PSoC Designer Software Subsystems
Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
Device Editor
development
environment
for
the
Programmable
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows NT 4.0, Windows 2000, Windows
PSoC Designer helps the customer to select an operating
configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
PSoC Designer sets up power on initialization tables for selected
PSoC block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components and, if the project uses more
than one operating configuration, contains routines to switch
between different sets of PSoC block configurations at run time.
PSoC Designer can print out a configuration sheet for a given
project configuration for use during application programming in
conjunction with the Device Data Sheet. After the framework is
generated, the user can add application-specific code to flesh
out the framework. It is also possible to change the selected
components and regenerate the framework.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Figure 3. PSoC Designer Subsystems
Context
Graphical Designer
PSoC
Sensitive
Interface
Help
Designer
Design Browser
The Design Browser allows users to select and import
preconfigured designs into the user’s project. Users can easily
browse
a
catalog of preconfigured designs to facilitate
time-to-design. Examples provided in the tools include a
300-baud modem, LIN Bus master and slave, fan controller, and
magnetic card reader.
Importable
Design
Database
PSoC
Configuration
Sheet
Application Editor
Device
Database
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.
PSoC
Designer
Core
Application
Database
Assembler. The macro assembler allows the assembly code to
be merged seamlessly with C code. The link libraries automati-
cally use absolute addressing or can be compiled in relative
mode, and linked with other software modules to get absolute
addressing.
Manufacturing
Information
File
Engine
Project
Database
User
Modules
Library
C Language Compiler. A C language compiler is available that
supports Cypress MicroSystems’ PSoC family devices. Even if
you have never worked in the C language before, the product
quickly allows you to create complete C programs for the PSoC
family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Emulation
Pod
In-Circuit
Emulator
Device
Programmer
Document Number: 3-12029 Rev. *E
Page 5 of 31
CY8C24223A, CY8C24423A
Debugger
of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides
high-level functions to control and respond to hardware events
at run-time. The API also provides optional interrupt service
routines that you can adapt as needed.
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by
interconnecting user modules to each other and the IO pins. At
this stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to developing code for the project, you
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specification and provides the high-level user
module API functions.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of the parallel or USB port. The base unit is universal and
operates with all PSoC devices. Emulation pods for each device
family are available separately. The emulation pod takes the
place of the PSoC device in the target board and performs full
speed (12 MHz) operation.
Figure 4. User Module and Source Code Development Flows
Device Editor
Designing with User Modules
Placement
User
Module
Selection
Source
Code
Generator
and
Parameter
-ization
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Iterative development cycles permit you to adapt the
hardware as well as the software. This substantially lowers the
risk of having to select a different part to meet the final design
requirements.
Generate
Application
Application Editor
Source
Code
Editor
Project
Manager
Build
Manager
To speed the development process, the PSoC Designer
Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library
contains over 50 common peripherals such as ADCs, DACs
Timers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Build
All
Debugger
Event &
Breakpoint
Manager
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures one or more digital PSoC blocks, one for each 8 bits
Interface
to ICE
Storage
Inspector
Document Number: 3-12029 Rev. *E
Page 6 of 31
CY8C24223A, CY8C24423A
The next step is to write your main program, and any
sub-routines using PSoC Designer’s Application Editor
subsystem. The Application Editor includes a Project Manager
that allows you to open the project source code files (including
all generated code files) from a hierarchal view. The source code
editor provides syntax coloring and advanced edit features for
both C and assembly language. File search capabilities include
simple string searches and recursive “grep-style” patterns. A
single mouse click invokes the Build Manager. It employs a
professional-strength “makefile” system to automatically analyze
all file dependencies and run the compiler and assembler as
necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in a
console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
Table 2. Acronyms (continued)
Acronym
LSb
Description
least-significant bit
LVD
low voltage detect
most-significant bit
program counter
MSb
PC
PLL
phase-locked loop
power on reset
POR
PPOR
precision power on reset
®
PSoC
Programmable System-on-Chip™
pulse width modulator
PWM
SC
switched capacitor
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
SRAM
static random access memory
Units of Measure
A units of measure table is located in the Electrical Specifications
measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this
document.
Table 2. Acronyms
Acronym
AC
Description
alternating current
ADC
API
analog-to-digital converter
application programming interface
central processing unit
continuous time
CPU
CT
DAC
DC
digital-to-analog converter
direct current
ECO
external crystal oscillator
EEPROM electrically erasable programmable read-only
memory
FSR
GPIO
GUI
HBM
ICE
full scale range
general purpose IO
graphical user interface
human body model
in-circuit emulator
ILO
internal low speed oscillator
internal main oscillator
input/output
IMO
IO
IPOR
imprecise power on reset
Document Number: 3-12029 Rev. *E
Page 7 of 31
CY8C24223A, CY8C24423A
Pinouts
The CY8C24x23A automotive PSoC device is available in a variety of packages which are listed and illustrated in the following tables.
Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO.
20-Pin Part Pinout
Table 3. 20-Pin Part Pinout (SSOP)
Type
Figure 5. CY8C24223A 20-Pin PSoC Device
Pin
No.
Pin
Name
Description
Digital Analog
A, I,P0[7]
A,IO, P0[5]
A,IO, P0[3]
A,I, P0[1]
Vdd
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
1
IO
IO
I
P0[7] Analog column mux input
P0[6], A,I
2
IO
P0[5] Analog column mux input and column
output
P0[4], A,I
P0[2], A,I
3
IO
IO
I
P0[3] Analog column mux input and column
output
Vss
P0[0], A,I
XRES
P1[6]
SSOP
I2CSCL,P1[7]
I2C SDA,P1[5]
P1[3]
4
5
6
7
8
9
IO
P0[1] Analog column mux input
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA
Power
IO
Vss
Ground connection
I2CSCL,XTALin,P1[1]
Vss
P1[7] I2C Serial Clock (SCL)
P1[5] I2C Serial Data (SDA)
P1[3]
10
IO
IO
IO
P1[1] Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*
10 Power
11 IO
Vss
Ground connection
P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*
12 IO
13 IO
14 IO
15 Input
P1[2]
P1[4] Optional External Clock Input (EXTCLK)
P1[6]
XRES Active high external reset with internal pull
down
16 IO
17 IO
18 IO
19 IO
20 Power
I
I
I
I
P0[0] Analog column mux input
P0[2] Analog column mux input
P0[4] Analog column mux input
P0[6] Analog column mux input
Vdd
Supply voltage
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 3-12029 Rev. *E
Page 8 of 31
CY8C24223A, CY8C24423A
28-Pin Part Pinout
Table 4. 28-Pin Part Pinout (SSOP)
Pi
n
Type
Figure 6. CY8C24423A 28-Pin PSoC Device
Pin
Description
Digi- Ana-
No
.
Name
tal
log
A, I,P0[7]
A,IO, P0[5]
A,IO, P0[3]
A,I, P0[1]
1
2
3
Vdd
P0[6], A, I
P0[4], A, I
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
IO
I
P0[7] Analog column mux input
IO
IO
IO
IO
I
P0[5] Analog column mux input and column
output
P0[2], A, I
4
P2[7]
P0[0], A, I
5
P2[5]
P2[6],Ex ternalVRef
P2[4],Ex ternalAGND
P2[2], A, I
6
7
8
3
P0[3] Analog column mux input and column
output
A,I, P2[3]
A, I,P2[1]
SSOP
4
5
6
7
8
9
IO
P0[1] Analog column mux input
Vss
9
P2[0], A, I
IO
P2[7]
I2CSCL,P1[7]
I2CSDA,P1[5]
P1[3]
XRES
P1[6]
10
11
12
13
14
IO
P2[5]
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA
IO
I
I
P2[3] Direct switched capacitor block input
P2[1] Direct switched capacitor block input
I2CSCL,XTALin,P1[1]
Vss
IO
Power
Vss
Ground connection
10 IO
11 IO
12 IO
13 IO
P1[7] I2C Serial Clock (SCL)
P1[5] I2C Serial Data (SDA)
P1[3]
P1[1] Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*
14 Power
15 IO
Vss
Ground connection
P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*
16 IO
17 IO
18 IO
19 Input
P1[2]
P1[4] Optional External Clock Input (EXTCLK)
P1[6]
XRES Active high external reset with internal pull
down
20 IO
21 IO
22 IO
23 IO
24 IO
25 IO
26 IO
27 IO
28 Power
I
I
P2[0] Direct switched capacitor block input
P2[2] Direct switched capacitor block input
P2[4] External Analog Ground (AGND)
P2[6] External Voltage Reference (VRef)
P0[0] Analog column mux input
I
I
I
I
P0[2] Analog column mux input
P0[4] Analog column mux input
P0[6] Analog column mux input
Vdd
Supply voltage
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 3-12029 Rev. *E
Page 9 of 31
CY8C24223A, CY8C24423A
Register Mapping Tables
Register Reference
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.
This section lists the registers of the CY8C24x23A automotive
PSoC device. For detailed register information, refer the PSoC
Programmable System-on-Chip Technical Reference Manual.
Register Conventions
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Abbreviations Used
The register conventions specific to this section are listed in the
following table.
Table 5. Abbreviations
Convention
Description
Read register or bit(s)
R
W
L
Write register or bit(s)
Logical register or bit(s)
Clearable register or bit(s)
Access is bit specific
C
#
Document Number: 3-12029 Rev. *E
Page 10 of 31
CY8C24223A, CY8C24423A
Table 6. Register Map Bank 0 Table: User Space
PRT0DR
PRT0IE
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
RW
RW
RW
RW
RW
RW
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
RW
RW
RW
RW
RW
RW
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
I2C_CFG
I2C_SCR
I2C_DR
RW
#
RW
#
I2C_MSCR
INT_CLR0
INT_CLR1
RW
RW
INT_CLR3
INT_MSK3
RW
RW
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
#
AMX_IN
RW
INT_MSK0
INT_MSK1
INT_VC
RW
RW
RC
W
W
RW
#
ARF_CR
CMP_CR0
ASY_CR
CMP_CR1
RW
#
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL_X
#
RC
RC
RW
RW
W
W
RW
#
#
RW
#
W
RW
#
MUL_Y
W
MUL_DH
MUL_DL
ACC_DR1
ACC_DR0
R
R
#
RW
RW
W
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 3-12029 Rev. *E
Page 11 of 31
CY8C24223A, CY8C24423A
Table 6. Register Map Bank 0 Table: User Space (continued)
DCB03DR2
DCB03CR0
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
RW
#
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
ACC_DR3
ACC_DR2
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RW
RW
RW
RW
RW
RW
RW
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
CPU_F
RL
CPU_SCR1
CPU_SCR0
#
#
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Table 7. Register Map Bank 1 Table: Configuration Space
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
80
RW
RW
RW
RW
RW
RW
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
RW
RW
RW
RW
RW
RW
RW
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
RW
RW
RW
RW
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 3-12029 Rev. *E
Page 12 of 31
CY8C24223A, CY8C24423A
Table 7. Register Map Bank 1 Table: Configuration Space (continued)
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
ASC21CR3
97
RW
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
RW
RW
RW
RW
RW
RW
RW
R
DBB00FN
DBB00IN
DBB00OU
RW
RW
RW
CLK_CR0
CLK_CR1
ABF_CR0
AMD_CR0
RW
RW
RW
RW
DBB01FN
DBB01IN
DBB01OU
RW
RW
RW
VLT_CMP
AMD_CR1
ALT_CR0
RW
RW
DCB02FN
DCB02IN
DCB02OU
RW
RW
RW
IMO_TR
ILO_TR
BDG_TR
ECO_TR
W
W
RW
W
DCB03FN
DCB03IN
DCB03OU
RW
RW
RW
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RW
RW
RW
RW
RW
RW
RW
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
CPU_F
RL
CPU_SCR1
CPU_SCR0
#
#
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 3-12029 Rev. *E
Page 13 of 31
CY8C24223A, CY8C24423A
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C24x23A automotive PSoC device. For the latest electrical
specifications, visit http://www.cypress.com/psoc.
o
o
o
Specifications are valid for -40 C ≤ T ≤ 125 C and T ≤ 135 C, except where noted.
A
J
Figure 7. Voltage versus CPU Frequency
5.25
4.75
Valid
Operating
Region
3.00
93 kHz
12 MHz
24 MHz
CPUFrequency
The following table lists the units of measure that are used in this section.
Table 8. Units of Measure
Symbol
Unit of Measure
degree Celsius
Symbol
Unit of Measure
o
C
μW
mA
ms
mV
nA
ns
microwatts
milli-ampere
milli-second
milli-volts
dB
decibels
fF
femto farad
hertz
Hz
KB
Kbit
kHz
kΩ
1024 bytes
1024 bits
nanoampere
nanosecond
nanovolts
kilohertz
nV
W
kilohm
ohm
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
megahertz
megaohm
pA
pF
pp
picoampere
picofarad
microampere
microfarad
microhenry
microsecond
microvolts
peak-to-peak
ppm
ps
sps
s
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
microvolts root-mean-square
V
Document Number: 3-12029 Rev. *E
Page 14 of 31
CY8C24223A, CY8C24423A
Absolute Maximum Ratings
Table 9. Absolute Maximum Ratings
Symbol
Description
Storage Temperature
Min
Typ
Max
Units
Notes
o
T
-55
+25
+125
C
Higher storage temperatures
reduce data retention time.
STG
Recommended storage temper-
ature is +25°C ± 25°C. Storage
o
temperatures above 65 C
degrades reliability. Maximum
combined storage and operational
time at +125°C is 7000 hours.
o
T
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
-40
-0.5
–
–
–
–
–
–
–
+125
+5.75
Vdd + 0.5
Vdd + 0.5
+25
C
A
Vdd
V
V
V
V
Vss - 0.5
Vss - 0.5
-25
IO
DC Voltage Applied to Tri-state
Maximum Current into any Port Pin
Electro Static Discharge Voltage
Latch-up Current
V
IOZ
MIO
I
mA
V
ESD
LU
2000
–
–
Human Body Model ESD.
200
mA
Operating Temperature
Table 10. Operating Temperature
Symbol
Description
Min
-40
-40
Typ
–
Max
+125
+135
Units
Notes
o
T
Ambient Temperature
Junction Temperature
C
A
o
T
–
C
The temperature rise from ambient
to junction is package specific. See
on page 29. The user must limit the
power consumption to comply with
this requirement.
J
Document Number: 3-12029 Rev. *E
Page 15 of 31
CY8C24223A, CY8C24423A
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
A
Table 11. DC Chip-Level Specifications
Symbol
Description
Min
4.75
–
Typ
–
Max
5.25
8
Units
V
Notes
Vdd
Supply Voltage
Supply Current
o
I
5
mA
Conditions are Vdd = 5.25V, -40 C ≤ T
DD
A
o
≤ 125 C, CPU = 3 MHz, SYSCLK
doubler disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75 kHz,
analog power = off.
I
Sleep (Mode) Current with POR, LVD, Sleep
–
–
–
4
4
6
13
100
15
μA
μA
μA
Conditions are with internal slow speed
SB
a
o
Timer, and WDT.
oscillator, Vdd = 5.25V, -40 C ≤ T
≤
A
o
55 C. Analog power = off.
I
Sleep (Mode) Current with POR, LVD, Sleep
Conditions are with internal slow speed
SBH
a
o
Timer, and WDT at high temperature.
oscillator, Vdd = 5.25V, 55 C < T
≤
A
o
125 C. Analog power = off.
I
Sleep (Mode) Current with POR, LVD, Sleep
Conditions are with properly loaded, 1
SBXTL
a
Timer, WDT, and external crystal.
μW max, 32.768 kHz crystal.
o
o
Vdd = 5.25V, -40 C ≤ T ≤ 55 C.
A
Analog power = off.
I
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal at high temper-
–
6
100
μA
Conditions are with properly loaded,
SBXTLH
1μW max, 32.768 kHz crystal.
a
o
o
ature.
Vdd = 5.25V, 55 C < T ≤ 125 C.
A
Analog power = off.
V
Reference Voltage (Bandgap)
1.25
1.3
1.35
V
Trimmed for appropriate Vdd.
REF
a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar
functions enabled.
DC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance.
A
Table 12. DC GPIO Specifications
Symbol
Description
Min
4
Typ
5.6
5.6
–
Max
Units
kΩ
Notes
R
Pull up Resistor
8
8
–
PU
PD
OH
R
Pull down Resistor
High Output Level
4
kΩ
V
3.5
V
IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])).
V
Low Output Level
–
–
0.75
V
IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])). Total IOL budget
of 150 mA.
OL
V
V
V
I
Input Low Level
–
2.2
–
–
–
0.8
V
V
Vdd = 4.75 to 5.25
Vdd = 4.75 to 5.25
IL
IH
H
Input High Level
Input Hysterisis
60
1
–
–
mV
nA
pF
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
Gross tested to 1 μA
IL
C
–
3.5
10
Package and pin dependent.
IN
o
Temp = 25 C
C
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent.
OUT
o
Temp = 25 C
Document Number: 3-12029 Rev. *E
Page 16 of 31
CY8C24223A, CY8C24423A
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
A
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.
Table 13. DC Operational Amplifier Specifications
Symbol
Description
Min
–
Typ
Max
Units
Notes
V
Input Offset Voltage (absolute value) Low Power
Input Offset Voltage (absolute value) Mid Power
Input Offset Voltage (absolute value) High Power
1.6
1.3
1.2
11
9
9
mV
mV
mV
OSOA
–
–
o
TCV
Input Offset Voltage Drift
–
7.0
200
4.5
35.0
–
μV/ C
OSOA
I
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
–
pA Gross tested to 1 μA
pF
EBOA
C
–
10
Package and pin
INOA
o
dependent. Temp = 25 C.
V
Common Mode Voltage Range
Common Mode Voltage Range (high power or high
opamp bias)
0.0
0.5
–
–
Vdd
Vdd - 0.5
V
The common-mode input
voltage range is
CMOA
measured through an
analog output buffer. The
specification includes the
limitations imposed by the
characteristics of the
analog output buffer.
G
Open Loop Gain
Power = Low
Power = Medium
Power = High
Specification is applicable
OLOA
–
–
–
80
80
80
dB athighpower. Forallother
dB bias modes (except high
dB power, high opamp bias),
minimum is 60 dB.
V
V
High Output Voltage Swing (worst case internal load)
Power = Low
Power = Medium
Power = High
OHIGHOA
OLOWOA
SOA
Vdd - 0.2
Vdd - 0.2
Vdd - 0.5
–
–
–
–
–
–
V
V
V
Low Output Voltage Swing (worst case internal load)
Power = Low
Power = Medium
Power = High
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
I
Supply Current (including associated AGND buffer)
Power = Low
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
μA
μA
μA
μA
μA
μA
Power = High, Opamp Bias = High
PSRR
Supply Voltage Rejection Ratio
–
80
–
dB Vss ≤ VIN ≤ (Vdd - 2.25) or
OA
(Vdd - 1.25V) ≤ VIN ≤ Vdd
Document Number: 3-12029 Rev. *E
Page 17 of 31
CY8C24223A, CY8C24423A
DC Low Power Comparator Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
A
Table 14. DC Low Power Comparator Specifications
Symbol
Description
Low power comparator (LPC) reference voltage range
LPC supply current
Min
0.2
–
Typ
–
Max
Vdd - 1
40
Units
V
V
I
REFLPC
10
2.5
μA
mV
SLPC
V
LPC voltage offset
–
30
OSLPC
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
A
Table 15. DC Analog Output Buffer Specifications
Symbol
Description
Input Offset Voltage (Absolute Value)
Input Offset Voltage Drift
Min
Typ
3
Max
Units
mV
μV/°C
V
V
–
18
OSOB
TCV
–
+6
–
–
OSOB
CMOB
V
Common-Mode Input Voltage Range
Output Resistance
0.5
Vdd - 1.0
R
–
1
–
W
OUTOB
V
V
High Output Voltage Swing (Load = 32 ohms to Vdd/2)
Low Output Voltage Swing (Load = 32 ohms to Vdd/2)
0.5 x Vdd + 1.1
–
–
–
V
OHIGHOB
OLOWOB
SOB
–
0.5 x Vdd - 1.3
V
I
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
–
–
1.1
2.6
5.1
8.8
mA
mA
PSRR
Supply Voltage Rejection Ratio
–
64
–
dB
OB
Document Number: 3-12029 Rev. *E
Page 18 of 31
CY8C24223A, CY8C24423A
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
A
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling
of the digital signal may appear on the AGND.
Table 16. DC Analog Reference Specifications
Symbol
Description
Bandgap Voltage Reference
Min
Typ
Max
Units
BG
–
1.25
1.30
1.35
V
a
AGND = Vdd/2
CT Block Power = High
Vdd/2 - 0.02
2.4
Vdd/2
2.6
Vdd/2 + 0.02
2.8
V
V
V
V
V
V
a
–
–
–
–
–
AGND = 2 x BandGap
CT Block Power = High
a
AGND = P2[4] (P2[4] = Vdd/2)
CT Block Power = High
P2[4] - 0.02
1.23
P2[4]
1.30
2.08
0.000
P2[4] + 0.02
1.37
a
AGND = BandGap
CT Block Power = High
a
AGND = 1.6 x BandGap
CT Block Power = High
1.98
2.14
AGND Column to Column Variation (AGND =
a
Vdd/2)
-0.035
0.035
CT Block Power = High
–
–
–
–
–
–
–
–
–
–
–
RefHi = Vdd/2 + BandGap
Ref Control Power = High
Vdd/2 + 1.15
3.65
Vdd/2 +1.30
3.9
Vdd/2 +1.45
4.15
V
V
V
V
V
V
V
V
V
V
V
RefHi = 3 x BandGap
Ref Control Power = High
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
Ref Control Power = High
P2[6] + 2.4
P2[4] + 1.24
P2[4] + P2[6] - 0.1
3.9
P2[6] + 2.6
P2[4] +1.30
P2[6] + 2.8
P2[4] + 1.36
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
Ref Control Power = High
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
Ref Control Power = High
P2[4] + P2[6] P2[4] + P2[6] + 0.1
RefHi = 3.2 x BandGap
Ref Control Power = High
4.16
Vdd/2 - 1.3
1.3
4.42
1.15
RefLo = Vdd/2 – BandGap
Ref Control Power = High
Vdd/2 - 1.45
1.15
RefLo = BandGap
Ref Control Power = High
1.45
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
Ref Control Power = High
2.4 - P2[6]
P2[4] - 1.45
P2[4] - P2[6] - 0.1
2.6 - P2[6]
1.3
2.8 - P2[6]
P2[4] - 1.15
P2[4] - P2[6] + 0.1
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
Ref Control Power = High
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
Ref Control Power = High
P2[4] - P2[6]
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.05V.
Document Number: 3-12029 Rev. *E
Page 19 of 31
CY8C24223A, CY8C24423A
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
A
Table 17. DC Analog PSoC Block Specifications
Symbol
Description
Resistor Unit Value (Continuous Time)
Capacitor Unit Value (Switch Cap)
Min
–
Typ
12.24
80
Max
–
Units
kΩ
R
C
CT
SC
–
–
fF
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
A
Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Programmable
System-on-Chip Technical Reference Manual for more information on the VLT_CR register.
Table 18. DC POR and LVD Specifications
Symbol
Description
Min
Typ
4.55
4.55
0
Max
Units
V
Vdd Value for PPOR Trip (positive ramp)
PORLEV[1:0] = 10b
V
V
V
4.70
PPOR2R
PPOR2
PH2
Vdd Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 10b
V
PPOR Hysteresis
PORLEV[1:0] = 10b
–
–
mV
Vdd Value for LVD Trip
VM[2:0] = 110b
VM[2:0] = 111b
V
V
4.62
4.710
4.73
4.814
4.83
4.950
V
V
LVD6
LVD7
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
A
Table 19. DC Programming Specifications
Symbol
Vdd
Description
Min
4.75
–
Typ
–
Max
–
Units
V
Notes
Supply Voltage for Flash Write Operations
Supply Current During Programming or Verify
Input Low Voltage During Programming or Verify
Input High Voltage During Programming or Verify
IWRITE
DDP
I
10
–
25
0.8
–
mA
V
V
V
–
ILP
IHP
2.2
–
–
V
I
Input Current when Applying Vilp to P1[0] or P1[1] During
Programming or Verify
–
0.2
mA Driving internal
pull down resistor.
ILP
I
Input Current when Applying Vihp to P1[0] or P1[1] During
Programming or Verify
–
–
1.5
mA Driving internal
pull down resistor.
IHP
V
V
Output Low Voltage During Programming or Verify
Output High Voltage During Programming or Verify
–
–
–
–
Vss + 0.75
V
V
OLV
3.5
100
Vdd
–
OHV
a
Flash
Flash
Flash
Flash Endurance (per block)
–
Erase/write
cycles per block.
ENPB
ENT
DR
a,b
Flash Endurance (total)
6,400
–
–
–
Erase/write
cycles.
c
Flash Data Retention
15
–
–
Years
a. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writ-
ing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
b. A maximum of 64 x 100 block endurance cycles is allowed.
c. Flash data retention based on the use condition of ≤ 7000 hours at T ≤ 125°C and the remaining time at T ≤ 65°C.
A
A
Document Number: 3-12029 Rev. *E
Page 20 of 31
CY8C24223A, CY8C24423A
AC Electrical Characteristics
AC Chip-Level Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
A
Table 20. AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
F
Internal Main Oscillator Frequency for 24 MHz 22.95
24
24.96
MHz Trimmed. Using factory trim
values.
IMO24
F
F
F
F
F
CPU Frequency (5V Nominal)
Digital PSoC Block Frequency
Digital PSoC Block Frequency
Internal Low Speed Oscillator Frequency
External Crystal Oscillator
0.09
–
12
–
12.48
–
MHz
CPU1
48M
MHz Not allowed.
a
0
24
24.96
64
MHz
kHz
24M
15
–
32
32K1
32K2
32.768
–
kHz Accuracy is capacitor and
crystal dependent. 50% duty
cycle.
F
PLL Frequency
–
23.986
–
MHz A multiple (x732) of crystal
frequency.
PLL
Jitter24M2
24 MHz Period Jitter (PLL)
–
0.5
0.5
–
–
–
800
10
ps
ms
ms
ms
ms
ns
T
T
T
T
PLL Lock Time
PLLSLEW
PLLSLEWSLOW
OS
PLL Lock Time for Low Gain Setting
External Crystal Oscillator Startup to 1%
External Crystal Oscillator Startup to 100 ppm
32 kHz Period Jitter
–
50
1700
2800
100
–
2620
3800
–
OSACC
Jitter32k
–
T
External Reset Pulse Width
24 MHz Duty Cycle
10
40
–
–
60
–
μs
%
XRST
DC24M
50
Step24M
24 MHz Trim Step Size
50
kHz
ps
Jitter24M1P
Jitter24M1R
24 MHz Period Jitter (IMO) Peak-to-Peak
–
300
–
24 MHz Period Jitter (IMO) Root Mean
Squared
–
600
12.48
–
ps
F
T
Maximum frequency of signal on row input or
row output.
–
0
–
–
MHz
MAX
Supply Ramp Time
μs
RAMP
a. See the individual user module data sheets for information on maximum frequencies for user modules.
Document Number: 3-12029 Rev. *E
Page 21 of 31
CY8C24223A, CY8C24423A
Figure 8. PLL Lock Timing Diagram
PLL
Enable
T
24 MHz
PLLSLEW
FPLL
PLL
Gain
0
Figure 9. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
T
24 MHz
PLLSLEWLOW
FPLL
PLL
Gain
1
Figure 10. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
T
OS
F32K2
Figure 11. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F24M
Figure 12. 32 kHz Period Jitter (ECO) Timing Diagram
Jitter32k
F32K2
Document Number: 3-12029 Rev. *E
Page 22 of 31
CY8C24223A, CY8C24423A
AC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
A
Table 21. AC GPIO Specifications
Symbol
Description
Min
0
Typ
–
Max
12.48
22
Units
Notes
F
GPIO Operating Frequency
MHz Normal Strong Mode
GPIO
TRiseF
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
2
–
ns
ns
ns
ns
Vdd = 4.75 to 5.25V, 10% - 90%
TFallF
TRiseS
TFallS
2
–
22
Vdd = 4.75 to 5.25V, 10% - 90%
Vdd = 4.75 to 5.25V, 10% - 90%
Vdd = 4.75 to 5.25V, 10% - 90%
9
27
22
–
9
–
Figure 13. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
A
Note Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Table 22. AC Operational Amplifier Specifications
Symbol
SR
Description
Min
Typ
Max
Units
Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain)
Power = Low
ROA
0.15
0.15
0.15
1.7
1.7
6.5
–
V/μs
V/μs
V/μs
V/μs
V/μs
V/μs
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High
–
–
Power = High, Opamp Bias = High
SR
Falling Slew Rate (20% to 80%) (10 pF load, Unity Gain)
Power = Low
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High
Power = High, Opamp Bias = High
FOA
0.01
0.01
0.01
0.5
0.5
4.0
–
V/μs
V/μs
V/μs
V/μs
V/μs
V/μs
–
–
BW
Gain Bandwidth Product
Power = Low
Power = Low, Opamp Bias = High
Power = Medium
Power = Medium, Opamp Bias = High
Power = High
OA
0.75
0.75
0.75
3.1
3.1
5.4
–
MHz
MHz
MHz
MHz
MHz
MHz
–
–
Power = High, Opamp Bias = High
Document Number: 3-12029 Rev. *E
Page 23 of 31
CY8C24223A, CY8C24423A
AC Low Power Comparator Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
A
Table 23. AC Low Power Comparator Specifications
Symbol
Description
LPC response time
Min
Typ
Max
Units
Notes
T
–
–
50
μs
≥ 50 mV overdrive comparator
reference set within V
RLPC
.
REFLPC
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 14. Typical AGND Noise with P2[4] Bypass
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 15. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
0.01
0.1
1
10
100
Freq (kHz)
Document Number: 3-12029 Rev. *E
Page 24 of 31
CY8C24223A, CY8C24423A
AC Digital Block Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
A
Table 24. AC Digital Block Specifications
Function
Description
Min
Typ
Max
24.96
–
Units
MHz
ns
Notes
All Functions Maximum Block Clocking Frequency
a
Timer
Capture Pulse Width
50
–
–
–
–
–
–
Maximum Frequency, No Capture
Maximum Frequency, With Capture
Enable Pulse Width
–
–
24.96
24.96
–
MHz 4.75V < Vdd < 5.25V
MHz
a
Counter
Dead Band
50
ns
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
Kill Pulse Width:
–
–
24.96
24.96
MHz 4.75V < Vdd < 5.25V
MHz
Asynchronous Restart Mode
Synchronous Restart Mode
Disable Mode
20
–
–
–
–
–
–
–
ns
a
50
ns
a
50
–
ns
Maximum Frequency
–
–
24.96
24.96
MHz 4.75V < Vdd < 5.25V
MHz 4.75V < Vdd < 5.25V
CRCPRS
(PRS Mode)
Maximum Input Clock Frequency
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
Maximum Input Clock Frequency
–
–
–
–
–
24.96
4.1
MHz
SPIM
MHz Maximumdatarateat 4.1 MHz
due to 2 x over clocking.
SPIS
Maximum Input Clock Frequency
–
–
–
2.05
–
MHz
ns
a
Width of SS_ Negated Between Transmissions
Maximum Input Clock Frequency
50
Transmitter
Receiver
–
8.2
MHz Maximum data rate at 3.08
MHz due to 8 x over clocking.
Maximum Input Clock Frequency
–
16
24.96
MHz Maximum data rate at 3.08
MHz due to 8 x over clocking.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 3-12029 Rev. *E
Page 25 of 31
CY8C24223A, CY8C24423A
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
A
Table 25. AC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
T
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
ROB
SOB
–
–
–
–
3
3
μs
μs
T
Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
–
–
–
–
3
3
μs
μs
SR
SR
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High
ROB
0.6
0.6
–
–
–
–
V/μs
V/μs
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High
FOB
0.6
0.6
–
–
–
–
V/μs
V/μs
BW
BW
Small Signal Bandwidth, 20mV , 3dB BW, 100 pF Load
Power = Low
Power = High
OB
OB
pp
0.8
0.8
–
–
–
–
MHz
MHz
Large Signal Bandwidth, 1V , 3dB BW, 100 pF Load
pp
Power = Low
Power = High
300
300
–
–
–
–
kHz
kHz
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
A
Table 26. AC External Clock Specifications
Symbol
Description
Min
0
Typ
–
Max
Units
MHz
ns
F
Frequency
24.24
OSCEXT
–
–
–
High Period
20.6
20.6
150
–
–
–
–
Low Period
–
ns
Power Up IMO to Switch
–
μs
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
A
Table 27. AC Programming Specifications
Symbol
Description
Min
1
Typ
–
Max
20
20
–
Units
ns
T
Rise Time of SCLK
Fall Time of SCLK
RSCLK
FSCLK
SSCLK
HSCLK
SCLK
T
T
T
F
T
T
T
1
–
ns
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
–
8
MHz
ms
ms
ns
Flash Erase Time (Block)
–
15
30
–
–
ERASEB
WRITE
DSCLK
Flash Block Write Time
–
–
Data Out Delay from Falling Edge of SCLK
–
45
Document Number: 3-12029 Rev. *E
Page 26 of 31
CY8C24223A, CY8C24423A
2
AC I C Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
A
2
Table 28. AC Characteristics of the I C SDA and SCL Pins
Standard Mode
Fast Mode
Min Max
Symbol
Description
Units
Min
0
Max
100
–
F
T
SCL Clock Frequency
0
400
–
kHz
SCLI2C
Hold Time (repeated) START Condition. After this period, the first
clock pulse is generated.
4.0
0.6
μs
HDSTAI2C
T
T
T
T
T
T
T
T
LOW Period of the SCL Clock
4.7
4.0
4.7
0
–
–
–
–
–
–
–
–
1.3
0.6
0.6
0
–
–
μs
μs
μs
μs
ns
μs
μs
ns
LOWI2C
HIGH Period of the SCL Clock
HIGHI2C
SUSTAI2C
HDDATI2C
SUDATI2C
SUSTOI2C
BUFI2C
Setup Time for a Repeated START Condition
Data Hold Time
–
–
a
Data Setup Time
250
4.0
4.7
–
100
0.6
1.3
0
–
Setup Time for STOP Condition
–
Bus Free Time Between a STOP and START Condition
Pulse Width of spikes are suppressed by the input filter.
–
50
SPI2C
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t
≥ 250 ns must then be met. This is automatically the
SU;DAT
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line t
+ t
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
rmax
SU;DAT
Figure 16. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TSPI2C
T
LOWI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
SCL
TSUSTOI2C
TSUSTAI2C
THDDATI2C
THDSTAI2C
THIGHI2C
S
Sr
P
S
Document Number: 3-12029 Rev. *E
Page 27 of 31
CY8C24223A, CY8C24423A
Packaging Information
This section illustrates the packaging specifications for the CY8C24x23A automotive PSoC device, along with the thermal impedances
for each package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
Figure 17. 20-Pin (210-Mil) SSOP
51-85077 *C
Document Number: 3-12029 Rev. *E
Page 28 of 31
CY8C24223A, CY8C24423A
Figure 18. 28-Pin (210-Mil) SSOP
51-85079 *C
Thermal Impedances
Capacitance on Crystal Pins
Table 30. Typical Package Capacitance on Crystal Pins
Package Package Capacitance
2.6 pF
2.8 pF
Table 29. Thermal Impedances per Package
Package
Typical θ
*
JA
o
20 SSOP
28 SSOP
117 C/W
20 SSOP
28 SSOP
o
101 C/W
* T = T + POWER x θJA
J
A
Solder Reflow Peak Temperature
The following table lists the minimum solder reflow peak temperature to achieve good solderability.
Table 31. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature* Maximum Peak Temperature
o
o
20 SSOP
28 SSOP
240 C
260 C
o
o
240 C
260 C
o
*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 C with
o
Sn-Pb or 245 ± 5 C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
Document Number: 3-12029 Rev. *E
Page 29 of 31
CY8C24223A, CY8C24423A
Ordering Information
The following table lists the CY8C24x23A automotive PSoC device group’s key package features and ordering codes.
Table 32. CY8C24x23A Automotive PSoC Key Features and Ordering Information
20 Pin (210 Mil) SSOP
CY8C24223A-12PVXE
CY8C24223A-12PVXET
CY8C24423A-12PVXE
CY8C24423A-12PVXET
4K
4K
4K
4K
256
256
256
256
No
No
No
No
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
4
4
4
4
6
6
6
6
16
16
24
24
8
8
2
2
2
2
Yes
Yes
Yes
Yes
20 Pin (210 Mil) SSOP
(Tape and Reel)
28 Pin (210 Mil) SSOP
10
10
28 Pin (210 Mil) SSOP
(Tape and Reel)
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Ordering Code Definitions
CY 8 C 24 xxx-12xx
Package Type:
Thermal Rating:
C = Commercial
I = Industrial
PX = PDIP Pb-Free
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
LFX = QFN Pb-Free
LKX = QFN Pb-Free
AX = TQFP Pb-Free
E = Extended
Speed: 12 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 3-12029 Rev. *E
Page 30 of 31
CY8C24223A, CY8C24423A
Document History Page
®
Document Title: CY8C24223A, CY8C24423A PSoC Programmable System-on-Chip™
Document Number: 38-12029
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
**
238268
271471
SFV
See ECN
See ECN
First release of CY8C24x23A Automotive Preliminary Data Sheet.
*A
HMT
Update per SFV memo. Input MWR changes, including removing SMP. Change
to Final.
*B
*C
286089
512475
HMT
HMT
See ECN
See ECN
Update characterization data. Fine tune pinouts. Add Reflow Peak Temp. table.
Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add ISSP note
to pinout tables. Update typical and recommended Storage Temperature per
extended temp. specs. Update CY branding and QFN convention. Update
copyright and trademarks.
*D
*E
2101387 AESA
See ECN
Post to www.cypress.com
2619935 OGNE/AESA
12/11/2008 Changed title to “CY8C24223A, CY8C24423A PSoC® Programmable
System-on-Chip™”
19.
Updated data sheet template.
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© Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 3-12029 Rev. *E
Revised December 11, 2008
Page 31 of 31
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names
mentioned in this document may be the trademarks of their respective holders.
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