CY7C68023/CY7C68024
step on each falling edge of the Read Enable pulse. A 10k pull-
up is an option For RE1-0#.
3.3
Additional Pin Descriptions
3.3.1
DPLUS, DMINUS
3.3.7
CLE
DPLUS and DMINUS are the USB signaling pins, and they
should be tied to the D+ and D– pins of the USB connector.
Because they operate at high frequencies, the USB signals
require special consideration when designing the layout of the
PCB. General guidelines are given at the end of this
document.
The Command Latch Enable output pin is used to indicate that
the data on the I/O bus is a command. The data is latched into
the NAND Flash control register on the rising edge of WE#
when CLE is HIGH.
3.3.8
ALE
3.3.2
XTALIN, XTALOUT
The Address Latch Enable output pin is used to indicate that
the data on the I/O bus is an address. The data is latched into
the NAND Flash address register on the rising edge of WE#
when ALE is HIGH.
24-MHz Xtal
3.3.9
LED1#
12 pF
12 pF
The Data Activity LED output pin is used to indicate data
transfer activity. LED1# is asserted LOW at the beginning of a
data transfer, and set to a high-Z state when the transfer is
complete. If this functionality is not utilized, leave LED1#
floating.
12-pF capacitor
values assume a
trace capacitance
of 3 pF per side on a
four-layer FR4 PCB
3.3.10 LED2#
The Chip Active LED output pin is used to indicate proper
device operation. LED2# is asserted LOW when the NX2LP is
powered and initialized. It is placed in a high-Z state under all
other conditions. If this functionality is not utilized, leave
LED2# floating.
XTALIN
XTALOUT
Figure 3-2. XTALIN, XTALOUT Diagram
3.3.11 WP_NF#
The Write-protect NAND Flash output pin is used to control the
write-protect pins on NAND Flash devices. This pin should be
tied to the Write Protect pins of the NAND Flash devices. If
WP_SW# is asserted LOW during a data transfer, or if internal
operations are still pending, the NX2LP will wait until the
operation is complete before asserting WP_NF# to ensure that
there is no data loss or risk of OS error.
The NX2LP requires a 24-MHz (±100 ppm) signal to derive
internal timing. Typically, a 24-MHz (20-pF, 500-µW, parallel-
resonant fundamental mode) crystal is used, but a 24-MHz
square wave from another source can also be used. If a crystal
is used, connect its pins to XTALIN and XTALOUT, and also
through 12-pF capacitors to GND. If an alternate clock source
is used, apply it to XTALIN and leave XTALOUT open.
3.3.12 WP_SW#
3.3.3
Data[7-0]
The Write-protect Switch input pin is used to select whether or
not NAND Flash write-protection is enabled by the NX2LP.
When the pin is asserted LOW, the NX2LP will report to the
host that the NAND Flash is write-protected, the WP_NF# will
be driven LOW, and any attempts to write to the configuration
data memory area will be blocked by the NX2LP. If this pin is
asserted LOW during a data transfer, or if internal operations
are still pending, the NX2LP will wait until the operation is
complete before asserting WP_NF# to ensure that there is no
data loss or risk of OS error.
The Data[7-0] I/O pins provide an 8-bit interface to a NAND
Flash device. These pins are used to transfer address,
command, and read/write data between the NX2LP and NAND
Flash.
3.3.4
R_B[2-1]#
The Ready/Busy input pins are used to determine the state of
the currently selected NAND Flash device. These pins must
be pulled HIGH through a 2k-4k resistor. These pins are pulled
LOW by the NAND Flash when it is busy.
3.3.13 CE[7-0]#
3.3.5
WE#
The Chip Enable output pins are used to select the NAND
Flash that the NX2LP will interface. Unused Chip Enable pins
should be left floating.
The Write Enable output pin is used by the NAND Flash to
latch commands, address, and data during the rising edge of
the pulse.
3.3.14 RESET#
3.3.6
RE[1-0]#
Asserting RESET# for 10 ms will reset the NX2LP. A reset
and/or watchdog chip is recommended to ensure that startup
and brownout conditions are properly handled.
The Read Enable output pins are used to control the data flow
from the NAND Flash devices. The device presents valid data
and will increment its internal column address counter by one
Document #: 38-08055 Rev. *B
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