CY7C1380C
CY7C1382C
18-Mb (512K x 36/1M x 18) Pipelined SRAM
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 225, 200,166 and
133MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.8 ns (for 225-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 166-MHz device)
— 4.2 ns (for 133-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
The CY7C1380C/CY7C1382C SRAM integrates 524,288 x 36
and 1,048,576 x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (
), depth-expansion Chip
CE
1
[2]
Enables (CE and
), Burst Control inputs (
,
,
CE
2
ADSC ADSP
3
), Write Enables (
ADV
, and
), and Global Write
and
BW
BWE
X
(
). Asynchronous inputs include the Output Enable (
GW
)
OE
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor ( ) or
ADSP
) are active. Subsequent
Address Strobe Controller (
ADSC
burst addresses can be internally generated as controlled by
the Advance pin ( ).
®
ADV
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
• Asynchronous output enable
controlled by the byte write control inputs.
when active
GW
• Single Cycle Chip Deselect
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA
and 165-Ball fBGA packages
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
causes all bytes to be written.
LOW
The CY7C1380C/CY7C1382C operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
250 MHz
225 MHz
2.8
200 MHz
3.0
167 MHz
3.4
133 MHz
4.2
Unit
ns
Maximum Access Time
2.6
350
70
Maximum Operating Current
325
300
275
245
mA
mA
Maximum CMOS Standby Current
Shaded areas contain advance information.
70
70
70
70
Please contact your local Cypress sales representative for availability of these parts.
Notes:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE , CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.
3
2
Cypress Semiconductor Corporation
Document #: 38-05237 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised February 26, 2004
CY7C1380C
CY7C1382C
Pin Configurations
100-pin TQFP Pinout
DQPC
1
DQPB
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQB
NC
2
DQc
VDDQ
VSSQ
DQC
DQB
NC
3
4
5
3
VDDQ
VDDQ
4
VSSQ
VSSQ
5
DQB
NC
6
6
DQC
7
DQB
NC
7
DQC
8
DQB
DQB
8
9
DQC
9
DQB
DQB
VSSQ
10
VSSQ
VSSQ
10
VDDQ
11
VDDQ
VDDQ
11
DQC
12
DQB
DQB
12
13
14
15
DQC
13
DQB
DQB
NC
14
VSS
NC
NC
VDD
VDD
15
CY7C1382C
(1M x 18)
CY7C1380C
(512K X 36)
NC
16
VDD
NC
16
VDD
ZZ
VSS
17
ZZ
DQA
VSS
DQB
17
18
19
DQD
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
DQA
DQB
VDDQ
20
VDDQ
VDDQ
20
VSSQ
21
VSSQ
VSSQ
21
DQD
22
DQA
DQB
22
23
24
25
DQD
23
DQA
DQA
DQB
DQPB
DQD
24
DQD
25
DQA
NC
NC
VSSQ
26
VSSQ
VSSQ
26
VSSQ
VDDQ
NC
NC
NC
VDDQ
27
VDDQ
VDDQ
27
DQD
28
DQA
NC
28
DQD
29
DQA
NC
29
DQPD
30
DQPA
NC
30
Document #: 38-05237 Rev. *D
Page 3 of 36
CY7C1380C
CY7C1382C
Pin Configurations (continued)
119-ball BGA (1 Chip Enable with JTAG)
CY7C1380C (512K x 36)
1
2
3
4
5
6
7
V
A
A
A
A
V
DDQ
A
ADSP
ADSC
DDQ
B
C
NC
NC
A
A
A
A
A
A
A
A
NC
NC
V
DD
DQ
DQP
V
NC
CE
V
DQP
DQ
B
D
E
F
C
C
SS
SS
SS
SS
SS
SS
B
DQ
DQ
DQ
V
V
V
V
DQ
DQ
DQ
B
C
C
1
B
V
V
DDQ
OE
ADV
GW
DDQ
C
B
DQ
DQ
DQ
V
BW
V
BW
V
DQ
DQ
V
DQ
G
H
J
C
C
C
C
B
B
B
B
DQ
DQ
C
SS
SS
B
V
NC
V
NC
V
DDQ
DDQ
DD
DD
DD
DQ
DQ
V
CLK
NC
V
DQ
DQ
K
D
D
D
SS
SS
A
A
A
L
M
N
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
BW
BW
D
D
D
A
A
A
D
A
V
V
V
V
V
V
DDQ
BWE
A1
DDQ
SS
SS
SS
SS
DQ
DQ
D
A
P
R
DQ
DQP
A
V
A0
V
DQP
A
DQ
D
D
SS
SS
A
NC
NC
MODE
V
NC
A
NC
DD
T
NC / 72M
TMS
A
A
A
NC / 36M
NC
ZZ
U
V
TDI
TCK
TDO
V
DDQ
DDQ
CY7C1382C (512K x 18)
2
A
1
3
A
A
A
4
5
A
A
A
6
A
A
A
7
A
B
C
D
E
F
V
V
DDQ
ADSP
ADSC
DDQ
NC
A
NC
NC
A
V
NC
NC
DD
DQ
NC
V
NC
CE
V
DQP
A
B
SS
SS
SS
SS
SS
SS
SS
SS
NC
DQ
V
V
V
V
V
V
NC
DQ
DQ
B
A
1
V
NC
V
DDQ
OE
ADV
GW
DDQ
A
G
H
J
NC
DQ
NC
DQ
DQ
A
BW
V
B
B
DQ
NC
NC
V
DDQ
B
SS
A
V
V
NC
V
NC
V
DDQ
DD
DD
DD
NC
DQ
V
CLK
NC
V
NC
DQ
DQ
K
L
B
SS
SS
A
DQ
NC
DQ
V
NC
BW
B
SS
A
A
V
V
V
V
V
NC
DQ
V
DDQ
M
N
P
BWE
A1
DDQ
B
SS
SS
SS
SS
DQ
NC
V
NC
DQ
B
SS
A
NC
DQP
V
A0
NC
B
SS
A
R
T
NC
A
A
MODE
A
V
NC
A
A
A
NC
ZZ
DD
NC / 72M
NC / 36M
TCK
U
V
TMS
TDI
TDO
NC
V
DDQ
DDQ
Document #: 38-05237 Rev. *D
Page 4 of 36
CY7C1380C
CY7C1382C
Pin Configurations (continued)
165-ball fBGA
CY7C1380C (512K x 36)
1
NC / 288M
NC
2
3
4
5
6
7
8
9
10
A
11
NC
A
B
C
D
CE1
BWC
BWD
VSS
VDD
BWB
BWA
VSS
VSS
CE
ADSC
A
BWE
GW
VSS
ADV
ADSP
VDDQ
VDDQ
3
A
CE2
VDDQ
VDDQ
CLK
VSS
VSS
A
NC / 144M
DQPB
DQB
OE
VSS
VDD
DQPC
DQC
NC
NC
DQC
VSS
DQB
DQC
DQC
DQC
DQC
VSS
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
E
F
DQC
DQC
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQB
DQB
ZZ
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
NC / 72M
TDI
A1
TDO
A0
MODE NC / 36M
A
A
TMS
TCK
A
A
A
A
R
CY7C1382C (1M x 18)
1
NC / 288M
NC
2
A
3
4
5
NC
6
7
8
9
10
A
11
A
A
BWB
NC
CE
CE1
CE2
BWE
GW
VSS
ADSC
OE
ADV
ADSP
VDDQ
VDDQ
3
A
BWA
VSS
VSS
CLK
VSS
VSS
A
NC / 144M
DQPA
DQA
B
C
D
NC
NC
VDDQ
VDDQ
VSS
VDD
VSS
NC
NC
NC
DQB
VSS
VDD
NC
DQB
DQB
DQB
VSS
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
E
F
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQA
DQA
ZZ
NC
G
H
J
NC
NC
DQB
DQB
DQB
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
NC / 72M
TDI
A1
TDO
MODE NC / 36M
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05237 Rev. *D
Page 5 of 36
CY7C1380C
CY7C1382C
CY7C1380C–Pin Definitions
Name
A , A , A
TQFP
BGA
fBGA
I/O
Description
Address Inputs used to select one of the
37,36,32,
33,34,35,
42,43,44,45,
46,47,48,
49,50,81,
82,99,100
P4,N4,
A2,B2,
C2,R2,
R6,P6,A2,
A10,B2,
B10,N6,P3,P4,
P8,P9,P10,
Input-
0
1
Synchronous 256Kaddresslocations. Sampledattherising
edge of the CLK if
or
is active
are sampled
ADSP ADSC
[2]
A3,B3,C3,
T3,T4,A5,B5, P11,R3,R4,R8,
C5,
T5,A6,B6,C6,
R6
LOW, and CE , CE , and CE
1
2
3
active. A1: A0 are fed to the two-bit counter.
.
R9,R10,R11
93,94,95,
96
L5,G5,
G3,L3
B5,A5,A4,
B4
Input-
Synchronous
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
BW BW
A,
B
BW BW
C,
D
H4
B7
Input-
Global Write Enable Input, active LOW.
88
GW
Synchronous When asserted LOW on the rising edge of CLK,
a global write is conducted (ALL bytes are
written, regardless of the values on BW and
X
BWE).
87
89
M4
K4
A7
B6
Input-
Byte Write Enable Input, active LOW. Sam-
BWE
CLK
Synchronous pled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW,
during a burst operation.
98
E4
A3
Input-
Chip Enable 1 Input, active LOW. Sampled on
CE
1
Synchronous the rising edge of CLK. Used in conjunction with
CE and CE to select/deselect the device.
2
3
ADSP is ignored if CE is HIGH.
1
[2]
CE
CE
97
92
-
-
B3
A6
Input-
Chip Enable 2 Input, active HIGH. Sampled
2
3
Synchronous on the rising edge of CLK. Used in conjunction
with CE and CE to select/deselect the device.
1
3
Input-
Synchronous the rising edge of CLK. Used in conjunction with
CE and CE to select/deselect the device.Not
Chip Enable 3 Input, active LOW. Sampled on
[2]
1
2
available for AJ package version.
Not
connected for BGA. Where referenced, CE is
3
assumed active throughout this document for
BGA.
86
83
F4
B8
A9
Input-
Output Enable, asynchronous input, active
OE
Asynchronous LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during
the first clock of a read cycle when emerging
from a deselected state.
G4
Input-
Advance Input signal, sampled on the rising
ADV
Synchronous edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst
cycle.
Document #: 38-05237 Rev. *D
Page 6 of 36
CY7C1380C
CY7C1382C
CY7C1380C–Pin Definitions (continued)
Name
TQFP
BGA
fBGA
I/O
Description
Address Strobe from Processor, sampled
84
A4
B9
Input-
ADSP
Synchronous on therisingedgeof CLK, activeLOW. When
asserted LOW, addresses presented to the
device are captured in the address registers.
A1: A0 are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when
CE is deasserted HIGH.
1
B4
T7
A8
Input-
AddressStrobefromController, sampledon
85
64
ADSC
Synchronous the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the
device are captured in the address registers.
A1: A0 are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only
ADSP is recognized.
ZZ
H11
Input-
ZZ “sleep” Input, active HIGH. When
Asynchronous asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
52,53,56,
57,58,59,
62,63,68,
69,72,73,
74,75,78,
79,2,3,6,7,8,9,
12,13,18,19,22
,
K6,L6,
M6,N6,
K7,L7,
N7,P7,
E6,F6,
G6,H6,
D7,E7,
G7,H7,
D1,E1,
G1,H1,
E2,F2,
G2,H2,
K1,L1,
N1,P1,
K2,L2,
M2,N2,
P6,D6,
D2,P2
M11,L11,
K11,J11,
I/O-
Bidirectional Data I/O lines. As inputs, they
DQs, DQPs
Synchronous feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs,
they deliver the data contained in the memory
location specified by the addresses presented
J10,K10,
L10,M10,
D10,E10,
F10,G10,
D11,E11,
F11,G11,
D1,E1,F1,
G1,D2,E2,F2,
G2,J1,
during the previous
clock rise of the read cycle.
The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as
23,24,25,
28,29,51,
80,1,30
outputs. When HIGH, DQs and DQP are
X
placed in a tri-state condition.
K1,L1,M1,
J2,K2,L2,
M2,N11,
C11,C1,N1
V
V
15,41,65,
91
J2,C4,J4,R4, D4,D8,E4,E8, Power Supply Power supply inputs to the core of the de-
DD
J6
F4,F8,
G4,G8,H4,H8,
J4,J8,
vice.
K4,K8,L4,
L8,M4,M8
17,40,67,
90
D3,E3,
F3,H3,
K3,M3,
N3,P3,
D5,E5,
F5,H5,
K5,M5,
N5,P5
C4,C5,C6,C7,
C8,D5,D6,D7,
E5,E6,E7,F5,
F6,F7,G5,G6,
G7,H2,H5,H6,
H7,J5,J6,J7,
K5,K6,K7,
Ground
Ground for the core of the device.
SS
L5,L6,L7,
M5,M6,M7,N4,
N8
Document #: 38-05237 Rev. *D
Page 7 of 36
CY7C1380C
CY7C1382C
CY7C1380C–Pin Definitions (continued)
Name
TQFP
BGA
fBGA
I/O
Description
V
5,10,21,26,55,
60,71,
-
-
I/O Ground Ground for the I/O circuitry.
SSQ
76
V
4,11,20,27,54, A1,F1,J1,M1, C3,C9,D3,D9,
I/O Power
Supply
Power supply for the I/O circuitry.
DDQ
61,70,
77
U1,
A7,F7,J7,M7,
U7
E3,E9,F3,F9,G
3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,N3,
N9
MODE
31
R3
R1
Input-
Static
Selects Burst Order. When tied to GND
selectslinearburstsequence. WhentiedtoV
or left floating selects interleaved burst
DD
sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an
internal pull-up.
TDO
TDI
-
-
-
-
U5
U3
U2
P7
P5
R5
JTAG serial Serial data-out to the JTAG circuit. Delivers
output data on the negative edge of TCK. If the JTAG
Synchronous feature is not being utilized, this pin should be
disconnected. This pin is not available onTQFP
packages.
JTAG serial Serial data-In to the JTAG circuit. Sampled
input
on the rising edge of TCK. If the JTAG feature
Synchronous is not being utilized, this pin can be discon-
nected or connected to V . This pin is not
DD
available on TQFP packages.
TMS
JTAG serial Serial data-In to the JTAG circuit. Sampled
input
on the rising edge of TCK. If the JTAG feature
Synchronous is not being utilized, this pin can be discon-
nected or connected to V . This pin is not
DD
available on TQFP packages.
TCK
NC
U4
R7
JTAG-Clock Clock input to the JTAG circuitry. If the JTAG
feature is not being utilized, this pin must be
connected to V . This pin is not available on
SS
TQFP packages.
14,16,66,
39,38
B1,C1,
A11,B1,C2,C1
-
No Connects. Not internally connected to the
die
R1,T1,T2,J3, 0,H1,H3,H9,
D4, H10,
L4,J5,R5,6T, N2,N5,N7,N10
6U,
B7,C7,
R7
,P1,A1,B11,P2
,R2,N6
Document #: 38-05237 Rev. *D
Page 8 of 36
CY7C1380C
CY7C1382C
CY7C1382C:Pin Definitions
Name
A , A , A
TQFP
BGA
fBGA
I/O
Description
Address Inputs used to select one of the 512K
37,36,32,
33,34,35,
42,43,44,
45,46,47,
48,49,50,
80,81,82,
99,100
P4,N4,
A2,B2,
C2,R2,
T2,A3,
B3,C3,
T3,A5,
B5,C5,
T5,A6,
B6,C6,
R6,T6
R6,P6,A2,
A10,A11,
B2,B10,P3,P4,
N6,P8,P9,
P10,P11,
R3,R4,R8,R9,
R10,
Input-
0
1
Synchronous address locations. Sampled at the rising edge of
the CLK if or is active LOW, and CE ,
ADSP ADSC
CE , and CE are sampled active. A1: A0 are fed
1
2
3
to the two-bit counter.
.
R11
93,94
88
G3,L5
B5,A4
B7
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified
BW BW
A,
B
with BWE to conduct byte writes to the SRAM.
.
Sampled on the rising edge of CLK
H4
Input-
Global Write Enable Input, active LOW. When
GW
Synchronous asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written,
regardless of the values on BW and BWE).
X
87
89
M4
K4
A7
B6
Input-
Byte Write Enable Input, active LOW. Sampled
BWE
CLK
Synchronous on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a
burst operation.
98
E4
A3
Input-
Chip Enable 1 Input, active LOW. Sampled on the
CE
1
Synchronous rising edge of CLK. Used in conjunction with CE
2
and CE to select/deselect the device. ADSP is
3
ignored if CE is HIGH.
1
[2]
CE
CE
97
92
-
-
B3
A6
Input-
Synchronous the rising edge of CLK. Used in conjunction with
CE and CE to select/deselect the device.
Chip Enable 2 Input, active HIGH. Sampled on
2
3
1
3
Input-
Chip Enable 3 Input, active LOW. Sampled on the
Synchronous rising edge of CLK. Used in conjunction with CE
1
andCE toselect/deselectthedevice. Notavailable
2
for AJ package version.
Not connected for BGA.
Where referenced, CE is assumed active
3
throughout this document for BGA.
86
83
F4
B8
A9
Input-
Output Enable, asynchronous input, active
OE
Asynchronous LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When
deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock
of a read cycle when emerging from a deselected
state.
G4
Input-
Advance Input signal, sampled on the rising
ADV
Synchronous edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst
cycle.
Document #: 38-05237 Rev. *D
Page 9 of 36
CY7C1380C
CY7C1382C
CY7C1382C:Pin Definitions (continued)
Name
TQFP
BGA
fBGA
I/O
Description
Address Strobe from Processor, sampled on
84
A4
B9
Input-
ADSP
Synchronous the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device
are captured in the address registers. A1: A0 are
also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ASDP is ignored when CE is deasserted HIGH.
1
P4
T7
A8
Input-
AddressStrobefromController, sampledonthe
85
64
ADSC
Synchronous rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are
captured in the address registers. A1: A0 are also
loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ZZ
H11
Input-
ZZ “sleep” Input, active HIGH. When asserted
Asynchronous HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For
normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
58,59,62,
63,68,69,
72,73,8,9,
12,13,18,
19,22,23,
74,24
P7,K7,
G7,E7,
F6,H6,L6,N6,
D1,
J10,K10,
L10,M10,
D11,E11,
I/O-
Bidirectional Data I/O lines. As inputs, they feed
DQs,
DQPs
Synchronous into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by the
F11,G11,J1,K1
,L1,M1,D2,E2,
F2,
H1,L1,
N1,E2,
G2,K2,
M2,D6,
P2
addresses presented during the previous
clock rise
of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQs and
G2,C11,N1
DQP are placed in a tri-state condition.
X
V
V
15,41,65,
91
C4,J2,J4,J6, D4,D8,E4,E8, Power Supply Power supply inputs to the core of the device.
DD
R4
F4,F8,
G4,G8,H4,
H8,J4,J8,
K4,K8,L4,
L8,M4,M8
17,40,67,
90
D3,D5,
H2,C4,C5,C6,
Ground
Ground for the core of the device.
SS
E5,E3,F3,F5, C7,C8,D5,D6,
G5,
H3,H5,
K3,K5,L3,M3,
M5,
D7,E5,E6,E7,
F5,F6,F7,
G5,G6,G7,
H5,H6,H7,J5,J
6,J7,
K5,K6,K7,
L5,L6,L7,
M5,M6,M7,N4,
N8
N3,N5,
P3,P5
V
5,10,21,26,55,
60,71,
-
-
I/O Ground Ground for the I/O circuitry.
SSQ
76
Document #: 38-05237 Rev. *D
Page 10 of 36
CY7C1380C
CY7C1382C
CY7C1382C:Pin Definitions (continued)
Name
TQFP
BGA
fBGA
I/O
Description
V
4,11,20,27,54, A1,A7,F1,F7, C3,C9,D3,D9, I/O Power Sup- Power supply for the I/O circuitry.
DDQ
61,70,
77
J1,J7,M1,M7,
U1,U7
E3,E9,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,N3,
N9
ply
MODE
TDO
TDI
31
R3
U5
U3
R1
P7
P5
Input-
Static
Selects Burst Order. When tied to GND selects
linear burst sequence. When tied to V or left
DD
floating selects interleaved burst sequence. This is
a strap pin and should remain static during device
operation. Mode Pin has an internal pull-up.
-
JTAG serial Serial data-out to the JTAG circuit. Delivers data
output on the negative edge of TCK. If the JTAG feature is
Synchronous not being utilized, this pin should be left uncon-
nected. This pin is not available on TQFP
packages.
-
JTAG serial Serial data-In to the JTAGcircuit. Sampled on the
input
Synchronous utilized, this pin can be left floating or connected to
through a pull up resistor. This pin is not avail-
rising edge of TCK. If the JTAG feature is not being
V
DD
able on TQFP packages.
TMS
TCK
NC
-
-
U2
U4
R5
R7
JTAG serial Serial data-In to the JTAGcircuit. Sampled on the
input
rising edge of TCK. If the JTAG feature is not being
Synchronous utilized, this pin can be disconnected or connected
to V . This pin is not available on TQFP packages.
DD
JTAG-Clock Clock input to the JTAG circuitry. If the JTAG
feature is not being utilized, this pin must be
connected to V . This pin is not available on TQFP
SS
packages.
1,2,3,6,7,
14,16,25,
28,29,30,
38,39,
51,52,53,
56,57,66,
75,78,79,
95,96
B1,B7,
C1,C7,
D2,D4,
D7,E1,
E6,H2,
F2,G1,
G6,H7,
J3,J5,K1,
A5,B1,B4,
C1,C2,C10,D1
,D10,
E1,E10,F1,
F10,G1,
G10,H1,H3,H9
,H10,J2,J11,
K2,
-
No Connects. Not internally connected to the die.
K6,L4,L2,L7, K11,L2,L1,M2,
M6, M11,
N2,L7,P1,P6, N2,N10,N5,N7
R1,
R5,R7,
T1,T4,U6
N11,P1,A1,
B11,
P2,R2
Document #: 38-05237 Rev. *D
Page 11 of 36
CY7C1380C
CY7C1382C
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BW ) and
X
Maximum access delay from the clock rise (t ) is 3.0ns
ADV inputs are ignored during this first cycle.
CO
(200-MHz device).
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
The CY7C1380C supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
then the Write operation is controlled by BWE and BW
X
signals. The CY7C1380C provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write (BW ) input, will selectively write to only the desired
X
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
Because the CY7C1380C is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW ) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
X
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE , CE , CE are all asserted active, and
Three synchronous Chip Selects (CE , CE , CE ) and an
asynchronous Output Enable (OE) provide for easy bank
1
2
3
selection and output tri-state control. ADSP is ignored if CE
1
2
3
1
(4) the appropriate combination of the Write inputs (GW, BWE,
is HIGH.
and BW ) are asserted active to conduct a Write to the desired
X
Single Read Accesses
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into
the address register and the address advancement logic while
being delivered to the memory array. The ADV input is ignored
during this cycle. If a global Write is conducted, the data
presented to the DQs is written into the corresponding address
location in the memory core. If a Byte Write is conducted, only
the selected bytes are written. Bytes not selected during a
Byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations.
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE , CE , CE are all asserted active, and (3) the Write
1
2
3
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE is HIGH. The address presented to the address inputs (A)
1
is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.0 ns (200-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single Read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP or ADSC signals, its output will tri-state immedi-
ately.
Because the CY7C1380C is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1380C provides a two-bit wraparound counter, fed
by A1: A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE , CE , CE are all asserted active. The address
1
2
3
Document #: 38-05237 Rev. *D
Page 12 of 36
CY7C1380C
CY7C1382C
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
the
“sleep” mode. CE , CE , CE , ADSP, and ADSC must
1
2
3
remain inactive for the duration of t
returns LOW
after the ZZ input
ZZREC
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
.
ZZ Mode Electrical Characteristics
Parameter
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > V – 0.2V
Min.
Max.
60mA
Unit
mA
ns
I
t
t
t
t
DDZZ
DD
ZZ > V – 0.2V
2t
ZZS
DD
CYC
ZZ < 0.2V
2t
ns
ZZREC
ZZI
CYC
ZZ Active to snooze current
This parameter is sampled
This parameter is sampled
2t
ns
CYC
ZZ Inactive to exit snooze current
0
ns
RZZI
Operation
Add. Used
None
CE
X
L
CE
WRITE
CLK
DQ
CE
H
L
ZZ ADSP ADSC ADV
OE
X
X
X
X
X
X
L
2
3
1
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Snooze Mode,Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
X
X
H
X
H
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
None
None
L
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
L
None
X
L
X
X
X
L
X
Tri-State
Q
External
External
External
External
External
Next
L-H
L
L
L
H
X
L
L-H Tri-State
L
L
H
H
H
H
H
X
L-H
L-H
D
Q
L
L
L
H
H
H
H
H
L
L
L
H
L
L-H Tri-State
L-H
L-H Tri-State
L-H
X
X
H
X
X
X
H
H
H
Q
Next
L
H
L
Next
L
Q
Document #: 38-05237 Rev. *D
Page 13 of 36
CY7C1380C
CY7C1382C
Truth Table[ 3, 4, 5, 6, 7, 8]
Operation
Add. Used
Next
CE
X
CE
X
WRITE
CLK
DQ
CE
ZZ ADSP ADSC ADV
OE
2
3
1
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle,Suspend Burst
H
L
L
L
L
L
L
L
L
L
X
H
X
H
H
X
X
H
X
H
H
H
H
H
H
H
H
H
L
L
H
H
L-H Tri-State
Next
X
H
X
X
H
H
X
H
X
X
L
L
X
X
L
L-H
L-H
L-H
D
D
Q
Next
X
X
L
Current
Current
Current
Current
Current
Current
X
X
H
H
H
H
H
H
H
H
H
H
L
X
X
H
L
L-H Tri-State
L-H
L-H Tri-State
X
X
Q
X
X
H
X
X
X
X
L-H
L-H
D
D
WRITE Cycle,Suspend Burst
X
X
L
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the signal. is asynchronous and is not sampled with the clock.
OE
OE
6. CE , CE , and CE are available only in the TQFP package. BGA package has only 2 chip selects CE and CE .
1
2
3
1
2
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks
X
after the
or with the assertion of
. As a result,
ADSC
must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state.
is a
OE
OE
ADSP
don't care for the remainder of the write cycle
8.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when
is
OE
OE
.
inactive or when the device is deselected, and all data bits behave as output when
is active (LOW)
OE
Truth Table for Read/Write[5]
Function (CY7C1380C)
BW
BW
X
H
H
H
H
L
BW
X
H
H
L
BW
A
GW
H
BWE
H
D
C
B
Read
Read
X
H
H
H
H
H
H
H
H
L
X
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
Write Byte A – ( DQ and DQP )
A
A
Write Byte B – ( DQ and DQP )
H
L
B
B
Write Bytes B, A
Write Byte C – ( DQ and DQP )
L
H
H
L
H
L
C
C
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
L
L
H
L
L
L
Write Byte D – ( DQ and DQP )
H
H
H
H
L
H
H
L
H
L
D
D
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
L
L
H
L
L
L
L
H
H
L
H
L
L
L
L
L
H
L
L
L
L
Write All Bytes
X
X
X
X
Truth Table for Read/Write[5]
Function (CY7C1382C)
BW
X
BW
A
GW
H
BWE
B
Read
Read
H
L
L
L
L
L
X
X
H
L
H
H
H
H
H
L
H
H
L
Write Byte A – ( DQ and DQP )
A
A
Write Byte B – ( DQ and DQP )
H
L
B
B
Write Bytes B, A
Write All Bytes
Write All Bytes
L
L
L
X
X
Document #: 38-05237 Rev. *D
Page 14 of 36
CY7C1380C
CY7C1382C
Test MODE SELECT (TMS)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
The CY7C1380C incorporates a serial boundary scan test
access port (TAP). This port operates in accordance with IEEE
Standard 1149.1-1990 but does not have the set of functions
required for full 1149.1 compliance. These functions from the
IEEE specification are excluded because their inclusion
places an added delay in the critical speed path of the SRAM.
Note that the TAP controller functions in a manner that does
not conflict with the operation of other devices using 1149.1
fully compliant TAPs. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure . TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
The CY7C1380C contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID
register.
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alter-
nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
0
Bypass Register
TEST-LOGIC
1
RESET
0
2
1
0
0
0
1
1
1
Selection
Circuitry
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
Instruction Register
31 30 29
Identification Register
0
Selection
Circuitry
TDI
TDO
0
0
.
.
.
2
1
1
1
CAPTURE-DR
CAPTURE-IR
0
0
x
.
.
.
.
.
2
1
SHIFT-DR
0
SHIFT-IR
0
Boundary Scan Register
1
1
1
1
EXIT1-DR
EXIT1-IR
TCK
TMS
0
0
TAP CONTROLLER
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
UPDATE-DR
UPDATE-IR
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Registers
Test Access Port (TAP)
Test Clock (TCK)
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
Document #: 38-05237 Rev. *D
Page 15 of 36
CY7C1380C
CY7C1382C
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
IDCODE
Boundary Scan Register
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The SRAM has a 75-bit-long
register.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
SAMPLE/PRELOAD
Identification (ID) Register
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus
t
t
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
hold time ( CS plus CH).
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Document #: 38-05237 Rev. *D
Page 16 of 36
CY7C1380C
CY7C1382C
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
BYPASS
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
TH
CYC
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Parameter
Symbol
Min
Max
Units
Clock
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
Output Times
t
100
ns
MHz
ns
TCYC
t
10
20
TF
t
40
40
TH
t
ns
TL
TCK Clock LOW to TDO Valid
t
t
ns
ns
TDOV
TCK Clock LOW to TDO Invalid
Setup Times
0
TDOX
TMS Set-Up to TCK Clock Rise
TDI Set-Up to TCK Clock Rise
Capture Set-Up to TCK Rise
Hold Times
t
10
10
10
ns
ns
TMSS
t
TDIS
t
CS
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
t
10
10
10
ns
ns
ns
TMSH
t
TDIH
Capture Hold after Clock Rise
t
CH
Notes:
t
t
9. CS and CH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1ns.
R
F
Document #: 38-05237 Rev. *D
Page 17 of 36
CY7C1380C
CY7C1382C
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ........ ........................................VSS to 3.3V
Input rise and fall times...................... ..............................1ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Input pulse levels...............................................VSS to 2.5V
Input rise and fall time ......................................................1ns
Input timing reference levels................... ......................1.25V
Output reference levels .................. ..............................1.25V
Test load termination supply voltage .................... ........1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
ZO= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
[11]
(0°C < TA < +70°C; Vdd = 3.3V ±0.165V unless otherwise noted)
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
2.4
2.0
2.9
2.1
MAX
UNITS
V
V
V
V
V
V
V
V
V
V
V
V
µA
V
V
V
V
V
V
Output HIGH Voltage
I
I
I
= -4.0 mA,V
= -1.0 mA,V
= -100 µA
= 3.3V
= 2.5V
OH1
OH2
OL1
OL2
IH
OH
OH
OH
DDQ
DDQ
V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
0.4
0.4
0.2
0.2
I
I
= 8.0 mA
= 100 µA
OL
OL
2.0
1.7
-0.3
-0.3
-5
V
V
+ 0.3
DD
DD
+ 0.3
0.8
IL
0.7
5
I
GND < V < V
IN DDQ
X
Note:
11. All voltages referenced to VSS (GND).
Document #: 38-05237 Rev. *D
Page 18 of 36
CY7C1380C
CY7C1382C
Identification Register Definitions
CY7C1380C
(512KX36)
CY7C1382C
(1MX18)
DESCRIPTION
INSTRUCTION FIELD
010
0100
1010
Revision Number (31:29)
Device Depth (28:24)
Describes the version number.
01010
Reserved for Internal Use
000000
100101
00000110100
1
000000
010101
00000110100
1
Device Width (23:18)
Defines memory type and architecture
Defines width and density
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
REGISTER NAME
BIT SIZE(X36)
BIT SIZE(X18)
3
3
Instruction
1
1
Bypass
32
72
32
72
ID
Boundary Scan Order
Identification Codes
INSTRUCTION
CODE
DESCRIPTION
000
EXTEST
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
001
010
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
011
100
RESERVED
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
101
110
111
RESERVED
RESERVED
BYPASS
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operations.
Document #: 38-05237 Rev. *D
Page 19 of 36
CY7C1380C
CY7C1382C
119-Ball BGA Boundary Scan Order
CY7C1380C (512K x 36)
BIT#
BALL ID
BIT#
BALL ID
1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
B2
K4
H4
M4
F4
B4
A4
G4
C6
A6
D6
D7
E6
G6
H7
E7
F6
G7
H6
T7
K7
L6
2
P4
3
N4
4
R6
5
T5
6
T3
7
R2
8
R3
9
P2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
P1
N2
L2
K1
N1
M2
L1
K2
Not Bonded (Preset to 1)
H1
G2
E2
N6
P7
K6
L7
D1
H2
G1
F2
M6
N7
P6
B5
B3
C5
C3
C2
A2
T4
B6
E1
D2
A5
A3
E4
Internal
L3
G3
G5
L5
Internal
Document #: 38-05237 Rev. *D
Page 20 of 36
CY7C1380C
CY7C1382C
119-Ball BGA Boundary Scan Order
CY7C1382C (1M x 18)
BIT#
BALL ID
BIT#
BALL ID
1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
B2
K4
2
P4
H4
3
M4
N4
4
F4
R6
5
B4
T5
6
A4
T3
7
G4
R2
8
C6
R3
9
A6
Not Bonded (Preset to 0)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
T6
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
P2
D6
N1
E7
M2
F6
L1
G7
K2
H6
Not Bonded (Preset to 1)
T7
H1
K7
G2
L6
E2
N6
D1
P7
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
A5
B5
B3
C5
C3
C2
A2
T2
B6
A3
E4
Internal
Not Bonded (Preset to 0)
Internal
G3
L5
Internal
Document #: 38-05237 Rev. *D
Page 21 of 36
CY7C1380C
CY7C1382C
165-Ball fBGA Boundary Scan Order
CY7C1380C (512K x 36)
BIT#
BALL ID
BIT#
BALL ID
1
B6
B7
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
N6
R6
P6
R4
R3
P4
P3
R1
N1
L2
2
3
A7
4
B8
5
A8
6
B9
7
A9
8
B10
A10
C11
E10
F10
G10
D10
D11
E11
F11
G11
H11
J10
K10
L10
M10
J11
K11
L11
M11
N11
R11
R10
R9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
K2
J2
M2
M1
L1
K1
J1
Internal
G2
F2
E2
D2
G1
F1
E1
D1
C1
A2
B2
A3
B3
B4
A4
A5
B5
A6
R8
P10
P9
P8
P11
Document #: 38-05237 Rev. *D
Page 22 of 36
CY7C1380C
CY7C1382C
165-Ball fBGA Boundary Scan Order
CY7C1382C (1M x 18)
BIT#
BALL ID
BIT#
BALL ID
0
B6
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
N6
1
B7
R6
2
A7
P6
3
B8
R4
4
A8
R3
5
B9
P4
6
A9
P3
7
B10
R1
8
A10
Not Bonded (Preset to 0)
9
A11
Not Bonded (Preset to 0)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
N1
C11
M1
D11
L1
E11
K1
F11
J1
G11
Internal
H11
G2
J10
F2
K10
E2
L10
D2
M10
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
A2
R11
R10
R9
B2
A3
B3
R8
Not Bonded (Preset to 0)
P10
P9
Not Bonded (Preset to 0)
A4
B5
A6
P8
P11
Document #: 38-05237 Rev. *D
Page 23 of 36
CY7C1380C
CY7C1382C
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on V Relative to GND........ –0.3V to +4.6V
DD
Ambient
Range
Temperature
V
V
DDQ
DC Voltage Applied to Outputs
DD
in Tri-State........................................... –0.5V to V
+ 0.5V
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
DDQ
to V
DC Input Voltage....................................–0.5V to V + 0.5V
DD
Industrial
-40°C to +85°C
DD
Electrical Characteristics Over the Operating Range
Parameter
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
Unit
V
V
3.6
DD
V
V
V
V
V
I
V
V
V
V
V
V
V
V
V
V
= 3.3V
= 2.5V
V
DD
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
2.625
V
Output HIGH Voltage
Output LOW Voltage
= 3.3V, V = Min., I = –4.0 mA
V
OH
OL
IH
DD
OH
= 2.5V, V = Min., I = –1.0 mA
2.0
V
DD
OH
= 3.3V, V = Min., I = 8.0 mA
0.4
0.4
V
DD
OL
= 2.5V, V = Min., I = 1.0 mA
V
DD
OL
Input HIGH Voltage
= 3.3V
= 2.5V
= 3.3V
= 2.5V
2.0
1.7
V
V
+ 0.3V
V
DD
DD
+ 0.3V
V
Input LOW Voltage
–0.3
–0.3
–5
0.8
V
IL
0.7
5
V
Input Load Current ex- GND ≤ V ≤ V
cept ZZ and MODE
µA
X
I
DDQ
Input Current of MODE Input = V
–30
–30
–5
µA
µA
SS
Input = V
5
DD
Input Current of ZZ
Input = V
Input = V
µA
SS
DD
5
µA
I
I
Output Leakage Current GND ≤ V ≤ V
Output Disabled
5
µA
OZ
I
DDQ,
V
Operating Supply
V
f = f
= Max., I
= 0 mA,
4.0-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
7.5-ns cycle, 133 MHz
4.0-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
7.5-ns cycle, 133 MHz
All speeds
350
325
300
275
245
120
110
100
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DD
DD
DD
OUT
= 1/t
MAX CYC
Current
I
I
Automatic CE
Power-down
Current—TTL Inputs
V = Max, Device Deselected,
DD
SB1
SB2
V
≥ V or V ≤ V
IN
IH
IN
IL
f = f
= 1/t
MAX CYC
85
Automatic CE
Power-down
Current—CMOS Inputs f = 0
V
V
= Max, Device Deselected,
≤ 0.3V or V > V – 0.3V,
70
DD
IN
IN
DDQ
Document #: 38-05237 Rev. *D
Page 24 of 36
CY7C1380C
CY7C1382C
[12, 13] (continued)
Electrical Characteristics Over the Operating Range
Parameter
Description
Automatic CE
Power-down
Test Conditions
Min.
Max.
105
100
95
Unit
mA
mA
mA
mA
mA
mA
I
V
= Max, Device Deselected, or 4.0-ns cycle, 250 MHz
DD
SB3
V
≤ 0.3V or V > V
– 0.3V
IN
IN
DDQ
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
7.5-ns cycle, 133 MHz
All speeds
Current—CMOS Inputs f = f
= 1/t
MAX
CYC
85
80
I
Automatic CE
Power-down
Current—TTL Inputs
V
V
= Max, Device Deselected,
80
SB4
DD
≥ V or V ≤ V , f = 0
IN
IH IN IL
Shaded areas contain advance information.
Notes:
12. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > -2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
< V
DD\
13. TPower-up: Assumes a linear ramp from 0v to V (min.) within 200ms. During this time V < V and V
DD
IH
DD
DDQ
Thermal Resistance[14]
TQFP
Package
BGA
Package
fBGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard
test methods and procedures
for measuring thermal
31
45
46
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
6
7
3
°C/W
impedence, per EIA / JESD51.
Capacitance[14]
TQFP
BGA
fBGA
Parameter
Description
Input Capacitance
Test Conditions
Package
Package
Package
Unit
pF
C
C
C
T = 25°C, f = 1 MHz,
5
5
5
8
8
8
9
9
9
IN
A
V
V
= 3.3V.
DD
Clock Input Capacitance
Input/Output Capacitance
pF
CLK
I/O
= 2.5V
DDQ
pF
Notes:
14. Tested initially and after any design or process change that may affect these parameters
Document #: 38-05237 Rev. *D
Page 25 of 36
CY7C1380C
CY7C1382C
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDD
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
GND
5 pF
R = 351Ω
≤ 1ns
≤ 1ns
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDD
90%
10%
Z = 50Ω
0
10%
L
GND
5 pF
R =1538Ω
≤ 1ns
≤ 1ns
V = 1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Document #: 38-05237 Rev. *D
Page 26 of 36
CY7C1380C
CY7C1382C
Switching Characteristics Over the Operating Range
250 MHz
225 MHz
200 MHz
167 MHz
133 MHz
Parameter
Description
Min. Max
Min. Max Min. Max Unit
t
V
(Typical) to the first Access
1
1
1
1
1
ms
POWER
DD
Clock
t
t
t
Clock Cycle Time
Clock HIGH
4.0
1.7
1.7
4.4
2.0
2.0
5
6
7.5
2.5
2.5
ns
ns
ns
CYC
CH
2.0
2.0
2.2
2.2
Clock LOW
CL
Output Times
t
t
t
t
t
t
t
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
2.6
1.0
2.8
1.0
3.0
1.3
3.4
4.2
ns
ns
ns
ns
ns
ns
ns
CO
1.3
1.3
1.3
1.3
DOH
CLZ
Clock to Low-Z
1.0
1.0
1.3
Clock to High-Z
2.6
2.8
3.0
3.4
3.4
3.4
4.2
CHZ
OEV
OELZ
OEHZ
2.6
2.8
3.0
OE LOW to Output Valid
0
0
0
0
0
LOW to Output Low-Z
OE
2.6
2.8
3.0
3.4
4.0
OE HIGH to Output High-Z
Setup Times
t
t
Address Set-up Before CLK Rise
1.2
1.2
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
ns
ns
AS
,
ADSC ADSP Set-up Before CLK
ADS
Rise
t
t
1.2
1.2
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
ns
ns
ADV Set-up Before CLK Rise
ADVS
Set-up Before CLK
GW, BWE, BW
Rise
WES
X
t
t
Data Input Set-up Before CLK Rise
1.2
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
ns
ns
DS
Chip Enable Set-Up Before CLK Rise 1.2
CES
Hold Times
t
t
t
t
t
t
Address Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
AH
,
Hold After CLK Rise
ADH
ADVH
WEH
DH
ADSP ADSC
ADV Hold After CLK Rise
,
,
GW BWE BW Hold After CLK Rise
X
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
CEH
Shaded areas contain advance information.
Notes:
15. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V ( minimum) initially before a read or write operation
DD
POWER
can be initiated.
16. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
17. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
18. This parameter is sampled and not 100% tested.
19. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05237 Rev. *D
Page 27 of 36
CY7C1380C
CY7C1382C
Switching Waveforms
Read Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,
BWx
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV
suspends
burst.
t
t
OEV
CO
t
t
OEHZ
t
t
CHZ
OELZ
DOH
t
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Notes:
21. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
22.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document #: 38-05237 Rev. *D
Page 28 of 36
CY7C1380C
CY7C1382C
Switching Waveforms (continued)
Write Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BWX
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
Data In (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Document #: 38-05237 Rev. *D
Page 29 of 36
CY7C1380C
CY7C1382C
Switching Waveforms (continued)
Read/Write Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE,
BWX
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
Note:
23.
24. GW is HIGH.
.
The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by
ADSP or ADSC
Document #: 38-05237 Rev. *D
Page 30 of 36
CY7C1380C
CY7C1382C
Switching Waveforms (continued)
ZZ Mode Timing
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
26. DQs are in high-Z when exiting ZZ sleep mode
Document #: 38-05237 Rev. *D
Page 31 of 36
CY7C1380C
CY7C1382C
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Part and Package Type
250
CY7C1380C-250AC
CY7C1382C-250AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
Commercial
CY7C1380C-250BGC
CY7C1382C-250BGC
BG119 119 PBGA
BB165A 165 fBGA
CY7C1380C-250BZC
CY7C1382C-250BZC
225
200
CY7C1380C-225AC
CY7C1382C-225AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
CY7C1380C-225BGC
CY7C1382C-225BGC
BG119 119 PBGA
BB165A 165 fBGA
CY7C1380C-225BZC
CY7C1382C-225BZC
CY7C1380C-200AC
CY7C1382C-200AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
CY7C1380C-200BGC
CY7C1382C-200BGC
CY7C1380C-200BZC
CY7C1382C-200BZC
BG119 119 PBGA
BB165A 165 fBGA
167
CY7C1380C-167AC
CY7C1382C-167AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
CY7C1380C-167BGC
CY7C1382C-167BGC
BG119 119 PBGA
CY7C1380C-167BZC
CY7C1382C-167BZC
BB165A 165 fBGA
133
167
CY7C1380C-133AC
A101
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
CY7C1380C-167AI
CY7C1382C-167AI
Industrial
CY7C1380C-167BGI
CY7C1382C-167BGI
BG119 119 PBGA
BB165A 165 fBGA
CY7C1380C-167BZI
CY7C1382C-167BZI
Shaded areas contain advance information.
Please contact your local sales representative for availability of these parts.
Document #: 38-05237 Rev. *D
Page 32 of 36
CY7C1380C
CY7C1382C
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
STAND-OFF
0.05 MIN.
0.15 MAX.
SEATING PLANE
0.25
GAUGE PLANE
R 0.08 MIN.
0.20 MAX.
0°-7°
0.60 0.15
0.20 MIN.
1.00 REF.
51-85050-*A
DETAIL
A
Document #: 38-05237 Rev. *D
Page 33 of 36
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1380C
CY7C1382C
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05237 Rev. *D
Page 34 of 36
CY7C1380C
CY7C1382C
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05237 Rev. *D
Page 35 of 36
CY7C1380C
CY7C1382C
Document History Page
Document Title: CY7C1380C/CY7C1382C 18-Mb (512K x 36/1M x 18) Pipelined SRAM
Document Number: 38-05237
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
116277
121540
08/27/02
11/21/02
SKX
DSG
New Data Sheet
*A
Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85122
(BB165A) to rev. *C
*B
*C
121797
128904
11/21/02
09/11/03
CJM
DPM
Added 7C1380C-133 spec
Updated Ordering Information
Changed ordering of notes
Updated JTAG Boundary Scan order
Removed Pipelined Read/Write Timing diagram
Added t
specification in Switching Characteristics table
POWER
*D
206081
02/13/04
RKF
Final Datasheet
Document #: 38-05237 Rev. *D
Page 36 of 36
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