Cypress CY7C1361C User Manual

CY7C1361C

CY7C1363C

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

Features

Functional Description^[1]

• Supports 100, 133-MHz bus operations

• Supports 100-MHz bus operations (Automotive)

• 256K × 36/512K × 18 common I/O

The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36/512K x 18

Synchronous Flow-through SRAMs, respectively designed to

interface with high-speed microprocessors with minimum glue

logic. Maximum access delay from clock rise is 6.5 ns

(133-MHz version). A 2-bit on-chip counter captures the first

address in a burst and increments the address automatically

for the rest of the burst access. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

• 3.3V –5% and +10% core power supply (V

)

• 2.5V or 3.3V I/O power supply (V

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

)

DDQ

addresses, all data inputs, address-pipelining Chip Enable

[2]

• Provide high-performance 2-1-1-1 access rate

(CE ), depth-expansion Chip Enables (CE and CE ), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables (BW ,

• User-selectable burst counter supporting Intel

and BWE), and Global Write (GW). Asynchronous inputs

include the Output Enable (OE) and the ZZ pin.

Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

The CY7C1361C/CY7C1363C allows either interleaved or

linear burst sequences, selected by the MODE input pin. A

HIGH selects an interleaved burst sequence, while a LOW

selects a linear burst sequence. Burst accesses can be

initiated with the Processor Address Strobe (ADSP) or the

cache Controller Address Strobe (ADSC) inputs. Address

advancement is controlled by the Address Advancement

(ADV) input.

• Asynchronous output enable

• Available in lead-free 100-Pin TQFP package, lead-free

and non lead-free 119-Ball BGA package and 165-Ball

FBGA package

• TQFP Available with 3-Chip Enable and 2-Chip Enable

• IEEE 1149.1 JTAG-Compatible Boundary Scan

•“ZZ” Sleep Mode option

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

The CY7C1361C/CY7C1363C operates from a +3.3V core

power supply while all outputs may operate with either a +2.5

or +3.3V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

133 MHz

6.5

100 MHz

8.5

Unit

Maximum Access Time

Maximum Operating Current

250

180

Maximum CMOS Standby Current

Comm/Ind’l

Automotive

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE is for A version of TQFP (3 Chip Enable Option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.

Cypress Semiconductor Corporation

Document #: 38-05541 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 14, 2006

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CY7C1361C

CY7C1363C

Pin Configurations

100-Pin TQFP Pinout (3 Chip Enables) (A version)

DQP_C

DQP_B

DQ_B

V_DDQ

V_SSQ

DQ_B

V_SSQ

V_DDQ

DQ_B

V_SS

V_DDQ

V_SSQ

V_DDQ

V_SSQ

DQP_A

DQ_A

V_SSQ

V_DDQ

DQ_A

V_SS

DQ_C

V_DDQ

V_SSQ

DQ_C

DQ_B

V_SSQ

V_DDQ

DQ_B

V_SS/DNU

V_DD

DQ_C

V_SSQ

V_DDQ

DQ_C

V_SS/DNU

V_DD

CY7C1363C

(512K x 18)

CY7C1361C

(256K x 36)

V_SS

V_DD

V_SS

DQ_D

DQ_A

V_DDQ

V_SSQ

DQ_A

V_SSQ

V_DDQ

DQ_A

DQP_A

DQ_B

V_DDQ

V_SSQ

DQ_B

DQP_B

V_SSQ

V_DDQ

DQ_A

V_DDQ

V_SSQ

DQ_A

DQ_D

V_DDQ

V_SSQ

DQ_D

V_SSQ

V_DDQ

DQ_D

V_SSQ

V_DDQ

DQP_D

Document #: 38-05541 Rev. *F

Page 3 of 31

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CY7C1361C

CY7C1363C

Pin Configurations (continued)

100-Pin TQFP Pinout (2 Chip Enables) (AJ Version)

DQP_C

DQ_C

V_DDQ

V_SSQ

DQ_C

V_SSQ

V_DDQ

DQ_C

V_SS/DNU

DQP_B

DQ_B

V_DDQ

V_SSQ

DQ_B

V_SSQ

V_DDQ

DQ_B

V_SS

V_DDQ

V_SSQ

V_DDQ

V_SSQ

DQP_A

DQ_A

V_SSQ

V_DDQ

DQ_A

V_SS

DQ_B

V_SSQ

V_DDQ

DQ_B

V_SS/DNU

V_DD

V_SS

DQ_D

V_DD

CY7C1363C

(512K x 18)

CY7C1361C

(256K x 36)

V_SS

V_DD

DQ_A

V_DDQ

V_SSQ

DQ_A

V_SSQ

V_DDQ

DQ_A

DQP_A

DQ_B

V_DDQ

V_SSQ

DQ_B

DQP_B

V_SSQ

V_DDQ

DQ_A

V_DDQ

V_SSQ

DQ_A

DQ_D

V_DDQ

V_SSQ

DQ_D

V_SSQ

V_DDQ

DQ_D

DQP_D

V_SSQ

V_DDQ

Document #: 38-05541 Rev. *F

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CY7C1361C

CY7C1363C

Pin Configurations (continued)

119-Ball BGA Pinout (2 Chip Enables with JTAG)

CY7C1361C (256K x 36)

DDQ

ADSP

ADSC

DDQ

NC/288M

NC/144M

NC/512M

NC/1G

DQP

DDQ

ADV

DDQ

CLK

DDQ

BWE

DDQ

DQP

MODE

NC/72M

TMS

NC/36M

TDI

TCK

TDO

DDQ

CY7C1363C (512K x 18)

DDQ

ADSP

ADSC

DDQ

NC/288M

NC/512M

NC/144M

NC/1G

DQP

ADV

DDQ

CLK

DDQ

BWE

DDQ

DQP

MODE

NC/72M

NC/36M

TCK

TMS

TDI

TDO

DDQ

Document #: 38-05541 Rev. *F

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CY7C1361C

CY7C1363C

Pin Configurations (continued)

165-Ball FBGA Pinout (3 Chip Enable)

CY7C1361C (256K x 36)

CE₁

BW_C

BW_B

ADV

NC/288M

NC/144M

DQP_C

BWE

V_SS

ADSC

CE₂

V_DDQ

BW_D

V_SS

BW_A

V_SS

CLK

V_SS

V_DD

ADSP

V_DDQ

NC/576M

DQP_B

DQ_B

DQ_C

NC/1G

DQ_B

DQ_C

V_DD

DQ_C

V_SS

V_DDQ

V_DD

V_SS

V_DD

V_DDQ

DQ_B

DQ_C

V_SS

DQ_B

DQ_D

V_DDQ

DQ_A

DQ_D

DQP_D

DQ_D

V_DDQ

V_DD

V_SS

V_DD

V_SS

V_DDQ

DQ_A

DQP_A

NC/18M

NC/72M

TDI

TDO

MODE

NC/36M

TMS

TCK

CY7C1363C (512K x 18)

CE₁

BW_B

ADV

NC/288M

NC/144M

BWE

V_SS

ADSC

CE₂

V_DDQ

V_SS

V_DD

BW_A

V_SS

CLK

V_SS

V_DD

ADSP

V_DDQ

NC/576M

DQP_A

DQ_A

NC/1G

DQ_B

V_SS

V_DDQ

V_DD

V_SS

V_DD

V_DDQ

DQ_A

V_SS

DQ_A

V_SS

DQ_B

V_DDQ

DQ_A

DQ_B

DQP_B

V_DDQ

V_DD

V_SS

NC/18M

V_SS

V_DD

V_SS

V_DDQ

DQ_A

NC/72M

TDI

TDO

MODE

NC/36M

TMS

TCK

Document #: 38-05541 Rev. *F

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CY7C1361C

CY7C1363C

Pin Definitions

Name

I/O

Description

Address Inputs used to select one of the address locations. Sampled at the rising

A , A , A

Input-

[2]

Synchronous edge of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE

are sampled

active. A

feed the 2-bit counter.

[1:0]

BW ,BW

Input-

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the

BW ,BW

Synchronous SRAM. Sampled on the rising edge of CLK.

Input- Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a

Synchronous global write is conducted (ALL bytes are written, regardless of the values on BW and BWE).

CLK

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment

the burst counter when ADV is asserted LOW, during a burst operation.

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in

[2]

Synchronous conjunction with CE and CE

to select/deselect the device. ADSP is ignored if CE is

HIGH. CE is sampled only when a new external address is loaded.

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

[2]

Synchronous conjunction with CE and CE

to select/deselect the device. CE is sampled only when

a new external address is loaded.

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in

Synchronous conjunction with CE and CE to select/deselect the device.CE is sampled only when a

[2]

Input-

new external address is loaded.

Input-

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.

Asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are

tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle

when emerging from a deselected state.

ADV

Input-

Advance Input signal, sampled on the rising edge of CLK. When asserted, it automat-

Synchronous ically increments the address in a burst cycle.

ADSP

Input-

Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.

Synchronous When asserted LOW, addresses presented to the device are captured in the address

registers. A

are also loaded into the burst counter. When ADSP and ADSC are both

[1:0]

asserted, only ADSP is recognized. ASDP is ignored when

is deasserted HIGH.

ADSC

Input-

Synchronous When asserted LOW, addresses presented to the device are captured in the address

registers. A are also loaded into the burst counter. When ADSP and ADSC are both

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.

[1:0]

asserted, only ADSP is recognized.

BWE

Input-

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal

Synchronous must be asserted LOW to conduct a byte write.

Input-

ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a

Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation,

this pin has to be LOW or left floating. ZZ pin has an internal pull-down.

I/O-

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is

Synchronous triggered by the rising edge of CLK. As outputs, they deliver the data contained in the

memory location specified by the addresses presented during the previous clock rise of

the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,

the pins behave as outputs. When HIGH, DQ and DQP are placed in a tri-state

condition.The outputs are automatically tri-stated during the data portion of a write

sequence, during the first clock when emerging from a deselected state, and when the

device is deselected, regardless of the state of OE.

I/O-

Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ .

DQP

Synchronous During write sequences, DQP is controlled by BW correspondingly.

MODE

Input-

Static

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V

or left floating selects interleaved burst sequence. This is a strap pin and should remain

static during device operation. Mode Pin has an internal pull-up.

Power Supply Power supply inputs to the core of the device.

I/O Power Supply Power supply for the I/O circuitry.

DDQ

Document #: 38-05541 Rev. *F

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CY7C1361C

CY7C1363C

Pin Definitions (continued)

Name

I/O

Description

Ground

Ground for the core of the device.

I/O Ground

Ground for the I/O circuitry.

SSQ

TDO

JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the

Synchronous JTAG feature is not being utilized, this pin should be left unconnected. This pin is not

available on TQFP packages.

TDI

JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG

Synchronous feature is not being utilized, this pin can be left floating or connected to V through a pull

up resistor. This pin is not available on TQFP packages.

TMS

JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG

Synchronous feature is not being utilized, this pin can be disconnected or connected to V . This pin

is not available on TQFP packages.

TCK

JTAG-

Clock

Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must

be connected to V . This pin is not available on TQFP packages.

–

No Connects. Not internally connected to the die. 18M, 36M, 72M, 144M, 288M, 576M

and 1G are address expansion pins and are not internally connected to the die.

/DNU

Ground/DNU

This pin can be connected to Ground or should be left floating.

Document #: 38-05541 Rev. *F

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CY7C1361C

CY7C1363C

active, (2) ADSC is asserted LOW, (3) ADSP is deasserted

Functional Overview

HIGH, and (4) the write input signals (GW, BWE, and BW )

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. Maximum access delay from

indicate a write access. ADSC is ignored if ADSP is active

LOW.

the clock rise (t

) is 6.5 ns (133-MHz device).

CDV

The addresses presented are loaded into the address register

and the burst counter/control logic and delivered to the

The CY7C1361C/CY7C1363C supports secondary cache in

systems utilizing either a linear or interleaved burst sequence.

The interleaved burst order supports Pentium and i486™

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is

user-selectable, and is determined by sampling the MODE

input. Accesses can be initiated with either the Processor

Address Strobe (ADSP) or the Controller Address Strobe

(ADSC). Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

memory core. The information presented to DQ

will be

[A:D]

written into the specified address location. Byte writes are

allowed. All I/Os are tri-stated when a write is detected, even

a byte write. Since this is a common I/O device, the

asynchronous OE input signal must be deasserted and the

I/Os must be tri-stated prior to the presentation of data to DQ .

As a safety precaution, the data lines are tri-stated once a write

cycle is detected, regardless of the state of OE.

Burst Sequences

The CY7C1361C/CY7C1363C provides an on-chip two-bit

wraparound burst counter inside the SRAM. The burst counter

Byte write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW ) inputs. A Global Write

is fed by A

, and can follow either a linear or interleaved

[1:0]

burst order. The burst order is determined by the state of the

MODE input. A LOW on MODE will select a linear burst

sequence. A HIGH on MODE will select an interleaved burst

order. Leaving MODE unconnected will cause the device to

default to a interleaved burst sequence.

Enable (GW) overrides all byte write inputs and writes data to

all four bytes. All writes are simplified with on-chip

synchronous self-timed write circuitry.

[2]

Three synchronous Chip Selects (CE , CE , CE ) and an

asynchronous Output Enable (OE) provide for easy bank

Interleaved Burst Address Table

selection and output tri-state control. ADSP is ignored if CE

is HIGH.

(MODE = Floating or V_DD

)

First

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

Single Read Accesses

Address

A1: A0

A single read access is initiated when the following conditions

are satisfied at clock rise: (1) CE , CE , and CE

[2]

are all

asserted active, and (2) ADSP or ADSC is asserted LOW (if

the access is initiated by ADSC, the write inputs must be

deasserted during this first cycle). The address presented to

the address inputs is latched into the address register and the

burst counter/control logic and presented to the memory core.

If the OE input is asserted LOW, the requested data will be

Linear Burst Address Table (MODE = GND)

available at the data outputs a maximum to t

rise. ADSP is ignored if CE is HIGH.

after clock

CDV

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are

[2]

satisfied at clock rise: (1) CE , CE , CE

are all asserted

active, and (2) ADSP is asserted LOW. The addresses

presented are loaded into the address register and the burst

inputs (GW, BWE, and BW )are ignored during this first clock

cycle. If the write inputs are asserted active (see Write Cycle

Descriptions table for appropriate states that indicate a write)

on the next clock rise, the appropriate data will be latched and

written into the device.Byte writes are allowed. All I/Os are

tri-stated during a byte write.Since this is a common I/O

device, the asynchronous OE input signal must be deasserted

and the I/Os must be tri-stated prior to the presentation of data

to DQs. As a safety precaution, the data lines are tri-stated

once a write cycle is detected, regardless of the state of OE.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CE , CE , CE , ADSP, and ADSC must

remain inactive for the duration of t

returns LOW.

[2]

Single Write Accesses Initiated by ADSC

after the ZZ input

ZZREC

This write access is initiated when the following conditions are

[2]

satisfied at clock rise: (1) CE , CE , and CE

are all asserted

Document #: 38-05541 Rev. *F

Page 9 of 31

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CY7C1361C

CY7C1363C

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

ZZ > V – 0.2V

Min.

Max.

Unit

Sleep mode standby current

Comm/ind’l

Automotive

DDZZ

Device operation to ZZ

ZZ recovery time

ZZ > V – 0.2V

ZZS

CYC

ZZ < 0.2V

ZZREC

ZZI

CYC

ZZ active to sleep current

ZZ Inactive to exit sleep current

This parameter is sampled

RZZI

Truth Table ^{[3, 4, 5, 6, 7]}

Address

Used CE CE CE ZZ ADSP

Cycle Description

ADSC ADV WRITE OE CLK

Deselected Cycle, Power-down None

L-H

Tri-state

Sleep Mode, Power-down

Read Cycle, Begin Burst

Write Cycle, Begin Burst

Read Cycle, Begin Burst

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

None

External

L-H

Tri-state

Current

Tri-state

Notes:

3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.

4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.

5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks after

the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't

care for the remainder of the write cycle.

7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is

inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

Document #: 38-05541 Rev. *F

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CY7C1361C

CY7C1363C

Partial Truth Table for Read/Write^{[3, 8]}

Function (CY7C1361C)

BWE

Read

Write Byte (A, DQP )

Write Byte (B, DQP )

Write Bytes (B, A, DQP , DQP )

Write Byte (C, DQP )

Write Bytes (C, A, DQP , DQP )

Write Bytes (C, B, DQP , DQP )

Write Bytes (C, B, A, DQP , DQP , DQP )

Write Byte (D, DQP )

Write Bytes (D, A, DQP , DQP )

Write Bytes (D, B, DQP , DQP )

Write Bytes (D, B, A, DQP , DQP , DQP )

Write Bytes (D, B, DQP , DQP )

Write Bytes (D, B, A, DQP , DQP , DQP )

Write Bytes (D, C, A, DQP , DQP , DQP )

Write All Bytes

Truth Table for Read/Write^{[3, 8]}

BWE

Function (CY7C1363C)

Read

Write Byte A – (DQ and DQP )

Write Byte B – (DQ and DQP )

Write All Bytes

Note:

8. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid Appropriate write will be done based on which byte write is active.

Document #: 38-05541 Rev. *F

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CY7C1361C

CY7C1363C

Test MODE SELECT (TMS)

IEEE 1149.1 Serial Boundary Scan (JTAG)

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this ball unconnected if the TAP is not used. The ball is

pulled up internally, resulting in a logic HIGH level.

The CY7C1361C/CY7C1363C incorporates a serial boundary

scan test access port (TAP) in the BGA package only. The

TQFP package does not offer this functionality. This part

operates in accordance with IEEE Standard 1149.1-1900, but

doesn’t have the set of functions required for full 1149.1

compliance. These functions from the IEEE specification are

excluded because their inclusion places an added delay in the

critical speed path of the SRAM. Note the TAP controller

functions in a manner that does not conflict with the operation

of other devices using 1149.1 fully compliant TAPs. The TAP

operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.

Test Data-In (TDI)

The TDI ball is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. TDI

is internally pulled up and can be unconnected if the TAP is

unused in an application. TDI is connected to the most signif-

icant bit (MSB) of any register. (See Tap Controller Block

Diagram.)

The CY7C1361C/CY7C1363C contains a TAP controller,

instruction register, boundary scan register, bypass register,

and ID register.

Test Data-Out (TDO)

Disabling the JTAG Feature

The TDO output ball is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine. The output changes on the

falling edge of TCK. TDO is connected to the least significant

bit (LSB) of any register. (See Tap Controller State Diagram.)

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(V ) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to V through a pull-up resistor. TDO should be

left unconnected. Upon power-up, the device will come up in

a reset state which will not interfere with the operation of the

device.

TAP Controller Block Diagram

Bypass Register

TAP Controller State Diagram

TEST-LOGIC

Selection

Circuitry

RESET

Instruction Register

31 30 29

Identification Register

Selection

Circuitry

TDI

TDO

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

CAPTURE-IR

Boundary Scan Register

SHIFT-DR

SHIFT-IR

TCK

TMS

EXIT1-DR

EXIT1-IR

TAP CONTROLLER

PAUSE-DR

PAUSE-IR

Performing a TAP Reset

EXIT2-DR

EXIT2-IR

A RESET is performed by forcing TMS HIGH (V ) for five

rising edges of TCK. This RESET does not affect the operation

of the SRAM and may be performed while the SRAM is

operating.

UPDATE-DR

UPDATE-IR

At power-up, the TAP is reset internally to ensure that TDO

comes up in a High-Z state.

TAP Registers

The 0/1 next to each state represents the value of TMS at the

rising edge of TCK.

Registers are connected between the TDI and TDO balls and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time through

the instruction register. Data is serially loaded into the TDI ball

on the rising edge of TCK. Data is output on the TDO ball on

the falling edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

Document #: 38-05541 Rev. *F

Page 12 of 31

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CY7C1361C

CY7C1363C

TDI and TDO balls as shown in the Tap Controller Block

Diagram. Upon power-up, the instruction register is loaded

with the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.

through the instruction register through the TDI and TDO balls.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be

executed whenever the instruction register is loaded with all

0s. EXTEST is not implemented in this SRAM TAP controller,

and therefore this device is not compliant to 1149.1. The TAP

controller does recognize an all-0 instruction.

When the TAP controller is in the Capture-IR state, the two

least significant bits are loaded with a binary “01” pattern to

allow for fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

TDI and TDO balls. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

When an EXTEST instruction is loaded into the instruction

instruction has been loaded. There is one difference between

the two instructions. Unlike the SAMPLE/PRELOAD

instruction, EXTEST places the SRAM outputs in a High-Z

state.

(V ) when the BYPASS instruction is executed.

Boundary Scan Register

IDCODE

The boundary scan register is connected to all the input and

bidirectional balls on the SRAM.

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO balls and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state.

The boundary scan register is loaded with the contents of the

RAM I/O ring when the TAP controller is in the Capture-DR

state and is then placed between the TDI and TDO balls when

the controller is moved to the Shift-DR state. The EXTEST,

SAMPLE/PRELOAD and SAMPLE Z instructions can be used

to capture the contents of the I/O ring.

The IDCODE instruction is loaded into the instruction register

upon power-up or whenever the TAP controller is given a test

logic reset state.

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI and the LSB is connected to TDO.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO balls when the TAP

controller is in a Shift-DR state. It also places all SRAM outputs

into a High-Z state.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1-mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the in-

struction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is cap-

tured in the boundary scan register.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is possi-

ble that during the Capture-DR state, an input or output will

undergo a transition. The TAP may then try to capture a signal

while in transition (metastable state). This will not harm the

device, but there is no guarantee as to the value that will be

captured. Repeatable results may not be possible.

TAP Instruction Set

Overview

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in the

Instruction Codes table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

The TAP controller used in this SRAM is not fully compliant to

the 1149.1 convention because some of the mandatory 1149.1

instructions are not fully implemented.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture set-up plus

hold times (t and t ). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE/PRELOAD instruction. If this

is an issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK# captured in the

boundary scan register.

The TAP controller cannot be used to load address data or

control signals into the SRAM and cannot preload the I/O

buffers. The SRAM does not implement the 1149.1 commands

EXTEST or INTEST or the PRELOAD portion of

SAMPLE/PRELOAD; rather, it performs a capture of the I/O

ring when these instructions are executed.

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the bound-

ary scan register between the TDI and TDO pins.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

Document #: 38-05541 Rev. *F

Page 13 of 31

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CY7C1363C

PRELOAD allows an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells

prior to the selection of another boundary scan test operation.

BYPASS

When the BYPASS instruction is loaded in the instruction

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

The shifting of data for the SAMPLE and PRELOAD phases

can occur concurrently when required—that is, while data

captured is shifted out, the preloaded data can be shifted in.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

TAP Timing

Test Clock

(TCK)

CYC

TMSS

TDIS

TMSH

Test Mode Select

(TMS)

TDIH

Test Data-In

(TDI)

TDOV

TDOX

Test Data-Out

(TDO)

DON’T CARE

UNDEFINED

[9, 10]

TAP AC Switching Characteristics Over the Operating Range

Parameter

Clock

Parameter

Min.

Max.

Unit

TCK Clock Cycle Time

TCK Clock Frequency

TCK Clock HIGH Time

TCK Clock LOW Time

MHz

TCYC

Output Times

TCK Clock LOW to TDO Valid

TCK Clock LOW to TDO Invalid

TDOV

TDOX

Set-up Times

TMS Set-Up to TCK Clock Rise

TDI Set-Up to TCK Clock Rise

Capture Set-Up to TCK Rise

TMSS

TDIS

Hold Times

TMS Hold after TCK Clock Rise

TDI Hold after Clock Rise

TMSH

TDIH

Capture Hold after Clock Rise

Notes:

9. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.

10. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.

Document #: 38-05541 Rev. *F

Page 14 of 31

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CY7C1361C

CY7C1363C

3.3V TAP AC Test Conditions

2.5V TAP AC Test Conditions

Input pulse levels ................................................ V to 3.3V

Input pulse levels.................................................V to 2.5V

Input rise and fall times................................................... 1 ns

Input timing reference levels...........................................1.5V

Output reference levels...................................................1.5V

Test load termination supply voltage...............................1.5V

Input rise and fall time .....................................................1 ns

Input timing reference levels......................................... 1.25V

Output reference levels ................................................ 1.25V

Test load termination supply voltage ............................ 1.25V

3.3V TAP AC Output Load Equivalent

2.5V TAP AC Output Load Equivalent

1.5V

1.25V

50Ω

TDO

Z_O= 50Ω

20pF

TAP DC Electrical Characteristics And Operating Conditions

[11]

(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)

Parameter

Description

= –4.0 mA

Conditions

= 3.3V

= 2.5V

= 3.3V

= 2.5V

= 3.3V

= 2.5V

= 3.3V

= 2.5V

= 3.3V

= 2.5V

= 3.3V

= 2.5V

Min.

2.4

2.0

2.9

2.1

Max.

Unit

Output HIGH Voltage

OH1

OH2

OL1

OL2

DDQ

= –1.0 mA

= –100 µA

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Input Load Current

= 8.0 mA

= 100 µA

0.4

0.2

2.0

1.7

+ 0.3

–0.5

–0.3

–5

0.7

GND < V < V

DDQ

µA

Identification Register Definitions

CY7C1361C

(256K x36)

CY7C1363C

(512K x18)

Instruction Field

Description

Revision Number (31:29)

000

01011

000

Describes the version number.

Reserved for Internal Use

[12]

Device Depth (28:24)

01011

Device Width (23:18) 119-BGA

Device Width (23:18) 165-FBGA

Cypress Device ID (17:12)

101001

000001

100110

00000110100

101001

000001

010110

Defines memory type and architecture

Defines width and density

Cypress JEDEC ID Code (11:1)

ID Register Presence Indicator (0)

00000110100 Allows unique identification of SRAM vendor.

Indicates the presence of an ID register.

Notes:

11. All voltages referenced to V (GND).

12. Bit #24 is “1” in the Register Definitions for both 2.5V and 3.3V versions of this device.

Document #: 38-05541 Rev. *F

Page 15 of 31

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CY7C1363C

Scan Register Sizes

Bit Size (x 36)

Bit Size (x 18)

Instruction

Bypass

Boundary Scan Order (119-ball BGA package)

Boundary Scan Order (165-ball FBGA package)

Identification Codes

Instruction

EXTEST

Code

Description

000

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM outputs to High-Z state.

IDCODE

001

010

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operations.

SAMPLE Z

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED

011

100

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation.

RESERVED

BYPASS

101

110

111

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

Document #: 38-05541 Rev. *F

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CY7C1363C

119-Ball BGA Boundary Scan Order

CY7C1361C (256K x 36)

CY7C1363C (512K x 18)

Signal

Name

Signal

Name

Bit # ball ID

Name

CLK

Bit # ball ID

Bit #

ball ID

Name

CLK

Bit #

ball ID

BWE

ADSC

ADSP

ADV

ADSC

ADSP

ADV

MODE

Internal

DQP

Internal

DQP

Internal

DQP

Internal

DQP

Internal

DQP

Internal

BWD

Internal

Document #: 38-05541 Rev. *F

Page 17 of 31

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CY7C1361C

CY7C1363C

165-Ball FBGA Boundary Scan Order

CY7C1361C (256K x 36)

CY7C1363C (512K x 18)

Signal

Name

Signal

Name

Signal

Name

Bit # ball ID

Name

CLK

Bit #

ball ID

Bit # ball ID

Bit #

ball ID

CLK

BWE

ADSC

ADSP

ADV

ADSC

ADSP

ADV

MODE

Internal

B10

A10

C11

E10

F10

G10

D10

D11

E11

F11

G11

H11

J10

K10

L10

M10

J11

K11

L11

M11

N11

R11

R10

P10

DQP

B10

Internal

A10

DQP

A11

Internal

C11

Internal

DQP

D11

E11

Internal

F11

Internal

G11

H11

J10

K10

L10

Internal

M10

Internal

R11

Internal

DQP

Internal

DQP

Internal

R10

P10

Internal

P11

Document #: 38-05541 Rev. *F

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CY7C1361C

CY7C1363C

Current into Outputs (LOW)......................................... 20 mA

Maximum Ratings

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Latch-up Current..................................................... >200 mA

Storage Temperature ................................–65°C to + 150°C

Operating Range

Ambient Temperature with

Power Applied............................................–55°C to + 125°C

Ambient

Range

Temperature

DDQ

Supply Voltage on V Relative to GND....... –0.5V to + 4.6V

Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%

Supply Voltage on V

Relative to GND .....–0.5V to + V

DDQ

to V

Industrial

–40°C to +85°C

DC Voltage Applied to Outputs

in tri-state ............................................ –0.5V to V

+ 0.5V

Automotive –40°C to +125°C

DDQ

DC Input Voltage....................................–0.5V to V + 0.5V

[13, 14]

Electrical Characteristics Over the Operating Range

Parameter

Description

Power Supply Voltage

I/O Supply Voltage

Test Conditions

Min.

3.135

2.375

2.4

Max.

Unit

3.6

for 3.3V I/O

for 2.5V I/O

DDQ

2.625

Output HIGH Voltage

Output LOW Voltage

for 3.3V I/O, I = −4.0 mA

for 2.5V I/O, I = −1.0 mA

2.0

for 3.3V I/O, I = 8.0 mA

0.4

for 2.5V I/O, I = 1.0 mA

[13]

Input HIGH Voltage

for 3.3V I/O

for 2.5V I/O

for 3.3V I/O

for 2.5V I/O

2.0

1.7

+ 0.3V

0.8

[13]

Input LOW Voltage

–0.3

–5

0.7

Input Leakage Current GND ≤ V ≤ V

except ZZ and MODE

µA

DDQ

Input Current of MODE Input = V

–30

–5

µA

Input = V

Input Current of ZZ

Input = V

Output Leakage Current GND < V < V

Output Disabled

–5

DDQ,

Operating Supply

f = f

= Max., I

= 0 mA,

7.5-ns cycle,133 MHz

10-ns cycle,100 MHz

250

180

110

150

OUT

= 1/t

MAX CYC

Current

Automatic CE

Power-down

Max. V , Device Deselected, All speeds (Comm/Ind’l)

SB1

V > V or V < V , f = f

IN IH IN IL MAX,

10-ns cycle,100 MHz

(Automotive)

Current—TTL Inputs

inputs switching

Automatic CE

Power-down

Current—CMOS Inputs f = 0, inputs static

Max. V , Device Deselected, All speeds

SB2

> V – 0.3V or V < 0.3V,

DD IN

Automatic CE

Power-down

Current—CMOS Inputs f = f

Max. V , Device Deselected, All speeds (Comm/Ind’l)

100

120

SB3

> V

– 0.3V or V < 0.3V,

DDQ IN

10-ns cycle,100 MHz

(Automotive)

, inputs switching

MAX

Automatic CE

Power-down

Current—TTL Inputs

Max. V , Device Deselected, All speeds (Comm/Ind’l)

SB4

> V or V < V

IN IH IN IL

10-ns cycle,100 MHz

(Automotive)

f = 0, inputs static

Notes:

13. Overshoot: V (AC) < V +1.5V (Pulse width less than t

/2), undershoot: V (AC) > –2V (Pulse width less than t /2).

CYC

14. T

: Assumes a linear ramp from 0V to V (min.) within 200ms. During this time V < V and V

< V

Power-up

DDQ

Document #: 38-05541 Rev. *F

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CY7C1363C

Capacitance^[15]

100 TQFP 119 BGA 165 FBGA

Parameter

Description

Input Capacitance

Test Conditions

Max.

Unit

T = 25°C, f = 1 MHz,

= 3.3V

= 2.5V

Clock Input Capacitance

Input/Output Capacitance

CLK

I/O

DDQ

Thermal Resistance^[15]

100 TQFP

Package

119 BGA

Package

165 FBGA

Package

Parameter

Description

Test Conditions

Unit

Θ_JA

Thermal Resistance

(Junction to Ambient)

Test conditions follow standard

test methods and procedures

for measuring thermal

29.41

34.1

16.8

°C/W

Θ_JC

Thermal Resistance

(Junction to Case)

6.31

14.0

3.0

°C/W

impedance, per EIA/JESD51

AC Test Loads and Waveforms

3.3V I/O Test Load

R = 317Ω

3.3V

OUTPUT

ALL INPUT PULSES

90%

V_DDQ

90%

10%

Z = 50Ω

R = 50Ω

10%

GND

5 pF

INCLUDING

R = 351Ω

≤ 1 ns

V = 1.5V

JIG AND

SCOPE

(a)

(b)

(c)

2.5V I/O Test Load

R = 1667Ω

2.5V

OUTPUT

R = 50Ω

OUTPUT

ALL INPUT PULSES

90%

V_DDQ

GND

90%

10%

Z = 50Ω

10%

5 pF

R = 1538Ω

≤ 1 ns

V = 1.25V

INCLUDING

JIG AND

SCOPE

(a)

(b)

(c)

Note:

15. Tested initially and after any design or process change that may affect these parameters.

Document #: 38-05541 Rev. *F

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CY7C1363C

[20, 21]

Switching Characteristics Over the Operating Range

–133

–100

Parameter

Description

Min.

Max.

Min.

Max.

Unit

[16]

(Typical) to the first Access

POWER

Clock

Clock Cycle Time

Clock HIGH

7.5

3.0

4.0

CYC

Clock LOW

Output Times

Data Output Valid After CLK Rise

Data Output Hold After CLK Rise

6.5

8.5

CDV

DOH

CLZ

2.0

[17, 18, 19]

Clock to Low-Z

[17, 18, 19]

Clock to High-Z

3.5

CHZ

OEV

OELZ

OEHZ

OE LOW to Output Valid

[17, 18, 19]

OE LOW to Output Low-Z

[17, 18, 19]

OE HIGH to Output High-Z

3.5

Set-up Times

Address Set-up Before CLK Rise

1.5

ADSP, ADSC Set-up Before CLK Rise

ADV Set-up Before CLK Rise

ADS

ADVS

WES

GW, BWE, BW

Set-up Before CLK Rise

[A:D]

Data Input Set-up Before CLK Rise

Chip Enable Set-up

CES

Hold Times

Address Hold After CLK Rise

0.5

ADSP, ADSC Hold After CLK Rise

ADH

WEH

ADVH

GW, BWE, BW

Hold After CLK Rise

[A:D]

ADV Hold After CLK Rise

Data Input Hold After CLK Rise

Chip Enable Hold After CLK Rise

CEH

Notes:

16. This part has a voltage regulator internally; t

is the time that the power needs to be supplied above V (minimum) initially, before a read or write operation

POWER

can be initiated.

17. t

, t

, and t

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

OEHZ

CHZ CLZ OELZ

18. At any given voltage and temperature, t

is less than t

and t

is less than t

to eliminate bus contention between SRAMs when sharing the same

OEHZ

OELZ

CHZ

CLZ

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

19. This parameter is sampled and not 100% tested.

20. Timing reference level is 1.5V when V

= 3.3V and is 1.25V when V

= 2.5V.

DDQ

21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

Document #: 38-05541 Rev. *F

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CY7C1361C

CY7C1363C

Timing Diagrams

[22]

Read Cycle Timing

CYC

CLK

ADH

ADS

ADSP

ADSC

ADH

ADS

ADDRESS

WES

WEH

GW, BWE,BW

Deselect Cycle

CES

CEH

ADVH

ADVS

ADV

ADV suspends burst

CDV

OEV

OELZ

OEHZ

CHZ

DOH

CLZ

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A1)

Data Out (Q)

High-Z

CDV

Burst wraps around

to its initial state

Single READ

BURST

READ

DON’T CARE

UNDEFINED

Note:

22. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.

Document #: 38-05541 Rev. *F

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CY7C1363C

Timing Diagrams (continued)

[22, 23]

Write Cycle Timing

CYC

CLK

ADH

ADS

ADSP

ADSC extends burst

ADH

ADS

ADH

ADS

ADSC

ADDRESS

Byte write signals are ignored for first cycle when

ADSP initiates burst

WEH

WES

BWE,

BWX

WEH

WES

CEH

CES

ADVH

ADVS

ADV

ADV suspends burst

Data in (D)

High-Z

D(A2)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

D(A1)

OEHZ

Data Out (Q)

BURST READ

BURST WRITE

Extended BURST WRITE

Single WRITE

DON’T CARE

UNDEFINED

Note:

23.

Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.

Document #: 38-05541 Rev. *F

Page 23 of 31

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CY7C1363C

Timing Diagrams (continued)

[22, 24, 25]

Read/Write Cycle Timing

CYC

CLK

ADH

ADS

ADSP

ADSC

ADDRESS

BWE, BWX

WEH

WES

CEH

CES

ADV

OELZ

High-Z

D(A3)

D(A5)

D(A6)

Data In (D)

OEHZ

CDV

Data Out (Q)

Q(A1)

Q(A2)

Q(A4)

Q(A4+1)

Q(A4+2)

Q(A4+3)

Back-to-Back

Back-to-Back READs

Single WRITE

BURST READ

WRITEs

DON’T CARE

UNDEFINED

Notes:

24. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

25.

GW is HIGH.

Document #: 38-05541 Rev. *F

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CY7C1363C

Timing Diagrams (continued)

[26, 27]

ZZ Mode Timing

CLK

ZZREC

ZZI

SUPPLY

DDZZ

RZZI

ALL INPUTS

(except ZZ)

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

Notes:

26. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

27. DQs are in high-Z when exiting ZZ sleep mode.

Document #: 38-05541 Rev. *F

Page 25 of 31

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CY7C1361C

CY7C1363C

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz)

Package

Diagram

Operating

Range

Ordering Code

Part and Package Type

133 CY7C1361C-133AXC

CY7C1363C-133AXC

CY7C1361C-133AJXC

CY7C1363C-133AJXC

CY7C1361C-133BGC

CY7C1363C-133BGC

CY7C1361C-133BGXC

CY7C1363C-133BGXC

CY7C1361C-133BZC

CY7C1363C-133BZC

CY7C1361C-133BZXC

CY7C1363C-133BZXC

CY7C1361C-133AXI

CY7C1363C-133AXI

CY7C1361C-133AJXI

CY7C1363C-133AJXI

CY7C1361C-133BGI

CY7C1363C-133BGI

CY7C1361C-133BGXI

CY7C1363C-133BGXI

CY7C1361C-133BZI

CY7C1363C-133BZI

CY7C1361C-133BZXI

CY7C1363C-133BZXI

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

(3 Chip Enable)

Commercial

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

(2 Chip Enable)

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

(3 Chip Enable)

lndustrial

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

(2 Chip Enable)

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

Document #: 38-05541 Rev. *F

Page 26 of 31

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CY7C1361C

CY7C1363C

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz)

Package

Diagram

Operating

Range

Ordering Code

Part and Package Type

100 CY7C1361C-100AXC

CY7C1363C-100AXC

CY7C1361C-100AJXC

CY7C1363C-100AJXC

CY7C1361C-100BGC

CY7C1363C-100BGC

CY7C1361C-100BGXC

CY7C1363C-100BGXC

CY7C1361C-100BZC

CY7C1363C-100BZC

CY7C1361C-100BZXC

CY7C1363C-100BZXC

CY7C1361C-100AXI

CY7C1363C-100AXI

CY7C1361C-100AJXI

CY7C1363C-100AJXI

CY7C1361C-100BGI

CY7C1363C-100BGI

CY7C1361C-100BGXI

CY7C1363C-100BGXI

CY7C1361C -100BZI

CY7C1363C-100BZI

CY7C1361C-100BZXI

CY7C1363C-100BZXI

100 CY7C1361C-100AXE

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

(3 Chip Enable)

Commercial

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

(2 Chip Enable)

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

(3 Chip Enable)

lndustrial

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

(2 Chip Enable)

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Automotive

Document #: 38-05541 Rev. *F

Page 27 of 31

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CY7C1361C

CY7C1363C

Package Diagrams

100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)

16.00 0.20

1.40 0.05

14.00 0.10

100

0.30 0.08

0.65

TYP.

12° 1°

(8X)

SEE DETAIL

0.20 MAX.

1.60 MAX.

R 0.08 MIN.

0.20 MAX.

0° MIN.

SEATING PLANE

STAND-OFF

0.05 MIN.

0.15 MAX.

NOTE:

0.25

1. JEDEC STD REF MS-026

GAUGE PLANE

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

R 0.08 MIN.

0.20 MAX.

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

0°-7°

0.60 0.15

0.20 MIN.

51-85050-*B

1.00 REF.

DETAIL

Document #: 38-05541 Rev. *F

Page 28 of 31

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CY7C1361C

CY7C1363C

Package Diagrams (continued)

119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)

Ø0.05 M C

Ø0.25 M C A B

A1 CORNER

Ø0.75 0.15(119X)

Ø1.00(3X) REF.

1.27

0.70 REF.

3.81

12.00

7.62

14.00 0.20

0.15(4X)

30° TYP.

51-85115-*B

SEATING PLANE

Document #: 38-05541 Rev. *F

Page 29 of 31

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CY7C1361C

CY7C1363C

Package Diagrams (continued)

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D

165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)

BOTTOM VIEW

PIN 1 CORNER

TOP VIEW

Ø0.05 M C

Ø0.25 M C A B

PIN 1 CORNER

-0Ø.060.25 M C A B

Ø0.50 (165X)

+0.14

-0.06

Ø0.50₃

(165X)

11 10

+0.14

11 10

1.00

5.00

1.00

5.00

10.00

13.00 0.10

0.15(4X)

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

PACKAGE WEIGHT : 0.475g

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE WEIGHT : 0.475g

PACKAJEGDEECCORDEEFE:RBEBN0ACEC: MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

SEATING PLANE

51-85180-*A

i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM

Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05541 Rev. *F

Page 30 of 31

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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CY7C1361C

CY7C1363C

Document History Page

Document Title: CY7C1361C/CY7C1363C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

Document Number: 38-05541

Orig. of

REV.

ECN NO. Issue Date

Change

Description of Change

241690

278969

332059

See ECN

RKF

New data sheet

RKF

Changed Boundary Scan order to match the B rev of these devices.

PCI

Removed 117-MHz Speed Bin

Address expansion pins/balls in the pinouts for all packages are modified

as per JEDEC standard

Added Address Expansion pins in the Pin Definitions Table

Changed Device Width (23:18) for 119-BGA from 000001 to 101001

Added separate row for 165 -FBGA Device Width (23:18)

Changed I

from 35 mA to 50 mA

DDZZ

Changed I

and I

from 40 mA to 110 and 100 mA, respectively

SB1

SB3

Modified V

Corrected I

test conditions

OL, OH

Test Condition from (V ≥ V – 0.3V or V ≤ 0.3V) to

SB4

(V ≥ V or V ≤ V ) in the Electrical Characteristics table

Changed Θ and Θ for TQFP Package from 25 and 9 °C/W to 29.41

and 6.13 °C/W

respectively

Changed Θ and Θ for BGA Package from 25 and 6°C/W to 34.1 and

14.0 °C/W

respectively

Changed Θ and Θ for FBGA Package from 27 and 6 °C/W to 16.8

and 3.0 °C/W respectively

Added lead-free information for 100-pin TQFP, 119 BGA and 165 FBGA

packages

Updated Ordering Information Table

377095

408298

See ECN

PCI

Changed I

from 30 to 40 mA

SB2

Modified test condition in note# 14 from V < V to V < V

RXU

Changed address of Cypress Semiconductor Corporation on Page# 1

from “3901 North First Street” to “198 Champion Court”

Changed tri state to tri-state.

Modified “Input Load” to “Input Leakage Current except ZZ and MODE”

in the Electrical Characteristics Table.

Replaced Package Name column with Package Diagram in the Ordering

Information table.

Updated the ordering information.

433033

501793

See ECN

NXR

VKN

Included Automotive range.

Added the Maximum Rating for Supply Voltage on V

Relative to GND

from 5 ns to 10 ns in TAP

DDQ

Changed t , t from 25 ns to 20 ns and t

TH TL

TDOV

AC Switching Characteristics table.

Updated the Ordering Information table.

Document #: 38-05541 Rev. *F

Page 31 of 31

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