Cypress CY7C1347G User Manual

CY7C1347G  
4-Mbit (128K x 36) Pipelined Sync SRAM  
Functional Description[1]  
Features  
The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined  
Fully registered inputs and outputs for pipelined operation  
SRAM designed to support zero-wait-state secondary cache  
with minimal glue logic. CY7C1347G IO pins can operate at  
either the 2.5V or the 3.3V level. The IO pins are 3.3V tolerant  
128K x 36 common IO architecture  
3.3V core power supply (V  
)
DD  
when V  
= 2.5V. All synchronous inputs pass through input  
DDQ  
registers controlled by the rising edge of the clock. All data  
outputs pass through output registers controlled by the rising  
edge of the clock. Maximum access delay from the clock rise is  
2.6 ns (250 MHz device). CY7C1347G supports either the  
interleaved burst sequence used by the Intel Pentium processor  
or a linear burst sequence used by processors such as the  
2.5V/3.3V IO power supply (V  
)
DDQ  
Fast clock to output times: 2.6 ns (for 250 MHz device)  
®
®
User-selectable burst counter supporting Intel Pentium  
interleaved or linear burst sequences  
Separate processor and controller address strobes  
Synchronous self-timed writes  
®
PowerPC . The burst sequence is selected through the MODE  
pin. Accesses can be initiated by asserting either the Address  
Strobe from Processor (ADSP) or the Address Strobe from  
Controller (ADSC) at clock rise. Address advancement through  
the burst sequence is controlled by the ADV input. A 2-bit on-chip  
wraparound burst counter captures the first address in a burst  
sequence and automatically increments the address for the rest  
of the burst access.  
Asynchronous output enable  
Offered in Pb-free 100-Pin TQFP, Pb-free and non Pb-free  
119-Ball BGA package, and 165-Ball FBGA package  
“ZZ” sleep mode option and stop clock option  
Byte write operations are qualified with the four Byte Write Select  
Available in industrial and commercial temperature ranges  
(BW  
) inputs. A Global Write Enable (GW) overrides all byte  
[A:D]  
write inputs and writes data to all four bytes. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
Three synchronous Chip Selects (CE , CE , CE ) and an  
1
2
3
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. To provide proper data  
during depth expansion, OE is masked during the first clock of a  
read cycle when emerging from a deselected state.  
Selection Guide  
Specification  
250 MHz  
2.6  
200 MHz  
2.8  
166 MHz  
3.5  
133 MHz  
4.0  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
325  
265  
240  
225  
mA  
mA  
40  
40  
40  
40  
Note  
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.  
Cypress Semiconductor Corporation  
Document #: 38-05516 Rev. *F  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 15, 2009  
 
CY7C1347G  
Pinouts  
Figure 1. 100-Pin TQFP  
DQPC  
DQC  
DQC  
VDDQ  
VSSQ  
DQC  
DQC  
DQC  
DQC  
VSSQ  
VDDQ  
DQC  
DQC  
NC  
DQPB  
DQB  
DQB  
VDDQ  
VSSQ  
DQB  
DQB  
DQB  
DQB  
VSSQ  
VDDQ  
DQB  
DQB  
VSS  
1
2
3
4
5
6
7
8
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
BYTE C  
BYTE B  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
CY7C1347G  
VDD  
NC  
VSS  
NC  
VDD  
ZZ  
DQD  
DQD  
VDDQ  
VSSQ  
DQD  
DQD  
DQD  
DQD  
VSSQ  
VDDQ  
DQD  
DQD  
DQPD  
DQA  
DQA  
VDDQ  
VSSQ  
DQA  
DQA  
DQA  
DQA  
VSSQ  
VDDQ  
DQA  
DQA  
DQPA  
BYTE D  
BYTE A  
Document #: 38-05516 Rev. *F  
Page 3 of 22  
CY7C1347G  
Pinouts (continued)  
Figure 2. 119-Ball BGA  
2
1
3
A
A
A
4
5
A
A
A
6
A
7
V
A
CE  
A
ADSP  
ADSC  
V
DDQ  
A
B
C
D
E
F
DDQ  
NC/288M  
NC/144M  
CE  
A
NC/576M  
NC/1G  
2
3
V
DD  
DQ  
DQP  
V
NC  
CE  
V
DQP  
DQ  
C
C
SS  
SS  
SS  
SS  
SS  
SS  
B
B
DQ  
DQ  
DQ  
DQ  
DQ  
V
V
V
V
V
DQ  
DQ  
DQ  
DQ  
V
DQ  
B
C
C
1
B
V
V
DDQ  
DDQ  
C
C
C
OE  
ADV  
GW  
B
B
B
G
H
J
DQ  
DQ  
BW  
V
BW  
V
C
C
B
B
B
C
DQ  
DQ  
SS  
SS  
V
NC  
V
NC  
V
DDQ  
DDQ  
DD  
DD  
DD  
K
DQ  
DQ  
V
CLK  
V
DQ  
DQ  
D
D
SS  
SS  
A
A
L
M
N
DQ  
DQ  
DQ  
DQ  
BW  
V
NC  
BWE  
A1  
BW  
DQ  
DQ  
DQ  
DQ  
D
D
D
D
D
A
A
A
A
A
V
V
V
V
DDQ  
DDQ  
SS  
SS  
DQ  
V
DQ  
D
SS  
SS  
A
P
R
T
DQ  
DQP  
A
V
A0  
V
DQP  
A
DQ  
D
D
SS  
SS  
A
NC  
NC  
MODE  
A
V
NC  
A
A
NC  
ZZ  
DD  
NC/72M  
NC  
A
NC/36M  
NC  
U
V
NC  
NC  
NC  
V
DDQ  
DDQ  
Figure 3. 165-Ball FBGA  
1
2
3
CE1  
4
BWC  
5
BWB  
6
CE  
7
8
9
ADV  
10  
A
11  
NC  
NC/288M  
NC/144M  
DQPC  
BWE  
GW  
VSS  
VSS  
VSS  
ADSC  
A
B
C
D
A
A
3
CE2  
VDDQ  
VDDQ  
BWD  
VSS  
BWA  
VSS  
VSS  
CLK  
VSS  
VSS  
OE  
VSS  
VDD  
ADSP  
VDDQ  
VDDQ  
A
NC/576M  
DQPB  
DQB  
NC  
DQC  
NC/1G  
DQB  
DQC  
VDD  
DQC  
DQC  
DQC  
DQC  
VSS  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDDQ  
VDDQ  
VDDQ  
NC  
DQB  
DQB  
DQB  
NC  
DQB  
E
F
DQC  
DQC  
NC  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
DQB  
DQB  
ZZ  
G
H
J
DQD  
DQD  
DQD  
DQD  
DQD  
DQD  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQA  
DQA  
DQA  
DQA  
DQA  
DQA  
K
L
DQD  
DQPD  
NC  
DQD  
NC  
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
NC  
VSS  
NC/18M  
A1  
VSS  
VSS  
NC  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQA  
NC  
A
DQA  
DQPA  
NC/9M  
M
N
P
NC/72M  
A0  
MODE  
NC/36M  
A
A
NC  
NC  
A
A
A
A
R
Document #: 38-05516 Rev. *F  
Page 4 of 22  
CY7C1347G  
Table 1. Pin Definitions  
Name IO  
A ,A ,A  
Description  
Address Inputs Used to Select One of the 128K Address Locations. Sampled at the rising edge  
Input-  
0
1
Synchronous  
of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. A feeds  
1
2
3
[1:0]  
the 2-bit counter.  
BW BW  
Input-  
Synchronous  
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.  
Sampled on the rising edge of CLK.  
A,  
B,  
D
BW BW  
C,  
GW  
Input-  
Synchronous  
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global  
write is conducted (ALL bytes are written, regardless of the values on BW  
and BWE).  
[A:D]  
BWE  
CLK  
Input-  
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be  
Synchronous  
asserted LOW to conduct a byte write.  
Input-Clock  
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst  
counter when ADV is asserted LOW, during a burst operation.  
CE  
Input-  
Synchronous  
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE  
2
1
and CE to select or deselect the device. ADSP is ignored if CE is HIGH. CE is sampled only when  
3
1
1
a new external address is loaded.  
CE  
CE  
Input-  
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE  
1
2
Synchronous  
and CE to select or deselect the device. CE is sampled only when a new external address is loaded.  
3
2
Input-  
Synchronous  
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE  
1
3
and CE to select or deselect the device. CE is sampled only when a new external address is loaded.  
2
3
OE  
Input-  
Asynchronous  
Output Enable, Asynchronous Input, Active LOW. Controls the direction of the IO pins. When LOW,  
the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data  
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.  
ADV  
Input-  
Synchronous  
Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically  
increments the address in a burst cycle.  
ADSP  
Input-  
Synchronous  
Address Strobe from Processor, Sampled on the Rising Edge of CLK. When asserted LOW,  
addresses presented to the device are captured in the address registers. A  
are also loaded into the  
[1:0]  
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored  
when CE is deasserted HIGH.  
1
ADSC  
ZZ  
Input-  
Address Strobe from Controller, Sampled on the Rising Edge of CLK. When asserted LOW,  
Synchronous  
addresses presented to the device are captured in the address registers. A  
are also loaded into the  
[1:0]  
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.  
Input-  
Asynchronous  
ZZ “Sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition with  
data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an  
internal pull down.  
DQ DQ  
IO-  
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by the  
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the  
addresses presented during the previous clock rise of the read cycle. The direction of the pins is  
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs  
are placed in a tri-state condition.  
A,  
B
D
DQ DQ  
Synchronous  
C,  
DQP DQP  
A,  
B,  
D
DQP DQP  
C,  
V
V
V
V
Power Supply  
Ground  
Power Supply Inputs to the Core of the Device  
Ground for the Core of the Device  
DD  
SS  
IO Power Supply Power Supply for the IO circuitry  
DDQ  
SSQ  
IO Ground  
Ground for the IO circuitry  
MODE  
Input-  
Static  
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V  
or left  
DDQ  
floating selects interleaved burst sequence. This is a strap pin and must remain static during device  
operation. Mode pin has an internal pull up.  
NC, NC/9M,  
NC/18M,  
NC/36M,  
NC/72M,  
NC/144M,  
NC/288M,  
NC/576M,  
NC/1G  
No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,  
NC/288M, NC/576M, and NC/1G are address expansion pins that are not internally connected to the  
die.  
Document #: 38-05516 Rev. *F  
Page 5 of 22  
CY7C1347G  
described in Table 6 on page 8. Asserting the Byte Write Enable  
Functional Overview  
input (BWE) with the selected Byte Write (BW  
tively writes to only the desired bytes.  
) input selec-  
[A:D]  
All synchronous inputs pass through input registers controlled by  
the rising edge of the clock. All data outputs pass through output  
registers controlled by the rising edge of the clock. Maximum  
Bytes not selected during a byte write operation remain  
unaltered. A synchronous self-timed write mechanism is  
provided to simplify the write operations.  
access delay from the clock rise (t ) is 2.6 ns (250 MHz device).  
CO  
The CY7C1347G supports secondary cache in systems using  
either a linear or interleaved burst sequence. The linear burst  
sequence is suited for processors that use a linear burst  
sequence. The burst order is user selectable, and is determined  
by sampling the MODE input. Accesses can be initiated with  
either the Address Strobe from Processor (ADSP) or the Address  
Strobe from Controller (ADSC). Address advancement through  
the burst sequence is controlled by the ADV input. A two-bit  
on-chip wraparound burst counter captures the first address in a  
burst sequence and automatically increments the address for the  
rest of the burst access.  
Because the CY7C1347G is a common IO device, the Output  
Enable (OE) must be deasserted HIGH before presenting data  
to the DQs and DQPs inputs. Doing so tri-states the output  
drivers. As a safety precaution, DQs and DQPs are automatically  
tri-stated whenever a write cycle is detected, regardless of the  
state of OE.  
Single Write Accesses Initiated by ADSC  
ADSC write accesses are initiated when the following conditions  
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted  
HIGH, (3) CE , CE , CE are all asserted active, and (4) the  
1
2
3
Byte write operations are qualified with the Byte Write Enable  
appropriate combination of the write inputs (GW, BWE, and  
(BWE) and Byte Write Select (BW  
) inputs. A Global Write  
BW ) are asserted active to conduct a write to the desired  
[A:D]  
[A:D]  
Enable (GW) overrides all byte write inputs and writes data to all  
four bytes. All writes are simplified with on-chip synchronous  
self-timed write circuitry.  
byte(s). ADSC-triggered write accesses require a single clock  
cycle to complete. The address presented to A is loaded into  
[16:0]  
the address register and the address advancement logic while  
being delivered to the RAM core. The ADV input is ignored  
during this cycle. If a global write is conducted, the data  
presented to the DQs and DQPs is written into the corresponding  
address location in the RAM core. If a byte write is conducted,  
only the selected bytes are written. Bytes not selected during a  
byte write operation remain unaltered. A synchronous self-timed  
write mechanism has been provided to simplify the write opera-  
tions.  
Three synchronous Chip Selects (CE , CE , CE ) and an  
1
2
3
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. ADSP is ignored if CE is  
1
HIGH.  
Single Read Accesses  
This access is initiated when the following conditions are  
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)  
CE , CE , CE are all asserted active, and (3) the write signals  
Because the CY7C1347G is a common IO device, the Output  
Enable (OE) must be deasserted HIGH before presenting data  
to the DQs and DQPs inputs. Doing so tri-states the output  
drivers. As a safety precaution, DQs and DQPs are automatically  
tri-stated whenever a write cycle is detected, regardless of the  
state of OE.  
1
2
3
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE is  
1
HIGH. The address presented to the address inputs (A  
) is  
[16:0]  
stored into the address advancement logic and the Address  
Register while being presented to the memory core. The corre-  
sponding data is allowed to propagate to the input of the Output  
Registers. At the rising edge of the next clock the data is allowed  
to propagate through the Output Register and onto the data bus  
within 2.6 ns (250 MHz device) if OE is active LOW. The only  
exception occurs when the SRAM is emerging from a deselected  
state to a selected state, its outputs are always tri-stated during  
the first cycle of the access. After the first cycle of the access,  
the outputs are controlled by the OE signal. Consecutive single  
read cycles are supported. After the SRAM is deselected at clock  
rise by the chip select and either ADSP or ADSC signals, its  
output tri-states immediately.  
Burst Sequences  
The CY7C1347G provides a two-bit wraparound counter, fed by  
A
, that implements either an interleaved or linear burst  
[1:0]  
sequence. The interleaved burst sequence is designed  
specifically to support Intel Pentium applications. The linear  
burst sequence is designed to support processors that follow a  
linear burst sequence. The burst sequence is user-selectable  
through the MODE input.  
Asserting ADV LOW at clock rise automatically increments the  
burst counter to the next address in the burst sequence. Both  
read and write burst operations are supported.  
Single Write Accesses Initiated by ADSP  
This access is initiated when both of the following conditions are  
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE ,  
1
Sleep Mode  
CE , CE are all asserted active. The address presented to  
2
3
The ZZ input pin is an asynchronous input. Asserting ZZ places  
the SRAM in a power conservation “sleep” mode. Two clock  
cycles are required to enter into or exit from this “sleep” mode.  
While in this mode, data integrity is guaranteed. Accesses  
pending when entering the “sleep” mode are not considered valid  
nor is the completion of the operation guaranteed. The device  
A
is loaded into the Address Register and the address  
[16:0]  
advancement logic while being delivered to the RAM core. The  
write signals (GW, BWE, and BW  
ignored during this first cycle.  
) and ADV inputs are  
[A:D]  
ADSP-triggered write accesses require two clock cycles to  
complete. If GW is asserted LOW on the second clock rise, the  
data presented to the DQs and DQPs inputs is written into the  
corresponding address location in the RAM core. If GW is HIGH,  
must be deselected before entering the “sleep” mode. CE , CE ,  
1
2
CE , ADSP, and ADSC must remain inactive for the duration of  
3
t
after the ZZ input returns LOW.  
ZZREC  
then the write operation is controlled by BWE and BW  
[A:D]  
signals. The CY7C1347G provides byte write capability that is  
Document #: 38-05516 Rev. *F  
Page 6 of 22  
CY7C1347G  
Table 2. Interleaved Burst Sequence  
Table 3. Linear Burst Sequence  
First  
Address  
Second  
Address  
Third  
Address  
Fourth  
Address  
First  
Address  
Second  
Address  
Third  
Address  
Fourth  
Address  
A
A
A
A
A
A
A
A
[1:0]  
[1:0]  
[1:0]  
[1:0]  
[1:0]  
[1:0]  
[1:0]  
[1:0]  
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
00  
01  
10  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
Table 4. ZZ Mode Electrical Characteristics  
Parameter  
Description  
Snooze mode standby current  
Device operation to ZZ  
ZZ recovery time  
Test Conditions  
ZZ > V 0.2V  
Min  
Max  
Unit  
mA  
ns  
I
t
t
t
t
40  
DDZZ  
ZZS  
DD  
ZZ > V 0.2V  
2t  
DD  
CYC  
ZZ < 0.2V  
2t  
ns  
ZZREC  
ZZI  
CYC  
ZZ Active to snooze current  
This parameter is sampled  
This parameter is sampled  
2t  
ns  
CYC  
ZZ Inactive to exit snooze current  
0
ns  
RZZI  
Table 5. Truth Table  
Next Cycle  
Add.  
Used  
CE  
CE  
CE  
3
ZZ ADSP ADSC ADV WRITE OE CLK  
DQ  
1
2
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Snooze Mode, Power Down  
Read Cycle, Begin Burst  
None  
None  
H
L
X
L
X
X
H
X
H
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H Tri-State  
L-H Tri-State  
L-H Tri-State  
L-H Tri-State  
L-H Tri-State  
None  
L
X
L
L
None  
L
H
H
X
L
None  
L
X
X
H
H
H
H
H
X
X
X
X
L
None  
X
L
X
X
X
L
X
Tri-State  
External  
External  
External  
External  
External  
Next  
L-H Q  
Read Cycle, Begin Burst  
L
L
L
H
X
L
L-H Tri-State  
L-H D  
Write Cycle, Begin Burst  
L
L
H
H
H
H
H
X
X
Read Cycle, Begin Burst  
L
L
L
H
H
H
H
H
H
L-H Q  
Read Cycle, Begin Burst  
L
L
L
H
H
L
L-H Tri-State  
L-H Tri-State  
L-H Q  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
X
X
H
H
X
X
X
X
H
H
H
H
Next  
L
Next  
L
L
L-H Q  
Next  
L
H
L-H Tri-State  
Note  
2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW.  
3. WRITE = L when any one or more Byte Write Enable signals (BW , BW , BW , BW ) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BW ,  
A
B
C
D
A
BW , BW , BW ), BWE, GW = H.  
B
C
D
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.  
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks after  
[A:D]  
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to allow the outputs to tri-state. OE is a don't care for  
the remainder of the write cycle.  
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive  
or when the device is deselected, and all data bits behave as output when OE is active (LOW).  
Document #: 38-05516 Rev. *F  
Page 7 of 22  
           
CY7C1347G  
[2, 3, 4, 5, 6]  
Table 5. Truth Table  
Next Cycle  
(continued)  
Add.  
Used  
CE  
CE  
CE  
3
ZZ ADSP ADSC ADV WRITE OE CLK  
DQ  
1
2
Write Cycle, Continue Burst  
Write Cycle, Continue Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
Next  
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
X
H
H
X
X
H
X
H
H
H
H
H
H
H
H
L
L
L
L
X
X
L
L-H D  
L-H D  
L-H Q  
Next  
Current  
Current  
Current  
Current  
Current  
Current  
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H Tri-State  
L-H Q  
H
X
X
L-H Tri-State  
L-H D  
L
L-H D  
Table 6. Partial Truth Table for Read/Write  
Function  
GW  
BWE  
H
L
BW  
X
H
H
H
H
H
H
H
H
L
BW  
X
H
H
H
H
L
BW  
BW  
A
D
C
B
Read  
Read  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X
H
H
L
X
H
L
Write Byte A – DQ  
L
A
Write Byte B – DQ  
Write Bytes B, A  
L
H
L
B
L
L
Write Byte C– DQ  
Write Bytes C, A  
Write Bytes C, B  
L
H
H
L
H
L
C
L
L
L
L
H
L
Write Bytes C, B, A  
L
L
L
Write Byte D– DQ  
Write Bytes D, A  
Write Bytes D, B  
L
H
H
H
H
L
H
H
L
H
L
D
L
L
L
L
H
L
Write Bytes D, B, A  
Write Bytes D, C  
Write Bytes D, C, A  
Write Bytes D, C, B  
Write All Bytes  
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
Write All Bytes  
X
X
X
X
X
Note  
7. This table is only a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write is based on which byte write is active.  
x
Document #: 38-05516 Rev. *F  
Page 8 of 22  
   
CY7C1347G  
Maximum Ratings  
Exceeding the maximum ratings may shorten the battery life of  
the device. User guidelines are not tested.  
Current into Outputs (LOW)......................................... 20 mA  
Static Discharge Voltage.......................................... > 2001V  
(MIL-STD-883, Method 3015)  
Storage Temperature ..................................... −65°C to +150°C  
Ambient Temperature with  
Latch-Up Current................................................... > 200 mA  
Power Applied.................................................. −55°C to +125°C  
Operating Range  
Supply Voltage on V Relative to GND.........−0.5V to +4.6V  
DD  
Ambient  
Supply Voltage on V  
Relative to GND........−0.5V to +V  
DD  
DDQ  
Range  
V
V
DDQ  
DD  
Temperature  
0°C to +70°C  
–40°C to +85°C  
DC Voltage Applied to Outputs  
in High-Z State ........................................... −0.5V to V + 0.5V  
Commercial  
Industrial  
3.3V  
5%/+10% to V  
2.5V 5%  
DD  
DD  
DC Input Voltage ....................................... −0.5V to V + 0.5V  
DD  
Electrical Characteristics  
Over the Operating Range  
Parameter  
Description  
Power Supply Voltage  
IO Supply Voltage  
Test Conditions  
Min  
Max  
Unit  
V
V
3.135  
2.375  
2.4  
3.6  
DD  
V
V
V
V
DDQ  
OH  
DD  
Output HIGH Voltage  
For 3.3V IO, I = –4.0 mA  
V
OH  
For 2.5V IO, I = –1.0 mA  
2.0  
V
OH  
V
V
V
I
Output LOW Voltage  
For 3.3V IO, I = 8.0 mA  
0.4  
0.4  
V
OL  
IH  
IL  
OL  
For 2.5V IO, I = 1.0 mA  
V
OL  
Input HIGH Voltage  
For 3.3V IO  
For 2.5V IO  
For 3.3V IO  
For 2.5V IO  
GND < V < V  
2.0  
1.7  
V
V
+ 0.3V  
V
DD  
DD  
+ 0.3V  
V
Input LOW Voltage  
–0.3  
–0.3  
5  
0.8  
V
0.7  
5
V
Input Leakage Current  
Except ZZ and MODE  
μA  
X
I
DDQ  
Input Current of MODE Input = V  
Input = V  
30  
5  
μA  
μA  
SS  
DD  
SS  
DD  
5
Input Current of ZZ  
Input = V  
Input = V  
μA  
30  
5
μA  
I
I
Output Leakage Current GND V V  
Output Disabled  
5  
μA  
OZ  
I
DDQ,  
V
Operating Supply  
V
f = f  
= Max., I  
= 0 mA,  
4 ns cycle, 250 MHz  
5 ns cycle, 200 MHz  
6 ns cycle, 166 MHz  
7.5 ns cycle, 133 MHz  
4 ns cycle, 250 MHz  
5 ns cycle, 200 MHz  
6 ns cycle, 166 MHz  
7.5 ns cycle, 133 MHz  
All speeds  
325  
265  
240  
225  
120  
110  
100  
90  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
DD  
DD  
DD  
OUT  
= 1/t  
MAX CYC  
Current  
I
I
Automatic CE  
Power Down  
Current—TTL Inputs  
Max. V , Device Deselected,  
DD  
SB1  
SB2  
V
> V or V < V  
IN  
IH  
IN  
IL  
f = f  
= 1/t  
MAX CYC  
Automatic CE  
Power Down  
Max. V , Device Deselected,  
40  
DD  
V
< 0.3V or V > V  
– 0.3V,  
IN  
IN  
DDQ  
Current—CMOS Inputs f = 0  
Notes  
8. Overshoot: V (AC) < V +1.5V (pulse width less than t  
/2). Undershoot: V (AC) > –2V (pulse width less than t /2).  
CYC  
IH  
DD  
CYC  
IL  
9.  
T
: assumes a linear ramp from 0V to V (min) within 200 ms. During this time V < V and V  
< V  
.
Power up  
DD  
IH  
DD  
DDQ  
DD  
Document #: 38-05516 Rev. *F  
Page 9 of 22  
   
CY7C1347G  
Electrical Characteristics (continued)  
[8, 9]  
Over the Operating Range  
Parameter  
Description  
Automatic CE  
Power Down  
Current—CMOS Inputs f = f  
Test Conditions  
Min  
Max  
105  
95  
Unit  
mA  
mA  
mA  
mA  
mA  
I
Max. V , Device Deselected, or 4 ns cycle, 250 MHz  
SB3  
DD  
V
< 0.3V or V > V  
– 0.3V  
IN  
IN  
CYC  
DDQ  
5 ns cycle, 200 MHz  
6 ns cycle, 166 MHz  
7.5 ns cycle, 133 MHz  
= 1/t  
MAX  
85  
75  
I
Automatic CE  
Max. V , Device Deselected,  
45  
SB4  
DD  
Power Down  
Current—TTL Inputs  
V
V or V V , f = 0  
IN IH IN IL  
Capacitance  
Tested initially and after any design or process changes that may affect these parameters.  
100 TQFP  
119 BGA  
Max  
165 FBGA  
Max  
Parameter  
Description  
Test Conditions  
Unit  
Max  
C
Input Capacitance  
T = 25°C, f = 1 MHz,  
5
5
5
5
5
7
5
5
7
pF  
pF  
pF  
IN  
A
V
V
= 3.3V.  
DD  
C
C
Clock Input Capacitance  
Input/Output Capacitance  
CLK  
IO  
= 3.3V  
DDQ  
Thermal Resistance  
Tested initially and after any design or process changes that may affect these parameters.  
100 TQFP  
Package  
119 BGA  
Package  
165 FBGA  
Package  
Parameter  
Description  
Test Conditions  
Unit  
Θ
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard  
test methods and procedures for  
measuring thermal impedance,  
per EIA/JESD51.  
30.32  
34.1  
20.3  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
6.85  
14.0  
4.6  
°C/W  
JC  
AC Test Loads and Waveforms  
Figure 4. AC Test Loads and Waveforms  
3.3V IO Test Load  
R = 317Ω  
3.3V  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
OUTPUT  
90%  
10%  
Z = 50Ω  
0
RL = 50Ω  
10%  
GND  
5 pF  
R = 351Ω  
1 ns  
1 ns  
VT = 1.5V  
INCLUDING  
JIG AND  
SCOPE  
(c)  
(a)  
(b)  
2.5V IO Test Load  
R = 1667Ω  
2.5V  
OUTPUT  
R = 50Ω  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
90%  
10%  
Z = 50Ω  
0
10%  
L
5 pF  
R = 1538Ω  
1 ns  
1 ns  
INCLUDING  
JIG AND  
SCOPE  
VT = 1.25V  
(c)  
(a)  
(b)  
Document #: 38-05516 Rev. *F  
Page 10 of 22  
 
CY7C1347G  
Switching Characteristics  
Over the Operating Range  
–250  
Max  
–200  
–166  
–133  
Unit  
Parameter  
Description  
(Typical) to the first Access  
Min  
Min  
Max  
Min  
Max  
Min Max  
t
1
1
1
1
ms  
V
POWER  
DD  
Clock  
t
t
t
Clock Cycle Time  
Clock HIGH  
4.0  
1.7  
1.7  
5.0  
2.0  
2.0  
6.0  
2.5  
2.5  
7.5  
3.0  
3.0  
ns  
ns  
ns  
CYC  
CH  
Clock LOW  
CL  
Output Times  
t
t
t
Data Output Valid After CLK Rise  
Data Output Hold After CLK Rise  
2.6  
2.8  
3.5  
4.0  
ns  
ns  
ns  
CO  
1.0  
0
1.0  
0
1.5  
0
1.5  
0
DOH  
CLZ  
Clock to Low-Z  
t
t
t
t
2.6  
2.6  
2.8  
2.8  
3.5  
3.5  
4.0  
4.5  
ns  
ns  
ns  
ns  
Clock to High-Z  
CHZ  
OE LOW to Output Valid  
OEV  
0
0
0
0
OE LOW to Output Low-Z  
OELZ  
OEHZ  
2.6  
2.8  
3.5  
4.0  
OE HIGH to Output High-Z  
Setup Times  
t
t
Address Setup Before CLK Rise  
ADSC, ADSP Setup Before CLK Rise  
ADV Setup Before CLK Rise  
1.2  
1.2  
1.2  
1.2  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
AS  
ADS  
t
t
1.2  
1.2  
1.2  
1.2  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
ADVS  
WES  
GW, BWE, BW Setup Before CLK Rise  
X
t
t
Data Input Setup Before CLK Rise  
Chip Enable Setup Before CLK Rise  
1.2  
1.2  
1.2  
1.2  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
DS  
CES  
Hold Times  
t
t
Address Hold After CLK Rise  
ADSP, ADSC Hold After CLK Rise  
ADV Hold After CLK Rise  
0.3  
0.3  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
AH  
ADH  
t
0.3  
0.3  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ADVH  
WEH  
t
GW, BWE, BW Hold After CLK Rise  
X
t
t
Data Input Hold After CLK Rise  
Chip Enable Hold After CLK Rise  
0.3  
0.3  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
DH  
CEH  
Notes  
10. This part has an internal voltage regulator; t  
is the time that the power must be supplied above V (min) initially before a read or write operation can be initiated.  
DD  
POWER  
11. t  
, t  
, t  
, and t  
are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms on page 10. Transition is measured ±200 mV  
CHZ CLZ OELZ  
OEHZ  
from steady-state voltage.  
12. At any voltage and temperature, t  
is less than t  
and t  
is less than t  
to eliminate bus contention between SRAMs when sharing the same data bus.  
OEHZ  
OELZ  
CHZ  
CLZ  
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z  
before Low-Z under the same system conditions.  
13. This parameter is sampled and not 100% tested.  
14. Timing references level is 1.5V when V  
= 3.3V and is 1.25V when V  
= 2.5V on all data sheets.  
DDQ  
DDQ  
15. Test conditions shown in (a) of AC Test Loads and Waveforms on page 10 unless otherwise noted.  
Document #: 38-05516 Rev. *F  
Page 11 of 22  
           
CY7C1347G  
Switching Waveforms  
Figure 5. Read Cycle Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC  
t
t
ADH  
ADS  
t
t
AH  
AS  
A1  
A2  
A3  
ADDRESS  
Burst continued with  
new base address  
t
t
WEH  
WES  
GW, BWE,  
BW [A:D]  
Deselect  
cycle  
t
t
CEH  
CES  
CE  
t
t
ADVH  
ADVS  
ADV  
OE  
ADV  
suspends  
burst.  
t
t
OEV  
CO  
t
t
OEHZ  
t
t
CHZ  
OELZ  
DOH  
t
CLZ  
t
Q(A2)  
Q(A2  
+
1)  
Q(A2  
+
2)  
Q(A2  
+
3)  
Q(A2)  
Q(A2  
+
1)  
Q(A1)  
Data Out (Q)  
High-Z  
CO  
Burst wraps around  
to its initial state  
Single READ  
BURST READ  
DON’T CARE  
UNDEFINED  
Note  
16. In this diagram, when CE is LOW, CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH, CE is HIGH, CE is LOW, or CE is HIGH.  
1
2
3
1
2
3
Document #: 38-05516 Rev. *F  
Page 12 of 22  
 
CY7C1347G  
Switching Waveforms (continued)  
Figure 6. Write Cycle Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC extends burst  
t
t
ADH  
ADS  
t
t
ADH  
ADS  
ADSC  
t
t
AH  
AS  
A1  
A2  
A3  
ADDRESS  
Byte write signals are  
ignored for first cycle when  
ADSP initiates burst  
t
t
WEH  
WES  
BWE,  
BW[A :B]  
t
t
WEH  
WES  
GW  
CE  
t
t
CEH  
CES  
t
t
ADVH  
ADVS  
ADV  
OE  
ADV suspends burst  
t
t
DH  
DS  
Data In (D)  
D(A2)  
D(A2  
+
1)  
D(A2  
+
1)  
D(A2  
+
2)  
D(A2  
+
3)  
D(A3)  
D(A3  
+
1)  
D(A3  
+
2)  
D(A1)  
High-Z  
t
OEHZ  
Data Out (Q)  
BURST READ  
Single WRITE  
BURST WRITE  
Extended BURST WRITE  
DON’T CARE  
UNDEFINED  
Note  
17. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BW LOW.  
x
Document #: 38-05516 Rev. *F  
Page 13 of 22  
 
CY7C1347G  
Switching Waveforms (continued)  
Figure 7. Read/Write Cycle Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC  
t
t
AH  
AS  
A1  
A2  
A3  
A4  
A5  
A6  
ADDRESS  
t
t
WEH  
WES  
BWE,  
BW[A:D]  
t
t
CEH  
CES  
CE  
ADV  
OE  
t
t
DH  
t
CO  
DS  
t
OELZ  
Data In (D)  
High-Z  
D(A3)  
D(A5)  
D(A6)  
t
t
OEHZ  
CLZ  
Data Out (Q)  
Q(A1)  
Q(A2)  
Q(A4)  
Q(A4+1)  
Q(A4+2)  
Q(A4+3)  
High-Z  
Back-to-Back READs  
Single WRITE  
BURST READ  
Back-to-Back  
WRITEs  
DON’T CARE  
UNDEFINED  
Notes  
18. The data bus (Q) remains in High-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.  
19. GW is HIGH.  
Document #: 38-05516 Rev. *F  
Page 14 of 22  
   
CY7C1347G  
Switching Waveforms (continued)  
Figure 8. ZZ Mode Timing  
CLK  
t
t
ZZ  
ZZREC  
ZZ  
t
ZZI  
I
SUPPLY  
I
DDZZ  
t
RZZI  
ALL INPUTS  
(except ZZ)  
DESELECT or READ Only  
Outputs (Q)  
High-Z  
DON’T CARE  
Notes  
20. Device must be deselected when entering ZZ mode. See Table 5 on page 7 for all possible signal conditions to deselect the device.  
21. DQs are in high-Z when exiting ZZ sleep mode.  
Document #: 38-05516 Rev. *F  
Page 15 of 22  
   
CY7C1347G  
Ordering Information  
The following table lists all possible speed, package and temperature range options supported for these devices. Note that some  
options listed may not be available for order entry. To verify the availability of a specific option, visit the Cypress website at  
www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales  
representative for the status of availability of parts.  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office  
Table 7. Ordering Information  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
133  
166  
200  
CY7C1347G-133AXC  
CY7C1347G-133BGC  
CY7C1347G-133BGXC  
CY7C1347G-133BZC  
CY7C1347G-133BZXC  
CY7C1347G-133AXI  
CY7C1347G-133BGI  
CY7C1347G-133BGXI  
CY7C1347G-133BZI  
CY7C1347G-133BZXI  
CY7C1347G-166AXC  
CY7C1347G-166BGC  
CY7C1347G-166BGXC  
CY7C1347G-166BZC  
CY7C1347G-166BZXC  
CY7C1347G-166AXI  
CY7C1347G-166BGI  
CY7C1347G-166BGXI  
CY7C1347G-166BZI  
CY7C1347G-166BZXI  
CY7C1347G-200AXC  
CY7C1347G-200BGC  
CY7C1347G-200BGXC  
CY7C1347G-200BZC  
CY7C1347G-200BZXC  
CY7C1347G-200AXI  
CY7C1347G-200BGI  
CY7C1347G-200BGXI  
CY7C1347G-200BZI  
CY7C1347G-200BZXI  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm)  
Commercial  
119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free  
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm)  
Industrial  
119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free  
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm)  
Commercial  
Industrial  
119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free  
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm)  
119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free  
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm)  
Commercial  
Industrial  
119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free  
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm)  
119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free  
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
Document #: 38-05516 Rev. *F  
Page 16 of 22  
CY7C1347G  
Table 7. Ordering Information (continued)  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
250  
CY7C1347G-250AXC  
CY7C1347G-250BGC  
CY7C1347G-250BGXC  
CY7C1347G-250BZC  
CY7C1347G-250BZXC  
CY7C1347G-250AXI  
CY7C1347G-250BGI  
CY7C1347G-250BGXI  
CY7C1347G-250BZI  
CY7C1347G-250BZXI  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm)  
Commercial  
Industrial  
119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free  
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free  
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm)  
119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free  
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
Document #: 38-05516 Rev. *F  
Page 17 of 22  
CY7C1347G  
Package Diagrams  
Figure 9. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050  
16.00 0.20  
14.00 0.10  
1.40 0.05  
100  
81  
80  
1
0.30 0.08  
0.65  
TYP.  
12° 1°  
(8X)  
SEE DETAIL  
A
30  
51  
31  
50  
0.20 MAX.  
1.60 MAX.  
R 0.08 MIN.  
0.20 MAX.  
0° MIN.  
SEATING PLANE  
STAND-OFF  
0.05 MIN.  
0.15 MAX.  
NOTE:  
1. JEDEC STD REF MS-026  
0.25  
GAUGE PLANE  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE  
R 0.08 MIN.  
0.20 MAX.  
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH  
3. DIMENSIONS IN MILLIMETERS  
0°-7°  
0.60 0.15  
0.20 MIN.  
1.00 REF.  
51-85050 *B  
DETAIL  
A
Document #: 38-05516 Rev. *F  
Page 18 of 22  
CY7C1347G  
Package Diagrams (continued)  
Figure 10. 119-Ball BGA (14 x 22 x 2.4 mm), 51-85115  
51-85115 *B  
Document #: 38-05516 Rev. *F  
Page 19 of 22  
CY7C1347G  
Package Diagrams (continued)  
Figure 11. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180  
BOTTOM VIEW  
PIN 1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
-0.06  
PIN 1 CORNER  
Ø0.50  
(165X)  
+0.14  
1
2
3
4
5
6
7
8
9
10  
11  
11 10  
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00  
5.00  
10.00  
13.00 0.10  
B
13.00 0.10  
B
0.15(4X)  
NOTES :  
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)  
PACKAGE WEIGHT : 0.475g  
JEDEC REFERENCE : MO-216 / DESIGN 4.6C  
PACKAGE CODE : BB0AC  
SEATING PLANE  
C
51-85180 *A  
Document #: 38-05516 Rev. *F  
Page 20 of 22  
CY7C1347G  
Document History Page  
Document Title: CY7C1347G 4-Mbit (128K x 36) Pipelined Sync SRAM  
Document Number: 38-05516  
Submission Orig. of  
REV.  
ECN  
Description of Change  
Date  
Change  
**  
224364  
276690  
See ECN  
See ECN  
RKF  
New data sheet  
*A  
VBL  
Changed TQFP package in Ordering Information section to lead-free TQFP  
Added comment of BG and BZ lead-free package availability  
*B  
333625  
See ECN  
SYT  
Removed 225 MHz and 100 MHz speed grades  
Modified Address Expansion balls in the pinouts for 100 TQFP Package as per  
JEDEC standards and updated the Pin Definitions accordingly  
Modified V  
V
test conditions  
OL, OH  
Replaced TBDs for Θ and Θ to their respective values on the Thermal Resis-  
JA  
JC  
tance table  
Changed the package name for 100 TQFP from A100RA to A101  
Removed comment on the availability of BG lead-free package  
Updated the Ordering Information by shading and unshading MPNs as per  
availability  
*C  
419256  
See ECN  
RXU  
Converted from Preliminary to Final.  
Changed address of Cypress Semiconductor Corporation on Page #1 from “3901  
North First Street” to “198 Champion Court”  
Swapped typo CE and  
Modified test condition from V < V to V < V  
Modified test condition from V  
in the Truth Table column heading on Page #6  
CE  
2
3
IH  
DD  
IH  
DD.  
< V  
< V to V  
DDQ  
DD  
DDQ DD  
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the  
Electrical Characteristics Table.  
Replaced Package Name column with Package Diagram in the Ordering Infor-  
mation table.  
Replaced Package Diagram of 51-85050 from *A to *B  
Replaced Package Diagram of 51-85180 from ** to *A  
Updated the Ordering Information.  
*D  
480124  
See ECN  
See ECN  
VKN  
VKN  
Added the Maximum Rating for Supply Voltage on V  
Updated the Ordering Information table.  
Relative to GND.  
DDQ  
*E  
*F  
1078184  
Corrected write timing diagram on page 12  
2633279 01/15/2009 NXR/AESA Updated Ordering Information and data sheet template.  
Document #: 38-05516 Rev. *F  
Page 21 of 22  
CY7C1347G  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
© Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document #: 38-05516 Rev. *F  
Revised January 15, 2009  
Page 22 of 22  
All products and company names mentioned in this document may be the trademarks of their respective holders.  

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