Cypress CY7C1346H User Manual

CY7C1346H  
2-Mbit (64K x 36) Pipelined Sync SRAM  
Features  
Functional Description[1]  
• Registered inputs and outputs for pipelined operation  
• 64K × 36 common I/O architecture  
• 3.3V core power supply  
The CY7C1346H SRAM integrates 64K x 36 SRAM cells with  
advanced synchronous peripheral circuitry and a two-bit  
counter for internal burst operation. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
• 3.3V/2.5V I/O operation  
• Fast clock-to-output times  
(
), depth-expansion Chip Enables (CE and  
), Burst  
CE  
3
CE  
2
1
— 3.5 ns (166-MHz device)  
Control inputs (  
,
,
), Write Enables  
and  
ADV  
), and Global Write (  
BWE  
ADSC ADSP  
(
, and  
). Asynchronous  
GW  
BW  
• Provide high-performance 3-1-1-1 access rate  
[A:D]  
inputs include the Output Enable ( ) and the ZZ pin.  
OE  
®
• User-selectable burst counter supporting Intel  
Addresses and chip enables are registered at rising edge of  
®
Pentium interleaved or linear burst sequences  
clock when either Address Strobe Processor (  
) or  
ADSP  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
Address Strobe Controller (  
burst addresses can be internally generated as controlled by  
the Advance pin ( ).  
) are active. Subsequent  
ADSC  
ADV  
• Asynchronous output enable  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to four bytes wide as  
• Offered in JEDEC-standard lead-free 100-pin TQFP  
package  
• “ZZ” Sleep Mode Option  
controlled by the Byte Write control inputs.  
when active  
GW  
causes all bytes to be written.  
LOW  
The CY7C1346H operates from a +3.3V core power supply  
while all outputs also operate with either a +3.3V/2.5V supply.  
All  
inputs  
and  
outputs  
are  
JEDEC-standard  
JESD8-5-compatible.  
Logic Block Diagram  
A0, A1, A  
ADDRESS  
REGISTER  
2
A[1:0]  
Q1  
MODE  
ADV  
CLK  
BURST  
COUNTER  
AND  
CLR  
Q0  
LOGIC  
ADSC  
ADSP  
DQD,DQD  
BYTE  
WRITE REGISTER  
DQD ,DQPD  
BYTE  
WRITE DRIVER  
BWD  
BWC  
DQC ,DQPC  
BYTE  
WRITE DRIVER  
DQC,DQPC  
BYTE  
WRITE REGISTER  
DQs  
OUTPUT  
BUFFERS  
DQPA  
DQPB  
DQPC  
DQPD  
OUTPUT  
REGISTERS  
MEMORY  
ARRAY  
SENSE  
AMPS  
DQB,DQPB  
BYTE  
WRITE DRIVER  
E
DQB,DQPB  
BYTE  
WRITE REGISTER  
BWB  
DQA,DQPA  
BYTE  
WRITE DRIVER  
DQA ,DQPA  
BYTE  
WRITE REGISTER  
BWA  
BWE  
INPUT  
REGISTERS  
GW  
CE1  
CE2  
CE3  
OE  
ENABLE  
REGISTER  
PIPELINED  
ENABLE  
SLEEP  
CONTROL  
ZZ  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05672 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 26, 2006  
CY7C1346H  
Pin Definitions  
Name  
I/O  
Description  
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge  
A , A , A  
Input-  
0
1
Synchronous of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. A , A  
1
2
3
1
0
feed the 2-bit counter.  
BW ,BW  
Input- Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM.  
Synchronous Sampled on the rising edge of CLK.  
A
B
BW ,BW  
C
D
GW  
Input-  
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global  
Synchronous Write is conducted (ALL bytes are written, regardless of the values on BW  
and BWE).  
[A:D]  
BWE  
CLK  
Input-  
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be  
Synchronous asserted LOW to conduct a Byte Write.  
Input-  
Clock  
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst  
counter when ADV is asserted LOW, during a burst operation.  
CE  
CE  
CE  
Input-  
Synchronous  
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with  
1
2
3
CE  
and CE to select/deselect the device. ADSP is ignored if CE is HIGH. CE is sampled only  
2
3
1
1
when a new external address is loaded.  
Input-  
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with  
Synchronous CE and CE to select/deselect the device. CE  
is sampled only when a new external address is  
1
3
2
loaded.  
Input-  
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with  
Synchronous CE and CE to select/deselect the device. CE is sampled only when a new external address is  
1
2
3
loaded.  
OE  
Input-  
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When  
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as  
input data pins. OE is masked during the first clock of a Read cycle when emerging from a  
deselected state.  
ADV  
Input-  
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it  
Synchronous automatically increments the address in a burst cycle.  
ADSP  
Input- Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When  
Synchronous asserted LOW, A is captured in the address registers. A , A are also loaded into the burst counter.  
1
0
When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE  
1
is deasserted HIGH.  
ADSC  
ZZ  
Input-  
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When  
Synchronous asserted LOW, A is captured in the address registers. A , A are also loaded into the burst counter.  
1
0
When ADSP and ADSC are both asserted, only ADSP is recognized.  
Input-  
ZZ “Sleep” Input, active HIGH. This input, when HIGH places the device in a non-time-critical  
Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left  
floating. ZZ pin has an internal pull-down.  
DQ DQ  
I/O-  
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by  
A,  
B
DQ DQ  
Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified  
by “A” during the previous clock rise of the Read cycle. The direction of the pins is controlled by OE.  
When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs are placed  
in a tri-state condition.  
C,  
D,  
DQP ,  
A
DQP  
B
DQP ,DQP  
C
V
Power Supply Power supply inputs to the core of the device.  
DD  
SS  
V
Ground  
Ground for the core of the device.  
Document #: 38-05672 Rev. *B  
Page 3 of 16  
CY7C1346H  
Pin Definitions (continued)  
Name  
I/O  
Description  
V
V
I/O Power Power supply for the I/O circuitry.  
Supply  
DDQ  
I/O Ground Ground for the I/O circuitry.  
SSQ  
MODE  
Input-  
Static  
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V or left  
floating selects interleaved burst sequence. This is a strap pin and should remain static during  
device operation. Mode Pin has an internal pull-up.  
DD  
NC  
No Connects. Not internally connected to the die. 4M, 9M,18M, 72M, 144M, 288M, 576M and 1G  
are address expansion pins and are not internally connected to the die.  
Single Write Accesses Initiated by ADSP  
Functional Overview  
This access is initiated when both of the following conditions  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock.  
are satisfied at clock rise: (1) ADSP is asserted LOW, and  
(2) CE , CE , CE are all asserted active. The address  
1
2
3
presented to A is loaded into the address register and the  
The CY7C1346H supports secondary cache in systems  
utilizing either a linear or interleaved burst sequence. The  
interleaved burst order supports Pentium and i486™  
processors. The linear burst sequence is suited for processors  
that utilize a linear burst sequence. The burst order is user  
selectable, and is determined by sampling the MODE input.  
Accesses can be initiated with either the Processor Address  
Strobe (ADSP) or the Controller Address Strobe (ADSC).  
Address advancement through the burst sequence is  
controlled by the ADV input. A two-bit on-chip wraparound  
burst counter captures the first address in a burst sequence  
and automatically increments the address for the rest of the  
burst access.  
address advancement logic while being delivered to the RAM  
array. The Write signals (GW, BWE, and BW  
inputs are ignored during this first cycle.  
) and ADV  
[A:D]  
ADSP-triggered Write accesses require two clock cycles to  
complete. If GW is asserted LOW on the second clock rise, the  
data presented to the DQ inputs is written into the corre-  
sponding address location in the memory array. If GW is HIGH,  
then the Write operation is controlled by BWE and BW  
[A:D]  
signals. The CY7C1346H provides Byte Write capability that  
is described in the Write Cycle Descriptions table. Asserting  
the Byte Write Enable input (BWE) with the selected Byte  
Write (BW  
) input, will selectively write to only the desired  
[A:D]  
bytes. Bytes not selected during a Byte Write operation will  
remain unaltered. A synchronous self-timed Write mechanism  
has been provided to simplify the Write operations.  
Byte Write operations are qualified with the Byte Write Enable  
(BWE) and Byte Write Select (BW  
) inputs. A Global Write  
[A:D]  
Enable (GW) overrides all Byte Write inputs and writes data to  
all four bytes. All writes are simplified with on-chip  
synchronous self-timed Write circuitry.  
Because the CY7C1346H is a common I/O device, the Output  
Enable (OE) must be deasserted HIGH before presenting data  
to the DQ inputs. Doing so will tri-state the output drivers. As  
a safety precaution, DQ are automatically tri-stated whenever  
a Write cycle is detected, regardless of the state of OE.  
Three synchronous Chip Selects (CE , CE , CE ) and an  
1
2
3
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. ADSP is ignored if CE  
is HIGH.  
1
Single Write Accesses Initiated by ADSC  
ADSC Write accesses are initiated when the following condi-  
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is  
Single Read Accesses  
This access is initiated when the following conditions are  
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)  
deasserted HIGH, (3) CE , CE , CE are all asserted active,  
1
2
3
and (4) the appropriate combination of the Write inputs (GW,  
CE , CE , CE are all asserted active, and (3) the Write  
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored  
BWE, and BW ) are asserted active to conduct a Write to  
1
2
3
[A:D]  
the desired byte(s). ADSC-triggered Write accesses require a  
single clock cycle to complete. The address presented to A is  
loaded into the address register and the address  
advancement logic while being delivered to the memory array.  
The ADV input is ignored during this cycle. If a global Write is  
conducted, the data presented to DQ is written into the corre-  
sponding address location in the memory core. If a Byte Write  
is conducted, only the selected bytes are written. Bytes not  
selected during a Byte Write operation will remain unaltered.  
A synchronous self-timed Write mechanism has been  
provided to simplify the Write operations.  
if CE is HIGH. The address presented to the address inputs  
1
(A) is stored into the address advancement logic and the  
address register while being presented to the memory array.  
The corresponding data is allowed to propagate to the input of  
the output registers. At the rising edge of the next clock the  
data is allowed to propagate through the output register and  
onto the data bus within t  
if OE is active LOW. The only  
CO  
exception occurs when the SRAM is emerging from a  
deselected state to a selected state, its outputs are always  
tri-stated during the first cycle of the access. After the first cycle  
of the access, the outputs are controlled by the OE signal.  
Consecutive single Read cycles are supported. Once the  
SRAM is deselected at clock rise by the chip select and either  
ADSP or ADSC signals, its output will tri-state immediately.  
Because the CY7C1346H is a common I/O device, the Output  
Enable (OE) must be deserted HIGH before presenting data  
to the DQ inputs. Doing so will tri-state the output drivers. As  
a safety precaution, DQs are automatically tri-stated whenever  
a Write cycle is detected, regardless of the state of OE.  
Document #: 38-05672 Rev. *B  
Page 4 of 16  
CY7C1346H  
Burst Sequences  
Interleaved Burst Address Table  
(MODE = Floating or VDD  
)
The CY7C1346H provides a two-bit wraparound counter, fed  
by A , A , that implements either an interleaved or linear burst  
First  
Second  
Third  
Fourth  
1
0
sequence. The interleaved burst sequence is designed specif-  
ically to support Intel Pentium applications. The linear burst  
sequence is designed to support processors that follow a  
linear burst sequence. The burst sequence is user selectable  
through the MODE input.  
Address  
Address  
Address  
Address  
A , A  
A , A  
A , A  
A , A  
1
0
1
0
1
0
1
0
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
Asserting ADV LOW at clock rise will automatically increment  
the burst counter to the next address in the burst sequence.  
Both Read and Write burst operations are supported.  
Sleep Mode  
Linear Burst Address Table (MODE = GND)  
The ZZ input pin is an asynchronous input. Asserting ZZ  
places the SRAM in a power conservation “sleep” mode. Two  
clock cycles are required to enter into or exit from this “sleep”  
mode. While in this mode, data integrity is guaranteed.  
Accesses pending when entering the “sleep” mode are not  
considered valid nor is the completion of the operation  
guaranteed. The device must be deselected prior to entering  
First  
Second  
Third  
Fourth  
Address  
Address  
Address  
Address  
A , A  
A , A  
A , A  
A , A  
1
0
1
0
1
0
1
0
00  
01  
10  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
the “sleep” mode. CE , CE , CE , ADSP, and ADSC must  
1
2
3
remain inactive for the duration of t  
after the ZZ input  
ZZREC  
returns LOW.  
ZZ Mode Electrical Characteristics  
Parameter  
Description  
Sleep mode standby current  
Device operation to ZZ  
Test Conditions  
ZZ > V – 0.2V  
Min.  
Max.  
Unit  
mA  
ns  
I
t
t
t
t
40  
DDZZ  
DD  
ZZ > V – 0.2V  
2t  
ZZS  
DD  
CYC  
CYC  
ZZ recovery time  
ZZ < 0.2V  
2t  
ns  
ZZREC  
ZZI  
CYC  
ZZ Active to sleep current  
ZZ Inactive to exit sleep current  
This parameter is sampled  
This parameter is sampled  
2t  
ns  
0
ns  
RZZI  
Document #: 38-05672 Rev. *B  
Page 5 of 16  
CY7C1346H  
Truth Table [2, 3, 4, 5, 6, 7]  
Next Cycle  
Add. Used CE  
CE  
CE  
3
ZZ  
ADSP  
ADSC  
ADV WRITE  
OE  
CLK  
DQ  
1
2
Deselect Cycle,  
Power-down  
None  
H
X
X
L
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
L-H Tri-State  
L-H Tri-State  
L-H Tri-State  
L-H Tri-State  
L-H Tri-State  
Deselect Cycle,  
Power-down  
None  
L
L
X
L
X
H
X
H
X
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
X
X
X
X
X
L
Deselect Cycle,  
Power-down  
None  
L
Deselect Cycle,  
Power-down  
None  
L
H
H
X
L
Deselect Cycle,  
Power-down  
None  
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
L
Sleep Mode,  
Power-down  
None  
X
L
X
X
X
L
X
Tri-State  
Q
READ Cycle,  
Begin Burst  
External  
External  
External  
External  
External  
Next  
L-H  
READ Cycle,  
Begin Burst  
L
L
L
H
X
L
L-H Tri-State  
WRITE Cycle,  
Begin Burst  
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
L-H  
L-H  
D
Q
READ Cycle,  
Begin Burst  
L
L
L
H
H
H
H
H
H
L
READ Cycle,  
Begin Burst  
L
L
L
H
L
L-H Tri-State  
L-H  
L-H Tri-State  
L-H  
L-H Tri-State  
READ Cycle,  
Continue Burst  
X
X
H
H
X
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
Q
READ Cycle,  
Continue Burst  
Next  
L
H
L
READ Cycle,  
Continue Burst  
Next  
L
Q
READ Cycle,  
Continue Burst  
Next  
L
H
X
X
L
WRITE Cycle,  
Continue Burst  
Next  
L
L-H  
L-H  
L-H  
D
D
Q
WRITE Cycle,  
Continue Burst  
Next  
L
L
READ Cycle,  
Suspend Burst  
Current  
Current  
Current  
Current  
H
H
H
H
H
H
H
H
READ Cycle,  
Suspend Burst  
H
L
L-H Tri-State  
L-H  
L-H Tri-State  
READ Cycle,  
Suspend Burst  
Q
READ Cycle,  
H
Suspend Burst  
Notes:  
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.  
3. WRITE = L when any one or more Byte Write Enable signals (BW ,BW ,BW ,BW and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals  
)
D
A
B
C
(BW ,BW ,BW ,BW ), BWE, GW = H.  
A
B
C
D
4. The DQ pins are controlled by the current cycle and the  
signal.  
is asynchronous and is not sampled with the clock.  
OE  
OE  
5. CE , CE , and CE are available only in the TQFP package.  
1
2
3
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW  
. Writes may occur only on subsequent clocks  
[A:D]  
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Tri-State. OE is a  
don't care for the remainder of the Write cycle  
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE  
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).  
Document #: 38-05672 Rev. *B  
Page 6 of 16  
CY7C1346H  
[2, 3, 4, 5, 6, 7]  
Truth Table (continued)  
Next Cycle  
Add. Used CE  
CE  
CE  
3
ZZ  
ADSP  
ADSC  
ADV WRITE  
OE  
CLK  
DQ  
1
2
WRITE Cycle,  
Suspend Burst  
Current  
X
X
X
L
H
H
H
L
X
L-H  
D
WRITE Cycle,  
Suspend Burst  
Current  
H
X
X
L
X
H
H
L
X
L-H  
D
Truth Table for Read/Write[2, 3]  
Function  
GW  
BWE  
BW  
BW  
BW  
BW  
A
D
C
B
Read  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
X
H
H
H
H
H
H
H
H
L
X
X
H
H
L
X
H
L
Read  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
H
H
H
L
Write Byte A – (DQ and DQP )  
A
A
Write Byte B – (DQ and DQP )  
H
L
B
B
Write Bytes B, A  
Write Byte C – (DQ and DQP )  
L
H
H
L
H
L
C
C
Write Bytes C, A  
Write Bytes C, B  
Write Bytes C, B, A  
L
L
H
L
L
L
Write Byte D – (DQ and DQP )  
H
H
H
H
L
H
H
L
H
L
D
D
Write Bytes D, A  
Write Bytes D, B  
Write Bytes D, B, A  
Write Bytes D, C  
L
L
H
L
L
L
L
H
H
L
H
L
Write Bytes D, C, A  
Write Bytes D, C, B  
Write All Bytes  
L
L
L
L
H
L
L
L
L
Write All Bytes  
X
X
X
X
Document #: 38-05672 Rev. *B  
Page 7 of 16  
CY7C1346H  
DC Input Voltage ................................... –0.5V to V + 0.5V  
Maximum Ratings  
DD  
Current into Outputs (LOW)......................................... 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage........................................... >2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature .................................65°C to +150°C  
Latch-up Current..................................................... >200 mA  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Operating Range  
Supply Voltage on V Relative to GND........ –0.5V to +4.6V  
DD  
Ambient  
Range  
Temperature  
V
V
DDQ  
Supply Voltage on V  
Relative to GND ......0.5V to +V  
DD  
DD  
DDQ  
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V –5%  
DC Voltage Applied to Outputs  
in Tri-State........................................... –0.5V to V  
to V  
+ 0.5V  
DD  
Industrial  
-40°C to +85°C  
DDQ  
[8, 9]  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Power Supply Voltage  
I/O Supply Voltage  
Test Conditions  
Min.  
Max.  
Unit  
V
V
3.135  
3.135  
2.375  
2.4  
3.6  
DD  
V
V
V
V
V
I
for 3.3V I/O  
for 2.5V I/O  
V
V
DDQ  
DD  
2.625  
Output HIGH Voltage  
Output LOW Voltage  
for 3.3V I/O, I = –4.0 mA  
V
V
OH  
OL  
IH  
OH  
for 2.5V I/O, I = –1.0 mA  
2.0  
OH  
for 3.3V I/O, I = 8.0 mA  
0.4  
0.4  
OL  
for 2.5V I/O, I = 1.0 mA  
OL  
[8]  
Input HIGH Voltage  
for 3.3V I/O  
for 2.5V I/O  
for 3.3V I/O  
for 2.5V I/O  
GND V V  
2.0  
1.7  
V
+ 0.3V  
V
V
DD  
V
+ 0.3V  
DD  
[8]  
Input LOW Voltage  
–0.3  
–0.3  
–5  
0.8  
V
IL  
0.7  
5
V
Input Leakage Current  
except ZZ and MODE  
µA  
X
I
DDQ  
Input Current of MODE  
Input = V  
Input = V  
Input = V  
Input = V  
–30  
–5  
µA  
µA  
µA  
µA  
µA  
mA  
SS  
DD  
SS  
DD  
5
Input Current of ZZ  
30  
5
I
I
Output Leakage Current  
GND V V  
Output Disabled  
–5  
OZ  
I
DDQ,  
V
Operating Supply Current  
V
f = f  
= Max., I  
= 0 mA,  
240  
DD  
DD  
DD  
OUT  
= 1/t  
CYC  
MAX  
I
I
I
I
Automatic CS Power-down  
Current—TTL Inputs  
V
= Max, Device Deselected, V V or  
100  
40  
mA  
mA  
mA  
mA  
SB1  
SB2  
SB3  
SB4  
DD  
V , f = f  
IN  
IH  
V
= 1/t  
IN  
IL  
MAX CYC  
Automatic CS Power-down  
Current—CMOS Inputs  
V
= Max, Device Deselected, V 0.3V or  
DD IN  
V
> V  
– 0.3V, f = 0  
IN  
DDQ  
Automatic CS Power-down  
Current—CMOS Inputs  
V
= Max, Device Deselected, or V 0.3V  
85  
DD  
IN  
or V > V  
– 0.3V, f = f  
= 1/t  
IN  
DDQ  
MAX CYC  
Automatic CS Power-down  
Current—TTL Inputs  
V
V
= Max, Device Deselected, V V or  
45  
DD  
IN  
IH  
V , f = 0  
IN  
IL  
/2), undershoot: V (AC) > –2V (Pulse width less than t /2).  
CYC  
Notes:  
8. Overshoot: V (AC) < V +1.5V (Pulse width less than t  
IH  
DD  
CYC  
IL  
9. T  
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V  
< V  
.
Power-up  
DD  
IH  
DD  
DDQ  
DD  
Document #: 38-05672 Rev. *B  
Page 8 of 16  
CY7C1346H  
Capacitance[10]  
100 TQFP  
Parameter  
Description  
Input Capacitance  
Test Conditions  
Max.  
Unit  
pF  
C
T = 25°C, f = 1 MHz,  
5
5
5
IN  
A
V
= 3.3V.  
DD  
C
Clock Input Capacitance  
Input/Output Capacitance  
pF  
CLK  
I/O  
V
= 2.5V  
DDQ  
C
pF  
Thermal Resistance[10]  
100 TQFP  
Package  
Parameter  
Description  
Test Conditions  
Unit  
Θ
Θ
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard test  
methods and procedures for measuring  
thermal impedance, per EIA/JESD51  
30.32  
°C/W  
JA  
Thermal Resistance  
(Junction to Case)  
6.85  
°C/W  
JC  
AC Test Loads and Waveforms  
3.3V I/O Test Load  
R = 317Ω  
3.3V  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
OUTPUT  
90%  
10%  
Z = 50Ω  
0
R = 50Ω  
10%  
L
GND  
5 pF  
R = 351Ω  
1 ns  
1 ns  
V = 1.5V  
L
INCLUDING  
JIG AND  
SCOPE  
(c)  
(a)  
(b)  
2.5V I/O Test Load  
R = 1667Ω  
2.5V  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
OUTPUT  
90%  
10%  
Z = 50Ω  
0
R = 50Ω  
10%  
L
5 pF  
R =1538Ω  
1 ns  
1 ns  
INCLUDING  
V = 1.25V  
T
JIG AND  
SCOPE  
(a)  
(b)  
(c)  
Note:  
10. Tested initially and after any design or process change that may affect these parameters.  
Document #: 38-05672 Rev. *B  
Page 9 of 16  
CY7C1346H  
[11, 12]  
Switching Characteristics Over the Operating Range  
-166  
Parameter  
Description  
Min.  
Max.  
Unit  
[13]  
t
V
(Typical) to the First Access  
1
ms  
POWER  
DD  
Clock  
t
t
t
Clock Cycle Time  
Clock HIGH  
6.0  
2.5  
2.5  
ns  
ns  
ns  
CYC  
CH  
Clock LOW  
CL  
Output Times  
t
t
t
t
t
t
t
Data Output Valid after CLK Rise  
Data Output Hold after CLK Rise  
3.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CO  
1.5  
0
DOH  
CLZ  
[14, 15, 16]  
Clock to Low-Z  
[14, 15, 16]  
Clock to High-Z  
3.5  
3.5  
CHZ  
OEV  
OELZ  
OEHZ  
OE LOW to Output Valid  
[14, 15, 16]  
OE LOW to Output Low-Z  
0
[14, 15, 16]  
OE HIGH to Output High-Z  
3.5  
Set-up Times  
t
t
t
t
t
t
Address Set-up before CLK Rise  
ADSC, ADSP Set-up before CLK Rise  
ADV Set-up before CLK Rise  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
ns  
ns  
ns  
ns  
AS  
ADS  
ADVS  
WES  
DS  
GW, BWE, BW  
Set-up before CLK Rise  
[A:D]  
Data Input Set-up before CLK Rise  
Chip Enable Set-Up before CLK Rise  
CES  
Hold Times  
t
t
t
t
t
t
Address Hold after CLK Rise  
ADSP, ADSC Hold after CLK Rise  
ADV Hold after CLK Rise  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
AH  
ADH  
ADVH  
WEH  
DH  
GW, BWE, BW  
Hold after CLK Rise  
[A:D]  
Data Input Hold after CLK Rise  
Chip Enable Hold after CLK Rise  
CEH  
Notes:  
11. Timing reference level is 1.5V when V  
= 3.3V and 1.25V when V  
= 2.5V.  
DDQ  
DDQ  
12. Test conditions shown in (a) of AC Test Loads unless otherwise noted.  
13. This part has a voltage regulator internally; t  
is the time that the power needs to be supplied above V (minimum) initially before a Read or Write operation  
POWER  
DD  
can be initiated.  
14. t  
, t  
, t  
, and t  
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.  
CHZ CLZ OELZ  
OEHZ  
15. At any given voltage and temperature, t  
is less than t  
and t  
is less than t  
to eliminate bus contention between SRAMs when sharing the same  
CLZ  
OEHZ  
OELZ  
CHZ  
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed  
to achieve High-Z prior to Low-Z under the same system conditions.  
16. This parameter is sampled and not 100% tested.  
Document #: 38-05672 Rev. *B  
Page 10 of 16  
CY7C1346H  
Switching Waveforms  
[17]  
Read Cycle Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC  
t
t
ADH  
ADS  
t
t
AH  
AS  
A1  
A2  
A3  
ADDRESS  
Burst continued with  
new base address  
t
t
WEH  
WES  
GW, BWE,  
BW[A:D]  
Deselect  
cycle  
t
t
CEH  
CES  
CE  
t
t
ADVH  
ADVS  
ADV  
OE  
ADV  
suspends  
burst.  
t
t
OEV  
CO  
t
t
OEHZ  
t
t
CHZ  
OELZ  
DOH  
t
CLZ  
t
Q(A2)  
Q(A2 + 1)  
Q(A2 + 2)  
Q(A2 + 3)  
Q(A2)  
Q(A2 + 1)  
Q(A1)  
Data Out (Q)  
High-Z  
CO  
Burst wraps around  
to its initial state  
Single READ  
BURST READ  
DON’T CARE  
UNDEFINED  
Note:  
17. On this diagram, when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.  
1
2
3
1
2
3
Document #: 38-05672 Rev. *B  
Page 11 of 16  
CY7C1346H  
Switching Waveforms (continued)  
[17, 18]  
Write Cycle Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC extends burst  
t
t
ADH  
ADS  
t
t
ADH  
ADS  
ADSC  
t
t
AH  
AS  
A1  
A2  
A3  
ADDRESS  
Byte write signals are  
ignored for first cycle when  
ADSP initiates burst  
t
t
WEH  
WES  
BWE,  
BW[A :D]  
t
t
WEH  
WES  
GW  
CE  
t
t
CEH  
CES  
t
t
ADVH  
ADVS  
ADV  
OE  
ADV suspends burst  
t
t
DH  
DS  
Data In (D)  
D(A2)  
D(A2 + 1)  
D(A2 + 1)  
D(A2 + 2)  
D(A2 + 3)  
D(A3)  
D(A3 + 1)  
D(A3 + 2)  
D(A1)  
High-Z  
t
OEHZ  
Data Out (Q)  
BURST READ  
Single WRITE  
BURST WRITE  
Extended BURST WRITE  
DON’T CARE  
UNDEFINED  
Note:  
18.  
Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW  
LOW.  
[A:D]  
Document #: 38-05672 Rev. *B  
Page 12 of 16  
CY7C1346H  
Switching Waveforms (continued)  
[17, 19, 20]  
Read/Write Cycle Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC  
t
t
AH  
AS  
A1  
A2  
A3  
A4  
A5  
A6  
ADDRESS  
t
t
WEH  
WES  
BWE,  
BW[A:D]  
t
t
CEH  
CES  
CE  
ADV  
OE  
t
t
DH  
t
CO  
DS  
t
OELZ  
Data In (D)  
High-Z  
High-Z  
D(A3)  
D(A5)  
D(A6)  
t
t
OEHZ  
CLZ  
Data Out (Q)  
Q(A1)  
Q(A2)  
Q(A4)  
Q(A4+1)  
Q(A4+2)  
Q(A4+3)  
Back-to-Back READs  
Single WRITE  
BURST READ  
Back-to-Back  
WRITEs  
DON’T CARE  
UNDEFINED  
Notes:  
19. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.  
20. GW is HIGH.  
Document #: 38-05672 Rev. *B  
Page 13 of 16  
CY7C1346H  
Switching Waveforms (continued)  
[21, 22]  
ZZ Mode Timing  
CLK  
t
t
ZZ  
ZZREC  
ZZ  
t
ZZI  
I
SUPPLY  
I
DDZZ  
t
RZZI  
ALL INPUTS  
(except ZZ)  
DESELECT or READ Only  
Outputs (Q)  
High-Z  
DON’T CARE  
Notes:  
21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.  
22. DQs are in High-Z when exiting ZZ sleep mode.  
Document #: 38-05672 Rev. *B  
Page 14 of 16  
CY7C1346H  
Ordering Information  
“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered”.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
CY7C1346H-166AXC  
CY7C1346H-166AXI  
Package Type  
166  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Commercial  
Industrial  
Package Diagrams  
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)  
16.00 0.20  
14.00 0.10  
1.40 0.05  
100  
81  
80  
1
0.30 0.08  
0.65  
TYP.  
12° 1°  
(8X)  
SEE DETAIL  
A
30  
51  
31  
50  
0.20 MAX.  
1.60 MAX.  
R 0.08 MIN.  
0.20 MAX.  
0° MIN.  
SEATING PLANE  
STAND-OFF  
0.05 MIN.  
0.15 MAX.  
NOTE:  
1. JEDEC STD REF MS-026  
0.25  
GAUGE PLANE  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE  
R 0.08 MIN.  
0.20 MAX.  
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH  
3. DIMENSIONS IN MILLIMETERS  
0°-7°  
0.60 0.15  
0.20 MIN.  
51-85050-*B  
1.00 REF.  
DETAIL  
A
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark  
of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.  
Document #: 38-05672 Rev. *B  
Page 15 of 16  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C1346H  
Document History Page  
Document Title: CY7C1346H 2-Mbit (64K x 36) Pipelined Sync SRAM  
Document Number: 38-05672  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
347357  
420879  
See ECN  
See ECN  
PCI  
New Data sheet  
Converted from Preliminary to Final.  
*A  
RXU  
Changed address of Cypress Semiconductor Corporation on Page# 1 from  
“3901 North First Street” to “198 Champion Court”  
Removed 133MHz Speed bin.  
Changed three-state to tri-state.  
Modified test condition from V < V to V < V  
IH  
DD  
IH  
DD  
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the  
Electrical Characteristics Table.  
Replaced Package Name column with Package Diagram in the Ordering  
Information table.  
Replaced Package Diagram of 51-85050 from *A to *B  
*B  
459347  
See ECN  
NXR  
Included 2.5V I/O option  
Updated the Ordering Information table.  
Document #: 38-05672 Rev. *B  
Page 16 of 16  

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