CY7C1345G
4-Mbit (128K x 36) Flow Through Sync SRAM
Features
Functional Description
■ 128K x 36 common IO
The CY7C1345G is a 128K x 36 synchronous cache RAM
designed to interface with high speed microprocessors with
minimum glue logic. The maximum access delay from clock rise
is 6.5 ns (133 MHz version). A two-bit on-chip counter captures
the first address in a burst and increments the address automat-
ically for the rest of the burst access. All synchronous inputs are
gated by registers controlled by a positive edge triggered Clock
Input (CLK). The synchronous inputs include all addresses, all
■ 3.3V core power supply (V
)
DD
■ 2.5V or 3.3V IO supply (V
)
DDQ
■ Fast clock-to-output times
❐ 6.5 ns (133 MHz version)
■ Provide high performance 2-1-1-1 access rate
data inputs, address pipelining Chip Enable (CE ), depth
1
expansion Chip Enables (CE and CE ), Burst Control inputs
■ User selectable burst counter supporting Intel Pentium inter-
leaved or linear burst sequences
2
3
(ADSC, ADSP,
ADV), Write Enables BW and BWE), and
and
(
,
x
Global Write (GW). Asynchronous inputs include the Output
■ Separate processor and controller address strobes
■ Synchronous self-timed write
Enable (OE) and the ZZ pin.
The CY7C1345G enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address Strobe
(ADSC) inputs.
■ Asynchronous output enable
■ Available in Pb-free 100-Pin TQFP package, Pb-free and
non-Pb-free 119-Ball BGA package
■ ZZ Sleep Mode option
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (
are internally generated as controlled by the Advance pin (ADV).
) is active. Subsequent burst addresses
ADSC
The CY7C1345G operates from a +3.3V core power supply
while all outputs operate with either a +2.5 or +3.3V supply. All
inputs and outputs are JEDEC standard JESD8-5 compatible.
For best practice recommendations, refer to the Cypress appli-
Selection Guide
Parameter
Maximum Access Time
133 MHz
6.5
100 MHz
8.0
Unit
ns
Maximum Operating Current
Maximum Standby Current
225
205
mA
mA
40
40
Cypress Semiconductor Corporation
Document Number: 38-05517 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 15, 2007
CY7C1345G
Pin Configurations
100-Pin TQFP Pinout
DQPC
1
DQPB
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
2
DQB
DQB
3
4
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
5
6
7
8
BYTE C
BYTE B
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
NC
CY7C1345G
NC
VDD
ZZ
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
BYTE D
BYTE A
Document Number: 38-05517 Rev. *E
Page 3 of 20
CY7C1345G
Pin Configurations (continued)
119-Ball BGA Pinout
2
1
3
A
A
A
4
5
A
A
A
6
7
A
B
C
D
E
F
V
A
CE
A
A
V
DDQ
ADSP
ADSC
DDQ
NC/288M
NC/144M
NC/576M
NC/1G
CE
A
2
3
V
DD
DQ
DQP
DQ
V
NC
V
DQP
DQ
DQ
C
C
SS
SS
SS
SS
SS
SS
B
B
DQ
V
V
V
V
DQ
CE
C
C
B
B
1
V
DQ
DQ
DQ
DQ
DQ
DQ
V
OE
DDQ
C
B
DDQ
G
H
J
DQ
DQ
BW
V
BW
V
ADV
GW
C
C
C
B
B
B
C
B
DQ
DQ
C
SS
SS
B
V
V
NC
V
NC
V
V
DDQ
DDQ
DD
DD
DD
DQ
DQ
V
CLK
NC
V
DQ
DQ
K
D
D
SS
SS
A
A
L
M
N
DQ
DQ
DQ
DQ
BW
V
BW
DQ
DQ
DQ
DQ
D
D
D
D
D
A
A
A
A
A
V
V
V
V
DDQ
BWE
A1
DDQ
SS
SS
DQ
V
DQ
D
SS
SS
A
P
R
T
DQ
DQP
A
V
A0
V
DQP
A
DQ
D
D
SS
SS
A
NC
NC
MODE
A
V
NC
A
A
NC
ZZ
DD
NC/72M
NC
A
NC/36M
NC
U
V
NC
NC
NC
V
DDQ
DDQ
Document Number: 38-05517 Rev. *E
Page 4 of 20
CY7C1345G
Pin Definitions
Name
IO
Description
Address Inputs Used to Select One of the 128K Address Locations. Sampled at the rising edge
A0, A1, A
Input
Synchronous of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. A feed
1
2
3
[1:0]
the two-bit counter.
BW BW
Input Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
A,
B
BW , BW
C
D
GW
Input
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global
Synchronous write is conducted (ALL bytes are written, regardless of the values on BW
and BWE).
[A:D]
BWE
CLK
Input
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal is asserted
Synchronous LOW to conduct a byte write.
Input Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Input
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
1
2
Synchronous CE and CE to select or deselect the device. ADSP is ignored if CE is HIGH. CE is sampled only
2
3
1
1
when a new external address is loaded.
CE
Input
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE and CE to select or deselect the device. CE is sampled only when a new external address is
1
3
2
loaded.
Input
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
3
Synchronous CE and CE to select or deselect the device. CE is sampled only when a new external address is
1
2
3
loaded.
OE
Input
Output Enable, asynchronous Input, Active LOW. Controls the direction of the IO pins. When
Asynchronous LOW, the IO pins act as outputs. When deasserted HIGH, IO pins are tri-stated and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input
Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically incre-
Synchronous ments the address in a burst cycle.
ADSP
Input
Address Strobe from Processor, sampled on the rising edge of CLK, Active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A
are
[1:0]
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized. ASDP is ignored when CE is deasserted HIGH.
1
ADSC
Input
Address Strobe from Controller, sampled on the rising edge of CLK, Active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A
are
[1:0]
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized.
ZZ
Input
ZZ sleep Input, Active HIGH. When asserted HIGH places the device in a non-time critical sleep
Asynchronous condition with data integrity preserved. During normal operation, this pin is low or left floating. ZZ pin
has an internal pull down.
DQs
DQP DQP
IO
Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by
Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
A,
B
DQP DQP
by the addresses presented during the previous clock rise of the read cycle. The direction of the pins
C,
D
is controlled by
DQP
. When OE is asserted LOW, the pins act as outputs. When HIGH, DQs and
OE
are placed in a tri-state condition.
[A:D]
V
V
V
Power Supply Power supply inputs to the core of the device.
DD
Ground
Ground for the core of the device.
SS
IO Power
Supply
Power supply for the IO circuitry.
DDQ
V
IO Ground Ground for the IO circuitry.
SSQ
Document Number: 38-05517 Rev. *E
Page 5 of 20
CY7C1345G
Pin Definitions (continued)
Name
MODE
IO
Description
Input
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V or left
floating selects interleaved burst sequence. This is a strap pin and must remain static during device
operation. Mode Pin has an internal pull up.
DD
NC
No Connects. Not Internally connected to the die.
NC/9M,
–
No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,
NC/288M, NC/576M, and NC/1G are address expansion pins and are not internally connected to the
die.
NC/18M,
NC/36M
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
Single Write Accesses Initiated by ADSP
Functional Overview
Single write access is initiated when the following conditions are
satisfied at clock rise:
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
1. CE , CE , and CE are all asserted active
1
2
3
clock rise (t ) is 6.5 ns (133 MHz device).
CO
2. ADSP is asserted LOW.
The CY7C1345G supports secondary cache in systems using
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486™ processors. The linear
burst sequence is suited for processors that use a linear burst
sequence. The burst order is user selectable and is determined
by sampling the MODE input. Accesses are initiated with either
the Processor Address Strobe (ADSP) or the Controller Address
Strobe (ADSC). Address advancement through the burst
sequence is controlled by the ADV input. A two-bit on-chip wrap
around burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
The addresses presented are loaded into the address register
and the burst inputs (GW, BWE, and BW ) are ignored during this
first clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data is latched and
written into the device. Byte writes are allowed. During byte
x
writes, BW controls DQ and BW controls DQ , BW controls
A
A
B
B
C
DQ , and BW controls DQ . All IOs are tri-stated during a byte
C
D
D
write. Since this is a common IO device, the asynchronous OE
input signal is deasserted and the IOs are tri-stated prior to the
presentation of data to DQ . As a safety precaution, the data
s
lines are tri-stated once a write cycle is detected, regardless of
the state of OE.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
) inputs. A Global Write
[A:D]
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise:
Three synchronous Chip Selects (CE , CE , and CE ) and an
1
2
3
1. CE , CE , and CE are all asserted active.
asynchronous Output Enable (OE) provide for easy bank
1
2
3
selection and output tri-state control. ADSP is ignored if CE is
HIGH.
2. ADSC is asserted LOW.
3. ADSP is deasserted HIGH
1
4. The write input signals (GW, BWE, and BW ) indicate a write
x
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise:
access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter or control logic and delivered to the
1. CE , CE , and CE are all asserted active.
1
2
3
memory core. The information presented to DQ
is written
[D:A]
2. ADSP or ADSC is asserted LOW (if the access is initiated by
ADSC, the write inputs are deasserted during this first cycle).
into the specified address location. Byte writes are allowed.
During byte writes, BW controls DQ , BW controls DQ , BW
C
A
A
B
B
controls DQ , and BW controls DQ . All IOs and even a byte
The address presented to the address inputs is latched into the
address register and the burst counter or control logic and
presented to the memory core. If the OE input is asserted LOW,
the requested data is available at the data outputs a maximum
C
D
D
write are tri-stated when a write is detected. Since this is a
common IO device, the asynchronous OE input signal is
deasserted and the IOs are tri-stated prior to the presentation of
data to DQs. As a safety precaution, the data lines are tri-stated
to t
after clock rise. ADSP is ignored if CE is HIGH.
CDV
1
once a write cycle is detected, regardless
of the state of OE.
Document Number: 38-05517 Rev. *E
Page 6 of 20
CY7C1345G
Table 2. Linear Burst Address Table (MODE = GND)
Burst Sequences
The CY7C1345G provides an on-chip two-bit wrap around burst
First
Second
Third
Fourth
counter inside the SRAM. The burst counter is fed by A
and
Address
Address
Address
Address
[1:0]
follows either a linear or interleaved burst order. The burst order
is determined by the state of the MODE input. A LOW on MODE
selects a linear burst sequence. A HIGH on MODE selects an
interleaved burst order. Leaving MODE unconnected causes the
device to default to a interleaved burst sequence.
A ,A
A ,A
A ,A
A ,A
1
0
1
0
1
0
1
0
00
01
10
11
01
10
11
10
11
00
11
00
01
00
01
10
Table 1. Interleaved Burst Address Table
(MODE = Floating or V
)
DD
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. In this
mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device is
deselected prior to entering the sleep mode. CEs, ADSP, and
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
ADSC must remain inactive for the duration of t
ZZ input returns LOW.
after the
ZZREC
ZZ Mode Electrical Characteristics
Parameter
Description
Sleep mode standby current
Test Conditions
ZZ > V – 0.2V
Min
Max
40
Unit
mA
ns
I
t
t
t
t
DDZZ
DD
Device operation to ZZ
ZZ recovery time
ZZ > V – 0.2V
2t
ZZS
DD
CYC
ZZ < 0.2V
2t
ns
ZZREC
ZZI
CYC
ZZ Active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2t
ns
CYC
0
ns
RZZI
Document Number: 38-05517 Rev. *E
Page 7 of 20
CY7C1345G
Truth Table
The truth table for CY7C1345G follows.
Address
Used
Cycle Description
CE
CE
CE
3
ZZ
ADSP ADSC ADV WRITE OE CLK
DQ
1
2
Deselected Cycle, Power
down
None
None
None
None
None
H
X
X
L
X
L
L
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L-H
L-H
L-H
L-H
L-H
Tri-State
Deselected Cycle, Power
down
L
L
L
X
L
X
L
X
H
X
X
L
L
L
L
Tri-State
Tri-State
Tri-State
Tri-State
Deselected Cycle, Power
down
L
Deselected Cycle, Power
down
H
H
Deselected Cycle, Power
down
X
Sleep Mode, Power down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
External
External
External
External
External
Next
X
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
X
X
X
L
X
X
X
X
X
X
L
X
X
X
L
X
L
X
Tri-State
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Q
L
L
L
H
X
L
Tri-State
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
D
L
L
L
H
H
H
H
H
H
L
Q
L
L
L
H
L
Tri-State
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Tri-State
Next
L
Q
Next
L
H
X
X
L
Tri-State
Next
L
D
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
Tri-State
Q
H
X
X
Tri-State
D
D
L
Notes
1. X = “Do Not Care,” H = Logic HIGH, and L = Logic LOW.
2. WRITE = L when any one or more Byte Write enable signals (BW , BW , BW , BW ) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BW ,
A
B
C
D
A
BW , BW , BW ), BWE, GW = H.
B
C
D
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks after
[A: D]
the ADSP or with the assertion of ADSC. As a result, OE is driven HIGH prior to the start of the write cycle to enable the outputs to tri-state. OE is a “Do Not Care” for
the remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive
OE
or when the device is deselected, and all data bits behave as output when
is active (LOW).
Document Number: 38-05517 Rev. *E
Page 8 of 20
CY7C1345G
Truth Table for Read or Write
The partial truth table for read or write follows.
Function
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
BW
X
H
H
H
H
H
H
H
H
L
BW
X
H
H
H
H
L
BW
X
H
H
L
BW
A
D
C
B
Read
Read
X
H
L
Write Byte (A, DQP )
L
A
Write Byte (B, DQP )
L
H
L
B
Write Bytes (B, A, DQP , DQP )
L
L
A
B
Write Byte (C, DQP )
L
H
H
L
H
L
C
Write Bytes (C, A, DQP , DQP )
L
L
C
A
Write Bytes (C, B, DQP , DQP )
L
L
H
L
C
B
Write Bytes (C, B, A, DQP , DQP , DQP )
L
L
L
C
B
A
Write Byte (D, DQP )
L
H
H
H
H
L
H
H
L
H
L
D
Write Bytes (D, A, DQP , DQP )
L
L
D
A
Write Bytes (D, B, DQP , DQP )
L
L
H
L
D
A
Write Bytes (D, B, A, DQP , DQP , DQP )
L
L
L
D
B
A
Write Bytes (D, B, DQP , DQP )
L
L
H
H
L
H
L
D
B
Write Bytes (D, B, A, DQP , DQP , DQP )
L
L
L
D
C
A
Write Bytes (D, C, A, DQP , DQP , DQP )
L
L
L
H
L
D
B
A
Write All Bytes
Write All Bytes
L
L
L
L
X
X
X
X
X
Note
6. This table is only a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write is done based on the active byte write.
x
Document Number: 38-05517 Rev. *E
Page 9 of 20
CY7C1345G
DC Input Voltage ................................... –0.5V to V + 0.5V
Maximum Ratings
DD
Current into Outputs (LOW) ........................................ 20 mA
Exceeding the maximum ratings may shorten the battery life of
the device. These user guidelines are not tested.
Static Discharge Voltage
(MIL-STD-883, Method 3015) .................................. >2001V
Latch up Current..................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Supply Voltage on V Relative to GND........–0.5V to +4.6V
Ambient
DD
Range
V
V
DDQ
DD
Temperature
0°C to +70°C
–40°C to +85°C
Supply Voltage on V
Relative to GND.......–0.5V to +V
DD
DDQ
Commercial
Industrial
3.3V
−5%/+10%
2.5V –5%
DC Voltage Applied to Outputs
in tri-state.............................................–0.5V to V
to V
DD
+ 0.5V
DDQ
Electrical Characteristics
Over the Operating Range
Parameter
Description
Power Supply Voltage
IO Supply Voltage
Test Conditions
Min
Max
Unit
V
V
3.135
2.375
2.4
3.6
DD
V
V
V
V
DDQ
OH
DD
Output HIGH Voltage
for 3.3V IO, I = –4.0 mA
V
OH
for 2.5V IO, I = –1.0 mA
2.0
V
OH
V
V
V
I
Output LOW Voltage
Input HIGH Voltage
for 3.3V, IO, I = 8.0 mA
0.4
0.4
V
OL
IH
IL
OL
for 2.5V IO, I = 1.0 mA
V
OL
for 3.3V IO
for 2.5V IO
for 3.3V IO
for 2.5V IO
2.0
1.7
V
V
+ 0.3V
+ 0.3V
0.8
V
V
DD
DD
[7]
Input LOW Voltage
–0.3
–0.3
−5
V
0.7
V
Input Leakage Current except GND ≤ V ≤ V
ZZ and MODE
5
µA
X
I
DDQ
Input Current of MODE
Input = V
Input = V
Input = V
Input = V
–30
–5
µA
µA
SS
DD
SS
DD
5
Input Current of ZZ
µA
30
5
µA
I
I
Output Leakage Current
GND ≤ V ≤ V , Output Disabled
DDQ
–5
µA
OZ
I
V
Operating Supply Current V = Max, I
= 0 mA,
7.5 ns cycle, 133 MHz
10 ns cycle, 100 MHz
225
205
90
mA
mA
mA
mA
DD
DD
DD
OUT
= 1/t
CYC
f = f
MAX
I
I
I
I
Automatic CE Power down
Current—TTL Inputs
Max V , Device Deselected, 7.5 ns cycle, 133 MHz
DD
SB1
V
≥ V or V ≤ V , f = f
,
IN
IH
IN
IL
MAX
10 ns cycle, 100 MHz
80
inputs switching
Automatic CE Power down
Current—CMOS Inputs
Max V , Device Deselected, All speeds
40
mA
SB2
SB3
SB4
DD
V
≥ V – 0.3V or V ≤ 0.3V,
IN
DD IN
f = 0, inputs static
Automatic CE Power down
Current—CMOS Inputs
Max V , Device Deselected, 7.5 ns cycle, 133 MHz
75
65
mA
mA
DD
V
≥ V
– 0.3V or V
IN
≤
IN
DDQ
10 ns cycle, 100 MHz
0.3V, f = f
, inputs switching
MAX
Automatic CE Power down
Current—TTL Inputs
Max V , Device Deselected, All speeds
45
mA
DD
V
≥ V – 0.3V or V ≤ 0.3V,
IN
DD IN
f = 0, inputs static
Notes
7. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t /2).
CYC
IH
DD
CYC
IL
8.
T
: Assumes a linear ramp from 0V to V (min) within 200 ms. During this time V < V and V
< V
Power up
DD
IH
DD
DDQ DD.
Document Number: 38-05517 Rev. *E
Page 10 of 20
CY7C1345G
Capacitance
Tested initially and after any design or process change that may affect these parameters.
119 BGA
Max
100 TQFP
Max
Parameter
Description
Input Capacitance
Test Conditions
Unit
C
C
C
T = 25°C, f = 1 MHz,
5
5
5
5
5
7
pF
pF
pF
IN
A
V
= 3.3V.
DD
Clock Input Capacitance
CLK
IO
V
= 3.3V
DDQ
Input or Output Capacitance
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
100 TQFP
Package
119 BGA
Package
Parameter
Description
Test Conditions
Unit
Θ
Θ
Thermal Resistance
(Junction to Ambient)
Test conditions follow
standardtestmethodsand
procedures for measuring
thermal impedance, per
EIA/JESD51.
30.32
34.1
°C/W
JA
Thermal Resistance
(Junction to Case)
6.85
14.0
°C/W
JC
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
GND
5 pF
R = 351Ω
≤ 1ns
≤ 1ns
V = 1.5V
T
INCLUDING
JIG AND
SCOPE
(a)
(b)
(c)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
INCLUDING
R = 1538Ω
≤ 1 ns
≤ 1 ns
V = 1.25V
T
JIG AND
SCOPE
(a)
(b)
(c)
Document Number: 38-05517 Rev. *E
Page 11 of 20
CY7C1345G
Switching Characteristics
Over the Operating Range
–133
–100
Unit
Parameter
Description
Min Max Min Max
t
V
(Typical) to the first Access
1
1
ms
POWER
DD
Clock
t
t
t
Clock Cycle Time
Clock HIGH
7.5
2.5
2.5
10
4.0
4.0
ns
ns
ns
CYC
CH
Clock LOW
CL
Output Times
t
t
t
t
t
t
t
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
6.5
8.0
ns
ns
ns
ns
ns
ns
ns
CDV
DOH
CLZ
2.0
0
2.0
0
Clock to Low Z
Clock to High Z
3.5
3.5
3.5
3.5
CHZ
OEV
OELZ
OEHZ
OE LOW to Output Valid
OE LOW to Output Low Z
0
0
OE HIGH to Output High Z
3.5
3.5
Setup Times
t
t
t
t
t
t
Address Setup Before CLK Rise
ADSP, ADSC Setup Before CLK Rise
ADV Setup Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
AS
ADS
ADVS
WES
DS
GW, BWE, BW Setup Before CLK Rise
x
Data Input Setup Before CLK Rise
Chip Enable Setup
CES
Hold Times
t
t
t
t
t
t
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
AH
ADSP, ADSC Hold After CLK Rise
ADH
WEH
ADVH
DH
GW, BWE, BW Hold After CLK Rise
x
ADV Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
CEH
Notes
9. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
11. This part has a voltage regulator internally; t
initiated.
is the time that the power needs to be supplied above V (minimum) initially before a read or write operation is
POWER
DD
12. t
, t
,t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady state voltage.
CHLZ CLZ OELZ
OEHZ
13. At any voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data bus.
CLZ
OEHZ
OELZ
CHZ
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High
Z prior to Low Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
Document Number: 38-05517 Rev. *E
Page 12 of 20
CY7C1345G
Timing Diagrams
Figure 1 shows the read cycle timing.
Figure 1. Read Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
[A:B]
CE
Deselect Cycle
t
t
CES
CEH
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2
+
1)
Q(A2 + 2)
Q(A2
+
3)
Q(A2)
Q(A2
+
1)
Q(A2
+
2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note:
15. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document Number: 38-05517 Rev. *E
Page 13 of 20
CY7C1345G
Timing Diagrams (continued)
Figure 2 shows the write cycle timing.
Figure 2. Write Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW[A:B]
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2
+
1)
D(A2
+
1)
D(A2
+
2)
D(A2
+
3)
D(A3)
D(A3
+
1)
D(A3
+
2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
DON’T CARE
UNDEFINED
Note:
16.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
x
Document Number: 38-05517 Rev. *E
Page 14 of 20
CY7C1345G
Timing Diagrams (continued)
Figure 3 shows the read and write timing.
Figure 3. Read/Write Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
BWE, BW [A:B]
CE
t
t
WEH
WES
t
t
CEH
CES
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
Back-to-Back READs
Single WRITE
BURST READ
DON’T CARE
UNDEFINED
Notes:
17. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
18. GW is HIGH.
Document Number: 38-05517 Rev. *E
Page 15 of 20
CY7C1345G
Timing Diagrams (continued)
Figure 4 shows the ZZ mode timing.
Figure 4. ZZ Mode Timing
CLK
ZZ
t
t
ZZ
ZZREC
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
19. Device must be deselected when entering ZZ mode. See “Truth Table” on page 8 for all possible signal conditions to deselect the device.
20. DQs are in high-Z when exiting ZZ sleep mode.
Document Number: 38-05517 Rev. *E
Page 16 of 20
CY7C1345G
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
133 CY7C1345G-133AXC
CY7C1345G-133BGC
CY7C1345G-133BGXC
CY7C1345G-133AXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)
Commercial
119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)
lndustrial
CY7C1345G-133BGI
CY7C1345G-133BGXI
100 CY7C1345G-100AXC
CY7C1345G-100BGC
CY7C1345G-100BGXC
CY7C1345G-100AXI
119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)
Commercial
lndustrial
119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1345G-100BGI
CY7C1345G-100BGXI
119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
Document Number: 38-05517 Rev. *E
Page 17 of 20
CY7C1345G
Package Diagrams
Figure 5. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
1.00 REF.
51-85050-*B
DETAIL
A
Document Number: 38-05517 Rev. *E
Page 18 of 20
CY7C1345G
Package Diagrams (continued)
Figure 6.119-Ball BGA (14 x 22 x 2.4 mm), 51-85115
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.75 0.15(119X)
Ø1.00(3X) REF.
7
1
2
3
4
5
6
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
G
H
J
K
L
J
K
L
M
N
P
R
T
M
N
P
R
T
U
U
1.27
0.70 REF.
A
3.81
12.00
7.62
B
14.00 0.20
0.15(4X)
30° TYP.
SEATING PLANE
C
51-85115-*B
Document Number: 38-05517 Rev. *E
Page 19 of 20
CY7C1345G
Document History Page
Document Title: CY7C1345G, 4-Mbit (128K x 36) Flow Through Sync SRAM
Document Number: 38-05517
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
See ECN
See ECN
**
224365
278513
RKF
New datasheet
Deleted 66 MHz
*A
VBL
Changed TQFP package to Pb-free TQFP in Ordering Information section
Added BG Pb-free package
See ECN
*B
333626
SYT
Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA
Packages as per JEDEC standards and updated the Pin Definitions accordingly
Modified V
V
test conditions
OL, OH
Replaced ‘Snooze’ with ‘Sleep’
Removed 117 MHz speed bin
Replaced TBDs for Θ and Θ to their respective values on the Thermal Resis-
JA
JC
tance table
Removed comment on the availability of BG Pb-free package
Updated the Ordering Information by shading and unshading MPNs as per
availability
See ECN
*C
418633
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Modified test condition from V < V to V < V
IH
DD
IH
DD.
Modified test condition from V
< V to V
< V
DDQ
DD
DDQ DD
Modified Input Load to Input Leakage Current except ZZ and MODE in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering Infor-
mation table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information
See ECN
See ECN
*D
*E
480124
VKN
VKN
Added the Maximum Rating for Supply Voltage on V
Updated the Ordering Information table.
Relative to GND
DDQ
1274724
Corrected Write Cycle timing waveform
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05517 Rev. *E
Revised July 15, 2007
Page 20 of 20
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