CY7C1338G
4-Mbit (128K x 32) Flow-Through Sync SRAM
Features
Functional Description[1]
• 128K x 32 common I/O
• 3.3V core power supply (V
• 2.5V or 3.3V I/O supply (V
The CY7C1338G is a 128K x 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
)
DD
)
DDQ
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
• Provide high-performance 2-1-1-1 access rate
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE ), depth-expansion Chip Enables (CE and CE ), Burst
®
• User-selectable burst counter supporting Intel
®
1
2
3
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW , and BWE), and Global Write (GW). Asynchronous
[A:D]
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1338G allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
• Asynchronous output enable
• Offered in lead-free 100-Pin TQFP package, lead-free
and non-lead-free 119-Ball BGA package
• “ZZ” Sleep Mode option
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1338G operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
A0, A1, A
ADDRESS
REGISTER
A[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
AND LOGIC
Q0
CLR
ADSC
ADSP
DQD BYTE
DQD BYTE
WRITE REGISTER
BWD
WRITE REGISTER
DQC BYTE
DQC BYTE
WRITE REGISTER
BWC
WRITE REGISTER
OUTPUT
BUFFERS
MEMORY
ARRAY
SENSE
AMPS
DQs
DQB BYTE
DQB BYTE
WRITE REGISTER
BWB
WRITE REGISTER
DQA BYTE
WRITE REGISTER
DQA BYTE
BWA
BWE
WRITE REGISTER
INPUT
REGISTERS
GW
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05521 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 5, 2006
CY7C1338G
Pin Configurations (continued)
119-Ball BGA Pinout
2
1
3
A
A
A
4
5
A
A
A
6
7
A
B
C
D
E
F
V
A
CE
A
A
V
DDQ
ADSP
ADSC
DDQ
NC/288M
NC/576M
NC/1G
NC/9M
A
2
NC/144M
V
DD
DQ
DQ
NC
DQ
V
NC
CE
V
NC
DQ
DQ
C
C
SS
SS
SS
SS
SS
SS
B
V
V
V
V
DQ
C
B
B
1
V
DQ
DQ
DQ
V
DQ
V
DDQ
OE
DDQ
C
C
C
B
G
H
J
DQ
DQ
DQ
BW
V
BW
V
ADV
GW
C
B
B
C
B
DQ
DQ
DQ
C
SS
SS
B
B
V
NC
V
NC
V
V
DDQ
DDQ
DD
DD
DD
K
DQ
DQ
V
CLK
NC
V
DQ
DQ
D
D
SS
SS
A
A
L
M
N
DQ
DQ
DQ
DQ
BW
V
BW
V
DQ
DQ
DQ
DQ
D
D
D
D
D
A
A
A
A
A
V
V
DDQ
BWE
A1
DDQ
SS
SS
DQ
V
V
DQ
D
SS
SS
A
P
R
T
DQ
NC
A
V
A0
V
NC
A
DQ
D
SS
SS
A
NC
NC
MODE
A
V
NC
A
NC
ZZ
DD
NC/72M
NC
A
NC/36M
NC
V
NC
NC
NC
V
DDQ
U
DDQ
Pin Definitions
Name
I/O
Input-
Synchronous of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. A
[1:0]
Description
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
feed
A0, A1, A
1
2
3
the 2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
BW , BW
Input-
A
B
BW , BW
C
D
GW
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Synchronous write is conducted (ALL bytes are written, regardless of the values on BW
and BWE).
[A:D]
BWE
CLK
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE
CE
CE
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
1
2
3
Synchronous CE and CE to select/deselect the device. ADSP is ignored if CE is HIGH. CE is sampled only
2
3
1
1
when a new external address is loaded.
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE and CE to select/deselect the device. CE is sampled only when a new external address is
1
3
2
loaded.
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE and CE to select/deselect the device. CE is sampled only when a new external address is
1
2
3
loaded.
OE
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected
state.
ADV
Input-
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
Synchronous increments the address in a burst cycle.
Document #: 38-05521 Rev. *D
Page 3 of 17
CY7C1338G
Pin Definitions (continued)
Name
ADSP
I/O
Description
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
Input-
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A
are
[1:0]
also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-
nized. ASDP is ignored when CE is deasserted HIGH
1
ADSC
ZZ
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A
are also loaded
[1:0]
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Input-
ZZ “sleep” Input, active HIGH. Whenasserted HIGH places the device in a non-time-critical“sleep”
Asynchronous condition with data integrity preserved. During normal operation, this pin has to be low or left floating.
ZZ pin has an internal pull-down.
DQs
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by
Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the
pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs
are placed in a tri-state condition.
V
Power
Supply
Power supply inputs to the core of the device.
DD
V
V
Ground
Ground for the core of the device.
SS
I/O Power Power supply for the I/O circuitry.
Supply
DDQ
V
I/O Ground Ground for the I/O circuitry.
SSQ
MODE
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V or left
DD
floating selects interleaved burst sequence. This is a strap pin and should remain static during device
operation. Mode Pin has an internal pull-up.
NC
No Connects. Not Internally connected to the die.
NC/9M,
–
No Connects. Not internally connected to the die. NC/9M,NC/18M,NC/36M,NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins that are not internally connected to
the die.
NC/18M
NC/36M
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
Three synchronous Chip Selects (CE , CE , CE ) and an
1
2
3
the clock rise (t ) is 6.5 ns (133-MHz device).
C0
asynchronous Output Enable (OE) provide for easy bank
The CY7C1338G supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
selection and output tri-state control. ADSP is ignored if CE
is HIGH.
1
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE , CE , and CE are all
1
2
3
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to t
after clock
CDV
rise. ADSP is ignored if CE is HIGH.
Byte write operations are qualified with the Byte Write Enable
1
(BWE) and Byte Write Select (BW
) inputs. A Global Write
[A:D]
Document #: 38-05521 Rev. *D
Page 4 of 17
CY7C1338G
Single Write Accesses Initiated by ADSP
A[1:0], and can follow either a linear or interleaved burst order.
The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to a inter-
leaved burst sequence.
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE , CE , CE are all asserted
1
2
3
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BW[ ])are ignored during this first
A:D
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
During byte writes, BW controls DQ and BWB controls DQ .
A
A
B
BWC controls DQ , and BW controls DQ . All I/Os are
C
D
D
tri-stated during a byte write.Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless of the state of OE.
inactive for the duration of t
LOW.
after the ZZ input returns
ZZREC
Single Write Accesses Initiated by ADSC
Interleaved Burst Address Table
(MODE = Floating or VDD
This write access is initiated when the following conditions are
)
satisfied at clock rise: (1) CE , CE , and CE are all asserted
1
2
3
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW
indicate a write access. ADSC is ignored if ADSP is active
LOW.
First
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
)
Address
A1, A0
[A:D]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ
will be
[A:D]
written into the specified address location. Byte writes are
allowed. During byte writes, BW controls DQ , BW controls
A
A
B
Linear Burst Address Table (MODE = GND)
DQ , BW controls DQ , and BW controls DQ . All I/Os are
B
C
C
D
D
tri-stated when a write is detected, even a byte write. Since this
is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless
of the state of OE.
First
Second
Third
Fourth
Address
Address
Address
Address
A ,A
A ,A
A ,A
A ,A
1
0
1
0
1
0
1
0
00
01
10
11
01
10
11
10
11
00
11
00
01
00
01
10
Burst Sequences
The CY7C1338G provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
ZZ Mode Electrical Characteristics
Parameter
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
Min.
Max.
Unit
I
t
t
t
t
ZZ > V – 0.2V
40
mA
ns
ns
ns
ns
DDZZ
DD
ZZ > V – 0.2V
2t
ZZS
DD
CYC
CYC
ZZ recovery time
ZZ < 0.2V
2t
CYC
ZZREC
ZZI
ZZ active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2t
0
RZZI
Document #: 38-05521 Rev. *D
Page 5 of 17
CY7C1338G
Truth Table [2, 3, 4, 5, 6]
Address
Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK
Cycle Description
DQ
1
2
3
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Sleep Mode, Power-down
Read Cycle, Begin Burst
None
None
H
L
X
L
X
X
H
X
X
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
None
L
X
L
L
None
L
H
H
X
L
None
X
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
X
X
L
X
Tri-State
Q
External
External
External
External
External
Next
L-H
Read Cycle, Begin Burst
L
L
L
H
X
L
L-H Tri-State
Write Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
Read Cycle, Begin Burst
L
L
L
H
H
H
H
H
H
L
Read Cycle, Begin Burst
L
L
L
H
L
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H Tri-State
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H Tri-State
L-H
L-H Tri-State
Q
H
X
X
L-H
L-H
D
D
L
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW , BW , BW , BW ) and BWE = L or GW= L. WRITE = H when all Byte write enable signals
A
B
C
D
(BW , BW , BW , BW ), BWE, GW = H.
A
B
C
D
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks
X
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state.
is a
OE
don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05521 Rev. *D
Page 6 of 17
CY7C1338G
Partial Truth Table for Read/Write[2, 7]
Function
Read
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
BW
X
H
H
H
H
H
H
H
H
L
BW
X
H
H
H
H
L
BW
X
H
H
L
BW
A
D
C
B
X
H
L
Read
Write Byte A
L
Write Byte B
L
H
L
Write Bytes B, A
Write Byte C
L
L
L
H
H
L
H
L
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D
L
L
L
L
H
L
L
L
L
L
H
H
H
H
L
H
H
L
H
L
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C, A
Write All Bytes
Write All Bytes
L
L
L
L
H
L
L
L
L
L
L
H
H
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
X
X
X
X
X
Note:
7. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document #: 38-05521 Rev. *D
Page 7 of 17
CY7C1338G
DC Input Voltage ................................... –0.5V to V + 0.5V
Maximum Ratings
DD
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current..................................................... >200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on V Relative to GND........ –0.5V to +4.6V
DD
Ambient
]
Supply Voltage on V
Relative to GND ......–0.5V to +V
Range
Temperature
V
V
DDQ
DDQ
DD
DD
DC Voltage Applied to Outputs
in tri-state ............................................ –0.5V to V
Commercial 0°C to +70°C 3.3V −5%/+10% 2.5V –5%
+ 0.5V
to V
DDQ
DD
Industrial
–40°C to +85°C
[8, 9]
Electrical Characteristics Over the Operating Range
Parameter
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Test Conditions
Min.
3.135
2.375
2.4
Max.
Unit
V
V
V
V
3.6
DD
V
V
DDQ
OH
DD
for 3.3V I/O, I = –4.0 mA
V
OH
for 2.5V I/O, I = –1.0 mA
2.0
V
OH
V
V
V
I
Output LOW Voltage
Input HIGH Voltage
for 3.3V I/O,I = 8.0 mA
0.4
0.4
V
OL
IH
IL
OL
for 2.5V I/O, I = 1.0 mA
V
OL
for 3.3V I/O
for 2.5V I/O
for 3.3V I/O
for 2.5V I/O
2.0
1.7
V
V
+ 0.3V
+ 0.3V
0.8
V
DD
DD
V
[8]
Input LOW Voltage
–0.3
–0.3
−5
V
0.7
V
Input Leakage Current GND ≤ V ≤ V
except ZZ and MODE
5
µA
X
I
DDQ
Input Current of MODE Input = V
–30
–5
µA
µA
SS
Input = V
5
DD
Input Current of ZZ
Input = V
Input = V
µA
SS
DD
30
5
µA
I
I
Output Leakage Current GND ≤ V ≤ V
, Output Disabled
–5
µA
OZ
I
DDQ
V
Operating Supply
V = Max., I
DD
= 0 mA,
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
225
205
90
mA
mA
mA
mA
DD
DD
OUT
Current
f = f
= 1/t
MAX CYC
I
I
I
Automatic CE
Power-Down
Current—TTL Inputs
Max. V , Device Deselected, 7.5-ns cycle, 133 MHz
DD
SB1
V
≥ V or V ≤ V , f = f
,
IN
IH
IN
IL
MAX
10-ns cycle, 100 MHz
80
inputs switching
Automatic CE
Power-Down
Current—CMOS Inputs f = 0, inputs static
Max. V , Device Deselected, All speeds
40
mA
SB2
SB3
DD
V
≥ V – 0.3V or V ≤ 0.3V,
IN
DD IN
Automatic CE
Power-Down
Current—CMOS Inputs 0.3V,
f = f
Max. V , Device Deselected, 7.5-ns cycle, 133 MHz
75
65
mA
mA
DD
V
≥ V
– 0.3V or V
≤
IN
DDQ
IN
10-ns cycle, 100 MHz
, inputs switching
MAX
I
Automatic CE
Power-Down
Current—TTL Inputs
Max. V , Device Deselected, All speeds
45
mA
SB4
DD
V
≥ V – 0.3V or V ≤ 0.3V,
IN DD IN
f = 0, inputs static
Notes:
8. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t /2).
CYC
IH
DD
CYC
IL
9. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
Document #: 38-05521 Rev. *D
Page 8 of 17
CY7C1338G
Capacitance[10]
119 BGA
Max.
100 TQFP
Max.
Parameter
Description
Input Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Unit
pF
C
C
C
5
5
5
5
5
7
IN
A
V
V
= 3.3V.
DD
Clock Input Capacitance
Input/Output Capacitance
pF
CLK
I/O
= 3.3V
DDQ
pF
Thermal Resistance[10]
100 TQFP
Package
119 BGA
Package
Parameter
ΘJA
Description
Test Conditions
Unit
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test
methods and procedures for
measuringthermalimpedance,per
EIA/JESD51.
30.32
34.1
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
6.85
14.0
°C/W
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
GND
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
V = 1.5V
T
INCLUDING
JIG AND
SCOPE
(a)
(b)
(c)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
5 pF
R =1538Ω
≤ 1ns
≤ 1ns
V = 1.25V
T
INCLUDING
JIG AND
SCOPE
(a)
(b)
(c)
Note:
10. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05521 Rev. *D
Page 9 of 17
CY7C1338G
[11, 12, 13, 14, 15, 16]
Switching Characteristics Over the Operating Range
–133
–100
Parameter
Description
Min.
Max.
Min.
Max.
Unit
[11]
t
V
(Typical) to the first Access
1
1
ms
POWER
DD
Clock
t
t
t
Clock Cycle Time
Clock HIGH
7.5
2.5
2.5
10
4.0
4.0
ns
ns
ns
CYC
CH
Clock LOW
CL
Output Times
t
t
t
t
t
t
t
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
6.5
8.0
ns
ns
ns
ns
ns
ns
ns
CDV
2.0
0
2.0
0
DOH
CLZ
[12, 13, 14]
Clock to Low-Z
[12, 13, 14]
Clock to High-Z
3.5
3.5
3.5
3.5
CHZ
OEV
OELZ
OEHZ
OE LOW to Output Valid
[12, 13, 14]
OE LOW to Output Low-Z
0
0
[12, 13, 14]
3.5
3.5
OE HIGH to Output High-Z
Setup Times
t
t
t
t
t
t
Address Set-up Before CLK Rise
ADSP, ADSC Set-up Before CLK Rise
ADV Set-up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
1.5
2.0
ns
ns
ns
ns
ns
ns
AS
ADS
ADVS
WES
DS
GW, BWE, BW Set-up Before CLK Rise
X
Data Input Set-up Before CLK Rise
Chip Enable Set-up
CES
Hold Times
t
t
t
t
t
t
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
AH
ADSP, ADSC Hold After CLK Rise
ADH
WEH
ADVH
DH
GW, BWE, BW Hold After CLK Rise
X
ADV Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
CEH
Notes:
11. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially before a read or write operation
DD
POWER
can be initiated.
12. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
CHZ CLZ OELZ
13. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
OEHZ
OELZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
15. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05521 Rev. *D
Page 10 of 17
CY7C1338G
Timing Diagrams
[17]
Read Cycle Timing
t
CYC
t
CLK
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
[A:D]
Deselect Cycle
t
t
CES
CEH
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst.
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note:
17. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05521 Rev. *D
Page 11 of 17
CY7C1338G
Timing Diagrams (continued)
[17, 18]
Write Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW[A:D]
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
DON’T CARE
UNDEFINED
Note:
18.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
LOW.
[A:D]
Document #: 38-05521 Rev. *D
Page 12 of 17
CY7C1338G
Timing Diagrams (continued)
[17, 19, 20]
Read/Write Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
BWE, BW[A:D]
CE
t
t
WEH
WES
t
t
CEH
CES
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
Back-to-Back READs
Single WRITE
BURST READ
WRITEs
DON’T CARE
UNDEFINED
Notes:
19. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
20.
GW is HIGH.
Document #: 38-05521 Rev. *D
Page 13 of 17
CY7C1338G
Timing Diagrams (continued)
[21, 22]
ZZ Mode Timing
CLK
ZZ
t
t
ZZ
ZZREC
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
22. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05521 Rev. *D
Page 14 of 17
CY7C1338G
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Part and Package Type
133 CY7C1338G-133AXC
CY7C1338G-133BGC
CY7C1338G-133BGXC
CY7C1338G-133AXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Commercial
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
lndustrial
CY7C1338G-133BGI
CY7C1338G-133BGXI
100 CY7C1338G-100AXC
CY7C1338G-100BGC
CY7C1338G-100BGXC
CY7C1338G-100AXI
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Commercial
lndustrial
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1338G-100BGI
CY7C1338G-100BGXI
119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
Package Diagrams
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
A
Document #: 38-05521 Rev. *D
Page 15 of 17
CY7C1338G
Package Diagrams (continued)
119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.75 0.15(119X)
Ø1.00(3X) REF.
1
2
3
4
5
6
7
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
G
H
J
K
L
J
K
L
M
N
P
R
T
M
N
P
R
T
U
U
1.27
0.70 REF.
A
3.81
12.00
7.62
B
14.00 0.20
0.15(4X)
30° TYP.
51-85115-*B
SEATING PLANE
C
Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05521 Rev. *D
Page 16 of 17
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1338G
Document History Page
Document Title: CY7C1338G 4-Mbit (128K x 32) Flow-Through Sync SRAM
Document Number: 38-05521
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
224369
278513
See ECN
See ECN
RKF
VBL
New data sheet
Deleted 66 MHz
*A
Changed TQFP to PB-Free TQFP in Ordering Info section
Added PB-Free BG package
*B
333626
See ECN
SYT
Removed 117-MHz speed bin
Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA
Packages as per JEDEC standards and updated the Pin Definitions accord-
ingly
Modified V
V
test conditions
OL, OH
Replaced ‘Snooze’ with ‘Sleep’
Replaced TBD’s for Θ and Θ to their respective values on the Thermal
JA
JC
Resistance table
Removed comment on the availability of BG lead-free package
Updated the Ordering Information by shading and unshading MPNs as per
availability
*C
418633
See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed I from Electrical Characteristics table on Page #8
OS
Modified test condition from V < V to V < V
IH
DD
IH
DD
< V
Modified test condition from V
< V to V
DDQ
DD
DDQ DD
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information table
*D
480368
See ECN
VKN
Added the Maximum Rating for Supply Voltage on V
Updated the Ordering Information table.
Relative to GND.
DDQ
Document #: 38-05521 Rev. *D
Page 17 of 17
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