CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
18-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
Features
Functional Description
■ Separate independent read and write data ports
❐ Supports concurrent transactions
The CY7C1161V18, CY7C1176V18, CY7C1163V18, and
CY7C1165V18 are 1.8V Synchronous Pipelined SRAMs
equipped with QDR™-II+ architecture. QDR-II+ architecture
consists of two separate ports to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
■ 300 MHz to 400 MHz clock for high bandwidth
■ 4-word burst to reduce address bus frequency
■ DoubleDataRate(DDR)interfacesonbothreadandwriteports
(data transferred at 800 MHz) at 400 MHz
operations. QDR-II+ architecture has separate data inputs and
data outputs to completely eliminate the need to turn around the
data bus that is required with common IO devices. Each port can
be accessed through a common address bus. Addresses for
read and write addresses are latched onto alternate rising edges
of the input (K) clock. Accesses to the QDR-II+ read and write
ports are completely independent of one another. In order to
maximize data throughput, both read and write ports are
equipped with Double Data Rate (DDR) interfaces. Each
address location is associated with four 8-bit words
(CY7C1161V18), 9-bit words (CY7C1176V18), 18-bit words
(CY7C1163V18), or 36-bit words (CY7C1165V18) that burst
sequentially into or out of the device. Because data can be trans-
ferred into and out of the device on every rising edge of both input
clocks K and K, memory bandwidth is maximized while simpli-
fying system design by eliminating bus turnarounds.
■ Read latency of 2.5 clock cycles
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate port selects for depth expansion
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ Available in x8, x9, x18, and x36 configurations
Depth expansion is accomplished with port selects for each port.
Port selects allow each port to operate independently.
■ Full data coherency providing most current data
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the or K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
■ Core V = 1.8V ± 0.1V; IO V
= 1.4V to V
DD
DD
DDQ
■ Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ Variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
With cycle read latency of 2.5 cycles:
CY7C1161V18 – 2M x 8
CY7C1176V18 – 2M x 9
CY7C1163V18 – 1M x 18
CY7C1165V18 – 512K x 36
Selection Guide
Description
400 MHz
400
375 MHz
375
333 MHz
333
300 MHz
300
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
1080
1020
920
850
Note
1. The QDR consortium specification for V
is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V
DDQ
DDQ
= 1.4V to V
.
DD
Cypress Semiconductor Corporation
Document Number: 001-06582 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 06, 2008
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Logic Block Diagram (CY7C1163V18)
D
[17:0]
18
Write Write Write Write
Address
Register
A
(17:0)
Reg
Reg
Reg
Reg
18
Address
Register
A
(17:0)
18
RPS
K
K
Control
Logic
CLK
Gen.
DOFF
Read Data Reg.
72
CQ
CQ
36
V
REF
Reg.
Reg.
Reg.
WPS
BWS
Control
Logic
Q
[17:0]
36
[1:0]
18
18
QVLD
Logic Block Diagram (CY7C1165V18)
D
[35:0]
36
Write Write Write Write
Address
Register
A
(16:0)
Reg
Reg Reg
Reg
17
Address
Register
A
(16:0)
17
RPS
K
K
Control
Logic
CLK
Gen.
DOFF
Read Data Reg.
144
CQ
CQ
72
V
REF
Reg.
Reg.
Reg.
WPS
BWS
Control
Logic
Q
[35:0]
72
[3:0]
36
36
QVLD
Document Number: 001-06582 Rev. *D
Page 3 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Pin Configurations
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1161V18 (2M x 8)
1
2
3
6
9
10
11
5
7
8
4
NC/72M
A
K
NC/144M
A
NC/36M
CQ
A
CQ
WPS
NWS1
RPS
NC
NC
NC
NC
NC
D4
NC
NC
NC
A
NC/288M
K
NWS0
A
A
NC
NC
NC
NC
NC
NC
Q3
D3
NC
B
C
D
VSS
VSS
A
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
D5
Q4
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
D2
NC
Q2
NC
NC
ZQ
D1
NC
Q0
E
F
Q5
NC
NC
G
VREF
NC
NC
Q6
VDDQ
NC
VDDQ
NC
VREF
Q1
H
J
DOFF
NC
NC
NC
NC
NC
NC
NC
NC
NC
K
L
D6
NC
NC
NC
D7
NC
NC
NC
Q7
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
NC
D0
NC
NC
M
N
P
A
QVLD
A
A
A
A
A
A
A
TDO
TCK
A
NC
A
TMS
TDI
R
CY7C1176V18 (2M x 9)
1
2
NC/72M
NC
3
6
K
9
10
NC/36M
NC
11
CQ
Q4
D4
NC
Q3
5
NC
7
8
4
WPS
A
CQ
NC
NC
NC
NC
A
NC/144M RPS
A
A
B
C
D
NC
NC
NC
Q5
NC/288M
A
K
BWS0
A
A
NC
NC
NC
NC
VSS
VSS
NC
VSS
VSS
VSS
NC
D5
VSS
VSS
VSS
NC
NC
NC
D6
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
D3
NC
E
F
NC
NC
NC
Q6
VDD
VDD
VDD
VDD
VDD
VSS
NC
NC
ZQ
D2
NC
Q1
NC
NC
G
H
J
VDDQ
NC
VREF
Q2
DOFF
NC
VREF
NC
NC
Q7
VDDQ
NC
NC
NC
D7
NC
NC
Q8
NC
NC
K
L
NC
NC
NC
NC
NC
NC
NC
D8
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
D0
D1
NC
Q0
M
N
P
A
QVLD
A
A
A
A
A
A
A
TDO
TCK
A
NC
A
TMS
TDI
R
Document Number: 001-06582 Rev. *D
Page 4 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Pin Configurations (continued)
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1163V18 (1M x 18)
2
3
5
BWS1
NC
6
7
9
10
NC/72M
NC
11
CQ
Q8
D8
D7
Q6
Q5
D5
1
4
WPS
A
8
CQ
NC
NC
NC
NC
NC
NC
NC/144M NC/36M
K
NC/288M RPS
A
A
B
C
D
E
F
Q9
NC
D9
K
BWS0
A
A
NC
NC
NC
D10
Q10
Q11
D12
Q13
VSS
A
NC
VSS
VSS
VSS
VSS
VSS
Q7
D11
NC
VSS
VSS
VSS
VDD
VDD
VSS
VSS
VDD
VDD
VSS
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
D6
Q12
D13
NC
NC
NC
G
VDDQ
NC
DOFF
NC
VREF
NC
VDDQ
D14
VDDQ
VDDQ
VDD
VDD
VSS
VSS
VDD
VDD
VDDQ
VDDQ
VREF
Q4
ZQ
D4
H
J
NC
NC
NC
NC
NC
NC
Q15
NC
Q14
D15
D16
Q16
Q17
VDDQ
VDDQ
VSS
VDD
VSS
VSS
A
VSS
VSS
VSS
A
VDD
VSS
VSS
A
VDDQ
VDDQ
VSS
NC
D3
NC
Q1
NC
D0
Q3
Q2
D2
D1
Q0
K
L
NC
NC
NC
NC
M
N
P
D17
NC
VSS
VSS
A
QVLD
A
A
A
A
A
A
A
R
TDO
A
A
TMS
TDI
TCK
NC
CY7C1165V18 (512K x 36)
7
1
2
3
8
RPS
A
9
10
11
CQ
Q8
D8
D7
4
WPS
A
5
6
K
NC/288M NC/72M
NC/36M NC/144M
A
B
C
D
CQ
BWS2
BWS3
A
BWS1
Q27
D27
D28
Q29
Q30
D30
Q18
Q28
D20
D18
D19
Q19
K
D17
D16
Q16
Q17
Q7
BWS0
A
VSS
VSS
NC
VSS
VSS
VSS
VSS
VSS
D15
D29
Q21
D22
VREF
Q31
D32
Q24
Q20
D21
Q22
VDDQ
D23
Q23
D24
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
Q15
D14
Q13
VDDQ
D12
Q12
D11
D6
Q14
D13
VREF
Q4
Q6
Q5
D5
ZQ
D4
Q3
Q2
E
F
G
H
J
DOFF
D31
Q32
Q33
D33
D34
Q35
D3
K
L
Q11
Q34
D26
D35
D25
Q25
Q26
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
D10
Q10
Q9
Q1
D9
D0
D2
D1
Q0
M
N
P
A
QVLD
A
A
A
A
A
A
A
TDO
TCK
A
A
TMS
TDI
R
NC
Document Number: 001-06582 Rev. *D
Page 5 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Pin Definitions
Pin Name
IO
Pin Description
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
D
Input-
[x:0]
Synchronous CY7C1161V18−D
[7:0]
CY7C1176V18−D
[8:0]
CY7C1163V18−D
CY7C1165V18−D
[17:0]
[35:0]
WPS
Input-
Synchronous a write operation is initiated. Deasserting deselects the write port. Deselecting the write port causes
to be ignored.
Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active,
D
[x:0]
,
1
Input-
Nibble Write Select 0, 1 − Active LOW (CY7C1161V18 Only). Sampled on the rising edge of the
NWS , NWS
0
Synchronous K and K clocks during Write operations. Used to select the nibble that is written into the device. NWS
0
controls D
and NWS controls D
.
[3:0]
1
[7:4]
All the nibble write selects are sampled on the same edge as the data. Deselecting a nibble write
select causes the corresponding nibble of data to be ignored and not written into the device.
BWS , BWS ,
Input-
Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks
0
1
3
Synchronous during write operations. Used to select the byte that is written into the device during the current portion
BWS , BWS
2
of the write operation. Bytes not written remain unaltered.
CY7C1176V18 − BWS controls D
0
[8:0].
CY7C1163V18 − BWS controls D
and BWS controls D
[17:9]..
0
[8:0]
1
CY7C1165V18 − BWS controls D
, BWS controls D
, BWS controls D
and BWS
[26:18], 3
0
[8:0]
1
[17:9]
2
controls D
[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
causes the corresponding byte of data to be ignored and not written into the device.
A
Input-
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.
Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1161V18, 2M x 9 (4 arrays each of 512K
x 9) for CY7C1176V18, 1M x 18 (4 arrays each of 256K x 18) for CY7C1163V18, and 512K x 36 (4
arrays each of 128K x 36) for CY7C1165V18. Therefore, only 19 address inputs are needed to access
the entire memory array of CY7C1161V18 and CY7C1176V18, 18 address inputs for CY7C1163V18,
and 17 address inputs for CY7C1165V18. These inputs are ignored when the appropriate port is
deselected.
Q
Outputs-
Data Output Signals. These pins drive out the requested data during a read operation. Valid data
[x:0]
Synchronous is driven out on the rising edge of both the K and K clocks during read operations or K and K when
in single clock mode. When the read port is deselected, Q
are automatically tri-stated.
[x:0]
CY7C1161V18 − Q
[7:0]
[8:0]
.
.
CY7C1176V18 − Q
CY7C1163V18 − Q
CY7C1165V18 − Q
[17:0]
.
.
[35:0]
RPS
Input-
Read Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active,
Synchronous a read operation is initiated. Deasserting causes the read port to be deselected. When deselected,
the pending access is enabled to complete and the output drivers are automatically tri-stated following
the next rising edge of the K clock. Each read access consists of a burst of four sequential transfers.
QVLD
K
Valid Output Valid Output Indicator. Indicates valid output data. QVLD is edge-aligned with CQ and CQ.
Indicator
Input-
Clock
Positive Input Clock Input. Rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
edge of K.
when in single clock mode. All accesses are initiated on the rising
[x:0]
K
Input-
Clock
Negative Input Clock Input. K is used to capture synchronous inputs presented to the device and
to drive out data through Q when in single clock mode.
[x:0]
CQ
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
clock (K) of the QDR-II+. The timings for the echo clocks are shown in “Switching Characteristics”
Document Number: 001-06582 Rev. *D
Page 6 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Pin Definitions (continued)
Pin Name
CQ
IO
Pin Description
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
clock (K) of the QDR-II+. The timings for the echo clocks are shown in “Switching Characteristics”
ZQ
Input
Input
Output Impedance Matching Input. Used to tune the device outputs to the system data bus
impedance. CQ, CQ and Q output impedance are set to 0.2 x RQ, where RQ is a resistor
[x:0]
connected between ZQ and ground. Alternatively, this pin is connected directly to V
, which
DDQ
enables the minimum impedance mode. This pin cannot be connected directly to GND or left uncon-
nected.
DOFF
DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
timings in the DLL turned-off operation are different from those listed in this data sheet. For normal
operation, this pin is connected to a pull up through a 10 KΩ or less pull up resistor. The device
behaves in QDR-I mode when the DLL is turned off. In this mode, the device operates at a frequency
of up to 167 MHz with QDR-I timing.
TDO
Output
Input
Input
Input
N/A
TDO for JTAG.
TCK
TCK Pin for JTAG.
TDI
TDI Pin for JTAG.
TMS
TMS Pin for JTAG.
NC
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and
NC/36M
NC/72M
NC/144M
NC/288M
N/A
N/A
N/A
N/A
V
Input-
REF
Reference AC measurement points.
V
V
V
Power Supply Power Supply Inputs to the Core of the Device.
DD
Ground
Ground for the Device.
SS
Power Supply Power Supply Inputs for the Outputs of the Device.
DDQ
Document Number: 001-06582 Rev. *D
Page 7 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Write Operations
Functional Overview
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
The CY7C1161V18, CY7C1176V18, CY7C1163V18, and
CY7C1165V18 are synchronous pipelined burst SRAMs
equipped with both a read port and a write port. The read port is
dedicated to read operations and the write port is dedicated to
write operations. Data flows into the SRAM through the write port
and out through the read port. These devices multiplex the
address inputs in order to minimize the number of address pins
required. By having separate read and write ports, the QDR-II+
completely eliminates the need to “turn-around” the data bus. It
avoids any possible data contention, thereby, simplifying system
design. Each access consists of four 8-bit data transfers in the
case of CY7C1161V18, four 9-bit data transfers in the case of
CY7C1176V18, four 18-bit data transfers in the case of
CY7C1163V18, and four 36-bit data transfers in the case of
CY7C1165V18 in two clock cycles.
clock rise, the data presented to D
the lower 18-bit write data register, provided BWS
is latched and stored into
[17:0]
are both
[1:0]
asserted active. On the subsequent rising edge of the negative
input clock (K), the information presented to D is also stored
[17:0]
are both asserted
into the write data register, provided BWS
[1:0]
active. This process continues for one more cycle until four 18-bit
words (a total of 72 bits) of data are stored in the SRAM. The 72
bits of data are then written into the memory array at the specified
location. Therefore, write accesses to the device cannot be
initiated on two consecutive K clock rises. The internal logic of
the device ignores the second write request. Write accesses are
initiated on every other rising edge of the positive input clock (K).
Doing so pipelines the data flow such that 18 bits of data can be
transferred into the device on every rising edge of the input
clocks (K and K).
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input and output timings are referenced to
the rising edge of the Input clocks (K/K).
When deselected, the write port ignores all inputs after the
pending write operations are completed.
All synchronous data inputs (D
) pass through input registers
[x:0]
Byte Write Operations
controlled by the input clocks (K and K). All synchronous data
outputs (Q ) pass through output registers controlled by the
[x:0]
Byte write operations are supported by the CY7C1163V18. A
write operation is initiated as described in the Write Operations
section above. The bytes that are written are determined by
BWS and BWS , which are sampled with each set of 18-bit data
rising edge of the Input clocks (K and K) also.
All synchronous control (RPS, WPS, BWS
through input registers controlled by the rising edge of the input
clocks (K and K).
) inputs pass
[x:0]
0
1
words. Asserting the appropriate byte write select input during
the data portion of a write enables the data being presented to
be latched and written into the device. Deasserting the byte write
select input during the data portion of a write allows the data
stored in the device for that byte to remain unaltered. This feature
is used to simplify read, modify, and write operations to a byte
write operation.
CY7C1163V18 is described in the following sections. The same
basic descriptions apply to CY7C1161V18, CY7C1176V18, and
CY7C1165V18.
Read Operations
The CY7C1163V18 is organized internally as four arrays of 256K
x 18. Accesses are completed in a burst of four sequential 18-bit
data words. Read operations are initiated by asserting RPS
active at the rising edge of the positive input clock (K). The
address presented to address inputs are stored in the Read
address register. Following the next two K clock rises, the corre-
sponding lowest order 18-bit word of data is driven onto the
Concurrent Transactions
The read and write ports on the CY7C1163V18 operate
completely independent of one another. Because each port
latches the address inputs on different clock edges, the user can
read or write to any location, regardless of the transaction on the
other port. If the ports access the same location when a read
follows a write in successive clock cycles, the SRAM delivers the
most recent information associated with the specified address
location. This includes forwarding data from a write cycle initiated
on the previous K clock rise.
Q
using K as the output timing reference. On the subse-
[17:0]
quent rising edge of K, the next 18-bit data word is driven onto
the Q . This process continues until all four 18-bit data words
[17:0]
have been driven out onto Q
. The requested data is valid
[17:0]
0.45 ns from the rising edge of the Input clock K or K. In order to
maintain the internal logic, each read access must be allowed to
complete. Each read access consists of four 18-bit data words
and takes two clock cycles to complete. Therefore, read
accesses to the device cannot be initiated on two consecutive K
clock rises. The internal logic of the device ignores the second
read request. Read accesses can be initiated on every other K
clock rise. Doing so pipelines the data flow such that data is
transferred out of the device on every rising edge of the input
clocks K and K.
Read accesses and write access are scheduled such that one
transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on the
previous state of the SRAM. If both ports are deselected, the
read port takes priority. If a read is initiated on the previous cycle,
the write port assumes priority (because read operations cannot
be initiated on consecutive cycles). If a write was initiated on the
previous cycle, the read port assumes priority (because write
operations cannot be initiated on consecutive cycles). Therefore,
asserting both port selects active from a deselected state results
in alternating read or write operations initiated, with the first
access being a read.
When the read port is deselected, the CY7C1163V18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the outputs following the next
rising edge of the negative input clock (K). This allows for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Document Number: 001-06582 Rev. *D
Page 8 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Depth Expansion
Valid Data Indicator (QVLD)
The CY7C1163V18 has a port select input for each port. This
enables easy depth expansion. Both port selects are only
sampled on the rising edge of the positive input clock (K). Each
port select input can deselect the specified port. Deselecting a
port does not affect the other port. All pending transactions (read
and write) are completed before the device is deselected.
QVLD is provided on the QDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the QDR-II+ device
along with data output. This signal is also edge-aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
DLL
Programmable Impedance
These chips utilize a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
erations in QDRII/DDRII/QDRII+/DDRII+.” The DLL can also be
reset by slowing or stopping the input clocks K and K for a
minimum of 30 ns. However, it is not necessary for the DLL to be
reset in order to lock to the desired frequency. During power up
when the DOFF is tied HIGH, the DLL is locked after 2048 cycles
of stable clock.
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V to enable the SRAM to adjust its output
SS
driver impedance. The value of RQ must be 5X the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω, with V
= 1.5V. The
DDQ
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR-II+ to simplify data capture
on high speed systems. Two echo clocks are generated by the
QDR-II+. CQ is referenced with respect to K and CQ is refer-
enced with respect to K. These are free running clocks and are
synchronized to the input clock of the QDR-II+. The timings for
the echo clocks are shown in the AC timing table.
Document Number: 001-06582 Rev. *D
Page 9 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Application Example
Figure 1 shows four QDR-II+ used in an application.
Figure 1. Application Example
RQ = 250ohms
RQ = 250ohms
ZQ
CQ/CQ
Q
ZQ
CQ/CQ
Q
Vt
SRAM #1
BWS
SRAM #4
D
A
D
A
R
K
RPS WPS
K
K
K
BWS
RPS WPS
DATA IN
DATA OUT
Address
R
R
Vt
Vt
RPS
BUS MASTER
WPS
BWS
(CPU or ASIC)
CLKIN/CLKIN
Source K
Source K
R = 50ohms, Vt = V
/2
DDQ
Truth Table
The truth table for the CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 follows.
Operation
K
RPS WPS
DQ
DQ
DQ
DQ
Write Cycle: Load
address on rising edge of
K; input write data on two
consecutive K and K rising
edges.
L-H
H
L
D(A) at K(t + 1) ↑ D(A + 1) at K(t + 1) ↑ D(A + 2) at K(t + 2) ↑ D(A + 3) at K(t + 2) ↑
Read Cycle (2.5 Cycle
Latency):Loadaddresson
rising edge of K; wait one
and a half cycle; read data
on two consecutive K and
K rising edges.
L-H
L
X
Q(A) at K(t + 2) ↑ Q(A + 1) at K(t + 3) ↑ Q(A + 2) at K(t + 3)↑ Q(A + 3) at K(t + 4) ↑
NOP: No operation.
L-H
H
X
H
X
D = X
Q = High Z
D = X
Q = High Z
D = X
Q = High Z
D = X
Q = High Z
Standby: Clock stopped. Stopped
Previous State
Previous State
Previous State
Previous State
Notes
2. The above application shows four QDR-II+ being used.
3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
4. Device powers up deselected and the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.
6. “t” represents the cycle at which a read or write operation is started. t + 1, t + 2, t + 3 and t + 4 are the first, second, third, and fourth clock cycles, respectively succeeding
the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
8. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
9. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
10. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
second read or write request.
Document Number: 001-06582 Rev. *D
Page 10 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Write Cycle Descriptions
The write cycle descriptions of CY7C1161V18 and CY7C1163V18 follow.
BWS / BWS /
0
1
K
Comments
K
NWS
NWS
1
0
L
L
L
L
L–H
–
During the data portion of a write sequence:
CY7C1161V18 − both nibbles (D
) are written into the device.
[7:0]
CY7C1163V18 − both bytes (D
) are written into the device.
[17:0]
–
L–H
–
L-H During the data portion of a write sequence:
CY7C1161V18 − both nibbles (D
) are written into the device.
) are written into the device.
[7:0]
CY7C1163V18 − both bytes (D
[17:0]
L
H
H
L
–
During the data portion of a write sequence:
CY7C1161V18 − only the lower nibble (D
) is written into the device, D
remains unaltered.
remains unaltered.
[3:0]
[7:4]
CY7C1163V18 − only the lower byte (D
) is written into the device, D
[8:0]
[17:9]
L
L–H During the data portion of a write sequence:
CY7C1161V18 − only the lower nibble (D
) is written into the device, D
remains unaltered.
remains unaltered.
[3:0]
[7:4]
CY7C1163V18 − only the lower byte (D
) is written into the device, D
[8:0]
[17:9]
H
H
L–H
–
–
During the data portion of a write sequence:
CY7C1161V18 − only the upper nibble (D
) is written into the device, D
) is written into the device, D
remains unaltered.
[3:0]
[7:4]
CY7C1163V18 − only the upper byte (D
remains unaltered.
[17:9]
[8:0]
L
L–H During the data portion of a write sequence:
CY7C1161V18 − only the upper nibble (D
) is written into the device, D
) is written into the device, D
remains unaltered.
remains unaltered.
[7:4]
[3:0]
[8:0]
CY7C1163V18 − only the upper byte (D
[17:9]
H
H
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
The write cycle operation of CY7C1176V18 follows.
BWS
K
L–H
–
K
Comments
0
L
L
–
During the data portion of a write sequence, the single byte (D
) is written into the device.
) is written into the device.
[8:0]
L–H During the data portion of a write sequence, the single byte (D
[8:0]
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Note
11. Is based upon a Write cycle was initiated per the Write Cycle Description Truth Table. NWS , NWS , BWS , BWS , BWS , and BWS can be altered on different
0
1
0
1
2
3
portions of a Write cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-06582 Rev. *D
Page 11 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
The write cycle descriptions of CY7C1165V18 follows.
BWS
BWS
BWS
BWS
3
K
K
Comments
0
1
2
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D
the device.
) are written into
) are written into
[35:0]
L
L
L
H
H
L
L
H
H
H
H
L
L
H
H
H
H
H
H
L
–
L–H
–
L–H During the data portion of a write sequence, all four bytes (D
the device.
[35:0]
–
During the data portion of a write sequence, only the lower byte (D
) is written
) is written
[8:0]
[8:0]
into the device. D
remains unaltered.
[35:9]
L
L–H During the data portion of a write sequence, only the lower byte (D
into the device. D remains unaltered.
[35:9]
H
H
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D
) is written into
[17:9]
the device. D
and D
remains unaltered.
[8:0]
[35:18]
L
L–H During the data portion of a write sequence, only the byte (D
the device. D and D remains unaltered.
) is written into
[17:9]
[8:0]
[35:18]
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D
) is written into
) is written into
) is written into
) is written into
[26:18]
[26:18]
[35:27]
[35:27]
the device. D
and D
remains unaltered.
[17:0]
[35:27]
L
L–H During the data portion of a write sequence, only the byte (D
the device. D and D remains unaltered.
[17:0]
[35:27]
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D
the device. D remains unaltered.
[26:0]
L
L–H During the data portion of a write sequence, only the byte (D
the device. D remains unaltered.
[26:0]
H
H
H
H
H
H
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Document Number: 001-06582 Rev. *D
Page 12 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Instruction Register
IEEE 1149.1 Serial Boundary Scan (JTAG)
Three-bit instructions are serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
page 16. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard 1149.1-2001. The TAP operates using JEDEC
standard 1.8V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
When the TAP controller is in the Capture IR state, the two least
significant bits are loaded with a binary “01” pattern to allow fault
isolation of the board level serial test path.
(V ) to prevent clocking of the device. TDI and TMS are inter-
SS
nally pulled up and may be unconnected. They may alternatively
be connected to V through a pull up resistor. TDO must be left
unconnected. Upon power up, the device comes up in a reset
state which does not interfere with the operation of the device.
Bypass Register
DD
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables data to be shifted through the SRAM
with minimal delay. The bypass register is set LOW (V ) when
the BYPASS instruction is executed.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
SS
Boundary Scan Register
Test Mode Select
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this pin unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can
be used to capture the contents of the Input and Output ring.
Test Data In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see “TAP Controller State
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSb) on any register.
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSb of the register is connected to
TDI and the LSb is connected to TDO.
Identification (ID) Register
Test Data Out (TDO)
The ID register is loaded with a vendor-specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the “Identification Register Definitions”
The TDO output pin is used to serially clock data out from the
registers. The output is active depending upon the current state
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSb) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (V ) for five rising
TAP Instruction Set
DD
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high Z state.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the “Instruction
RESERVED and must not be used. The other five instructions
are described below.
TAP Registers
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
Registers are connected between the TDI and TDO pins and
enables data to be scanned into and out of the SRAM test
circuitry. Only one register is selected at a time through the
instruction registers. Data is serially loaded into the TDI pin on
the rising edge of TCK. Data outputs on the TDO pin on the falling
edge of TCK.
Document Number: 001-06582 Rev. *D
Page 13 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
IDCODE
PRELOAD enables an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
before the selection of another boundary scan test operation.
The IDCODE instruction causes a vendor-specific 32-bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and enables
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction is
loaded into the instruction register upon power up or whenever
the TAP controller is given a test logic reset state.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data is shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High Z state until the next command is given
during the Update IR state.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the instruc-
tion register and the TAP controller is in the Capture-DR state, a
snapshot of data on the inputs and output pins is captured in the
boundary scan register.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller puts the
output bus into a tri-state mode.
The user must be aware that the TAP controller clock only oper-
ates at a frequency up to 20 MHz, while the SRAM clock oper-
ates more than an order of magnitude faster. Because there is a
large difference in the clock frequencies, it is possible that during
the Capture-DR state, an input or output undergoes a transition.
The TAP then tries to capture a signal while in transition (meta-
stable state). This does not harm the device but there is no guar-
antee as to the value that is captured. Repeatable results are not
possible.
The boundary scan register has a special bit located at bit 47.
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a High
Z condition.
To guarantee that the boundary scan register captures the cor-
rect value of a signal, the SRAM signal is stabilized long enough
This bit is set by entering the SAMPLE/PRELOAD or EXTEST
command, and then shifting the desired bit into that cell, during
the Shift-DR state. During Update-DR, the value loaded into that
shift register cell latches into the preload register. When the
EXTEST instruction is entered, this bit directly controls the output
Q-bus pins. Note that this bit is preset HIGH to enable the output
when the device is powered up, and also when the TAP controller
is in the Test Logic Reset state.
to meet the TAP controller's capture setup plus hold times (t
CS
and t ). The SRAM clock input is not captured correctly if there
CH
is no way in a design to stop (or slow) the clock during a SAM-
PLE/PRELOAD instruction. If this is an issue, it is still possible to
capture all other signals and simply ignore the value of the CK
and CK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-06582 Rev. *D
Page 14 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
TAP Controller State Diagram
Figure 2. Tap Controller State Diagram
TEST-LOGIC
1
RESET
0
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
1
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note
12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-06582 Rev. *D
Page 15 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
TAP Controller Block Diagram
Figure 3. Tap Controller Block Diagram
0
Bypass Register
Selection
TDI
Selection
Circuitry
2
1
0
0
0
TDO
Circuitry
Instruction Register
29
31 30
.
.
2
1
Identification Register
.
106 .
.
.
2
1
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
The Tap Electrical Characteristics table over the operating range follows.
Parameter
Description
Output HIGH Voltage
Test Conditions
= −2.0 mA
Min
1.4
1.6
Max
Unit
V
V
V
V
V
V
V
I
I
I
I
I
OH1
OH2
OL1
OL2
IH
OH
OH
OL
OL
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
= −100 μA
= 2.0 mA
V
0.4
0.2
V
= 100 μA
V
0.65 V
V
+ 0.3
V
DD
DD
Input LOW Voltage
–0.3
–5
0.35 V
5
V
IL
DD
Input and Output Load Current
GND ≤ V ≤ V
DD
μA
X
I
Notes
13. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
14. Overshoot: V (AC) < V + 0.35V (pulse width less than t /2)
/2), Undershoot: V (AC) > −0.3V (pulse width less than t
IH
DDQ
CYC
IL
CYC
15. All voltage referenced to ground.
Document Number: 001-06582 Rev. *D
Page 16 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
TAP AC Switching Characteristics
The Tap AC Switching Characteristics over the operating range follows.
Parameter
Description
Min
Max
Unit
ns
t
t
t
t
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
50
TCYC
20
MHz
ns
TF
TH
TL
20
20
TCK Clock LOW
ns
Setup Times
t
t
t
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
ns
ns
ns
TMSS
TDIS
CS
Hold Times
t
t
t
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
TMSH
TDIH
CH
Capture Hold after Clock Rise
Output Times
t
t
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
10
ns
ns
TDOV
TDOX
0
TAP Timing and Test Conditions
The Tap Timing and Test Conditions for the CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 follows.
0.9V
ALL INPUT PULSES
50Ω
1.8V
TDO
0.9V
0V
Z = 50
Ω
0
C = 20 pF
L
tTL
tTH
GND
(a)
Test Clock
TCK
tTCYC
tTMSH
tTMSS
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Notes
16. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
17. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
Document Number: 001-06582 Rev. *D
Page 17 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Identification Register Definitions
Value
Instruction Field
Description
CY7C1161V18
CY7C1176V18
000
CY7C1163V18
000
CY7C1165V18
Revision Number
(31:29)
000
000
Version number.
Cypress Device ID 11010010001000101 11010010001001101 11010010001010101 11010010001100101 Defines the type of
(28:12)
SRAM.
Cypress JEDEC ID
(11:1)
00000110100
1
00000110100
1
00000110100
1
00000110100
1
Enables unique
identification of
SRAM vendor.
ID Register
Presence (0)
Indicates the
presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
Bypass
3
1
ID
32
107
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between
TDI and TDO. This forces all SRAM output drivers to a High Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the input and output ring contents. Places the boundary scan register
between TDI and TDO. This operation does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operation.
Document Number: 001-06582 Rev. *D
Page 18 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Boundary Scan Order
Bit #
0
Bump ID
6R
Bit #
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Bump ID
11H
10G
9G
Bit #
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Bump ID
7B
6B
6A
5B
5A
4A
5C
4B
3A
1H
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
Bit #
81
Bump ID
3G
2G
1J
1
6P
82
2
6N
83
3
7P
11F
11G
9F
84
2J
4
7N
85
3K
3J
5
7R
86
6
8R
10F
11E
10E
10D
9E
87
2K
1K
2L
7
8P
88
8
9R
89
9
11P
10P
10N
9P
90
3L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
91
1M
1L
10C
11D
9C
92
93
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
10M
11N
9M
94
9D
95
11B
11C
9B
96
9N
97
11L
11M
9L
98
10B
11A
Internal
9A
99
100
101
102
103
104
105
106
10L
11K
10K
9J
8B
7C
9K
6C
3F
10J
11J
8A
1G
1F
7A
Document Number: 001-06582 Rev. *D
Page 19 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Power Up Sequence in QDR-II+ SRA
DLL Constraints
During power up, when the DOFF is tied HIGH, the DLL gets
locked after 2048 cycles of stable clock. QDR-II+ SRAMs must
be powered up and initialized in a predefined manner to prevent
undefined operations.
■ DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
KC Var
■ The DLL functions at frequencies down to 120 MHz
■ If the input clock is unstable and the DLL is enabled, then the
DLL locks onto an incorrect frequency, causing unstable SRAM
behavior. To avoid this, provide 2048 cycles stable clock to
relock to the desired clock frequency
Power Up Sequence
■ Apply power with DOFF tied HIGH (All other inputs can be
HIGH or LOW)
❐ Apply V before V
DD
DDQ
❐ Apply V
before V
or at the same time as V
DDQ
REF REF
■ Provide stable power and clock (K, K) for 2048 cycles to lock
the DLL
Power Up Waveforms
Figure 4. Power Up Waveforms
K
K
Start Normal
Operation
Unstable Clock
> 2048 Stable Clock
Clock Start (Clock Starts after V /V
DD DDQ
is Stable)
V
/V
+
V
/V Stable (< 0.1V DC per 50 ns)
DD DDQ
DD DDQ
Fix HIGH (tie to V
DDQ
)
DOFF
Document Number: 001-06582 Rev. *D
Page 20 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V
Latch up Current.................................................... > 200 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with Power Applied. –55°C to + 125°C
Operating Range
Ambient
Supply Voltage on V Relative to GND .......–0.5V to + 2.9V
V
DDQ
DD
Range
Commercial
Industrial
Temperature (T )
V
A
DD
Supply Voltage on V
Relative to GND..... –0.5V to + V
DD
DDQ
0°C to +70°C
1.8 ± 0.1V
1.4V to
DC Applied to Outputs in High Z ........–0.5V to V
+ 0.3V
V
DDQ
DD
–40°C to +85°C
DC Input Voltage ...............................–0.5V to V + 0.3V
DD
Electrical Characteristics
The DC Electrical Characteristics over the operating range follows.
Parameter
Description
Power Supply Voltage
IO Supply Voltage
Test Conditions
Min
1.7
1.4
Typ
Max
Unit
V
1.8
1.5
1.9
V
V
DD
V
V
V
V
V
V
V
I
V
DD
DDQ
OH
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
V
V
/2 – 0.12
/2 – 0.12
– 0.2
V
V
/2 + 0.12
/2 + 0.12
V
DDQ
DDQ
DDQ
V
OL
DDQ
I
I
= −0.1 mA, Nominal Impedance
V
V
V
OH(LOW)
OL(LOW)
IH
OH
OL
DDQ
DDQ
= 0.1 mA, Nominal Impedance
V
0.2
V
SS
V
+ 0.1
V
+ 0.15
– 0.1
REF
V
REF
DDQ
–0.15
V
V
IL
Input Leakage Current
Output Leakage Current
Input Reference Voltage
GND ≤ V ≤ V
−2
−2
2
μA
μA
V
X
I
DDQ
I
GND ≤ V ≤ V
Output Disabled
2
OZ
I
DDQ,
V
Typical Value = 0.75V
0.68
0.75
0.95
850
920
1020
1080
250
260
290
300
REF
I
V
Operating Supply
V
= Max, I
= 0 mA, 300 MHz
333 MHz
mA
mA
mA
mA
mA
mA
mA
mA
DD
DD
DD
OUT
CYC
f = f
= 1/t
max
375 MHz
400 MHz
I
Automatic Power Down
Current
Max V
,
300 MHz
SB1
DD
Both Ports Deselected,
333 MHz
375 MHz
400 MHz
V
≥ V or V ≤ V
IN
IH
IN
IL
f = f
= 1/t
,
max
CYC
Inputs Static
AC Electrical Characteristics
Over the operating range follows.
Parameter
Description
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min
Typ
–
Max
Unit
V
V
V
+ 0.2
V
+ 0.24
DDQ
IH
IL
REF
V
–0.24
–
V
– 0.2
V
REF
Notes
18. Power up: Is based upon a linear ramp from 0V to V (min) within 200 ms. During this time V < V and V
< V
.
DD
DD
IH
DD
DDQ
19. Output are impedance controlled. I = −(V
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
OH
DDQ
20. Output are impedance controlled. I = (V
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
OL
DDQ
21. V
(min) = 0.68V or 0.46V
, whichever is larger, V
(max) = 0.95V or 0.54V
, whichever is smaller.
DDQ
REF
DDQ
REF
22. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-06582 Rev. *D
Page 21 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter Description Test Conditions
Input Capacitance T = 25°C, f = 1 MHz,
Max
Unit
pF
C
5
6
7
IN
A
V
= 1.8V
DD
V
C
C
Clock Input Capacitance
Output Capacitance
pF
CLK
O
= 1.5V
DDQ
pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
165 FBGA
Package
Parameter
Description
Test Conditions
Unit
Θ
Thermal Resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
17.2
°C/W
JA
Θ
Thermal Resistance
(junction to case)
4.15
°C/W
JC
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms
VREF = 0.75V
0.75V
VREF
VREF
0.75V
R = 50Ω
OUTPUT
[23]
ALL INPUT PULSES
Z = 50Ω
0
OUTPUT
1.25V
Device
R = 50Ω
L
0.75V
Under
Device
Under
0.25V
Test
5 pF
VREF = 0.75V
Slew Rate = 2 V/ns
ZQ
Test
ZQ
RQ =
RQ =
250Ω
250Ω
INCLUDING
JIG AND
SCOPE
(a)
(b)
Notes
23. Unless otherwise noted, test conditions are based upon signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, V
= 1.5V, input
DDQ
pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC Test Loads.
OL OH
Document Number: 001-06582 Rev. *D
Page 22 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Switching Characteristics
Over the operating range
400 MHz
375 MHz
333 MHz
300 MHz
Cypress Consortium
Parameter Parameter
Description
Unit
Min Max Min Max Min Max Min Max
t
t
t
t
t
V
(Typical) to the First Access
1
–
1
–
1
–
1
–
ms
ns
POWER
CYC
KH
DD
t
t
t
t
K Clock Cycle Time
2.50 8.40 2.66 8.40 3.0 8.40 3.3 8.40
KHKH
KHKL
KLKH
KHKH
Input Clock (K/K) HIGH
Input Clock (K/K) LOW
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
t
t
CYC
KL
CYC
K Clock Rise to K Clock Rise
(rising edge to rising edge)
1.06
1.13
1.28
1.40
ns
KHKH
Setup Times
t
t
t
t
t
t
Address Setup to K Clock Rise
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
ns
ns
ns
SA
AVKH
IVKH
IVKH
Control Setup to K Clock Rise (RPS, WPS)
SC
Double Data Rate Control Setup to Clock (K, K) 0.28
Rise (BWS , BWS BWS , BWS )
0.28
0.28
0.28
SCDDR
0
1,
2
3
t
t
D Setup to Clock (K/K) Rise
[X:0]
0.28
–
0.28
–
0.28
–
0.28
–
ns
SD
DVKH
Hold Times
t
t
t
t
t
t
Address Hold after K Clock Rise
Control Hold after K Clock Rise (RPS, WPS)
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
ns
ns
ns
HA
KHAX
KHIX
KHIX
HC
Double Data Rate Control Hold after Clock (K/K) 0.28
Rise (BWS , BWS BWS , BWS )
0.28
0.28
0.28
HCDDR
0
1,
2
3
t
t
D Hold after Clock (K/K) Rise
[X:0]
0.28
–
0.28
–
0.28
–
0.28
–
ns
HD
KHDX
Output Times
t
t
t
t
K/K Clock Rise to Data Valid
–
0.45
–
–
0.45
–
–
0.45
–
–
0.45
–
ns
ns
CO
CHQV
CHQX
Data Output Hold after Output K/K Clock Rise –0.45
(Active to Active)
–0.45
–0.45
–0.45
DOH
t
t
t
t
t
t
t
t
t
t
t
t
K/K Clock Rise to Echo Clock Valid
Echo Clock Hold after K/K Clock Rise
Echo Clock High to Data Valid
–
0.45
–
–
0.45
–
–
0.45
–
–
0.45
–
ns
ns
ns
ns
ns
ns
CCQO
CQOH
CQD
CHCQV
CHCQX
CQHQV
CQHQX
CQHCQL
CQHCQH
–0.45
–
–0.45
–0.45
–0.45
0.2
–
0.2
–
0.2
–
0.2
–
Echo Clock High to Data Invalid
–0.2
0.81
0.81
–0.2
0.88
0.88
–0.2
1.03
1.03
–0.2
1.15
1.15
CQDOH
CQH
Output Clock (CQ/CQ) HIGH
–
–
–
–
CQ Clock Rise to CQ Clock Rise
–
–
–
–
CQHCQH
(rising edge to rising edge)
t
t
t
t
t
t
Clock (K/K) Rise to High Z (Active to High Z)
–
0.45
–
–
0.45
–
–
0.45
–
–
0.45
–
ns
ns
ns
CHZ
CLZ
CHQZ
CHQX1
QVLD
Clock (K/K) Rise to Low Z
–0.45
–0.45
–0.45
–0.45
Echo Clock High to QVLD Valid
–0.20 0.20 –0.20 0.20 –0.20 0.20 –0.20 0.20
QVLD
Notes
24. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
25. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V minimum initially before a Read or Write operation can
POWER
DD
be initiated.
26. These parameters are extrapolated from the input timing parameters (t
– 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t
) is already
KHKH
KC Var
included in the t
). These parameters are only guaranteed by design and are not tested in production.
KHKH
27. t
, t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ± 100 mV from steady state voltage.
CHZ CLZ
28. At any voltage and temperature t
is less than t
and t
less than t
.
CHZ
CLZ
CHZ
CO
29. t
spec is applicable for both rising and falling edges of QVLD signal.
QVLD
Document Number: 001-06582 Rev. *D
Page 23 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Switching Characteristics
[23, 24]
Over the operating range
(continued)
400 MHz
375 MHz
333 MHz
300 MHz
Cypress Consortium
Parameter Parameter
Description
Unit
Min Max Min Max Min Max Min Max
DLL Timing
t
t
t
t
t
t
Clock Phase Jitter
–
0.20
–
–
0.20
–
–
0.20
–
–
0.20
–
ns
Cycles
ns
KC Var
KC Var
DLL Lock Time (K)
2048
30
2048
30
2048
30
2048
30
KC lock
KC Reset
KC lock
KC Reset
K Static to DLL Reset
–
–
–
–
Note
30. Hold to >V or <V .
IH
IL
Document Number: 001-06582 Rev. *D
Page 24 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Switching Waveforms
Read/Write/Deselect Sequence
Figure 6. Waveform for 2.5 Cycle Read Latency
WRITE
3
READ
4
NOP
1
READ
2
WRITE
5
NOP
6
7
8
K
t
t
KL
t
t
KH
CYC
KHKH
K
RPS
t
t
SC HC
t
t
SC
HC
WPS
A
A0
A1
A2
A3
t
t
HD
t
t
HD
SA
HA
t
SD
t
SD
D11
D12
D30
D32
D33
t
D10
QVLD
D13
D31
D
QVLD
t
QVLD
t
DOH
t
t
CQDOH
CO
t
t
CHZ
t
CLZ
t
CQD
Q
Q00 Q01 Q02
CCQO
Q20 Q21 Q22
Q23
Q03
(Read Latency = 2.5 Cycles)
CQOH
CQ
CQ
CCQO
t
t
t
CQHCQH
CQH
CQOH
DON’T CARE
UNDEFINED
Notes
31. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
32. Outputs are disabled (High Z) one clock cycle after a NOP.
33. In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 001-06582 Rev. *D
Page 25 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Ordering Information
Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com
for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
400 CY7C1161V18-400BZC
CY7C1176V18-400BZC
CY7C1163V18-400BZC
CY7C1165V18-400BZC
CY7C1161V18-400BZXC
CY7C1176V18-400BZXC
CY7C1163V18-400BZXC
CY7C1165V18-400BZXC
CY7C1161V18-400BZI
CY7C1176V18-400BZI
CY7C1163V18-400BZI
CY7C1165V18-400BZI
CY7C1161V18-400BZXI
CY7C1176V18-400BZXI
CY7C1163V18-400BZXI
CY7C1165V18-400BZXI
375 CY7C1161V18-375BZC
CY7C1176V18-375BZC
CY7C1163V18-375BZC
CY7C1165V18-375BZC
CY7C1161V18-375BZXC
CY7C1176V18-375BZXC
CY7C1163V18-375BZXC
CY7C1165V18-375BZXC
CY7C1161V18-375BZI
CY7C1176V18-375BZI
CY7C1163V18-375BZI
CY7C1165V18-375BZI
CY7C1161V18-375BZXI
CY7C1176V18-375BZXI
CY7C1163V18-375BZXI
CY7C1165V18-375BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Commercial
Industrial
Commercial
Industrial
Document Number: 001-06582 Rev. *D
Page 26 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com
for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
333 CY7C1161V18-333BZC
CY7C1176V18-333BZC
CY7C1163V18-333BZC
CY7C1165V18-333BZC
CY7C1161V18-333BZXC
CY7C1176V18-333BZXC
CY7C1163V18-333BZXC
CY7C1165V18-333BZXC
CY7C1161V18-333BZI
CY7C1176V18-333BZI
CY7C1163V18-333BZI
CY7C1165V18-333BZI
CY7C1161V18-333BZXI
CY7C1176V18-333BZXI
CY7C1163V18-333BZXI
CY7C1165V18-333BZXI
300 CY7C1161V18-300BZC
CY7C1176V18-300BZC
CY7C1163V18-300BZC
CY7C1165V18-300BZC
CY7C1161V18-300BZXC
CY7C1176V18-300BZXC
CY7C1163V18-300BZXC
CY7C1165V18-300BZXC
CY7C1161V18-300BZI
CY7C1176V18-300BZI
CY7C1163V18-300BZI
CY7C1165V18-300BZI
CY7C1161V18-300BZXI
CY7C1176V18-300BZXI
CY7C1163V18-300BZXI
CY7C1165V18-300BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Commercial
Industrial
Commercial
Industrial
Document Number: 001-06582 Rev. *D
Page 27 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Package Diagram
Figure 7. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180
BOTTOM VIEW
PIN 1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
-0.06
PIN 1 CORNER
Ø0.50
(165X)
+0.14
1
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00
5.00
10.00
13.00 0.10
B
13.00 0.10
B
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
SEATING PLANE
C
51-85180-*A
Document Number: 001-06582 Rev. *D
Page 28 of 29
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Document History Page
Document Title: CY7C1161V18/CY7C1176V18/CY7C1163V18/CY7C1165V18, 18-Mbit QDR™-II+ SRAM 4-Word Burst Archi-
tecture (2.5 Cycle Read Latency)
Document Number: 001-06582
Orig. of
Change
REV.
ECN No. Issue Date
Description of Change
**
430351
461654
See ECN
See ECN
NXR
New data sheet
*A
NXR
Revised the MPNs from
CY7C1176BV18 to CY7C1176V18
CY7C1163BV18 to CY7C1163V18
CY7C1165BV18 to CY7C1165V18
Changed t and t from 40 ns to 20 ns, changed t
, t
, t , t
, t
,
TH
TL
TMSS TDIS CS TMSH TDIH
t
from 10 ns to 5 ns and changed t
from 20 ns to 10 ns in TAP AC
CH
TDOV
Switching Characteristics table
Modified power up waveform
*B
497629
See ECN
NXR
Changed the V
operating voltage to 1.4V to V in the Features section, in
DDQ DD
Operating Range table and in the DC Electrical Characteristics table
Added foot note in page 1
Changed the Maximum rating of Ambient Temperature with Power Applied from
–10°C to +85°C to –55°C to +125°C
Changed V
(max) spec from 0.85V to 0.95V in the DC Electrical Character-
REF
istics table and in the note below the table
Updated foot note 22 to specify Overshoot and Undershoot Spec
Updated Θ and Θ values
JA
JC
Removed x9 part and its related information
Updated footnote 25
*C
1167806
See ECN VKN/KKVTMP Converted from preliminary to final
Added x8 and x9 parts
Changed I values from 800 mA to 1080 mA for 400 MHz, 766 mA to 1020 mA
DD
for 375 MHz, 708 mA to 920 mA for 333 MHz, 663 mA to 850 mA for 300 MHz
Changed I values from 235 mA to 300 mA for 400 MHz, 227 mA to 290 mA
SB
for 375 MHz, 212 mA to 260 mA for 333 MHz, 201 mA to 250 mA for 300 MHz
Changed t
spec to 8.4 ns for all speed bins
CYC(max)
Changed Θ value from 13.48 °C/W to 17.2 °C/W
JA
Updated Ordering Information table
*D
2199066 See ECN
VKN/AESA Added footnote# 22 related to I
DD
© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-06582 Rev. *D
Revised March 06, 2008
Page 29 of 29
QDR™ is a trademark of Cypress Semiconductor Corp. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All
product and company names mentioned in this document are the trademarks of their respective holders.
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