CY7C1034DV33
6-Mbit (256K X 24) Static RAM
Features
Functional Description
■ High speed
The CY7C1034DV33 is a high performance CMOS static RAM
organized as 256K words by 24 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
❐ t = 10 ns
AA
■ Low active power
❐ I
= 175 mA at 10 ns
■ Low CMOS standby power
❐ I = 25 mA
CC
To write to the device, enable the chip (CE LOW, CE HIGH,
1
2
and CE LOW) while forcing the Write Enable (WE) input LOW.
3
To read from the device, enable the chip by taking CE LOW, CE
SB2
1
2
HIGH, and CE LOW, while forcing the Output Enable (OE) LOW
7 for a complete description of Read and Write modes.
3
■ Operating voltages of 3.3 ± 0.3V
■ 2.0V data retention
The 24 IO pins (IO to IO ) are placed in a high impedance state
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
0
23
when the device is deselected (CE HIGH, CE LOW, or CE
1
2
3
HIGH) or when the output enable (OE) is HIGH during a write
operation. (CE LOW, CE HIGH, CE LOW, and WE LOW).
1
2
3
■ Easy memory expansion with CE , CE , and CE features
1
2
3
■ Available in Pb-free standard 119-Ball PBGA
Logic Block Diagram
INPUT BUFFER
IO0 – IO23
256K x 24
ARRAY
A
(9:0)
CE1, CE2, CE3
COLUMN
DECODER
WE
OE
CONTROL LOGIC
A
(17:10)
Cypress Semiconductor Corporation
Document Number: 001-08351 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 16, 2009
CY7C1034DV33
DC Input Voltage ............................... –0.5V to V + 0.5V
Maximum Ratings
CC
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage............. ...............................>2001V
(MIL-STD-883, Method 3015)
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Latch up Current...................................................... >200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Supply Voltage on V Relative to GND ....–0.5V to +4.6V
CC
Ambient
Range
V
CC
DC Voltage Applied to Outputs
in High Z State ................................... –0.5V to V + 0.5V
Temperature
CC
Industrial
–40°C to +85°C
3.3V ± 0.3V
DC Electrical Characteristics
Over the operating range
–10
Parameter
Description
Test Conditions
= Min, I = –4.0 mA
Unit
Min
Max
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
V
V
2.4
V
V
OH
OL
IH
CC
OH
V
V
V
I
= Min, I = 8.0 mA
0.4
+ 0.3
CC
OL
2.0
–0.3
–1
V
V
CC
[2]
0.8
+1
V
IL
Input Leakage Current
Output Leakage Current
GND < V < V
μA
μA
mA
IX
I
CC
I
I
GND < V
< V , output disabled
–1
+1
OZ
CC
OUT
CC
V
Operating Supply
V
= Max, f = f
= 1/t ,
RC
175
CC
CC
MAX
Current
I
= 0 mA CMOS levels
OUT
I
I
Automatic CE Power Down Max V , CE , CE > V CE < V ,
30
25
mA
mA
SB1
SB2
CC
1
3
IH,
2
IL
Current — TTL Inputs
V
> V or V < V , f = f
IN
IH
IN
IL
MAX
Automatic CE Power Down Max V , CE , CE > V – 0.3V, CE < 0.3V,
CC
1
3
CC
2
Current — CMOS Inputs
V
> V – 0.3V, or V < 0.3V, f = 0
IN CC IN
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Input Capacitance
IO Capacitance
Test Conditions
Max
Unit
C
T = 25°C, f = 1 MHz, V = 3.3V
8
pF
pF
IN
A
CC
C
10
OUT
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
119-Ball
PBGA
Parameter
Description
Test Conditions
Unit
Θ
Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch,
four layer printed circuit board
20.31
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
8.35
°C/W
JC
Notes
2.
V
(min) = –2.0V and V (max) = V + 2V for pulse durations of less than 20 ns.
IH CC
IL
3. CE refers to a combination of CE , CE , and CE . CE is active LOW when CE is LOW, CE is HIGH, and CE is LOW. CE is HIGH when CE is HIGH or CE is LOW
1
2
3
1
2
3
1
2
or CE is HIGH.
3
Document Number: 001-08351 Rev. *C
Page 3 of 9
CY7C1034DV33
Figure 2. AC Test Loads and Waveform
50Ω
R1 317 Ω
3.3V
= 1.5V
OUTPUT
V
TH
OUTPUT
Z = 50Ω
0
30 pF*
R2
351Ω
5 pF*
*Including jig
and scope
(a)
*Capacitive Load consists of all
components of the test environment
(b)
All input pulses
90%
3.0V
GND
90%
10%
10%
Fall Time:> 1V/ns
Rise Time > 1V/ns
(c)
AC Switching Characteristics
Over the operating range
–10
Parameter
Description
Unit
Min
Max
Read Cycle
[6]
t
t
t
t
t
t
t
t
t
t
t
t
V
(Typical) to the First Access
100
10
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
power
RC
CC
Read Cycle Time
Address to Data Valid
10
AA
Data Hold from Address Change
3
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
CE Active LOW to Data Valid
10
5
OE LOW to Data Valid
OE LOW to Low Z
1
3
0
[7]
OE HIGH to High Z
5
5
CE Active LOW to Low Z
CE Deselect HIGH to High Z
CE Active LOW to Power Up
CE Deselect HIGH to Power Down
10
PD
Notes
4. Valid SRAM operation does not occur until the power supplies reach the minimum operating V (3.0V). 100 μs (t
) after reaching the minimum operating V ,
DD
DD
power
normal SRAM operation begins including reduction in V to the data retention (V
, 2.0V) voltage.
DD
CCDR
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use
6.
7.
t
t
gives the minimum amount of time that the power supply is at typical V values until the first memory access is performed.
POWER
, t
CC
, t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady
HZOE HZCE HZWE LZOE LZCE
LZWE
state voltage.
8. These parameters are guaranteed by design and are not tested.
Document Number: 001-08351 Rev. *C
Page 4 of 9
CY7C1034DV33
AC Switching Characteristics (continued)
[5]
Over the operating range
–10
Parameter
Description
Unit
Min
Max
Write Cycle
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
10
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE Active LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
SCE
AW
7
0
HA
0
SA
7
PWE
SD
Data Setup to Write End
Data Hold from Write End
5.5
0
HD
[7]
WE HIGH to Low Z
3
LZWE
HZWE
[7]
WE LOW to High Z
5
Data Retention Characteristics
Over the operating range
Parameter
Description
for Data Retention
CC
Conditions
Min
Typ
Max
Unit
V
V
2
V
DR
I
Data Retention Current9
V
= 2V, CE , CE > V – 0.2V,
25
mA
CCDR
CC
2
1
3
CC
CE < 0.2V,V > V – 0.2V or V < 0.2V
IN
CC
IN
t
t
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
CDR
[12]
t
R
RC
Figure 3. Data Retention Waveform
DATA RETENTION MODE
3.0V
3.0V
V
VDR > 2V
CC
t
t
R
CDR
CE
Notes
9. The internal write time of the memory is defined by the overlap of CE LOW, CE HIGH, CE LOW, and WE LOW. Chip enables must be active and WE must be LOW
1
2
3
to initiate a write and the transition of any of these signals terminates the write. The input data setup and hold timing are referenced to the leading edge of the signal
that terminates the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
11. Tested initially and after any design or process changes that may affect these parameters.
and t
.
HZWE
SD
12. Full device operation requires linear V ramp from V to V
> 50 μs or stable at V
> 50 μs.
CC
DR
CC(min)
CC(min)
Document Number: 001-08351 Rev. *C
Page 5 of 9
CY7C1034DV33
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled)
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
V
CC
ICC
t
PU
SUPPLY
CURRENT
50%
50%
ISB
Figure 6. Write Cycle No. 1 (CE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA IO
DATA VALID
Notes
13. Device is continuously selected. OE, CE = V .
IL
14. WE is HIGH for read cycle.
15. Address valid before or similar to CE transition LOW.
16. Data IO is high impedance if OE = V
.
IH
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 001-08351 Rev. *C
Page 6 of 9
CY7C1034DV33
Switching Waveforms (continued)
Figure 7. Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
t
PWE
SA
WE
OE
t
t
SD
HD
DATA VALID
IN
DATA IO
NOTE 18
t
HZOE
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA IO
NOTE 18
DATA VALID
t
t
LZWE
HZWE
Truth Table
CE
H
X
X
L
CE
CE
X
X
H
L
OE
WE
X
IO – IO
23
Mode
Power
1
2
3
0
X
X
X
X
L
High Z
High Z
High Z
Power Down
Power Down
Power Down
Read
Standby (I
Standby (I
Standby (I
)
)
)
SB
SB
SB
L
X
X
X
H
H
H
H
Full Data Out
Full Data In
High Z
Active (I
Active (I
)
)
)
CC
CC
CC
L
L
X
H
L
Write
L
L
H
Selected, Outputs Disabled Active (I
Note
18. During this period, the IOs are in the output state and input signals are not applied.
Document Number: 001-08351 Rev. *C
Page 7 of 9
CY7C1034DV33
Ordering Information
Speed
Package
Name
Operating
Range
Ordering Code
(ns)
Package Type
10
CY7C1034DV33-10BGXI
51-85115 119-Ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-Free)
Industrial
Package Diagram
Figure 9. 119-Ball PBGA (14 x 22 x 2.4 mm)
51-85115-*B
Document Number: 001-08351 Rev. *C
Page 8 of 9
CY7C1034DV33
Document History Page
Document Title: CY7C1034DV33 6-Mbit (256K X 24) Static RAM
Document Number: 001-08351
Orig. of
Change
Submission
Date
REV. ECN NO.
Description of Change
**
469517
499604
NXR
NXR
See ECN New data sheet
*A
See ECN Added note 1 for NC pins
Changed I specification from 150 mA to 185 mA
CC
Updated Test Condition for I in DC Electrical Characteristics table
CC
Added note for t
, t
, t
, t , t , t
in AC Switching Characteristics
ACE LZCE HZCE PU PD SCE
Table on page 4
*B
*C
1462586 VKN/SFV
2644842 VKN/PYRS
See ECN Converted from preliminary to final
Updated block diagram
Changed I specification from 185 mA to 225 mA
CC
Updated thermal specs
01/23/09
Replaced Commercial range with the Industrial
Replaced 8 ns speed with 10 ns
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Document Number: 001-08351 Rev. *C
Revised January 16, 2009
Page 9 of 9
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