CY7C09079V/89V/99V
CY7C09179V/89V/99V
CY7C09079V/89V/99V
CY7C09179V/89V/99V
3.3V 32K/64K/128K x 8/9
Synchronous Dual-Port Static RAM
■ 3.3V low operating power
Features
■ True Dual-Ported memory cells which enable simultaneous
access of the same memory location
■ Active= 115 mA (typical)
■ 6 Flow-Through and Pipelined devices
■ 32K x 8/9 organizations (CY7C09079V/179V)
■ 64K x 8/9 organizations (CY7C09089V/189V)
■ 128K x 8/9 organizations (CY7C09099V/199V)
■ 3 Modes
■ Standby= 10 μA (typical)
■ Fully synchronous interface for easier operation
■ Burst counters increment addresses internally
■ Shorten cycle times
■ Minimize bus noise
■ Flow-Through
■ Supported in Flow-Through and Pipelined modes
■ Pipelined
■ Dual Chip Enables for easy depth expansion
■ Automatic power down
■ Burst
■ Commercial and Industrial temperature ranges
■ Available in 100-pin TQFP
■ Pipelined output mode on both ports enables fast 100 MHz
operation
■ 0.35-micron CMOS for optimum speed and power
■ Pb-free packages available
Logic Block Diagram
R/W
R/W
OE
L
R
OE
L
R
CE
CE
CE
CE
0L
1L
0R
1R
1
1
0
0
0/1
0/1
1
0
0
1
0/1
0/1
FT/Pipe
FT/Pipe
L
R
8/9
8/9
7/8R
I/O –I/O
I/O –I/O
0L
7/8L
0R
I/O
Control
I/O
Control
15/16/17
15/16/17
A –A
A –A
14/15/16R
0
14/15/16L
0
Counter/
Counter/
Address
Register
Decode
CLK
CLK
ADS
L
R
R
R
R
Address
Register
Decode
True Dual-Ported
ADS
L
RAM Array
CNTEN
CNTEN
L
CNTRST
CNTRST
L
Notes
1. See page 6 for Load Conditions.
2. I/O –I/O for x8 devices, I/O –I/O for x9 devices.
0
7
0
8
3. A –A for 32K, A –A for 64K, and A –A for 128K devices.
0
14
0
15
0
16
Cypress Semiconductor Corporation
Document #: 38-06043 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 10, 2008
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Pin Configurations (continued
Figure 2. 100-Pin TQFP (Top View0 - CY7C09199V (128K x 9), CY7C09189V (64K x 9),CY7C09179V (32K x 9)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
2
NC
A7L
3
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R
A16R
GND
NC
A8L
4
A9L
5
A10L
A11L
A12L
A13L
A14L
A15L
A16L
VCC
NC
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
[8]
[9]
NC
NC
NC
NC
NC
NC
CE0L
CE1L
CE0R
CE1R
CNTRSTL
R/WL
CNTRSTR
R/WR
OEL
OER
FT/PIPEL
FT/PIPER
GND
NC
NC
24
25
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Document #: 38-06043 Rev. *C
Page 3 of 21
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Selection Guide
CY7C09079V/89V/99V CY7C09079V/89V/99V
CY7C09179V/89V/99V CY7C09179V/89V/99V
CY7C09079V/89V/99V
CY7C09179V/89V/99V-6
CY7C09079V/89V/99V
CY7C09179V/89V/99V-7
Description
-9
-12
f
(MHz)
100
6.5
83
67
50
MAX2
(Pipelined)
Max. Access Time
(ns) (Clock to Data,
Pipelined)
7.5
9
12
Typical Operating
175
25
155
25
135
20
115
20
Current I (mA)
CC
Typical Standby
Current for I
SB1
(mA) (Both Ports
TTL Level)
Typical Standby
10 μA
10 μA
10 μA
10 μA
Current for I
SB3
(μA) (Both Ports
CMOS Level)
Pin Definitions
Left Port
Right Port
Description
A
–A
A
–A
Address Inputs (A –A for 32K; A –A for 64K; and A –A for 128K devices).
14 15 16
0L
16L
0R
16R
0
0
0
ADS
ADS
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads
the burst counter with the address present on the address pins.
L
R
CE ,CE
CE ,CE
Chip Enable Input. To select either the left or right port, both CE AND CE must be asserted
0L
1L
0R
1R
0
1
to their active states (CE ≤ V and CE ≥ V ).
0
IL
1
IH
CLK
CLK
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f
.
L
R
MAX
CNTEN
CNTEN
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are
asserted LOW.
L
R
CNTRST
CNTRST
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its
respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
L
R
I/O –I/O
I/O –I/O
Data Bus Input/Output (I/O –I/O for x8 devices; I/O –I/O for x9 devices).
0L
8L
0R
8R
0
7
0
8
OE
OE
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during
read operations.
L
R
R/W
R/W
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
L
R
FT/PIPE
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
L
FT/PIPE
R
GND
NC
Ground Input.
No Connect.
Power Input.
V
CC
Notes
8. This pin is NC for CY7C09179V.
9. This pin is NC for CY7C09179V and CY7C09189V
Document #: 38-06043 Rev. *C
Page 4 of 21
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Static Discharge Voltage............................................>2001V
Latch-Up Current.....................................................>200 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Operating Range
Storage Temperature................................. –65°C to +150°C
Ambient Temperature with Power Applied..–55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +4.6V
DC Voltage Applied to
Ambient
Range
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
Commercial
3.3V ± 300 mV
Industrial
3.3V ± 300 mV
Outputs in High Z State ...........................–0.5V to V +0.5V
CC
DC Input Voltage .....................................–0.5V to V +0.5V
CC
Output Current into Outputs (LOW)............................. 20 mA
Electrical Characteristics Over the Operating Range
CY7C09079V/89V/99V
CY7C09179V/89V/99V
[1]
[1]
-6
-7
-9
-12
Parameter
Description
V
V
Output HIGH Voltage (V = Min. I
–4.0 mA)
=
=
2.4
2.4
2.0
2.4
2.0
2.4
V
V
OH
CC
OH
Output LOW Voltage (V = Min. I
0.4
0.8
0.4
0.8
0.4
0.8
0.4
0.8
OL
CC
OH
+4.0 mA)
V
V
I
Input HIGH Voltage
Input LOW Voltage
Output Leakage Current
2.0
2.0
V
V
IH
IL
–10
10 –10
175 320
10 –10
10 –10
10 μA
115 205 mA
mA
OZ
I
I
I
I
Operating Current
(V =Max. I =0 mA)
Outputs Disabled
Commercial.
155 275
275 390
135 225
185 295
CC
CC
OUT
Industrial
Standby Current (Both
Commercial.
25
95
25
85
20 65
35 75
20
50 mA
mA
SB1
SB2
SB3
Ports TTL Level)
CE
L
Industrial
85 120
& CE ≥ V , f = f
R
IH
MAX
Standby Current (One
Commercial.
115 175
10 250
105 165
165 210
95 150
105 160
85 140 mA
mA
Port TTL Level)
CE |
L
Industrial
CE ≥ V , f = f
R
IH
MAX
Standby Current (Both
Ports CMOS Level)
Commercial.
10 250
10 250
10 250
10 250
10 250 μA
Industrial
μA
CE & CE ≥ V – 0.2V,
L
R
CC
f = 0
I
Standby Current (One
Port CMOS Level)
Commercial
105 135
95 125
125 170
85 115
95 125
75 100 mA
mA
SB4
Industrial
CE | CE ≥ V , f = f
L
R
IH
MAX
Capacitance
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max
10
Unit
pF
C
C
Input Capacitance
Output Capacitance
IN
A
V
= 3.3V
CC
10
pF
OUT
Notes
10. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
11. Industrial parts are available in CY7C09099V and CY7C09199V only.
12. CE and CE are internal signals. To select either the left or right port, both CE AND CE must be asserted to their active states (CE ≤ V and CE ≥ V ).
L
R
0
1
0
IL
1
IH
Document #: 38-06043 Rev. *C
Page 5 of 21
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Figure 3. AC Test Loads
3.3V
3.3V
R
TH
= 250Ω
R1 = 590Ω
OUTPUT
C = 30 pF
OUTPUT
C = 30 pF
R1 = 590Ω
OUTPUT
C = 5 pF
R2 = 435Ω
R2 = 435Ω
V
TH
= 1.4V
(a) Normal Load (Load 1)
(c) Three-State Delay(Load 2)
(b) Thévenin Equivalent (Load 1)
(Used for t
, t
, & t
CKLZ OLZ OHZ
including scope and jig)
Figure 4. AC Test Loads (Applicable to -6 and -7 only)
ALL INPUTPULSES
90%
Z = 50
Ω
R = 50Ω
0
OUTPUT
3.0V
GND
90%
10%
C
10%
3 ns
3 ns
≤
V
TH
= 1.4V
≤
(a) Load 1 (-6 and -7 only)
Figure 5. Load Derating Curve
0.60
0.50
0.40
0.30
0.20
0.1 0
0.00
1 0
1 5
20
25
30
35
Capacitance (pF)
Note
13. Test Conditions: C = 10 pF.
Document #: 38-06043 Rev. *C
Page 6 of 21
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Switching Characteristics Over the Operating Range
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Parameter
Description
-6
-7
-9
-12
Min Max Min Max Min Max Min Max
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
f
Flow-Through
53
45
83
40
67
33
50
MAX1
MAX2
CYC1
CYC2
CH1
CL1
CH2
CL2
R
Max
Max
Pipelined
100
Clock Cycle Time - Flow-Through
Clock Cycle Time - Pipelined
Clock HIGH Time - Flow-Through
Clock LOW Time - Flow-Through
Clock HIGH Time - Pipelined
Clock LOW Time - Pipelined
Clock Rise Time
19
10
6.5
6.5
4
22
12
7.5
7.5
5
25
15
12
12
6
30
20
12
12
8
4
5
6
8
3
3
3
3
3
3
3
3
Clock Fall Time
F
Address Set-Up Time
3.5
0
4
0
4
1
4
1
4
1
4
1
4
1
5
1
4
1
4
1
4
1
4
1
4
1
4
1
5
1
4
1
SA
Address Hold Time
HA
Chip Enable Set-Up Time
Chip Enable Hold Time
R/W Set-Up Time
3.5
0
4
SC
0
HC
3.5
0
4
SW
R/W Hold Time
0
HW
Input Data Set-Up Time
Input Data Hold Time
3.5
0
4
SD
0
HD
ADS Set-Up Time
3.5
0
4
SAD
HAD
SCN
HCN
SRST
HRST
OE
ADS Hold Time
0
CNTEN Set-Up Time
3.5
0
4.5
0
CNTEN Hold Time
CNTRST Set-Up Time
CNTRST Hold Time
3.5
0
4
0
Output Enable to Data Valid
OE to Low Z
8
9
10
12
OLZ
OHZ
2
1
2
1
2
1
2
1
OE to High Z
7
7
7
20
9
7
Clock to Data Valid - Flow-Through
Clock to Data Valid - Pipelined
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
15
6.5
18
7.5
25
12
CD1
CD2
DC
CKHZ
CKLZ
2
2
2
2
2
2
2
2
2
2
2
2
9
9
9
9
Port to Port Delays
t
t
Write Port Clock HIGH to Read Data Delay
Clock to Clock Set-Up Time
30
9
35
10
40
15
40
15
ns
ns
CWDD
CCS
Notes
14. Test conditions used are Load 2.
15. This parameter is guaranteed by design, but it is not production tested.
Document #: 38-06043 Rev. *C
Page 7 of 21
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Switching Waveforms (continued)
Figure 6. Read Cycle for Flow-Through Output (FT/PIPE = V )
IL
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
tSC
tHC
CE1
R/W
tSW
tSA
tHW
tHA
An
An+1
An+2
An+3
ADDRESS
DATAOUT
tCKHZ
Qn+2
tDC
tDC
Qn
tCD1
Qn+1
tCKLZ
tOHZ
tOLZ
OE
tOE
Notes
16. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
17. ADS = V , CNTEN and CNTRST = V
.
IH
IL
18. The output is disabled (high-impedance state) by CE =V or CE = V following the next rising edge of the clock.
0
IH
1
IL
19. Addresses do not have to be accessed sequentially since ADS = V constantly loads the address on the rising edge of the CLK. Numbers are for reference
IL
only.
Document #: 38-06043 Rev. *C
Page 8 of 21
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Switching Waveforms (continued)
Figure 7. Read Cycle for Pipelined Operation (FT/PIPE = V )
IH
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
tSC
tHC
CE1
R/W
tSW
tSA
tHW
tHA
ADDRESS
DATAOUT
An
An+1
An+2
An+3
tDC
1 Latency
tCD2
Qn
Qn+1
Qn+2
tOHZ
tCKLZ
tOLZ
OE
t
OE
Figure 8. Bank Select Pipelined Read
-
tCYC2
tCH2
tCL2
CLKL
tHA
tSA
A3
A4
ADDRESS(B1)
A5
A0
A1
A2
tHC
tSC
CE0(B1)
tCD2
tCD2
tCD2
tCKHZ
tHC
tCKHZ
tSC
D0
D3
D1
DATAOUT(B1)
ADDRESS(B2)
tHA
tSA
tDC
A2
tDC
A3
tCKLZ
A4
A5
A0
A1
tHC
tSC
CE0(B2)
tCD2
tCKHZ
tCD2
tSC
tHC
DATAOUT(B2)
D4
D2
tCKLZ
tCKLZ
Document #: 38-06043 Rev. *C
Page 9 of 21
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Switching Waveforms (continued)
Figure 9. Left Port Write to Flow-Through Right Port Read
CLKL
R/WL
tHW
tSW
tHA
tSA
NO
MATCH
ADDRESSL
DATAINL
MATCH
tHD
tSD
VALID
tCCS
CLKR
R/WR
tCD1
tSW tHW
tSA tHA
NO
MATCH
MATCH
ADDRESSR
tCWDD
tCD1
DATAOUTR
VALID
VALID
tDC
tDC
Notes
20. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS
(B1)
= ADDRESS
.
(B2)
21. OE and ADS = V ; CE
, CE
, R/W, CNTEN, and CNTRST = V
.
IH
IL
1(B1)
1(B2)
22. The same waveforms apply for a right port write to flow-through left port read.
23. CE and ADS = V ; CE , CNTEN, and CNTRST = V
.
IH
0
IL
1
24. OE = V for the right port, which is being read from. OE = V for the left port, which is being written to.
IL
IH
25. It t
≤ maximum specified, then data from right port READ is not valid until the maximum specified for t
. If t >maximum specified, then data is not valid
CCS
CCS
CWDD
until t
+ t
. t
does not apply in this case.
CCS
CD1 CWDD
Document #: 38-06043 Rev. *C
Page 10 of 21
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Switching Waveforms (continued)
Figure 10. Pipelined Read-to-Write-to-Read (OE = V )
IL
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
R/W
tSW
tHW
tSW
tHW
An
An+1
An+2
An+2
An+3
An+4
ADDRESS
DATAIN
tSD tHD
tSA
tHA
Dn+2
tCD2
tCD2
tCKHZ
tCKLZ
Qn
Qn+3
DATAOUT
READ
NO OPERATION
WRITE
READ
Document #: 38-06043 Rev. *C
Page 11 of 21
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Switching Waveforms (continued)
Figure 11. Pipelined Read-to-Write-to-Read (OE Controlled)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
R/W
tHW
tSW
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
DATAIN
tSA
tHA
tSD tHD
Dn+2
Dn+3
tCD2
tCKLZ
tCD2
DATAOUT
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
Notes
26. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
27. CE and ADS = V ; CE , CNTEN, and CNTRST = V
.
IH
0
IL
1
28. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity.
Document #: 38-06043 Rev. *C
Page 12 of 21
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Switching Waveforms (continued)
Figure 12. Flow-Through Read-to-Write-to-Read (OE = V )
IL
tCYC1
tCL1
tCH1
CLK
CE0
tSC
tHC
CE1
R/W
tSW
tHW
tSW
tHW
An
An+1
An+2
An+2
An+3
An+4
ADDRESS
DATAIN
tSD
tHD
tSA
tHA
Dn+2
tCD1
tCD1
tCD1
tCD1
DATAOUT
Qn
tDC
Qn+1
tCKHZ
Qn+3
tCKLZ
tDC
NO
OPERATION
READ
WRITE
READ
Figure 13. Flow-Through Read-to-Write-to-Read (OE Controlled)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
R/W
tSW
tHW
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
DATAIN
tSD
tHD
tSA
tHA
Dn+2
Dn+3
tOE
tCD1
tDC
tCD1
tCD1
Qn
Qn+4
tDC
DATAOUT
OE
tOHZ
tCKLZ
READ
WRITE
READ
Document #: 38-06043 Rev. *C
Page 13 of 21
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Switching Waveforms (continued)
Figure 14. Pipelined Read with Address Counter Advance
tCYC2
tCL2
tCH2
CLK
tSA
tHA
ADDRESS
An
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tSCN
tHCN
tCD2
DATAOUT
Qx-1
Qx
tDC
Qn
Qn+1
COUNTER HOLD
Qn+2
Qn+3
READ
READ WITH COUNTER
READ WITH COUNTER
EXTERNAL
ADDRESS
Figure 15. Flow-Through Read with Address Counter Advance
tCYC1
tCH1
tCL1
CLK
tSA
tHA
An
ADDRESS
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tCD1
tSCN
tHCN
DATAOUT
Qn+3
Qn+2
Qx
tDC
Qn
Qn+1
READ
WITH
READ
COUNTER HOLD
READ WITH COUNTER
EXTERNAL
ADDRESS
COUNTER
Note
29. CE and OE = V ; CE , R/W and CNTRST = V .
IH
0
IL
1
Document #: 38-06043 Rev. *C
Page 14 of 21
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Switching Waveforms (continued)
Figure 16. Write with Address Counter Advance (Flow-Through or Pipelined Outputs)
tCYC2
tCL2
tCH2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
An+1
An+2
An+3
An+4
tSAD
tHAD
ADS
CNTEN
DATAIN
tSCN
tHCN
Dn
Dn+1
Dn+1
Dn+2
Dn+3
Dn+4
tSD
tHD
WRITE EXTERNAL
ADDRESS
WRITE WITH WRITE COUNTER
COUNTER HOLD
WRITE WITH COUNTER
Notes
30. CE and R/W = V ; CE and CNTRST = V .
IH
0
IL
1
31. The “Internal Address” is equal to the “External Address” when ADS = V and equals the counter output when ADS = V
.
IL
IH
Document #: 38-06043 Rev. *C
Page 15 of 21
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Switching Waveforms (continued)
Figure 17. Counter Reset (Pipelined Outputs)
tCYC2
tCL2
tCH2
CLK
tSA tHA
An
An+1
ADDRESS
INTERNAL
ADDRESS
AX
0
1
An
An+1
tSW tHW
R/W
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSRST
tHRST
CNTRST
DATAIN
tSD tHD
D0
DATAOUT
Q0
Q1
Qn
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
Notes
32. CE = V ; CE = V .
IH
0
IL
1
33. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
Document #: 38-06043 Rev. *C
Page 16 of 21
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Table 1. Read/Write and Enable Operation
Inputs
Outputs
OE
CLK
CE
CE
R/W
I/O –I/O
Operation
0
1
0
9
X
H
X
X
High-Z
High-Z
Deselected
X
X
L
X
L
L
L
L
X
L
Deselected
Write
H
H
H
D
D
IN
H
X
Read
OUT
H
X
High-Z
Outputs Disabled
Table 2. Address Counter Control Operation
Previous
Address
CLK ADS CNTEN CNTRST
I/O
Mode
Operation
Address
X
X
X
L
X
X
H
L
D
D
D
Reset
Counter Reset to Address 0
Address Load into Counter
out(0)
A
X
H
H
Load
Hold
n
out(n)
out(n)
X
A
H
External Address Blocked—Counter
Disabled
n
n
X
A
H
L
H
D
Increment Counter Enabled—Internal Address
Generation
out(n+1)
Notes
34. “X” = “Don’t Care”, “H” = V , “L” = V
.
IL
IH
35. ADS, CNTEN, CNTRST = “Don’t Care.”
36. OE is an asynchronous input signal.
37. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle.
38. CE and OE = V ; CE and R/W = V
.
IH
0
IL
1
39. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
40. Counter operation is independent of CE and CE .
0
1
Document #: 38-06043 Rev. *C
Page 17 of 21
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Ordering Information
32K x8 3.3V Synchronous Dual-Port SRAM
Speed (ns)
Ordering Code
CY7C09079V-6AC
CY7C09079V-7AC
CY7C09079V-7AI
CY7C09079V-9AC
CY7C09079V-12AC
Package Name
A100
Package Type
Operating Range
Commercial
Commercial
Industrial
[1]
6.5
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
[1]
7.5
A100
A100
9
A100
Commercial
Commercial
12
A100
64K x8 3.3V Synchronous Dual-Port SRAM
Speed (ns)
Ordering Code
CY7C09089V-6AC
CY7C09089V-6AXC
CY7C09089V-7AC
CY7C09089V-9AC
CY7C09089V-12AC
CY7C09089V-12AXC
CY7C09089V-12AXI
Package Name
A100
Package Type
Operating Range
[1]
6.5
100-Pin Thin Quad Flat Pack
Commercial
A100
100-Pin Pb-Free Thin Quad Flat Pack Commercial
[1]
7.5
A100
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Commercial
Commercial
Commercial
9
A100
12
A100
A100
100-Pin Pb-Free Thin Quad Flat Pack Commercial
100-Pin Pb-Free Thin Quad Flat Pack Industrial
A100
128K x8 3.3V Synchronous Dual-Port SRAM
Speed (ns)
Ordering Code
CY7C09099V-6AC
CY7C09099V-6AXC
CY7C09099V-7AC
CY7C09099V-7AI
CY7C09099V-7AXI
CY7C09099V-9AC
CY7C09099V-9AI
CY7C09099V-12AC
CY7C09099V-12AXC
Package Name
A100
Package Type
Operating Range
[1]
6.5
100-Pin Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
Commercial
Commercial
Commercial
Industrial
A100
[1]
7.5
A100
A100
A100
Industrial
9
A100
Commercial
Industrial
A100
12
A100
Commercial
Commercial
A100
32K x9 3.3V Synchronous Dual-Port SRAM
Speed (ns)
Ordering Code
CY7C09179V-6AC
CY7C09179V-6AXC
CY7C09179V-7AC
CY7C09179V-9C
Package Name
A100
Package Type
Operating Range
6.5
100-Pin Thin Quad Flat Pack
Commercial
A100
100-Pin Pb-Free Thin Quad Flat Pack Commercial
7.5
A100
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Commercial
Commercial
Commercial
9
A100
12
CY7C09179V-12AC
CY7C09179V-12AXC
A100
A100
100-Pin Pb-Free Thin Quad Flat Pack Commercial
Document #: 38-06043 Rev. *C
Page 18 of 21
CY7C09079V/89V/99V
CY7C09179V/89V/99V
64K x9 3.3V Synchronous Dual-Port SRAM
Speed (ns)
Ordering Code
CY7C09189V-6AC
CY7C09189V-6AXC
CY7C09189V-7AC
CY7C09189V-9AC
CY7C09189V-12AC
CY7C09189V-12AXC
Package Name
A100
Package Type
Operating Range
6.5
100-Pin Thin Quad Flat Pack
Commercial
A100
100-Pin Pb-Free Thin Quad Flat Pack Commercial
7.5
A100
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Commercial
Commercial
Commercial
9
A100
12
A100
A100
100-Pin Pb-Free Thin Quad Flat Pack Commercial
128K x9 3.3V Synchronous Dual-Port SRAM
Speed (ns)
Ordering Code
CY7C09199V-6AC
CY7C09199V-6AXC
CY7C09199V-7AC
CY7C09199V-7AXC
CY7C09199V-9AC
CY7C09199V-9AXC
CY7C09199V-9AI
Package Name
A100
Package Type
Operating Range
Commercial
6.5
100-Pin Thin Quad Flat Pack
A100
100-Pin Pb-Free Thin Quad Flat Pack Commercial
100-Pin Thin Quad Flat Pack Commercial
100-Pin Pb-Free Thin Quad Flat Pack Commercial
100-Pin Thin Quad Flat Pack Commercial
100-Pin Pb-Free Thin Quad Flat Pack Commercial
100-Pin Thin Quad Flat Pack Industrial
100-Pin Pb-Free Thin Quad Flat Pack Industrial
100-Pin Thin Quad Flat Pack Commercial
100-Pin Pb-Free Thin Quad Flat Pack Commercial
7.5
A100
A100
9
A100
A100
A100
CY7C09199V-9AXI
CY7C09199V-12AC
CY7C09199V-12AXC
A100
12
A100
A100
Document #: 38-06043 Rev. *C
Page 19 of 21
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Package Diagram
Figure 18. 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 (51-85048)
51-85048-*B
Document #: 38-06043 Rev. *C
Page 20 of 21
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document History Page
Document Title: CY7C09079V/89V/99V, CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9Synchronous Dual Port Static
RAM
Document Number: 38-06043
Orig. of
Change
Orig. of
Change
Rev.
ECN No.
Description of Change
**
110191
122293
365034
SZV
09/29/01
12/27/02
Change from Spec number: 38-00667 to 38-06043
*A
*B
RBI
Power up requirements added to Operating Conditions Information
PCN
See ECN Added Pb-Free Logo
Added Pb-Free Part Ordering Information:
CY7C09089V-6AXC, CY7C09089V-12AXC, CY7C09099V-6AXC,
CY7C09099V-7AI, CY7C09099V-7AXI, CY7C09099V-12AXC,
CY7C09179V-6AXC, CY7C09179V-12AXC, CY7C09189V-6AXC,
CY7C09189V-12AXC, CY7C09199V-6AXC, CY7C09199V-7AXC,
CY7C09199V-9AXC, CY7C09199V-9AXI, CY7C09199V-12AXC
*C
2623658
VKN/PYRS 12/17/08
Added CY7C09089V-12AXI part in the Ordering information table
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Document #: 38-06043 Rev. *C
Revised December 10, 2008
Page 21 of 21
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