Cypress CY62147DV30 User Manual

CY62147DV30  
4-Mbit (256K x 16) Static RAM  
vanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life™ (MoBL ) in portable  
Features  
®
• Temperature Ranges  
applications such as cellular telephones. The device also has  
an automatic power-down feature that significantly reduces  
power consumption. The device can also be put into standby  
mode reducing power consumption by more than 99% when  
deselected (CE HIGH or both BLE and BHE are HIGH). The  
Industrial: –40°C to +85°C  
— Automotive-A: –40°C to +85°C  
— Automotive-E: –40°C to +125°C  
• Very high speed: 45 ns  
input/output pins (I/O through I/O ) are placed in a high-im-  
0
15  
pedance state when: deselected (CE HIGH), outputs are dis-  
abled (OE HIGH), both Byte High Enable and Byte Low Enable  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW and WE LOW).  
• Wide voltage range: 2.20V–3.60V  
• Pin-compatible with CY62147CV25, CY62147CV30, and  
CY62147CV33  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
• Ultra-low active power  
— Typical active current: 1.5 mA @ f = 1 MHz  
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is  
0
7
written into the location specified on the address pins (A  
— Typical active current: 8 mA @ f = f  
0
max  
through A ). If Byte High Enable (BHE) is LOW, then data  
17  
• Ultra low standby power  
from I/O pins (I/O through I/O ) is written into the location  
8
15  
• Easy memory expansion with CE, and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
specified on the address pins (A through A ).  
0
17  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
• Available in Pb-freeand non Pb-free 48-ball VFBGA and  
non Pb-free 44-pin TSOPII  
pins will appear on I/O to I/O . If Byte High Enable (BHE) is  
0
7
LOW, then data from memory will appear on I/O to I/O . See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
• Byte power-down feature  
8
15  
Functional Description[1]  
The CY62147DV30 is available in a 48-ball VFBGA, 44 Pin  
TSOPII packages.  
The CY62147DV30 is a high-performance CMOS static RAM  
organized as 256K words by 16 bits. This device features ad-  
Logic Block Diagram  
DATA IN DRIVERS  
A
10  
9
A
A
8
7
6
A
A
A
A
256K x 16  
RAM Array  
5
4
3
2
I/O –I/O  
0
7
A
I/O –I/O  
A
8
15  
A
A
1
0
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
CE  
Power -Down  
Circuit  
BHE  
BLE  
Note:  
Cypress Semiconductor Corporation  
Document #: 38-05340 Rev. *F  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 31, 2006  
CY62147DV30  
Output Current into Outputs (LOW)............................. 20 mA  
Maximum Ratings  
Static Discharge Voltage........................................... >2001V  
(per MIL-STD-883, Method 3015)  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Latch-up Current......................................................>200 mA  
Storage Temperature .................................65°C to +150°C  
Operating Range  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Ambient  
Supply Voltage to Ground  
Potential......................................–0.3V to + V  
Temperature  
[9]  
Device  
Range  
[T ]  
V
CC  
+ 0.3V  
A
CC(MAX)  
CY62147DV30L Automotive-E –40°C to +125°C 2.20V  
to  
DC Voltage Applied to Outputs  
[6,7]  
in High-Z State  
..........................–0.3V to V  
+ 0.3V  
+ 0.3V  
CC(MAX)  
..................... –0.3V to V  
CC(MAX)  
CY62147DV30LL  
Industrial  
–40°C to +85°C  
3.60V  
[6,7]  
DC Input Voltage  
Automotive-A –40°C to +85°C  
Electrical Characteristics (Over the Operating Range)  
–45  
–55/–70  
[5]  
[5]  
Parameter Description  
Test Conditions  
Min. Typ.  
Max.  
Min. Typ.  
2.0  
Max.  
Unit  
V
V
V
V
Output HIGH I = –0.1 mA  
Voltage  
V
V
V
V
= 2.20V  
= 2.70V  
= 2.20V  
= 2.70V  
2.0  
2.4  
V
V
OH  
OL  
IH  
OH  
CC  
CC  
CC  
CC  
I
I
I
= –1.0 mA  
= 0.1 mA  
= 2.1 mA  
2.4  
OH  
OL  
OL  
Output LOW  
Voltage  
0.4  
0.4  
0.4  
0.4  
V
V
Input HIGH  
Voltage  
V
V
V
V
= 2.2V to 2.7V  
= 2.7V to 3.6V  
= 2.2V to 2.7V  
= 2.7V to 3.6V  
1.8  
2.2  
V
V
+ 0.3V 1.8  
V
V
+ 0.3V  
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
+ 0.3V 2.2  
+ 0.3V  
V
Input LOW  
Voltage  
–0.3  
–0.3  
–1  
0.6  
–0.3  
–0.3  
–1  
0.6  
0.8  
+1  
+1  
+4  
+1  
+1  
+4  
15  
3
V
IL  
0.8  
+1  
V
I
I
Input Leakage GND < V < V  
Current  
µA  
µA  
µA  
µA  
µA  
µA  
mA  
mA  
IX  
I
CC  
Ind’l  
[9]  
Auto-A  
Auto-E  
–1  
[9]  
–4  
Output  
Leakage  
Current  
GND < V < V  
Output Disabled  
,
–1  
+1  
–1  
OZ  
O
CC  
Ind’l  
[9]  
[9]  
Auto-A  
Auto-E  
–1  
–4  
I
I
V
Operating f = f  
= 1/t  
V
= V  
CCmax  
= 0 mA  
10  
20  
3
8
CC  
CC  
MAX  
RC  
CC  
Supply  
Current  
I
OUT  
f = 1 MHz  
1.5  
1.5  
CMOS levels  
Automatic CE CE > V 0.2V,  
Power-Down V >V –0.2V,V <0.2V)  
Ind’l LL  
8
8
8
µA  
SB1  
CC  
[9]  
IN  
f = f  
CC  
IN  
Auto-A LL  
Current —  
CMOS Inputs Data Only),  
f = 0 (OE, WE, BHE and  
(Address and  
MAX  
[9]  
Auto-E  
L
25  
BLE), V = 3.60V  
CC  
I
Automatic CE CE > V – 0.2V,  
Ind’l  
LL  
8
8
8
µA  
SB2  
CC  
Power-Down  
Current —  
V
V
> V – 0.2V or  
< 0.2V,  
[9]  
IN  
IN  
CC  
Auto-A LL  
[9]  
CMOS Inputs f = 0, V = 3.60V  
Auto-E  
L
25  
CC  
Notes:  
6. V  
7. V  
= –2.0V for pulse durations less than 20 ns.  
IL(min.)  
= V + 0.75V for pulse durations less than 20 ns.  
IH(max.)  
CC  
8. Full device AC operation assumes a 100-µs ramp time from 0 to V (min) and 200-µs wait time after V stabilization.  
CC  
CC  
9. Auto-A is available in –70 and Auto-E is available in –55.  
Document #: 38-05340 Rev. *F  
Page 3 of 12  
CY62147DV30  
[10]  
Capacitance (for all packages)  
Parameter  
Description  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max.  
10  
Unit  
pF  
C
C
Input Capacitance  
Output Capacitance  
IN  
A
V
= V  
CC  
CC(typ)  
10  
pF  
OUT  
Thermal Resistance[10]  
Parameter  
Description  
Test Conditions  
VFBGA  
TSOP II  
Unit  
Θ
Thermal Resistance  
(Junction to Ambient)  
Still Air, soldered on a 3 × 4.5 inch, four-layer  
printed circuit board  
72  
75.13  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
8.86  
8.95  
°C/W  
JC  
AC Test Loads and Waveforms[10]  
R1  
ALL INPUT PULSES  
V
V
CC  
CC  
90%  
10%  
90%  
OUTPUT  
10%  
GND  
Fall Time = 1 V/ns  
Rise Time = 1 V/ns  
R2  
50 pF  
INCLUDING  
JIG AND  
SCOPE  
Equivalent to:  
THÉVENIN EQUIVALENT  
R
TH  
OUTPUT  
V
Parameters  
2.50V  
16667  
15385  
8000  
3.0V  
1103  
1554  
645  
Unit  
R1  
R2  
R
TH  
TH  
V
1.20  
1.75  
V
Data Retention Characteristics (Over the Operating Range)  
[5]  
Parameter  
Description  
Conditions  
Min.  
Typ.  
Max. Unit  
V
I
V
for Data Retention  
1.5  
V
DR  
CC  
Data Retention Current  
V
= 1.5V  
L (Auto-E)  
15  
6
µA  
CCDR  
CC  
CE > V – 0.2V,  
CC  
LL (Ind’l/Auto-A)  
V
V
> V – 0.2V or  
IN  
IN  
CC  
< 0.2V  
[10]  
t
t
Chip Deselect to Data Retention  
Time  
0
ns  
ns  
CDR  
[12]  
R
Operation Recovery Time  
t
RC  
Data Retention Waveform[13]  
DATA RETENTION MODE  
> 1.5 V  
V
V
CC(min)  
CC(min)  
V
V
CC  
DR  
t
t
R
CDR  
CE or  
BHE.BLE  
Notes:  
10. Tested initially and after any design or process changes that may affect these parameters.  
11. Test condition for the 45-ns part is a load capacitance of 30 pF.  
12. Full device operation requires linear V ramp from V to V  
> 100 µs or stable at V  
> 100 µs.  
CC  
DR  
CC(min.)  
CC(min.)  
13. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.  
Document #: 38-05340 Rev. *F  
Page 4 of 12  
CY62147DV30  
[14]  
Switching Characteristics Over the Operating Range  
[11]  
45 ns  
Min.  
55 ns  
70 ns  
Parameter  
Description  
Max.  
Min.  
55  
Max.  
Min.  
70  
Max.  
Unit  
Read Cycle  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
45  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
45  
55  
70  
AA  
Data Hold from Address Change  
CE LOW to Data Valid  
10  
10  
OHA  
ACE  
DOE  
LZOE  
HZOE  
LZCE  
HZCE  
PU  
45  
25  
55  
25  
70  
35  
OE LOW to Data Valid  
[15]  
OE LOW to LOW Z  
5
10  
0
5
10  
0
5
10  
0
[15, 16]  
OE HIGH to High Z  
15  
20  
20  
20  
25  
25  
[15]  
CE LOW to Low Z  
[15, 16]  
CE HIGH to High Z  
CE LOW to Power-Up  
CE HIGH to Power-Down  
BLE/BHE LOW to Data Valid  
45  
45  
55  
55  
70  
70  
PD  
DBE  
LZBE  
HZBE  
[15]  
BLE/BHE LOW to Low Z  
10  
10  
10  
[15, 16]  
BLE/BHE HIGH to HIGH Z  
15  
20  
25  
[17]  
Write Cycle  
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
45  
40  
40  
0
55  
40  
40  
0
70  
60  
60  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CE LOW to Write End  
SCE  
AW  
Address Set-up to Write End  
Address Hold from Write End  
Address Set-up to Write Start  
WE Pulse Width  
HA  
0
0
0
SA  
35  
40  
25  
0
40  
40  
25  
0
45  
60  
30  
0
PWE  
BW  
BLE/BHE LOW to Write End  
Data Set-up to Write End  
Data Hold from Write End  
SD  
HD  
[15, 16]  
WE LOW to High-Z  
15  
20  
25  
HZWE  
LZWE  
[15]  
WE HIGH to Low-Z  
10  
10  
10  
Notes:  
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of V  
/2, input  
CC(typ)  
pulse levels of 0 to V  
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.  
CC(typ.)  
OL OH  
15. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any  
HZCE  
LZCE HZBE  
LZBE HZOE  
LZOE  
HZWE  
LZWE  
given device.  
16. t  
, t  
, t  
, and t  
transitions are measured when the outputs enter a high impedence state.  
HZOE HZCE HZBE  
HZWE  
17. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any  
IL  
IL  
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates  
the write.  
Document #: 38-05340 Rev. *F  
Page 5 of 12  
CY62147DV30  
Switching Waveforms  
[18, 19]  
Read Cycle 1 (Address Transition Controlled)  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
[19, 20]  
Read Cycle No. 2 (OE Controlled)  
ADDRESS  
CE  
t
RC  
t
PD  
HZCE  
t
t
ACE  
OE  
t
HZOE  
t
DOE  
BHE/BLE  
t
LZOE  
t
HZBE  
t
DBE  
t
LZBE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PU  
V
I
CC  
CC  
SUPPLY  
CURRENT  
50%  
50%  
I
SB  
Notes:  
18. The device is continuously selected. OE, CE= V , BHE and/or BLE = V  
.
IL  
IL  
19. WE is HIGH for read cycle.  
20. Address valid prior to or coincident with CE and BHE, BLE transition LOW.  
Document #: 38-05340 Rev. *F  
Page 6 of 12  
CY62147DV30  
Switching Waveforms (continued)  
[17, 21, 22]  
Write Cycle No. 1 (WE Controlled)  
t
WC  
ADDRESS  
CE  
tSCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
BW  
BHE/BLE  
OE  
t
SD  
t
HD  
DATAIN  
DATA I/O  
NOTE23  
t
HZOE  
[17, 21, 22]  
Write Cycle No. 2 (CE Controlled)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
t
HA  
AW  
tPWE  
WE  
t
BW  
BHE/BLE  
OE  
t
t
SD  
HD  
DATAIN  
DATA I/O  
NOTE 23  
t
HZOE  
Notes:  
21. Data I/O is high impedance if OE = V  
.
IH  
22. If CE goes HIGH simultaneously with WE = V , the output remains in a high-impedance state.  
IH  
23. During this period, the I/Os are in output state and input signals should not be applied.  
Document #: 38-05340 Rev. *F  
Page 7 of 12  
CY62147DV30  
Switching Waveforms (continued)  
[22]  
Write Cycle No. 3 (WE Controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
BW  
BHE/BLE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
HD  
t
SD  
NOTE 23  
DATAI/O  
DATAIN  
t
HZWE  
t
LZWE  
[22]  
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
tBW  
BHE/BLE  
t
SA  
tPWE  
WE  
tHZWE  
tHD  
t
SD  
DATA I/O  
DATAIN  
NOTE 23  
tLZWE  
Document #: 38-05340 Rev. *F  
Page 8 of 12  
CY62147DV30  
Truth Table  
CE  
H
X
WE  
X
OE  
X
BHE  
X
BLE  
X
Inputs/Outputs  
High Z  
High Z  
Data Out (I/O –I/O  
Mode  
Deselect/Power-Down  
Deselect/Power-Down  
Read  
Power  
Standby (I  
Standby (I  
)
SB  
X
X
H
H
)
SB  
L
H
L
L
L
)
Active (I )  
CC  
O
15  
L
H
L
H
L
Data Out (I/O –I/O );  
Read  
Active (I )  
CC  
O
7
I/O –I/O in High Z  
8
15  
L
H
L
L
H
Data Out (I/O –I/O );  
Read  
Active (I  
)
8
15  
CC  
I/O –I/O in High Z  
0
7
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z  
Output Disabled  
Output Disabled  
Output Disabled  
Write  
Active (I  
Active (I  
Active (I  
Active (I  
Active (I  
)
CC  
High Z  
High Z  
)
CC  
)
CC  
L
Data In (I/O –I/O  
)
)
CC  
O
15  
L
H
Data In (I/O –I/O );  
Write  
)
CC  
O
7
I/O –I/O in High Z  
8
15  
L
L
X
L
H
Data In (I/O –I/O );  
Write  
Active (I  
)
8
15  
CC  
I/O –I/O in High Z  
0
7
Ordering Information  
Speed  
(ns)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
45  
CY62147DV30LL-45BVXI 51-85150 48-ball (6 mm × 8mm × 1 mm) VFBGA (Pb-free)  
Industrial  
CY62147DV30LL-45ZSXI  
CY62147DV30LL-55BVI  
CY62147DV30LL-55BVXI  
CY62147DV30LL-55ZSXI  
CY62147DV30L-55BVXE  
CY62147DV30L-55ZSXE  
CY62147DV30LL-70BVI  
CY62147DV30LL-70BVXA  
51-85087 44-pin TSOP II (Pb-free)  
55  
70  
51-85150 48-ball (6 mm × 8mm × 1 mm) VFBGA  
48-ball (6 mm × 8mm × 1 mm) VFBGA (Pb-free)  
51-85087 44-pin TSOP II (Pb-free)  
Industrial  
51-85150 48-ball (6 mm × 8mm × 1 mm) VFBGA (Pb-free)  
51-85087 44-pin TSOP II (Pb-free)  
Automotive-E  
51-85150 48-ball (6 mm × 8mm × 1 mm) VFBGA  
48-ball (6 mm × 8mm × 1 mm) VFBGA (Pb-free)  
Industrial  
Automotive-A  
Document #: 38-05340 Rev. *F  
Page 9 of 12  
CY62147DV30  
Package Diagram  
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)  
BOTTOM VIEW  
A1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
A1 CORNER  
Ø0.30 0.05(48X)  
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
E
B
C
D
E
F
F
G
G
H
H
1.875  
A
A
0.75  
B
6.00 0.10  
3.75  
B
6.00 0.10  
0.15(4X)  
51-85150-*D  
SEATING PLANE  
C
Document #: 38-05340 Rev. *F  
Page 10 of 12  
CY62147DV30  
Package Diagram (continued)  
44-Pin TSOP II (51-85087)  
51-85087-*A  
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and  
company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-05340 Rev. *F  
Page 11 of 12  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY62147DV30  
Document History Page  
®
Document Title:CY62147DV30 MoBL 4-Mbit (256K x 16) Static RAM  
Document Number: 38-05340  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
127481  
131010  
213252  
06/17/03  
01/23/04  
See ECN  
HRT  
CBD  
AJU  
New Data Sheet  
*A  
Changed from Advance to Preliminary  
*B  
Changed from Preliminary to Final  
Added 70 ns speed bin  
Modified footnote 7 to include ramp time and wait time  
Modified input and output capacitance values to 10 pF  
Modified Thermal Resistance values on page 4  
Added “Byte power-down feature” in the features section  
Modified Ordering Information for Pb-free parts  
*C  
*D  
257349  
316039  
See ECN  
See ECN  
PCI  
PCI  
Modified ordering information for 70-ns Speed Bin  
Added 45-ns Speed Bin in AC, DC and Ordering Information tables  
Added Footnote #10 on page #4  
Added Pb-free package ordering information on page # 9  
Changed 44-lead TSOP-II package name on page 11 from Z44 to ZS44  
Standardized Icc values across ‘L’ and ‘LL’ bins  
*E  
*F  
330365  
498575  
See ECN  
See ECN  
AJU  
Added Automotive product information  
NXR  
Added Automotive-A range  
Added note# 9 on page# 3  
Updated ordering information table  
Document #: 38-05340 Rev. *F  
Page 12 of 12  

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