Cypress CY14E256L User Manual

CY14E256L  
256 Kbit (32K x 8) nvSRAM  
Features  
Functional Description  
25 ns, 35 ns, and 45 ns access times  
Pin compatible with STK14C88  
The Cypress CY14E256L is a fast static RAM with a nonvolatile  
element in each memory cell. The embedded nonvolatile  
elements incorporate QuantumTrap technology producing the  
world’s most reliable nonvolatile memory. The SRAM provides  
unlimited read and write cycles, while independent, nonvolatile  
data resides in the highly reliable QuantumTrap cell. Data  
transfers from the SRAM to the nonvolatile elements (the  
STORE operation) takes place automatically at power down. On  
power up, data is restored to the SRAM (the RECALL operation)  
from the nonvolatile memory. Both the STORE and RECALL  
operations are also available under software control. A hardware  
STORE is initiated with the HSB pin.  
Hands off automatic STORE on power down with external 68  
µF capacitor  
STORE to QuantumTrap™ nonvolatile elements is initiated by  
software, hardware, or AutoStore™ on power down  
RECALL to SRAM initiated by software or power up  
Unlimited READ, WRITE, and RECALL cycles  
1,000,000 STORE cycles to QuantumTrap  
100 year data retention to QuantumTrap  
Single 5V+10% operation  
Commercial and industrial temperature  
32-pin SOIC and CDIP (300 mil) packages  
RoHS compliance  
Logic Block Diagram  
V
CC  
V
CAP  
Quantum Trap  
512 X 512  
POWER  
CONTROL  
A5  
STORE  
A6  
A7  
A8  
RECALL  
STORE/  
RECALL  
CONTROL  
STATIC RAM  
ARRAY  
512 X 512  
HSB  
A9  
A11  
A12  
A13  
A14  
SOFTWARE  
DETECT  
A13  
-
A0  
DQ0  
COLUMN I/O  
DQ1  
DQ2  
DQ3  
COLUMN DEC  
DQ4  
DQ5  
DQ6  
DQ7  
A0  
A4  
A10  
A1  
A3  
A2  
OE  
CE  
WE  
Cypress Semiconductor Corporation  
Document Number: 001-06968 Rev. *F  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 30, 2009  
CY14E256L  
having a capacitor of between 68uF and 220uF (+ 20%) rated at  
6V should be provided. The voltage on the VCAP pin is driven to  
5V by a charge pump internal to the chip. A pull up is placed on  
WE to hold it inactive during power up.  
Device Operation  
The CY14E256L nvSRAM is made up of two functional compo-  
nents paired in the same physical cell. These are an SRAM  
memory cell and a nonvolatile QuantumTrap cell. The SRAM  
memory cell operates as a standard fast static RAM. Data in the  
SRAM is transferred to the nonvolatile cell (the STORE  
operation) or from the nonvolatile cell to SRAM (the RECALL  
operation). This unique architecture enables the storage and  
recall of all cells in parallel. During the STORE and RECALL  
operations, SRAM READ and WRITE operations are inhibited.  
The CY14E256L supports unlimited reads and writes similar to  
a typical SRAM. In addition, it provides unlimited RECALL opera-  
tions from the nonvolatile cells and up to one million STORE  
operations.  
Figure 2. AutoStore Mode  
SRAM Read  
The CY14E256L performs a READ cycle whenever CE and OE  
are LOW while WE and HSB are HIGH. The address specified  
on pins A0–14 determines the 32,768 data bytes accessed. When  
the READ is initiated by an address transition, the outputs are  
valid after a delay of tAA (READ cycle 1). If the READ is initiated  
by CE or OE, the outputs are valid at tACE or at tDOE, whichever  
is later (READ cycle 2). The data outputs repeatedly respond to  
address changes within the tAA access time without the need for  
transitions on any control input pins, and remains valid until  
another address change or until CE or OE is brought HIGH, or  
WE or HSB is brought LOW.  
In system power mode, both VCC and VCAP are connected to the  
+5V power supply without the 68 μF capacitor. In this mode, the  
AutoStore function of the CY14E256L operates on the stored  
system charge as power goes down. The user must, however,  
guarantee that VCC does not drop below 3.6V during the 10 ms  
STORE cycle.  
SRAM Write  
A WRITE cycle is performed whenever CE and WE are LOW and  
HSB is HIGH. The address inputs must be stable prior to entering  
the WRITE cycle and must remain stable until either CE or WE  
goes HIGH at the end of the cycle. The data on the common IO  
pins DQ0–7 are written into the memory if it has valid tSD, before  
the end of a WE controlled WRITE or before the end of an CE  
controlled WRITE. Keep OE HIGH during the entire WRITE cycle  
to avoid data bus contention on common IO lines. If OE is left  
LOW, internal circuitry turns off the output buffers tHZWE after WE  
goes LOW.  
To reduce unnecessary nonvolatile stores, AutoStore and  
Hardware Store operations are ignored, unless at least one  
WRITE operation has taken place since the most recent STORE  
or RECALL cycle. Software initiated STORE cycles are  
performed regardless of whether a WRITE operation has taken  
place. An optional pull-up resistor is shown connected to HSB.  
The HSB signal is monitored by the system to detect if an  
AutoStore cycle is in progress.  
AutoStore Operation  
If the power supply drops faster than 20 us/volt before Vcc  
reaches VSWITCH, then a 2.2 ohm resistor should be connected  
between VCC and the system supply to avoid momentary excess  
The CY14E256L stores data to nvSRAM using one of three  
storage operations:  
of current between VCC and VCAP  
.
1. Hardware store activated by HSB  
2. Software store activated by an address sequence  
3. AutoStore on device power down  
AutoStore Inhibit mode  
If an automatic STORE on power loss is not required, then VCC  
is tied to ground and + 5V is applied to VCAP (Figure 3). This is  
the AutoStore Inhibit mode, where the AutoStore function is  
disabled. If the CY14E256L is operated in this configuration,  
references to VCC are changed to VCAP throughout this data  
sheet. In this mode, STORE operations are triggered through  
software control or the HSB pin. To enable or disable Autostore  
using an I/O port pin see “” on page 5. It is not permissible to  
change between these three options” on the fly”.  
AutoStore operation is a unique feature of QuantumTrap  
technology and is enabled by default on the CY14E256L.  
During normal operation, the device draws current from VCC to  
charge a capacitor connected to the VCAP pin. This stored  
charge is used by the chip to perform a single STORE operation.  
If the voltage on the VCC pin drops below VSWITCH, the part  
automatically disconnects the VCAP pin from VCC. A STORE  
operation is initiated with power provided by the VCAP capacitor.  
Figure 2 shows the proper connection of the storage capacitor  
(VCAP) for automatic store operation. A charge storage capacitor  
Document Number: 001-06968 Rev. *F  
Page 3 of 18  
 
CY14E256L  
Figure 3. AutoStore Inhibit Mode  
If the CY14E256L is in a WRITE state at the end of power up  
RECALL, the SRAM data is corrupted. To help avoid this  
situation, a 10 Kohm resistor is connected either between WE  
and system VCC or between CE and system VCC  
.
Software STORE  
Data is transferred from the SRAM to the nonvolatile memory by  
a software address sequence. The CY14E256L software  
STORE cycle is initiated by executing sequential CE controlled  
READ cycles from six specific address locations in exact order.  
During the STORE cycle, an erase of the previous nonvolatile  
data is first performed followed by a program of the nonvolatile  
elements. When a STORE cycle is initiated, input and output are  
disabled until the cycle is completed.  
Because a sequence of READs from specific addresses is used  
for STORE initiation, it is important that no other READ or WRITE  
accesses intervene in the sequence. If they intervene, the  
sequence is aborted and no STORE or RECALL takes place.  
To initiate the software STORE cycle, the following READ  
sequence is performed:  
1. Read address 0x0E38, Valid READ  
2. Read address 0x31C7, Valid READ  
3. Read address 0x03E0, Valid READ  
4. Read address 0x3C1F, Valid READ  
5. Read address 0x303F, Valid READ  
6. Read address 0x0FC0, Initiate STORE cycle  
Hardware STORE (HSB) Operation  
The CY14E256L provides the HSB pin for controlling and  
acknowledging the STORE operations. The HSB pin is used to  
request a hardware STORE cycle. When the HSB pin is driven  
LOW, the CY14E256L conditionally initiates a STORE operation  
after tDELAY. An actual STORE cycle only begins if a WRITE to  
the SRAM takes place since the last STORE or RECALL cycle.  
The HSB pin also acts as an open drain driver that is internally  
driven LOW to indicate a busy condition, while the STORE  
(initiated by any means) is in progress. Pull up this pin with an  
external 10K ohm resistor to VCAP if HSB is used as a driver.  
The software sequence is clocked with CE controlled READs.  
When the sixth address in the sequence is entered, the STORE  
cycle commences and the chip is disabled. It is important that  
READ cycles and not WRITE cycles are used in the sequence.  
It is not necessary that OE is LOW for a valid sequence. After the  
tSTORE cycle time is fulfilled, the SRAM is again activated for  
READ and WRITE operation.  
SRAM READ and WRITE operations, that are in progress when  
HSB is driven LOW by any means, are given time to complete  
before the STORE operation is initiated. After HSB goes LOW,  
the CY14E256L continues SRAM operations for tDELAY. During  
tDELAY, multiple SRAM READ operations take place. If a WRITE  
is in progress when HSB is pulled LOW, it allows a time, tDELAY  
to complete. However, any SRAM WRITE cycles requested after  
HSB goes LOW are inhibited until HSB returns HIGH.  
Software RECALL  
Data is transferred from the nonvolatile memory to the SRAM by  
a software address sequence. A software RECALL cycle is  
initiated with a sequence of READ operations in a manner similar  
to the software STORE initiation. To initiate the RECALL cycle,  
the following sequence of CE controlled READ operations is  
performed:  
During any STORE operation, regardless of how it is initiated,  
the CY14E256L continues to drive the HSB pin LOW, releasing  
it only when the STORE is complete. After completing the  
STORE operation, the CY14E256L remains disabled until the  
HSB pin returns HIGH.  
1. Read address 0x0E38, Valid READ  
2. Read address 0x31C7, Valid READ  
3. Read address 0x03E0, Valid READ  
4. Read address 0x3C1F, Valid READ  
5. Read address 0x303F, Valid READ  
6. Read address 0x0C63, Initiate RECALL cycle  
If HSB is not used, it is left unconnected.  
Hardware RECALL (Power Up)  
Internally, RECALL is a two step procedure. First, the SRAM data  
is cleared, and then the nonvolatile information is transferred into  
the SRAM cells. After the tRECALL cycle time, the SRAM is once  
again ready for READ and WRITE operations. The RECALL  
operation does not alter the data in the nonvolatile elements. The  
nonvolatile data can be recalled an unlimited number of times.  
During power up or after any low power condition (VCC  
<
V
RESET), an internal RECALL request is latched. When VCC  
once again exceeds the sense voltage of VSWITCH, a RECALL  
cycle is automatically initiated and takes tHRECALL to complete.  
Document Number: 001-06968 Rev. *F  
Page 4 of 18  
 
CY14E256L  
Figure 4. Current Versus Cycle Time (READ)  
Data Protection  
The CY14E256L protects data from corruption during low  
voltage conditions by inhibiting all externally initiated STORE  
and WRITE operations. The low voltage condition is detected  
when VCC is less than VSWITCH. If the CY14E256L is in a WRITE  
mode (both CE and WE are low) at power up after a RECALL or  
after a STORE, the WRITE is inhibited until a negative transition  
on CE or WE is detected. This protects against inadvertent writes  
during power up or brown out conditions.  
Noise Considerations  
The CY14E256L is a high speed memory. It must have a high  
frequency bypass capacitor of approximately 0.1 µF connected  
between VCC and VSS, using leads and traces that are as short  
as possible. As with all high speed CMOS ICs, careful routing of  
power, ground, and signals reduce circuit noise.  
Figure 5. Current Versus Cycle Time (WRITE)  
Hardware Protect  
The CY14E256L offers hardware protection against inadvertent  
STORE operation and SRAM WRITEs during low voltage condi-  
tions. When VCAP<VSWITCH, all externally initiated STORE  
operations and SRAM WRITEs are inhibited. AutoStore can be  
completely disabled by tying VCC to ground and applying + 5V  
to VCAP. This is the AutoStore Inhibit mode; in this mode,  
STOREs are only initiated by explicit request using either the  
software sequence or the HSB pin.  
Low Average Active Power  
CMOS technology provides the CY14E256L the benefit of  
drawing significantly less current when it is cycled at times longer  
than 50 ns. Figure 4 shows the relationship between ICC and  
READ or WRITE cycle time. Worst case current consumption is  
shown for both CMOS and TTL input levels (commercial temper-  
ature range, VCC = 5.5V, 100% duty cycle on chip enable). Only  
standby current is drawn when the chip is disabled. The overall  
average current drawn by the CY14E256L depends on the  
following items:  
Preventing Store  
The STORE function is disabled by holding HSB high with a  
driver capable of sourcing 30 mA at a VOH of at least 2.2V,  
because it has to overpower the internal pull down device. This  
device drives HSB LOW for 20 μs at the onset of a STORE.  
When the CY14E256L is connected for AutoStore operation  
The duty cycle of chip enable  
The overall cycle rate for accesses  
The ratio of READs to WRITEs  
CMOS versus TTL input levels  
The operating temperature  
The VCC level  
(system VCC connected to VCC and a 68 μF capacitor on VCAP  
)
and VCC crosses VSWITCH on the way down, the CY14E256L  
attempts to pull HSB LOW. If HSB does not actually get below  
VIL, the part stops trying to pull HSB LOW and abort the STORE  
attempt.  
IO loading  
Document Number: 001-06968 Rev. *F  
Page 5 of 18  
   
CY14E256L  
manufacturing test to ensure these system routines work  
consistently.  
Best Practices  
nvSRAM products have been used effectively for over 15 years.  
While ease of use is one of the product’s main system values,  
experience gained working with hundreds of applications has  
resulted in the following suggestions as best practices:  
Power up boot firmware routines should rewrite the nvSRAM  
into the desired state. While the nvSRAM is shipped in a preset  
state, best practice is to again rewrite the nvSRAM into the  
desired state as a safeguard against events that might flip the  
bit inadvertently (program bugs, incoming inspection routines,  
and so on).  
The nonvolatile cells in an nvSRAM are programmed on the  
test floor during final test and quality assurance. Incoming  
inspection routines at customer or contract manufacturer’s  
sitessometimesreprogramthesevalues. FinalNVpatternsare  
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End  
product’s firmware should not assume an NV array is in a set  
programmed state. Routines that check memory content  
values to determine first time system configuration, cold or  
warm boot status, and so on should always program a unique  
NV pattern (for example, complex 4-byte pattern of 46 E6 49  
53 hex or more random bytes) as part of the final system  
TheVCAP valuespecifiedinthisdatasheetincludesaminimum  
and a maximum value size. Best practice is to meet this  
requirementandnotexceedthemaximumVCAP valuebecause  
the higher inrush currents may reduce the reliability of the  
internal pass transistor. Customers that want to use a larger  
V
CAP value to make sure there is extra store charge should  
discuss their VCAP size selection with Cypress to understand  
any impact on the VCAP voltage level at the end of a tRECALL  
period.  
Table 1. Hardware Mode Selection  
CE  
H
L
WE  
X
HSB  
H
A13–A0  
Mode  
IO  
Power  
Standby  
Active[1]  
Active  
X
X
X
X
Not Selected  
Read SRAM  
Write SRAM  
Output High Z  
Output Data  
Input Data  
H
H
L
L
H
[2]  
X
X
L
Nonvolatile STORE Output High Z  
ICC2  
L
H
H
0x0E38  
0x31C7  
0x03E0  
0x3C1F  
0x303F  
0x0FC0  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
ICC2  
Nonvolatile STORE Output High Z  
L
H
H
0x0E38  
0x31C7  
0x03E0  
0x3C1F  
0x303F  
0x0C63  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Nonvolatile RECALL Output High Z  
Notes  
1. I/O state assumes OE < V . Activation of nonvolatile cycles does not depend on state of OE.  
IL  
2. HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes, the part goes into  
standby mode, inhibiting all operations until HSB rises.  
3. CE and OE LOW and WE HIGH for output behavior.  
4. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.  
5. While there are 15 addresses on the CY14E256L, only the lower 14 are used to control software modes.  
Document Number: 001-06968 Rev. *F  
Page 6 of 18  
         
CY14E256L  
Package Power Dissipation  
Capability (TA = 25°C) ................................................... 1.0W  
Maximum Ratings  
Exceeding maximum ratings may shorten the useful life of the  
device. These user guidelines are not tested.  
Surface Mount Lead Soldering  
Temperature (3 Seconds).......................................... +260°C  
Storage Temperature ................................. –65°C to +150°C  
DC output Current (1 output at a time, 1s duration) .... 15 mA  
Ambient Temperature with  
Power Applied ............................................ –55°C to +125°C  
Static Discharge Voltage.......................................... > 2001V  
(MIL-STD-883, Method 3015)  
Supply Voltage on VCC Relative to GND ..........–0.5V to 7.0V  
Latch Up Current ................................................... > 200 mA  
Voltage Applied to Outputs  
in High Z State.......................................0.5V to VCC + 0.5V  
Operating Range  
Input Voltage...........................................–0.5V to Vcc + 0.5V  
Range  
Commercial  
Industrial  
Ambient Temperature  
0°C to +70°C  
VCC  
Transient Voltage (<20 ns) on  
Any Pin to Ground Potential ..................2.0V to VCC + 2.0V  
4.5V to 5.5V  
4.5V to 5.5V  
-40°C to +85°C  
DC Electrical Characteristics  
Over the operating range (VCC = 4.5V to 5.5V) [6]  
Parameter  
Description  
Test Conditions  
Min  
Max  
Unit  
ICC1  
Average VCC Current  
tRC = 25 ns  
Commercial  
97  
80  
70  
mA  
mA  
t
t
RC = 35 ns  
RC = 45 ns  
Dependent on output loading and cycle rate.  
Values obtained without output loads.  
Industrial  
100  
85  
70  
mA  
mA  
mA  
I
OUT = 0 mA.  
ICC2  
ICC3  
Average VCC Current  
during STORE  
All Inputs Do Not Care, VCC = Max  
Average current for duration tSTORE  
3
mA  
mA  
Average VCC Current at  
WE > (VCC – 0.2V). All other inputs cycling.  
Dependent on output loading and cycle rate. Values obtained  
without output loads.  
10  
t
RC= 200 ns, 5V, 25°C  
Typical  
ICC4  
Average VCAP Current  
during AutoStore Cycle  
All Inputs Do Not Care, VCC = Max  
Average current for duration tSTORE  
2
mA  
mA  
[7]  
ISB  
VCC Standby Current  
CE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V).  
Standby current level after nonvolatile cycle is complete.  
Inputs are static. f = 0 MHz.  
1.5  
[7]  
ISB1  
VCC Standby Current  
(Standby, Cycling TTL  
Input Levels)  
tRC = 25 ns, CE > VIH  
tRC = 35 ns, CE > VIH  
tRC = 45 ns, CE > VIH  
Commercial  
30  
25  
22  
mA  
mA  
mA  
Industrial  
31  
26  
23  
mA  
mA  
mA  
IIX  
Input Leakage Current  
VCC = Max, VSS < VIN < VCC  
-1  
-5  
+1  
+5  
μA  
IOZ  
Off State Output Leakage VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL  
Current  
μA  
VIH  
VIL  
Input HIGH Voltage  
2.2  
VCC  
0.5  
+
V
V
V
Input LOW Voltage  
VSS  
0.5  
0.8  
VOH  
Output HIGH Voltage  
IOUT = –4 mA  
2.4  
Notes  
6.  
V
reference levels throughout this data sheet refer to V if that is where the power supply connection is made, or V  
if V is connected to ground.  
CC  
CC  
CAP CC  
7. CE > V does not produce standby current levels until any nonvolatile cycle in progress has timed out.  
IH  
Document Number: 001-06968 Rev. *F  
Page 7 of 18  
   
CY14E256L  
DC Electrical Characteristics  
Over the operating range (continued)(VCC = 4.5V to 5.5V) [6]  
Parameter  
VOL  
Description  
Test Conditions  
Min  
Max  
0.4  
Unit  
V
Output LOW Voltage  
IOUT = 8 mA  
VBL  
Logic ‘0’ Voltage on HSB IOUT = 3 mA  
Output  
0.4  
V
VCAP  
Storage Capacitor  
Between VCAP pin and Vss, 6V rated. 68 µF +20% nom.  
54  
260  
uF  
Data Retention and Endurance  
Parameter  
Description  
Min  
100  
Unit  
DATAR  
NVC  
Data Retention  
Nonvolatile STORE Operations  
Years  
K
1,000  
Capacitance  
In the following table, the capacitance parameters are listed.[8]  
Parameter  
CIN  
COUT  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
TA = 25°C, f = 1 MHz,  
CC = 0 to 3.0V  
Max  
5
Unit  
pF  
V
7
pF  
Thermal Resistance  
In the following table, the thermal resistance parameters are listed.[8]  
Parameter  
Description  
Test Conditions  
32-SOIC  
32-CDIP  
Unit  
ΘJA  
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard test methods  
and procedures for measuring thermal  
impedance, per EIA / JESD51.  
35.45  
TBD  
°C/W  
ΘJC  
Thermal Resistance  
(Junction to Case)  
13.26  
TBD  
°C/W  
Figure 6. AC Test Loads  
For Tri-state Specs  
R1 963  
Ω
R1 963Ω  
5.0V  
5.0V  
Output  
Output  
R2  
R2  
512  
30 pF  
5 pF  
512Ω  
Ω
AC Test Conditions  
Input Pulse Levels....................................................0V to 3V  
Input Rise and Fall Times (10% - 90%)........................ <5 ns  
Input and Output Timing Reference Levels.................... 1.5V  
Note  
8. These parameters are guaranteed by design and are not tested.  
Document Number: 001-06968 Rev. *F  
Page 8 of 18  
 
CY14E256L  
AC Switching Characteristics  
SRAM Read Cycle  
Parameter  
25 ns  
35 ns  
45 ns  
Unit  
Description  
Cypress  
Alt  
Min  
Max  
Min  
Max  
Min  
Max  
Parameter  
tACE  
tELQV  
tAVAV, ELEH  
tAVQV  
Chip Enable Access Time  
Read Cycle Time  
25  
35  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tRC  
t
25  
35  
45  
tAA  
tDOE  
Address Access Time  
25  
10  
35  
15  
45  
20  
tGLQV  
Output Enable to Data Valid  
Output Hold After Address Change  
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
tOHA  
tAXQX  
5
5
5
5
5
5
tLZCE  
tHZCE  
tLZOE  
tHZOE  
tELQX  
tEHQZ  
10  
10  
25  
13  
13  
35  
15  
15  
45  
tGLQX  
0
0
0
0
0
0
tGHQZ  
[8]  
tPU  
tELICCH  
tEHICCL  
[8]  
tPD  
Switching Waveforms  
Figure 7. SRAM Read Cycle 1: Address Controlled [9, 10]  
W5&  
$''5(66  
W$$  
W2+$  
'4ꢀꢁ'$7$ꢀ287ꢂ  
'$7$ꢀ9$/,'  
Figure 8. SRAM Read Cycle 2: CE and OE Controlled [9]  
W5&  
$''5(66  
&(  
W$&(  
W3'  
W+=&(  
W/=&(  
2(  
W+=2(  
W'2(  
W/=2(  
'4ꢀꢁ'$7$ꢀ287ꢂ  
'$7$ꢀ9$/,'  
$&7,9(  
W38  
67$1'%<  
,&&  
Notes  
9. WE and HSB must be HIGH during SRAM Read cycles.  
10. Device is continuously selected with CE and OE both Low.  
11. Measured ±200 mV from steady state output voltage.  
Document Number: 001-06968 Rev. *F  
Page 9 of 18  
     
CY14E256L  
SRAM Write Cycle  
Parameter  
25 ns  
35 ns  
45 ns  
Unit  
Description  
Write Cycle Time  
Cypress  
Parameter  
Alt  
Min  
Max  
Min  
Max  
Min  
Max  
tWC  
tAVAV  
tWLWH, WLEH  
tELWH, ELEH  
tDVWH, DVEH  
tWHDX, EHDX  
tAVWH, AVEH  
tAVWL, AVEL  
tWHAX, EHAX  
tWLQZ  
tWHQX  
25  
20  
20  
10  
0
35  
25  
25  
12  
0
45  
30  
30  
15  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tPWE  
tSCE  
tSD  
tHD  
tAW  
tSA  
tHA  
tHZWE  
tLZWE  
t
Write Pulse Width  
t
Chip Enable To End of Write  
Data Setup to End of Write  
Data Hold After End of Write  
Address Setup to End of Write  
Address Setup to Start of Write  
Address Hold After End of Write  
Write Enable to Output Disable  
Output Active After End of Write  
t
t
t
20  
0
25  
0
30  
0
t
t
0
0
0
[11,12]  
10  
13  
15  
5
5
5
Switching Waveforms  
Figure 9. SRAM Write Cycle 1: WE Controlled [13, 14]  
tWC  
ADDRESS  
CE  
tHA  
tSCE  
tAW  
tSA  
tPWE  
WE  
tHD  
tSD  
DATA VALID  
DATA IN  
tHZWE  
tLZWE  
HIGH IMPEDANCE  
PREVIOUS DATA  
DATA OUT  
Figure 10. SRAM Write Cycle 2: CE Controlled [13, 14]  
tWC  
ADDRESS  
tHA  
tSCE  
tSA  
CE  
WE  
tAW  
tPWE  
tSD  
tHD  
DATA IN  
DATA VALID  
HIGH IMPEDANCE  
DATA OUT  
Notes  
12. If WE is Low when CE goes Low, the outputs remain in the high impedance state.  
13. HSB must be high during SRAM WRITE cycles.  
14.  
CE or WE must be greater than V during address transitions.  
IH  
Document Number: 001-06968 Rev. *F  
Page 10 of 18  
     
CY14E256L  
AutoStore or Power Up RECALL  
CY14E256L  
Parameter  
Alt  
Description  
Unit  
Min  
Max  
tHRECALL  
tRESTORE  
tHLHZ  
tHLQZ , BLQZ  
Power up RECALL Duration  
STORE Cycle Duration  
550  
10  
μs  
ms  
μs  
V
tSTORE  
tDELAY  
t
Time Allowed to Complete SRAM Cycle  
Low Voltage Trigger Level  
Low Voltage Reset Level  
1
VSWITCH  
VRESET  
tVCCRISE  
4.0  
4.5  
3.6  
V
VCC Rise Time  
150  
μs  
ns  
[13]  
tVSBL  
Low Voltage Trigger (VSWITCH) to HSB low  
300  
Switching Waveforms  
Figure 11. AutoStore/Power Up RECALL  
WE  
Notes  
15. t  
starts from the time V rises above V  
.
SWITCH  
HRECALL  
CC  
16. CE and OE low and WE high for output behavior.  
17. HSB is asserted low for 1us when V  
drops through V  
. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB is released and no store  
CAP  
SWITCH  
takes place.  
Document Number: 001-06968 Rev. *F  
Page 11 of 18  
   
CY14E256L  
Software Controlled STORE/RECALL Cycle  
The software controlled STORE/RECALL cycle follows. [19]  
25 ns  
35 ns  
45 ns  
Unit  
Parameter  
Alt  
Description  
Min  
Max  
Min  
Max  
Min  
Max  
tRC  
tAVAV  
tAVEL  
tELEH  
tELAX  
STORE/RECALL Initiation Cycle Time  
Address Setup Time  
25  
0
35  
0
45  
0
ns  
ns  
ns  
ns  
μs  
[18, 19]  
tSA  
tCW  
Clock Pulse Width  
20  
20  
25  
20  
30  
20  
[18, 19]  
tHACE  
Address Hold Time  
tRECALL  
RECALL Duration  
20  
20  
20  
Switching Waveforms  
Figure 12. CE Controlled Software STORE/RECALL Cycle [19]  
tRC  
tRC  
ADDRESS # 1  
ADDRESS # 6  
ADDRESS  
CE  
tSA  
tSCE  
tHACE  
OE  
t
STORE / tRECALL  
HIGH IMPEDANCE  
DATA VALID  
DATA VALID  
DQ (DATA)  
Notes  
18. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).  
19. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.  
Document Number: 001-06968 Rev. *F  
Page 12 of 18  
   
CY14E256L  
Hardware STORE Cycle  
CY14E256L  
Parameter  
Alt  
Description  
Unit  
Min  
Max  
tDHSB  
tPHSB  
tHLBL  
tRECOVER, HHQX  
t
Hardware STORE High to Inhibit Off  
Hardware STORE Pulse Width  
700  
ns  
ns  
ns  
tHLHX  
15  
Hardware STORE Low to STORE Busy  
300  
Switching Waveforms  
Figure 13. Hardware STORE Cycle  
Note  
20. t  
is only applicable after t  
is complete.  
STORE  
DHSB  
Document Number: 001-06968 Rev. *F  
Page 13 of 18  
 
CY14E256L  
Part Numbering Nomenclature (Commercial and Industrial)  
CY 14 E 256 L- SZ 25 X C T  
Option:  
T-Tape and Reel  
Blank - Std.  
Temperature:  
C - Commercial (0 to 70°C)  
I - Industrial (-40 to 85°C)  
Speed:  
Pb-Free  
25 - 25 ns  
35 - 35 ns  
45 - 45 ns  
Package  
SZ - 32-SOIC  
D - 32-CDIP  
Data Bus:  
L - x8  
Density:  
256 - 256 Kb  
Voltage:  
E - 5.0V  
nvSRAM  
14 - AutoStore + Software Store + Hardware Store  
Cypress  
Ordering Information  
Speed  
(ns)  
Operating  
Range  
Ordering Code  
Package Diagram  
Package Type  
25  
CY14E256L-SZ25XCT  
CY14E256L-SZ25XC  
CY14E256L-SZ25XIT  
CY14E256L-SZ25XI  
CY14E256L-SZ35XCT  
CY14E256L-SZ35XC  
CY14E256L-SZ35XIT  
CY14E256L-SZ35XI  
CY14E256L-SZ45XCT  
CY14E256L-SZ45XC  
CY14E256L-SZ45XIT  
CY14E256L-SZ45XI  
CY14E256L-D45XI  
51-85127  
51-85127  
51-85127  
51-85127  
51-85127  
51-85127  
51-85127  
51-85127  
51-85127  
51-85127  
51-85127  
51-85127  
001-51694  
32-pin SOIC (300 mil)  
32-pin SOIC (300 mil)  
32-pin SOIC (300 mil)  
32-pin SOIC (300 mil)  
32-pin SOIC (300 mil)  
32-pin SOIC (300 mil)  
32-pin SOIC (300 mil)  
32-pin SOIC (300 mil)  
32-pin SOIC (300 mil)  
32-pin SOIC (300 mil)  
32-pin SOIC (300 mil)  
32-pin SOIC (300 mil)  
32-pin CDIP (300 mil)  
Commercial  
Industrial  
35  
45  
Commercial  
Industrial  
Commercial  
Industrial  
All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts  
Document Number: 001-06968 Rev. *F  
Page 14 of 18  
CY14E256L  
Package Diagram  
Figure 14. 32-Pin (300 Mil) SOIC (51-85127)  
PIN 1 ID  
16  
1
MIN.  
MAX.  
DIMENSIONS IN INCHES[MM]  
REFERENCE JEDEC MO-119  
0.292[7.416]  
0.299[7.594]  
0.405[10.287]  
0.419[10.642]  
PART #  
17  
32  
S32.3 STANDARD PKG.  
SZ32.3 LEAD FREE PKG.  
SEATING PLANE  
0.810[20.574]  
0.822[20.878]  
0.090[2.286]  
0.100[2.540]  
0.004[0.101]  
0.050[1.270]  
TYP.  
0.006[0.152]  
0.012[0.304]  
0.041[1.041]  
0.026[0.660]  
0.032[0.812]  
0.021[0.533]  
0.004[0.101]  
0.0100[0.254]  
0.014[0.355]  
0.020[0.508]  
51-85127-*A  
Document Number: 001-06968 Rev. *F  
Page 15 of 18  
CY14E256L  
Package Diagram (continued)  
Figure 15. 32-Pin (300 Mil) CDIP (001-51694)  
001-51694 **  
Document Number: 001-06968 Rev. *F  
Page 16 of 18  
CY14E256L  
Document History Page  
Document Title: CY14E256L 256 Kbit (32K x 8) nvSRAM  
Document Number: 001-06968  
Submission  
Date  
Orig. of  
Change  
Rev.  
ECN No.  
Description of Change  
**  
427789  
437321  
472053  
503290  
See ECN  
See ECN  
See ECN  
See ECN  
TUP  
TUP  
TUP  
PCI  
New data sheet  
Show data sheet on external Web  
*A  
*B  
*C  
Updated Part Numbering Nomenclature and Ordering Information  
Changed from “Advance” to “Preliminary”  
Changed the term “Unlimited” to “Infinite”  
Changed ICC3 value from 10mA to 15mA  
Removed Industrial Grade mention  
Removed 35 ns speed bin  
Removed ICC1 values from the DC table for 35 ns Industrial Grade  
Corrected VIL min specification from (VCC - 0.5) to (VSS - 0.5)  
Removed all references pertaining to OE controlled Software STORE and  
RECALL operation  
Changed the address locations of the software STORE/RECALL com-  
mand  
Updated Part Nomenclature Table and Ordering Information Table  
*D  
1349963  
See ECN  
UHA/SFV  
GVCH  
Changed from “Preliminary” to “Final.” Updated AC Test Conditions  
Updated Ordering Information Table  
*E  
*F  
2427986  
2606744  
See ECN  
02/19/09  
Move to external web  
GVCH/PYRS Updated Feature Section  
Added 35 ns access speed specs  
Added CDIP package  
Removed HSB ganging feature  
Added footnote 5  
Updates all the notes  
Added Best practices  
Added Industrial specs  
Changed Icc3 from 15 mA to 10 mA  
Added ISB1 spec  
Added parameter VBL  
Changed VIH test conditions from -2 and 4 to -4 and 8mA  
Added footnote 6 and 7  
Added tVSBL and VRESET parameter to Autostore or Power-up Recall table  
Added Thermal resistance values  
Changed parameter tAS to tSA  
Renamed tGLAX to tHACE  
Renamed tRESTORE to tDHSB  
Updated Figure 13  
Document Number: 001-06968 Rev. *F  
Page 17 of 18  
CY14E256L  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales  
Products  
PSoC  
PSoC Solutions  
General  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-06968 Rev. *F  
Revised January 30, 2009  
Page 18 of 18  
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective  
holders.  

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