PRELIMINARY
CY14B108L, CY14B108N
8 Mbit (1024K x 8/512K x 16) nvSRAM
Features
Functional Description
■ 20 ns, 25 ns, and 45 ns Access Times
The Cypress CY14B108L/CY14B108N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
■ Internally organized as 1024K x 8 (CY14B108L) or 512K x 16
(CY14B108N)
organized as 1024 Kbytes of 8 bits each or 512K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
■ Hands off Automatic STORE on power down with only a small
Capacitor
®
■ STORE to QuantumTrap nonvolatile elements initiated by
®
Software, device pin, or AutoStore on power down
■ RECALL to SRAM initiated by Software or power up
■ Infinite Read, Write, and RECALL Cycles
■ 200,000 STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3V +20%, -10% operation
■ Commercial and Industrial Temperatures
■ 48-ball FBGA and 44-pin and 54-pin TSOP-II packages
■ Pb-free and RoHS compliant
VCAP
VCC
Quatrum Trap
2048 X 2048 X 2
A0
A1
A2
A3
A4
A5
A6
POWER
R
CONTROL
STORE
O
W
RECALL
STORE/RECALL
CONTROL
D
E
C
O
D
E
R
HSB
STATIC RAM
ARRAY
2048 X 2048 X 2
A7
A8
A17
SOFTWARE
DETECT
A14 - A2
A18
A19
DQ0
DQ1
DQ2
DQ3
I
DQ4
DQ5
DQ6
N
P
U
T
B
U
F
F
E
R
S
DQ7
COLUMN I/O
DQ8
DQ9
DQ10
OE
COLUMN DEC
WE
DQ11
DQ12
DQ13
DQ14
CE
BLE
A9 A10 A11 A12 A13 A14 A15 A16
DQ15
BHE
Note
1. Address A - A for x8 configuration and Address A - A for x16 configuration.
0
19
0
18
2. Data DQ - DQ for x8 configuration and Data DQ - DQ for x16 configuration.
0
7
0
15
3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-45523 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 19, 2009
PRELIMINARY
CY14B108L, CY14B108N
Table 1. Pin Definitions
Pin Name
I/O Type
Description
A – A
Input
Address Inputs Used to Select one of the 1,048,576 bytes of the nvSRAM for x8 Configuration.
0
19
18
A – A
Address Inputs Used to Select one of the 524,288 words of the nvSRAM for x16 Configuration.
0
DQ – DQ
Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on
0
7
operation.
DQ – DQ
Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on
0
15
operation.
WE
Input
Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the specific
address location.
Input
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
CE
OE
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. IO pins are tri-stated on deasserting OE HIGH.
Input
Input
Byte High Enable, Active LOW. Controls DQ - DQ .
BHE
BLE
15
8
Byte Low Enable, Active LOW. Controls DQ - DQ .
7
0
V
Ground
Ground for the Device. Must be connected to the ground of the system.
SS
V
Power Supply Power Supply Inputs to the Device.
CC
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in
progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak
internal pull up resistor keeps this pin HIGH if not connected (connection optional). After each STORE
operation HSB will be driven HIGH for short time with standard output high current.
HSB
V
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
CAP
nonvolatile elements.
NC
No Connect No Connect. This pin is not connected to the die.
Document #: 001-45523 Rev. *B
Page 3 of 24
PRELIMINARY
CY14B108L, CY14B108N
Figure 3 shows the proper connection of the storage capacitor
Device Operation
CAP
The CY14B108L/CY14B108N nvSRAM is made up of two
functional components paired in the same physical cell. They are
a SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B108L/CY14B108N supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
page 16 for a complete description of read and write modes.
. The voltage on
CAP
the V
pin is driven to V by a regulator on the chip. A pull
CAP
CC
up should be placed on WE to hold it inactive during power up.
This pull up is effective only if the WE signal is tri-state during
power up. Many MPUs tri-state their controls on power up. This
should be verified when using the pull up. When the nvSRAM
comes out of power-on-recall, the MPU must be active or the WE
held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
SRAM Read
Figure 3. AutoStore Mode
The CY14B108L/CY14B108N performs a read cycle when CE
and OE are LOW and WE and HSB are HIGH. The address
Vcc
specified on pins A
or A
determines which of the
0-19
0-18
1,048,576 data bytes or 524,288 words of 16 bits each are
accessed. Byte enables (BHE, BLE) determine which bytes are
enabled to the output, in the case of 16-bit words. When the read
is initiated by an address transition, the outputs are valid after a
0.1uF
Vcc
delay of t (read cycle 1). If the read is initiated by CE or OE,
AA
the outputs are valid at t
or at t
, whichever is later (read
ACE
DOE
cycle 2). The data output repeatedly responds to address
WE
VCAP
changes within the t access time without the need for transi-
AA
tions on any control input pins. This remains valid until another
address change or until CE or OE is brought HIGH, or WE or
HSB is brought LOW.
VCAP
VSS
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
Hardware STORE Operation
the end of the cycle. The data on the common I/O pins DQ
0–15
The CY14B108L/CY14B108N provides the HSB pin to control
and acknowledge the STORE operations. Use the HSB pin to
request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B108L/CY14B108N conditionally initiates a
are written into the memory if the data is valid t before the end
SD
of a WE controlled write or before the end of an CE controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. Keep OE HIGH during
the entire write cycle to avoid data bus contention on common
I/O lines. If OE is left LOW, internal circuitry turns off the output
STORE operation after t
. An actual STORE cycle only
DELAY
begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven LOW to indicate a busy
condition when the STORE (initiated by any means) is in
progress.
buffers t
after WE goes LOW.
HZWE
AutoStore Operation
SRAM read and write operations that are in progress when HSB
is driven LOW by any means are given time to complete before
the STORE operation is initiated. After HSB goes LOW, the
CY14B108L/CY14B108N continues SRAM operations for
The CY14B108L/CY14B108N stores data to the nvSRAM using
one of the following three storage operations: Hardware STORE
activated by HSB; Software STORE activated by an address
sequence; AutoStore on device power down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14B108L/CY14B108N.
t
. If a write is in progress when HSB is pulled LOW it is
DELAY
enabled a time, t
to complete. However, any SRAM write
DELAY
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B108L/CY14B108N. But any SRAM read and
write cycles are inhibited until HSB is returned HIGH by MPU or
other external source.
During a normal operation, the device draws current from V to
CC
charge a capacitor connected to the V
pin. This stored
CAP
charge is used by the chip to perform a single STORE operation.
If the voltage on the V pin drops below V , the part
CC
SWITCH
automatically disconnects the V
pin from V . A STORE
CAP
CC
During any STORE operation, regardless of how it is initiated,
the CY14B108L/CY14B108N continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Once the
operation is initiated with power provided by the V
capacitor.
CAP
Document #: 001-45523 Rev. *B
Page 4 of 24
PRELIMINARY
CY14B108L, CY14B108N
STORE operation is completed, the CY14B108L/CY14B108N
remains disabled until the HSB pin returns HIGH. Leave the HSB
unconnected if it is not used.
The software sequence may be clocked with CE controlled reads
or OE controlled reads. After the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. HSB is driven LOW. It is important to use read cycles
and not write cycles in the sequence, although it is not necessary
Hardware RECALL (Power Up)
During power up or after any low power condition
that OE be LOW for a valid sequence. After the t
cycle time
STORE
is fulfilled, the SRAM is activated again for the read and write
operation.
(V < V
), an internal RECALL request is latched. When
CC
SWITCH
V
again exceeds the sense voltage of V
cycle is automatically initiated and takes t
, a RECALL
to complete.
CC
SWITCH
HRECALL
Software RECALL
During this time, HSB is driven LOW by the HSB driver.
Transfer the data from the nonvolatile memory to the SRAM with
a software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed.
Software STORE
Transfer data from the SRAM to the nonvolatile memory with a
software address sequence. The CY14B108L/CY14B108N
Software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared; then, the nonvolatile information is transferred
To initiate the Software STORE cycle, the following read
sequence must be performed.
into the SRAM cells. After the t
cycle time, the SRAM is
RECALL
again ready for read and write operations. The RECALL
operation does not alter the data in the nonvolatile elements.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
Document #: 001-45523 Rev. *B
Page 5 of 24
PRELIMINARY
CY14B108L, CY14B108N
Table 2. Mode Selection
A
- A
X
Mode
IO
Power
Standby
Active
CE
WE
OE, BHE, BLE
15
0
H
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
L
L
L
H
L
L
X
L
X
X
Active
[6]
H
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
Disable
[6]
L
L
L
H
H
H
L
L
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active I
CC2
[6]
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
Notes
5. While there are 20 address lines on the CY14B108L (19 address lines on the CY14B108N), only the 13 address lines (A - A ) are used to control software modes.
14
2
Rest of the address lines are don’t care.
6. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document #: 001-45523 Rev. *B
Page 6 of 24
PRELIMINARY
CY14B108L, CY14B108N
Preventing AutoStore
Noise Considerations
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
■ ThenonvolatilecellsinthisnvSRAMproductaredeliveredfrom
Cypress with 0x00 written in all cells. Incoming inspection
routines at customer or contract manufacturer’s sites
sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex
or more random bytes) as part of the final system manufac-
turing test to ensure these system routines work consistently.
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the Software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
■ Power up boot firmware routines should rewrite the nvSRAM
into the desired state (for example, autostore enabled). While
the nvSRAM is shipped in a preset state, best practice is to
again rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently such as
program bugs and incoming inspection routines.
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power down
cycles. The part comes from the factory with AutoStore enabled.
■ The VCAP value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirementandnotexceedthemaximumVCAPvaluebecause
the nvSRAM internal algorithm calculates VCAP charge and
Data Protection
discharge time based on this max V
value. Customers that
CAP
want to use a larger VCAP value to make sure there is extra
store charge and store time should discuss their VCAP size
selection with Cypress to understand any impact on the VCAP
voltage level at the end of a tRECALL period.
The CY14B108L/CY14B108N protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected when V < V
. If the CY14B108L/CY14B108N
CC
SWITCH
is in a write mode (both CE and WE are LOW) at power up, after
a RECALL or STORE, the write is inhibited until the SRAM is
enabled after t
(HSB to output active). This protects against
LZHSB
inadvertent writes during power up or brown out conditions.
Document #: 001-45523 Rev. *B
Page 7 of 24
PRELIMINARY
CY14B108L, CY14B108N
Transient Voltage (<20 ns) on
Any Pin to Ground Potential................ ..–2.0V to V + 2.0V
Maximum Ratings
CC
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Package Power Dissipation
Capability (T = 25°C)....................................................1.0W
A
Storage Temperature ..................................–65°C to +150°C
Maximum Accumulated Storage Time
Surface Mount Pb Soldering
Temperature (3 Seconds)...........................................+260°C
DC Output Current (1 output at a time, 1s duration) ....15 mA
At 150°C Ambient Temperature..........................1000h
At 85°C Ambient Temperature.................... ..20 Years
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Ambient Temperature with
Power Applied.............................................–55°C to +150°C
Latch Up Current................................................... > 200 mA
Supply Voltage on V Relative to GND.......... –0.5V to 4.1V
Operating Range
CC
Voltage Applied to Outputs
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
V
CC
in High-Z State ...................................... –0.5V to V + 0.5V
CC
2.7V to 3.6V
2.7V to 3.6V
Input Voltage ..........................................–0.5V to Vcc + 0.5V
–40°C to +85°C
DC Electrical Characteristics
Over the Operating Range (V = 2.7V to 3.6V)
CC
Parameter
Description
Average V Current
Test Conditions
Min
Max
Unit
I
t
t
t
= 20 ns
= 25 ns
= 45 ns
Commercial
Industrial
70
70
55
mA
mA
mA
CC1
CC
RC
RC
RC
Values obtained without output loads (I
= 0 mA)
= 0 mA).
OUT
OUT
75
75
57
mA
mA
mA
I
I
Average V Current All Inputs Don’t Care, V = Max
20
mA
CC2
CC
CC
during STORE
Average current for duration t
STORE
AverageV Currentat All I/P cycling at CMOS levels.
40
mA
CC3
CC
t
= 200 ns, 3V, 25°C Values obtained without output loads (I
RC
typical
I
I
Average V
Current All Inputs Don’t Care, V = Max
10
10
mA
mA
CC4
CAP
CC
during AutoStore Cycle Average current for duration t
STORE
V
Standby Current CE > (V – 0.2V). All others V < 0.2V or > (V – 0.2V). Standby
CC IN CC
SB
CC
current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
[8]
IX
I
Input Leakage Current V = Max, V < V < V
(except HSB)
–2
–200
–2
+2
+2
+2
μA
μA
μA
V
CC
SS
IN
CC
Input Leakage Current V = Max, V < V < V
CC
SS
IN
CC
(for HSB)
I
Off-State Output
Leakage Current
V
= Max, V < V
< V , CE or OE > V or BHE/BLE > V
IH
OZ
CC
SS
OUT
CC
IH
or WE < V
IL
V
Input HIGH Voltage
2.0
V
+
IH
CC
0.5
V
V
V
V
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Storage Capacitor
V
– 0.5
ss
0.8
V
V
IL
I
I
= –2 mA
= 4 mA
2.4
OH
OL
OUT
0.4
V
OUT
Between V
pin and V , 5V Rated
122
360
μF
CAP
CAP
SS
Notes
7. Typical conditions for the active current shown on the DC Electrical characteristics are average values at 25°C (room temperature), and V = 3V. Not 100% tested.
CC
8. The HSB pin has I
= -2 uA for V of 2.4V when both active HIGH and LOW drivers are disabled. When they are enabled standard V and V are valid. This
OUT
O
H
O
H
O
L
parameter is characterized but not tested.
V (Storage capacitor) nominal value is 150uF.
CAP
9.
Document #: 001-45523 Rev. *B
Page 8 of 24
PRELIMINARY
CY14B108L, CY14B108N
Data Retention and Endurance
Parameter
Description
Min
20
Unit
Years
K
DATA
Data Retention
R
NV
Nonvolatile STORE Operations
200
C
Capacitance
In the following table, the capacitance parameters are listed.
Parameter Description
Input Capacitance
Output Capacitance
Test Conditions
Max
14
Unit
C
C
T = 25°C, f = 1 MHz,
pF
pF
IN
A
V
= 0 to 3.0V
CC
14
OUT
Thermal Resistance
In the following table, the thermal resistance parameters are listed.
Parameter
Description
Test Conditions
Test conditions follow standard test methods
48-FBGA 44-TSOP II 54-TSOP II Unit
ΘJA
Thermal Resistance
(Junction to Ambient) and procedures for measuring thermal
28.82
31.11
30.73
°C/W
impedance, in accordance with EIA/JESD51.
ΘJC
Thermal Resistance
(Junction to Case)
7.84
5.56
6.08
°C/W
Figure 4. AC Test Loads
577 Ω
for tri-state specs
577 Ω
3.0V
OUTPUT
3.0V
OUTPUT
R1
R1
R2
789 Ω
R2
789 Ω
5 pF
30 pF
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V
Input Rise and Fall Times (10% - 90%)........................ <3 ns
Input and Output Timing Reference Levels .................... 1.5V
Note
10. These parameters are guaranteed but not tested.
Document #: 001-45523 Rev. *B
Page 9 of 24
PRELIMINARY
CY14B108L, CY14B108N
AC Switching Characteristics
Parameters
20 ns
25 ns
45 ns
Description
Unit
Cypress
Alt
Min
Max
Min
Max
Min
Max
Parameters Parameters
SRAM Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
20
25
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ACE
RC
ACS
RC
AA
20
25
45
Address Access Time
20
10
25
12
45
20
AA
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Byte Enable to Data Valid
DOE
OHA
OE
OH
LZ
3
3
3
3
3
3
LZCE
HZCE
LZOE
8
8
10
10
15
15
HZ
0
0
0
0
0
0
OLZ
OHZ
PA
HZOE
PU
PD
20
10
25
12
45
20
PS
-
-
-
DBE
Byte Enable to Output Active
Byte Disable to Output Inactive
0
0
0
LZBE
HZBE
8
10
15
SRAM Write Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
20
15
15
8
25
20
20
10
0
45
30
30
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
PWE
SCE
SD
WC
WP
CW
DW
DH
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active after End of Write
Byte Enable to End of Write
0
HD
15
0
20
0
30
0
AW
AW
AS
SA
0
0
0
HA
WR
WZ
OW
8
10
15
HZWE
3
3
3
LZWE
BW
-
15
20
30
Switching Waveforms
Figure 5. SRAM Read Cycle #1: Address Controlled
tRC
Address
Address Valid
tAA
Output Data Valid
Previous Data Valid
tOHA
Data Output
Notes
11. WE must be HIGH during SRAM read cycles.
12. Device is continuously selected with CE, OE and BHE / BLE LOW.
13. Measured ±200 mV from steady state output voltage.
14. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
15. HSB must remain HIGH during READ and WRITE cycles.
Document #: 001-45523 Rev. *B
Page 10 of 24
PRELIMINARY
CY14B108L, CY14B108N
Figure 6. SRAM Read Cycle #2: CE and OE Controlled
Address
CE
Address Valid
tRC
tHZCE
tACE
tAA
tLZCE
tHZOE
tDOE
OE
tHZBE
tLZOE
tDBE
BHE, BLE
tLZBE
High Impedance
Data Output
Output Data Valid
tPU
tPD
Active
ICC
Standby
Figure 7. SRAM Write Cycle #1: WE Controlled
W:&
$GGUHVV
$GGUHVVꢀ9DOLG
W6&(
W+$
&(
W%:
%+(ꢁꢀ%/(
W$:
W3:(
:(
'DWDꢀ,QSXW
'DWDꢀ2XWSXW
W6$
W+'
W6'
,QSXWꢀ'DWDꢀ9DOLG
W/=:(
W+=:(
+LJKꢀ,PSHGDQFH
3UHYLRXVꢀ'DWD
Notes
16. CE or WE must be >V during address transitions.
IH
Document #: 001-45523 Rev. *B
Page 11 of 24
PRELIMINARY
CY14B108L, CY14B108N
Figure 8. SRAM Write Cycle #2: CE Controlled
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tBW
BHE, BLE
tPWE
WE
tHD
tSD
Input Data Valid
Data Input
High Impedance
Data Output
Figure 9. SRAM Write Cycle #3: BHE and BLE Controlled
tWC
Address
CE
Address Valid
tSCE
tSA
tHA
tBW
BHE, BLE
WE
tAW
tPWE
tSD
tHD
Data Input
Input Data Valid
High Impedance
Data Output
Document #: 001-45523 Rev. *B
Page 12 of 24
PRELIMINARY
CY14B108L, CY14B108N
AutoStore/Power Up RECALL
20 ns
25 ns
45 ns
Parameters
Description
Unit
Min
Max
Min
Max
20
Min
Max
20
t
t
t
Power Up RECALL Duration
STORE Cycle Duration
20
8
ms
ms
ns
V
HRECALL
8
8
STORE
DELAY
Time Allowed to Complete SRAM Cycle
Low Voltage Trigger Level
VCC Rise Time
20
25
25
V
t
2.65
2.65
2.65
SWITCH
150
150
150
μs
V
VCCRISE
V
HSB Output Driver Disable Voltage
HSB To Output Active Time
HSB High Active Time
1.9
5
1.9
5
1.9
5
HDIS
LZHSB
HHHD
t
t
μs
ns
500
500
500
Switching Waveforms
Figure 10. AutoStore or Power Up RECALL
VSWITCH
VHDIS
Note18
Note18
VVCCRISE
tSTORE
tSTORE
Note21
tHHHD
tHHHD
HSB OUT
Autostore
tDELAY
tLZHSB
tLZHSB
tDELAY
POWER-
UP
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(RWI)
Read & Write
Read & Write
POWER-UP
RECALL
BROWN
OUT
Autostore
POWER
DOWN
Autostore
POWER-UP
RECALL
Notes
17. t
starts from the time V rises above V
SWITCH.
HRECALL
CC
18. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware Store takes place.
19. On a Hardware STORE, Software STORE / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time t
.
DELAY
20. Read and Write cycles are ignored during STORE, RECALL, and while V is below V
CC
SWITCH.
21. HSB pin is driven HIGH to V only by internal 100kOhm resistor, HSB driver is disabled.
CC
Document #: 001-45523 Rev. *B
Page 13 of 24
PRELIMINARY
CY14B108L, CY14B108N
Software Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE and RECALL cycle parameters are listed.
20 ns
Max
25 ns
Max
45 ns
Max
Parameters
Description
Unit
Min
20
0
Min
25
0
Min
45
0
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
Address Setup Time
ns
ns
ns
ns
μs
RC
SA
Clock Pulse Width
15
0
20
0
30
0
CW
Address Hold Time
HA
RECALL Duration
200
200
200
RECALL
Switching Waveforms
Figure 11. CE and OE Controlled Software STORE/RECALL Cycle
tRC
tRC
Address
CE
Address #1
tCW
Address #6
tCW
tSA
tHA
tHA
tHA
tSA
tHA
OE
tDELAY
tHHHD
tHZCE
HSB (STORE only)
DQ (DATA)
tLZCE
tLZHSB
High Impedance
tSTORE/tRECALL
RWI
Figure 12. Autostore Enable/Disable Cycle
tRC
tRC
Address
Address #1
tCW
Address #6
tCW
tSA
CE
tSA
tHA
tHA
tHA
tHA
OE
tSS
tHZCE
tLZCE
tDELAY
DQ (DATA)
Notes
22. The software sequence is clocked with CE controlled or OE controlled reads.
23. The six consecutive addresses must be read in the order listed in Table 2 on page 6. WE must be HIGH during all six consecutive cycles.
Document #: 001-45523 Rev. *B
Page 14 of 24
PRELIMINARY
CY14B108L, CY14B108N
Hardware STORE Cycle
20 ns
25 ns
45 ns
Parameters
Description
Unit
Min
Max
Min
Max
Min
Max
t
t
t
HSB To Output Active Time when write latch not set
Hardware STORE Pulse Width
20
25
25
ns
ns
μs
DHSB
15
15
15
PHSB
Soft Sequence Processing Time
100
100
100
SS
Switching Waveforms
Figure 13. Hardware STORE Cycle
Write latch set
tPHSB
HSB (IN)
tSTORE
tHHHD
tDELAY
HSB (OUT)
DQ (Data Out)
RWI
tLZHSB
Write latch not set
tPHSB
HSB pin is driven high to VCC only by Internal
100kOhm resistor,
HSB (IN)
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
tDELAY
tDHSB
tDHSB
HSB (OUT)
RWI
Figure 14. Soft Sequence Processing
tSS
tSS
Soft Sequence
Command
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
Address #1
Address #6
tCW
CE
VCC
Notes
24. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
25. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
Document #: 001-45523 Rev. *B
Page 15 of 24
PRELIMINARY
CY14B108L, CY14B108N
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
For x8 Configuration
[2]
CE
H
L
WE
X
OE
X
Inputs/Outputs
Mode
Power
Standby
Active
High Z
Data Out (DQ –DQ );
Deselect/Power down
Read
H
L
0
7
L
H
H
High Z
Data in (DQ –DQ );
Output Disabled
Write
Active
L
L
X
Active
0
7
For x16 Configuration
[2]
CE
H
L
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
Mode
Power
Standby
High-Z
High-Z
Deselect/Power down
Output Disabled
Read
X
X
H
H
Active
Active
Active
L
H
L
L
L
Data Out (DQ –DQ
)
0
15
L
H
L
H
L
Data Out (DQ –DQ );
Read
0
7
DQ –DQ in High-Z
8
15
L
H
L
L
H
Data Out (DQ –DQ );
Read
Active
8
15
DQ –DQ in High-Z
0
7
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High-Z
Output Disabled
Output Disabled
Output Disabled
Write
Active
Active
Active
Active
Active
High-Z
High-Z
L
Data In (DQ –DQ
)
15
0
L
H
Data In (DQ –DQ );
Write
0
7
DQ –DQ in High-Z
8
15
L
L
X
L
H
Data In (DQ –DQ );
Write
Active
8
15
DQ –DQ in High-Z
0
7
Document #: 001-45523 Rev. *B
Page 16 of 24
PRELIMINARY
CY14B108L, CY14B108N
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
20
CY14B108L-ZS20XCT
CY14B108L-ZS20XC
CY14B108L-ZS20XIT
CY14B108L-ZS20XI
CY14B108L-BA20XCT
CY14B108L-BA20XC
CY14B108L-BA20XIT
CY14B108L-BA20XI
CY14B108N-BA20XCT
CY14B108N-BA20XC
CY14B108N-BA20XIT
CY14B108N-BA20XI
CY14B108N-ZSP20XCT
CY14B108N-ZSP20XC
CY14B108N-ZSP20XIT
CY14B108N-ZSP20XI
CY14B108L-ZS25XCT
CY14B108L-ZS25XC
CY14B108L-ZS25XIT
CY14B108L-ZS25XI
CY14B108L-BA25XCT
CY14B108L-BA25XC
CY14B108L-BA25XIT
CY14B108L-BA25XI
CY14B108N-BA25XCT
CY14B108N-BA25XC
CY14B108N-BA25XIT
CY14B108N-BA25XI
CY14B108N-ZSP25XCT
CY14B108N-ZSP25XC
CY14B108N-ZSP25XIT
CY14B108N-ZSP25XI
51-85087
51-85087
51-85087
51-85087
51-85128
51-85128
51-85128
51-85128
51-85128
51-85128
51-85128
51-85128
51-85160
51-85160
51-85160
51-85160
51-85087
51-85087
51-85087
51-85087
51-85128
51-85128
51-85128
51-85128
51-85128
51-85128
51-85128
51-85128
51-85160
51-85160
51-85160
51-85160
44-pin TSOP II
44-pin TSOP II
Commercial
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
44-pin TSOP II
44-pin TSOP II
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
25
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Document #: 001-45523 Rev. *B
Page 17 of 24
PRELIMINARY
CY14B108L, CY14B108N
Ordering Information (continued)
Speed
Package
Diagram
Operating
Range
Ordering Code
(ns)
Package Type
45
CY14B108L-ZS45XCT
CY14B108L-ZS45XC
CY14B108L-ZS45XIT
CY14B108L-ZS45XI
CY14B108L-BA45XCT
CY14B108L-BA45XC
CY14B108L-BA45XIT
CY14B108L-BA45XI
CY14B108N-BA45XCT
CY14B108N-BA45XC
CY14B108N-BA45XIT
CY14B108N-BA45XI
CY14B108N-ZSP45XCT
CY14B108N-ZSP45XC
CY14B108N-ZSP45XIT
CY14B108N-ZSP45XI
51-85087
51-85087
51-85087
51-85087
51-85128
51-85128
51-85128
51-85128
51-85128
51-85128
51-85128
51-85128
51-85160
51-85160
51-85160
51-85160
44-pin TSOP II
44-pin TSOP II
Commercial
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
All parts are Pb-free. The above table contains Preliminary information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 001-45523 Rev. *B
Page 18 of 24
PRELIMINARY
CY14B108L, CY14B108N
Part Numbering Nomenclature
CY 14 B 108L-ZS P 20 X C T
Option:
T - Tape & Reel
Blank - Std.
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Speed:
20 - 20 ns
Pb-Free
25 - 25 ns
45 - 45 ns
P - 54 Pin
Blank - 44 Pin/48 Ball
Package:
BA - 48 FBGA
ZS - TSOP II
Data Bus:
L - x8
N - x16
Density:
108 - 8 Mb
Voltage:
B - 3.0V
NVSRAM
14 - Auto Store + Software STORE + Hardware STORE
Cypress
Document #: 001-45523 Rev. *B
Page 19 of 24
PRELIMINARY
CY14B108L, CY14B108N
Package Diagrams
Figure 15. 44-Pin TSOP II (51-85087)
DIMENSION IN MM (INCH)
MAX
MIN.
PIN 1 I.D.
22
1
R
O
E
K
A
X
S G
EJECTOR PIN
23
44
TOP VIEW
BOTTOM VIEW
10.262 (0.404)
10.058 (0.396)
0.400(0.016)
0.300 (0.012)
0.800 BSC
(0.0315)
BASE PLANE
0.10 (.004)
0.210 (0.0083)
0.120 (0.0047)
0°-5°
18.517 (0.729)
18.313 (0.721)
0.597 (0.0235)
0.406 (0.0160)
SEATING
PLANE
51-85087-*A
Document #: 001-45523 Rev. *B
Page 20 of 24
PRELIMINARY
CY14B108L, CY14B108N
Package Diagrams (continued)
Figure 16. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30 0.05(48X)
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15(4X)
SEATING PLANE
C
51-85128-*D
Document #: 001-45523 Rev. *B
Page 21 of 24
PRELIMINARY
CY14B108L, CY14B108N
Package Diagrams (continued)
Figure 17. 54-Pin TSOP II (51-85160)
51-85160-**
Document #: 001-45523 Rev. *B
Page 22 of 24
PRELIMINARY
CY14B108L, CY14B108N
Document History Page
Document Title: CY14B108L/CY14B108N 8 Mbit (1024K x 8/512K x 16) nvSRAM
Document Number: 001-45523
Submission
Rev. ECN No. Orig. of Change
Description of Change
Date
**
2428826
2520023
GVCH
See ECN
06/23/08
New Data Sheet
Updated I for tRC=20ns, 25ns and 45ns access speed for both industrial
*A
GVCH/PYRS
CC1
and Commercial temperature Grade
Updated Thermal resistance values for 48-FBGA,44-TSOP II and 54-TSOP II
packages
Changed t
value from 16ns to 15ns
CW
*B
2676670
GVCH/PYRS
03/20/2009 Added maximum accumulated storage time for 150°C and 85°C Temperature
Added best practices
Changed I
Changed I
Changed I
from 12mA to 20mA
from 38mA to 40mA
from 12mA to 10mA
CC2
CC3
CC4
Changed I from 6mA to 10mA
SB
Changed V
from 164uF to 360uF
CAP
Changed Input Rise and Fall Times from 5ns to 3ns
Updated I
Changed t
Changed t
, I
, I and I Test conditions
to 20ns, 25ns, 25ns for 15ns, 20ns, 45ns part respectively
from 15ms to 8ms
CC1 CC3 SB OZ
DELAY
STORE
Added V
, t
and t
parameters
HDIS HHHD
LZHSB
Software controlled STORE/RECALL cycle table: Changed t to t
AS
SA
Changed t
to t
parameter
GHAX
HA
Added t
DHSB
Changed t
to t
HLHX
PHSB
Updated t from 70us to 100us
SS
Added Truth table for SRAM operations
Updated ordering information
Document #: 001-45523 Rev. *B
Page 23 of 24
PRELIMINARY
CY14B108L, CY14B108N
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
PSoC Solutions
General
Clocks & Buffers
Wireless
Low Power/Low Voltage
Precision Analog
LCD Drive
Memories
Image Sensors
CAN 2.0b
USB
© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-45523 Rev. *B
Revised March 19, 2009
Page 24 of 24
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective
holders.
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