Cypress CY14B104M User Manual

PRELIMINARY

CY14B104K, CY14B104M

Table 1. Pin Definitions (continued)

Pin Name

I/O Type

Description

Output

Interrupt Output. Programmable to respond to the clock alarm, the watchdog timer, and the power

monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).

INT

Ground

Ground for the Device. Must be connected to ground of the system.

Power Supply Power Supply Inputs to the Device. 3.0V +20%, –10%

Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.

When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull

up resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation

HSB is driven HIGH for short time with standard output high current.

HSB

Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to

CAP

nonvolatile elements.

Device Operation

AutoStore Operation

The CY14B104K/CY14B104M nvSRAM is made up of two

functional components paired in the same physical cell. These

are a SRAM memory cell and a nonvolatile QuantumTrap cell.

The SRAM memory cell operates as a standard fast static RAM.

Data in the SRAM is transferred to the nonvolatile cell (the

STORE operation), or from the nonvolatile cell to the SRAM (the

RECALL operation). Using this unique architecture, all cells are

stored and recalled in parallel. During the STORE and RECALL

operations SRAM read and write operations are inhibited. The

CY14B104K/CY14B104M supports infinite reads and writes

similar to a typical SRAM. In addition, it provides infinite RECALL

operations from the nonvolatile cells and up to 200K STORE

operations. See the “Truth T a ble For SRAM Operations” on

page 23 for a complete description of read and write modes.

The CY14B104K/CY14B104M stores data to the nvSRAM using

one of three storage operations. These three operations are:

Hardware STORE, activated by the HSB; Software STORE,

activated by an address sequence; AutoStore, on device power

down. The AutoStore operation is a unique feature of

QuantumTrap technology and is enabled by default on the

CY14B104K/CY14B104M.

During normal operation, the device draws current from V to

charge a capacitor connected to the V

pin. This stored

CAP

charge is used by the chip to perform a single STORE operation.

If the voltage on the V pin drops below V , the part

SWITCH

automatically disconnects the V

pin from V . A STORE

CAP

operation is initiated with power provided by the V

capacitor.

CAP

Figure 2. AutoStore Mode

Vcc

SRAM Read

The CY14B104K/CY14B104M performs a read cycle whenever

CE and OE are LOW, and WE and HSB are HIGH. The address

0.1uF

specified on pins A

or A

determines which of the 524,288

0-18

0-17

data bytes or 262,144 words of 16 bits each are accessed. Byte

enables (BHE, BLE) determine which bytes are enabled to the

output, in the case of 16-bit words. When the read is initiated by

Vcc

an address transition, the outputs are valid after a delay of t

(read cycle 1). If the read is initiated by CE or OE, the outputs

are valid at t or at t , whichever is later (read cycle 2). The

data output repeatedly responds to address changes within the

ACE

DOE

V_CAP

access time without the need for transitions on any control

input pins. This remains valid until another address change or

until CE or OE is brought HIGH, or WE or HSB is brought LOW.

V_CAP

V_SS

SRAM Write

A write cycle is performed when CE and WE are LOW and HSB

is HIGH. The address inputs must be stable before entering the

write cycle and must remain stable until CE or WE goes HIGH at

Figure 2 shows the proper connection of the storage capacitor

(V ) for automatic STORE operation. Refer to DC Electrical

the end of the cycle. The data on the common I/O pins DO

0-15

are written into the memory if it is valid t before the end of a

CAP

Characteristics on page 14 for the size of the V

. The voltage

WE controlled write or before the end of a CE controlled write.

The Byte Enable inputs (BHE, BLE) determine which bytes are

written, in the case of 16-bit words. Keep OE HIGH during the

entire write cycle to avoid data bus contention on common I/O

lines. If OE is left LOW, internal circuitry turns off the output

CAP

on the V

pin is driven to V by a regulator on the chip. A pull

CAP

up should be placed on WE to hold it inactive during power up.

This pull up is only effective if the WE signal is tri-state during

power up. Many MPUs tri-state their controls on power up. Verify

this when using the pull up. When the nvSRAM comes out of

buffers t

after WE goes LOW.

HZWE

Document #: 001-07103 Rev. *K

Page 3 of 31

PRELIMINARY

CY14B104K, CY14B104M

power-on-recall, the MPU must be active or the WE held inactive

until the MPU comes out of reset.

To initiate the Software STORE cycle, the following read

sequence must be performed:

1. Read address 0x4E38 Valid READ

2. Read address 0xB1C7 Valid READ

3. Read address 0x83E0 Valid READ

4. Read address 0x7C1F Valid READ

5. Read address 0x703F Valid READ

6. Read address 0x8FC0 Initiate STORE cycle

To reduce unnecessary nonvolatile STOREs, AutoStore and

Hardware STORE operations are ignored unless at least one

write operation has taken place since the most recent STORE or

RECALL cycle. Software initiated STORE cycles are performed

regardless of whether a write operation has taken place. The

HSB signal is monitored by the system to detect if an AutoStore

cycle is in progress.

The software sequence may be clocked with CE or OE controlled

reads. Both CE and OE must be toggled for the sequence to be

executed. After the sixth address in the sequence is entered, the

STORE cycle starts and the chip is disabled. It is important to use

read cycles and not write cycles in the sequence. The SRAM is

Hardware STORE (HSB) Operation

The CY14B104K/CY14B104M provides the HSB pin to control

and acknowledge the STORE operations. The HSB pin is used

to request a Hardware STORE cycle. When the HSB pin is driven

LOW, the CY14B104K/CY14B104M conditionally initiates a

activated again for read and write operations after the t

STORE

cycle time.

STORE operation after t

. An actual STORE cycle begins

DELAY

only if a write to the SRAM has taken place since the last STORE

or RECALL cycle. The HSB pin also acts as an open drain driver

that is internally driven LOW to indicate a busy condition when

the STORE (initiated by any means) is in progress.

Software RECALL

Data is transferred from the nonvolatile memory to the SRAM by

a software address sequence. A software RECALL cycle is

initiated with a sequence of read operations in a manner similar

to the Software STORE initiation. To initiate the RECALL cycle,

perform the following sequence of CE or OE controlled read

operations:

SRAM read and write operations, that are in progress when HSB

is driven LOW by any means, are given time t

to complete

DELAY

before the STORE operation is initiated. However, any SRAM

write cycles requested after HSB goes LOW are inhibited until

HSB returns HIGH. In case the write latch is not set, HSB is not

driven LOW by the CY14B104K/CY14B104M but any SRAM

read and write cycles are inhibited until HSB is returned HIGH by

MPU or external source.

1. Read address 0x4E38 Valid READ

2. Read address 0xB1C7 Valid READ

3. Read address 0x83E0 Valid READ

4. Read address 0x7C1F Valid READ

5. Read address 0x703F Valid READ

6. Read address 0x4C63 Initiate RECALL cycle

During any STORE operation, regardless of how it is initiated,

the CY14B104KA/CY14B104MA continues to drive the HSB pin

LOW, releasing it only when the STORE is complete. Upon

completion

the

STORE

operation,

the

CY14B104K/CY14B104M remains disabled until the HSB pin

returns HIGH. Leave the HSB unconnected if it is not used.

Internally, RECALL is a two step procedure. First, the SRAM data

is cleared; then, the nonvolatile information is transferred into the

SRAM cells. After the t

ready for read and write operations. The RECALL operation

does not alter the data in the nonvolatile elements.

cycle time, the SRAM is again

RECALL

Hardware RECALL (Power Up)

During power up or after any low power condition

(V < V

), an internal RECALL request is latched. When

SWITCH

again exceeds the V

on powerup, a RECALL cycle

SWITCH

is automatically initiated and takes t

to complete. During

HRECALL

this time, the HSB pin is driven LOW by the HSB driver and all

reads and writes to nvSRAM are inhibited.

Software STORE

Data is transferred from the SRAM to the nonvolatile memory by

a software address sequence. The CY14B104K/CY14B104M

Software STORE cycle is initiated by executing sequential CE or

OE controlled read cycles from six specific address locations in

exact order. During the STORE cycle, an erase of the previous

nonvolatile data is first performed, followed by a program of the

nonvolatile elements. After a STORE cycle is initiated, further

input and output are disabled until the cycle is completed.

Because a sequence of reads from specific addresses is used

for STORE initiation, it is important that no other read or write

accesses intervene in the sequence, or the sequence is aborted

and no STORE or RECALL takes place.

Document #: 001-07103 Rev. *K

Page 4 of 31

PRELIMINARY

CY14B104K, CY14B104M

Table 2. Mode Selection

[6]

[3]

Mode

I/O

Power

Standby

Active

- A

OE, BHE, BLE

Not Selected

Read SRAM

Write SRAM

Output High Z

Output Data

Input Data

Active

[7]

0x4E38

0xB1C7

0x83E0

0x7C1F

0x703F

0x8B45

Read SRAM

AutoStore

Output Data

Active

Disable

[7]

0x4E38

0xB1C7

0x83E0

0x7C1F

0x703F

0x4B46

Read SRAM

AutoStore

Output Data

Active

Enable

[7]

0x4E38

0xB1C7

0x83E0

0x7C1F

0x703F

0x8FC0

Read SRAM

Nonvolatile

STORE

Output Data

Output High Z

Active I

CC2

[7]

0x4E38

0xB1C7

0x83E0

0x7C1F

0x703F

0x4C63

Read SRAM

Nonvolatile

RECALL

Output Data

Output High Z

Active

manner similar to the software RECALL initiation. To initiate the

AutoStore enable sequence, the following sequence of CE or OE

controlled read operations must be performed:

Preventing AutoStore

The AutoStore function is disabled by initiating an AutoStore

disable sequence. A sequence of read operations is performed

in a manner similar to the Software STORE initiation. To initiate

the AutoStore disable sequence, the following sequence of CE

or OE controlled read operations must be performed:

1. Read address 0x4E38 Valid READ

2. Read address 0xB1C7 Valid READ

3. Read address 0x83E0 Valid READ

4. Read address 0x7C1F Valid READ

5. Read address 0x703F Valid READ

6. Read address 0x4B46 AutoStore Enable

1. Read address 0x4E38 Valid READ

2. Read address 0xB1C7 Valid READ

3. Read address 0x83E0 Valid READ

4. Read address 0x7C1F Valid READ

5. Read address 0x703F Valid READ

6. Read address 0x8B45 AutoStore Disable

If the AutoStore function is disabled or re-enabled, a manual

STORE operation (hardware or software) issued to save the

AutoStore state through subsequent power down cycles. The

part comes from the factory with AutoStore enabled.

AutoStore is re-enabled by initiating an AutoStore enable

sequence. A sequence of read operations is performed in a

Notes

6. While there are 19 address lines on the CY14B104K (18 address lines on the CY14B104M), only the 13 address lines (A - A ) are used to control software modes.

Rest of the address lines are don’t care.

7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.

Document #: 001-07103 Rev. *K

Page 5 of 31

PRELIMINARY

CY14B104K, CY14B104M

Setting the Clock

Data Protection

Setting the write bit ‘W’ (in the flags register at 0x7FFF0) to a ‘1’

stops updates to the time keeping registers and enables the time

to be set. The correct day, date, and time is then written into the

registers and must be in 24 hour BCD format. The time written is

referred to as the “Base Time”. This value is stored in nonvolatile

registers and used in the calculation of the current time.

Resetting the write bit to ‘0’ transfers the values of timekeeping

registers to the actual clock counters, after which the clock

resumes normal operation.

The CY14B104K/CY14B104M protects data from corruption

during low voltage conditions by inhibiting all externally initiated

STORE and write operations. The low voltage condition is

detected when

is less than

If the

SWITCH

CY14B104K/CY14B104M is in a write mode (both CE and WE

are LOW) at power up, after a RECALL or STORE, the write is

inhibited until the SRAM is enabled after t

(HSB to output

LZHSB

active). This protects against inadvertent writes during power up

or brown out conditions.

If the time written to the timekeeping registers is not in the correct

BCD format, each invalid nibble of the RTC registers continue

counting to 0xF before rolling over to 0x0 after which RTC

resumes normal operation.

Noise Considerations

Refer to CY application note AN1064.

Real Time Clock Operation

nvTIME Operation

Note The values entered in the timekeeping, alarm, calibration,

and interrupt registers need a STORE operation to be saved in

nonvolatile memory. Therefore, while working in AutoStore

disabled mode, the user must perform a STORE operation after

writing into the RTC registers for the RTC to work correctly.

The CY14B104K/CY14B104M offers internal registers that

contain clock, alarm, watchdog, interrupt, and control functions.

RTC registers use the last 16 address locations of the SRAM.

Internal double buffering of the clock and timer information

registers prevents accessing transitional internal clock data

during a read or write operation. Double buffering also

circumvents disrupting normal timing counts or the clock

accuracy of the internal clock when accessing clock data. Clock

and alarm registers store data in BCD format.

Backup Power

The RTC in the CY14B104K is intended for permanently

powered operation. The V

or V

pin is connected

RTCcap

RTCbat

depending on whether a capacitor or battery is chosen for the

application. When the primary power, V , fails and drops below

the device switches to the backup power supply.

SWITCH

The clock oscillator uses very little current, which maximizes the

backup time available from the backup source. Regardless of the

clock operation with the primary source removed, the data stored

in the nvSRAM is secure, having been stored in the nonvolatile

elements when power was lost.

RTC functionality is described with respect to CY14B104K in the

following sections. The same description applies to

CY14B104M, except for the RTC register addresses. The RTC

0x7FFFF, while those for CY14B104M range from 0x3FFF0 to

0x3FFFF. Refer to T a ble 4 on page 10 and T a ble 5 on page 11

for a detailed Register Map description.

During backup operation, the CY14B104K consumes

maximum of 300 nanoamps at room temperature. User must

choose capacitor or battery values according to the application.

Clock Operations

Backup time values based on maximum current specifications

are shown in the following table. Nominal backup times are

approximately two times longer.

The clock registers maintain time up to 9,999 years in one

second increments. The time can be set to any calendar time and

the clock automatically keeps track of days of the week and

month, leap years, and century transitions. There are eight

registers dedicated to the clock functions, which are used to set

time with a write cycle and to read time during a read cycle.

These registers contain the time of day in BCD format. Bits

defined as ‘0’ are currently not used and are reserved for future

use by Cypress.

Table 3. RTC Backup Time

Capacitor Value

Backup Time

72 hours

14 days

0.1F

0.47F

1.0F

30 days

Reading the Clock

Using a capacitor has the obvious advantage of recharging the

backup source each time the system is powered up. If a battery

is used, a 3V lithium is recommended and the CY14B104K

sources current only from the battery when the primary power is

removed. However the battery is not recharged at any time by

the CY14B104K. The battery capacity must be chosen for total

anticipated cumulative down time required over the life of the

system.

The double buffered RTC register structure reduces the chance

of reading incorrect data from the clock. The user must stop

internal updates to the CY14B104K time keeping registers

before reading clock data, to prevent reading of data in transition.

Stopping the register updates does not affect clock accuracy.

The updating process is stopped by writing a ‘1’ to the read bit

‘R’ (in the flags register at 0x7FFF0), and does not restart until a

‘0’ is written to the read bit. The RTC registers are then read while

the internal clock continues to run. After a ‘0’ is written to the read

bit (‘R’), all RTC registers are simultaneously updated within

20 ms

Stopping and Starting the Oscillator

The OSCEN bit in the calibration register at 0x7FFF8 controls

the enable and disable of the oscillator. This bit is nonvolatile and

is shipped to customers in the “enabled” (set to 0) state. To

preserve the battery life when the system is in storage, OSCEN

Document #: 001-07103 Rev. *K

Page 6 of 31

PRELIMINARY

CY14B104K, CY14B104M

must be set to ‘1’. This turns off the oscillator circuit, extending

the battery life. If the OSCEN bit goes from disabled to enabled,

it takes approximately one second (two seconds maximum) for

the oscillator to start.

toggle at a nominal frequency of 512 Hz. Any deviation

measured from the 512 Hz indicates the degree and direction of

the required correction. For example, a reading of 512.01024 Hz

indicates a +20 ppm error. Hence, a decimal value of –10

(001010b) must be loaded into the Calibration register to offset

this error.

While system power is off, If the voltage on the backup supply

or V

) falls below their respective minimum level,

RTCcap

RTCbat

the oscillator may fail.The CY14B104K has the ability to detect

oscillator failure when system power is restored. This is recorded

in the OSCF (Oscillator Failed bit) of the flags register at the

Note Setting or changing the Calibration register does not affect

the test output frequency.

To set or clear CAL, set the write bit “W” (in the flags register at

0x7FFF0) to “1” to enable writes to the Flag register. Write a

value to CAL, and then reset the write bit to “0” to disable writes.

address 0x7FFF0. When the device is powered on (V

goes

above V

) the OSCEN bit is checked for “enabled” status.

SWITCH

If the OSCEN bit is enabled and the oscillator is not active within

the first 5 ms, the OSCF bit is set to “1”. The system must check

for this condition and then write ‘0’ to clear the flag. Note that in

addition to setting the OSCF flag bit, the time registers are reset

to the “Base Time” (see Setting the Clock on page 6), which is

the value last written to the timekeeping registers. The control or

calibration registers and the OSCEN bit are not affected by the

‘oscillator failed’ condition.

Alarm

The alarm function compares user programmed values of alarm

time and date (stored in the registers 0x7FFF1-5) with the corre-

sponding time of day and date values. When a match occurs, the

alarm internal flag (AF) is set and an interrupt is generated on

INT pin if Alarm Interrupt Enable (AIE) bit is set.

There are four alarm match fields - date, hours, minutes, and

seconds. Each of these fields has a match bit that is used to

determine if the field is used in the alarm match logic. Setting the

match bit to ‘0’ indicates that the corresponding field is used in

the match process. Depending on the match bits, the alarm

occurs as specifically as once a month or as frequently as once

every minute. Selecting none of the match bits (all 1s) indicates

that no match is required and therefore, alarm is disabled.

Selecting all match bits (all 0s) causes an exact time and date

match.

The value of OSCF must be reset to ‘0’ when the time registers

are written for the first time. This initializes the state of this bit

which may have become set when the system was first powered

on.

To reset OSCF, set the write bit “W” (in the Flags register at

0x7FFF0) to a “1” to enable writes to the Flag register. Write a

“0” to the OSCF bit and then reset the write bit to “0” to disable

writes.

Calibrating the Clock

There are two ways to detect an alarm event: by reading the AF

flag or monitoring the INT pin. The AF flag in the flags register at

0x7FFF0 indicates that a date or time match has occurred. The

AF bit is set to “1” when a match occurs. Reading the flags

interrupt pin may also be used to detect an alarm event.

The RTC is driven by a quartz controlled crystal with a nominal

frequency of 32.768 kHz. Clock accuracy depends on the quality

of the crystal and calibration. The crystals available in market

typically have an error of +20 ppm to +35 ppm. However,

CY14B104K employs a calibration circuit that improves the

accuracy to +1/–2 ppm at 25°C. This implies an error of +2.5

seconds to -5 seconds per month.

To set, clear or enable an alarm, set the ‘W’ bit (in Flags Register

- 0x7FFF0) to ‘1’ to enable writes to Alarm Registers. After writing

the alarm value, clear the ‘W’ bit back to “0” for the changes to

take effect.

The calibration circuit adds or subtracts counts from the oscillator

divider circuit to achieve this accuracy. The number of pulses that

are suppressed (subtracted, negative calibration) or split (added,

positive calibration) depends upon the value loaded into the five

calibration bits found in Calibration register at 0x7FFF8. The

calibration bits occupy the five lower order bits in the Calibration

and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates

positive calibration and a ‘0’ indicates negative calibration.

Adding counts speeds the clock up and subtracting counts slows

the clock down. If a binary ‘1’ is loaded into the register, it corre-

sponds to an adjustment of 4.068 or –2.034 ppm offset in oscil-

lator error, depending on the sign.

Note CY14B104K requires the alarm match bit for seconds

(0x7FFF2 - D7) to be set to ‘0’ for proper operation of Alarm Flag

and Interrupt.

Watchdog Timer

The Watchdog Timer is a free running down counter that uses

the 32 Hz clock (31.25 ms) derived from the crystal oscillator.

The oscillator must be running for the watchdog to function. It

begins counting down from the value loaded in the Watchdog

Timer register.

The timer consists of a loadable register and a free running

counter. On power up, the watchdog time out value in register

0x7FFF7 is loaded into the Counter Load register. Counting

begins on power up and restarts from the loadable value any time

the Watchdog Strobe (WDS) bit is set to ‘1’. The counter is

compared to the terminal value of ‘0’. If the counter reaches this

value, it causes an internal flag and an optional interrupt output.

You can prevent the time out interrupt by setting WDS bit to ‘1’

prior to the counter reaching ‘0’. This causes the counter to

reload with the watchdog time out value and to be restarted. As

long as the user sets the WDS bit prior to the counter reaching

the terminal value, the interrupt and WDT flag never occur.

Calibration occurs within a 64-minute cycle. The first 62 minutes

in the cycle may, once per minute, have one second shortened

by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is

loaded into the register, only the first two minutes of the

64-minute cycle are modified. If a binary 6 is loaded, the first 12

are affected, and so on. Therefore, each calibration step has the

effect of adding 512 or subtracting 256 oscillator cycles for every

125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm

of adjustment per calibration step in the Calibration register.

To determine the required calibration, the CAL bit in the Flags

Document #: 001-07103 Rev. *K

Page 7 of 31

“AutoStore/Power Up RECALL” on page 20)

PRELIMINARY

CY14B104K, CY14B104M

New time out values are written by setting the watchdog write bit

to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out

value bits D5-D0 are enabled to modify the time out value. When

WDW is ‘1’, writes to bits D5-D0 are ignored. The WDW function

enables a user to set the WDS bit without concern that the

watchdog timer value is modified. A logical diagram of the

watchdog timer is shown in Figure 3. Note that setting the

watchdog time out value to ‘0’ disables the watchdog function.

determine the cause of the interrupt. The INT pin driver has two

bits that specify its behavior when an interrupt occurs.

An Interrupt is raised only if both a flag is raised by one of the

three sources and the respective interrupt enable bit in Interrupts

two programmable bits, H/L and P/L, determine the behavior of

the output pin driver on INT pin. These two bits are located in the

Interrupt register and can be used to drive level or pulse mode

output from the INT pin. In pulse mode, the pulse width is

internally fixed at approximately 200 ms. This mode is intended

to reset a host microcontroller. In the level mode, the pin goes to

its active polarity until the Flags register is read by the user. This

mode is used as an interrupt to a host microcontroller. The

control bits are summarized in the following section.

The output of the watchdog timer is the flag bit WDF that is set if

the watchdog is allowed to time out. If the Watchdog Interrupt

Enable (WIE) bit in the Interrupt register is set, a hardware

interrupt on INT pin is also generated on watchdog timeout. The

flag and the hardware interrupt are both cleared when user reads

the Flags registers.

Figure 3. Watchdog Timer Block Diagram

Interrupts are only generated while working on normal power and

are not triggered when system is running in backup power mode.

Clock

Oscillator

1 Hz

Divider

Note CY14B104K generates valid interrupts only after the

32,768 KHz

Powerup Recall sequence is completed. All events on INT pin

32 Hz

must be ignored for t

duration after powerup.

HRECALL

Zero

Compare

WDF

Counter

Interrupt Register

Watchdog Interrupt Enable - WIE. When set to ‘1’, the

watchdog timer drives the INT pin and an internal flag when a

watchdog time out occurs. When WIE is set to ‘0’, the watchdog

timer only affects the WDF flag in Flags register.

Load

WDS

Alarm Interrupt Enable - AIE. When set to ‘1’, the alarm match

drives the INT pin and an internal flag. When AIE is set to ‘0’, the

alarm match only affects the AF Flags register.

WDW

Power Fail Interrupt Enable - PFE. When set to ‘1’, the power

fail monitor drives the pin and an internal flag. When PFE is set

to ‘0’, the power fail monitor only affects the PF flag in Flags

Watchdog

write to

Watchdog

Power Monitor

High/Low - H/L. When set to a ‘1’, the INT pin is active HIGH

The CY14B104K provides a power management scheme with

power fail interrupt capability. It also controls the internal switch

to backup power for the clock and protects the memory from low

and the driver mode is push pull. The INT pin drives high only

when V is greater than V

. When set to a ‘0’, the INT pin

SWITCH

is active LOW and the drive mode is open drain. The INT pin

must be pulled up to Vcc by a 10k resistor while using the

interrupt in active LOW mode.

Pulse/Level - P/L. When set to a ‘1’ and an interrupt occurs, the

INT pin is driven for approximately 200 ms. When P/L is set to a

‘0’, the INT pin is driven high or low (determined by H/L) until the

Flags or Control register is read.

access. The power monitor is based on an internal band gap

reference circuit that compares the V

voltage to V

SWITCH

threshold.

As described in the section “AutoStore Operation” on page 3,

when V is reached as V decays from power loss, a data

SWITCH

STORE operation is initiated from SRAM to the nonvolatile

elements, securing the last SRAM data state. Power is also

When an enabled interrupt source activates the INT pin, an

external host reads the Flags registers to determine the cause.

Remember that all flags are cleared when the register is read. If

the INT pin is programmed for Level mode, then the condition

clears and the INT pin returns to its inactive state. If the pin is

programmed for Pulse mode, then reading the flag also clears

the flag and the pin. The pulse does not complete its specified

duration if the Flags register is read. If the INT pin is used as a

host reset, the Flags register is not read during a reset

switched from V to the backup supply (battery or capacitor) to

operate the RTC oscillator.

When operating from the backup source, read and write opera-

tions to nvSRAM are inhibited and the clock functions are not

available to the user. The clock continues to operate in the

background. The updated clock data is available to the user

delay after V

is restored to the device (see

HRECALL

Flags Register

Interrupts

The Flag register has three flag bits: WDF, AF, and PF, which can

be used to generate an interrupt. They are set by the watchdog

timeout, alarm match, or power fail monitor respectively. The

processor can either poll this register or enable interrupts when

a flag is set. These flags are automatically reset once the register

is read. The flags register is automatically loaded with the value

0x00 on power up (except for the OSCF bit. See “Stopping and

Starting the Oscillator” on page 6.)

The CY14B104K has Flags register, Interrupt register, and

Interrupt logic that can signal interrupt to the microcontroller.

There are three potential sources for interrupt: watchdog timer,

power monitor, and alarm timer. Each of these can be individually

enabled to drive the INT pin by appropriate setting in the Interrupt

in the Flags register (0x7FFF0) that the host processor uses to

Document #: 001-07103 Rev. *K

Page 8 of 31

PRELIMINARY

CY14B104K, CY14B104M

Figure 4. RTC Recommended Component Configuration

Recommended Values

= 32.768 KHz (6 pF)

C₁= 21 pF

C₂= 21 pF

Note: The recommended values for C1 and C2 include

board trace capacitance.

Figure 5. Interrupt Block Diagram

WDF

Watchdog

Timer

WDF - Watchdog Timer Flag

WIE - Watchdog Interrupt

Enable

WIE

P/L

PF - Power Fail Flag

PFE - Power Fail Enable

Power

Monitor

INT

AF - Alarm Flag

AIE - Alarm Interrupt Enable

PFE

Driver

VINT

P/L - Pulse Level

H/L - High/Low

H/L

Clock

Alarm

AIE

Document #: 001-07103 Rev. *K

Page 9 of 31

PRELIMINARY

CY14B104K, CY14B104M

[8]

Table 4. RTC Register Map

[9]

BCD Format Data

Function/Range

CY14B104K CY14B104M

Years

Months

0x7FFFF

0x7FFFE

0x3FFFF

0x3FFFE

10s Years

Years: 00–99

10s

Months: 01–12

Months

0x7FFFD

0x7FFFC

0x7FFFB

0x7FFFA

0x7FFF9

0x7FFF8

0x3FFFD

0x3FFFC

0x3FFFB

0x3FFFA

0x3FFF9

0x3FFF8

10s Day of Month

Day Of Month

Day of week

Day of Month: 01–31

Day of week: 01–07

Hours: 00–23

10s Hours

10s Minutes

Hours

Minutes

Seconds

Minutes: 00–59

10s Seconds

Seconds: 00–59

OSCEN

(0)

CalSign

(0)

Calibration (00000)

Calibration Values

0x7FFF7

0x7FFF6

0x7FFF5

0x3FFF7

0x3FFF6

0x3FFF5

WDS

(0)

WDW (0)

WDT (000000)

Watchdog

WIE (0) AIE (0)

PFE (0)

H/L

(1)

P/L (0)

Interrupts

M (1)

10s Alarm Date

10s Alarm Hours

Alarm Day

Alarm, Day of Month:

01–31

0x7FFF4

0x7FFF3

0x3FFF4

0x3FFF3

M (1)

Alarm Hours

Alarm, Hours: 00–23

10 Alarm Minutes

Alarm Minutes

Alarm, Minutes:

00–59

0x7FFF2

0x3FFF2

M (1)

10 Alarm Seconds

Alarm, Seconds

Alarm, Seconds:

00–59

0x7FFF1

0x7FFF0

0x3FFF1

0x3FFF0

10s Centuries

AF PF

Centuries

Centuries: 00–99

WDF

OSCF

CAL (0) W (0) R (0)

Flags

Note

8. Upper Byte D -D (CY14B104MA) of RTC registers are reserved for future use

9. ( ) designates values shipped from the factory.

10. This is a binary value, not a BCD value.

Document #: 001-07103 Rev. *K

Page 10 of 31

PRELIMINARY

CY14B104K, CY14B104M

Table 5. Register Map Detail

Description

CY14B104K

CY14B104M

Time Keeping - Years

D4 D3

0x7FFFF

0x3FFFF

10s Years

Years

Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years;

upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The

range for the register is 0–99.

Time Keeping - Months

0x7FFFE

0x3FFFE

10s Month

Months

Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates

from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range

for the register is 1–12.

Time Keeping - Date

0x7FFFD

0x7FFFC

0x7FFFB

0x7FFFA

0x7FFF9

0x3FFFD

0x3FFFC

0x3FFFB

0x3FFFA

0x3FFF9

10s Day of Month

Day of Month

Contains the BCD digits for the date of the month. Lower nibble (four bits) contains the lower digit

and operates from 0 to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3.

The range for the register is 1–31. Leap years are automatically adjusted for.

Time Keeping - Day

Day of Week

Lower nibble (three bits) contains a value that correlates to day of the week. Day of the week is a

ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day

value, because the day is not integrated with the date.

Time Keeping - Hours

10s Hours

Hours

Contains the BCD value of hours in 24 hour format. Lower nibble (four bits) contains the lower

digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from

0 to 2. The range for the register is 0–23.

Time Keeping - Minutes

Minutes

10s Minutes

Contains the BCD value of minutes. Lower nibble (four bits) contains the lower digit and operates

from 0 to 9; upper nibble (three bits) contains the upper minutes digit and operates from 0 to 5.

The range for the register is 0–59.

Time Keeping - Seconds

Seconds

10s Seconds

Contains the BCD value of seconds. Lower nibble (four bits) contains the lower digit and operates

from 0 to 9; upper nibble (three bits) contains the upper digit and operates from 0 to 5. The range

for the register is 0–59.

Document #: 001-07103 Rev. *K

Page 11 of 31

PRELIMINARY

CY14B104K, CY14B104M

Table 5. Register Map Detail (continued)

Description

CY14B104K

CY14B104M

Calibration/Control

D4 D3

0x7FFF8

0x3FFF8

OSCEN

Calibration

Sign

Calibration

OSCEN

Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs.

Disabling the oscillator saves battery or capacitor power during storage.

Calibration

Sign

Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from

the time-base.

Calibration

These five bits control the calibration of the clock.

WatchDog Timer

0x7FFF7

0x3FFF7

WDS

WDW

WDT

WDS

Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to

0 has no effect. The bit is cleared automatically after the watchdog timer is reset. The WDS bit is

write only. Reading it always returns a 0.

WDW

Watchdog Write Enable. Setting this bit to 1 disables any WRITE to the watchdog timeout value

(D5–D0). This allows the user to set the watchdog strobe bit without disturbing the timeout value.

Setting this bit to 0 allows bits D5–D0 to be written to the watchdog register when the next write

cycle is complete. This function is explained in more detail in Watchdog Timer on page 7.

WDT

Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this

31.25 ms (a setting of 1) to 2 seconds (setting of 3 Fh). Setting the watchdog timer register to 0

disables the timer. These bits can be written only if the WDW bit was set to 0 on a previous cycle.

Interrupt Status/Control

0x7FFF6

0x3FFF6

WIE

AIE

PFE

H/L

P/L

WIE

Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer

drives the INT pin and the WDF flag. When set to 0, the watchdog timeout affects only the WDF

flag.

AIE

Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin and the AF flag. When

set to 0, the alarm match only affects the AF flag.

PFE

Power Fail Enable. When set to 1, the power fail monitor drives the INT pin and the PF flag. When

set to 0, the power fail monitor affects only the PF flag.

Reserved for future use

H/L

High/Low. When set to 1, the INT pin is driven active HIGH. When set to 0, the INT pin is open

drain, active LOW.

P/L

Pulse/Level. When set to 1, the INT pin is driven active (determined by H/L) by an interrupt source

for approximately 200 ms. When set to 0, the INT pin is driven to an active level (as set by H/L)

until the flags register is read.

Alarm - Day

0x7FFF5

0x3FFF5

10s Alarm Date

Alarm Date

Contains the alarm value for the date of the month and the mask bit to select or deselect the date

value.

Match. When this bit is set to 0, the date value is used in the alarm match. Setting this bit to 1

causes the match circuit to ignore the date value.

Document #: 001-07103 Rev. *K

Page 12 of 31

PRELIMINARY

CY14B104K, CY14B104M

Table 5. Register Map Detail (continued)

Description

CY14B104K

CY14B104M

Alarm - Hours

D4 D3

0x7FFF4

0x3FFF4

10s Alarm Hours

Alarm Hours

Contains the alarm value for the hours and the mask bit to select or deselect the hours value.

Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1

causes the match circuit to ignore the hours value.

Alarm - Minutes

0x7FFF3

0x7FFF2

0x3FFF3

0x3FFF2

10s Alarm Minutes

Alarm Minutes

Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.

Match. When this bit is set to 0, the minutes value is used in the alarm match. Setting this bit to 1

causes the match circuit to ignore the minutes value.

Alarm - Seconds

10s Alarm Seconds

Alarm Seconds

Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.

Match. When this bit is set to 0, the seconds value is used in the alarm match. Setting this bit to

1 causes the match circuit to ignore the seconds value.

Time Keeping - Centuries

0x7FFF1

0x7FFF0

0x3FFF1

0x3FFF0

Centuries

10s Centuries

Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0

to 9; upper nibble contains the upper digit and operates from 0 to 9. The range for the register is

0-99 centuries.

Flags

WDF

OSCF

CAL

WDF

Watchdog Timer Flag. This read only bit is set to 1 when the watchdog timer is allowed to reach

0 without being reset by the user. It is cleared to 0 when the Flags register is read or on power up

Alarm Flag. This read only bit is set to 1 when the time and date match the values stored in the

alarm registers with the match bits = 0. It is cleared when the Flags register is read or on power up.

Power Fail Flag. This read only bit is set to 1 when power falls below the power fail threshold

. It is cleared to 0 when the Flags register is read or on power up.

SWITCH

OSCF

Oscillator Fail Flag. Set to 1 on power up if the oscillator is enabled and not running in the first 5

ms of operation. This indicates that RTC backup power failed and clock value is no longer valid.

This bit survives power cycle and is never cleared internally by the chip. The user must check for

this condition and write '0' to clear this flag.

CAL

Calibration Mode. When set to 1, a 512 Hz square wave is output on the INT pin. When set to 0,

the INT pin resumes normal operation. This bit defaults to 0 (disabled) on power up.

Write Enable: Setting the W bit to 1 freezes updates of the RTC registers. The user can then write

to RTC registers, Alarm registers, Calibration register, Interrupt register and Flags register. Setting

the W bit to 0 causes the contents of the RTC registers to be transferred to the time keeping

counters if the time has been changed (a new base time is loaded). This bit defaults to 0 on power

up.

Read Enable: Setting R bit to 1, stops clock updates to user RTC registers so that clock updates

are not seen during the reading process. Set R bit to 0 to resume clock updates to the holding

Document #: 001-07103 Rev. *K

Page 13 of 31

PRELIMINARY

CY14B104K, CY14B104M

Transient Voltage (<20 ns) on

Any Pin to Ground Potential .................. –2.0V to V + 2.0V

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Package Power Dissipation

Capability (T = 25°C) ................................................... 1.0W

Storage Temperature ................................. –65°C to +150°C

Maximum Accumulated Storage Time

Surface Mount Pb Soldering

Temperature (3 Seconds).......................................... +260°C

DC Output Current (1 output at a time, 1s duration).....15 mA

At 150°C Ambient Temperature................................... 1000h

At 85°C Ambient Temperature..................... ........... 20 Years

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Ambient Temperature with

Power Applied ............................................ –55°C to +150°C

Latch Up Current ................................................... > 200 mA

Supply Voltage on V Relative to GND ..........–0.5V to 4.1V

Operating Range

Voltage Applied to Outputs

in High-Z State.......................................–0.5V to V + 0.5V

Range

Commercial

Industrial

Ambient Temperature

0°C to +70°C

Input Voltage...........................................–0.5V to Vcc + 0.5V

2.7V to 3.6V

–40°C to +85°C

DC Electrical Characteristics

Over the Operating Range (V = 2.7V to 3.6V)

Parameter

Description

Average V Current

Test Conditions

Min

Max

Unit

= 20 ns

= 25 ns

= 45 ns

Commercial

CC1

Values obtained without output loads (I

= 0 mA)

Industrial

OUT

Average V Current All Inputs Don’t Care, V = Max.

CC2

during STORE

Average current for duration t

STORE

[11]

Average V Current All I/P cycling at CMOS levels.

CC3

at t = 200 ns, 3V,

Values obtained without output loads (I

= 0 mA).

OUT

25°C typical

AverageV

during AutoStore

Cycle

Current All Inputs Don’t Care, V = Max.

CC4

CAP

Average current for duration t

STORE

Standby Current CE > (V – 0.2V). All others V < 0.2V or > (V – 0.2V). Standby

CC IN CC

current level after nonvolatile cycle is complete.

Inputs are static. f = 0 MHz.

[12]

InputLeakageCurrent V = Max, V < V < V

(except HSB)

–1

–100

–1

μA

InputLeakageCurrent V = Max, V < V < V

(for HSB)

Off State Output

Leakage Current

= Max, V < V

< V , CE or OE > V or BHE/BLE > V

OUT

or WE < V

Input HIGH Voltage

Input LOW Voltage

2.0

+ 0.5

– 0.5

0.8

Output HIGH Voltage I

= –2 mA

= 4 mA

2.4

OUT

Output LOW Voltage

Storage Capacitor

0.4

OUT

[13]

Between V

pin and V , 5V Rated

180

μF

CAP

Notes

11. Typical conditions for the active current shown on the DC Electrical characteristics are average values at 25°C (room temperature), and V = 3V. Not 100% tested.

12. The HSB pin has I

= -2 uA for V of 2.4V when both active HIGH and LOW drivers are disabled. When they are enabled standard V and V are valid. This

OUT

parameter is characterized but not tested.

13. V (Storage capacitor) nominal value is 68uF.

CAP

Document #: 001-07103 Rev. *K

Page 14 of 31

PRELIMINARY

CY14B104K, CY14B104M

Data Retention and Endurance

Parameter

Description

Min

Unit

Years

DATA

Data Retention

Nonvolatile STORE Operations

200

Capacitance

In the following table, the capacitance parameters are listed.

Parameter Description

Input Capacitance

Output Capacitance

Test Conditions

T = 25°C, f = 1 MHz,

Max

Unit

= 0 to 3.0V

OUT

Thermal Resistance

In the following table, the thermal resistance parameters are listed.

Parameter

Description

Test Conditions

44 TSOP II 54 TSOP II Unit

Θ_JA

Thermal Resistance

(Junction to Ambient)

Testconditionsfollowstandard

test methods and procedures

for measuring thermal

impedance, in accordance

with EIA/JESD51.

31.11

30.73

°C/W

Θ_JC

Thermal Resistance

(Junction to Case)

5.56

6.08

°C/W

Figure 6. AC Test Loads

577Ω

3.0V

OUTPUT

3.0V

OUTPUT

789Ω

5 pF

30 pF

AC Test Conditions

Input Pulse Levels ....................................................0V to 3V

Input Rise and Fall Times (10% - 90%)........................ <3 ns

Input and Output Timing Reference Levels .................... 1.5V

Note

14. These parameters are only guaranteed by design and are not tested.

Document #: 001-07103 Rev. *K

Page 15 of 31

PRELIMINARY

CY14B104K, CY14B104M

Table 6. RTC Characteristics

Parameters

Description

RTC Backup Current

Test Conditions

Min

Typ

Max Units

[15]

Room Temperature (25 C)

300

450

3.3

3.6

BAK

Hot Temperature (85 C)

RTC Battery Pin Voltage

RTC Capacitor Pin Voltage

RTC Oscillator Time to Start

1.8

1.5

3.0

RTCbat

RTCcap

tOCS

sec

Notes

15. From either V

or V

RTCbat.

RTCcap

Document #: 001-07103 Rev. *K

Page 16 of 31

PRELIMINARY

CY14B104K, CY14B104M

AC Switching Characteristics

Parameters

20 ns

25 ns

45 ns

Description

Unit

Cypress

Parameters

Alt

Min

Max

Min

Max

Min

Max

Parameters

SRAM Read Cycle

Chip Enable Access Time

ACE

ACS

[16]

Read Cycle Time

[17]

Address Access Time

Output Enable to Data Valid

Output Hold After Address Change

Chip Enable to Output Active

Chip Disable to Output Inactive

Output Enable to Output Active

Output Disable to Output Inactive

Chip Enable to Power Active

Chip Disable to Power Standby

Byte Enable to Data Valid

DOE

OHA

[17]

[14, 18]

LZCE

HZCE

LZOE

HZOE

OLZ

OHZ

DBE

[14]

Byte Enable to Output Active

Byte Disable to Output Inactive

LZBE

HZBE

SRAM Write Cycle

Write Cycle Time

Write Pulse Width

PWE

SCE

Chip Enable To End of Write

Data Setup to End of Write

Data Hold After End of Write

Address Setup to End of Write

Address Setup to Start of Write

Address Hold After End of Write

Write Enable to Output Disable

Output Active after End of Write

Byte Enable to End of Write

[14, 18,19]

[14, 18]

HZWE

LZWE

Switching Waveforms

[16, 17, 20]

Figure 7. SRAM Read Cycle 1: Address Controlled

t_RC

Address

Address Valid

t_AA

Output Data Valid

Previous Data Valid

t_OHA

Data Output

Notes

16. WE must be HIGH during SRAM read cycles.

17. Device is continuously selected with CE, OE and BHE / BLE LOW.

18. Measured ±200 mV from steady state output voltage.

19. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.

20. HSB must remain HIGH during READ and WRITE cycles.

Document #: 001-07103 Rev. *K

Page 17 of 31

PRELIMINARY

CY14B104K, CY14B104M

Switching Waveforms

[3 , 16 , 20]

Figure 8. SRAM Read Cycle 2: CE Controlled

Address

Address Valid

t_RC

t_HZCE

t_ACE

t_AA

t_LZCE

t_HZOE

t_DOE

t_HZBE

t_LZOE

t_DBE

BHE, BLE

t_LZBE

High Impedance

Data Output

Output Data Valid

t_PD

t_PU

Active

I_CC

Standby

[3, 19, 20, 21]

Figure 9. SRAM Write Cycle 1: WE Controlled

t_WC

Address

Address Valid

t_SCE

t_HA

t_BW

BHE, BLE

t_AW

t_PWE

Data Input

Data Output

t_SA

t_HD

t_SD

Input Data Valid

t_LZWE

t_HZWE

High Impedance

Previous Data

Notes

21. CE or WE must be >V during address transitions.

Document #: 001-07103 Rev. *K

Page 18 of 31

PRELIMINARY

CY14B104K, CY14B104M

Switching Waveforms

[3, 19, 20, 21]

Figure 10. SRAM Write Cycle 2: CE Controlled

t_WC

Address Valid

Address

t_SA

t_SCE

t_HA

t_BW

BHE, BLE

t_PWE

t_HD

t_SD

Input Data Valid

Data Input

High Impedance

Data Output

[6, 19, 20, 21, 22]

Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled

(Not applicable for RTC register writes)

t_WC

Address

Address Valid

t_SCE

t_SA

t_HA

t_BW

BHE, BLE

t_AW

t_PWE

t_SD

t_HD

Data Input

Input Data Valid

High Impedance

Data Output

Note

22. Only CE and WE controlled writes to RTC registers are allowed. BLE pin must be held LOW before CE or WE pin goes LOW for writes to RTC register.

Document #: 001-07103 Rev. *K

Page 19 of 31

PRELIMINARY

CY14B104K, CY14B104M

AutoStore/Power Up RECALL

20 ns

25 ns

45 ns

Parameters

Description

Unit

Min

Max

Min

Max

Min

Max

[23]

Power Up RECALL Duration

STORE Cycle Duration

HRECALL

[24]

STORE

DELAY

[25]

Time Allowed to Complete SRAM Cycle

Low Voltage Trigger Level

VCC Rise Time

2.65

SWITCH

150

μs

VCCRISE

HSB Output Driver Disable Voltage

HSB To Output Active Time

HSB High Active Time

1.9

HDIS

LZHSB

HHHD

μs

500

Switching Waveforms

[26]

Figure 12. AutoStore or Power Up RECALL

V_SWITCH

V_HDIS

Note²⁴

V_VCCRISE

t_STORE

Note²⁷

t_HHHD

HSB OUT

Autostore

t_DELAY

t_LZHSB

t_DELAY

POWER-

RECALL

t_HRECALL

Read & Write

Inhibited

(RWI)

Read & Write

POWER-UP

RECALL

BROWN

OUT

Autostore

POWER

DOWN

Autostore

POWER-UP

RECALL

Notes

23. t

starts from the time V rises above V

SWITCH.

HRECALL

24. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.

25. On a Hardware STORE, Software STORE / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time t

DELAY

26. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V

SWITCH.

27. HSB pin is driven HIGH to VCC only by internal 100kOhm resistor, HSB driver is disabled.

Document #: 001-07103 Rev. *K

Page 20 of 31

PRELIMINARY

CY14B104K, CY14B104M

Software Controlled STORE and RECALL Cycle

In the following table, the software controlled STORE and RECALL cycle parameters are listed.

[28, 29]

20 ns

25 ns

45 ns

Parameters

Description

Unit

Min

Max

Min

Max

Min

Max

STORE/RECALL Initiation Cycle Time

Address Setup Time

μs

Clock Pulse Width

Address Hold Time

RECALL Duration

200

100

200

100

200

100

RECALL

[32, 33]

Soft Sequence Processing Time

Switching Waveforms

[29]

Figure 13. CE and OE Controlled Software STORE and RECALL Cycle

t_RC

Address

Address #1

t_CW

Address #6

t_CW

t_SA

t_HA

t_SA

t_HA

t_DELAY

t_HHHD

t_HZCE

HSB (STORE only)

DQ (DATA)

t_LZCE

t_LZHSB

High Impedance

t_STORE/t_RECALL

RWI

Figure 14. Autostore Enable and Disable Cycle

t_RC

Address

Address #1

t_CW

Address #6

t_CW

t_SA

t_HA

t_SS

t_HZCE

t_LZCE

t_DELAY

DQ (DATA)

Notes

28. The software sequence is clocked with CE controlled or OE controlled reads.

29. The six consecutive addresses must be read in the order listed in Table 1. WE must be HIGH during all six consecutive cycles.

30. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

31. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.

Document #: 001-07103 Rev. *K

Page 21 of 31

PRELIMINARY

CY14B104K, CY14B104M

Hardware STORE Cycle

20 ns

25 ns

45 ns

Parameters

Description

Unit

Min

Max

Min

Max

Min

Max

HSB To Output Active Time when write latch not set

Hardware STORE Pulse Width

DHSB

PHSB

Switching Waveforms

[24]

Figure 15. Hardware STORE Cycle

Write latch set

t_PHSB

HSB (IN)

t_STORE

t_HHHD

t_DELAY

HSB (OUT)

DQ (Data Out)

RWI

t_LZHSB

Write latch not set

t_PHSB

HSB pin is driven high to V_CConly by Internal

100kOhm resistor,

HSB (IN)

HSB driver is disabled

SRAM is disabled as long as HSB (IN) is driven low.

t_DELAY

t_DHSB

HSB (OUT)

RWI

[32, 33]

Figure 16. Soft Sequence Processing

t_SS

Soft Sequence

Command

Soft Sequence

Command

Address

Address #1

t_SA

Address #6

t_CW

Address #1

Address #6

t_CW

V_CC

Notes

32. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

33. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.

Document #: 001-07103 Rev. *K

Page 22 of 31

PRELIMINARY

CY14B104K, CY14B104M

Truth Table For SRAM Operations

HSB should remain HIGH for SRAM Operations.

For x8 Configuration

[2]

Inputs and Outputs

Mode

Deselect/Power down

Power

Standby

Active

High Z

Data Out (DQ –DQ );

Read

High Z

Output Disabled

Write

Active

Data in (DQ –DQ );

Active

For x16 Configuration

[2]

BHE

BLE

Inputs and Outputs

High-Z

Data Out (DQ –DQ

Mode

Power

Standby

Deselect/Power down

Output Disabled

Read

Active

)

Data Out (DQ –DQ );

Read

DQ –DQ in High-Z

Data Out (DQ –DQ );

Read

Active

DQ –DQ in High-Z

High-Z

Output Disabled

Write

Active

High-Z

Data In (DQ –DQ

)

Data In (DQ –DQ );

Write

DQ –DQ in High-Z

Data In (DQ –DQ );

Write

Active

DQ –DQ in High-Z

Document #: 001-07103 Rev. *K

Page 23 of 31

PRELIMINARY

CY14B104K, CY14B104M

Part Numbering Nomenclature

CY14 B 104 K ZS P 20 X C T

Option:

T - Tape & Reel

Blank - Std.

Temperature:

C - Commercial (0 to 70°C)

I - Industrial (–40 to 85°C)

Speed:

20 - 20 ns

Pb-Free

25 - 25 ns

45 - 45 ns

P - 54 Pin

Blank - 44 Pin

Package:

ZS - TSOP II

Data Bus:

K - x8 + RTC

M - x16 + RTC

Density:

104 - 4 Mb

Voltage:

B - 3.0V

NVSRAM

14 - AutoStore + Software STORE + Hardware STORE

Cypress

Document #: 001-07103 Rev. *K

Page 24 of 31

PRELIMINARY

CY14B104K, CY14B104M

Ordering Information

Speed

(ns)

Package

Diagram

Operating

Range

Ordering Code

Package Type

CY14B104K-ZS20XCT

CY14B104K-ZS20XC

CY14B104K-ZS20XIT

CY14B104K-ZS20XI

51-85087

51-85160

51-85087

51-85187

51-85160

51-85087

51-85187

51-85160

44-pin TSOPII

54-pin TSOPII

44-pin TSOPII

54-pin TSOPII

44-pin TSOPII

54-pin TSOPII

Commercial

Industrial

CY14B104M-ZSP20XCT

CY14B104M-ZSP20XC

CY14B104M-ZSP20XIT

CY14B104M-ZSP20XI

CY14B104K-ZS25XCT

CY14B104K-ZS25XC

CY14B104K-ZS25XIT

CY14B104K-ZS25XI

Commercial

Industrial

Commercial

Industrial

CY14B104M-ZSP25XCT

CY14B104M-ZSP25XC

CY14B104M-ZSP25XIT

CY14B104M-ZSP25XI

CY14B104K-ZS45XCT

CY14B104K-ZS45XC

CY14B104K-ZS45XIT

CY14B104K-ZS45XI

Commercial

Industrial

Commercial

Industrial

CY14B104M-ZSP45XCT

CY14B104M-ZSP45XC

CY14B104M-ZSP45XIT

CY14B104M-ZSP45XI

Commercial

Industrial

All parts are Pb-free. The above table contains Preliminary information. Please contact your local Cypress sales representative for availability of these parts.

Document #: 001-07103 Rev. *K

Page 25 of 31

PRELIMINARY

CY14B104K, CY14B104M

Package Diagrams

Figure 17. 44-Pin TSOP II (51-85087)

DIMENSION IN MM (INCH)

MAX

MIN.

PIN 1 I.D.

S G

EJECTOR PIN

TOP VIEW

BOTTOM VIEW

10.262 (0.404)

10.058 (0.396)

0.400(0.016)

0.300 (0.012)

0.800 BSC

(0.0315)

BASE PLANE

0.10 (.004)

0.210 (0.0083)

0.120 (0.0047)

0°-5°

18.517 (0.729)

18.313 (0.721)

0.597 (0.0235)

0.406 (0.0160)

SEATING

PLANE

51-85087 *A

Document #: 001-07103 Rev. *K

Page 26 of 31

PRELIMINARY

CY14B104K, CY14B104M

Package Diagrams (continued)

Figure 18. 54-Pin TSOP II (51-85160)

51-85160 **

Document #: 001-07103 Rev. *K

Page 27 of 31

PRELIMINARY

CY14B104K, CY14B104M

Document History Page

Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock

Document Number: 001-07103

Submission

Date

Orig. of

Change

Rev. ECN No.

Description of Change

431039

489096

See ECN

TUP

New Data Sheet

Removed 48 SSOP Package

Added 44 TSOPII and 54 TSOPII Packages

Updated Part Numbering Nomenclature and Ordering Information

Added Soft Sequence Processing Time Waveform

Added RTC Characteristics Table

Added RTC Recommended Component Configuration

499597

See ECN

PCI

Removed 35ns speed bin

Added 55ns speed bin. Updated AC table for the same

Changed “Unlimited” read/write to “infinite” read/write

Features section: Changed typical I at 200-ns cycle time to 8 mA

Changed STORE cycles from 500K to 200K cycles.

Shaded Commercial grade in operating range table.

Modified Icc/Isb specs.

Changed V

value in DC table

CAP

Added 44 TSOP II in Thermal Resistance table

Modified part nomenclature table. Changes reflected in the ordering information

table.

517793

See ECN

TUP

Removed 55ns speed bin

Changed pinout for 44TSOPII and 54TSOPII packages

Changed I to 1mA

Changed I

to 3mA

CC4

Changed V

Changed V max to Vcc + 0.5V

min to 35μF

CAP

Changed t

to 15ns

to 10ns

to 15ns

STORE

PWE

SCE

Changed t to 5ns

Changed t

to 10ns

Removed t

HLBL

Added Timing Parameters for BHE and BLE - t

Removed min. specification for Vswitch

, t

DBE LZBE HZBE BW

Changed t

to 1ns

max. of 70us

GLAX

Added t

DELAY

Changed t specification from 70us min. to 70us max.

825240

914280

See ECN

UHA

Changed the data sheet from Advance information to Preliminary

Changed t

Changed the value of I

Changed the value of t

to 10ns in 15ns part

DBE

in 15ns part to 7ns and in 25ns part to10ns

HZBE

in 15ns part to 15ns and in 25ns part to 20ns

to t

GLAX

GHAX

to 25mA

in 15ns part to 15ns

CC3

Changed the figure-14 title from 54-Pb to 54 Pin

Included all the information for 45ns part in this data sheet

Document #: 001-07103 Rev. *K

Page 28 of 31

PRELIMINARY

CY14B104K, CY14B104M

Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock

Document Number: 001-07103

Submission

Date

Orig. of

Change

Rev. ECN No.

Description of Change

1890926

See ECN

vsutmp8/AE- Added Footnote 1, 2 and 3.

Updated Logic Block diagram

Updated Pin definition Table

Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8)

package.

Corrected typo in V min spec

Changed the value of I

from 25mA to 13mA

CC3

Changed I value from 1mA to 2mA

Updated ordering information table

Rearranging of Footnotes.

Changed Package diagrams title.

The pins X1 and X2 interchanged in 44TSOP II(x8) and 54TSOP II(x16) pinout

diagram.

2267286

See ECN

GVCH/PYRS Rearranging of “Features”

Added BHE and BLE Information in Pin Definitions Table

Updated Figure 2 (Autostore mode)

Updated footnote 6

RTC Register Map:Register 0x1FFF6:Changed D4 from ABE to 0

information

Changed I

& I

from 3mA to 6mA

CC2

CC3

CC4

from 13mA to 15mA

Changed I from 2mA to 3mA

Added input leakage current (I ) for HSB in DC Electrical Characteristics table

Changed Vcap from 35uF min and 57uF max value to 54uF min and 82uF max

value

Corrected typo in t

value from 22ns to 20ns for 45ns part

DBE

value from 22ns to 15ns for 45ns part

HZBE

value from 15ns to 10ns for 15ns part

Changed Vrtccap max from 2.7V to 3.6V

Changed tRECALL from 100 to 200us

Added footnote 10, 29

Reframed footnote 18, 25

Added footnote 18 to figure 8 (SRAM WRITE Cycle #1)

Added footnote 18, 26 and 27 to figure 9 (SRAM WRITE Cycle #2)

2483627

See ECN

GVCH/PYRS Removed 8 mA typical I at 200 ns cycle time in Feature section

Referenced footnote 9 to I

in DC Characteristics table

CC3

Changed I

from 15 mA to 35 mA

CC3

Changed Vcap minimum value from 54 uF to 61 uF

Changed t to t

AVAV

Changed V

minimum value from 1.2V to 1.5V

RTCcap

Figure 12:Changed t to t and t

SCE to CW

Document #: 001-07103 Rev. *K

Page 29 of 31

PRELIMINARY

CY14B104K, CY14B104M

Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock

Document Number: 001-07103

Submission

Date

Orig. of

Change

Rev. ECN No.

Description of Change

2519319

06/20/08

GVCH/PYRS Added 20 ns access speed in “Features”

Added I for tRC=20 ns for both industrial and Commercial temperature Grade

CC1

Updated Thermal resistance values for 44-TSOP II and 54-TSOP II packages

Added AC Switching Characteristics specs for 20 ns access speed

Added Software controlled STORE/RECALL cycle specs for 20 ns access speed

Updated ordering information and Part numbering nomenclature

2600941

11/04/08

GVCH/PYRS Removed 15 ns access speed from “Features”

Changed part number from CY14B104K/CY14B104M to

CY14B104KA/CY14B104MA

Updated Logic block diagram

Updated footnote 1

Added footnote 2

Pin definition: Updated WE, HSB and NC pin description

Page 4: Updated SRAM READ, SRAM WRITE, Autostore operation description

Page 4: Updated Hardware store operation and Hardware RECALL (Power up)

description

Footnote 1 and 8 referenced for Mode selection Table

Updated footnote 6

Page 6: updated Data protection description

Page 6: Updated Starting and stopping the oscillator description

Page 7: Updated Calibrating the clock description

Page 7: Updated Alarm description

Page 8: Added Flags register

Added footnote 10 and 11

Updated Figure 4: Removed RF register and Changed C value from 56pF to

12pF

Updated Register Map Table 3

Updated Register map detail Table 4

Maximum Ratings: Added Max. Accumulated storage time

Changed Output short circuit current parameter name to DC output current

Changed I

from 6mA to 10mA

from 6mA to 5mA

CC2

CC4

Changed I from 3mA to 5mA

Updated I

and I Test conditions

CC1, CC3, SB

Changed V

voltage max value from 82uF to 180uF

CAP

Updated footnote 12 and 13

Added footnote 14

Added Data retention and Endurance Table

Updated Input Rise and Fall time in AC test Conditions

Changed tOCS value for minimum temperature from 10 to 2 sec

updated tOCS value for room temperature from 5 to 1sec

Referenced footnote 20 to t

parameter

OHA

Updated All switching waveforms

Updated footnote 20

Added Figure 11 (SRAM WRITE CYCLE:BHE and BLE controlled)

Updated t

value

DELAY

Added V

, t

and t

parameters

HDIS HHHD

LZHSB

Updated footnote 27

Added footnote 29

Software controlled STORE/RECALL Table: Changed t to t

Changed t

to t

GHAX

Changed t value from 1ns to 1ns

Added t

parameter

DHSB

Changed t

to t

HLHX

PHSB

Updated t from 70us to 100us

Added truth table for SRAM operations

Updated ordering information and part numbering nomenclature

Document #: 001-07103 Rev. *K

Page 30 of 31

psoc.cypress.com/solutions

PRELIMINARY

CY14B104K, CY14B104M

Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock

Document Number: 001-07103

Submission

Date

Orig. of

Change

Rev. ECN No.

*K 2653928

Description of Change

02/04/09

GVCH/PYRS Changed Part number from CY14B104KA/CY14B104MA to

CY14B104K/CY14B104M

Updated Real Time Clock operation description

Added factory default values to register map table 3

Added footnote 9

Updated Flag register description in Table 4

Updated C1, C2 values to 21uF, 21uF respectively

Changed I

Changed V

value from 350 nA to 450 nA at hot temperature

BAK

typical value from 2.4V to 3.0V

RTCcap

Referenced Note 15 to parameters t

, t

LZCE HZCE LZOE, HZOE, LZBE, LZWE, HZWE-

and t

HZBE

Added footnote 22

Updated Figure 13

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at cypress.com/sales.

Products

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PSoC Solutions

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psoc.cypress.com/low-power

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psoc.cypress.com/usb

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 001-07103 Rev. *K

Revised January 29, 2009

Page 31 of 31

AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective

holders.