PRELIMINARY
CY14B104LA, CY14B104NA
4 Mbit (512K x 8/256K x 16) nvSRAM
Features
Functional Description
■
20 ns, 25 ns, and 45 ns access times
The Cypress CY14B104LA/CY14B104NA is a fast static RAM,
with a nonvolatile element in each memory cell. The memory is
■
Internally organized as 512K x 8 (CY14B104LA) or 256K x 16
(CY14B104NA)
organized as 512K bytes of 8 bits each or 256K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
■
■
Hands off automatic STORE on power down with only a small
capacitor
STORE to QuantumTrap® nonvolatile elements initiated by
software, device pin, or AutoStore® on power down
■
■
■
■
■
■
■
■
RECALL to SRAM initiated by software or power up
Infinite Read, Write, and Recall cycles
200,000 STORE cycles to QuantumTrap
20 year data retention
Single 3V +20%, -10% operation
Commercial and industrial temperatures
48-ball FBGA and 44/54-pin TSOP-II packages
Pb-free and RoHS compliance
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Notes
1. Address A - A for x8 configuration and Address A - A for x16 configuration.
0
18
0
17
2. Data DQ - DQ for x8 configuration and Data DQ - DQ for x16 configuration.
0
7
0
15
3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-49918 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 11, 2009
PRELIMINARY
CY14B104LA, CY14B104NA
Pinouts (continued)
Figure 3. Pin Diagram - 54 Pin TSOP II (x16)
NC
54
53
52
51
50
49
HSB
NC
1
2
3
[4]
NC
A
0
A
17
A
1
A
16
4
5
6
A
2
A
15
A
3
OE
48
47
46
45
A
4
BHE
BLE
DQ
7
8
9
10
11
12
13
14
CE
DQ
DQ
0
1
15
DQ
DQ
DQ
V
14
13
12
54 - TSOP II
(x16)
DQ
DQ
44
43
42
41
40
39
2
3
V
CC
SS
Top View
(not to scale)
V
SS
V
CC
DQ
DQ
4
15
16
17
18
19
20
21
22
23
24
11
DQ
DQ
DQ
DQ
5
10
38
37
36
35
DQ
DQ
6
9
8
7
WE
A
5
V
CAP
A
14
34
33
32
31
30
29
28
A
6
A
13
A
A
7
A
8
12
A
11
A
A
9
10
NC
NC
NC
NC
NC
NC
25
26
27
Pin Definitions
Pin Name
A0 – A18
A0 – A17
I/O Type
Description
Input
Address Inputs Used to Select one of the 524,288 bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select one of the 262,144 words of the nvSRAM for x16 Configuration.
DQ0 – DQ7 Input/Output Bidirectional Data I/O Lines for x8 Configuration. Used as input or output lines depending on
operation.
DQ0 – DQ15
WE
Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on
operation.
Input
Write Enable Input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
Input
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
CE
OE
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tri-stated on deasserting OE HIGH.
Input
Input
Byte High Enable, Active LOW. Controls DQ15 - DQ8.
Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
BHE
BLE
VSS
Ground
Ground for the Device. Must be connected to the ground of the system.
VCC
Power Supply Power Supply Inputs to the Device.
Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection optional). After each store operation HSB
is driven HIGH for short time with standard output high current.
VCAP
NC
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
No Connect No Connect. This pin is not connected to the die.
Document #: 001-49918 Rev. *A
Page 3 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
the VCAP pin is driven to VCC by a regulator on the chip. A pull
up should be placed on WE to hold it inactive during power up.
This pull up is effective only if the WE signal is tri-state during
power up. Many MPUs tri-state their controls on power up. This
should be verified when using the pull up. When the nvSRAM
comes out of power-on-recall, the MPU must be active or the WE
held inactive until the MPU comes out of reset.
Device Operation
The CY14B104LA/CY14B104NA nvSRAM is made up of two
functional components paired in the same physical cell. They are
a SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B104LA/CY14B104NA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
16 for a complete description of read and write modes.
To reduce unnecessary nonvolatile stores, AutoStore and
hardware store operations are ignored unless at least one write
operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 4. AutoStore Mode
SRAM Read
Vcc
The CY14B104LA/CY14B104NA performs a read cycle when
CE and OE are LOW and WE and HSB are HIGH. The address
specified on pins A0-18 or A0-17 determines which of the 524,288
data bytes or 262,144 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of tAA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at tACE or at tDOE, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
tAA access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
0.1uF
Vcc
WE
VCAP
VCAP
VSS
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–15
are written into the memory if the data is valid tSD before the end
of a WE controlled write or before the end of an CE controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. It is recommended that
OE be kept HIGH during the entire write cycle to avoid data bus
contention on common I/O lines. If OE is left LOW, internal
circuitry turns off the output buffers tHZWE after WE goes LOW.
Hardware STORE Operation
control and acknowledge the STORE operations. Use the HSB
pin to request a hardware STORE cycle. When the HSB pin is
driven LOW, the CY14B104LA/CY14B104NA conditionally
initiates a STORE operation after tDELAY. An actual STORE cycle
only begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven LOW to indicate a busy
condition when the STORE (initiated by any means) is in
progress.
AutoStore Operation
SRAM read and write operations that are in progress when HSB
is driven LOW by any means are given time to complete before
the STORE operation is initiated. After HSB goes LOW, the
CY14B104LA/CY14B104NA continues SRAM operations for
The CY14B104LA/CY14B104NA stores data to the nvSRAM
using one of the following three storage operations: Hardware
Store activated by HSB; Software Store activated by an address
sequence; AutoStore on device power down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14B104LA/CY14B104NA.
t
DELAY. If a write is in progress when HSB is pulled LOW it is
enabled a time, tDELAY to complete. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B104LA/CY14B104NA. But any SRAM read
and write cycles are inhibited until HSB is returned HIGH by MPU
or other external source.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
During any STORE operation, regardless of how it is initiated,
the CY14B104LA/CY14B104NA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. When the
STORE operation is completed, the CY14B104LA/CY14B104NA
Figure 4 shows the proper connection of the storage capacitor
Document #: 001-49918 Rev. *A
Page 4 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
remains disabled until the HSB pin returns HIGH. Leave the HSB
unconnected if it is not used.
The software sequence may be clocked with CE controlled reads
or OE controlled reads. After the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. HSB is driven LOW. It is important to use read cycles
and not write cycles in the sequence, although it is not necessary
that OE be LOW for a valid sequence. After the tSTORE cycle time
is fulfilled, the SRAM is activated again for the read and write
operation.
Hardware RECALL (Power Up)
During power up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
During this time, HSB is driven LOW by the HSB driver.
Software RECALL
Software STORE
Transfer the data from the nonvolatile memory to the SRAM with
a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed.
Transfer data from the SRAM to the nonvolatile memory with a
software address sequence. The CY14B104LA/CY14B104NA
software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
Table 1. Mode Selection
[7]
A15 - A0
Mode
I/O
Power
Standby
Active
CE
WE
H
X
X
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
L
L
L
H
L
L
X
L
Active
H
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Disable
Notes
7. While there are 19 address lines on the CY14B104LA (18 address lines on the CY14B104NA), only the 13 address lines (A - A ) are used to control software modes.
14
2
Rest of the address lines are don’t care.
8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document #: 001-49918 Rev. *A
Page 5 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
Table 1. Mode Selection (continued)
[7]
OE, BHE, BLE[3]
A15 - A0
Mode
I/O
Power
CE
WE
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
[8]
L
L
H
H
L
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Active ICC2
Nonvolatile Store Output High Z
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Preventing AutoStore
Data Protection
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
The CY14B104LA/CY14B104NA protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected
when
VCC
<
VSWITCH
.
If
the
CY14B104LA/CY14B104NA is in a write mode (both CE and WE
are LOW) at power up, after a RECALL or STORE, the write is
inhibited until the SRAM is enabled after tLZHSB (HSB to output
active). This protects against inadvertent writes during power up
or brown out conditions.
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
Noise Considerations
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (hardware or software) must be issued to save
the AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
Document #: 001-49918 Rev. *A
Page 6 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state (for example, autostore enabled). While
the nvSRAM is shipped in a preset state, best practice is to
again rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently such as
program bugs and incoming inspection routines.
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The VCAP value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirementandnotexceedthemaximumVCAPvaluebecause
the nvSRAM internal algorithm calculates VCAP charge and
discharge time based on this max VCAP value. Customers that
want to use a larger VCAP value to make sure there is extra
store charge and store time should discuss their VCAP size
selection with Cypress to understand any impact on the VCAP
voltage level at the end of a tRECALL period.
■
ThenonvolatilecellsinthisnvSRAMproductaredeliveredfrom
Cypress with 0x00 written in all cells. Incoming inspection
routines at customer or contract manufacturer’s sites
sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex
or more random bytes) as part of the final system manufac-
turing test to ensure these system routines work consistently.
Document #: 001-49918 Rev. *A
Page 7 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
Transient Voltage (<20 ns) on
Any Pin to Ground Potential................ ..–2.0V to VCC + 2.0V
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Package Power Dissipation
Capability (TA = 25°C)....................................................1.0W
Storage Temperature ..................................–65°C to +150°C
Maximum Accumulated Storage Time
Surface Mount Pb Soldering
Temperature (3 Seconds)...........................................+260°C
DC Output Current (1 output at a time, 1s duration) ....15 mA
At 150°C Ambient Temperature..........................1000h
At 85°C Ambient Temperature.................... ..20 Years
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Ambient Temperature with
Power Applied.............................................–55°C to +150°C
Latch Up Current................................................... > 200 mA
Supply Voltage on VCC Relative to GND.......... –0.5V to 4.1V
Operating Range
Voltage Applied to Outputs
in High-Z State ...................................... –0.5V to VCC + 0.5V
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
2.7V to 3.6V
2.7V to 3.6V
Input Voltage ..........................................–0.5V to Vcc + 0.5V
–40°C to +85°C
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.6V)
Parameter
Description
Test Conditions
Min
Max
Unit
ICC1
Average VCC Current tRC = 20 ns
tRC = 25 ns
Commercial
Industrial
65
65
50
mA
mA
mA
t
RC = 45 ns
Values obtained without output loads (IOUT = 0 mA)
70
70
52
mA
mA
mA
ICC2
Average VCC Current All Inputs Don’t Care, VCC = Max
during STORE Average current for duration tSTORE
10
mA
[9]
ICC3
AverageVCC Currentat All I/P cycling at CMOS levels.
RC= 200 ns, 3V, 25°C Values obtained without output loads (IOUT = 0 mA).
35
mA
t
typical
ICC4
ISB
Average VCAP Current All Inputs Don’t Care, VCC = Max
during AutoStore Cycle Average current for duration tSTORE
5
5
mA
mA
VCC Standby Current CE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V). Standby
current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
IIX
Input Leakage Current VCC = Max, VSS < VIN < VCC
(except HSB)
–1
–100
–1
+1
+1
+1
μA
μA
μA
V
Input Leakage Current VCC = Max, VSS < VIN < VCC
(for HSB)
IOZ
VIH
Off-State Output
Leakage Current
VCC = Max, VSS < VOUT < VCC, CE or OE > VIH or BHE/BLE > VIH
or WE < VIL
Input HIGH Voltage
2.0
VCC
0.5
+
VIL
Input LOW Voltage
Vss – 0.5
2.4
0.8
V
V
VOH
VOL
Output HIGH Voltage IOUT = –2 mA
Output LOW Voltage
Storage Capacitor
IOUT = 4 mA
0.4
V
VCAP
Between VCAP pin and VSS, 5V Rated
61
180
μF
Notes
9. Typical conditions for the active current shown on the DC Electrical characteristics are average values at 25°C (room temperature), and V = 3V. Not 100% tested.
CC
10. The HSB pin has I
= -2 uA for V of 2.4V when both active HIGH and LOW drivers are disabled. When they are enabled standard V and V are valid. This
OUT
O
H
O
H
O
L
parameter is characterized but not tested.
11. V (storage capacitor) nominal value is 68 uF.
CAP
Document #: 001-49918 Rev. *A
Page 8 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
Data Retention and Endurance
Parameter
Description
Min
20
Unit
Years
K
DATAR
NVC
Data Retention
Nonvolatile STORE Operation
200
Capacitance
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max
7
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
CC = 0 to 3.0V
V
COUT
7
pF
Thermal Resistance
Parameter
Description
Test Conditions
48-FBGA 44-TSOP II 54-TSOP II Unit
ΘJA
Thermal Resistance
(Junction to Ambient) and procedures for measuring thermal
Test conditions follow standard test methods
28.82
31.11
30.73
°C/W
impedance, in accordance with EIA/JESD51.
ΘJC
Thermal Resistance
(Junction to Case)
7.84
5.56
6.08
°C/W
Figure 5. AC Test Loads
577Ω
R1
for tri-state specs
577Ω
3.0V
OUTPUT
3.0V
OUTPUT
R1
R2
789Ω
R2
789Ω
5 pF
30 pF
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V
Input Rise and Fall Times (10% - 90%)........................ <3 ns
Input and Output Timing Reference Levels .................... 1.5V
Note
12. These parameters are guaranteed but not tested.
Document #: 001-49918 Rev. *A
Page 9 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
AC Switching Characteristics
Parameters
20 ns
25 ns
45 ns
Description
Unit
Cypress
Parameters
Alt
Min
Max
Min
Max
Min
Max
Parameters
SRAM Read Cycle
tACE
tACS
tRC
tAA
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
-
Chip Enable Access Time
20
25
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[13]
tRC
Read Cycle Time
20
25
45
tAA
Address Access Time
20
10
25
12
45
20
tDOE
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Byte Enable to Data Valid
tOHA
3
3
3
3
3
3
tLZCE
tHZCE
tLZOE
8
8
10
10
15
15
0
0
0
0
0
0
tHZOE
[12]
tPU
[12]
tPD
20
10
25
12
45
20
tDBE
tLZBE
-
Byte Enable to Output Active
Byte Disable to Output Inactive
0
0
0
tHZBE
-
8
10
15
SRAM Write Cycle
tWC
tPWE
tSCE
tSD
tWC
Write Cycle Time
20
15
15
8
25
20
20
10
0
45
30
30
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWP
tCW
tDW
tDH
tAW
tAS
tWR
tWZ
tOW
-
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active after End of Write
Byte Enable to End of Write
tHD
0
tAW
15
0
20
0
30
0
tSA
tHA
0
0
0
tHZWE
8
10
15
tLZWE
tBW
3
3
3
15
20
30
Switching Waveforms
tRC
Address
Address Valid
tAA
Output Data Valid
Previous Data Valid
tOHA
Data Output
Notes
13. WE must be HIGH during SRAM read cycles.
14. Device is continuously selected with CE, OE and BHE / BLE LOW.
15. Measured ±200 mV from steady state output voltage.
16. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
17. HSB must remain HIGH during read and write cycles.
Document #: 001-49918 Rev. *A
Page 10 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
Address
CE
Address Valid
tRC
tHZCE
tACE
tAA
tLZCE
tHZOE
tDOE
OE
tHZBE
tLZOE
tDBE
BHE, BLE
tLZBE
High Impedance
Standby
Data Output
Output Data Valid
tPU
tPD
Active
ICC
tWC
Address
Address Valid
tSCE
tHA
CE
tBW
BHE, BLE
tAW
tPWE
WE
Data Input
Data Output
tSA
tHD
tSD
Input Data Valid
tLZWE
tHZWE
High Impedance
Previous Data
Note
18. CE or WE must be >V during address transitions.
IH
Document #: 001-49918 Rev. *A
Page 11 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tBW
BHE, BLE
tPWE
WE
tHD
tSD
Input Data Valid
Data Input
High Impedance
Data Output
tWC
Address
CE
Address Valid
tSCE
tSA
tHA
tBW
BHE, BLE
WE
tAW
tPWE
tSD
tHD
Data Input
Input Data Valid
High Impedance
Data Output
Document #: 001-49918 Rev. *A
Page 12 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
AutoStore/Power Up RECALL
20 ns
25 ns
45 ns
Parameters
Description
Unit
Min
Max
20
Min
Max
20
Min
Max
20
[19]
tHRECALL
Power Up RECALL Duration
STORE Cycle Duration
ms
ms
ns
V
[20]
tSTORE
8
8
8
tDELAY
Time Allowed to Complete SRAM Cycle
Low Voltage Trigger Level
VCC Rise Time
20
25
25
VSWITCH
2.65
2.65
2.65
tVCCRISE
150
150
150
μs
V
VHDIS
HSB Output Driver Disable Voltage
HSB To Output Active Time
HSB High Active Time
1.9
5
1.9
5
1.9
5
tLZHSB
tHHHD
μs
ns
500
500
500
Switching Waveforms
VSWITCH
VHDIS
Note20
Note20
VVCCRISE
tSTORE
tSTORE
Note23
tHHHD
tHHHD
HSB OUT
Autostore
tDELAY
tLZHSB
tLZHSB
tDELAY
POWER-
UP
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(RWI)
Read & Write
Read & Write
POWER-UP
RECALL
BROWN
OUT
Autostore
POWER
DOWN
Autostore
POWER-UP
RECALL
Notes
19. t
starts from the time V rises above V
SWITCH.
HRECALL
CC
20. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware Store takes place.
21. On a Hardware STORE, Software Store / Recall, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time t
.
DELAY
22. Read and write cycles are ignored during STORE, RECALL, and while VCC is below V
SWITCH.
23. HSB pin is driven HIGH to VCC only by internal 100 kOhm resistor, HSB driver is disabled.
Document #: 001-49918 Rev. *A
Page 13 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
Software Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE and RECALL cycle parameters are listed.[24, 25]
20 ns
Max
25 ns
Max
45 ns
Max
Parameters
tRC
tSA
tCW
tHA
tRECALL
Description
Unit
Min
20
0
Min
25
0
Min
45
0
STORE/RECALL Initiation Cycle Time
Address Setup Time
ns
ns
ns
ns
μs
Clock Pulse Width
15
0
20
0
30
0
Address Hold Time
RECALL Duration
200
200
200
Switching Waveforms
W5&
W5&
$GGUHVV
&(
$GGUHVVꢀꢍꢇ
W&:
$GGUHVVꢀꢍꢊ
W&:
W6$
W+$
W+$
W+$
W6$
W+$
2(
W+++'
W+=&(
+6%ꢀꢎ6725(ꢀRQO\ꢏ
'4ꢀꢎ'$7$ꢏ
W'(/$<
W/=&(
W/=+6%
+LJKꢀ,PSHGDQFH
W6725(ꢅW5(&$//
5:,
Figure 13. AutoStore Enable/Disable Cycle
W5&
W5&
$GGUHVV
&(
$GGUHVVꢀꢍꢇ
W&:
$GGUHVVꢀꢍꢊ
W&:
W6$
W+$
W+$
W+$
W6$
W+$
2(
W66
W+=&(
W/=&(
W'(/$<
'4ꢀꢎ'$7$ꢏ
5:,
Notes
24. The software sequence is clocked with CE controlled or OE controlled reads.
25. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles.
Document #: 001-49918 Rev. *A
Page 14 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
Hardware STORE Cycle
20 ns
25 ns
45 ns
Parameters
Description
Unit
Min
Max
Min
Max
Min
Max
tDHSB
tPHSB
HSB To Output Active Time when write latch not set
Hardware STORE Pulse Width
20
25
25
ns
ns
μs
15
15
15
tSS
Soft Sequence Processing Time
100
100
100
Switching Waveforms
Write latch set
tPHSB
HSB (IN)
tSTORE
tHHHD
tDELAY
HSB (OUT)
DQ (Data Out)
RWI
tLZHSB
Write latch not set
tPHSB
HSB pin is driven high to VCC only by Internal
100kOhm resistor,
HSB (IN)
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
tDELAY
tDHSB
tDHSB
HSB (OUT)
RWI
tSS
tSS
Soft Sequence
Command
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
Address #1
Address #6
tCW
CE
VCC
Notes
26. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
27. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
Document #: 001-49918 Rev. *A
Page 15 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
For x8 Configuration
CE
H
L
WE
X
OE
X
Mode
Deselect/Power down
Read
Power
Standby
High Z
H
L
Data Out (DQ0–DQ7);
High Z
Active
Active
Active
L
H
H
Output Disabled
Write
L
L
X
Data in (DQ0–DQ7);
For x16 Configuration
CE
H
L
WE
X
OE
X
Mode
Deselect/Power down
Output Disabled
Read
Power
X
H
L
X
H
L
High-Z
Standby
Active
Active
Active
X
X
High-Z
L
H
L
Data Out (DQ0–DQ15)
L
H
L
H
L
Data Out (DQ0–DQ7);
DQ8–DQ15 in High-Z
Read
L
H
L
L
H
Data Out (DQ8–DQ15);
DQ0–DQ7 in High-Z
Read
Active
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High-Z
High-Z
High-Z
Output Disabled
Output Disabled
Output Disabled
Write
Active
Active
Active
Active
Active
L
Data In (DQ0–DQ15)
L
H
Data In (DQ0–DQ7);
DQ8–DQ15 in High-Z
Write
L
L
X
L
H
Data In (DQ8–DQ15);
DQ0–DQ7 in High-Z
Write
Active
Document #: 001-49918 Rev. *A
Page 16 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
Ordering Information
Speed
Package
Operating
Ordering Code
Package Type
(ns)
Diagram
51-85087
51-85087
51-85087
51-85087
51-85128
51-85128
51-85128
51-85128
51-85087
51-85087
51-85087
51-85087
51-85128
51-85128
51-85128
51-85128
51-85160
51-85160
51-85160
51-85160
51-85087
51-85087
51-85087
51-85087
51-85128
51-85128
51-85128
51-85128
51-85087
51-85087
51-85087
51-85087
51-85128
51-85128
51-85128
51-85128
51-85128
51-85160
51-85160
51-85160
51-85160
Range
20
CY14B104LA-ZS20XCT
CY14B104LA-ZS20XC
CY14B104LA-ZS20XIT
CY14B104LA-ZS20XI
CY14B104LA-BA20XCT
CY14B104LA-BA20XC
CY14B104LA-BA20XIT
CY14B104LA-BA20XI
CY14B104NA-ZS20XCT
CY14B104NA-ZS20XC
CY14B104NA-ZS20XIT
CY14B104NA-ZS20XI
CY14B104NA-BA20XCT
CY14B104NA-BA20XC
CY14B104NA-BA20XIT
CY14B104NA-BA20XI
CY14B104NA-ZSP20XCT
CY14B104NA-ZSP20XC
CY14B104NA-ZSP20XIT
CY14B104NA-ZSP20XI
CY14B104LA-ZS25XCT
CY14B104LA-ZS25XC
CY14B104LA-ZS25XIT
CY14B104LA-ZS25XI
CY14B104LA-BA25XCT
CY14B104LA-BA25XC
CY14B104LA-BA25XIT
CY14B104LA-BA25XI
CY14B104NA-ZS25XCT
CY14B104NA-ZS25XC
CY14B104NA-ZS25XIT
CY14B104NA-ZS25XI
CY14B104NA-BA25XCT
CY14B104NA-BA25XC
CY14B104NA-BA25XIT
CY14B104NA-BA25XI
CY14B104NA-BA25I
44-pin TSOP II
44-pin TSOP II
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
44-pin TSOP II
44-pin TSOP II
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
44-pin TSOP II
44-pin TSOP II
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
44-pin TSOP II
44-pin TSOP II
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
25
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
CY14B104NA-ZSP25XCT
CY14B104NA-ZSP25XC
CY14B104NA-ZSP25XIT
CY14B104NA-ZSP25XI
Commercial
Industrial
Document #: 001-49918 Rev. *A
Page 17 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
Ordering Information (continued)
Speed
Package
Operating
Ordering Code
(ns)
Package Type
Diagram
51-85087
51-85087
51-85087
51-85087
51-85128
51-85128
51-85128
51-85128
51-85087
51-85087
51-85087
51-85087
51-85128
51-85128
51-85128
51-85128
51-85160
51-85160
51-85160
51-85160
Range
45
CY14B104LA-ZS45XCT
CY14B104LA-ZS45XC
CY14B104LA-ZS45XIT
CY14B104LA-ZS45XI
CY14B104LA-BA45XCT
CY14B104LA-BA45XC
CY14B104LA-BA45XIT
CY14B104LA-BA45XI
CY14B104NA-ZS45XCT
CY14B104NA-ZS45XC
CY14B104NA-ZS45XIT
CY14B104NA-ZS45XI
CY14B104NA-BA45XCT
CY14B104NA-BA45XC
CY14B104NA-BA45XIT
CY14B104NA-BA45XI
CY14B104NA-ZSP45XCT
CY14B104NA-ZSP45XC
CY14B104NA-ZSP45XIT
CY14B104NA-ZSP45XI
44-pin TSOP II
44-pin TSOP II
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
44-pin TSOP II
44-pin TSOP II
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-ball FBGA
48-ball FBGA
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
The above table contains Preliminary information. Contact your local Cypress sales representative for availability of these parts.
Document #: 001-49918 Rev. *A
Page 18 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
Part Numbering Nomenclature
CY 14 B 104 L A -ZS P 20 X C T
Option:
T - Tape & Reel
Blank - Std.
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
X - Pb-Free
Blank - SnPb
Speed:
20 - 20 ns
25 - 25 ns
45 - 45 ns
P - 54 Pin
Blank - 44 Pin/48 Ball
Package:
BA - 48 FBGA
ZS - TSOP II
Die Revision:
Blank - No Rev
A - 1st Rev
Data Bus:
L - x8
N - x16
Density:
104 - 4 Mb
Voltage:
B - 3.0V
NVSRAM
14 - Auto Store + Software Store + Hardware Store
Cypress
Document #: 001-49918 Rev. *A
Page 19 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
Package Diagrams
Figure 16. 44-Pin TSOP II (51-85087)
DIMENSION IN MM (INCH)
MAX
MIN.
PIN 1 I.D.
22
1
R
O
E
K
A
X
S G
EJECTOR PIN
23
44
TOP VIEW
BOTTOM VIEW
10.262 (0.404)
10.058 (0.396)
0.400(0.016)
0.300 (0.012)
0.800 BSC
(0.0315)
BASE PLANE
0.10 (.004)
0.210 (0.0083)
0.120 (0.0047)
0°-5°
18.517 (0.729)
18.313 (0.721)
0.597 (0.0235)
0.406 (0.0160)
SEATING
PLANE
51-85087-*A
Document #: 001-49918 Rev. *A
Page 20 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
Package Diagrams (continued)
Figure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30 0.05(48X)
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15(4X)
SEATING PLANE
C
51-85128-*D
Document #: 001-49918 Rev. *A
Page 21 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
Package Diagrams (continued)
Figure 18. 54-Pin TSOP II (51-85160)
51-85160-**
Document #: 001-49918 Rev. *A
Page 22 of 23
PRELIMINARY
CY14B104LA, CY14B104NA
Document History Page
Document Title: CY14B104LA/CY14B104NA 4 Mbit (512K x 8/256K x 16) nvSRAM
Document Number: 001-49918
Submission
Rev. ECN No. Orig. of Change
Description of Change
Date
**
2606696
2672700
GVCH/PYRS
GVCH/PYRS
11/13/08
03/12/09
New Data Sheet
*A
Added best practices
Added CY14B104NA-BA25I part number
Added footnote12 for HZ/LZ parameters
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
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© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-49918 Rev. *A
Revised March 11, 2009
Page 23 of 23
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductors. All other products and company names mentioned in this document are the trademarks of their respective holders.
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