Application Note: Spartan-II
MP3 NG: A Next Generation Consumer
Platform
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Application Note
Summary
This application note illustrates the use of Xilinx Spartan-II FPGA and an IDT RC32364 RISC
controller in a handheld, consumer electronics platform. Specifically the target application is an
MP3 audio player with advanced user interface features.
In this application the Spartan device is used to implement the complex system level glue logic
required to interface and manage the memory and I/O devices. The RC32364 implements the
MP3 decoding functions, the graphical user interface, and various device control functions.
Introduction
While the design is targeted at solving a specific problem, decoding and playing compressed
audio streams, it illustrates solutions to a number of general technical issues. These include:
• Supporting a graphical user interface in an embedded system.
• Implementing cost-effective interfaces to LCD displays, touch screens, USB, IRDA, and
CompactFlash in an embedded system.
• Error handling when using NAND FLASH memory.
• Controlling SDRAM memory.
MP3
MP3 Market
Background
The MP3 player market emerged in late 1998, when Diamond Multimedia shipped its Rio MP3
audio player. While there is considerable diversity in opinions about the potential size of this
market, market analysts all agree that the opportunity is significant and will experience rapid
growth in the short term. Like any new market, the feature set of MP3 players is likely to change
as more users buy them. Key dynamics in this market include:
• Copy Protection. While the Secure Digital Music Initiative (SDMI) promises to make a
wider variety of music available in MP3 format, there is considerable technical uncertainty
about implementation timetables.
• Non-MP3 Formats. While MP3 is the dominant format for music available on the Internet,
other large players are pushing other formats tailored to their business agendas.
• Extended Features. At $150 to $250 an MP3 player is a relatively expensive consumer
electronics purchase. The dominant component of that price is the FLASH memory that
these devices use. This cost component is more or less the same for all vendors, and
constrains price point differentiation. One way to increase the perceived value of an MP3
player, and therefore get a competitive advantage, is to add value added features tailored to
the target market.
Due to these market dynamics, including the potential for rapid changes in feature
requirements, the best approach is a flexible high-performance system. This flexibility
manifests itself in two forms. The first is the use of a high-performance processor, which
supports the addition of additional soft features without the need to resort to optimized
assembly language. The second is the use of a low-cost, high-density FPGA to provide flexible
I/O support for the processor.
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SED1743
LCD Column
Driver
7
Serial Data
128
128
USBN9602
3
USB
128 x 128
LCD Panel
&
Control
Interface
SED1758
LCD Row
Driver
2
3
Serial Data
Serial Data
4 Wire Touch
Membrane
8
IRQ
RC32364
RISC
CPU
Xilinx
Spartan II
FPGA
32
21
Addr/Data
Control
MAX1108
2 Channel
ADC
2
3
Control Port
Serial Audio
L
CS4343
Audio
DAC
To Stereo
Headphone
Jack
R
IRMS6100
IRDA
Transceiver
3
16 Data
11 Address
17 Control
11 Control
CompactFlash
Interface
9
Control
8
MT48LC1M16A1
SDRAM
KM29U64000T
FLASH
Figure 1: MP3 NG System Block Diagram
IDT RC32364 RISController™
The processor chosen for this design is the IDT RC32364. The features of this device that are
leveraged in this application are:
• Paged memory management unit.
• High-performance, 175 dhrystone MIPs at 133 MHz.
• Integer Multiply ACcumulate (MAC) support, 67M MACs/second at 133 MHz.
• Separate, line lockable, instruction (8 KB) and data (2 KB) caches.
• Power saving features including active power management and a power-down operating
mode.
• On-chip In Circuit Emulation (ICE) interface to provide access to internal CPU state
(registers, cache) and for debug control (breakpoints, single step, insert instructions into
pipeline).
Figure 2 shows the block diagram for this device. The complete data sheet for the RC32364
can be found at the following URL:
The RC32364’s MMU consists of address translation logic and a Translation Lookaside Buffer
(TLB) capable of supporting demand paged virtual memory. In addition, it includes several
features that are valuable in an embedded application such as variable sized pages and
by the RC32364.
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The variable page size lets each mapping independently represent memory regions that can
range from 4 KB to 16 MB. This feature lets the system designer adjust the address mapping
granularity for different memory regions.
Locking TLB entries excludes entries from being recommended for replacement when there is
an address miss. This lets the system designer have mappings for critical regions of code and
or data locked into the TLB for predictable real time performance.
RISCore32300TM
Extended MIPS 32
Integer CPU Core
RISCore4000 Compatible
System Control
Coprocessor (CPO)
MMU
w/
TLB
8kB
2-set,
I-Cache,
lockable
2kB D-Cache, 2-set,
lockable, write-back/write-through
RISCore32300 Internal Bus Interface
RC32364 Bus Interface Unit
Clock
Generation
Unit
Figure 2: RC32364 Block Diagram
(Courtesy IDT)
Virtual Address with 1M (220) 4-Kbyte pages
39
32 31 29 28
12 11
0
20 bits = 1M
VPN
20
ASID
8
Offset
12
Offset passed
Virtual-to-physical-
unchanged
physical memory
to
translation in TLB
Bits 31, 30 and 29 of the
virtual address select user, super-
visor, or kernel address spaces.
TLB
32-bit Physical Address
31
0
PFN
Offset
Offset
unchanged to physical
memory.
Virtual-to-
physical transla-
tion in TLB
pa ssed
TLB
39
32 31 29 28
24 23
0
VPN
Offset
24
ASID
8
8
8 bits = 256 pages
Virtual Address with 256 (28)16-Mbyte pages
Figure 3: RC32364 Address Translation
(Courtesy IDT)
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The RC32364 interfaces to the system through a 32-bit multiplexed address/data bus. The bus
offers a rich set of signals to control transfers of which only a subset was required for this
MasterClock
Data Input
AD(31:0)
Data Input
Addr
Addr
Addr(3:2)
Width(1:0)
ALE
Rd*
Wr*
CIP*
DT/R*
I/D*
DataEn*
Ack*
Last*
Figure 4: RC32364 Read Timing
(Courtesy IDT)
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Crystal CS4343
Stereo DAC
The Digital-to-Analog Converter chosen for this design is the Crystal CS4343 from Cirrus
Logic. This device features:
• 1.8V to 3.3V operation.
• 24-bit conversion at up to 96 kHz.
• Digital volume control.
• Digital bass and treble boost.
• Built-in headphone amplifier capable of delivering 5 mW into a 16 Ω load.
Figure 5 shows the block diagram for this device.
The CS4343 provides three interfaces: the analog stereo headphone interface, the serial port
used to transfer digital audio data streams, and the control port used to configure the device.
DIF1/SDA
DIF0/SCL
VQ_HP
VA_HP
RST
VA
CONTROL PORT
VD_IO
ANALOG
VOLUME
CONTROL
∆Σ
DAC
ANALOG
FILTER
DIGITAL
VOLUME
CONTROL
BASS/TREBLE
BOOST
LRCK
HP
HP
HEAD-
PHONE
AMPLIFIER
DIGITAL
FILTERS
DE-
EMPHASIS
SERIAL
PORT
LK/DEM
ANALOG
VOLUME
CONTROL
COMPRESSION
LIMITING
∆Σ
DAC
ANALOG
FILTER
SDATA
GND
MCLK
FILT+
REF_GND
Figure 5: CS4343 Block Diagram
(Courtesy Cirrus Logic)
The control port is an industry standard I2C slave interface. I2C is a multidrop, 2-wire, serial
interface consisting of a clock (SCL) and data (SDA) and operating at up to 100 kHz. (See
Figure 7 Control Port Timing.) The control port is used to configure device features such as
volume, muting, equalization, power management, and the operating mode of the serial port.
operation can be found in the I2C specification as described in the references.
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RST
t
irs
Repeated
Start
Stop
Start
Stop
SDA
SCL
t
t
t
t
t
buf
t
high
hdst
f
susp
hdst
t
t
t
t
t
sust
sud
r
low
hdd
Figure 6: Control Port Timing
(Courtesy Cirrus Logic)
The serial port can be configured for several operating modes. The mode of operation chosen
for this application is referred to in the CS4343 documentation as "Serial Audio Format 2".
Figure 7 gives an overview of serial port timing when in this mode.
Right Channel
LRCK
SCLK
Left Channel
SDATA
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Figure 7: Serial Port Timing
(Courtesy Cirrus Logic)
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Samsung
FLASH Memory
The FLASH memory chosen for this design is the KM29U64000T 8M x 8 device from Samsung
Semiconductor. This device is based on NAND FLASH technology and is popular in MP3 player
applications due to its high density and low cost per bit.
Figure 8 shows the block diagram for this device. The complete data sheet for the
KM29U64000T can be found at the following URL:
Y-Gating
2nd half Page Register & S/A
X-Buffers
A9 - A22
Latches
& Decoders
64M + 2M Bit
NAND Flash
ARRAY
Y-Buffers
Latches
A0 - A7
& Decoders
(512 + 16)Byte x 16384
1st half Page Register & S/A
Y-Gating
A8
Command
Command
Register
VCCQ
VSS
I/O Buffers & Latches
Global Buffers
CE
RE
WE
Control Logic
& High Voltage
Generator
I/0 0
I/0 7
Output
Driver
CLE ALE WP
Figure 8: KM29U64000T Block Diagram
(Courtesy Samsung Semiconductor)
Unfortunately this device also has two characteristics that present significant system level
design challenges. The first of these is the narrow, highly multiplexed interface that is used to
access the device. The KM29U64000T interfaces to the system through an 8-bit wide port that
The second and most challenging issue relates to data integrity, which is an issue common to
most devices using NAND technology. There are two aspects to this, the first of which is the fact
that devices when shipped may have memory blocks that may not be used due to data errors.
The data sheet for the device has a parameter called NVB that is the number valid blocks that
the device contains. The value of NVB varies from device to device and is specified to have a
minimum of 1014, a maximum of 1024, and typically 1020. While the first block is guaranteed
to be good, bad blocks can occur at any other location within the memory array. Invalid blocks
are marked at the factory by storing a "0" value at location "0" in either the first or second block
of the page. The system level impact of this is that it must keep track of which blocks are good
within the device and that this results in a non-contiguous memory map.
The second issue is that while the device is guaranteed to provide at least the minimum number
of valid blocks over its operational lifetime these devices may experience failures in additional
blocks throughout their life. In order to ensure system integrity some form of error detection and
correction must be implemented.
The discussion of the FLASH memory interface will discuss how these issues were addressed
in this design.
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CLE
tCEH
CE
tCHZ
tWC
WE
tWB
tAR2
tCRY
ALE
RE
tRHZ
t
R
tRC
tRR
A
9
~ A 16
Dout N+3
Dout 527
RB
A
0
~ A
7
Dout N
Dout N+1
Dout N+2
00h or 01h
A17 ~ A 22
I/O
0
-
7
t
Column
Address
Page(Row)
Address
Busy
R/B
Figure 9: KM29U64000T Read Timing
(Courtesy Samsung Semiconductor)
Micron SDRAM
Memory
The SDRAM memory chosen for this design is the MT48LC1M16A1S - 512K x 16 x 2 bank
device from Micron Semiconductor. This device is available in speed grades from 125 to 166
sheet for the MT48LC1M16 can be found at the following URL:
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BANK0
MEMORY
ARRAY
ROW-
ADDRESS
LATCH
11
2,048
(2,048 x 256 x 16)
CKE
CLK
DQML,
DQMH
256 (x16)
CONTROL
LOGIC
CS#
WE#
CAS#
RAS#
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
DATA
OUTPUT
REGISTER
MODE REGISTER
12
256
16
DQ0-
DQ15
16
COLUMN
DECODER
8
8
16
DATA
INPUT
REGISTER
256
REFRESH
CONTROLLER
ADDRESS
REGISTER
A0-A10, BA
12
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
REFRESH
COUNTER
11
ROW-
ADDRESS
MUX
256 (x16)
11
BANK1
MEMORY
ARRAY
ROW-
ADDRESS
LATCH
11
2,048
(2,048 x 256 x 16)
Figure 10: MT48LC1M16A1 Block Diagram
(Courtesy of Micron Technology, Inc.)
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMS CMH
COMMAND
DQM3
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS CMH
t
t
AH
AS
COLUMN m
A0-A9
ROW
ROW
2
(A0 - A7)
t
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
ROW
A10
BA
t
AS
AH
BANK
BANK
BANK
t
t
t
AC
AC
AC
t
t
t
t
t
OH
AC
OH
OH
OH
DOUT
m
DOUT m + 1
DOUT m + 2
DOUT m + 3
DQ
t
LZ
t
HZ
t
t
RP
RCD
CAS Latency
t
t
RAS
RC
Figure 11: MT48LC1M16A1 Read Timing
(Courtesy of Micron Technology, Inc.)
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National
The USB interface in the design is based on a National Semiconductor USBN9602 controller.
This device, packaged in a 28-pin SOIC package, supports full speed USB function controller
operation and includes an integrated USB transceiver. It contains seven endpoint FIFOs, two of
which are 64 bytes deep.
Semiconductor
USBN9602 USB
Function
Figure 12 shows a block diagram of this device. The complete data sheet for the USBN9602
can be found at the following URL:
Controller
CS
RD
WR
A0/ALE
D[7:0]/AD[7:0]
INTR
MODE[1:0]
RESET
Vcc
Microcontroller Interface
GND
Endpoint/Control FIFOs
XIN
48 MHz
XOUT
Oscillator
Control
Status
RX
Clock
CLKOUT
TX
Generator
SIE
Clock
Media Access Controller (MAC)
Recovery
USB Event
Detect
Physical Layer Interface (PHY)
V3.3
Transceiver
VReg
AGND
D+
D-
Upstream Port
Figure 12: USBN9602 Block Diagram
(Courtesy National Semiconductor)
The system interface for the USBN9602 is a simple 8-bit microprocessor bus that can be
configured to operate in a multiplexed or non-multiplexed mode. The multiplexed mode is more
attractive from a software perspective since it supports random access to the devices’ internal
registers. This mode also reduces the number of interface pins required. For both of these
when operating in multiplexed mode.
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ALE
CS
RD or WR
AD[7:0]
ADDR
DATA
Figure 13: USBN9602 Read / Write Cycle Timing
(Courtesy National Semiconductor)
System
Implementation
This section describes how all of these pieces are integrated into a complete system. First
described is the software architecture and the functionality of the key modules. Next is the
architecture and implementation of the logic contained in the Spartan-II FPGA.
Software Architecture
components fall into four categories:
• RTOS. A Real Time Operating System is included in the software architecture in order to
simplify the management of resources and concurrent activities.
• BIOS. The Basic Input Output System functions provide low level device management
functions and hardware abstraction.
• Protocol Stacks. These modules implement the network protocol layers for the
communications interfaces.
• Management Processes. These modules implement the application levels functions, and
these run as processes under the RTOS.
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UI
Manager
RTOS
MP3
Decoder
Memory
Manager
Audio
ISR
IRDA
USB
Stack Stack
IR
USB Touch Screen Audio FLASH MMU
BIOS BIOS BIOS BIOS BIOS BIOS BIOS
System
Hardware
Figure 14: System Software Architecture
The RTOS provides process scheduling and memory allocation functions. The RTOS could be
any of the commercially available packages. Probably more of a factor than any technical issue
is the licensing model for the product. Since this is a product that is targeted at the high-volume,
cost sensitive, consumer market, an RTOS that is licensed on an up front fee basis with no unit
royalties is the most attractive.
The various BIOS components will be discussed later in the sections that describe the
hardware implementation for each interface. The key application modules are as follows:
UI Manager
The User Interface (UI) manager is responsible for handling interaction between the user and
the system. This includes using the Screen BIOS to create the buttons and menus that the user
sees, getting user input through the Touch BIOS and using this information to coordinate
activities such as downloading and playing MP3 files. The UI manager would also spawn
separate processes for value added features such as an appointment calendar, or a phone
book, as needed.
MP3 Decoder and Audio ISR
The MP3 decoder runs as an independent process, controlled by the UI manager. When
activated, it uses the FLASH BIOS to fetch MP3 file data, decompresses it and places the audio
data in a queue. The audio Interrupt Service Routine (ISR) is activated by an interrupt from the
Audio DAC block in the FPGA. When activated, it reads data from this queue and writes it to
FIFOs in the Audio DAC block.
The key to getting optimal performance from the MP3 decoder on the RC32364 lies in taking
advantage of the MAC instruction supported by the processor. The instruction is particularly
valuable in the implementation of the Discrete Cosine Transform (DCT) for sub-band synthesis.
There are several sources for MP3 decoder code. A fixed point decoder (splay-0.81-
fixpoint.tgz) that was developed for the Linux ARM project can be downloaded from the
following URL:
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The reference code that was developed for the standard is available from the Fraunhofer
Institute at the following URL:
A commercial decoder is available from Xaudio. Information on the Xaudio product line is
available from:
Memory Manager
The Memory Manager handles the tasks required to mask NAND FLASH issues from the other
software in the system. Specifically these tasks are block mapping and code initialization.
Block Mapping
This involves maintaining a table of valid FLASH blocks and configuring the MMU to map them
into a linear address space. For the FLASH memory space the TLB entries are set to the same
8 KB size to match the block size of the FLASH itself, and the entries are not locked in the TLB.
A single TLB entry is used to map the SDRAM memory space. This entry is configured to map
a 4 MB memory space and is locked in the TLB.
In the event that an error is detected in a valid block, this code is also responsible for copying
the data to an unused block and marking the block in which the error was detected as bad.
Code Initialization
This function copies the code image from FLASH to RAM at boot time. This routine must also
perform error detection on the image as it is copied. If an error is detected, error correction must
be performed and the block mapping code informed.
Xilinx
Spartan- II
FPGA
Figure 15 shows the architecture implemented in the Spartan-II device for this application. It
consists of eight major functional blocks:
• IP Bus Controller
• CPU Interface
• LCD Controller
• Memory Datapath
• SDRAM Controller
• FLASH Controller
• CompactFlash Controller
• IRDA Controller
• DAC Interface
• Touch Screen Interface
These blocks are interconnected by a simple non-multiplexed, multi-master, address data bus
that is referred to as the IP bus. While the IP bus may appear to be a bus to the function blocks,
it is not a bus at all but instead uses multiplexers for gating data into the internal datapaths. This
approach eliminates the need for 3-state drivers within the design. In this implementation the
block diagram of the FPGA.
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LCD Controller
D_IN[31:0]
LCD Control
Signals
A_OUT[31:2]
Control Out
MUX
MUX
DAC Interface
D_OUT[31:0]
D_IN[31:0]
DAC Interface
Signals
A_IN[3:2]
Control In
CPU Interface
D_OUT[31:0]
Touch Screen
Interface
CPU Address/Data
D_IN[31:0]
CPU Control
A_OUT[31:2]
D_OUT[31:0]
D_IN[31:0]
USB Control
Control Out
ADC Interface
Signals
A_IN[3:2]
Control In
IRDA Controller
D_OUT[31:0]
Memory Interface
D_OUT[31:0]
D_IN[31:0]
D_IN[31:0]
Memory Data
Tranceiver Interface
A_IN[3:2]
Control In
A_IN[19:0]
Control In
Signals
Memory Address
SDRAM Controller
Control In
SDRAM Control
Signals
MUX
FLASH Controller
Control In
FLASH Control
Signals
CompactFlash
Controller
CompactFlash
Control
Control In
Signals
Figure 15: FPGA Logic Block Diagram
While most of the blocks are fairly independent, the FLASH, SDRAM, and CompactFlash
interfaces share common address and data busses. While this results in a fairly complex
muxing scheme for these datapaths it is necessary to keep the pin count within an acceptable
range.
The following sections will discuss the implementation of each of these functional blocks and
outline the hardware and software resources needed to support each.
IP Bus Controller
The IP Bus Controller block performs two functions: block address decoding and IP bus
arbitration.
The address decode block generates device selects for the IP block that is the target of the
transfer. It also controls the multiplexers that select the response signals from the target of the
transfer (ACK, DOUT, etc.).
IP bus arbitration between access requests from the CPU Interface and the LCD Controller are
handled by using a simple rotating priority scheme. The arbiter block also controls the
multiplexers that select which set of transfer control signals (RD, WR, etc.) control the transfer.
The FPGA device resources used to implement this block include an estimated 32 CLBs but no
I/O pads. There is no software required to support this block.
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CPU Interface
The CPU Interface block performs three functions: protocol conversion, CPU initialization and
CPU
Initialization
IR_INT_N
DAC_INT_N
CPU_COLDRESET_N
CPU_RESET_N
CPU_BUSGNT_N
CPU_INT_N[3:0]
SYS_CLK
DIN[31:0]
CPU_AD[31:0]
DOUT[31:0]
AOUT[31:4]
Latch
28
28
2
D
Q
CPU_ALE
Enable
CPU_ADDR[3:2]
AOUT[3:2]
CPU_MASTERCLK
Bus State
Machine
CPU_CIP_N
CPU_BE_N[3:0]
CPU_RD_N
CPU_WR_N
CPU_ACK_N
SYS_CLK
RD_OUT_N
WR_OUT_N[3:0]
ACK_IN
REQ_OUT
GNT_IN
USB_CS_N
USB_RD_N
USB_WR_N
Figure 16: CPU Interface Block Diagram
The CPU initialization block generates the required timing for the reset signals and drives
configuration information onto bus grant and the interrupts. This configuration information
configures the boot PROM width and enables the CPU timer. After initialization is complete the
block drives the IRDA and audio DAC interrupts out onto the CPU interrupt signals.
The bus state machine converts the signaling on the CPU bus into the format used on the local
IP bus, or if the transaction is to the USB interface, the signaling accepted by the USBN9602.
The FPGA device resources used to implement this block include an estimated 46 CLBs and
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Table 1: CPU Interface Signal Summary
Signal
Type
Description
CPU_MASTERCLK
Output All bus timing is relative to this clock. The CPU core frequency is derived by
multiplying this clock.
CPU_AD[31:0]
I/O
High-order multiplexed address and data bits.
CPU_ADDR[3:2]
Input
Non-multiplexed address lines. These serve as the word within block address for
cache refills (Addr[3:2]).
CPU_BE_N[3:0]
CPU_ALE
Input
Input
Input
Indicates which byte lanes are expected to participate in the transfer.
Address latch enable.
CPU_CIP_N
Denotes that a cycle is in progress. Asserted in the address phase and is asserted
until the ACK* for the last data is sampled.
CPU_RD_N
Input
Input
This active Low signal indicates that the current transaction is a read.
This active Low signal indicates that the current cycle transaction is a write.
CPU_WR_N
CPU_BUSGNT_N
Output During the power-on reset (Cold Reset), BusGnt* is an input and is used to load
ModeBit(5).
CPU_ACK_N
Output On read transactions, this signals the RC32364 that the memory system has placed
valid data on the A/D bus, and that the processor may move the data into the on-
chip Read Buffer. On a write transaction, this signals to the RC32364 that the
memory system has accepted the data on the A/D bus.
CPU_RESET_N
Output This active Low signal is used for both power-on and warm reset.
Output This active Low signal is used for power-on reset.
CPU_COLDRESET_N
CPU_INT_N[3:0]
Output Active Low interrupt signals to the CPU. During power-on, Int*(3:0)serves as
ModeBit(9:6).
US_CS_N
US_RD_N
US_WR_N
Output USB controller chip select.
Output USB controller read strobe.
Output USB controller write strobe.
There is no direct software support required for this block, but the USB interface itself requires
considerable software for operation. This software consists of the USB protocol stack, which
includes a USB interrupt service routine. The USB stack itself consists of two parts. The first of
these is the software required for participating in the USB protocol and the plug and play. The
second part is the application specific code required to transfers MP3 files from the host system
to the player.
LCD Controller
The LCD Controller is responsible for refreshing the screen with an image stored in the
SDRAM. In general its operation is similar to that of a CRT display controller. Unlike most
display controllers, the display format generated by the LCD controllers is not programmable by
the CPU. The raster format is fixed at 128 x 128 pixels and the display timing is fixed as well.
This makes sense in an embedded system such as this where the display is integrated into the
unit. Although the display format cannot be changed in the system, loading different FPGA
configurations into the FLASH when the unit is manufactured can accommodate different
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Shift
Register
FIFO
32
4
32
DI_D[3:0]
DIN[31:0]
D
Q
D
Q
Enable
Load
Wr Rd
State
Machine
SYS_CLK
DI_XSCL
DI_LP
BREQ_N
BGNT_N
RD_N
DI_FR
DI_YD
ACK_N
DI_YSCL
Address
Counter
9
9
AOUT[10:2]
Q
D
Enable
Load
21
Base
Address
AOUT[31:11]
Figure 17: LCD Controller Block Diagram
The LCD Controller is an IP bus master and fetches data for screen refresh independently of
CPU activities. The display data that is fetched is loaded into a FIFO using a block transfer
across the IP bus. The shift register loads display data from the FIFO and shifts it out as a 4-bit
wide data stream at 16 MHz the maximum shift rate supported by the display drivers.
In order to prevent disruption of the display image, the FIFO must have a new data word
available for the shift register every time it empties. This occurs every 500 ns (1 / [16 MHz / 8]).
Since there is a significant amount of overhead associated with each non-sequential access to
the SDRAM memory, fetches are made from it using multi-word bursts. The size of these bursts
is a compromise between different factors. Longer bursts are more efficient since the SDRAM
access overhead is amortized over a larger number of data words. Smaller bursts reduce the
size of the FIFO and also reduce bus latency by reducing the time that the LCD controller ties
up the IP bus. For this application a 2-word burst was chosen. The result is a 3-word deep FIFO
and display buffer fetches every 1 µs.
The FPGA device resources used to implement this block include an estimated 58 CLBs and
Table 2: LCD Controller Interface Signal Summary
Signal
DI_XD[3:0]
DI_XSCL
DI_LP
Type
Description
X driver data
Output
Output
Output
Output
Output
Output
X driver data shift clock
Latch pulse
DI_FR
Frame signal
DI_YD
Y driver scan start pulse
Y driver shift clock
DI_YSCL
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The only software support required for this block is the screen BIOS which consists of functions
to generate screen images by manipulating the frame buffer memory. This buffer appears as an
array of 512, 32-bit words with each word containing 32 pixels of the screen image. The most
significant bit of the word at the base address appears as the pixel in the upper left-hand corner
of the screen. The least significant bit of that memory word appears as the 32nd pixel in the first
row. The word and bit address of any pixel on the screen can be calculated using the following
formula:
Memory Address
Bit Address
= X * Y MOD 32
= X * Y REM 32
Where:
X and Y are the horizontal and vertical coordinates of the screen and
assume that the origin (X = 0, Y = 0) is in the upper left-hand corner of the screen.
MOD the integer division.
REM is the remainder of the division
Memory Interface
16-bit memory devices to the 32-bit IP bus. While the RC32364 is capable of fetching instruc-
tions and data from devices with varying bus widths, having the FPGA build 32-bit words for the
CPU reduces the number of bus cycles. This increases performance and also reduces power
A_IN[19:9]
A_IN[8:1]
MUX
MUX
MUX
MEM_ADDR[10:0]
A_IN[10:0]
MEM_DOUT[15:8]
MEM_DOUT[7:0]
D_IN[31:24]
D_IN[23:16]
D_IN[15:8]
D_IN[7:0]
Register
MEM_DIN[15:8]
D_OUT[31:24]
D_OUT[23:16]
MEM_D[15:0]
Q
D
MUX
Register
Q
D
Register
Q
D
D_OUT[15:8]
D_OUT[7:0]
MUX
MEM_DIN[7:0]
Figure 18: Memory Interface Block Diagram
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SDRAM Controller
application note XAPP134: Virtex Synthesizable High Performance SDRAM Controller. The
changes made in the original design are to adapt to the differences in the host interface. In the
original design the host interface is a multiplexed address data bus. In this application the IP
bus is non-multiplexed. Another difference is that the original design supported a 32-bit wide
memory configuration with two MT48LC1M16 memory devices. In the design a 16-bit wide
memory datapath and a single MT48LC1M16 is used.
sdrm_t.v from XAPP 134
SYS_CLK
State
Machine
State
Machine
SD_BA
SA_CS
SD_CLK
SD_CKE
SD_RAS
SD_CAS
SD_WE
SD_DQML
SDRAM_SEL_N
ACK_N
WR_IN_N[3:0]
Refresh
Counter
32
RD_IN_N
Figure 19: Figure 19 SDRAM Controller Block Diagram
The estimated FPGA device resources used to implement this block include an estimated 100
software support required for this block.
Table 3: SDRAM Controller Interface Signal Summary
Signal
SD_BA
Type
Description
Bank address
Output
Output
Output
Output
Output
Output
Output
Output
Output
SD_CS
Chip select
SD_CLK
SD_CKE
SD_RAS
SD_CAS
SD_WE
Transfer clock
Clock enable
Row address strobe
Column address strobe
Write enable
SD_DQML
SD_DQMH
Lower byte data mask
Higher byte data mask
FLASH Controller
The largest cost associated with this design is the large amount of FLASH memory, 32 MB or
more, that is required for storing MP3 audio files. In order to leverage this cost it is desirable to
use this memory for all non-volatile storage requirements within the system. This includes code
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Device decodes
FL_CE_N[3:0]
from
IP Bus Controller
State
Machine
FL_ALE
SYS_CLK
FLASH_SEL_N
ACK_N
FL_WE_N
FL_RE_N
FL_SE_N
FL_WP_N
FL_R/B_N
WR_IN_N[3:0]
RD_IN_N
Figure 20: FLASH Controller Block Diagram
When the architecture for this system was being planned, one issue that needed to be
addressed was whether to execute the program image directly from FLASH or to copy it to
SDRAM. There were two key issues that needed to be considered when making this decision.
Performance
The narrow, 8-bit, interface used for both address and data is one performance issue, but it is
not the biggest. The real problem is random access latency. Within a 512-byte memory page,
data can be read with a 50 ns read cycle time. The problem comes when the processor
accesses data on a different page. The time required to load a page into the page register,
where it can be accessed, is 7 µs. With a 66 MHz processor frequency this represents 462
instruction times. This latency will adversely effect real-time performance.
Error Handling
Each 512-byte page in the FLASH has 16 bytes of spare storage for storing ECC information.
The problem is that this is not enough storage for implementing ECC for small block sizes. For
example, to correct single bit errors on an RC32364 cache line (16 bytes) using a Hamming
code the following relationship must be satisfied:
N ≤ 2**K – K – 1
where: N is the number of data bits in the block
K is the number of ECC bits
Solving for K:
16 * 8 = 256 ≤ 2K – K – 1
K = 9 ECC bits per cache line
Since there are 32 (512/16) cache lines per page, a total of 36 bytes are needed for ECC
storage. Recall that 16 bytes are available.
In order to get around this problem, the block size could be increased to 32 bytes. At 32 bytes,
ten bits of ECC are required per block, but there are now only 16 blocks per page which is
consistent with the available ECC memory per page. Performing the block check over two
cache lines could accommodate this larger block size. The down side to this is that every time
a cache line is loaded, two would have to be checked with a corresponding increase in memory
latency.
As a result of this the decision was made to copy the executable image to the SDRAM memory
at boot time. This not only increases performance but also turns the ECC checking issue into a
non real-time software exercise.
The estimated FPGA device resources used to implement this block include an estimated 100
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Table 4: FLASH Controller Interface Signal Summary
Signal
FL_CE_N[3:0]
FL_ALE
Type
Description
Output Device chip enables, active Low.
Output Address latch enable.
FL_WE_N
FL_RE_N
FL_SE_N
Output Write enable, write data is latched on the rising edge.
Output Read enable, when Low enables device data output buffers.
Output Enable spare area when Low.
FL_WP_N
FL_R/B_N
Output Write protect, active Low.
Input
Open drain output from devices, pulled Low when a program,
erase, or read operation is in progress.
Software support required for this block consists of the FLASH BIOS which implements low
level primitives for programming, erasing, and checking validity of memory blocks.
IRDA Controller
The IRDA controller is essentially a specialized, fixed function UART. The separate, 2-word,
transmit and receive FIFOs reduce the interrupt overhead associated with data transmission.
At the maximum data rate that the IR transceiver can support (115 kb/s) the CPU will get an
.
Tx State
Machine
Shift
Register
FIFO
IR_TXD
32
MUX
32
D_IN[31:0]
D
Q
D
Q
Bus State
Machine
SYS_CLK
INT_N
RD_IN_N
WR_IN_N[3:0]
ACK_N
Shift
Register
FIFO
32
32
D_OUT[31:0]
IR_RXD
Q
D
Q
D
Rx State
Machine
Figure 21: IRDA Controller Block Diagram
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Table 5: Table 5 IRDA Transceiver Interface Signal Summary
Signal
IR_TXD
Type
Output
Input
Description
Transmit data
Receive data
IR_RXD
IR_SD
Output
Shut down signal, puts transceiver into low power mode
Audio DAC Interface
The interface for the CS4343 consists of two separate functional blocks, one for each of the
this interface.
Shift
Register
FIFO
32
32
32
D
Q
D
Q
D_IN[31:0]
DAC_SDATA
MUX
Shift
Register
FIFO
32
D
Q
D
Q
State
Machine
SYS_CLK
INT_N
DAC_MCLK
DAC_LRCK
RD_N
WR_N
ACK_N
Register
DAC_SCL
DAC_SDA
32
32
2
D_IN[31:0]
D
Q
D_OUT[31:0]
Figure 22: Audio DAC Interface Block Diagram
The control port interface is implemented as a 2-bit I/O port that is manipulated by software in
order to implement the I2C protocol used for accessing the control and status registers in the
DAC. This approach uses minimal device resources and is practical due to the low data rate of
this port and its infrequent use.
When the system is in operation, the serial audio port is in use most of the time. Therefore,
dedicated hardware is provided for implementing the transfer protocol and for delivering an
uninterrupted audio stream. This hardware consists of two, 4-word FIFOs, one for each audio
channel and a state machine to manage the FIFOs and sequence the interface signals.
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Like the IRDA controller, an interrupt is generated every time the FIFOs transfer their last word
into the shift registers. Assuming a 48 kHz audio sampling rate, this will result in an interrupt
every 83.3 µs. To put this in perspective, this means that the CPU will get an interrupt every
5,333 instructions.
Table 6: Audio DAC Interface Signal Summary
Signal
Type
Description
DAC_MCLK
DAC_LRCK
Output Master clock
Output Left / Right clock, determines which channel is currently being
transferred
DAC_SDATA
DAC_SCL
DAC_SDA
Output Serial audio data
Output I2C data clock
I/O
I2C data
Touch Screen Interface
The touch screen interface is an I/O port that lets the processor read the data returned by a
two-channel analog-to-digital converter. This lets the system software read the X and Y
coordinate resistance values that result from the user touching the screen. The system
Register
AD_SCK
32
32
3
D_IN[31:0]
AD_SDI
D
Q
AD_SDO
D_OUT[31:0]
Figure 23: Touch Interface Block Diagram
Table 7: Touch Screen Interface Signal Summary
Signal
AD_SCK
AD_SDI
Type
Output
Input
Description
Serial data clock
Serial data in
AD_SDO
Output
Serial data out
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Spartan Device
Selection
Spartan devices are available in a range of densities and packages. The following criteria were
used to select the device used in this application:
• I/O Pins. The design requires a total of 137 I/O pins. I/O pin requirements per block are
• Voltage. The design operates at 3.3V.
• Density. The estimated size of the design is 83,000 gates, with the usage broken out in
• Performance. The highest clock speed used in the device is 64 MHz, used to clock the
SDRAM controller state machines. The remaining logic runs at sub multiples of this clock
rate.
• Packaging. The size constraints imposed on most modem designs dictates a high-density
surface mount package.
Based on these criteria the device selected for this design is the XC2S100. This device offers
100K gates density, 3.3V operation, 176 user I/O, and is packaged in a space saving FG256
BGA package.
Table 8: FPGA Resource Usage Summary
Interface
CLB Usage Number of Signals
CPU
25
58
51
9
LCD Display
IRDA
59
3
USB
21
3
DAC
23
5
ADC
0
3
SDRAM
100
100
100
4
9
FLASH
10
17
11
16
137
CompactFlash
Memory Address Bus
Memory Data Bus
Total:
10
500
Conclusion
The design that has been outlined meets both original design objectives. Even with budgetary
system. The design also has enough spare resources both in terms of CPU cycles and FPGA
gates to support field upgrades. Operating at a core clock speed of 64 MHz, the RC32364 will
provide enough performance for both audio decoding and user interface functions. By locking
the audio decode functions in the instruction cache a significant increase in system
performance as well as reduced power consumption is achieved.
This design also illustrates how manufacturers can create designs that the optimized
integration of an ASIC while supporting the manufacturing and field upgrade flexibility of an
FPGA.
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Table 9: NG Player Semiconductor BOM
Part
Unit
Ext.
Item
Qty.
Mfg.
Number
Description
Flash, 64Mb
Volume
1M/Yr.
Cost
Cost.
1
2
4
Samsung
Micron
KM29U6400T
$10.00 $40.00
$3.50 $3.50
1
Mt48C1LC1M16A1TG7SIT SDRAM,
512K x 16 x 2 banks
200K/m
3
4
5
1
1
1
IDT
RC32364-133
XC2S100
XC1801
RISC CPU
100K
$11.50 $11.50
$10.00 $10.00
Xilinx
Xilinx
FPGA
20K/m
20K/m
Serial Configuration
PROM
$3.00
$3.00
6
7
1
1
NSC
USB9602
USB Interface Controller
20K/m
20K/m
$1.63
$2.50
$1.63
$2.50
SMOS
SED1758T0A
LCD Common Driver,
160 Rows
8
9
1
1
SMOS
SED1743T0A
TBD
LCD Segment Driver,
160 Columns
20K/m
est.
$2.50
$5.00
$2.50
$5.00
Various
160 x 160 LCD Panel,
Glass Only
10
11
12
13
14
1
1
1
1
1
MicroTouch
Infineon
Crystal
TBD
Touch Screen
est.
$5.00
$2.00
$2.00
$2.68
$2.81
$5.00
$2.00
$2.00
$2.68
$2.81
IRDT6100
CS4343
1Mb IRDA Transceiver
DAC Stereo Audio
AD Converter
20K/m
est
Maxim
MAX1108
MAX1705
disti
10K
Maxim
Step-up DC to DC
Converter
Notes: BOM includes only semiconductor content.
Total:
$94.12
References
RC32364 RISController, Hardware User’s Manual, April 1999, Integrated Device Technology
Xilinx Spartan-II FPGA Data Sheet, January 2000, Xilinx
IRMS6100 1.15 Mb/s IrDT Data Transceiver Data Sheet, May 1999, Infineon Technologies
SED1743 160-bit LCD Common Driver Data Sheet, Epson Electronics
SED1758 160-bit LCD Segment Driver Data Sheet, Epson Electronics
CS4343 Low Voltage, Stereo DAC with Headphone Amp Data Sheet, June 1999, Cirrus Logic
MAX1108 2-Channel, Serial 8-bit ADC, Data Sheet, October 1998, Maxim Integrated Products
USBN9602 Full Speed Function Controller With DMA Support Data Sheet, May 1998, National
Semiconductor
MT48LC1M16A1 S - 512K x 16 x 2 banks Synchronous DRAM Data Sheet, August 1999, Micron
Technologies
KM29U64000T 8M x 8 bit NAND Flash Memory, April 1999, Samsung Semiconductor
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Revision
History
Date
Version #
Revision
11/24/99
1.0
Initial release.
© 1999 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaim-
ers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are
the property of their respective owners.
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