TS2GSD1
33
Secure Digital Card
Description
Features
Secure Digital Card of high capacity but economic
cost. It is specifically designed to meet the security,
capacity and small form factor requirements in newly
emerging audio and video consumer electronic
devices.Transcend Secure Digital Card can lead you
to a colorful digital world.
• ROHS compliant product
• Operating Voltage: 2.7 ~ 3.6V
• Operating Temperature: -25 ~ 85°C
• Insertion/removal durability: 10,000 cycles
• Fully compatible with SD card spec. v1.1
• Mechanical Write Protection Switch
• Forward compatibility to MultiMediaCard Version 2.11
• Supports Copy Protection for Recorded Media(CPRM) for
music and other commercial media
Placement
• Form Factor: 24mm x 32mm x 2.1mm
Front
Back
Pin Definition
SD Mode
Description
SPI Mode
Pin No.
Name Type
Name Type
Description
Chip Select (neg true)
Data In
I/O/PP3
CS
DI
I
1
2
3
4
5
6
7
8
9
CD/DAT
CMD
VSS1
Card Detect/Data Line [Bit3]
Command/Response
Supply voltage ground
Supply voltage
PP
S
S
I
I
Supply voltage ground
Supply voltage
Clock
VSS
VDD
SCLK
VSS2
DO
S
VDD
S
CLK
Clock
I
S
VSS2
S
Supply voltage ground
Supply voltage ground
Data Out
DAT0 I/O/PP Data Line [Bit0]
DAT1 I/O/PP Data Line [Bit1]
O/PP
RSV
RSV
I/O/PP Data Line [Bit2]
DAT2
1
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TS2GSD1
33
Secure Digital Card
Bus Operating Conditions
• General
Parameter
Peak voltage on all lines
All Inputs
Symbol
Min.
-0.3
Max.
Unit
V
Remark
VDD+0.3
Input Leakage Current
All Outputs
-10
-10
10
10
µA
µA
Output Leakage Current
• Power Supply Voltage
Parameter
Symbol
VDD
Min.
2.0
Max.
3.6
Unit
V
Remark
CMD0, 15,55,ACMD41
commands
Supply voltage
Supply voltage specified in OCR register
2.7
3.6
V
Except CMD0, 15,55,
ACMD41 commands
Supply voltage differentials (VSS1, VSS2
)
-0.3
0.3
V
Power up time
250
ms
From 0v to VDD Min.
Note. The current consumption of any card during the power-up procedure must not exceed 10 mA.
• Bus Signal Line Load
The total capacitance CL the CLK line of the SD Memory Card bus is the sum of the bus master capacitance CHOST, the bus
capacitance CBUS itself and the capacitance CCARD of each card connected to this line:
CL = CHOST + CBUS + Ν*CCARD
Where N is the number of connected cards. Requiring the sum of the host and bus capacitances not to exceed 30 pF for
up to 10 cards, and 40 pF for up to 30 cards, the following values must not be exceeded:
Parameter
Bus signal line capacitance
Single card capacitance
Symbol
CL
Min.
10
Max.
100
10
Unit
pF
Remark
fPP ≤ 20 MHz, 7 cards
CCARD
pF
Maximum signal line inductance
Pull-up resistance inside card (pin1)
16
nH
kΩ
fPP ≤ 20 MHz
RDAT3
90
May be used for card
detection
Note that the total capacitance of CMD and DAT lines will be consist of CHOST, CBUS and one CCARD only since they are
connected separately to the SD Memory Card host.
Parameter
Pull-up resistance
Symbol
RCMD, RDAT
CL
Min.
10
Max.
100
Unit
kΩ
Remark
To prevent bus floating
fPP ≤ 5 MHz, 21 cards
Bus signal line capacitance
250
pF
3
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TS2GSD1
33
Secure Digital Card
• Bus Signal Levels
As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage.
To meet the requirements of the JEDEC specification JESD8-1A, the card input and output voltages shall be within the
following specified ranges for any VDD of the allowed voltage range:
Parameter
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Symbol
VOH
Min.
Max.
Unit
V
Remark
0.75* VDD
IOH = -100 μA @VDD min
IOL = -100 μA @VDD min
VOL
0.125* VDD
VDD + 0.3
0.25* VDD
V
VIH
0.625* VDD
V
VIL
VSS – 0.3
V
4
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TS2GSD1
33
Secure Digital Card
• Bus Timing
Parameter
Symbol
Min
Max.
Unit
Remark
Clock CLK (All values are referred to min (VIH) and max (VIL)
Clock frequency Data Transfer Mode
Clock frequency Identification Mode
(The low freq. is required for MultiMediaCard
compatibility.)
fPP
fOD
0
0
25
MHz CL ≤ 100 pF, (7 cards)
400
KHz CL ≤ 250 pF, (21 cards)
Clock low time
tWL
tWH
tTLH
10
50
10
50
ns
ns
ns
ns
ns
ns
CL ≤ 100 pF, (7 cards)
CL ≤ 250 pF, (21 cards)
CL ≤ 100 pF, (7 cards)
CL ≤ 250 pF, (21 cards)
CL ≤ 100 pF, (7 cards)
CL ≤ 250 pF, (21 cards)
Clock high time
Clock rise time
10
50
5
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TS2GSD1
33
Secure Digital Card
Clock fall time
tTHL
10
50
ns
ns
CL ≤ 100 pF, (7 cards)
CL ≤ 250 pF, (21 cards)
Inputs CMD, DAT (referenced to CLK)
Input set-up time
tISU
tIH
5
5
ns
ns
CL ≤ 25 pF, (1 cards)
Input hold time
CL ≤ 25 pF, (1 cards)
Outputs CMD, DAT (referenced to CLK)
Output Delay time
tODLY
0
14
ns
CL ≤ 25 pF, (1 cards)
6
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TS2GSD1
33
Secure Digital Card
Reliability and Durability
Temperature
Operation: -25°C / 85°C (Target spec)
Storage: -40°C (168h) / 85°C (500h)
Junction temperature: max. 95°C
Operation: 25°C / 95% rel. humidity
Storage: 40°C / 93% rel. hum./500h
Moisture and corrosion
Salt Water Spray: 3% NaCl/35C; 24h acc. MIL STD Method 1009
10.000 mating cycles; test procedure: tbd.
10N
Durability
Bending
Torque
0.15N.m or +/-2.5 deg
Drop test
1.5m free fall
UV light exposure
Visual inspection
Shape and form
UV: 254nm, 15Ws/cm² according to ISO 7816-1
No warp page; no mold skin; complete form; no cavities surface smoothness <=
-0.1 mm/cm² within contour; no cracks; no pollution (fat, oil dust, etc.)
Minimum moving force of WP witch 40gf (Ensures that the WP switch will not slide while it is inserted to the connector.)
WP Switch cycles minimum 1000 Cycles(@Slide force 0.4N to 5N)
Above technical information is based on industry standard data and tested to be reliable. However, Transcend makes no
warranty, either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product.
Transcend reserves the right to make changes in specifications at any time without prior notice.
7
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