TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Single-Chip 100-/1000-Mbit/s Device
Port Trunking/Load Sharing for
High-Bandwidth Interswitch Links
Integrated Physical Coding Sublayer (PCS)
Logic Provides Direct Interface to Gigabit
Transceivers
Supports Pretag Extended Port Awareness
EEPROM Interface for Autoconfiguration
(No CPU Required for Nonmanaged Switch)
Integrated Address-Lookup Engine and
Table Memory for 2-K Addresses
Provides Direct Input/Output (DIO) Interface
for Configuration and Statistics Information
Supports IEEE Std 802.1Q Virtual-LAN
(VLAN) Tagging Scheme
Supports On-Chip Per-Port Storage for
Etherstat and Remote Monitoring (RMON)
Management Information Bases (MIBs)
Provides Data Path for Network
Management Information [No External
Media-Access Control (MAC) Required]
Fabricated in 2.5-/3.3-V Low-Voltage
Technology
Full-Duplex IEEE Std 802.3 Flow Control
Half-Duplex Back-Pressure Flow Control
Supports Ring-Cascade Mode
Supports Spanning Tree
Fully Nonblocking Architecture Using
High-Bandwidth Rambus Memory
Packaged in 352-Terminal Ball Grid Array
Package
Simple Expansion Via the Gigabit Interface
for Higher-Density Port Solutions
description
The TNETX4090 is a 9-port 100-/1000-Mbit/s nonblocking Ethernet switch with an on-chip address-lookup
engine. The TNETX4090 provides a low-cost, high-performance switch solution. The TNETX4090 is a fully
manageable desktop switch solution achieved by combining the TNETX4090 with physical interfaces and
high-bandwidthrambus-basedpacketmemoryandaCPU. TheTNETX4090alsoprovidesaninterfacecapable
of receiving and transmitting simple-network management protocol (SNMP) and bridge protocol data units
(BPDU) (spanning tree) frames.
The TNETX4090 provides eight 10-/100-Mbit/s interfaces and one 100-/1000-Mbit/s interface. In half-duplex
mode, all ports support back-pressure flow control to reduce the risk of data loss for a long burst of activity. In
the full-duplex mode of operation, the device uses IEEE Std 802.3 frame-based flow control. With full-duplex
capability, ports0–7support200-Mbit/saggregatebandwidthconnections. Port8supports2Gbit/stodesktops,
high-speed servers, hubs, or other switches in the full-duplex mode. The physical coding sublayer (PCS)
function is integrated on chip to provide a direct 10-bit interface to the gigabit Ethernet transceiver. The
TNETX4090 also supports port trunking/load sharing on the 10-/100-Mbit ports. This can be used to group ports
on interswitch links to increase the effective bandwidth between the systems. In the ring-cascade mode, port 8
can be used to connect multiple devices in a ring topology, which provides a low-cost, high-port-density desktop
switch. Pretagging and extended port awareness allow the TNETX4090 to be used as a front end to a router
or crossbar switch to build a cost-effective, high-density, high-performance system.
The internal address-lookup engine (IALE) supports up to 2-K unicast/multicast and broadcast addresses and
up to 64 IEEE Std 802.1Q VLANs. For interoperability, each port can be programmed as an access port or
non-access port to recognize VLAN tags and transmit frames with VLAN tags to other systems that support
VLAN tagging. The IALE performs destination- and source-address comparisons and forwards unknown
source- and destination-address packets to ports specified via programmable masks.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI, ThunderSWITCH, and ThunderSWITCH II are trademarks of Texas Instruments Incorporated.
Ethernet and Etherstat are trademarks of Xerox Corporation.
Secure Fast Switching is a trademark of Cabletron Systems, Inc.
Port-trunking and load-sharing algorithms were contributed by Cabletron Systems, Inc. and are derived from, and compatible with, Secure Fast
Switching .
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PCS Duplex LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
RDRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
HIGHZ Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
RACBIST Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Frame Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
VLAN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Address Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Port Trunking/Load Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Port-Trunking Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Extended Port Awareness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Other Flow-Control Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . 57
System Test Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
RDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Writing RDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Reading RDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Internal Wrap Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Duplex Wrap Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . 60
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Physical Medium Attachment Interface (Port 8) . . . . . . . . . . . . 62
Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
GMII (Port 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
MII (Ports 0–8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
RDRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . 73
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DIO Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Receiving/Transmitting Management Frames . . . . . . . . . . . 27
State of DIO Signal Terminals During Hardware Reset . . . 28
IEEE Std 802.1Q VLAN Tags on the NM Port . . . . . . . . . . . 28
Frame Format on the NM Port . . . . . . . . . . . . . . . . . . . . . . . . 28
Full-Duplex NM Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
NM Bandwidth and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PHY Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Receive Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Giant (Long) Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Short Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Receive Filtering of Frames . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Transmit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Adaptive Performance Optimization (APO) . . . . . . . . . . . . . 33
Interframe Gap Enforcement . . . . . . . . . . . . . . . . . . . . . . . . . 33
Backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Receive Versus Transmit Priority . . . . . . . . . . . . . . . . . . . . . 33
10-/100-Mbit/s MII (ports 0–7) . . . . . . . . . . . . . . . . . . . . . . . . 34
Speed, Duplex, and Flow-Control Negotiation . . . . . . . . . . 34
100-/1000-Mbit/s PHY Interface (Port 8) . . . . . . . . . . . . . . . . . 36
Speed, Duplex, and Flow-Control Negotiation . . . . . . . . . . 36
Full-Duplex Hardware Flow Control . . . . . . . . . . . . . . . . . . . 37
Pretagging and Extended Port Awareness . . . . . . . . . . . . . 38
Ring-Cascade Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Interaction of EEPROM Load With the SIO Register . . . . . 43
Summary of EEPROM Load Outcomes . . . . . . . . . . . . . . . . 43
Compatibility With Future Device Revisions . . . . . . . . . . . . 44
LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Lamp Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Multi-LED Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
GGP PACKAGE
(BOTTOM VIEW)
26 25 24 23 22 21 20 19 18 17 16 15 14 1312 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
4
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Table 1. Signal-to-Ball Mapping (Signal Names Sorted Alphabetically)
SIGNAL
NAME
BALL
NO.
SIGNAL
NAME
BALL
NO.
SIGNAL
NAME
BALL
NO.
SIGNAL
NAME
BALL
NO.
SIGNAL
NAME
BALL
NO.
Y26
AC26
AA24
AB26
Y24
V24
U25
U26
T26
AF26
U24
AE18
AD19
AE19
C21
B21
B19
A21
C26
A20
B20
C20
D20
D19
C19
B23
A23
A22
B22
C22
D22
D21
D16
C16
B14
B16
D26
A15
B15
C15
D15
A16
C14
C17
A19
A18
B18
C18
B17
A17
C11
B11
A9
B6
A4
C6
C1
A5
B5
C5
D5
C4
B4
A8
A7
B7
C7
D7
B8
C8
H2
H1
L3
Y3
Y4
W1
AA2
T1
U1
U2
U3
U4
K25
K24
A3
A24
C23
D2
D3
D6
D24
D25
E1
DBUS_CTL
DBUS_DATA0
DBUS_DATA1
DBUS_DATA2
DBUS_DATA3
DBUS_DATA4
DBUS_DATA5
DBUS_DATA6
DBUS_DATA7
DBUS_DATA8
DBUS_EN
DCCTRL
DRX_CLK
DTX_CLK
DVREF
ECLK
EDIO
FLOW
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDa
L08_DPLX
LED_CLK
LED_DATA
M00-COL
M03_CRS
M06_RXD2
M06_RXD3
M06_RXDV
M06_RXER
M06_TCLK
M06_TXD0
M06_TXD1
M06_TXD2
M06_TXD3
M06_TXEN
M06_TXER
M07_COL
MDIO
M03_LINK
M03_RCLK
M03_RENEG
M03_RXD0
M03_RXD1
M03_RXD2
M03_RXD3
M03_RXDV
M03_RXER
M03_TCLK
M03_TXD0
M03_TXD1
M03_TXD2
M03_TXD3
M03_TXEN
M03_TXER
M04_COL
MRESET
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
M00_CRS
M00_LINK
M00_RCLK
M00_RENEG
M00_RXD0
M00_RXD1
M00_RXD2
M00_RXD3
M00_RXDV
M00_RXER
M00_TCLK
M00_TXD0
M00_TXD1
M00_TXD2
M00_TXD3
M00_TXEN
M00_TXER
M01_COL
M01_CRS
M01_LINK
M01_RCLK
M01_RENEG
M01_RXD0
M01_RXD1
M01_RXD2
M01_RXD3
M01_RXDV
M01_RXER
M01_TCLK
M01_TXD0
M01_TXD1
M01_TXD2
M01_TXD3
M01_TXEN
M01_TXER
M02_COL
M02_CRS
M02_LINK
M02_RCLK
M02_RENEG
M02_RXD0
M02_RXD1
M02_RXD2
M02_RXD3
M02_RXDV
M02_RXER
M02_TCLK
M02_TXD0
M02_TXD1
M02_TXD2
M02_TXD3
M02_TXEN
M02_TXER
M03_COL
R25
T25
V3
V2
P24
V26
V25
AA26
L26
M26
AF8
A1
AC6
AD6
AF3
AE6
AD1
AF7
AE7
AD7
AC7
AC8
AD8
AD4
AF5
AE5
AD5
AC5
AE4
AF4
AD12
AC12
AE13
AF17
AE17
AF12
AC17
AD17
AE12
AD13
AF9
AE9
AD9
AF10
AE10
AD10
AF11
AE11
AD11
AC11
AF16
AE16
AD16
AC16
AF15
AE15
AD15
AC15
AE14
AD14
K26
E2
E3
E4
M07_CRS
M07_LINK
M07_RCLK
M07_RENEG
M07_RXD0
M07_RXD1
M07_RXD2
M07_RXD3
M07_RXDV
M07_RXER
M07_TCLK
M07_TXD0
M07_TXD1
M07_TXD2
M07_TXD3
M07_TXEN
M07_TXER
M08_COL
E23
E24
E25
E26
F4
F23
F24
F25
F26
G23
G24
G25
G26
H24
H25
H26
J24
M04_CRS
A2
M04_LINK
M04_RCLK
M04_RENEG
M04_RXD0
M04_RXD1
M04_RXD2
M04_RXD3
M04_RXDV
M04_RXER
M04_TCLK
M04_TXD0
M04_TXD1
M04_TXD2
M04_TXD3
M04_TXEN
M04_TXER
M05_COL
A13
A14
A25
A26
AF13
AF14
B1
J3
F3
J1
K1
K2
K3
J2
B3
L4
B24
B26
C2
C25
N1
F1
G1
G2
G3
G4
H4
H3
N2
P3
T2
P2
F2
R1
R2
R3
R4
T4
T3
L2
M1
M2
M3
M4
L1
N3
V1
W3
AA1
W2
AA3
Y1
Y2
M08_CRS
J25
J26
M08_EWRAP
M08_GTCLK
M08_LINK
M08_LREF
M08_MII
N26
P1
K23
N23
N24
N25
AA4
AB1
AB2
AB3
AB4
AB23
AB24
AC1
AC2
AC3
AC24
AC25
AD18
AD26
AE8
AF6
AF18
P25
P26
R23
R24
R26
T24
M05_CRS
M08_PMA
M08_RCLK
M08_RFCLK
M08_RXD0
M08_RXD1
M08_RXD2
M08_RXD3
M08_RXD4
M08_RXD5
M08_RXD6
M08_RXD7
M08_RXDV
M08_RXER
M08_TXD0
M08_TXD1
M08_TXD2
M08_TXD3
M08_TXD4
M08_TXD5
M08_TXD6
M08_TXD7
M08_TXEN
M08_TXER
MDCLK
M05_LINK
M05_RCLK
M05_RENEG
M05_RXD0
M05_RXD1
M05_RXD2
M05_RXD3
M05_RXDV
M05_RXER
M05_TCLK
M05_TXD0
M05_TXD1
M05_TXD2
M05_TXD3
M05_TXEN
M05_TXER
M06_COL
U23
W23
W24
W25
W26
Y23
Y25
AA23
AA25
AB25
AD2
AD25
AE1
AE3
AE24
AE26
AF1
AF2
AF25
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A11
D1
A10
B10
C10
D10
C9
B9
C13
A12
B12
C12
D12
B13
D11
A6
M06_CRS
M06_LINK
M06_RCLK
M06_RENEG
M06_RXD0
M06_RXD1
GND
GND
GND
5
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Table 2. Signal-to-Ball Mapping (Signal Names Sorted Alphabetically) (Continued)
SIGNAL
NAME
BALL
NO.
SIGNAL
NAME
BALL
NO.
SIGNAL
NAME
BALL
NO.
SIGNAL
NAME
BALL
NO.
SIGNAL
NAME
BALL
NO.
M23
AF22
AE22
AD22
AF20
AE20
AD20
AC20
AF21
AE21
AD21
AC21
AF24
AF19
AF23
AC22
AE23
AD23
L24
M24
L23
M25
L25
B25
C3
C24
D4
V4
V23
D13
D17
H23
K4
P4
W4
AC10
AC14
AC19
T23
RESET
SAD0
SAD1
SCS
SDATA0
SDATA1
SDATA2
SDATA3
SDATA4
SDATA5
SDATA6
SDATA7
SDMA
SINT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(2.5)
DD(3.3)
DD(3.3)
DD(3.3)
DD(3.3)
DD(3.3)
DD(3.3)
DD(3.3)
DD(3.3)
DD(3.3)
DD(3.3)
AC4
AC9
AC13
AC18
AC23
AD3
AD24
AE2
SRDY
SRNW
SRXRDY
STXRDY
TCLK
TDI
TDO
TMS
TRST
D9
D14
D18
D23
J4
J23
N4
a
DD (2.5)
AE25
D8
B2
P23
V
DD(2.5)
6
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Terminal Functions
JTAG interface
TERMINAL
INTERNAL
RESISTOR
I/O
DESCRIPTION
†
NAME
NO.
Test clock. Clocks state information and test data into and out of the TNETX4090 during operation
of the test port.
I
I
Pullup
TCLK
L24
Test data input. Serially shifts test data and test instructions into the TNETX4090 during operation
of the test port. An internal pullup resistor is provided on TDI to ensure JTAG compliance.
Pullup
None
TDI
M24
L23
M25
L25
Test data out. Serially shifts test data and test instructions out of the TNETX4090 during operation
of the test port.
O
I
TDO
TMS
TRST
Test mode select. Controls the state of the test-port controller. An internal pullup resistor is provided
on TMS to ensure JTAG compliance.
Pullup
Pullup
Test reset. Asynchronously resets the test-port controller. An internal pullup resistor is provided on
TRST to ensure JTAG compliance.
I
†
Internal resistors are provided to pull signals to known values. The system designers should determine if additional pullups or pulldowns are
required in their systems.
control logic interface
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Devicereset. Assertedforaminimumof100µsafterpowersuppliesandclockshavestabilized. Thesystemclock
must be operational during reset.
M23
I
RESET
Flow control. When flow control is activated (flow in SysControl = 1) and the number of free external memory
buffers is below the threshold indicated in FlowThreshold, FLOW is asserted.
AF8
O
FLOW
100-/1000-Mbit/s MAC interface [gigabit media-independent interface (GMII) (port 8)]
TERMINAL
NAME
INTERNAL
RESISTOR
I/O
DESCRIPTION
†
PMA mode. PMA mode can be selected by either pulling M08_PMA low externally, or by setting the
reqpma bit in the PortxControl register. If M08_PMA is allowed to float high, the port is configured as
either an MII or GMII interface, as determined by the value of the M08_MII terminal.
I
Pullup
M08_PMA
M08_MII
MII or GMII selection. The value of this terminal is ignored if M08_PMA = 0. 100-Mbit/s MII mode can
be selected by either pulling M08_MII low externally, or by setting the req100 bit in the PortxControl
register. If M08_MII is allowed to float high, the port is configured as a GMII interface.
I
Pullup
†
Internal resistors are provided to pull signals to known values. The system designers should determine if additional pullups or pulldowns are
required in their systems.
7
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Terminal Functions (Continued)
100-/1000-Mbit/s MAC interface (GMII mode)
TERMINAL
NAME
INTERNAL
RESISTOR
I/O
DESCRIPTION
†
Collision sense. Assertion of M08_COL during half-duplex operation indicates network collision.
Additionally, during full-duplex operation, transmission of new frames does not commence if this
terminal is asserted.
I
Pulldown
M08_COL
I
Pulldown
None
Carrier sense. M08_CRS indicates a frame carrier signal is being received.
Enable wrap. M08_EWRAP reflects the state of the loopback bit in the PCS8Control register.
Transmit clock. Transmit clock output to attached physical layer (PHY) device.
Connection status. M08_LINK indicates the presence of port connection.
M08_CRS
O
O
M08_EWRAP
M08_GTCLK
None
I
Pulldown
M08_LINK
M08_LREF
– If M08_LINK = 0, there is no link.
– If M08_LINK = 1, the link is OK.
Renegotiate.M08_LREF indicates to the attached PHY device that this device wishes to negotiate
a new configuration.
– Following a 0-to-1 transition of neg in PortxControl, M08_LREF is asserted low, and
remains low until M08_LINK goes low. If M08_LINK was already low, M08_LREF is still
activated for at least one cycle.
O
None
– M08_LREF is asserted low for as long as initd in SysControl = 0, regardless of the state
of M08_LINK.
I
I
Pullup
Pullup
Receive clock. Receive clock source from the attached PHY.
M08_RCLK
Reference clock. Reference clock, used as the clock source for the transmit side of this port and
to generate M08_GTCLK.
M08_RFCLK
M08_RXD7
M08_RXD6
M08_RXD5
M08_RXD4
M08_RXD3
M08_RXD2
M08_RXD1
M08_RXD0
Receive data. Byte receive data from the attached PHY. When M08_RXDV is asserted, these
signals carry receive data. Data on these signals is synchronous to M08_RCLK.
I
Pullup
Receive data valid. M08_RXDV indicates data on M08_RXD7–M08_RXD0 is valid. This signal is
synchronous to M08_RCLK.
I
I
Pulldown
Pulldown
M08_RXDV
M08_RXER
Receive error. M08_RXER indicates reception of a coding error on received data.
M08_TXD7
M08_TXD6
M08_TXD5
M08_TXD4
M08_TXD3
M08_TXD2
M08_TXD1
M08_TXD0
Transmitdata. Byte transmit data. When M08_TXEN is asserted, these signals carry transmit data.
Data on these signals is synchronous to M08_GTCLK.
O
None
Transmit enable. M08_TXEN indicates valid transmit data on M08_TXD7–M08_TXD0. This signal
is synchronous to M08_GTCLK.
O
O
None
None
M08_TXEN
M08_TXER
Transmit error. M08_TXER allows coding errors to be propagated between the media-access
control (MAC) and the attached PHY. It is asserted at the end of an under-running frame, enabling
the device to force a coding error.
†
Internal resistors are provided to pull signals to known values. The system designers should determine if additional pullups or pulldowns are
required in their systems.
8
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Terminal Functions (Continued)
100-/1000-Mbit/s MAC interface [physical media attachment (PMA) mode]
TERMINAL
NAME
INTERNAL
I/O
DESCRIPTION
RESISTOR
Pulldown
Pulldown
None
Receive byte clock 1. M08_COL is used to input receive byte clock 1 from the attached SERDES
device.
I
M08_COL
I
Unused. This terminal can be left unconnected.
M08_CRS
Enable wrap. Output to attached SERDES device used to enable loopback testing of that device.
M08_EWRAP is asserted when loopback in PCSxControl = 1.
O
O
M08_EWRAP
M08_GTCLK
None
Transmit clock. Transmit clock output to attached SERDES device.
Signaldetect. This can be connected to the signal detect output from the external SERDES device.
I
Pulldown
M08_LINK
– If M08_LINK = 0, there is no signal.
– If M08_LINK = 1, signal is present.
Lock to reference. M08_LREF is asserted low during hard reset or when lckref in PortxControl = 1.
It is used by the external SERDES device to lock to its reference clock.
M08_LREF
M08_RCLK
O
I
None
Receive byte clock 0. M08_RCLK is used to input receive byte clock 0 from the attached SERDES
device.
Pullup
Reference clock. Reference clock, used as the clock source for the transmit side of this port and
to generate M08_GTCLK. M08_RFCLK provides the clock source for the entire internal PCS
sublayer.
I
Pullup
Pullup
M08_RFCLK
M08_RXD7
M08_RXD6
M08_RXD5
M08_RXD4
M08_RXD3
M08_RXD2
M08_RXD1
M08_RXD0
Receive data. Least significant eight bits of the 10-bit receive code group. Even-numbered code
groups are latched with M08_COL, and odd-numbered code groups are latched with M08_RCLK.
I
Receive data valid. M08_RXDV is used to receive the 9th bit of the 10-bit PMA code groups.
Even-numbered code groups are latched with M08_COL, and odd-numbered code groups are
latched with M08_RCLK.
I
I
Pulldown
Pulldown
M08_RXDV
M08_RXER
Receive error. M08_RXER is used to receive the 10th bit of the 10-bit PMA code groups.
Even-numbered code groups are latched with M08_COL, and odd-numbered code groups are
latched with M08_RCLK.
M08_TXD7
M08_TXD6
M08_TXD5
M08_TXD4
M08_TXD3
M08_TXD2
M08_TXD1
M08_TXD0
Transmit data. Least significant eight bits of the 10-bit transmit code group. Data on these signals
is synchronous to M08_GTCLK.
O
None
Transmit enable. M08_TXEN is used to transmit the 9th bit of the 10-bit PMA code groups. Data
on this signal is synchronous to M08_GTCLK.
O
O
None
None
M08_TXEN
M08_TXER
Transmit error. M08_TXER is used to transmit the 10th bit of the 10-bit PMA code groups. Data on
this signal is synchronous to M08_GTCLK.
9
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Terminal Functions (Continued)
100-/1000-Mbit/s MAC interface [media-independent interface (MII) mode]
TERMINAL
NAME
INTERNAL
RESISTOR
I/O
DESCRIPTION
Collision sense. Assertion of M08_COL during half-duplex operation indicates network collision.
Additionally, during full-duplex operation, transmission of new frames does not commence if this
terminal is asserted.
I
Pulldown
M08_COL
I
Pulldown
None
Carrier sense. M08_CRS indicates a frame carrier signal is being received.
Enable wrap. M08_EWRAP reflects the state of the loopback bit in the PCS8Control register.
Unused. This terminal can be left unconnected.
M08_CRS
O
O
M08_EWRAP
M08_GTCLK
None
Connection status. M08_LINK indicates the presence of port connection.
I
Pulldown
M08_LINK
M08_LREF
– If M08_LINK = 0, there is no link.
– If M08_LINK = 1, the link is OK.
Renegotiate.M08_LREF indicates to the attached PHY device that this device wishes to negotiate
a new configuration.
– Following a 0-to-1 transition of neg in PortxControl, M08_LREF is asserted low, and
remains low until M08_LINK goes low. If M08_LINK was already low, M08_LREF is still
activated for at least one cycle.
O
None
– M08_LREF is asserted low for as long as initd in SysControl = 0, regardless of the state
of M08_LINK.
I
I
Pullup
Pullup
Receive clock. Receive clock source from the attached PHY or PMI device.
Transmit clock. Transmit clock from the attached PHY or PMI device.
M08_RCLK
M08_RFCLK
M08_RXD7
M08_RXD6
I
Pullup
Unused. These terminals can be left unconnected.
IEEE Std 802.3x pause frame support selection
– If pulled low either internally or by the attached PHY or PMI device, M08_RXD5 causes the
port to not support pause frames.
– If not pulled low, the port does not support pause frames.
†
Pullup
M08_RXD5
M08_RXD4
I/O
I/O
I
Duplex selection [force half duplex (active low)]
– If pulled low either internally or by the attached PHY or PMI device, the port operates in
half-duplex mode.
– If not pulled low, the port operates in full-duplex mode.
†
Pullup
Pullup
M08_RXD3
M08_RXD2
M08_RXD1
M08_RXD0
Receive data. Nibble-wide receive data from the attached PHY or PMI device. When M08_RXDV
is asserted, these signals carry receive data. Data on these signals is synchronous to M08_RCLK.
Receive data valid. M08_RXDV indicates data on M08_RXD3–M08_RXD0 is valid. This signal is
synchronous to M08_RCLK.
I
I
Pulldown
Pulldown
M08_RXDV
M08_RXER
Receive error. Indicates reception of a coding error on received data.
M08_TXD7
M08_TXD6
M08_TXD5
M08_TXD4
O
O
None
None
Unused. These terminals can be left unconnected, but are driven low.
M08_TXD3
M08_TXD2
M08_TXD1
M08_TXD0
Transmit data. Nibble-wide transmit data. When M08_TXEN is asserted, these signals carry
transmit data. Data on these signals is synchronous to M08_RFCLK.
†
Not a true bidirectional terminal. It can only be actively pulled down.
10
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Terminal Functions (Continued)
100-/1000-Mbit/s MAC interface [media-independent interface (MII) mode] (continued)
TERMINAL
NAME
INTERNAL
RESISTOR
I/O
DESCRIPTION
Transmit enable. M08_TXEN indicates valid transmit data on M08_TXD3–M08_TXD0. This signal
is synchronous to M08_RFCLK.
O
None
None
M08_TXEN
M08_TXER
Transmit error. M08_TXER allows coding errors to be propagated between the MAC and the
attached PHY. It is asserted at the end of an under-running frame, enabling the device to force a
coding error.
O
10-/100-Mbit/s MAC interface (MII mode) (ports 0–7)
TERMINAL
NAME
INTERNAL
RESISTOR
I/O
DESCRIPTION
NO.
C21
D16
C11
A6
H2
N2
M00_COL
M01_COL
M02_COL
M03_COL
M04_COL
M05_COL
M06_COL
M07_COL
Collision sense. Assertion of Mxx_COL indicates network collision. In full-duplex mode, the
port does not start transmitting a new frame if this signal is active; the value of this terminal
is ignored at all other times.
I
Pulldown
Pulldown
Pulldown
Pullup
V1
AC6
B21
C16
B11
B6
H1
P3
M00_CRS
M01_CRS
M02_CRS
M03_CRS
M04_CRS
M05_CRS
M06_CRS
M07_CRS
I
I
I
Carrier sense. Indicates a frame-carrier signal is being received.
Connection status. Indicates the presence of port connection:
W3
AD6
B19
B14
A9
A4
L3
T2
AA1
AF3
M00_LINK
M01_LINK
M02_LINK
M03_LINK
M04_LINK
M05_LINK
M06_LINK
M07_LINK
– If Mxx_LINK = 0, there is no link.
– If Mxx_LINK = 1, the link is OK.
An internal pullup resistor is provided.
A21
B16
A11
C6
J3
P2
M00_RCLK
M01_RCLK
M02_RCLK
M03_RCLK
M04_RCLK
M05_RCLK
M06_RCLK
M07_RCLK
Receive clock. Receive clock source from the attached PHY device.
W2
AE6
11
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Terminal Functions (Continued)
10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued)
TERMINAL
NAME
INTERNAL
RESISTOR
I/O
DESCRIPTION
NO.
C26
D26
D1
C1
F3
M00_RENEG
M01_RENEG
M02_RENEG
M03_RENEG
M04_RENEG
M05_RENEG
M06_RENEG
Renegotiate.Indicates to the attached PHY device that this port wishes to renegotiate a new
configuration.
O
None
F2
AA3
D19
A16
C9
C4
J2
T4
W1
AC8
M00_RXDV
M01_RXDV
M02_RXDV
M03_RXDV
M04_RXDV
M05_RXDV
M06_RXDV
M07_RXDV
Receive data valid. Indicates data on Mxx_RXD7–Mxx_RxD0. is valid. This signal is
synchronous to Mxx_RCLK.
I
Pulldown
D20
C20
B20
A20
D15
C15
B15
A15
D10
C10
B10
A10
D5
C5
B5
A5
K3
K2
K1
J1
R4
R3
R2
R1
Y4
Y3
Y2
Y1
AC7
AD7
AE7
AF7
M00_RXD3
M00_RXD2
M00_RXD1
M00_RXD0
M01_RXD3
M01_RXD2
M01_RXD1
M01_RXD0
M02_RXD3
M02_RXD2
M02_RXD1
M02_RXD0
M03_RXD3
M03_RXD2
M03_RXD1
M03_RXD0
M04_RXD3
M04_RXD2
M04_RXD1
M04_RXD0
M05_RXD3
M05_RXD2
M05_RXD1
M05_RXD0
M06_RXD3
M06_RXD2
M06_RXD1
M06_RXD0
M07_RXD3
M07_RXD2
M07_RXD1
M07_RXD0
Receive data. Nibble receive data from the attached PHY device. Data on these signals is
synchronoustoMxx_RCLK. WhenMxx_RXDVandMxx_RXERarelow,theseterminalsare
sampled the cycle before Mxx_LINK goes high to configure the port, based on capabilities
negotiated by the attached PHY device as follows:
– Mxx_RXD0 indicates full-duplex mode when high; half duplex when low, and sets
duplex in PortxStatus.
– Mxx_RXD1 indicates IEEE Std 802.3 pause frame support when high; no pause
when low, and sets pause in PortxStatus.
– Mxx_RXD2 indicates 100 Mbit/s when high; 10 Mbit/s when low, and sets speed in
PortxStatus.
– Mxx_RXD3 is unused and is ignored.
I
Pullup
12
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Terminal Functions (Continued)
10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued)
TERMINAL
NAME
INTERNAL
RESISTOR
I/O
DESCRIPTION
NO.
C19
C14
B9
B4
L4
T3
AA2
AD8
M00_RXER
M01_RXER
M02_RXER
M03_RXER
M04_RXER
M05_RXER
M06_RXER
M07_RXER
I
Pulldown
Receive error. Indicates reception of a coding error on received data.
B23
C17
C13
A8
F1
L2
M00_TCLK
M01_TCLK
M02_TCLK
M03_TCLK
M04_TCLK
M05_TCLK
M06_TCLK
M07_TCLK
I
Pullup
Transmit clock. Transmit clock source from the attached PHY or PMI device.
T1
AD4
C22
B22
A22
A23
C18
B18
A18
A19
D12
C12
B12
A12
D7
C7
B7
A7
G4
G3
G2
G1
M4
M3
M2
M1
U4
U3
U2
U1
AC5
AD5
AE5
AF5
M00_TXD3
M00_TXD2
M00_TXD1
M00_TXD0
M01_TXD3
M01_TXD2
M01_TXD1
M01_TXD0
M02_TXD3
M02_TXD2
M02_TXD1
M02_TXD0
M03_TXD3
M03_TXD2
M03_TXD1
M03_TXD0
M04_TXD3
M04_TXD2
M04_TXD1
M04_TXD0
M05_TXD3
M05_TXD2
M05_TXD1
M05_TXD0
M06_TXD3
M06_TXD2
M06_TXD1
M06_TXD0
M07_TXD3
M07_TXD2
M07_TXD1
M07_TXD0
Transmit data. Byte transmit data. When Mxx_TXEN is asserted, these signals carry
transmit data. Data on these signals is synchronous to Mxx_TCLK. When Mxx_TXEN,
Mxx_TXER, and Mxx_LINK are all low, these terminals indicate the desired capabilities for
autonegotiation as follows:
– Mxx_TXD0 indicates full-duplex capability when high; half duplex when low, as
determined by reqhd in PortxControl.
– Mxx_TXD1 indicates IEEE Std 802.3 pause frame support when high; no pause
when low, as determined by reqnp in PortxControl.
– Mxx_TXD2 indicates 100 Mbit/s when high; 10 Mbit/s when low, as determined by
req10 in PortxControl.
– Mxx_TXD3 is unused and is 0.
O
None
13
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Terminal Functions (Continued)
10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued)
TERMINAL
NAME
INTERNAL
RESISTOR
I/O
DESCRIPTION
NO.
D22
B17
B13
B8
H4
L1
M00_TXEN
M01_TXEN
M02_TXEN
M03_TXEN
M04_TXEN
M05_TXEN
M06_TXEN
M07_TXEN
Transmit enable. Indicates valid transmit data on Mxx_TXDn. This signal is synchronous to
Mxx_TCLK.
O
None
V3
AE4
D21
A17
D11
C8
H3
N3
M00_TXER
M01_TXER
M02_TXER
M03_TXER
M04_TXER
M05_TXER
M06_TXER
M07_TXER
Transmiterror. AllowscodingerrorstobepropagatedacrosstheMII. Mxx_TXERisasserted
at the end of an under-running frame, enabling the TNETX4090 to force a coding error.
O
None
V2
AF4
MII management interface
TERMINAL
INTERNAL
RESISTOR
I/O
DESCRIPTION
NAME
NO.
Serial MII management data clock. Disabled [high-impedance (Z) state] through the use of the
serial input/output (SIO) register. An internal pullup resistor is provided.
K26
K25
K24
O
I/O
O
Pullup
Pullup
Pullup
MDCLK
Serial MII management data input/output. Disabled [high-impedance (Z) state] through the use
of the SIO register. An internal pullup resistor is provided.
MDIO
Serial MII management reset. Disabled [high-impedance (Z) state] through the use of the SIO
register. An internal pullup resistor is provided.
MRESET
14
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Terminal Functions (Continued)
RDRAM interface
TERMINAL
INTERNAL
I/O
DESCRIPTION
RESISTOR
NAME
NO.
Bus control. Controls signal-to-frame packets, transmits part of the operation code,
Y26
O
None
initiates data transfers, and terminates data transfers. This is a rambus signal logic (RSL)
signal (see Note 1).
DBUS_CTL
AC26
AA24
AB26
Y24
V24
U25
U26
T26
R25
DBUS_DATA0
DBUS_DATA1
DBUS_DATA2
DBUS_DATA3
DBUS_DATA4
DBUS_DATA5
DBUS_DATA6
DBUS_DATA7
DBUS_DATA8
Bus data. Signal lines for request, write-data, and read-data packets. The request packet
contains the address, operation codes, and other control information. These are RSL
signals (see Note 1).
I/O
None
Bus enable. Controls signal-to-transfer column addresses for random-access
(nonsequential) transactions. This is an RSL signal (see Note 1).
T25
P24
V26
O
I
None
None
None
DBUS_EN
DCCTRL
Current control program. Connected to the current control resistor whose other terminal
is connected to the termination voltage.
Receive clock. This signal is derived from DTX_CLK. This is an RSL signal (see Note 1).
It is connected directly to DTX_CLK in the TNETX4090.
O
DRX_CLK
Transmit clock. This is an RSL signal (see Note 1). The primary internal clock is derived
from this signal.
V25
I
I
None
None
DTX_CLK
DVREF
AA26
Reference voltage. Logic threshold reference voltage for RSL signals.
NOTE 1: RSL is a low-voltage swing, active-low signaling technology.
15
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Terminal Functions (Continued)
DIO interface
TERMINAL
INTERNAL
RESISTOR
I/O
DESCRIPTION
NAME
NO.
SAD0
SAD1
AF22
AE22
DIO address bus. Selects the internal host registers provided SDMA is high. Internal pullup
resistors are provided.
I
I
Pullup
Pullup
DIO chip select. When low, SCS indicates a DIO port access is valid. An internal pullup resistor
is provided.
AD22
SCS
AF20
AE20
AD20
AC20
AF21
AE21
AD21
AC21
SDATA0
SDATA1
SDATA2
SDATA3
SDATA4
SDATA5
SDATA6
SDATA7
I/O
Pullup
DIO data bus. Byte-wide bidirectional DIO port. External pullup resistors are required.
DIO DMA select. When low, SDMA modifies the behavior of the DIO interface to allow it to
operateefficientlywithanexternaldirectmemoryaccess(DMA)controller. SAD0andSAD1are
not used to select the internal host register for the access. Instead, the DIO address to access
internal registers is provided by the DMAAddress register, and one of two host register
addressesisselectedaccordingtodmaincinSysControl. Aninternalpullupresistorisprovided.
AF24
I
Pullup
SDMA
Interrupt. Interrupt to the attached microprocessor. The interrupt type can be found in the Int
register.
AF19
AF23
O
O
None
SINT
DIO ready. When low during reads, SRDY indicates to the host when data is valid to be read.
When low during writes, SRDY indicates when data has been received. SRDY is driven high
for one clock cycle before placing the output in high impedance after SCS is taken high. An
internal pullup resistor is provided.
Pullup
SRDY
DIO read not write
– When high, read operation is selected.
– When low, write operation is selected.
AC22
I
Pullup
SRNW
An internal pullup resistor is provided.
Network management (NM) port, receive ready. When high, SRXRDY indicates that the NM
port’s receive buffers are completely empty and the NM port is able to receive a frame of any
size up to 1535 bytes in length.
AE23
AD23
O
O
None
None
SRXRDY
STXRDY
Network management (NM) port, transmit ready. When high, STXRDY indicates that at least
one buffer of frame data is available to be read by the management CPU. It outputs a 1 if any
of the end-of-frame (eof), start-of-frame (sof), or interior-of-frame (iof) bits in NMTxControl is set
to 1, otherwise, it outputs 0.
EEPROM interface
TERMINAL
I/O
INTERNAL
RESISTOR
DESCRIPTION
NAME
ECLK
EDIO
NO.
L26
M26
O
None
EEPROM data clock. An internal pullup resistor is provided.
I/O
Pullup
EEPROM data input/output. An internal pullup resistor is provided.
16
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Terminal Functions (Continued)
LED interface
TERMINAL
INTERNAL
I/O
DESCRIPTION
RESISTOR
NAME
NO.
AD19
AE19
O
O
None
None
LED clock. Serial shift clock for the LED status data.
LED data. Serial LED status data.
LED_CLK
LED_DATA
100-/1000-Mbit/s port PCS LED interface
TERMINAL
NAME
INTERNAL
RESISTOR
I/O
DESCRIPTION
NO.
Duplex LED. When in PMA mode, this terminal is low if the port isconfiguredforfull-duplex
operation. It is high at all other times.
L08_DPLX
AE18
None
power supply
TERMINAL
NO.
DESCRIPTION
NAME
A1, A2, A13, A14, A25, A26,
AF13, AF14, B1, B3, B24,
B26, C2, C25, N1, N26, P1,
P25, P26, R23, R24, R26,
T24, U23, W23, W24, W25,
W26, Y23, Y25, AA23, AA25,
AB25, AD2, AD25, AE1, AE3,
AE24, AE26, AF1, AF2,
AF25, AF26
Ground. The 0-V reference for the TNETX4090.
GND
U24
Ground. The 0-V reference for the analog functions within the rambus ASIC cell (RAC).
2.5-V supply voltage. Power for the core.
GNDa
B2, B25, C3, C24, D4, D9,
D14, D18, D23, J4, J23, N4,
P23, V4, V23, AC4, AC9,
AC13, AC18, AC23, AD3,
AD24, AE2, AE25
V
DD(2.5)
D8, D13, D17, H23, K4, P4,
W4, AC10, AC14, AC19
3.3-V supply voltage. Power for the I/Os.
V
V
DD(3.3)
T23
2.5-V supply voltage. Power for the analog functions within the RAC.
a
DD (2.5)
17
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
DIO interface description
The DIO is a general-purpose interface that is used with a range of microprocessor or computer system
interfaces. The interface is backward compatible with the existing TI ThunderSWITCH products. The DIO
provides new signals to support external DMA controllers for improved performance.
This interface configures the switch using the attached CPU, and to access statistics registers (see Table 2).
DIO accesses the NM port to allow frame data to be transferred between the CPU and the switch to support
spanning tree, SNMP, and RMON. The CPU reads and writes packets directly under software control or an
external DMA controller can be used to improve performance. See TNETX4090 Programmer’s Reference
Guide, literature number SPAU003, for description of registers.
Table 2. DIO Internal Register Address Map
DIO
ADDRESS
BYTE 3
BYTE 2
BYTE 1
BYTE 0
Port1Control
Port3Control
Port5Control
Port7Control
Reserved
Port0Control
Port2Control
Port4Control
Port6Control
Port8Control
0x0000
0x0004
0x0008
0x000C
0x0010
Reserved
0x0014–0x003C
0x0040
Reserved
UnkVLANPort
MirrorPort
UplinkPort
Reserved
AgingThreshold
0x0044
Reserved
NLearnPorts
0x0048–0x004C
0x0050
TxBlockPorts
RxUniBlockPorts
0x0054
0x0058
RxMultiBlockPorts
UnkUniPorts
0x005C
0x0060
UnkMultiPorts
UnkSrcPorts
0x0064
0x0068
NewVLANIntPorts
Reserved
0x006C
0x0070–0x007C
0x0080
TrunkMap3
TrunkMap7
Trunk3Ports
TrunkMap2
TrunkMap6
Trunk2Ports
Reserved
TrunkMap1
TrunkMap5
Trunk1Ports
TrunkMap0
TrunkMap4
Trunk0Ports
RingPorts
0x0084
0x0088
0x008C
Reserved
0x0090–0x009C
0x00A0
DevCode
Reserved
SIO
Revision
DevNode[23:16]
DevNode[31:24]
DevNode[39:32]
DevNode[7:0]
DevNode[47:40]
DevNode[15:8]
0x00A4
Reserved
0x00A8
MCastLimit
Reserved
0x00DC
0x00E0
RamStatus
RamControl
Reserved
0x00E4
PauseTime100
PauseTime10
Reserved
0x00E8
PauseTime1000
0x00EC
0x00F0
Reserved
FlowThreshold
Reserved
LEDControl
0x00F4
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Table 2. DIO Internal Register Address Map (Continued)
DIO
BYTE 3
BYTE 2
BYTE 1
BYTE 0
ADDRESS
0x00F8
0x00FC
0x0100
0x0104
0x0108
0x010C
0x0110
0x0114
0x0118
0x011C
0x0120
0x0124
0x0128
0x012C
0x0130
0x0134
0x0138
0x013C
0x0140
0x0144
0x0148
0x014C
0x0150
0x0154
0x0158
0x015C
0x0160
0x0164
0x0168
0x016C
0x0170
0x0174
0x0178
0x017C
0x0180
0x0184
0x0188
0x018C
0x0190
0x0194
0x0198
0x019C
SysControl
StatControl
Reserved (for EEPROM CRC)
VLAN0Ports
VLAN1Ports
VLAN2Ports
VLAN3Ports
VLAN4Ports
VLAN5Ports
VLAN6Ports
VLAN7Ports
VLAN8Ports
VLAN9Ports
VLAN10Ports
VLAN11Ports
VLAN12Ports
VLAN13Ports
VLAN14Ports
VLAN15Ports
VLAN16Ports
VLAN17Ports
VLAN18Ports
VLAN19Ports
VLAN20Ports
VLAN21Ports
VLAN22Ports
VLAN23Ports
VLAN24Ports
VLAN25Ports
VLAN26Ports
VLAN27Ports
VLAN28Ports
VLAN29Ports
VLAN30Ports
VLAN31Ports
VLAN32Ports
VLAN33Ports
VLAN34Ports
VLAN35Ports
VLAN36Ports
VLAN37Ports
VLAN38Ports
VLAN39Ports
19
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Table 2. DIO Internal Register Address Map (Continued)
DIO
ADDRESS
BYTE 3
BYTE 2
BYTE 1
BYTE 0
VLAN40Ports
VLAN41Ports
VLAN42Ports
VLAN43Ports
VLAN44Ports
VLAN45Ports
VLAN46Ports
VLAN47Ports
VLAN48Ports
VLAN49Ports
VLAN50Ports
VLAN51Ports
VLAN52Ports
VLAN53Ports
VLAN54Ports
VLAN55Ports
VLAN56Ports
VLAN57Ports
VLAN58Ports
VLAN59Ports
VLAN60Ports
VLAN61Ports
VLAN62Ports
VLAN63Ports
Reserved
0x01A0
0x01A4
0x01A8
0x01AC
0x01B0
0x01B4
0x01B8
0x01BC
0x01C0
0x01C4
0x01C8
0x01CC
0x01D0
0x01D4
0x01D8
0x01DC
0x01E0
0x01E4
0x01E8
0x01EC
0x01F0
0x01F4
0x01F8
0x01FC
0x0200–0x02FC
0x0300
0x0304
0x0308
0x030C
0x0310
0x0314
0x0318
0x031C
0x0320
0x0324
0x0328
0x032C
0x0330
0x0334
0x0338
0x033C
0x0340
0x0344
VLAN1QID
VLAN3QID
VLAN5QID
VLAN7QID
VLAN9QID
VLAN11QID
VLAN13QID
VLAN15QID
VLAN17QID
VLAN19QID
VLAN21QID
VLAN23QID
VLAN25QID
VLAN27QID
VLAN29QID
VLAN31QID
VLAN33QID
VLAN35QID
VLAN0QID
VLAN2QID
VLAN4QID
VLAN6QID
VLAN8QID
VLAN10QID
VLAN12QID
VLAN14QID
VLAN16QID
VLAN18QID
VLAN20QID
VLAN22QID
VLAN24QID
VLAN26QID
VLAN28QID
VLAN30QID
VLAN32QID
VLAN34QID
20
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Table 2. DIO Internal Register Address Map (Continued)
DIO
ADDRESS
BYTE 3
BYTE 2
BYTE 1
BYTE 0
VLAN37QID
VLAN39QID
VLAN41QID
VLAN43QID
VLAN45QID
VLAN47QID
VLAN49QID
VLAN51QID
VLAN53QID
VLAN55QID
VLAN57QID
VLAN59QID
VLAN61QID
VLAN63QID
Port1QTag
VLAN36QID
VLAN38QID
VLAN40QID
VLAN42QID
VLAN44QID
VLAN46QID
VLAN48QID
VLAN50QID
VLAN52QID
VLAN54QID
VLAN56QID
VLAN58QID
VLAN60QID
VLAN62QID
Port0QTag
0x0348
0x034C
0x0350
0x0354
0x0358
0x035C
0x0360
0x0364
0x0368
0x036C
0x0370
0x0374
0x0378
0x037C
0x0380
Port3QTag
Port2QTag
0x0384
Port5QTag
Port4QTag
0x0388
Port7QTag
Port6QTag
0x038C
0x0390
Reserved
Port8QTag
Reserved
0x0394–0x03FC
0x0400
Port1Status
Port3Status
Port5Status
Port7Status
Reserved
Port0Status
Port2Status
Port4Status
Port6Status
Port8Status
0x0404
0x0408
0x040C
0x0410
Reserved
FindPort
0x0414–0x043C
0x0440
FindNode[23:16]
FindVLAN
FindNode[31:24]
FindControl
FindNode[39:32]
FindNode[7:0]
FindNode[47:40]
FindNode[15:8]
0x0444
0x0448
NewNode[23:16]
NewNode[31:24]
NewNode[39:32]
NewNode[7:0]
NewNode[47:40]
NewNode[15:8]
0x044C
0x0450
Reserved
NewVLAN
NewPort
0x0454
AddNode[23:16]
AddVLAN
AddNode[31:24]
AddDelControl
AddNode[39:32]
AddNode[7:0]
AddNode[47:40]
AddNode[15:8]
0x0458
0x045C
0x0460
AddPort
AgedNode[23:16]
AgedVLAN
AgedNode[31:24]
AgedPort
AgedNode[39:32]
AgedNode[7:0]
DelNode[39:32]
DelNode[7:0]
AgedNode[47:40]
AgedNode[15:8]
DelNode[47:40]
DelNode[15:8]
0x0464
0x0468
DelNode[23:16]
DelVLAN
DelNode[31:24]
DelPort
0x046C
0x0470
AgingCounter
NumNodes
0x0474
Reserved
0x0478–0x0540
0x0544
XMultiGroup17
XMultiGroup18
0x0548
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Table 2. DIO Internal Register Address Map (Continued)
DIO
ADDRESS
BYTE 3
BYTE 2
BYTE 1
BYTE 0
XMultiGroup19
XMultiGroup20
XMultiGroup21
XMultiGroup22
XMultiGroup23
XMultiGroup24
XMultiGroup25
XMultiGroup26
XMultiGroup27
XMultiGroup28
XMultiGroup29
XMultiGroup30
XMultiGroup31
XMultiGroup32
XMultiGroup33
XMultiGroup34
XMultiGroup35
XMultiGroup36
XMultiGroup37
XMultiGroup38
XMultiGroup39
XMultiGroup40
XMultiGroup41
XMultiGroup42
XMultiGroup43
XMultiGroup44
XMultiGroup45
XMultiGroup46
XMultiGroup47
XMultiGroup48
XMultiGroup49
XMultiGroup50
XMultiGroup51
XMultiGroup52
XMultiGroup53
XMultiGroup54
XMultiGroup55
XMultiGroup56
XMultiGroup57
XMultiGroup58
XMultiGroup59
XMultiGroup60
0x054C
0x0550
0x0554
0x0558
0x055C
0x0560
0x0564
0x0568
0x056C
0x0570
0x0574
0x0578
0x057C
0x0580
0x0584
0x0588
0x058C
0x0590
0x0594
0x0598
0x059C
0x05A0
0x05A4
0x05A8
0x05AC
0x05B0
0x05B4
0x05B8
0x05BC
0x05C0
0x05C4
0x05C8
0x05CC
0x05D0
0x05D4
0x05D8
0x05DC
0x05E0
0x05E4
0x05E8
0x05EC
0x05F0
22
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Table 2. DIO Internal Register Address Map (Continued)
DIO
ADDRESS
BYTE 3
BYTE 2
BYTE 1
BYTE 0
XMultiGroup61
XMultiGroup62
XMultiGroup63
Reserved
0x05F4
0x05F8
0x05FC
0x0600–0x060C
0x0700
PCS8Status
PCS8Control
Reserved
0x0704
PCS8ANLinkP
PCS8ANNxt
Reserved
PCS8ANAdvert
PCS8ANExp
0x0708
0x070C
PCS8ANLinkPNxt
0x0710
Reserved
Reserved
0x0714–0x0718
0x071C
PCS8ExStatus
Reserved
Reserved
0x0720–0x07FC
0x0800
DMAAddress
Reserved
Reserved
SysTest
Int
0x0804
IntEnable
0x0808
FreeStackLength
0x080C
RAMAddress
0x0810
Reserved
Reserved
RAMData
NMData
0x0814
Reserved
Reserved
NMRxControl
NMTxControl
0x0818
0x081C
0x0820
Reserved
0x0824–0x0FFC
0x1000–0x10FF
0x1900–0x3FFC
0x4000–0x5FFC
Manufacturing test registers (internal use only)
Reserved
Hardware reset
23
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
DIO interface description (continued)
Table3andTable4listtheleastsignificantbyteaddressfortheport-specificstatistics. Eachstatisticisfourbytes
long. To determine the address of a particular statistic, replace the xx in the head column with the characters
from the tail address. Table 3 has two tail columns: one for even-numbered ports and the other for
odd-numbered ports. See the TNETX4090 Programmer’s Reference Guide, literature number SPAU003, for
a detailed description of the statistic registers.
Example:
Port 7 head
64-octet frames tail
Port 7 octet frames statistic
=
=
=
0x83xx
A8 (odd-numbered port)
0x83A8
24
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Table 3. Port Statistics 1
TAIL
PORT NO.
HEAD
STATISTIC
EVEN
ODD
PORTS
PORTS
0
1
0x80xx
0x80xx
0x81xx
0x81xx
0x82xx
0x82xx
0x83xx
0x83xx
0x84xx
0x84xx
0x85xx
0x85xx
0x86xx
0x86xx
0x87xx
0x87xx
0x88xx
0x88xx
0x89xx
0x89xx
0x8Axx
0x8Axx
0x8Bxx
0x8Bxx
0x8Cxx
0x8Cxx
0x8Dxx
0x8Dxx
0x8Exx
0x8Exx
0x8Fxx
0x8Fxx
Receive octet
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
4C
50
54
58
5C
60
64
68
6C
70
74
78
7C
80
84
Good receive frames
Broadcast receive frames
Multicast receive frames
Receive CRC errors
2
88
3
8C
90
4
†
5
Receive align/code errors
Oversized receive frames
Receive jabbers
84
6
98
7
9C
A0
A4
A8
AC
B0
B4
B8
BC
C0
C4
C8
CC
D0
D4
D8
DC
E0
E4
E8
EC
F0
F4
F8
FC
8
Undersized receive frames
Receive fragments
64-octet frames
NM
65–127 octet frames
128–255 octet frames
256–511 octet frames
512–1023 octet frames
1024–1518 octet frames
Net octets
†
SQE test errors
Tx octets
Good transmit frames
†
Single-collision transmit frames
Reserved
†
Multiple-collision transmit frames
†
Carrier sense errors
†
Deferred transmit frames
†
Late collisions
†
Excessive collisions
Broadcast transmit frames
Filtered receive frames
Filtered receive frames
Transmit data errors
†
Collisions
Receive overruns
†
The NM port does not have this statistic. This address is reserved on the NM port.
25
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Table 4. Port Statistics 2
TAIL
(ALL PORTS)
PORT NO.
HEAD
STATISTIC
†
0
1
0x900x
0x901x
0x902x
0x903x
0x904x
0x905x
0x906x
0x907x
0x908x
0x909x
0x90Ax
0x90Bx
0x90Cx
0x90Dx
0x90Ex
0x90Fx
0x910x
0x911x
0x912x
0x913x
0x914x
0x915x
0x916x
0x917x
0x918x
0x919x
0x91Ax
0x91Bx
0x91Cx
0x91Dx
0x91Ex
0x91Fx
Pause transmit frames
0
4
†
Pause receive frames
Security violations
Reserved
2
8
3
C
4
5
6
7
8
NM
Reserved
†
The NM port does not have this statistic. This address is reserved on
the NM port.
26
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
DIO interface description (continued)
Table 5. Address-Lookup Statistics
PORT NO.
N/A
HEAD
0x9200–0x9FFC
0xA000
STATISTIC
Reserved
N/A
Unknown unicast destination addresses
Unknown multicast destination addresses
Unknown source addresses
Reserved
N/A
0xA004
N/A
0xA008
N/A
0xA00C–0xFFFC
WhenaccessingthestatisticsvaluesfromtheDIOport, itisnecessarytoperformfour1-byteDIOreadstoobtain
the full 32-bit counter. Counters always should be read in ascending byte-address order (0, 1, 2, 3). To prevent
the counter being updated while reading the four bytes, the entire 32-bit counter value is transferred to a holding
register when byte 0 is read.
To provide ease of use with both big- and little-endian CPUs, two alternative byte-ordering schemes are
supported. The mode of operations can be selected through the StatControl register.
receiving/transmitting management frames
Frames originating within the host are written to the NM port via the NMRxControl and NMData registers. Once
a frame has been fully written, it is then received by the switch and routed to the destination port(s).
Frames that were routed to this port from any of the switch ports are placed in a queue until the host is ready
to read them via the NMTxControl and NMData registers. They then are effectively transmitted out of the switch.
SDMA can be used to transmit or receive management frames (the SAD1–SAD0 terminals are ignored when
SDMA is asserted) (see Table 6). When SDMA is asserted, the switch uses the value in the DMAAddress
register instead of the DIO address registers to access frame data (this also can be used to access the switch
statistics). STXRDY and SRXRDY, the interrupts, freebuffs, eof, sof, and iof mechanisms can be used, as
desired, to prevent unwanted stalls on the DIO bus during busy periods.
Table 6. DMA Interface Signals
SIGNAL
SDMA
DESCRIPTION
Automatically sets up DIO address using the DMAAddress register
Indicates that at least one data frame buffer can be read by the management CPU
STXRDY
SRXRDY Indicates that the management CPU can write a frame of any size up to 1535 bytes
27
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
state of DIO signal terminals during hardware reset
The CPU can perform a hardware reset by writing to an address in the range of 0x40–0x5F (writes to a DMA
address in this range have no effect on reset); this is equivalent to asserting the hardware RESET terminal with
the following exceptions. During hardware reset, the output and bidirectional DIO terminals behave as shown
in Table 7.
DIO interface continues to operate. The reset condition remains active until SCS is driven high. SRDY does
not become high impedance or resistively pulled high (unlike a true hardware reset), so it still can be used
as a normal acknowledge in this case.
Following the reset, no EEPROM autoload is performed.
Table 7. DIO Interface During Hardware Reset
DIO INTERFACE
STATE DURING HARDWARE RESET
SRDY
High impedance – resistively pulled up
SDATA7–SDATA0 High impedance – resistively pulled up
STXRDY
SRXRDY
Driven low
Driven high
IEEE Std 802.1Q VLAN tags on the NM port
Frames received from the host via the NM port are required to contain a valid IEEE Std 802.1Q header (frames
that do not contain a valid IEEE Std 802.1Q header are incorrectly routed). They also can be corrupted at the
transmission port(s) as the tag-stripping process does not check that the four bytes after the source address
actually are a valid tag. The four bytes are a valid tag under all other circumstances.
When a frame is transmitted by the NM port (received by the host), no tag-stripping occurs, so the frame may
contain one or possibly two tags, depending on how the frame originally was received.
frame format on the NM port
The frame format on the NM port differs slightly from a standard Ethernet frame format. The key differences are:
the frame always contains an IEEE Std 802.1Q header in the four bytes following the source address (see
Figure 2). The TPID (tag protocol identifier or ethertype) field, however, is used in the switch for other purposes,
so a frame transmitted out of the switch on the NM port does not have the IEEE Std 802.1Q TPID of 81–00
(ethertype constant) value in these two bytes.
The first TPID byte output contains:
The frame source port number in the least significant bits. This allows the frame source port number to be
carried within the frame, which is useful for processing BPDUs, for example.
A cyclic redundancy check (CRC) type indicator (crctype) in the most significant bit (bit 7).
–
–
If crctype = 1, then the CRC word in the frame excludes the IEEE Std 802.1Q header.
If crctype = 0, then the CRC word in the frame includes the IEEE Std 802.1Q header. This CRC word is
for a regular IEEE Std 802.1Q frame format with the value in the IEEE Std 802.1Q TPID of 81–00
(ethertype constant) in the TPID field. Because the internal frame format uses the TPID field for other
purposes in the manner being described, it is necessary to insert the IEEE Std 802.1Q TPID of 81–00
(ethertype constant) value into the TPID field if the frame needs to be restored to a normal
IEEE Std 802.1Q frame format, which passes a CRC check.
28
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
frame format on the NM port (continued)
To provide a CRC word, which includes the header, the NM port generates a new CRC word as the frame is
being read out. It simultaneously checks the existing CRC in the frame and, if an error is found, ensures that
the final byte of the newly generated CRC is corrupted to contain an error, too. The CRC word is deliberately
corrupted if the header parity protection (described in the following) indicates an error in the header. In either
case, the pfe bit also is set to 1 after the final byte of the frame has been read from NMData.
If the frame was received on a port other than the NM port, then the crctype bit is set according to whether an
IEEE Std 802.1Q tag header was inserted into the frame during ingress.
–
–
If crctype = 1, a header was inserted.
If crctype = 0, a header was not inserted (crctype also is 0 if the frame VLAN ID was 0x000 and was
replaced by the port VLANID (PVID) from the PortxQTag register).
In an IEEE Std 802.1D-compliant application, the header simply can be removed from the frame to produce
a headerless frame with a correct CRC word.
–
All other bits in the byte are reserved and are 0.
The second TPID byte output contains:
Odd-parity protection bits for the other three bytes in the tag header
Bit 5 protects the first byte of the TPID field (i.e., the one containing crctype and source port number).
Bit 6 protects the first byte of the VLAN ID field.
Bit 7 protects the second byte of the VLAN ID field.
All other bits in the byte are reserved and are 0.
TPID (Tag Protocol Identifier)
TCI (Tag Control Information)
1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Priority cfi
VLAN ID
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
7
6
5
4
3 2 1 0 7 6 5 4 3 2 1 0
7
802.1Q header
Destination
Address
Source
Address
FCS
(CRC-32)
Length/Type
2 Bytes
Data
TPID
TCI
6 Bytes
2 Bytes
46–1517 Bytes
6 Bytes
2 Bytes
4 Bytes
Byte 1
Byte 2
Odd Parity Bits
2nd
TCI
1st
TCI
1st
TPID
CRC
Type
Source
Port
Reserved
Reserved
Byte Byte Byte
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Figure 2. NM Frame Format
29
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
frame format on the NM port (continued)
Any device reading frames out of the NM port must expect frames to be in the format shown in Figure 2.
Frames received into the switch on the NM port also must conform to this format, with the following caveats:
crc = 0 in NMRxControl
When the host is providing a frame containing valid CRC it also must provide in the TPID field valid header
parity protection and indicate via the crctype bit which type of CRC the frame contains [i.e., including the
header (crctype = 0), or excluding the header (crctype = 1)]. If crctype indicates that the header is included,
as for NM port transmissions, this mimics the presence of IEEE Std 802.1Q TPID of 81–00 (ethertype
constant) in the TPID field. If a CRC error or parity error is detected, the frame is discarded.
When crctype indicates that the header is included, the NM port regenerates CRC to exclude the header
during the reception process (this converts the frame into the required internal frame format).
crc = 1 in NMRxControl
If the switch is being asked to generate a CRC word for the frame, the values in the TPID field are ignored by
the NM port. The switch inserts header parity protection. It replaces the final four bytes of the frame with the
calculated CRC (the values in the final four bytes provided are don’t care).
In either case, the NM port inserts its own port number into the source port field in the least significant bits of
the first TPID byte, sets the crctype bit to 0, and also sets the reserved bits to 0.
Frames received from the host via the NM port are required to contain a valid IEEE Std 802.1Q VLAN ID in the
third and fourth bytes, following the source address (the NM port does not have a PortxQTag register for
inserting a VLAN tag if none is provided and does not have an rxacc bit). Frames that do not contain a VLAN
tag are incorrectly routed. They also can be corrupted at the transmission port(s). The header-stripping process
does not check that the two bytes after the source address are a valid IEEE Std 802.1Q TPID because there
is a valid header under all other circumstances.
When a frame is transmitted on the NM port, no header stripping occurs (again because the NM port does not
have a PortxQTag register or txacc bit), so the frame read by the host software contains one header (or possibly
more, depending on how the frame was received).
In either case, the NM port inserts its own port number into the source port field in the least significant bits of
the first TPID byte and sets the reserved bits to 0. Frames received from the host via the NM port are required
to contain a valid IEEE Std 802.1Q VLAN ID (VID) in the third and fourth bytes following the source address.
(The NM port does not have a default VLAN ID register for inserting a VLAN tag if none is provided. It cannot
also be configured as an access port.) Frames that do not contain a valid tag are incorrectly routed. They also
can be corrupted at the transmission port(s) as the tag-stripping process does not check that the four bytes after
the source address are a valid tag because they are valid tags under all other circumstances.
When a frame is transmitted on (read from) the NM port, no tag stripping occurs (because the NM port does
not have the default VLAN ID register or access configuration control), so the frame read by the host software
can contain one or more header tags, depending on how the frame was received.
30
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
full-duplex NM port
The NM port can intermix reception and transmission as desired. It is the direction of the NMData access (i.e.,
read or write) that determines whether a byte is removed from the transmit queue or added to the receive queue.
The DIO interface, however, is only half duplex since it cannot do a read and write at the same time.
NM bandwidth and priority
The NM port is capable of transferring a byte to or from NMData once every 80 ns, or 100 Mbit/s. This can be
sustained between the DIO port and the NM ports dedicated receive or receive buffers.
However, the NM port is prioritized lower than the other ports between its receive buffers and the external
memory system so that during periods of high activity, the NM port does not cause frames to be dropped on
the other ports.
interrupt processing
The SRXRDY signal and the nmrx interrupt are set when the receive FIFO is completely empty. This indicates
that the NM port is ready to accept a frame of any length (up to 1535 bytes).
If the host wished to download a sequence of frames, it could use the freebuffs field to determine space
availability.
PHY management interface
This interface gives the user an easy way to implement a software-controlled bit serial MII PHY management
interface.
MII devices that implement the management interface consisting of MDIO and MDCLK can be accessed
through an internal register (see the TNETX4090 Programmer’s Reference Guide, literature number SPAU003,
for details on controlling this interface). A third signal, MRESET, is provided to allow hardware reset of PHYs
that support it.
All three terminals have internal pullup resistors since they can be placed in a high-impedance state to allow
another bus master.
The interface does not implement any timing or MII frame formatting. The timing and frame format must be
ensured by the management software setting or clearing the bits within the internal registers in an appropriate
manner. Refer to the IEEE Std 802.3u and the MII device data sheets for the appropriate protocol requirements.
31
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
MAC interface
receive control
Data received from the PHYs is interpreted and assembled into the TNETX4090 buffer memory. Interpretation
involves detection and removal of the preamble, extraction of the address and frame length, extraction of the
IEEE Std 802.1Q header (if present), and data handling and CRC. Also included is a jabber-detection timer to
detect frames that exceed the maximum length being received on the network.
giant (long) frames
The maxlen bit within each port’s PortxControl register controls the maximum received frame size on that port.
Ifmaxlen=0, themaximumreceivedframelengthIs1535bytesifnoVLANheaderisinserted, or1531bytes
if a VLAN header is inserted. (When stored within the switch, a frame never can be longer than 1535 bytes).
If maxlen = 1, the maximum received frame length is 1518 bytes as specified by the IEEE Std 802.3. This
is the maximum length on the wire. If a VLAN header is inserted into a 1518-byte frame within the MAC,
the frame is stored as a 1522-byte frame within the switch.
All received frames that exceed the maximum size are discarded by the switch.
The long option bit in StatControl indicates how the statistics for long frames should be recorded.
short frames
All received frames shorter than 64 bytes are discarded upon reception and are not stored in memory or
transmitted.
receive filtering of frames
Received frames that contain an error (e.g., CRC, alignment, jabber, etc.) are discarded before transmission
and the relevant statistics counter is updated.
data transmission
The MAC takes data from the TNETX4090 internal buffer memory and passes it to the PHY. The data also is
synchronized to the transmit clock rate.
A CRC block checks that the outgoing frame has not been corrupted within the switch by verifying that it still
has a valid CRC as the frame is being transmitted. If a CRC error is detected, it is counted in the transmit data
errors counter.
transmit control
The frame control block handles the output of data to the PHYs. Several error states are handled. If a collision
is detected, the state machine jams the output. If the collision was late (after the first 64-byte buffer has been
transmitted), the frame is lost. If it is an early collision, the controller backs off before retrying. While operating
in full duplex, both carrier-sense (CRS) mode and collision-sensing modes are disabled (the switch does not
start transmitting a new frame if collision is active in full-duplex mode).
Internally, frame data only is removed from buffer memory once it has been successfully transmitted without
collision (for the half-duplex ports). Transmission recovery also is handled in this state machine. If a collision
is detected, frame recovery and retransmission are initiated.
32
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
adaptive performance optimization (APO)
Each Ethernet MAC incorporates APO logic. This can be enabled on an individual port basis. When enabled,
the MAC uses transmission pacing to enhance performance (when connected on networks using other transmit
pacing-capable MACs). Adaptive performance pacing introduces delays into the normal transmission of
frames, delaying transmission attempts between stations, reducing the probability of collisions occurring during
heavy traffic (as indicated by frame deferrals and collisions), thereby, increasing the chance of successful
transmission.
When a frame is deferred, suffers a single collision, multiple collisions, or excessive collisions, the pacing
counter is loaded with an initial value of 31. When a frame is transmitted successfully (without a deferral, single
collision, multiple collision, or excessive collision), the pacing counter is decremented by 1, down to 0.
With pacing enabled, a new frame is permitted to immediately [after one inter-packet gap (IPG)] attempt
transmission only if the pacing counter is 0. If the pacing counter is not 0, the frame is delayed by the pacing
delay (a delay of approximately four interframe gap delays).
NOTE:
APO affects only the IPG preceding the first attempt at transmitting a frame. It does not affect the
backoff algorithm for retransmitted frames.
interframe gap enforcement
The measurement reference for the interpacket gap of 96-bit times is changed, depending on frame traffic
conditions. If a frame is successfully transmitted (without collision), 96-bit times is measured from Mxx_TXEN.
If the frame suffered a collision, 96-bit times is measured from Mxx_CRS.
backoff
The device implements the IEEE Std 802.3 binary exponential backoff algorithm.
receive versus transmit priority
The queue manager prioritizes receive and transmit traffic as follows:
Highest priority is given to frames that currently are being transmitted. This ensures that transmitting frames
do not underrun.
Next priority is given to frames that are received if the free-buffer stack is not empty. This ensures that
received frames are not dropped unless it is impossible to receive them.
Lowest priority is given to frames that are queued for transmission but have not yet started to transmit.
These frames are promoted to the highest priority only when there is spare capacity on the memory bus.
The NM port receives the lowest priority to prevent frame loss during busy periods.
The memory bus has enough bandwidth to support the two highest priorities. The untransmitted frame queues
grow when frames received on different ports require transmission on the same port(s) and when frames are
repeatedly received on ports that are at a higher speed than the ports on which they are transmitted. Thisislikely
to be exacerbated by the reception of multicast frames, which typically require transmission on several ports.
When the backlog grows to such an extent that the free buffer stack is nearly empty, flow control is initiated (if
it has been enabled) to limit further frame reception.
33
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
10-/100-Mbit/s MII (ports 0–7)
speed, duplex, and flow-control negotiation
Each individual port can operate at 10 Mbit/s or 100 Mbit/s in half or full duplex, and can indicate (or not) support
of IEEE Std 802.3 flow control. The operating modes for each port can be negotiated between the MACs and
the PHYs after power up, by setting neg in PortxControl. This provides for unmanaged operation, when using
PHYs that support this signaling scheme.
If neg = 1, negotiation is initiated via the Mxx_LINK signal being driven low by the PHY. As long as Mxx_LINK
is low, the MAC indicates the capabilities it wishes the PHY to negotiate with. It outputs on:
Mxx_TXD0 is the desired duplex (0 = half, 1 = full). This signal reflects reqhd in the appropriate PortxControl
register.
Mxx_TXD1 is the desired IEEE Std 802.3 flow-control mode (0 = no pause, 1 = pause required). This signal
reflects the inverse of the value of reqnp in the appropriate PortxControl register.
Mxx_TXD2 is the desired speed (0 = 10 Mbit/s, 1 = 100 Mbit/s required). This signal reflects the inverse of
the value of req10 in the appropriate PortxControl register.
Mxx_TD3 does not take part in the negotiation process and outputs as 0 while Mxx_LINK is low.
As long as Mxx_LINK is low, the PHY outputs on:
Mxx_RXD0 is the result of duplex negotiation (0 = half, 1 = full) that is recorded in the duplex bit of the
appropriate PortxStatus register.
Mxx_RXD1 is the result of flow-control negotiation (0 = no pause, 1 = pause supported) that is recorded
in the pause bit of the appropriate PortxStatus register.
Mxx_RXD2 is the result of speed negotiation (0 = 10 Mbit/s, 1 = 100 Mbit/s supported) that is recorded in
the speed bit of the appropriate PortxStatus register.
Mxx_RXD3 is ignored by the switch when link is low.
If the switch is autobooted via an EEPROM, this negotiation is automatic (if the neg bit of the appropriate
PortxControl register is set to 1 by the EEPROM load). The switch is active and outputs valid requests on
Mxx_TXD0, Mxx_TXD1, and Mxx_TXD2 before Mxx_LINK is taken high by the PHY (see Figure 3).
If, however, a switch requires software initiation, or at a later time, software desires a change in the mode of
a port, it must request the PHY to drive Mxx_LINK low to begin renegotiation. This is achieved by writing to the
control registers within the PHY via the serial MII interface.
34
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
TXCLK
TXEN
TXER
Reserved Reserved
TXD3
Reserved Speed
Reserved Pause
Reserved Duplex
TXD2
TXD1
TXD0
LINK
RXCLK
RXDV
RXER
Reserved
Reserved
Reserved
Speed
RXD3
RXD2
RXD1
Reserved
Reserved
Pause
RXD0
Duplex
80-ms Min
750-ms Min
1200-ms Min
Link Fail or
Renegotiate
Autonegotiate
Page Swap Commences
Autonegotiate
Page Swap CompleteComplete and
Link Good
Autonegotiate
Figure 3. 10-/100-Mbit/s Port Negotiation With the TNETE2104
35
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
100-/1000-Mbit/s PHY interface (port 8)
This port is controlled by an IEEE Std 802.3-compliant MAC.
speed, duplex, and flow-control negotiation
When in PMA mode and autonegotiation is enabled, the on-chip PCS layer attempts to establish a compatible
mode of operation with the attached serializer/deserializer (SERDES).
If manual override has been established, no autonegotiation takes place and the interface mode of operation
is determined by the values in Port8Control.
The PCS layer may be forced to start autonegotiation by writing a 0 and then a 1 to the neg bit in Port8Control,
but, alternatively, you could hit the newaneg bit in PCS8Control.
Figure 4 shows how the gigabit port on the TNETX4090 can be connected to a SERDES device. Table 1 gives
a description of the device terminals.
TD0–TD7
TD8
M08_TXD0–M08_TXD7
M08_TXEN
TD9
M08_TXER
NC
CC
SYNC
SYNCEN
V
LOOPEN
M08_EWRAP
M08_LINK
Serial Data
Output
DOUT_TXP
DOUT_TXN
Tie to Signal Detect Terminal of
Optical Receiver, SERDES Device,
TNETX4090
Gigabit Port Terminals
or to V
TNETE2201
(SERDES Device)
CC
RD0–RD7
RD8
RD9
M08_RXD0–M08_RXD7
M08_RXDV
Serial Data
Input
DIN_RXP
DIN_RXN
M08_RXER
LCKREFN
RBC1
M08_LREF
M08_COL
M08_RCLK
M08_GTCLK
M08_RFCLK
RBC0
RFCLK
125-MHz Clock
NOTE: The SYNC output from the SERDES device is not used by the TNETX4090. The SYNCEN input on the SERDES device must be tied
high(enabled) for proper operation. The M08_LINK terminal on the TNETX4090 must be tied to the signal detect terminal of an attached
optical receiver or tied high if a comparable terminal is unavailable.
Figure 4. TNETX4090 Gigabit Port to SERDES Device Connections
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
speed, duplex, and flow-control negotiation (continued)
In 100-Mbit/s mode, M08_RXD4 and M08_RXD5 are reconfigured as open-drain inputs, to allow the port to
negotiate with the PHY device for duplex and IEEE Std 802.3 pause frame support at power up via the EEPROM
contents. M08_RXD4 is used for duplex and M08_RXD5 is used for pause (see Table 8 and Table 9).
Each of these terminals:
Has an integral weak pullup resistor.
Has a strong open-drain pulldown transistor that is enabled by setting to 1 the appropriate bit in
Port8Control.
Is connected (via synchronization logic) to the appropriate bit in PortxStatus. These bits directly control the
configuration of the ports.
Each terminal is considered bidirectional when pulled low by either the TNETX4090 or by the PHY (or other
external connections). If neither pulls the terminal low, the pullup resistor maintains a value of 1 on the terminal.
When the PHY does not pull down a terminal, it can determine the desired option being requested by the
TNETX4090. The TNETX4090 observes the terminal to determine if its desired option has been granted.
The sense of these signals is such that the higher-performance option is represented by a value of 1, so if the
MAC does not require the higher performance or the PHY cannot supply it, either can pull the signal low, forcing
the port to use the lower-performance option.
The status of the link for this port is indicated on M08_LINK and is observable in Port8Status. M08_LINK plays
no part in the negotiation of pause or duplex or their recording in Port8Status.
Table 8. Port 8 Duplex Negotiation in MII Mode
Port8Control
reqhd
Port8Status
duplex
M08_RXD4
OUTCOME
0
1
→
→
Floating 1
→
→
→
1
0
0
Full duplex
Half duplex
Half duplex
Driven 0 (by the TNETX4090)
Driven 0 (by PHY)
X
Table 9. Port 8 Pause Negotiation in MII Mode
Port8Control
reqnp
Port8Status
M08_RXD5
pause
OUTCOME
0
1
→
→
Floating 1
→
→
→
1
0
0
Pause support
No pause support
No pause support
Driven 0 (by the TNETX4090)
Driven 0 (by PHY)
X
full-duplex hardware flow control
This port provides hardware-level full-duplex flow control via the M08_COL and FLOW terminals.
The port does not start transmitting a new frame if M08_COL is active, though the value of this terminal is
ignored at other times.
FLOW becomes active when the number of free buffers is fewer than the number specified in
FlowThreshold, provided that flow in SysControl is set.
These two capabilities allow full-duplex flow control without the use of IEEE Std 802.3 pause frames when
connecting the TNETX4090 to another TNETX4090, or to some other device that supports this capability.
37
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
pretagging and extended port awareness
The TNETX4090 can be incorporated into a hierarchical system, whereby this port is connected to a crossbar
matrix with up to 17 1000-Mbit/s ports. By making this TNETX4090 aware of the ports on the crossbar matrix,
the crossbar matrix does not need to make any forwarding or filtering decisions, and can be relatively
inexpensive. To facilitate this, three forms of tags are provided on this port:
Pretag on transmission – containing the source port of the frame and a vector indicating the ports on the
crossbar matrix for which the frame is destined.
Pretag on reception (learning format) – containing the source port of the frame on the crossbar matrix.
Pretagonreception(directedformat)–containingavectorindicatingtheportsonthisTNETX4090forwhich
the frame is destined.
The information contained within these tags also enables the TNETX4090 to be incorporated in a system where
routing decisions are made at a higher level.
Use of pretagging is enabled by setting pretag in the appropriate PortxControl register.
pretag on transmission
Port 8 provides the frame source port and crossbar matrix destination port vector over eight cycles, beginning
withthefirstcyclethatM08_TXENishigh. Thepretagtakestheformofa32-bitvalue(dividedintoeightnibbles),
with each nibble being replicated on M08_TXD3–M08_TXD0 and M08_TXD7–M08_TXD4. This replaces the
preamble and sof delimiter normally generated at this time.
Figure 5 shows the timing relationship and Table 10 shows the fields within the tag.
M08_GTCLK
M08_TXEN
M08_TXD3–
3–0
3–0
7–4
7–4
11–8
11–8
15–12
15–12
19–16
19–16
23–20
23–20
27–24
27–24
31–28
31–28
Frame Data
Frame Data
M08_TXD0
M08_TXD7–
M08_TXD4
NOTE A: Ranges (e.g., 3–0) indicate which bits of the 32-bit pretag are output in each cycle.
Figure 5. Transmit Pretag Timing
38
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Table 10. Transmit Pretag Bit Definitions
BIT
NAME
FUNCTION
Reserved. These bits always are 0.
31–28 reserved
Receive header. Indicates whether an IEEE Std 802.1Q header was added to the frame on reception.
27
rxheader
– When rxheader = 1, an IEEE Std 802.1Q header was inserted.
– When rxheader = 0, no IEEE Std 802.1Q header was inserted.
26–25 reserved
24–20 portcode
19–17 reserved
Reserved. These bits always are 0.
Source port code. Indicates which port on the device received the frame. Codes 00000–01001 indicate ports 0–9,
respectively (port 9 is the NM DIO port). All other codes are reserved and are not generated.
Reserved. These bits always are 0.
Extended destination port vector. A bit for each port on the crossbar matrix. A 1 in position n indicates the frame is
destined for port n on the crossbar matrix.
†
xportvector
16–0
†
Bit vector, in which bit x corresponds to external crossbar matrix port x. Any number of ports can be selected at the same time.
pretag on reception
Port 8 can receive two tag formats, learning and directed, over eight cycles, beginning with the first cycle that
M08_RXDV is high. The pretag takes the form of a 32-bit value (divided into eight nibbles), with each nibble
being replicated on M08_RXD3–M08_RXD0 and M08_RXD7–M08_RXD4. This replaces the preamble and sof
delimiter normally received at this time.
Figure 6 shows the timing relationship, and Table 11 and Table 12 show the fields within the tag for learning and
directed format, respectively.
M08_RCLK
M08_RXDV
M08_RXD3–
M08_RXD0
3–0
7–4
11–8
15–12
19–16
23–20
27–24
31–28
Frame Data
Frame Data
M08_RXD7–
M08_RXD4
NOTE: Ranges (e.g., 3–0) indicate which bits of the 32-bit pretag are input in each cycle.
Figure 6. Receive Pretag Timing
Table 11. Learning Format Receive Pretag Bit Definitions
BIT
NAME
FUNCTION
Zero.Indicateslearningformat. Framesreceivedwiththistagformatareroutedusingthedeviceinternalframe-routing
algorithm. When the source address is learned, the crossbar matrix port number, indicated by xportcode, also is
learned, and is used to create the xportvector output as part of the transmit pretag for frames subsequently routed to
this address.
31
0
30–5 reserved
Reserved. Bits 30–5 are ignored.
Source port code. Portcode indicates which port on the device received the frame. Codes 00000–10000 indicate
ports 0–16, respectively. All other codes are reserved and are not generated.
‡
xportcode
4–0
‡
Binary code that selects a single port on this device or an external crossbar matrix connected to port 8
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Table 12. Directed Format Receive Pretag Bit Definitions
BIT
NAME
FUNCTION
One. Indicates directed format. The frame is routed to port(s) specified in portvector that are enabled (disabled in
portxcontrol = 0), regardless of whether the destination address is unicast or multicast (i.e., the destination address
is not examined).
The internal frame-routing algorithm is bypassed and has no effect on frame routing. The TxBlockPorts,
RxUniBlockPorts, and RxMultiBlockPorts registers also have no effect on frame reception or transmission.
31
1
Portvector is not examined to see if the source port has been specified as a destination port, so it is possible to send
a frame back out of port 8. If portvector is 0, the frame is discarded.
30–10 reserved
9–0 portvector
Reserved. Bits 30–10 are ignored.
Destination port vector. A bit for each port on this device. A 1 in position n indicates the frame is destined for port n
on this device.
ring-cascade topology
The ringports register allows port 8 to be used to cascade multiple TNETX4090 devices using a full-duplex
ring-cascade topology (see Figure 7).
Port 8
Port 8
Port 8
TNETX4090
TNETX4090
TNETX4090
0 1 2 3
4 5 6 7
0 1 2 3
4 5 6 7
0 1 2 3
4 5 6 7
Figure 7. Ring-Cascade Topology
This configuration provides a way to construct a higher port-density system using three or more TNETX4090s.
Setting the portvector bit corresponding to this port in RingPorts modifies the normal behavior of the switch in
several ways to enable the ring topology.
Frames received on this port can be retransmitted out through the same port. This allows frames destined
for a nonring port on another switch in the ring to pass through this switch.
Frames transmitted from a ring port have an out-of-band pretag in the clock cycle before Mxx_TXEN is
asserted. The contents of the pretag are determined as follows:
–
If the transmitted frame was received on a nonring port, the pretag consists of the ringid field from
RingPorts, replicated on Mxx_RXD3–Mxx_RXD0 and Mxx_RXD7–Mxx_RXD4.
–
If the transmitted frame was received on a ring port, the pretag is the same as the received pretag.
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
ring-cascade topology (continued)
Frames received on a ring port must have an out-of-band pretag in the clock cycle before Mxx_RXDV is
asserted. The contents of the pretag are examined, and based on the results, are either forwarded normally,
or immediately discarded within the MAC. If discarded, the frame does not affect any of the statistics or
address-lookup database. Frames are forwarded normally, unless:
–
–
–
The pretag is 0.
The two IDs within the pretag are not the same.
The ID within the received pretag is the same as ringid. This identifies a frame that originated at this
device, and that has passed completely around the ring.
The pretag format is shown in Figure 8.
M08_GTCLK
M08_TXEN
M08_RXDV
M08_TXD3–
M08_TXD0/
M08_RXD3–
M08_RXD0
Ring ID
Ring ID
Preamble
Preamble
M08_TXD7–
M08_TXD4/
M08_RXD7–
M08_RXD4
Figure 8. Ring-Topology Pretag Timing
The devices in the ring are connected as shown in Table 13.
Table 13. Ring-Topology Connectivity
SWITCH TERMINAL
n
n + 1
M08_TXD7
M08_TXD6
M08_TXD5
M08_TXD4
M08_TXD3
M08_TXD2
M08_TXD1
M08_TXD0
M08_TXEN
M08_TXER
M08_COL
→
→
→
→
→
→
→
→
→
→
←
M08_RXD7
M08_RXD6
M08_RXD5
M08_RXD4
M08_RXD3
M08_RXD2
M08_RXD1
M08_RXD0
M08_RXDV
M08_RXER
FLOW
NOTE: When a port is configured for the ring
topology, IEEE Std 802.3x flow control
should be disabled. Hardware-based
flow control is supported using the
FLOW and Mxx_COL terminals;
however, this must be enabled by
setting the flow bit in SysControl.
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
EEPROM interface
The EEPROM interface is provided so the system-level manufacturer can produce a CPU-less preconfigured
system. This also can be used to change or reconfigure the system and retain the preferences between system
power downs.
The EEPROM contains configuration and initialization information that is accessed infrequently, typically at
power up and after a reset. The organization of the EEPROM data is shown in the DIO address map. Downloads
are initiated in one of two ways:
At the end of hard reset (rising edge on RESET)
Writing a 1 to load in SysControl register. This bit is cleared automatically when the download completes.
It cannot be set during the download by the EEPROM data, thereby preventing a download loop.
During the download, no DIO writes are permitted. (If a DIO write is attempted, SRDY is held high until the
download has completed.)
Either a 24C02 or 24C08 serial EEPROM device can be used. Both use a two-wire serial interface for
communication and are available in a small-footprint package.
The 24C02 provides 2048 bits, organized as 256 × 8. Downloading data from the EEPROM initializes DIO
addresses 0x0000 through 0x00FB. These registers control all initializable functions except VLANs. The
downloading sequence starts with DIO address 0x0000, continuing in ascending order to 0x00FF.
The 24C08 provides 8192 bits, organized as 1024 × 8. Downloading data from the EEPROM initializes DIO
addresses 0x0000 through 0x03FF. These registers control all initializable functions, including VLANs. The
downloading sequence starts with DIO address 0x0100, continuing in ascending order to 0x03FF, followed
by address 0x0000, continuing in ascending order to 0x00FF. This ensures that SysControl is the last
register loaded.
The EEPROM size is detected automatically according to the address assigned to the EEPROM:
2048 bits, organized as a 256 × 8 EEPROM, should have its A0, A1, and A2 terminals tied low.
8192 bits, organized as a 1024 × 8 EEPROM, should have its A0 and A1 terminals tied low and A2 terminal
tied high (see Figure 9).
EDIO
TNETX4090
ECLK
SCL
24C0x
SDA
Flash EEPROM
A0 A1 A2
24C02: GND
24C08: V
DD
GND
Figure 9. Flash EEPROM Configuration
42
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
EEPROM interface (continued)
After the initial start condition, a slave address containing a device address of 000 is output on EDIO, and then
EDIO is observed for an acknowledge from the EEPROM. If an acknowledge is received, operation continues
for the 24C02 EEPROM. If none is received, a stop condition is generated, followed by another start condition
and slave address, this time containing a device address of 101. If this receives no acknowledge, no EEPROM
is present, and device operation continues, using the current register settings (i.e., those following a hardware
reset, or those previously entered by software).
When this device is driving EDIO, it drives out only a strong logical 0. When a logical 1 is intended to be driven
out, the terminal must be resistively pulled high. An on-chip 50-µA current-source pullup device is provided on
this terminal. The system designer must decide if this is sufficient to achieve a logical 1 level in a timely manner
or if an external supplementary resistor is required.
Multiple bus masters are not supported on the EEPROM interface because the ECLK terminal always is driven
by the device with a strong 0/strong 1 (i.e., not a strong 1/resistively pulled-up 1).
An Ethernet CRC check is used to ensure the EEPROM data is valid. The 4-byte CRC should be placed within
the EEPROM in four data bytes immediately following the last byte to be loaded (equivalent to locations
0x00FC–0x00FF, just above SysControl). As each byte is loaded from the EEPROM, the bits within that byte
are entered into the CRC checker bit-wise, most significant bit first.
A valid CRC always must be provided by the EEPROM. The EEPROM data for the most significant bit of
SysControl is withheld until the CRC computed by the device has been checked against the one read from the
EEPROM. If the CRC is invalid:
The reset bit is set to 1 in SysControl, load and initd are both 0, and the TNETX4090 does not begin
operation.
The fault LED is illuminated and remains in that state until the TNETX4090 is hardware reset or until load
in SysControl is set to 1.
interaction of EEPROM load with the SIO register
The EDIO terminal is shared with the SIO register edata bit. The edata and etxen bits must not both be set to
1 when the load bit is set or the EDIO terminal is held at resistive 1 and the EEPROM load fails.
The value of the eclk bit in SIO is don’t care when load is set, but to ensure the EEPROM does not see a glitch
on its clock signal, the load bit should not be set until the minimum clock high or low time required by the
EEPROM on its clock signal has expired since the eclk bit was last changed.
The SIO register is not loaded during the EEPROM download.
summary of EEPROM load outcomes
Table 14 summarizes the various states of register bits and the fault LED for each possible outcome following
an EEPROM load attempt.
Table 14. Summary of EEPROM Load Outcomes
†
OUTCOME
Successful load
STOP
LOAD INITD
FAULT LED
ECLK
‡
0
0
1
0
0
0
1
0
0
0
0
Not locked
Locked
‡
No EEPROM present
CRC error detected
1
Not locked
†
‡
Assuming the start bit was set to 1 by the EEPROM load
Assuming the fault bit in LEDControl = 0 and no memory system parity error is detected
43
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
compatibility with future device revisions
All EEPROM locations that correspond to reserved addresses in the memory map, register bits that are read
only, and register bits that are marked as reserved should be set to 0 to ensure compatibility with future versions
of the device. Failure to do so may result in the unintentional activation of features in future devices. All such
bits are included in the CRC calculation.
LED interface
This interface allows a visual status for each port to be displayed. In addition, the state of the internal flow control
and fault functions are displayed along with 12 software-controllable LEDs.
Each port has a single LED that can convey three states, as shown in Table 15.
Table 15. Port LED States
STATE
No link
DISPLAY
Off
On
Link, but no activity
Activity
Flashing at 8 Hz
Port 08 has an additional LED, C08, to indicate the occurrence of a collision when operating in PMA mode; this
LED also has three states, as shown in Table 16.
Table 16. Collision LED States
STATE
DISPLAY
No collision (or non PMA mode)
Occasional collision
Off
On
Frequent collisions
Flashing at 8 Hz
The interface is intended for use in conjunction with external octal shift registers, clocked with LED_CLK. Every
1/16th of a second, the status bits are shifted out via LED_DATA.
The status bits are shifted out in one of two possible orders, as determined by slast in LEDControl, to ensure
that systems that do not require all the LED status can be implemented with the minimum number of octal shift
registers.
If slast = 0, the software-controlled status bits are shifted out before the port status bits.
If slast = 1, the software-controlled status bits are shifted out after the port status bits.
The fault status bit is shifted out last, enabling a minimal system that displays only the fault status to be
implemented without any shift registers.
44
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Table 17. LED Status Bit Definitions and Shift Order
ORDER
NAME
FUNCTION
slast = 0
slast = 1
Software LEDs 0–11. These allow additional software-controlled status to be displayed. These
12 LEDs reflect the values of bits 0–11 of the swied field in LEDControl at the moment that the LED
interface samples them. If this occurs between writes to the most significant and least significant
bytes of LEDControl, these values appear on the LEDs, separated by 1/16th of a second.
1st–12th
11th–22nd SW0–SW11
PortstatusLEDs0–8. ThesenineLEDsindicatethestatusofports0–8, inthisorder(port0isoutput
first). Note that port 9 (management port) does not have an LED. The transmit multicast content
of these bits can be controlled by the txais bit in LEDControl. Note that IEEE Std 802.3x pause
frames never appear on the LEDs as port activity. The port’s LED toggles each 1/16th of a second
if there was any frame traffic (other than pause frames) on the port during the previous 1/16th of
a second.
13th–21st
1st–9th
P00–P08
Port 8 collision LED. LED is extinguished if port 8 is not in PMA mode. It indicates the collisions on
port8andtoggleseach1/16thofasecondifthereisacollisionontheportduringtheprevious1/16th
of a second.
22nd
23rd
10th
23rd
C08
Flow control. LED is on when the internal flow control is enabled and active. Active means that flow
control was asserted during the previous 1/16th of a second.
FLOW
Fault. LED indicates:
– the EEPROM CRC was invalid.
– an external DRAM parity error has occurred.
24th
24th
FAULT
– the FITLED in LEDControl has been set. The CRC and parity error indications are cleared
by hardware reset (terminal or DIO). The CRC error indication also is cleared by setting load
to 1. The parity error indication also is cleared by setting start to 1.
lamp test
When the device is in the hardware reset state, LED_DATA is driven low and LED_CLK runs continuously. This
causes all LEDs to be illuminated and serves as a lamp test function.
multi-LED display
The LED interface is intended to provide the lowest-cost display with a single multifunction LED per port. In
systemsrequiringafull-featuredisplayusingmultipleLEDsperport, thisisachievedbydrivingtheLEDsdirectly
from the PHY signals.
PCS duplex LED
This device includes a single 1000-Mbit/s port, which has an associated LED used to display the configuration
oftheincorporatedPCS. WhenthePCSisenabledandconfiguredforfull-duplexoperation, L08_DPLXisdriven
low, causinganyattachedLEDtobeilluminated. Atallothertimes, exceptduringlamptest, thisterminalisdriven
high.
RDRAM interface
The TNETX4090 requires the use of external memory devices to retain frame data during switching operations.
The high bandwidth requirements of gigabit-per-second Ethernet switching are met using a concurrent RDRAM
interface (see Rambus Layout Guide, literature number DL0033).
EachRDRAM interface operates at 600-Mbit/pin/s and is intended for use with 16-/18-/64-/72-Mbit/s concurrent
RDRAMs with access times of 50 ns. The TNETX4090 automatically determines the word length of the
RDRAMs during initialization and performs parity checks if 9-bit memories are in use.
A maximum of 16 RDRAM devices of differing organizations can be attached to any one RDRAM interface.
Multiple devices must be daisy-chained together via their SIN and SOUT terminals during initialization (see
Figure 10). All RDRAMs in a given system must be of the same type.
45
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
TNETX4090
V
CC
NC
9
V
V
DD
GND
TXCLK
REF
5
13
RXCLK
Concurrent
RDRAM
BUS ENABLE
BUS CTRL
BUS DATA (8–0)
S
IN
OUT
S
SCHAIN0
V
V
DD
GND
TXCLK
REF
5
13
RXCLK
Concurrent
RDRAM
BUS ENABLE
BUS CTRL
BUS DATA (8–0)
S
IN
OUT
S
SCHAIN1
V
V
DD
GND
TXCLK
REF
5
13
RXCLK
Concurrent
RDRAM
BUS ENABLE
BUS CTRL
BUS DATA (8–0)
S
IN
OUT
S
SCHAIN15
Clock
Source
NC – No internal connection
Figure 10. Multiple RDRAM Module Connections
46
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
JTAG interface
The TNETX4090 is fully IEEE Std 1149.1 compliant. It also includes on-chip pullup resistors on the five JTAG
terminals to eliminate the need for external ones. The instructions that TI supports are:
Mandatory (EXTEST, BYPASS, and SAMPLE/PRELOAD)
Optional public (HIGHZ, IDCODE, and BIST)
Private (various private instructions are used by TI for test purposes)
The opcodes for the various instructions (6-bit instruction register) are shown in Table 18.
Table 18. JTAG Instruction Opcodes
INSTRUCTION
TYPE
INSTRUCTION
NAME
JTAG
OPCODE
Mandatory
Mandatory
Optional
Optional
Optional
Private
EXTEST
SAMPLE/PRELOAD
IDCODE
000000
000001
000100
000101
000110
Others
111111
HIGHZ
RACBIST
TI testing
Mandatory
BYPASS
HIGHZ instruction
When selected, the HIGHZ instruction causes all outputs and bidirectional terminals to become high
impedance. All pullup and pulldown resistors are disabled.
RACBIST instruction
The RACBIST instruction invokes a built-in self test of the RAC and the rambus channel. This tests the integrity
of the connection between the TNETX4090 and the external RDRAMs. When selected, the value of the test can
be read via JTAG DR SCAN. A 2-bit status value is reported (see Table 19).
Table 19. JTAG BIST Status
PASS
(BIT 1)
COMPLETE
(BIT 0)
When bit 0 = 1
*0 = fail
*0 = BIST running
*1 = BIST complete
*1 = pass
The IDCODE for the TNETX4090 is shown in Table 20.
Table 20. JTAG ID Code
VARIANT
PART NUMBER
BIT 28 BIT 27 BIT 12 BIT 11
1011000111110111 00000010111
MANUFACTURE
LEAST SIGNIFICANT BIT
BIT 31
BIT 1
BIT 0
0000
1
47
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
frame routing
VLAN support
The internal routing engine supports the IEEE Std 802.1Q VLANs as shown in Figure 11 and described in the
following paragraphs.
Receive
Record
Number
IEEE Std
Non-
IEEE Std
802.1Q
Format
Frame
802.1Q
Format
Frame
VLAN ADDR
Port Information
Reset to
All 0s
Port Numbers,
Time Stamps
Locked, Secure,
NBLCK, New
VLAN and
Ethernet
Addresses
Reset is
Don’t Care
Header
Source
and
Destination
Lookups
If rxacc = 1
Header Inserted
Header
Possibly
Inserted
Source Address (SA)
Destination Address (DA)
Header
Inserted
If VLAN ID = 0x000
VLAN ID Replaced
No
Match
Port
Information
Reset 0x0001
SA
VLANnQID
VLAN
VLAN
DA
Source Port’s Inserted
PortxQTag VLAN ID
Header
Unicast/
Multicast
VLAN ID
Lookup
Index
Frame-Routing
Algorithm
Nauto
UnkVLAN
UnkUniPorts
UnkMultiPorts
UnkSrcPorts
UnkVLANPort
TxBlockPorts
RxUniBlockPorts
RxMultiBlockPorts
MirrorPort
Reset
Queue
Manager
1st Location:
0x001
No Match
Lshare
Nage
SysControl
All Others:
0x000
Mirror
Source Port Number
RAM
UplinkPort
TrunkMapx
TrunkxPorts
Port Routing Code
Destination
Port’s
Disable
All Ports
PortxControl
PortxQTag
Queue
NLearnPorts
Manager
VLAN
Ports
Header
VLANnPorts
Reset to
All 1s
Compare
VLAN IDs
IALE
Header
Stripped
Header
Retained
If (equal or
txacc = 1)
Then Strip Header,
Otherwise,
IEEE Std
Non-
802.1Q
Format
Frame
IEEE Std
802.1Q
Format
Frame
Keep Header
Header
Transmit
Figure 11. VLAN Overview
48
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
IEEE Std 802.1Q tags – reception
By the time the IALE examines the received frame, it contains an IEEE Std 802.1Q tag header (after the source
address). The tag used depends on the port configuration. If the port is configured as an access port, IALE
always uses the default VID programmed for this port and assumes that all received frames on this port are
untagged. If the frame already contained a tag, it is tagged again. If the port is programmed as a non-access
port, thetagaddeddependsonthereceivedframe. Iftheframeisnottaggedorthevalueofthetagfieldis0x000,
the default port VID is used to internally tag the frame. Otherwise, the VID contained in the frame is used by
the IALE.
The IALE supports 64 of the possible 4096 VIDs that can be encoded within the IEEE Std 802.1Q tag. The VID
in the received frame is compared with these 64 VLAN IDs to see which (if any) of them it matches.
unknown VLAN
If there is no match, the rest of the address-lookup process is abandoned. A new VLAN interrupt is provided
to the attached CPU. The source address, VLAN ID, and port information is provided in internal registers so that
the CPU can determine if it wants to add this VID to the lookup table. If the destination address is unicast, the
frame is discarded. If the destination address is a multicast/broadcast, the frame is forwarded based on a
programmable port mask.
known VLAN
If there is a match, the VLAN index associated with this VID, together with the destination and source address,
are forwarded to the address lookup and subsequent routing process. (Only one of the VIDs matches if they
have been programmed correctly. If more than one matches, the hardware chooses one of them.)
new VLAN member
The IALE checks to see if the source port already has been declared as a member of this VLAN. If not, an
interrupt is provided to allow the attached CPU to add this port as a new member of the VLAN.
IEEE Std 802.1Q header – transmission
The IEEE Std 802.1Q header is carried within the frame to the transmitting MAC port, where the decision to strip
out the header before transmission is made, based on the port configuration. If the port is configured as an
access port, the tag is stripped before transmission. If the frame is only 64 bytes long, four bytes of pad (0s)
are inserted between the end of the data and the start of the CRC word (a new CRC value is calculated and
inserted in the frame). Three, two, and one byte(s) are inserted for 65-, 66-, and 67-byte frames, respectively.
If the port is configured as a nonaccess port, the VID is compared with the default port VID. If they match, the
header is stripped; otherwise, the header is retained.
If the frame is transmitted to the NM port, no header stripping occurs; the frame is transmitted unaltered. It may
contain one or two IEEE Std 802.1Q headers, depending on how the frame is received.
address maintenance
The addresses within the IALE can be maintained automatically by the TNETX4090, where addresses are
learned/updated from the wire and deleted using one of two aging algorithms looked up during frame-routing
determination. Multicast addresses are not automatically learned or aged. The attached CPU can add/update,
find, or delete address records (see TNETX4090 Programmer’s Reference Guide, literature number SPAU003,
for details) via the DIO interface.
The learning and aging processes are completely independent. This allows addresses to be automatically
learned from the wire, but allows the CPU to manage the aging process under software control.
spanning-tree support
Each port provides independent controls to block reception or transmission of frames, learning of addresses,
or disable the port on a per-port basis. Blocking can be overridden to allow reception or transmission of
spanning-tree frames.
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ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
aging algorithms
time-threshold aging
When learning addresses, the IALE adds the address to the table and tags it with a time stamp. If another frame
is received with this address, the time stamp is refreshed. If the aging counter expires before another frame is
received from this source address, the address is deleted from the table. If the table is full, the oldest address
is deleted to make room for a new address, even if the age for this address has not expired.
table-full aging
In table-full aging, the oldest address (or one of the oldest addresses if there is more than one) automatically
is deleted from the IALE records only if the table is full, and a new address must be added to the table. In this
mode, the age stamp for the addresses is not refreshed.
frame-routing determination
When a frame is received, its 48-bit destination and source addresses are extracted and the VLAN index is
determined as described in VLAN Support. The destination address and VLAN index are then looked up in the
IALE records to determine if they exist. If a match is found, the information associated with the record is passed
on to the frame-routing algorithm. Figure 11 provides a flow diagram of the routing algorithm. For details of the
register information referred to in Figure 11, see the TNETX4090 Programmer’s Reference Guide, literature
number SPAU003.
The source address and VLAN index combination also are looked up in the IALE records to determine if they
exist. If a match is found, additional information is provided to the routing process (for details see the
TNETX4090 Programmer’s Reference Guide, literature number SPAU003).
50
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ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Start
Key:
interrupt
UnkVLAN
No
Known
VLAN?
statistic
Yes
Unkmem
No
Source Port = 1 in.
VLANnPorts?
Yes
Destination
Address
Found?
Yes
No
Destination
Locked
Destination
is
Destination
is
Destination
is
Yes
No
No
No
Bit = 1?
Multicast?
Multicast?
Multicast?
No
Yes
Yes
Yes
Source Port
Blocked by
RxMultiBlockPorts
and Dest.
Source Port
Blocked by
RxUniBlockPorts
and Dest.
Source Port
Blocked by
RxMultiBlockPorts or
UnkVLAN=0?
Source Port
Blocked by
RxMultiBlockPorts?
Source Port
Blocked by
RxUniBlockPorts?
Yes
Nblck=0?
Nblck=0?
Yes
Yes
Yes
Yes
No
No
No
No
No
Port Routing
Code = Port Code
From Records
Port Routing
Code = Port Vector
From Records
Port Routing
Code =
UnkMultiPorts
Port Routing
Code =
UnkUniPorts
Port Routing
Code =
UnkVLANPort
Unknown
Multicast
Destination
Unknown
Unlcast
Destination
Set Port Routing
Code to 0
Include UplinkPort
in Port
Routing Code
AND Port Routing
Code With VLAN
VLANnPorts Code
Destination
Cuplink Bit
Set?
Yes
No
To A
(Continued)
To B
(Continued)
To C
(Continued)
Figure 12. Frame-Routing Algorithm
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SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
A
B
new
Source
Port = 1 in
Source
No
No
Address
NLearnPorts?
Found?
Yes
Source
Yes
Locked
Bit = 1?
No
Source
No
AND UnkSrcPorts
With VLAN
VLANnPorts,
Port
Moved?
Yes
Then OR With
Port Routing Code
Yes
Unknown
Source
secvio
Source
Secure
Bit = 1?
Stayed
Within a
Trunk?
Yes
No
Source
Port
Security
Violation
No
Yes
chng
Discard
Frame
Yes
Source
Port = 1 in
Yes
RingPorts?
No
Remove Source Port
(and other trunk members)
From
Port Routing Code
To C
(Continued)
Figure 12. Frame-Routing Algorithm (Continued)
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ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
E
C
D
Remove:
– Disabled Ports
– Ports Blocked by TxBlockPorts
From Port Routing Code
If
[(Source Port = MirrorPort or
Port Routing Code Includes MirrorPort)
and (Source Port ! = UplinkPort)]
Yes
Mirr
Bit = 1?
Then
Include UplinkPort in Port Routing Code
No
Yes
No
Destination
Found?
Lshare = 1?
No
Port Routing Code
is Adjusted by
Load-Sharing
Algorithm
(see Note A)
Yes
Port Routing Code
is Adjusted by
Trunking Algorithm
(see Note A)
Yes
Discard
Frame
Port Routing
Code = 0?
No
Send Frame to
Ports Indicated by
Port Routing Code
NOTE A: See Port Trunking/Load Sharing
Figure 12. Frame-Routing Algorithm (Continued)
port routing code
The IALE creates a port routing code in which each bit (marked with a 1) represents a potential destination port
for the frame. This code is modified as it proceeds through the frame-routing algorithm. If the final code is all
0s, then the frame is discarded. If it is not, then the frame is transmitted on every port marked by a 1 within the
code.
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SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
removal of source port
Normally, the IALE does not route a frame to a port on which it was received. The port routing code is examined
to see if the source port is included. If so, the port routing code is modified to remove the source port.
IfthebitinRingPortscorrespondingtotheportthatreceivedtheframeisset, theportroutingcodeisnotmodified
to remove the source port. This is required for connecting the port to other like switches in a ring topology.
If the source port is a member of a trunk (see Trunking), then all the other ports that are members of the same
trunk also are removed from the port routing code.
port mirroring
It is possible to copy (or mirror) all frames that are received by and transmitted from a port to another designated
port, using the mirror port register.
It also is possible to mirror frames destined for a particular MAC address by using the copy-uplink feature. When
a frame specifies the destination address with the copy-uplink feature enabled, frames are copied to the
specified port.
copy-to-uplink (cuplink)
If destination address is a unicast and the cuplink bit of its address record has been set to a 1 (via a DIO add),
and when a frame specifies that destination, a copy of the frame is sent to the port specified in the UplinkPort
register.
port trunking/load sharing
Trunking allows two or more ports to be connected in parallel between switches to increase the bandwidth
between those devices. The trunking algorithm determines on which of these ports a frame is transmitted, so
that the load is spread evenly across these ports.
The TNETX4090 supports a maximum of four trunk groups for the 10-/100-Mbit ports. The port members of a
trunk group are software configurable via the DIO interface. Trunk-port determination is the final step in the IALE
frame-routing algorithm. Once the destination port(s) for a frame have been determined, the port routing code
is examined to see if any of the destination port(s) are members of a trunk. If so, the trunking algorithm is applied
to select the port within the trunk that transmits the frame – it may or may not be the one currently in the port
routing code. To determine the destination port within a trunk, bits 3–1 of the source and destination address
are XORed to produce a map index. This map index is used to index to a group of eight internal registers to
determine the destination port (for details see the TNETX4090 Programmer’s Reference Guide, literature
number SPAU003). Port trunking uses the destination/source address pairs to route the traffic to balance the
load more evenly across the trunked ports. Since the same destination/source address pair always uses the
same port to route the traffic, this also makes it much easier to debug network problems.
Load sharing is similar to trunking , but with two slight differences. It uses the trunking algorithm only once when
the destination address is unknown. Once the destination address has been learned, it uses the port routing
code associated with the destination address.
If the destination is unknown, the map index is derived from only the source address. If a server is
communicating with a large number of different clients, then, since the source address is the same, it is possible
to have very poor traffic distribution.
If the destination address is found in the IALE records when it is looked up, the port routing code is not
adjusted by the load-sharing algorithm.
The 3-bit map index is determined only from the source address, as follows:
–
–
–
Bits 47–32 are XORed to produce the most significant bit of the map index.
Bits 31–16 are XORed to produce the middle of the map index.
Bits 15–0 are XORed to produce the least significant bit of the map index.
54
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SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
port trunking example
This example shows how to set up the TNETX4090 to support two port trunks. The first trunk group consists
of ports 1, 3, 5, and 7 (see Table 21); the second trunk group consists of ports 0, 2, and 6 (see Table 22).
Table 21. Trunk Group 0 Port Membership (Trunk0Ports Register)
PORT
7
6
5
4
3
2
1
0
1
0
1
0
1
0
1
0
Table 22. Trunk Group 1 Port Membership (Trunk1Ports Register)
PORT
7
6
5
4
3
2
1
0
0
1
0
0
0
1
0
1
The TrunkMapx registers are used to control the distribution of traffic across the ports within a trunk group. In
this example, the traffic for trunk group 0 has been equally distributed 25% (this assumes that bits 3–1 of the
MAC addresses are random enough to give an even distribution) for each of the four ports in the trunk. For any
given source and destination address pair, the traffic always uses the same port within the trunk. This ensures
that packets do not get disordered on the trunk ports. Note that, since port 4 is not a member of any port trunk
group, all the entries for this port have been set to 1. In fact, functionally, this can be thought of as a single port
trunk.
Table 23. TrunkMapx Register Settings (for Traffic Distribution on Trunk Groups 0 and 1)
TRUNK PORT
MAP
INDEX
7
0
0
0
1
0
0
0
1
6
1
0
0
1
0
0
1
0
5
0
0
1
0
0
0
1
0
4
1
1
1
1
1
1
1
1
3
0
1
0
0
0
1
0
0
2
0
1
0
0
1
0
0
1
1
1
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
1
2
3
4
5
6
7
extended port awareness
When the port routing code is derived from an xportcode field, which has its most significant bit set (1xxxxx)
indicating a port on an external crossbar matrix connected to port 8, the port-8 bit in the port routing code is set,
and the five least significant bits of xportcode are used to create the pretag transmitted with the frame.
When bit 8 of the port routing code is set by a portvector field, the xroutecode field associated with the portvector
is used to create the pretag transmitted with the frame (either directly if xroutecode is in the range
000000–010000, or indirectly via a lookup in the XMultiGroup17–XMulUGroup63 registers if xroutecode is in
the range 010001–111111).
55
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SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
flow control
The TNETX4090 supports collision-based flow control for ports in half-duplex mode and IEEE Std 802.3x flow
control for ports in full-duplex mode. The flow bit in the SysControl register determines the action that will be
taken when back pressure is needed, that is, when there are insufficient resources to handle an inbound packet.
The holb bit in the SysControl register determines when back pressure is needed.
If flow = 0, packets are discarded at the ingress port when insufficient resources are available to handle
them.
If flow = 1, ports in half-duplex mode cause collisions to avoid accepting packets, ports in full-duplex mode
whose link partners negotiated to accept pause packets will send them; otherwise, packets are dropped.
If port 8 is in MII mode, the pause-frame transmission/reception is required to be symmetrical. If in GMII or
PMA mode, transmit and receive pause capabilities are negotiated independently.
With holb = 0, back pressure is applied to all ports when the number of buffers in the global pool is down
to the value in the FlowThreshold register (or half of this value if the packet arrives at a port in gigabit mode).
This prevents the reception of more frames at any port until the frame backlog is reduced and the number
of free buffers has risen above the threshold. When this happens, back pressure is removed from all ports
and packets can be received. The value in FlowThreshold should be set so that all ports can complete
reception of a maximum-size frame, that is, each port should have enough time to activate the flow
mechanisms without dumping a frame for which reception has started.
If holb = 1, back pressure is applied as when holb = 0, or to an individual port when the buffers held in
memory for data that arrived on that port is greater than the available pool remaining. Assume that
FlowThreshold is set small enough that this mechanism does not affect the back pressure in this mode. An
example is:
–
WhenportA’strafficbeginstobackloginmemory[nomattertowhatport(s)itisdestined], backpressure
will be applied when the amount of data backed up is greater than the available pool (about half the
buffers are assigned to data from port A). If A’s data stays backlogged and if data arriving at port B also
beginstobackloginmemory, backpressurewillbeappliedtoportBwhenitsdataamountstoone-fourth
of the buffer pool, or half of the half left after port A had back pressure applied. When port A’s traffic
begins to exit the switch, port A will stay back pressured until its data is equal to one third of the total. As
buffers become available, port B will be allowed to consume up to one third of the buffer pool (each
backlogged total is compared with the buffers available). In this mode, only the stations that have
caused their fair share of buffers to be removed from the available pool will be back pressured.
Setting holb = 1 activates circuitry that attempts to prevent a backlogged conversation stalling other port
traffic by using up all the memory buffers. Because the number of buffers charged to a particular port is
always compared with the number of buffers left, there is no threshold register for this mode.
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SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
other flow-control mechanisms
hardware flow control
If a port were in MII or GMII mode and full duplex, normally, its Mxx_COL would not be needed. Hardware flow
control has been added by preventing the start of a frame transmission if the Mxx_COL is high. This is useful
in ring mode; the Mxx_COL can be tied to the FLOW of the upstream neighbor for hardware flow control.
multicast limit
Because buffer resources for multicast (or broadcast) frames are released only when the last port has
transmitted the frame, multicast packets to fast and slow ports are released at the slow-port rate. Multicast traffic
from a fast port to a slow port could cause back pressure to be applied to the source port, blocking input from
that port. This occurs even if at least one of the ports in the multicast could have kept pace with the inbound
multicast packets. The MCastLimit register can limit the number of multicast packets allowed to be pending at
any output port. When the limit is reached, that port is not added to the routing vector of the next multicast packet
for which it was eligible. Eligibility is restored when the number of backlogged packets is again below the limit.
MCastLimit allows the user to set the ports subject to this restriction, and set the limit in 8 binary steps, from
2 to 256. The spanning-tree BPDU multicast packet is exempt from this limit.
other behavior changes resulting from flow-control bits or terminals
Clearing (the default) holbrm in the RingPorts register includes the test for buffer use controlled by the holb bit
in SysControl into the action of the FLOW terminal. FLOW goes high if either the number of buffers left is less
than the FlowThreshold value or a ring-mode port receive operation has exceeded its fair share of buffers.
Setting holbrm = 1 makes FLOW respond only to FlowThreshold value violations.
system test capabilities
RDRAM
The external RDRAM can be read and written using regular DIO accesses following a stop. Individual bytes can
be read and written. However, as the RDRAM memory is actually accessed in 128-byte pages, performing
128-byte accesses is the most efficient.
To access the RDRAM, the TNETX4090 must not be operating. The user must perform a reset and not set start
in SysControl. Both start and initd in SysControl must be 0. In addition, rdinit in SysTest must be set, indicating
that the RDRAM has initialized. This initialization sequence occurs automatically after a hard reset.
Read or write accesses to RDRAM are invoked via rdram and rdwrite in SysTest. Setting rdram to 1 causes a
128-byte transfer between the device and the RDRAM memory to be initiated.
The transfer direction is determined by rdwrite.
The external memory byte address for the access is specified by ramaddress in RAMAddress.
Data to be read from or written to RDRAM is accessed indirectly via RAMData.
writing RDRAM
Writing to RDRAM memory is accomplished as follows:
1. Write the byte address for the access to ramaddress in RAMAddress.
2. Write the data for the access to RAMData. Up to 64 bytes can be written, if all but the six least significant
bits of the address are the same for all the data. Inc in RAMAddress can be used to autoincrement the
address.
3. Set rdwrite = 0 and rdram = 1 (these can be written simultaneously).
4. If required, poll rdram until it becomes 0. This indicates that the write has completed.
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SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
reading RDRAM
Reading from RDRAM memory is accomplished as follows:
1. Write the byte address for the access to ramaddress in RAMAddress.
2. Set rdwrite = 1 and rdram = 1 (these can be written simultaneously).
3. Poll rdram until it becomes 0. This indicates that the read has completed.
4. Read the data for the access to RAMData. Up to 64 bytes can be read, provided that all but the six least
significantbitsoftheaddressarethesameforallthedata. IncinRAMAddresscanbeusedtoautoincrement
the address.
internal wrap test
Internal wrap mode causes some or all of the Ethernet MACs to be configured to loop back transmitted data
into the receive path. This allows a frame to be sent into a designated source port and then selectively routed
successively to and from ports involved in the test, before finally transmitting the frame out of the original port.
By varying the number of ports between which the frame is forwarded, the potential fault capture area is
expanded or constrained.
Intwrap in SysTest determines which ports loop back. Ports 0 or 8 can be configured to not loop back, allowing
them to be used as the start/end port for the test. Alternatively, the NM port (accessed via DIO) can be used
for this purpose, with all MII ports configured to loop back.
For a frame to be forwarded from one port to another in this fashion, the switch must be programmed as follows:
Assign a unique VID to each of the PortxQTag registers, and program these tags into the VLANnQID
registers.
The VLANnPorts register associated with each of the VLANnQID registers should have only one bit set,
indicating to which port frames containing that IEEE Std 802.3 tag should be routed.
Rxacc and Txacc for each port must be 1. This causes the port to add the VID from its PortxQTag to the
frame on reception, and strip the tag before transmission.
The destination address of the frames to be applied is not known, and UnkUniPorts and UnkMultiPorts
should be all 1s.
This causes the following:
1. The VID from the source port PortxQTag register is added to the frame upon reception. As the address of
the frame is unknown, it is forwarded to the AND of the appropriate VLANnPorts and UnkUniPorts (unicast)
or UnkMultiPorts (multicast). As VLANnPorts should contain only a single 1, this should be a single port.
2. The frame is transmitted from the destination port selected in 1. Its VLAN tag is stripped beforehand; the
frame loops back to the receive path.
3. Steps 1 and 2 are repeated, but the VID added upon reception is different from the one just stripped off at
transmission. This means a different VLANnPorts register is used to determine the destination.
The port order shown here is sequential, but the actual order depends on how ports are paired in the
VLANnPorts registers, and how the PortxQTag registers are assigned.
4. Eventually, the frame is sent to a port that is not configured for loopback, and leaves the switch.
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ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
internal wrap test (continued)
08
07
06
05
04
NM
00
TNETX4090
03
02
01
Figure 13. Internal Wrap Example
The operational status of the PHYs or external connections to the device do not have to be considered or
assumed good, when in internal loopback mode.
duplex wrap test
Duplex wrap test is similar to internal wrap mode (see Figure 13). The ports can be set to accept frame data
that is wrapped at the PHY. This permits network connections between the device and the PHY to be verified.
Any port can be the source port (not just the NM port as shown in Figure 14). By using multicast/broadcast
frames, traffic can be routed selectively between ports involved in the test or return the frame directly before
retransmission on the uplink. Software control of the external PHYs is required to configure them for loopback.
If the internal PCS is in use (port configured in PMA mode) loopback in PCSxControl also must be asserted.
This causes Mxx_EWRAP to be high, forcing external PMD into loopback mode.
Duplex frame-wrap test mode is selected by setting dpwrap in SysTest. When selected, the port is forced into
full duplex, allowing it to receive frames it transmits.
The switch is configured in the same manner as internal wrap.
08
PHY
PHY
07
06
05
04
TNETX4090
NM
00
03
02
01
Figure 14. Duplex Wrap Example
59
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ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 2.7 V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
DD(2.5)
DD(3.3)
DD
Supply voltage range, V a (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 2.7 V
Supply voltage range, DVREF (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V to 2.2 V
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.4 V
+ 0.5 V
I
DD(3.3)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
DD(3.3)
Output voltage range, V
O
Input voltage range (RSL), V
Output voltage range (RSL), V
Thermal impedance, junction-to-ambient package, Z
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DVREF – 0.35 to DVREF + 0.8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.0 to V
IR
OR
DD(2.5)
: Airflow = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 11.11°C/W
θJA
Airflow = 100 ft/min . . . . . . . . . . . . . . . . . 9.61°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.94°C/W
Thermal impedance, junction-to-case package, Z
Operating case temperature range, T
Storage temperature range, T
θJC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
C
stg
†
Stresses beyond those listed under “absolute maximum ratings” can cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
MIN NOM
MAX
2.7
UNIT
V
V
V
Supply voltage
2.5
3
2.6
3.3
2.0
DD(2.5)
Supply voltage
3.6
V
DD(3.3)
DVREF
RSL reference voltage
1.8
0
2.2
V
V
V
V
V
Input voltage
V
V
V
V
I
DD(3.3)
Output voltage
0
V
O
DD(3.3)
High-level input voltage
2
V
IH
IL
DD(3.3)
Low-level input voltage (see Note 2)
High-level output current
Low-level output current (except LED_DATA)
LED_DATA (terminal AE19)
High-level input voltage (RSL)
Low-level input voltage (RSL) (see Note 2)
High-level output current (RSL)
Low-level output current (RSL)
0
0.8
–2
2
V
I
I
I
mA
mA
mA
V
OH
OL
OL
0
DVREF+0.35
DVREF–0.35
–10
8
V
IHR
V
ILR
DVREF+0.8
DVREF–0.8
V
I
I
10
80
µA
mA
OHR
0
OLR
NOTE 2: The algebraic convention, in which the more-negative (less-positive) limit is designated as a minimum, is used for logic-voltage levels
only.
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
= rated
MIN
TYP
MAX
UNIT
V
V
V
High-level output voltage
Low-level output voltage
I
I
V –0.5
DD(3.3)
OH
OH
= rated
0.5
V
OL
OL
High-impedance-state output
current
I
V
O
= V or GND
±10
µA
OZ
DD
I
I
High-level input current
V = V
IH
1
µA
µA
V
IH
I
Low-level input current
V = V
I
–1
IL
IL
V
High-level output voltage (RSL)
Low-level output voltage (RSL)
I
2
0
V
OHR
OLR
OH
DD
0.4
V
V
V
= max,
DD(2.5V)
I
I
I
1.5
0.5
DD(2.5V)
DD(3.3V)
DD(2.5)
DTX_CLK and DRX_CLKf = 83.33 MHz
V
= max,
DD(3.3V)
DTX_CLK and DRX_CLKf = 83.33 MHz
Supply current
A
V
= max,
DD(2.5)
DTX_CLK and DRX_CLKf = 83.33 MHz
0.175
C
C
Capacitance, input
Capacitance, output
6
6
pF
pF
i
o
timing requirements over recommended operating conditions
JTAG interface
control signals
RESET (see Figure 15)
NO.
MIN
100
4
MAX
UNIT
1
1
t
t
Pulse duration, RESET low at power up
Pulse duration, RESET low at other times
µs
w(RESETP)
t
w(RESET)
cycle
1
RESET
Figure 15. RESET
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
physical medium attachment interface (port 8)
receive
PMA receive (see Figure 16)
NO.
MIN
16
MAX
UNIT
ns
1
–
t
t
t
t
t
t
t
t
t
t
Cycle time, receive byte clock 0 and 1 (Mxx_RCLK, Mxx_COL)
16
c(Mxx_RBC)
†
Drift rate of receive bye clock 0 and 1
0.2
40%
2.5
2.5
2.5
1.5
1.5
1.5
7.5
ns
drift(Mxx_RBC)
w(Mxx_RBC)
su(Mxx_RXD)
su(Mxx_RXDV)
su(Mxx_RXER)
h(Mxx_RXD)
2,3
4
Pulse duration, Mxx_RCLK, Mxx_COL low or high
60%
ns
Setup time, Mxx_RXD7–Mxx_RXD0 valid before Mxx_RCLK/COL↑
Setup time, Mxx_RXDV valid before Mxx_RCLK/COL↑
Setup time, Mxx_RXER valid before Mxx_RCLK/COL↑
Hold time, Mxx_RXD7–Mxx_RXD0 valid after Mxx_RCLK/COL↑
Hold time, Mxx_RXDV valid after Mxx_RCLK/COL↑
ns
4
ns
4
ns
5
ns
5
ns
h(Mxx_RXDV)
h(Mxx_RXER)
skew(Mxx_RBC)
5
Hold time, Mxx_RXER valid after Mxx_RCLK/COL↑
ns
6
Skew between receive byte clock 1 and receive byte clock 0
8.5
ns
†
t
is the (minimum) time for either RBC0 or RBC1 to drift from 63.5 MHz to 64.5 MHz or 60 Mhz to 59 MHz from their lock value. It is applicable
drift
under all input signal conditions (except under certain circumstances during comma detection), including invalid or absent input signals, if the
receiver clock recovery unit was previously locked to Mxx_RFCLK or to a valid input signal.
1
6
2
3
5
4
4
5
Receive Byte
Clock 0
Receive
Code Group
Data Group
Comma Detect
Receive Byte
Clock 0
Figure 16. PMA Receive
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
transmit
PMA transmit (see Figure 17)
NO.
MIN
MAX
UNIT
†
†
1
2,3
4
t
t
t
t
t
t
t
t
Cycle time, Mxx_GTCLK
8
8
ns
c(Mxx_GTCLK)
w(Mxx_GTCLK)
su(Mxx_TXD)
su(Mxx_TXEN)
su(Mxx_TXER)
h(Mxx_TXD)
Pulse duration, Mxx_GTCLK low or high
40%
60%
t
c(Mxx_GTCLK)
ns
Setup time, Mxx_RXD7–Mxx_RXD0 valid before Mxx_GTCLK↑
Setup time, Mxx_RXDV valid before Mxx_GTCLK↑
Setup time, Mxx_RXER valid before Mxx_GTCLK↑
Hold time, Mxx_RXD7–Mxx_RXD0 valid after Mxx_GTCLK↑
Hold time, Mxx_RXDV valid after Mxx_GTCLK↑
Hold time, Mxx_RXER valid after Mxx_GTCLK↑
2
2
2
1
1
1
4
ns
ns
ns
ns
ns
4
5
5
h(Mxx_TXDV)
h(Mxx_TXER)
5
†
±100-ppm tolerance
1
3
5
2
4
Transmit
Code Group
Transmit
Clock
Figure 17. PMA Transmit
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
GMII (port 8)
Figures 18–20 show the timing for the 100-/1000-Mbit/s GMII when operating at 1000 Mbit/s.
Both Mxx_CRS and Mxx_COL are driven asynchronously by the PHY. Mxx_RXD7–MxxRXD0 is driven by the
PHY on the falling edge of Mxx_RCLK. Mxx_RXD7–MxxRXD0 timing must be met during clock periods in which
Mxx_RXDV is asserted. Mxx_RXDV is asserted and deasserted by the PHY on the falling edge of Mxx_RCLK.
Mxx_RXER is driven by the PHY on the falling edge of Mxx_RCLK.
GMII receive (see Figure 18)
NO.
MIN
2
MAX
UNIT
ns
1
t
t
t
t
t
t
Setup time, Mxx_RXD7–Mxx_RXD0 valid before Mxx_RCLK↑
Setup time, Mxx_RXDV valid before Mxx_RCLK↑
Setup time, Mxx_RXER valid before Mxx_RCLK↑
Hold time, Mxx_RXD7–Mxx_RXD0 valid after Mxx_RCLK↑
Hold time, Mxx_RXDV valid after Mxx_RCLK↑
su(Mxx_RXD)
su(Mxx_RXDV)
su(Mxx_RXER)
h(Mxx_RXD)
1
2
ns
1
2
ns
2
1
ns
2
1
ns
h(Mxx_RXDV)
h(Mxx_RXER)
2
Hold time, Mxx_RXER valid after Mxx_RCLK↑
1
ns
Mxx_RCLK
1
2
Mxx_RXD7–Mxx_RXD0
Mxx_RXDV
Mxx_RXER
Figure 18. GMII Receive
Mxx_CRS and Mxx_COL are driven asynchronously by the PHY. Mxx_GTCLK is derived directly from
Mxx_RFCLK. Mxx_TXD7–Mxx_TXD7 is driven by the reconciliation sublayer synchronous to the Mxx_GTCLK.
Mxx_TXEN is asserted and deasserted by the reconciliation sublayer synchronous to the Mxx_GTCLK rising
edge. Mxx_TXER is driven synchronous to the rising edge of Mxx_GTCLK.
GMII transmit (see Figure 19)
NO.
MIN
1.5
1.5
1.5
MAX
4.5
UNIT
ns
1
t
t
t
Delay time, from Mxx_GTCLK↑ to Mxx_TXD3–MxxTXD0 valid
Delay time, from Mxx_GTCLK↑ to Mxx_TXEN valid
Delay time, from Mxx_GTCLK↑ to Mxx_TXER valid
d(Mxx_TXD)
d(Mxx_TXEN)
d(Mxx_TXER)
1
4.5
ns
1
4.5
ns
Mxx_GTCLK
1
Mxx_TXD7–Mxx_TXD0
Mxx_TXEN
Mxx_TXER
Figure 19. GMII Transmit
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
PMA and GMII clock (see Figure 20)
NO.
MIN
2.5
2.5
8
MAX
UNIT
ns
1
t
t
t
Pulse width low, Mxx_RFCLK
Pulse width high, Mxx_RFCLK
Cycle time, Mxx_RFCLK
r(Mxx_GCLK)
h(Mxx_GCLK)
w(Mxx_GCLK)
2
ns
3
ns
PMA and GMII clock (see Figure 20)
NO.
MIN
MAX
UNIT
ns
1
2
t
t
Rise time, Mxx_RFCLK
Fall time, Mxx_RFCLK
1
1
r(Mxx_GCLK)
ns
f(Mxx_GCLK)
3
Accuracy
duty cycle
100
40%
PPM
60%
†
tr and tf are measured between 20% and 80%, V
= min, output load (GTCLK) = 20pf.
DD(3.3-V)
3
1
2
Mxx_RFCLK
Figure 20. GMII Clock
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
MII (ports 0–8)
Figures 21–23 show the timing for the eight MIIs operating at either 10-Mbit/s or 100-Mbit/s, and the GMII
operating at 100-Mbit/s.
Mxx_CRS and Mxx_COL are driven asynchronously by the PHY. Mxx_RXD3–Mxx_RXD0 is driven by the PHY
on the falling edge of Mxx_RCLK. Mxx_RXD3–Mxx_RXD0 timing must be met during clock periods in which
Mxx_RXDV is asserted. Mxx_RXDV is asserted and deasserted by the PHY on the falling edge of Mxx_RCLK.
Mxx_RXER is driven by the PHY on the falling edge of Mxx_RCLK.
MII receive (see Figure 21)
NO.
MIN
8
MAX
UNIT
ns
1
t
t
t
t
t
t
Setup time, Mxx_RXD3–Mxx_RXD0 valid before Mxx_RCLK↑
Setup time, Mxx_RXDV valid before Mxx_RCLK↑
Setup time, Mxx_RXER valid before Mxx_RCLK↑
Hold time, Mxx_RXD3–Mxx_RXD0 valid after Mxx_RCLK↑
Hold time, Mxx_RXDV valid after Mxx_RCLK↑
su(Mxx_RXD)
su(Mxx_RXDV)
su(Mxx_RXER)
h(Mxx_RXD)
1
8
ns
1
8
ns
2
8
ns
2
8
ns
h(Mxx_RXDV)
h(Mxx_RXER)
2
Hold time, Mxx_RXER valid after Mxx_RCLK↑
8
ns
1
2
Mxx_RCLK
Mxx_RXD3–Mxx_RXD0
Mxx_RXDV
Mxx_RXER
Figure 21. MII Receive
NOTE: For port 8, M08_RFCLK is used for the transmit clock input.
Mxx_CRS and Mxx_COL are driven asynchronously by the PHY. Mxx_TXD3–Mxx_TXD0 is driven by the
reconciliationsublayersynchronoustoMxx_TCLK. Mxx_TXENisassertedanddeassertedbythereconciliation
sublayer synchronous to the Mxx_TCLK rising edge. Mxx_TXER is driven synchronous to the rising edge of
Mxx_TCLK.
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
MII transmit (see Figure 22)
NO.
MIN
5
MAX
15
UNIT
ns
1
1
1
t
t
t
Delay time, from Mxx_TCLK↑ to Mxx_TXD3–MxxTXD0 valid
Delay time, from Mxx_TCLK↑ to Mxx_TXEN valid
Delay time, from Mxx_TCLK↑ to Mxx_TXER valid
d(Mxx_TXD)
d(Mxx_TXEN)
d(Mxx_TXER)
5
15
ns
5
15
ns
1
Mxx_TCLK
Mxx_TXD3–Mxx_TXD0
Mxx_TXEN
Mxx_TXER
Figure 22. MII Transmit
MII clock (see Figure 23)
NO.
MIN
35%
35%
2.5
MAX
65%
65%
25
UNIT
1
2
3
t
t
t
Pulse width low Mxx_RCLK, Mxx_TCLK
Pulse width high Mxx_RCLK, Mxx_TCLK
Cycle time Mxx_RCLK, Mxx_TCLK
r(Mxx_CLK)
h(Mxx_CLK)
w(Mxx_CLK)
MHz
3
1
2
Mxx_RCLK
Mxx_TCLK
Figure 23. MII Clock
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
RDRAM interface
RDRAM (see Figure 24)
NO.
MIN
3.33
45%
0.5
MAX
3.33
55%
0.5
UNIT
1
t
t
t
t
t
t
t
Cycle time DTX_CLK, DRX_CLK
ns
c(DX_CLK)
2, 3
Pulse duration, DTX_CLK, DRX_CLK low or high
Pulse duration, tick time
t
w(DX_CLK)
c(DX_CLK)
4, 5
t
w(TICK)
cycle
ns
6, 8
Setup time, DBUS_DATA before tick
Hold time, DBUS_DATA after tick
0.35
0.35
su(DBUS_DATA)
h(DBUS_DATA)
d(DBUS_OUT)
7, 9
ns
10, 11
Delay time, DBUS_DATA, DBUS_CTRL, DBUS_EN from tick
Cycle time, internal clock
0.635 1.438
4
t
t
c(DX_CLK)
†
cycle
c(DX_CLK)
†
Not shown in Figure 24 due to scale
1
2
3
DTX_CLK
DRX_CLK
4
5
10
11
6
7
8
9
DBUS_DATA (in)
DBUS_CTRL
DBUS_EN
DBUS_DATA (out)
Figure 24. RDRAM
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ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
DIO interface
The DIO interface is simple and asynchronous to allow easy adaptation to a range of microprocessor devices
and computer system interfaces.
DIO and DMA writes (see Figure 25)
NO.
MIN
2t
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Pulse duration, SCS↓
w(SCS)
c
2
Setup time, SRNW valid before SCS↓
Setup time, SAD1–SAD0, SDMA valid before SCS↓
Setup time, SAD7–SAD0 valid before SCS↓
Hold time, SRNW low after SRDY↓
0
0
0
0
0
0
0
su(SRNW)
su(SAD)
3
4
su(SDATA)
h(SRNW)
h(SAD)
5
6
Hold time, SAD1–SAD0, SDMA valid after SRDY↓
Hold time, SAD7–SAD0 valid after SRDY↓
Hold time, SCS low after SRDY↓
7
h(SDATA)
h(SCSL)
8
9
Delay time from SCS↓ to SRDY↑
10
†
d(SRDYZH)
d(SRDYHL)
d(SRDYLH)
h(SCSH)
w(SRDY)
d(SINT)
10
11
12
13
14
Delay time from SCS↓ to SRDY↓
2t
c
Delay time from SCS↑ to SRDY↑
t
c
2t +10
c
Hold time, SCS high after SRDY↑
0
Pulse duration, SRDY↑
t
c
Delay time from SRDY↓ to SINT valid. (write to INT or INT_Enable register)
2t
c
†
When the switch is performing certain internal operations (e.g., EEPROM load), there is a delay of up to 20 ms (24C02) or 800 ms (24C08)
between SCS being asserted and SRDY being asserted.
4
10
3
1
2
9
8
5
6
11
12
SCS
SRNW
SAD1–SAD0
SDMA
7
SDATA7–
SDATA0
13
SRDY
SINT
14
Figure 25. DIO and DMA Writes
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ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
DIO and DMA reads (see Figure 26)
NO.
MIN
2t
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
Pulse duration, SCS low
w(SCSL)
c
Setup time, SRNW valid before SCS↓
Setup time, SAD1–SAD0, SDMA valid before SCS↓
Hold time, SRNW low after SRDY↓
Hold time, SAD1–SAD0, SDMA valid after SRDY↓
Hold time, SCS low after SRDY↓
0
0
0
0
0
0
su(SRNW)
su(SAD)
3
4
h(SRNW)
h(SAD)
5
6
h(SCSL)
7
Setup time from SRDY↓ to SDATA7–SDATA0 driven
Delay time from SCS↓ to SRDY↑
su(SDATAD)
d(SRDYZH)
d(SRDYHL)
d(SDATAZ)
d(SRDYLH)
h(SCSH)
8
10
†
9
Delay time from SCS↓ to SRDY↓
0
0
10
11
12
13
Delay time from SCS↑ to SDATA7–SDATA0 3-state
Delay time from SCS↑ to SRDY↑
10
t
c
2t +10
c
Hold time, SCS high after SRDY↑
0
Pulse duration, SRDY high
t
c
w(SRDY)
†
When the switch is performing certain internal operations (e.g., EEPROM load), there is a delay of up to 20 ms (24C02) or 800 ms (24C08)
between SCS being asserted and SRDY being asserted.
1
3
9
11
10
2
8
6
4
5
12
SCS
SRNW
SAD1–SAD0
SDMA
7
SDATA7–
SDATA0
13
SRDY
Figure 26. DIO and DMA Reads
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ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
EEPROM interface
For further information on EEPROM interface timing, refer to the 24C02 or 24C08 serial EEPROM data sheets.
EEPROM writes (see Figure 27)
NO.
MIN
383
383
0
MAX
UNIT
1
t
t
t
t
t
t
t
t
f
Setup time, start condition during ECLK high
Hold time, start condition during ECLK high
Hold time, data after ECLK↓
t
c
t
c
t
c
t
c
t
c
t
c
t
c
t
c
su(EDIO:Start)
h(EDIO:Start)
h(EDIO:Data)
su(EDIO:Data)
w(ECLK)
2
3
4
Setup time, data before ECLK↑
383
766
766
383
766
5
Pulse duration, ECLK low during start/stop
Pulse duration, ECLK high during start/stop
Pulse duration, ECLK high during data
Pulse duration, ECLK low during data
Clock frequency, ECLK
6
w(ECLK)
7
w(ECLK:Data)
w(ECLK:Data)
clock(ECLK)
8
9
98
kHz
3
4
1
2
EDIO (out)
ECLK
5
6
7
8
Figure 27. EEPROM Writes
EEPROM reads (see Figure 28)
NO.
MIN
10
0
MAX
UNIT
ns
1
2
t
t
Setup time, EDIO (in) before ECLK↑
su(EDIO)
Hold time, EDIO (in) after ECLK↓
ns
h(EDIO)
2
1
ECLK
EDIO (in)
Figure 28. EEPROM Reads
71
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
LED interface
LED (see Figure 29)
NO.
MIN
MAX
UNIT
1
2
3
4
5
6
t
t
t
t
t
t
Cycle time, LED_CLK
8
4
t
c(LED_CLK)
w(LED_CLK)
n(LED_CLK)
c(BURST)
c
c
Pulse duration, LED_CLK high
Number of LED_CLK pulses in burst
Cycle time, LED_CLK burst
t
†
24
‡
4687488
t
c
t
c
t
c
Setup time, LED_DATA before LED_CLK↑
Hold time, LED_DATA after LED_CLK↑
4
4
su(LED_DATA)
h(LED_DATA)
†
‡
During hard reset, LED_CLK runs continuously.
Does not apply during hard reset
4
3
1
6
2
5
LED_CLK
LED_DATA
First LED
Second LED
Last LED
First LED
Figure 29. LED
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
PARAMETER MEASUREMENT INFORMATION
The following load circuits and voltage waveforms show the conditions used for measuring switching characteristics.
Test points are illustrated schematically on the load circuits. Reference points are plotted on the voltage waveforms.
IV110
From Output
Under Test
From Output
Under Test
t
/t
, t
/t
Drive
Dependent
PLH PHL PZH PZL
N channel – t
P channel – t
only
only
IV110
PZH
PZL
C
L
(four load values)
Internal and Input
Macro Load Circuit
Output
Macro Load Circuit
Figure 30. Loading for Active Transitions
Input
t
/t
PHZ PLZ
+ Ion
V
N channel – t
P channel – t
only
only
PLZ
PHZ
High or Low
±
Figure 31. Loading for High-Impedance Transitions
t
t
f
r
V
0
DD
90%
1.3 V
90%
1.3 V
Input
10%
10%
t
t
PLH
PHL
V
Internal
In-Phase
Output
OH
OL
47%
47%
V
Figure 32. TTL Input Macro Propagation-Delay-Time Voltage Waveforms
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
PARAMETER MEASUREMENT INFORMATION
t
t
f
r
V
0
DD
80%
47%
80%
47%
Input
20%
20%
t
PHL
V
OH
OL
Out-of-Phase
Output
47%
47%
47%
V
t
t
PHL
PLH
t
PHL
V
OH
OL
In-Phase
Output
47%
V
Figure 33. Internal Push/Pull Output Propagation-Delay-Time Voltage Waveforms
t
t
f
r
V
0
DD
CMOS-Level
Input
80%
47%
80%
47%
20%
20%
CMOS t
CMOS t
PHL
PLH
V
OH
LVCMOS/TTL
Output
50%
1.3 V
50%
1.3 V
V
OL
TTL t
TTL t
PHL
PLH
Figure 34. TTL Output Macro Propagation-Delay-Time Voltage Waveforms
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
PARAMETER MEASUREMENT INFORMATION
Hi-Z
Input
(active-low
enable)
V
0
DD
80%
47%
20%
Active
PZH
t
V
OH
Output
High
50% LVCMOS
1.3 V TTL
Hi-Z (forced low)
Hi-Z (forced high)
t
PZL
Output
Low
50% LVCMOS
1.3 V TTL
V
OL
Hi-Z
Input
(active-low
enable)
V
0
DD
80%
47%
20%
Active
t
PHZ
+ Ion
0 mA
Output
High
1 mA
t
PLZ
0 mA
– Ion
Output
Low
1 mA
Figure 35. TTL 3-State Output Disable and Enable Voltage Waveforms
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TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
MECHANICAL DATA
GGP (S-PBGA-N352)
PLASTIC BALL GRID ARRAY (CAVITY DOWN) PACKAGE
31,75 SQ
35,20
34, 80
SQ
1,27
26 24 22 20 18 16 14 12 10
25 23 21 19 17 15 13 11
8
6
4
2
9
7
5
3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
Heat Slug
1,70 MAX
0,91 NOM
Seating Plane
0,15
0,50 MIN
0,90
0,60
M
0,30
4073223/A 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Thermally enhanced die down plastic package with top surface metal heat slug.
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PACKAGE OPTION ADDENDUM
4-May-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TNETX4090GGP
OBSOLETE
BGA
GGP
352
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
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Addendum-Page 1
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