User’s Guide
1998
Mixed-Signal Linear Products
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SLVP089 Synchronous Buck
Converter Evaluation Module
User’s Guide
Literature Number: SLVU001A
July 1998
Printed on Recycled Paper
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IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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Preface
Read This First
About This Manual
This user’s guide is a reference manual for the SLVP089 Synchronous Buck
Converter Evaluation Module used to evaluate the performance of the TL5001
PWM Controller. This document provides information to assist managers and
hardware engineers in application development.
How to Use This Manual
This manual provides the information and instructions necessary to design,
construct, operate, and understand the SLVP089. Chapter 1 describes and
lists the hardware requirements; Chapter 2 describes design considerations
and procedures; and Appendix A contains the data sheet for the TL5001 PWM
Controller
Related Documentation From Texas Instruments
The following books describe the TL5001 and related support tools. To obtain
a copy of any of these TI documents, call the Texas Instruments Literature Re-
sponse Center at (800) 477–8924. When ordering, please identify the book by
its title and literature number.
TL5001 Pulse-Width-Modulation Control Circuits Data Sheet (Literature
number SLVS084C). It contains electrical specifications, available tem-
perature options, general overview of the device, and application in-
formation.
Designing with the TL5001C PWM Controller Application Report
(Literature number SLVA034).
iii
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If You Need Assistance
If You Need Assistance . . .
If you want to . . .
Contact Texas Instruments at . . .
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about Texas Instruments
Call the Product Information
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(MSP)
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Send a fax: (972) 480–7800
Write to: Texas Instruments Incorporated
Product Information Center, MS 3123
P.O. Box 660246
Dallas, Texas 75266
Ask questions about product
operation or report sus-
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Make suggestions about or
report errors in documenta-
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Notes: 1) The literature number for the book is required; see the lower-right corner on the back cover.
2) Please mention the full title of the book, the literature number from the lower-right corner of the back cover, and the
publication date from the spine or front cover.
FCC Warning
Thisequipmentisintendedforuseinalaboratorytestenvironmentonly. Itgen-
erates, uses, and can radiate radio frequency energy and has not been tested
for compliance with the limits of computing devices pursuant to subpart J of
part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other en-
vironments may cause interference with radio communications, in which case
the user at his own expense will be required to take whatever measures may
be required to correct this interference.
Trademarks
TI is a trademark of Texas Instruments Incorporated.
iv
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Contents
1
2
Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
1.2
1.3
1.4
1.5
1.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Input/Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
2.2
2.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Operating Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Design Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3.1 Duty Cycle Estimate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3.2 Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3.3 Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3.4 Synchronous Switch and Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.3.5 Snubber Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.3.6 Controller Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.3.7 Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
v
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Figures
1–1
1–2
1–3
1–4
1–5
1–6
1–7
1–8
2–1
2–2
2–3
2–4
Typical Synchronous Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Input/Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Efficiency Vs Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Power Switch Turn-On and Delay from Q2 Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Power Switch Turn-Off and Delay to Q2 On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Inductor and Output Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Power Stage Bode Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Compensation Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Bode Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Output Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Tables
1–1
1–2
1–3
2–1
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Line/Load Regulation, 3.3-V (Total Variation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Load Regulation and Ripple, 3.3-V (9-V Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Operating Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
vi
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Chapter 1
Hardware
The SLVP089 Synchronous Buck Converter Evaluation Module (SLVP089)
provides a method for evaluating the performance of the TL5001 pulse-width-
modulation(PWM)controller. Thedevicecontainsallofthecircuitrynecessary
to control a switch-mode power supply in a voltage-mode configuration. This
manual explains how to construct basic power conversion circuits including
the design of the control chip functions and the basic loop. This chapter in-
cludes the following topics:
Topic
Page
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
1.2 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
1.3 Input/Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
1.4 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
1.5 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
1.6 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
1-1
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Introduction
1.1 Introduction
Synchronous buck converters provide the smaller size and higher efficiency
required by electronic equipment, particularly portable battery-operated
equipment. The synchronous buck converter reduces power losses
associated with a standard buck converter by substituting a power MOSFET
for the commutating diode. This reduces the typical 0.5-V to 1-V diode drop
to 0.3 V or less and increases system efficiency by up to 10 percent.
Continuous-current mode is desirable and is used in this EVM for the low
peak-to-average current ratio. Figure 1–1 shows a typical synchronous buck
converter.
Figure 1–1. Typical Synchronous Buck Converter
V
I
+
R3
C1
Q1
Q2
L1
V
O
R1
R2
Controller
FB
+
C2
CR1
R4
Transistor Q1 is the power switch and Q2 is the synchronous switch. A diode
in parallel with Q2 allows inductor current flow during the dead time when both
transistors are turned off. If dead time is not present in this configuration, high
transient shoot-through currents will flow during the transition when one tran-
sistor is turning on and the other is turning off, usually resulting in destruction
of the power stage switches.
TheSLVP089evaluationmodulewillsupplyanominal3.3-Voutputoveraload
range from 0 to 3 A using a dc input voltage of 5.5 V to 12 V. Full load efficiency
is typically 90 percent.
1-2
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1.2 Schematic
Figure 1–2. Schematic Diagram
J1
5.5 V to 12 V
1
V
V
GND
GND
I
I
2
3
4
+
+
C10
100 µ F
C5
100 µ F
C11
0.47µ F
R5
10 kΩ
Q1
IRF7406
PMOS
C14
0.1 µ F
L1
µ H
27
J2
R6
R10
1 kΩ
C15
C7
C13
C12
100µ F
1
15 Ω
U2
3.3 V
1.0 µ F
100µ F 10µ F
+
+
2
3
4
TPS2812
3.3 V
RTN
RTN
1
6
R7
3.3 Ω
CR3
C9
0.22 µ F
BAS16ZX
V
V
DD
CC
2
CR1
8
7
REG
R8
121 kΩ
V
CC
R12 10 kΩ
30BQ015
6
3
4
7
2
4
DTC
1IN
2IN
C6
1OUT
2OUT
U1
TL5001
Q2
1000 pF
C2
IRF7201
R11 30 kΩ
NMOS
5
COMP
µ F
0.033
R2
1.6 kΩ
GND
1
R13
10 kΩ
OUT
SCP
C3
0.0022
FB
RT
3
CR2
BAS16ZX
µ F
5
R4
+
R9
1.00 kΩ
C1
1µ F
2.32 kΩ
GND
8
R9
90.9 kΩ
C4
0.022µ F
R3
180 Ω
Note: Frequency is set to 100 kHz by R9. See TL5001 data sheet for the curve of oscillator frequency versus timing resistance.
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Input/Output Connections
1.3 Input/Output Connections
Figure 1–3 shows the input/output connections to the SLVP089.
Figure 1–3. Input/Output Connections
Power Supply
–
+
C5
Q1
R7
Q2
R5
C11
L1
C10
J1
U2
R13
C6
CR1
R12
J2
C14
1
CR3
R6
R10
1
JMP1
C13
C12
C8
SLVP089
R11
CR2
C15
U1
R4
R3
C3
C2
R9
R8
TEXAS INSTRUMENTS
TL5001
+3.3V, 3 AMP
SYNC. RECT BUCK
EVAL BOARD
REV2
C4
C9
C1
R2
R1
–
LOAD
+
Notes: 1) Source power should be able to supply a minimum of 2.5 A at 5.5-V input and/or 1.1-A at 12-V input.
2) Loadshouldbeabletosinkupto3Awithadequatepowerrating. Resistiveloadswithadequateratingsmaybeused.
1-4
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Board Layout
1.4 Board Layout
Figure 1–4 shows the SLVP089 board layout.
Figure 1–4. Board Layout
C5
Q1
Q2
R5
L1
C11
C10
R7
U2
R13
C6
CR1
J1
R12
C14
J2
1
CR3
1
R6
R10
JMP1
C13
C12
C8
R11CR2
C15
U1
R4
R3
C3
C2
R9
R8
TEXAS INSTRUMENTS
SLVP089
EVAL BOARD
REV2
C4
TL5001
+3.3V, 3 AMP
YNC. RECT BUCK
C9
C1
R2
R1
Hardware
1-5
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Bill of Materials
1.5 Bill of Materials
Table 1–1 lists materials required for the SLVP089.
Table 1–1.Bill of Materials
Qty Reference Part Number
Mfr
Description
1
1
1
1
1
1
1
4
C1
ECS-T1CY105R
Standard
Panasonic
Capacitor, Tant, 1 F, 20%, A Case
C11
C13
C14
C2
Capacitor, Cer, 0.47 F, 10%, X7R, 1210
Capacitor, Cer, 10 F, 10 V, Y5V,3225
Capacitor, Cer, 0.1 F, 10%, X7R, 1206
Capacitor, Cer, 0.033 F, 10%, X7R, 1206
Capacitor, Cer, 0.0022 F, 10%, X7R, 0805
Capacitor, Cer, 0.022 F, 10%, X7R, 0805
Capacitor, Tant, 100 F, 10 V, D Case
C3225Y5V1C106Z
Standard
TDK
Standard
C3
Standard
C4
Standard
C5, C7,
TPSD107M010R0100 AVX
C10, C12
1
1
1
2
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
C6
Standard
Standard
Capacitor, Cer, 1000 pF, 5%, NPO, 0805
Capacitor, Cer, 0.22 F, 10%, X7R, 1210
Rectifier, Schottky, 3 A, 15 V
C9
CR1
CR2, CR3
J1, J2
L1
30BQ015
BAS16ZXCT
Standard
NOVA 1
IR
Zetex
Diode, Signal, SOT-23
Connector, 4-pin header, 25 Mil, 0.1′′ Sp. Gold
Nova Mag
Inductor, 27 H
A
Q1
IRF7406
IRF7201
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
TL5001CD
TPS2812D
SLVP089
IR
IR
Transistor, P-CH FET, 30 V, 0.04 , 4.7 A, SO-8
Transistor, N-CH FET, 30 V, 0.03 , 7 A, SO-8
Resistor, 1.00 k
Q2
R1
R12, R13
R2
Resistor, 10 k
Resistor, 1.6 k
R3
Resistor, 180
R4
Resistor, 2.32 k
R5
Resistor, 10 k
R6
Resistor, 15
R7
Resistor, 3.3
R8
Resistor, 121 k
U1
TI
TI
IC, PWM, SO-8
U2
IC, dual MOSFET driver, SO-8
PWB
1-6
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Test Results
1.6 Test Results
Tables 1–2 and 1–3, along with Figures 1–5 through 1–8, show the test results
for the SLVP089.
Table 1–2.Line/Load Regulation, 3.3-V (Total Variation)
Line/Load
0.3 A
3.330
3.330
3.330
3.330
3.331
3.331
3.331
3.331
0.03%
0.9 A
3.329
3.329
3.328
3.329
3.330
3.330
3.330
3.330
0.06%
1.5 A
3.328
3.328
3.328
3.328
3.328
3.328
3.328
3.329
0.03%
3.0 A
3.324
3.324
3.325
3.325
3.325
3.325
3.325
3.325
0.03%
5.0 A
3.320
3.320
3.321
3.321
3.321
3.321
3.321
3.321
0.03%
Load Reg.
0.18%
0.18%
0.15%
0.15%
0.18%
0.18%
0.18%
0.18%
5.5 V Vo(V)
6.0 V Vo(V)
7.0 V Vo(V)
8.0 V Vo(V)
9.0 V Vo(V)
10 V Vo(V)
11 V Vo(V)
12 V Vo(V)
Line Reg.
Note: The calculation for load regulation only accounts for the worst case of load variation under the normal voltage condition
(i.e., 3.3 V at 3 A). All voltages were measured at the PCB header pins.
Table 1–3.Load Regulation and Ripple, 3.3-V (9-V Input)
Load
No Load 0.50 A
1.0 A
3.329
18
2.0 A
3.327
24
3.0 A
3.325
24
5.0 A
3.321
32
Reg.
Vo(V)
3.331
16
3.330
16
0.18%
Vo Ripple (mV P–P)
Vo Spikes (mV P–P)
0
24
24
34
48
60
Figure 1–5. Efficiency Vs Load
EFFICIENCY
vs
LOAD CURRENT
100
95
90
85
80
75
V = 5.5 V
I
V = 9 V
I
V = 12 V
I
70
0
1
2
3
4
5
Load Current – A
Hardware
1-7
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Test Results
Figure 1–6. Power Switch Turn-On and Delay from Q2 Off
V
= 12 V
CC
= 1.5 A
I
O
Q1 DRAIN
5 V/DIV
1
2
Q2 GATE
5 V/DIV
20 ns/Div
Figure 1–7. Power Switch Turn-Off and Delay to Q2 On
V
= 12 V
CC
= 1.5 A
I
O
Q1 Drain
5 V/Div
1
Q2 Gate
5 V/Div
2
20 ns/Div
1-8
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Test Results
Figure 1–8. Inductor and Output Ripple
V
= 12 V
CC
= 1.5 A
Inductor
Ripple
I
O
1 A/Div
1–DC
Output
Ripple
20 mV/Div
2–AC
2 µs/Div
Hardware
1-9
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1-10
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Chapter 2
Design Procedure
There are many possible ways to proceed when designing power supplies.
This chapter shows the procedure used in the design of the SLVP089. The
chapter includes the following topics:
Topic
Page
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Operating Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3 Design Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2-1
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Introduction
2.1 Introduction
The SLVP089 is a dc-dc synchronous buck converter module that provides a
3.3-V output at up to 3 A with an input voltage range of 5.5 V to 12 V. The PWM
controller is a TL5001 operating at a nominal frequency of 100 kHz. The
TL5001 is configured for a maximum duty cycle of 100 percent and has short-
circuit protection built in. The synchronous power stage consists of a PMOS
switch and an NMOS synchronous rectifier.
2-2
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Operating Specifications
2.2 Operating Specifications
Table 2–1 lists the operating specifications for the SLVP089.
Table 2–1.Operating Specifications
Specification
Min
5.5
3.10 3.30 3.50
Typ
Max Units
Input Voltage Range
12
V
V
Output Voltage Range
Output Current Range
Operating Frequency
Output Ripple
0
3
A
100
kHz
mV
50
Efficiency (V = 9 V, I = 3 A)
85% 90%
i
O
Design Procedure
2-3
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Design Procedures
2.3 Design Procedures
Detailed steps in the design of a buck-mode converter may be found in
Designing With the TL5001C PWM Controller (literature number SLVA034)
from TI. This section shows the basic steps involved in this design.
2.3.1 Duty Cycle Estimate
The duty cycle for a continuous-mode step-down converter is approximately:
V
V
O
d
D
V
– V
I
SAT
Assuming the diode or synchronous switch forward voltage V = 0.12 V and
d
the power-switch-on voltage V
= 0.15 V, the duty cycle for V = 5.5, 9, and
SAT
I
12 V is 0.64, 0.39, and 0.29, respectively.
2.3.2 Output Filter
A synchronous buck converter uses a single-stage LC filter. Choose an induc-
tortomaintaincontinuous-modeoperationdownto15percentoftheratedout-
put load:
I
2
0.15
The inductor value is:
V – V – V
I
2
0.15
3
0.9 A
O
O
D
t
I
SAT
O
L
I
O
–6
(12 – 0.15 – 3.3)
0.29
10
10
27.6
H
0.9
Assuming that all of the inductor ripple current flows through the capacitor and
the effective series resistance (ESR) is zero, the capacitance needed is:
I
O
0.9
C
22.5
F
3
8
100
10
0.05
8
f
V
O
Assuming the capacitance is very large, the ESR needed to limit the ripple to
50 mV is:
V
O
0.05
0.9
ESR
0.056
I
O
The output filter capacitor should be rated at least ten times the calculated ca-
pacitanceand 30–50 percent lower than the calculated ESR. This design used
two 100- F capacitors in parallel with a multilayer ceramic to reduce ESR.
2.3.3 Power Switch
Based on the preliminary estimate, r
should be less than 0.015 V 3A
DS(ON)
= 50 m . The IRF7406 is a 30-V p-channel MOSFET with r
= 40 m
DS(ON)
2-4
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Design Procedures
The power dissipation (conduction + switching losses) can be approximated
as:
2
O
P
I
r
D
0.5
V
I
t
f
D
DS(ON)
I
O
r
f
Assuming total switching time, t , = 100 ns, a 55°C maximum ambient tem-
r+f
perature, and r
adjustment factor = 1.6, then:
DS(ON)
(0.04
5.5
2
P
3
1.6)
0.64
0.1
D
–6
3
0.5
3
10
100
10
0.45 W
The thermal impedance for Q1 R
a one-inch-square pattern, thus:
= 90°C/W for FR-4 with 2-oz. copper and
JA
55
T
T
R
P
(90
0.45)
96°C
J
A
JA
D
2.3.4 Synchronous Switch and Rectifier
Thesynchronousswitchcalculationsfollowthesamepathasthepowerswitch
except that the duty cycle is 1–D. Then r should be less than 0.012 V
DS(ON)
3A = 40 m . Selecting an IRF7201 with an r
= 30 m , then:
DS(ON)
2
P
3
(0.03
5.5
1.6)
0.36
0.1
D
–6
3
0.5
3
10
100
10
0.238 W
T
T
A
R
P
55
(90
0.238)
76°C
J
JA
D
The catch rectifier serves as a backup device for the synchronous switch and
conducts during the time interval when both devices are off. The 30BQ015 is
a 3-A, 15-V rectifier in an SMC power surface-mount package. If the synchro-
nous switch were not used, the power dissipation for the catch diode would be:
P
I
V
1 – D
3
0.7
0.71
1.491 W
D
O
D
Min
However, since the catch diode actually conducts only during the deadtime
and switching time, the power dissipation is:
P
I
V
t
f
D
O
D
r
f
–6
3
3
0.7
0.1 10
100 10
2.1 mW
2.3.5 Snubber Network
Asnubbernetworkisusuallyneededtosuppresstheringingatthenodewhere
the power switch drain, output inductor, and synchronous switch drain con-
nect. This is usually a trial-and-error sequence of steps to optimize the net-
work, but as a starting point, select a snubber capacitor with a value that is
4–10 times larger than the estimated capacitance of the synchronous switch
and catch rectifier. Then, measuring a ringing time constant of 3 ns, R is:
3
10–9
C
3
10–9
10–12
R
3
1000
Design Procedure
2-5
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Design Procedures
2.3.6 Controller Functions
The controller functions, oscillator frequency, soft-start, dead-time-control,
short-circuit protection, and sense-divider-network are discussed in this sec-
tion.
The oscillator frequency is set by selecting the resistance value from the graph
in figure 6 of the TL5001 data sheet. For 100 kHz, a value of 90.9 k is se-
lected.
Dead-time control provides a minimum off-time for the power switch in each
cycle. Set this time by connecting a resistor between DTC and GND. For this
design, a maximum duty cycle of 100% is chosen. Then R8 is calculated as:
3
R8
(R9
1.25)
10
D V
– V
V
O(100%)
O(0%)
0.65]
O(0%)
3
(90.9
1.25)
10
[1(1.3 – 0.65)
119.8 K
121 k
Soft-start is added to reduce power-up transients. This is implemented by ad-
ding a capacitor across the dead-time resistor. In this design, a soft-start time
of 25 ms is used:
t
0.025 s
121 k
R
C
0.21
F
R
DT
The TL5001 has short circuit protection instead of a current sense circuit. If not
used, the SCP terminal must be connected to ground to allow the converter
to start up. If a timing capacitor is connected to SCP, it should have a time
constant that is greater than the soft-start time constant. This time constant is
chosen to be 75 ms:
C( F)
12.46
t
12.46
0.075 s
0.93
F
SCP
2.3.7 Loop Compensation
Loop compensation is necessary to stabilize the converter over the full range
of load, line, and gain conditions. A buck-mode converter has a two-pole LC
output filter with a 40-dB-per-decade rolloff. The total closed-loop response
neededforstabilityisa20-dB-per-decaderolloffwithaminimumphasemargin
of 30 degrees over the full bandwidth for all conditions. In addition, sufficient
bandwidth must be designed into the circuit to assure that the converter will
havegoodtransientresponse. Bothoftheserequirementsareachievedbyad-
ding compensation components around the error amplifier to modify the total
loop response.
The first step in design of the loop compensation network is the design of the
output sense divider. This sets the output voltage and the top resistor deter-
mines the relative size of the rest of the compensation design. Since the
TL5001 input bias current is 0.5 A (worst case), the divider current should be
at least 0.5 mA. Using a 1-k resistor for the bottom of the divider gives a divid-
er current of 1 mA. The top of the divider is calculated as:
V
– 1
(
)
3.3 –1
0.001
O
R
2.3 k
1 mA
2-6
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Design Procedures
Calculating the pulse-width-modulator gain as the change in output voltage
divided by the change in PWM input voltage gives:
V
O
9 – 0
1.3 – 0.65
A
13.85
22.8 db
PWM
V
COMP
The LC filter has a double pole at:
1
1
H
2.64 kHz
2
LC
2
21.6
168
F
(worst case values) and rolls off at 40-dB per decade after that until the ESR
zero is reached at:
1
1
38 kHz
–6
2 RC
2 (0.025) 210 10
This information is enough to calculate the required compensation values.
Figure 2–1 shows the power stage gain and phase plots.
Figure 2–1. Power Stage Bode Plot
FREQUENCY RESPONSE
0
50
40
30
20
10
0
–45
–90
–135
–180
–225
–270
–10
–315
–20
–30
–360
2
10
3
4
10
5
10
10
10
Frequency
This response must be corrected by addition of the following:
A pole at zero to give high dc gain
Two zeroes at approximately 2.6 kHz to cancel the LC poles
A pole at approximately 38 kHz to cancel the ESR zero
A final pole to roll off high-frequency gain
The compensation circuit shown in figure 2–2 can be used to implement the
above conditions.
Design Procedure
2-7
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Design Procedures
Figure 2–2. Compensation Network
C3
R2
R4
C2
C4
R3
_
+
V
I
V
O
V
ref
The transfer function for this circuit is:
f
f
V
[1
sR2(C2
sC2R4 [1
C3)] [1
sC3R2] [1
sC4(R3
sC4R3]
R4)]
Z1 Z2
O
V
I
f
f
f
P1 P2 P3
The desired output regulation is ±6 percent total deviation. The PWM control-
ler tolerance is ±5 percent, and the divider resistors are 1 percent; therefore,
thecontrolloopmustbeveryprecise. Aminimumdcgainof1000(60dB)gives
a0.1percenttolerance. Theintegrator(R4, C2)setsthegainofthecompensa-
tion network. The minimum modulator gain is 18 dB, therefore the compensa-
tion network must have a gain of at least 42 dB. With a desired crossover fre-
quency of 20 kHz and a desired slope of 20 dB per decade, choose an integra-
tor frequency of 2 kHz. This gives a gain of 46 dB at 10 Hz, which is sufficient
for this application. If more gain is needed, increase the integrator frequency.
R4 is already known, so C2 is calculated as:.
1
1
C2
0.034
F
0.033
F
2 (2 kHz)(2.32 k )
2 f
(R4)
P1
Setting f = 3 kHz to compensate for one of the LC poles gives:
Z2
1
1
C4
0.023
F
0.022
F
2 (3 kHz)(2.32 k )
2 f (R4)
Z2
Now R3 can be calculated using f (40 kHz), the ESR compensator:
P3
1
1
R3
181
180
2 (40 kHz)(0.022 F)
2
f
(C4)
P3
The other LC filter compensator uses R2 and C2:
1
1
R2
1.6 k
2 (3 kHz)(0.033 F)
2 f (C2)
Z1
The final rolloff pole (selected at 50 kHz) uses C3 and R2:
1
1
C3
0.002
F
0.0022
F
2 (50 kHz)(1.6 k )
2 f
(R2)
P2
2-8
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Design Procedures
Figure 2–3 shows the bode plot for the compensation network.
Figure 2–3. Bode Plot
90
70
45
40
35
50
30
10
30
25
–10
–30
–50
20
15
10
–70
5
0
–90
2
10
3
4
10
5
10
10
10
Frequency – Hz
Note from the output response shown in Figure 2–4 that the minimum phase
margin is 40 degrees and the bandwidth is 18 kHz under nominal operating
conditions.
Figure 2–4. Output Response
OUTPUT RESPONSE
–180
–225
–270
–315
–360
70
60
50
40
30
20
10
0
–10
–20
2
10
3
4
10
5
10
10
10
Frequency – Hz
Design Procedure
2-9
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2-10
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