Texas Instruments Power Supply ADS5102 EVM User Manual

ADS5102/3 EVM  
User’s Guide  
December 2001  
AAP High-Speed Data Converter (Dallas)  
SLAU077  
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EVM IMPORTANT NOTICE  
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:  
This evaluation kit being sold by TI is intended for use for ENGINEERING  
DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to  
befitforcommercialuse. Assuch, thegoodsbeingprovidedmaynotbecompleteinterms  
of required design-, marketing-, and/or manufacturing-related protective considerations,  
including product safety measures typically found in the end product incorporating the  
goods. As a prototype, this product does not fall within the scope of the European Union  
directive on electromagnetic compatibility and therefore may not meet the technical  
requirements of the directive.  
Should this evaluation kit not meet the specifications indicated in the EVM Users Guide,  
the kit may be returned within 30 days from the date of delivery for a full refund. THE  
FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO  
BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR  
STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS  
FOR ANY PARTICULAR PURPOSE.  
The user assumes all responsibility and liability for proper and safe handling of the goods.  
Further, the user indemnifies TI from all claims arising from the handling or use of the  
goods. Please be aware that the products received may not be regulatory compliant or  
agency certified (FCC, UL, CE, etc.). Due to the open construction of the product, it is  
the users responsibility to take any and all appropriate precautions with regard to  
electrostatic discharge.  
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER  
PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL,  
INCIDENTAL, OR CONSEQUENTIAL DAMAGES.  
TI currently deals with a variety of customers for products, and therefore our arrangement  
with the user is not exclusive.  
TI assumes no liability for applications assistance, customer product design,  
software performance, or infringement of patents or services described herein.  
Please read the EVM Users Guide and, specifically, the EVM Warnings and Restrictions  
notice in the EVM Users Guide prior to handling the product. This notice contains  
important safety information about temperatures and voltages. For further safety  
concerns, please contact the TI application engineer.  
Personshandlingtheproductmusthaveelectronicstrainingandobservegoodlaboratory  
practice standards.  
No license is granted under any patent right or other intellectual property right of TI  
covering or relating to any machine, process, or combination in which such TI products  
or services might be or are used.  
Mailing Address:  
Texas Instruments  
Post Office Box 655303  
Dallas, Texas 75265  
Copyright 2001, Texas Instruments Incorporated  
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EVM WARNINGS AND RESTRICTIONS  
It is important to operate this EVM within the specified input and output ranges as described  
in the EVM users guide.  
Exceeding the specified input range may cause unexpected operation and/or irreversible  
damage to the EVM. If there are questions concerning the input range, please contact a TI  
field representative prior to connecting the input power.  
Applyingloadsoutsideofthespecifiedoutputrangemayresultinunintendedoperationand/or  
possible permanent damage to the EVM. Please consult the EVM Users Guide prior to  
connecting any load to the EVM output. If there is uncertainty as to the load specification,  
please contact a TI field representative.  
During normal operation, some circuit components may have case temperatures greater than  
60°C. The EVM is designed to operate properly with certain components above 60°C as long  
as the input and output ranges are maintained. These components include but are not limited  
tolinearregulators, switchingtransistors, passtransistors, andcurrentsenseresistors. These  
types of devices can be identified using the EVM schematic located in the EVM Users Guide.  
When placing measurement probes near these devices during operation, please be aware  
that these devices may be very warm to the touch.  
Mailing Address:  
Texas Instruments  
Post Office Box 655303  
Dallas, Texas 75265  
Copyright 2001, Texas Instruments Incorporated  
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Preface  
Read This First  
About This Manual  
This users guide is to assist the user with the operation of the EVM using the  
ADS5102/3 devices.  
How to Use This Manual  
This document contains the following chapters:  
- Chapter 1Overview  
- Chapter 2Physical Description  
- Chapter 3Circuit Description  
Information About Cautions and Warnings  
This book may contain cautions and warnings.  
This is an example of a caution statement.  
A caution statement describes a situation that could potentially  
damage your software or equipment.  
This is an example of a warning statement.  
A warning statement describes a situation that could potentially  
cause harm to you.  
The information in a caution or a warning is provided for your protection.  
Please read each caution and warning carefully.  
v
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Contents  
FCC Warning  
This equipment is intended for use in a laboratory test environment only. It  
generates, uses, and can radiate radio frequency energy and has not been  
tested for compliance with the limits of computing devices pursuant to subpart  
J of part 15 of FCC rules, which are designed to provide reasonable protection  
against radio frequency interference. Operation of this equipment in other  
environments may cause interference with radio communications, in which  
case the user at his own expense will be required to take whatever measures  
may be required to correct this interference.  
vi  
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Contents  
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1  
1.1  
1.2  
1.3  
1.4  
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2  
EVM Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2  
Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2  
ADS5102/3 EVM Operational Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3  
2
3
Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1  
2.1  
2.2  
PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5  
Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1  
3.1  
Circuit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
3.1.1 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
3.1.2 External Reference Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
3.1.3 Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3  
3.1.4 Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3  
3.1.5 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3  
3.1.6 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3  
Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4  
3.2  
Figures  
21  
22  
23  
24  
Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
Inner Layer 1, Ground Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3  
Inner Layer 2, Power Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4  
Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5  
vii  
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Tables  
11  
12  
21  
31  
32  
Two Pin Jumper List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3  
Three Pin Jumper List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3  
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5  
Reference Voltage Adjustment Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
Output Connector J15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4  
Notes, Cautions, and Warnings  
Voltage Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2  
viii  
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Chapter 1  
Overview  
This users guide gives a general overview of the ADS5102/3 evaluation  
module (EVM) and provides a general description of the features and  
functions to be considered while using this module.  
Topic  
Page  
1.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2  
1.2 EVM Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2  
1.3 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2  
1.4 ADS5102/3 EVM Operational Procedure . . . . . . . . . . . . . . . . . . . . . . . . . 1-3  
1-1  
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Purpose  
1.1 Purpose  
The ADS5102/3 EVM provides a platform for evaluating the ADS5102/3  
analog-to-digital converter (ADC) under various signal, reference, and supply  
conditions. Use this document in combination with the EVM schematic  
diagram supplied.  
1.2 EVM Basic Functions  
Analog input to the ADC is provided via two external SMA connectors. The  
single-ended input the user provides is converted into a differential signal at  
the input of the device. One input uses a differential amplifier, while the other  
input is transformer coupled.  
The EVM provides an external SMA connection for input of the ADC clock. The  
user can send this clock to the output connector with the digital data or provide  
asecondclocksourcetobesentinplaceoftheADCclock. Thisallowstheuser  
to provide the required setup and hold times of the output data with respect to  
the output clock. See the Clock Inputs section for the proper configuration and  
operation.  
Digital output from the EVM is via a 40-pin connector. The digital lines from the  
ADC are buffered before going to this connector. More information on this  
connector can be found in the ADC output section.  
Power connections to the EVM are via banana jack sockets. Separate sockets  
are provided for the analog and digital supply.  
In addition to the internal reference provided by the ADS5102/3 device,  
options are provided on the EVM to allow adjustment of the ADC references  
via an onboard reference circuit. A precision voltage reference source, a  
resistor network, and an operational amplifier (op amp) provide the  
ADS5102/3 device reference voltages REFT and REFB.  
1.3 Power Requirements  
The EVM can be powered directly with a single 1.8-V supply if using the  
module with transformer coupled input, internal reference source, and 1.8-V  
logic outputs.  
A voltage of 3.3 V is required for the DRVDD power input to provide 3.3-V logic  
outputs. A voltage of ±5 V is required if using external references and/or  
differential amplifier input. Provision has also been made to allow the EVM to  
be powered with independent 1.8-V analog and digital supplies to provide  
higher performance.  
Voltage Limits  
Exceeding the maximum input voltages can damage EVM  
components. Undervoltage may cause improper operation of  
some or all of the EVM components.  
1-2  
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ADS5102/3 EVM Operational Procedure  
1.4 ADS5102/3 EVM Operational Procedure  
The ADS5102/3 EVM provides a flexible means of evaluating the ADS5102/3  
in a number of modes of operation. A basic setup procedure that can be used  
as a board confidence check is as follows:  
1) Verify all jumper settings against the schematic jumper list in Table 11  
and Table 12:  
Table 11.Two Pin Jumper List  
Jumper  
W10  
W11  
R39  
Function  
Installed  
Removed  
Default  
External REFT feed  
External REFB feed  
Positive analog input  
Negative analog input  
Positive analog input  
Negative analog input  
External  
Internal  
Removed  
Removed  
Installed  
Installed  
Removed  
Removed  
Removed  
External  
Internal  
Transformer coupled  
Transformer coupled  
Differential amplifier  
Differential amplifier  
No connection  
No connection  
No connection  
No connection  
R37  
R38  
R36  
R43, R44 Output clock option  
ADC clock at output connector Buff clock at output  
connector  
R42  
R14  
Optional output clock  
parallel termination  
Provides pullup termination  
No pullup termination  
Removed  
Removed  
Optional ADC clock  
parallel termination  
Provides pullup termination  
No pullup termination  
Table 12.Three Pin Jumper List  
Jumper  
Function  
Location: Pins 1–2  
Location: Pins 2–3  
Default  
W1  
Band gap input voltage  
(power down reference  
mode)  
REFT voltage to bandgap pin  
1.25 V to bandgap pin Removed  
W3  
Transformer and diff amp  
common mode select  
ADC output common mode  
voltage  
External common  
mode voltage  
12  
W4  
W5  
W6  
Power down select  
Output enable select  
Reference select  
Operate mode  
Power down mode  
Data bus enable  
Internal reference  
12  
23  
23  
Data bus tristate  
External reference  
2) Connect supplies to the EVM as follows:  
J
J
J
J
J
1.8-V analog supply to J6 and return to J5  
1.8-V digital supply to J9 and return to J10  
3.3-V driver supply to J13 and return to J14  
5-V analog supply to J7 and return to J8  
5-V analog supply to J11 and return to J8  
Overview  
1-3  
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ADS5102/3 EVM Operational Procedure  
3) Switch power supplies on.  
4) Use a function generator with 50-output to input a 40-MHz, 1.5-V offset,  
3-V amplitudesquarewavesignalintoJ3tobeusedastheADCclock.  
(p-p)  
Note:  
The frequency of the clock must be within the specification for the device  
speed grade.  
5) Use a function generator with 50-output to input a 1.5-V offset, 3-V  
(p-p)  
amplitude square wave signal into J4 to be used as the buffered output  
clock.  
Note:  
This signal must be the same frequency and synchronized with the ADC  
clock.  
6) Use a frequency generator with 50-output to input a 1.5-MHz, 0-V offset,  
0.4-V  
amplitude sine wave signal into J2. This provides a transformer  
(p-p)  
coupled differential signal to the ADC.  
7) The digital pattern on the output connector J15 now represents a sine  
wave and can be monitored using a logic analyzer.  
1-4  
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Chapter 2  
Physical Description  
ThischapterdescribesthephysicalcharacteristicsandPCBlayoutoftheEVM  
and lists the components used on the module.  
Topic  
Page  
2.1 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
2.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5  
2-1  
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PCB Layout  
2.1 PCB Layout  
The EVM is constructed on a 4-layer, 104 mm (4.1 inch) x 114 mm (4.5 inch)  
x 1,57 mm (0.062 inch) thick PCB using FR4 material. Figure 21 through  
Figure 24 show the individual layers.  
Figure 21. Top Layer  
2-2  
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PCB Layout  
Figure 22. Inner Layer 1, Ground Plane  
Physical Description  
2-3  
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PCB Layout  
Figure 23. Inner Layer 2, Power Plane  
2-4  
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Bill of Materials  
Figure 24. Bottom Layer  
2.2 Bill of Materials  
Table 21 lists the parts used in constructing the EVM.  
Table 21.Bill of Materials  
Description  
QTY Part Number  
MFG.  
REF DES  
47 µF, tantalum, 10%, 10 V  
0.1 µF,16 V, 10% capacitor  
10 µF, 10 V, 10% capacitor  
0.01 µF, 50 V,10% capacitor  
1.0 µF, 10 V, 10% capacitor  
22 pF, 50 V, 5%, capacitor  
0.001 µF, 16 V, 10% capacitor  
0.047 µF,16 V, 10% capacitor  
1.8 pF,16 V, 10% capacitor  
5
31  
9
10TPA47M  
SANYO  
Panasonic  
Murata  
AVX  
C72C76  
ECJ1VB1C104K  
GRM42X5R106K10  
C12C37, C62C66  
C51C54, C67C71  
C47C49 C60  
C40C46, C58, C59, C77  
C38, C39  
4
10  
2
AVX  
06035A220JAT2A  
AVX  
1
C50  
3
C55C57  
2
C1, C2  
Physical Description  
2-5  
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Bill of Materials  
Table 21. Bill of Materials (Continued)  
Description  
Qty. Part Number  
Mfg.  
Ref. Des.  
C3C7  
470 pF,16 V, 10% capacitor  
2.2 µF,16 V, 10% capacitor  
Ferrite bead  
5
1
5
3
1
9
2
1
2
1
3
6
3
C61  
FB1FB5  
R9R11  
R12  
499-resistor, 1/16 W, 1%  
523-resistor, 1/16 W, 1%  
49.9-resistor, 1/16 W, 1%  
1-kresistor, 1/16 W, 1%  
2.49-kresistor, 1/16 W, 1%  
475-resistor, 1/16 W, 1%  
953-resistor, 1/16 W, 1%  
2-kresistor, 1/16 W, 1%  
10-kresistor, 1/16 W, 1%  
100-resistor, 1/16 W, 1%  
ERJ3EKF499R0V  
ERJ3EKF523R0V  
ERJ3EKF49R9V  
Panasonic  
Panasonic  
Panasonic  
R1R8, R13  
R21, R22  
R23  
R24, R26  
R25  
R33R35  
R15R20  
R30R32  
R37R41  
0-resistor, 1/16 W, 1%  
4
ERJ3EKF0R00V  
Panasonic  
NOT INSTALLED:  
R14, R36, R38, R42R44  
1-kresistor, 1/16 W, 1%  
100-kresistor, 1/16 W, 1%  
3.01-kresistor, 1/16 W, 1%  
9.53-kresistor, 1/16 W, 1%  
1K Pot  
1
1
1
1
3
1
4
3
8
2
5
6
1
5
4
1
1
2
1
1
1
4
Panasonic  
Panasonic  
Panasonic  
Panasonic  
Bourns  
Mini-Circuits  
Macom  
Keystone  
Keystone  
Samtec  
Samtec  
Allied (molex)  
Samtec  
ALLIED  
ALLIED  
TI  
R46  
P100KHCTND  
R47  
R45  
ERJ6GEY0R00V  
3296Y102  
R51  
R27R29  
T1  
Transformer  
T11TKK81  
2262000009  
5011K  
SMA connectors  
Black test point  
Red test point  
J1J4  
TP9TP11  
TP1TP8  
W10, W11  
W1, W3W6  
5000K  
2POS_header  
TSW15007LS  
TSW15007LS  
8633285  
3POS_header  
2-circuit jumpers  
40-pin header  
TSW12007LD  
ST351A  
J15  
Red banana jacks  
Black banana jacks  
ADS51002/3  
J6, J7, J9, J1, J13  
ST351B  
J5, J8, J10, J14  
ADS5102/3  
U2  
TPS79225  
TPS79225DBVT  
742C163101JCT  
SN74AVC16244DGGR  
THS4141ID  
TI  
U4  
24-R-Pack  
Bourns  
TI  
RP1, RP2  
SN74AVC16244  
THS4141  
U6  
U1  
U3  
TI  
OPA4227  
OPA4227UA  
2192063  
TI  
Stand off hex (1/4 x 1)  
Allied  
2-6  
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Chapter 3  
Circuit Description  
This chapter describes the circuit function and shows the schematic for the  
EVM.  
Topic  
Page  
3.1 Circuit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
3.2 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4  
3-1  
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Circuit Function  
3.1 Circuit Function  
The following paragraphs describe the function of the individual circuits. See  
the data sheet for device operating characteristics.  
3.1.1 Analog Inputs  
The ADC has either transformer-coupled inputs or differential-amplifier inputs  
from a single-ended source. The inputs are provided via the SMA connectors  
J1 and J2 on the EVM, which must be configured as follows:  
- For a differential amplifier input to the ADC, a single ended source is  
connected to J1. R36 and R38 must be installed, and R37 and R39 must  
be removed. The input has a 50-terminator.  
- For a 1:1 transformer coupled input to the ADC, a single ended source is  
connected to J2. R36 and R38 must be removed, and R37 and R39 must  
be installed. The input is ac-coupled and has a 50-terminator.  
3.1.2 External Reference Inputs  
In addition to being able to use the internal reference of the ADC, a reference  
circuit has been included on the EVM. This circuit uses a precision 2.5-V,  
low-noise linear regulator as the primary source, and allows adjustment of the  
REFT and REFB signals to the ADC using potentiometers R27 and R28,  
respectively. A third source, CML, is also generated to provide an adjustable  
common mode voltage to be used by the transformer and differential amplifier  
during external reference operation. CML is adjusted by potentiometer R29.  
In order to use the ADC with external references, install jumpers W10 and  
W11, install jumper W3 between pins 2 and 3, jumper W6 between pins 1  
and 2, andjumperW1betweenpins1and2. IfREFTissettoanyvoltageother  
than1.25V, jumperW1mustbeinstalledbetweenpins2and3foroptimalADC  
performance. The ranges of the external reference signals are shown in  
Table 31.  
Table 31.Reference Voltage Adjustment Ranges  
Signal  
REFT  
Minimum Voltage  
0.9  
Typical Voltage  
Maximum Voltage  
1.25  
0.75  
1.0  
1.6  
0.9  
REFB  
CML  
0.3  
0.5  
1.25  
3-2  
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Thefollowingparagraphsdescribethefunctionoftheindividualcircuits.Seethedatasheetfordeviceoperatingcharacteristics.  
3.1.3 Clock Inputs  
The EVM provides separate inputs for the ADC clock and output buffer clock.  
This allows the user to send a modified version of the ADC clock (inverted,  
delayed, etc.) with the output data to generate the required setup and hold  
times for the user interface. The ADC clock input is SMA connector J3 and has  
provisions for serial and/or parallel termination. The buffered output clock  
input is SMA connector J4 and has provisions for serial and/or parallel  
termination. The clock inputs must be 50-square wave signals, 1.8-V or  
3.3-V referenced to ground, with a duty cycle of 50 ±5%. The EVM can operate  
with only one clock input by installing R43 and R44, and removing R41 and R8  
to prevent double termination.  
3.1.4 Control Inputs  
The ADC has three discrete inputs to control the operation of the device.  
3.1.4.1 Standby  
With jumper W4 installed between pins 2 and 3, the ADC is in power-down  
mode. The device is in operate mode with jumper W4 installed between pin 1  
and pin 2.  
3.1.4.2 Output Enable  
With jumper W5 installed between pins 1 and 2, the ADC data outputs are in  
a 3-state mode. The data outputs are enabled with jumper W5 installed  
between pins 2 and 3.  
3.1.4.3 Power Down Reference  
With jumper W6 installed between pins 1 and 2, the ADC internal reference  
is disabled and the device is in external reference mode. The ADC is in internal  
reference mode with jumper W6 installed between pins 2 and 3.  
3.1.5 Power  
Power is supplied to the EVM via banana jack sockets. A separate connection  
is provided for a 1.8-V analog supply (J6 and J5), a 1.8-V digital supply (J9 and  
J10), a 1.8/3.3-V digital driver supply (J13 and J14), and a ±5-V analog supply  
(J7, J8, and J11).  
3.1.6 Outputs  
The data outputs from the ADC are buffered using a SN74AVC16244 before  
going to header J15. The ADC and output buffer can provide 1.8-V or 3.3-V  
output levels. The voltage placed at the driver power inputs (J13 and J14)  
selects this. J15 is a standard 40-pin header on a 100-mil grid, and allows easy  
connection to a logic analyzer. The connector pin out is listed in Table 32.  
Circuit Description  
3-3  
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Schematic Diagram  
Table 32.Output Connector J15  
J15 Pin Description  
J15 Pin Description  
1
2
NC  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
Data Bit 6  
GND  
GND  
3
Output clock  
GND  
Data Bit 5  
GND  
4
5
NC  
Data Bit 4  
GND  
6
GND  
7
NC  
Data Bit 3  
GND  
8
GND  
9
NC  
Data Bit 2  
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
GND  
NC  
Data Bit 1  
GND  
GND  
NC  
Data Bit 0 (MSB)  
GND  
GND  
Data Bit 9 (MSB)  
GND  
NC  
GND  
Data Bit 8  
GND  
NC  
GND  
Data Bit 7  
GND  
NC  
GND  
3.2 Schematic Diagram  
The following figures show the schematic diagram for the EVM.  
3-4  
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2
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Revision History  
ECN Number  
R10  
499  
REV  
Approved  
C1  
+5VA  
1.8 pF  
C3  
C12  
AVDD  
U1  
THS4141  
470 pF  
0.1 uF  
D
C
B
A
D
C
B
A
J1  
AIN  
C40  
C13  
C41  
C14  
0.1 uF  
/PD  
+VCC  
(Note 1)  
R36  
1.0 uF  
0.1 uF  
1.0 uF  
R9  
R2  
1
8
2
1
5
4
AIN-  
+
499  
49.9  
0
VOUT-  
R37  
C38  
VOCM  
R1  
49.9  
0
22 pF  
VOUT+  
(Note 1)  
R3  
R38  
0
AIN+  
-
DVDD  
49.9  
-VCC  
R39  
0
C39  
-5VA  
R12  
523  
22 pF  
C20  
C43  
C47  
C16  
C5  
C18  
C2  
0.1 uF  
1.0 uF  
0.01 uF  
0.1 uF  
470 pF  
0.1 uF  
1.8 pF  
J2  
R11  
499  
AIN  
C15  
T1  
1
4
6
3
2
1
RP1  
0.1 uF  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
R13  
49.9  
AVDD  
NC_0  
NC_D00  
NC_D01  
D0  
T1-1T-KK81_XFMR  
NC_1  
D0  
1
2
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
N/C  
N/C  
N/C  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
C42  
C19  
C4  
470 pF  
C17  
C50  
0.001 uF  
R47  
100K  
AVDD  
1.0 uF  
0.1 uF  
0.1 uF  
3
D1  
AGND  
REFT  
REFB  
CML  
BG  
D1  
REFT  
REFB  
D2  
4
REFT  
REFB  
D2  
U2  
5
D3  
D3  
EXTERNAL_CML  
3
1
6
100  
EXTERNAL_CML  
W3  
7
ADS5102  
RP2  
2
C44  
1.0 uF  
C21  
0.1 uF  
8
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
D4  
D5  
D6  
D7  
D8  
D9  
W1  
+5VA  
N/C  
D4  
D5  
D6  
D7  
D8  
D9  
9
AGND  
N/C  
10  
11  
12  
R45  
3.01K  
N/C  
N/C  
R46  
1K  
DRVDD  
C46  
1.0 uF  
100  
C23  
0.1 uF  
DVDD  
R51  
DRVDD  
R14  
ADC_CLK  
C22  
0.1 uF  
C45  
(Note 2)  
ADC_CLK  
(Note 1)  
1.0 uF  
R43  
0
(Note 1)  
0
J3  
R40  
CLK  
1
Note 1. Part not installed  
INPUT CLOCK  
0
W4  
DRVDD  
R4  
49.9  
R17  
3
3
1
1
10K  
Note 2. For ADS5101, R51= 3.8K  
For ADS5102, R51= 4.42K  
For ADS5103, R51= 8.25K  
R16  
10K  
W5  
W6  
ꢀꢁ  
ADS5102  
R15  
10K  
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+5VA  
TP1  
D
C
B
A
R21  
1K  
D
C
B
A
C26  
0.1 uF  
C7  
470 pF  
U3A  
R27  
1k  
R18  
10K  
OPA4227UA  
R30  
100  
W10  
2
3
2
R5  
REFT  
1
(1.25V TYP)  
REFT  
49.9  
C51  
+
-5VA  
0.1%  
C48  
C58  
1 uF  
C24  
0.1 uF  
C55  
10 uF  
R33  
0.047 uF  
2.0 K  
0.01 uF  
C6  
470 pF  
C25  
0.1 uF  
R22  
1K  
+5VA  
TP2  
U4  
IN  
R23  
1
2
3
5
4
+2.5V  
OUT  
2.49K  
R28  
1k  
U3C  
R19  
10K  
R31  
100  
C52  
10 uF  
C61  
2.2 uF  
2
10  
9
W11  
+
C77  
1 uF  
GND  
R6  
8
REFB  
(0.75V TYP)  
REFB  
49.9  
C27  
C53  
+
0.1%  
OPA4227UA  
0.1 uF  
C49  
C59  
1 uF  
EN  
BYPASS  
C56  
0.047 uF  
10 uF  
R34  
2.0 K  
0.01 uF  
TPS79225  
R24  
475  
C60  
.01 uF  
R25  
953  
TP3  
R29  
1k  
U3B  
R20  
10K  
R32  
100  
2
5
6
R7  
7
EXTERNAL_CML  
(1V TYP)  
EXTERNAL_CML  
49.9  
C28  
0.1 uF  
C54  
+
0.1%  
OPA4227UA  
R35  
2.0 K  
10 uF  
C57  
0.047 uF  
R26  
475  
U3D  
12  
13  
14  
OPA4227UA  
ꢀꢁ  
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TP4  
TP5  
TP6  
TP7  
D
C
B
A
D
C
B
A
ADC Analog Supply (+1.8V)  
AVDD  
+1.8VA-PS  
+5VA-PS  
+5VA  
FB1  
FB2  
J6  
J7  
C29  
C63  
C30  
BANANA_JACK  
C62  
0.1 uF  
BANANA_JACK  
C72  
47 uF  
C67  
10 uF  
C73  
47 uF  
C68  
10 uF  
+
+
+
+
+
+
0.1 uF  
0.1 uF  
0.1 uF  
J5  
J8  
BANANA_JACK  
BANANA_JACK  
Analog Supply (+/-5volts) for Ext. Components  
TP8  
ADC Digital Supply (+1.8V)  
DVDD  
+1.8VD-PS  
-5VA-PS  
-5VA  
FB3  
FB4  
J9  
J11  
BANANA_JACK  
C31  
C65  
C32  
BANANA_JACK  
C64  
C74  
47 uF  
C69  
C75  
47 uF  
C70  
10 uF  
+
+
+
10 uF  
0.1 uF  
0.1 uF  
0.1 uF  
0.1 uF  
J10  
BANANA_JACK  
TP9  
TP10  
TP11  
ADC Driver Supply (+1.8V/3.3v)  
DRVDD  
+1.8V/+3.3VD-PS  
FB5  
J13  
C33  
BANANA_JACK  
C66  
C76  
47 uF  
C71  
+
10 uF  
0.1 uF  
0.1 uF  
J14  
BANANA_JACK  
ꢀꢁ  
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D
C
B
A
D
C
B
A
DRVDD  
C34  
C35  
C36  
C37  
0.1 uF  
0.1 uF  
0.1 uF  
0.1 uF  
DRVDD  
(Note 1)  
R42  
0
ADC_CLK  
ADC_CLK  
(Note 1)  
U6  
7
18  
31  
42  
1
R44  
0
DATA OUT  
J15  
VCC /OE1  
VCC /OE2  
VCC /OE3  
VCC /OE4  
48  
25  
24  
J4  
R41  
1
OUTPUT CLOCK  
0
R8  
49.9  
2
4
6
8
1
3
5
7
9
2
3
47  
46  
44  
43  
41  
40  
38  
37  
36  
35  
33  
32  
30  
29  
27  
26  
1Y1  
1Y2  
1Y3  
1Y4  
2Y1  
2Y2  
2Y3  
2Y4  
3Y1  
3Y2  
3Y3  
3Y4  
4Y1  
4Y2  
4Y3  
4Y4  
1A1  
1A2  
1A3  
1A4  
2A1  
2A2  
2A3  
2A4  
3A1  
3A2  
3A3  
3A4  
4A1  
4A2  
4A3  
4A4  
MSB  
5
D9  
10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
D8  
12 11  
14 13  
16 15  
18 17  
20 19  
22 21  
24 23  
26 25  
28 27  
30 29  
32 31  
34 33  
36 35  
38 37  
40 39  
6
8
D7  
9
D6  
11  
12  
13  
14  
16  
17  
19  
20  
22  
23  
D5  
D4  
D3  
D2  
D1  
D0  
NC_D01  
NC_D00  
NC_D01  
NC_D00  
40PIN_IDC  
LSB  
15  
45  
4
34  
28  
10  
21  
GND GND  
GND GND  
GND GND  
GND GND  
39  
SN74AVC16244DGG  
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