CC2420
2.4 GHz IEEE 802.15.4 / ZigBee-ready RF Transceiver
Applications
•
•
•
•
2.4 GHz IEEE 802.15.4 systems
ZigBee systems
Home/building automation
Industrial Control
•
•
•
Wireless sensor networks
PC peripherals
Consumer Electronics
Product Description
features reduce the load on the host
controller and allow CC2420 to interface
low-cost microcontrollers.
The CC2420 is a true single-chip 2.4 GHz
IEEE 802.15.4 compliant RF transceiver
designed for low power and low voltage
wireless applications. CC2420 includes a
digital direct sequence spread spectrum
baseband modem providing a spreading
gain of 9 dB and an effective data rate of
250 kbps.
The configuration interface and transmit /
receive FIFOs of CC2420 are accessed via
an SPI interface. In a typical application
CC2420 will be used together with a
microcontroller and a few external passive
components.
The CC2420 is a low-cost, highly integrated
solution for robust wireless communication
in the 2.4 GHz unlicensed ISM band. It
complies with worldwide regulations
covered by ETSI EN 300 328 and EN 300
440 class 2 (Europe), FCC CFR47 Part 15
(US) and ARIB STD-T66 (Japan).
CC2420 is based on Chipcon’s SmartRF®-
03 technology in 0.18 µm CMOS.
The CC2420 provides extensive hardware
support for packet handling, data
buffering, burst transmissions, data
encryption, data authentication, clear
channel assessment, link quality indication
and packet timing information. These
Key Features
•
True single-chip 2.4 GHz IEEE
802.15.4 compliant RF transceiver
with baseband modem and MAC
support
•
•
•
•
•
•
•
•
•
•
•
Programmable output power
No external RF switch / filter needed
I/Q low-IF receiver
I/Q direct upconversion transmitter
Very few external components
128(RX) + 128(TX) byte data buffering
Digital RSSI / LQI support
Hardware MAC encryption (AES-128)
Battery monitor
QLP-48 package, 7x7 mm
Complies with ETSI EN 300 328, EN
300 440 class 2, FCC CFR-47 part 15
and ARIB STD-T66
Powerful and flexible development
tools available
•
DSSS baseband modem with
2
MChips/s and 250 kbps effective data
rate.
Suitable for both RFD and FFD
operation
Low current consumption (RX: 18.8
mA, TX: 17.4 mA)
Low supply voltage (2.1 – 3.6 V) with
integrated voltage regulator
Low supply voltage (1.6 – 2.0 V) with
external voltage regulator
•
•
•
•
•
SWRS041B
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CC2420
SWRS041B
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CC2420
SWRS041B
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CC2420
1
Abbreviations
ADC
AES
AGC
-
-
-
Analog to Digital Converter
Advanced Encryption Standard
Automatic Gain Control
ARIB
BER
CBC-MAC
CCA
CCM
CFR
CSMA-CA
CTR
CW
DAC
DSSS
ESD
ESR
EVM
FCC
FCF
FIFO
FFCTRL
HSSD
IEEE
IF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Association of Radio Industries and Businesses
Bit Error Rate
Cipher Block Chaining Message Authentication Code
Clear Channel Assessment
Counter mode + CBC-MAC
Code of Federal Regulations
Carrier Sense Multiple Access with Collision Avoidance
Counter mode (encryption)
Continuous Wave
Digital to Analog Converter
Direct Sequence Spread Spectrum
Electro Static Discharge
Equivalent Series Resistance
Error Vector Magnitude
Federal Communications Commission
Frame Control Field
First In First Out
FIFO and Frame Control
High Speed Serial Debug
Institute of Electrical and Electronics Engineers
Intermediate Frequency
Industrial, Scientific and Medical
International Telecommunication Union – Telecommunication
Standardization Sector
Input / Output
ISM
ITU-T
I/O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/Q
In-phase / Quadrature-phase
kilo bits per second
Low-Noise Amplifier
kbps
LNA
LO
Local Oscillator
LQI
Link Quality Indication
Least Significant Bit / Byte
Medium Access Control
MAC Footer
LSB
MAC
MFR
MHR
MIC
MPDU
MSDU
NA
MAC Header
Message Integrity Code
MAC Protocol Data Unit
MAC Service Data Unit
Not Available
Not Connected
Offset - Quadrature Phase Shift Keying
Power Amplifier
Printed Circuit Board
Packet Error Rate
Physical Layer
PHY Header
NC
O-QPSK
PA
PCB
PER
PHY
PHR
PLL
PSDU
QLP
RAM
RBW
RF
Phase Locked Loop
PHY Service Data Unit
Quad Leadless Package
Random Access Memory
Resolution BandWidth
Radio Frequency
RSSI
RX
Receive Signal Strength Indicator
Receive
SWRS041B
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CC2420
SHR
SPI
TBD
T/R
TX
VCO
VGA
-
-
-
-
-
-
-
Synchronisation Header
Serial Peripheral Interface
To Be Decided / To Be Defined
Transmit / Receive
Transmit
Voltage Controlled Oscillator
Variable Gain Amplifier
2
References
[1]
IEEE std. 802.15.4 - 2003: Wireless Medium Access Control (MAC) and
Physical Layer (PHY) specifications for Low Rate Wireless Personal Area
Networks (LR-WPANs)
[2]
[3]
NIST FIPS Pub 197: Advanced Encryption Standard (AES), Federal
Information Processing Standards Publication 197, US Department of
Commerce/N.I.S.T., November 26, 2001. Available from the NIST website.
R. Housley, D. Whiting, N. Ferguson, Counter with CBC-MAC (CCM),
submitted to NIST, June 3, 2002. Available from the NIST website.
SWRS041B
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CC2420
3
Features
•
2400 – 2483.5 MHz RF Transceiver
•
802.15.4 MAC hardware support:
•
•
•
•
Direct
Sequence
Spread
•
•
Automatic preamble generator
Spectrum (DSSS) transceiver
250 kbps data rate, 2 MChip/s
chip rate
O-QPSK with half sine pulse
shaping modulation
Very low current consumption
(RX: 18.8 mA, TX: 17.4 mA)
High sensitivity (-95 dBm)
High adjacent channel rejection
(30/45 dB)
Synchronisation
word
insertion/detection
•
CRC-16
computation
and
checking over the MAC payload
Clear Channel Assessment
Energy detection / digital RSSI
Link Quality Indication
Full automatic MAC security
(CTR, CBC-MAC, CCM)
•
•
•
•
•
•
•
High alternate channel rejection
(53/54 dB)
•
802.15.4 MAC hardware security:
•
•
On-chip VCO, LNA and PA
Low supply voltage (2.1 – 3.6 V)
with on-chip voltage regulator
Programmable output power
I/Q low-IF soft decision receiver
•
Automated security operations
within the receive and transmit
FIFOs.
•
•
•
•
•
•
CTR mode encryption / decryption
CBC-MAC authentication
CCM encryption / decryption and
authentication
I/Q
direct
up-conversion
transmitter
•
Stand-alone AES encryption
•
•
Separate transmit and receive FIFOs
•
•
128 byte transmit data FIFO
128 byte receive data FIFO
•
Development tools available
•
•
Fully equipped development kit
Demonstration board reference
design with microcontroller code
Very few external components
•
Easy-to-use
generating the CC2420 configu-
ration data
software
for
•
Only reference crystal and
minimised number of passives
No external filters needed
a
•
•
•
Small size QLP-48 package, 7 x 7 mm
Complies with EN 300 328, EN 300
440 class 2, FCC CFR47 part 15 and
ARIB STD-T66
•
Easy configuration interface
•
•
4-wire SPI interface
Serial clock up to 10 MHz
SWRS041B
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CC2420
4
Absolute Maximum Ratings
Parameter
Min.
Max.
Units
Condition
Supply voltage for on-chip voltage regulator,
-0.3
3.6
V
VREG_INpin 43.
Supply voltage (VDDIO) for digital I/Os, DVDD3.3,
pin 25.
-0.3
3.6
2.0
V
V
Supply voltage (VDD) on AVDD_VCO, DVDD1.8,
etc (pin no 1, 2, 3, 4, 10, 14, 15, 17, 18, 20, 26, 35,
37, 44 and 48)
−0.3
Voltage on any digital I/O pin, (pin no. 21, 27-34
and 41)
-0.3
-0.3
VDDIO+0.3, max 3.6
VDD+0.3, max 2.0
V
V
Voltage on any other pin, (pin no. 6, 7, 8, 11, 12,
13, 16, 36, 38, 39, 40, 45, 46 and 47)
Input RF level
10
dBm
°C
Storage temperature range
Reflow solder temperature
−50
150
260
T = 10 s
°C
The absolute maximum ratings given
above should under no circumstances be
violated. Stress exceeding one or more of
the limiting values may cause permanent
damage to the device.
Caution!
ESD
sensitive
device.
Precaution should be used when handling
the device in order to prevent permanent
damage.
5
Operating Conditions
Parameter
Supply voltage for on-chip voltage regulator,
Min. Typ.
Max. Units Condition
2.1
3.6
V
VREG_INpin 43.
Supply voltage (VDDIO) for digital I/Os, DVDD3.3,
pin 25 .
1.6
3.6
V
The digital I/O voltage (DVDD3.3pin)
must match the external interfacing
circuit (e.g. microcontroller).
Supply voltage (VDD) on AVDD_VCO, DVDD1.8,
etc (pin no 1, 2, 3, 4, 10, 14, 15, 17, 18, 20, 26, 35,
37, 44 and 48)
1.6
1.8
2.0
85
V
The typical application uses regulated
1.8 V supply generated by the on-chip
voltage regulator.
Operating ambient temperature range, TA
−40
°C
SWRS041B
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CC2420
6
Electrical Specifications
Measured on CC2420 EM with transmission line balun, TA = 25 °C, DVDD3.3and VREG_IN= 3.3 V, internal
voltage regulator used if nothing else stated.
6.1 Overall
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
RF Frequency Range
2400
2483.5 MHz
Programmable in 1 MHz steps, 5
MHz steps for compliance with [1]
6.2 Transmit Section
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
Transmit bit rate
250
250
kbps
As defined by [1]
Transmit chip rate
2000
-3
2000
kChips/s As defined by [1]
Nominal output power
0
dBm
dB
Delivered to a single ended 50 Ω
load through a balun.
[1] requires minimum –3 dBm
Programmable output power range
24
The output power is
programmable in 8 steps from
approximately –24 to 0 dBm.
Harmonics
2
3
nd harmonic
rd harmonic
-44
-64
dBm
dBm
Measured conducted with 1 MHz
resolution bandwidth on spectrum
analyser. At max output power
delivered to a single ended 50 Ω
load through a balun. See page
Spurious emission
Maximum output power.
30 - 1000 MHz
1– 12.75 GHz
1.8 – 1.9 GHz
5.15 – 5.3 GHz
-56
-44
-56
-51
dBm
dBm
dBm
dBm
Complies with EN 300 328, EN
300 440, FCC CFR47 Part 15
and ARIB STD-T-66
Error Vector Magnitude (EVM)
Optimum load impedance
11
%
Measured as defined by [1]
[1] requires max. 35 %
95
+ j187
Differential impedance as seen
from the RF-port (RF_Pand
RF_N) towards the antenna. For
Ω
SWRS041B
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CC2420
6.3 Receive Section
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
Receiver Sensitivity
-90
-95
dBm
PER = 1%, as specified by [1]
Measured in a 50Ω single-ended
load through a balun.
[1] requires –85 dBm
Saturation (maximum input level)
0
10
dBm
PER = 1%, as specified by [1]
Measured in a 50Ω single–ended
load through a balun.
[1] requires –20 dBm
Adjacent channel rejection
+ 5 MHz channel spacing
Wanted signal @ -82 dBm,
adjacent modulated channel at
+5 MHz, PER = 1 %, as specified
by [1].
45
30
54
53
dB
dB
dB
dB
[1] requires 0 dB
Adjacent channel rejection
- 5 MHz channel spacing
Wanted signal @ -82 dBm,
adjacent modulated channel at
-5 MHz, PER = 1 %, as specified
by [1].
[1] requires 0 dB
Alternate channel rejection
+ 10 MHz channel spacing
Wanted signal @ -82 dBm,
adjacent modulated channel at
+10 MHz, PER = 1 %, as
specified by [1]
[1] requires 30 dB
Alternate channel rejection
- 10 MHz channel spacing
Wanted signal @ -82 dBm,
adjacent modulated channel at
-10 MHz, PER = 1 %, as
specified by [1]
[1] requires 30 dB
Channel rejection
≥ + 15 MHz
Wanted signal @ -82 dBm.
Undesired signal is an IEEE
802.15.4 modulated channel,
stepped through all channels
from 2405 to 2480 MHz. Signal
level for PER = 1%.
62
62
dB
dB
≤ - 15 MHz
Co-channel rejection
Wanted signal @ -82 dBm.
Undesired signal is an IEEE
802.15.4 modulated at the same
frequency as the desired signal.
Signal level for PER = 1%.
-3
dB
Blocking / Desensitisation
+/- 5 MHz from band edge
+/- 20 MHz from band edge
+/- 30 MHz from band edge
+/- 50 MHz from band edge
-28
-28
-27
-28
dBm
dBm
dBm
dBm
Wanted signal 3 dB above the
sensitivity level, CW jammer,
PER = 1%. Complies with EN
300 440 class 2.
Spurious emission
30 – 1000 MHz
1 – 12.75 GHz
-73
-58
dBm
dBm
Conducted measurement in a 50
Ω single ended load. Measured
according to EN 300 328, EN 300
440 class 2, FCC CFR47, Part 15
and ARIB STD-T-66
SWRS041B
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CC2420
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
Frequency error tolerance
-300
300
kHz
Difference between centre
frequency of the received RF
signal and local oscillator
frequency
[1] requires 200 kHz
Symbol rate error tolerance
Data latency
120
ppm
Difference between incoming
symbol rate and the internally
generated symbol rate
[1] requires 80 ppm
3
Processing delay in receiver.
Time from complete transmission
of SFD until complete reception
of SFD, i.e. from SFD goes active
on transmitter until active on
receiver.
µs
6.4 RSSI / Carrier Sense
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
Carrier sense level
− 77
dBm
Programmable in
RSSI.CCA_THR
RSSI dynamic range
RSSI accuracy
100
dB
dB
dB
µs
The range is approximately from
–100 dBm to 0 dBm
± 6
RSSI linearity
± 3
RSSI average time
128
8 symbol periods, as specified by
[1]
6.5 IF Section
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
Intermediate frequency (IF)
2
MHz
6.6 Frequency Synthesizer Section
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
Crystal oscillator frequency
16
MHz
Crystal frequency accuracy
requirement
- 40
40
ppm
Including aging and temperature
dependency, as specified by [1]
Crystal operation
Parallel
C381 and C391 are loading
SWRS041B
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CC2420
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
Crystal load capacitance
12
16
20
pF
16 pF recommended
Crystal ESR
60
Ω
Crystal oscillator start-up time
Phase noise
1.0
ms
16 pF load
Unmodulated carrier
−109
−117
−117
−117
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
At ±1 MHz offset from carrier
At ±2 MHz offset from carrier
At ±3 MHz offset from carrier
At ±5 MHz offset from carrier
PLL loop bandwidth
PLL lock time
100
kHz
192
The startup time from the crystal
oscillator is running and RX / TX
turnaround time
µs
6.7 Digital Inputs/Outputs
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
General
Signal levels are referred to the
voltage level at pin DVDD3.3
Logic "0" input voltage
Logic "1" input voltage
0
0.3*
DVDD
V
V
0.7*
DVDD
DVDD
Logic "0" output voltage
Logic "1" output voltage
Logic "0" input current
Logic "1" input current
FIFOsetup time
0
0.4
VDD
−1
V
V
Output current −8 mA,
3.3 V supply voltage
2.5
NA
NA
20
Output current 8 mA,
3.3 V supply voltage
Input signal equals GND
Input signal equals VDD
µA
µA
ns
1
TX unbuffered mode, minimum
time FIFOmust be ready before
the positive edge of FIFOP
FIFOhold time
10
ns
TX unbuffered mode, minimum
time FIFOmust be held after the
positive edge of FIFOP
Serial interface pins (SCLK, SI, SO
and CSn) timing specification
SWRS041B
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CC2420
6.8 Voltage Regulator
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
Note that the internal voltage
General
regulator can only supply
CC2420 and no external circuitry.
Input Voltage
2.1
1.7
13
3.0
1.8
20
3.6
1.9
29
V
On the VREG_INpin
Output Voltage
Quiescent current
V
On the VREG_OUTpin
No current drawn from the
VREG_OUTpin. Min and max
numbers include 2.1 through 3.6
V input voltage
µA
Start-up time
0.3
0.6
ms
6.9 Battery Monitor
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
Current consumption
6
30
90
When enabled
µA
Start-up time
Settling time
Step size
100
2
Voltage regulator already enabled
New toggle voltage programmed
µs
µs
50
10
80
50
mV
mV
mV
mV
Hysteresis
Absolute accuracy
Relative accuracy
-80
-50
May be software calibrated for
known reference voltage
6.10 Power Supply
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
Current consumption in different
Current drawn from VREG_IN,
through voltage regulator
Voltage regulator off (OFF)
Power Down mode (PD)
Idle mode (IDLE)
0.02
20
426
1
Voltage regulator off
Voltage regulator on
Including crystal oscillator and
voltage regulator
µA
µA
µA
Current Consumption,
receive mode
18.8
mA
SWRS041B
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CC2420
Parameter
Min.
Typ.
Max.
Unit
Condition / Note
Current Consumption,
transmit mode:
P = -25 dBm
P = -15 dBm
P = -10 dBm
P = −5 dBm
P = 0 dBm
8.5
9.9
11
14
17.4
mA
mA
mA
mA
mA
The output power is delivered
differentially to a 50 Ω singled
ended load through a balun, see
SWRS041B
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CC2420
7
Pin Assignment
1
36
35
34
33
32
VCO_GUARD
NC
2
AVDD_VCO
DVDD_RAM
3
AVDD_PRE
SO
4
SI
AVDD_RF1
SCLK
5
6
7
8
9
GND
RF_P
31
30
29
28
27
26
25
CSn
CC2420
FIFO
TXRX_SWITCH
RF_N
FIFOP
CCA
GND
AVDD_SW 10
SFD
NC
NC
11
12
DVDD1.8
DVDD3.3
AGND
Exposed die
attach pad
Figure 1. CC2420 Pinout – Top View
Pin
Pin Name
Pin type
Pin Description
AGND
-
Ground (analog)
Exposed die attach pad. Must be connected to solid ground
plane
VCO_GUARD
AVDD_VCO
AVDD_PRE
AVDD_RF1
GND
1
2
3
4
5
6
Power (analog)
Power (analog)
Power (analog)
Power (analog)
Ground (analog)
RF I/O
Connection of guard ring for VCO (to AVDD) shielding
1.8 V Power supply for VCO
1.8 V Power supply for Prescaler
1.8 V Power supply for RF front-end
Grounded pin for RF shielding
RF_P
Positive RF input/output signal to LNA/from PA in
receive/transmit mode
TXRX_SWITCH
RF_N
7
8
Power (analog)
RF I/O
Common supply connection for integrated RF front-end. Must
be connected to RF_Pand RF_Nexternally through a DC
path
Negative RF input/output signal to LNA/from PA in
receive/transmit mode
GND
9
Ground (analog)
Grounded pin for RF shielding
AVDD_SW
NC
NC
10
11
12
13
14
15
Power (analog)
-
-
-
Power (analog)
Power (analog)
1.8 V Power supply for LNA / PA switch
Not Connected
Not Connected
Not Connected
1.8 V Power supply for receive and transmit mixers
1.8 V Power supply for transmit / receive IF chain
NC
AVDD_RF2
AVDD_IF2
SWRS041B
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CC2420
Pin
Pin Name
Pin type
Pin Description
NC
16
17
18
19
20
21
22
23
24
25
26
27
28
29
-
Not Connected
AVDD_ADC
DVDD_ADC
DGND_GUARD
DGUARD
RESETn
DGND
DSUB_PADS
DSUB_CORE
DVDD3.3
DVDD1.8
SFD
Power (analog)
Power (digital)
Ground (digital)
Power (digital)
Digital Input
Ground (digital)
Ground (digital)
Ground (digital)
Power (digital)
Power (digital)
Digital output
Digital output
Digital output
1.8 V Power supply for analog parts of ADCs and DACs
1.8 V Power supply for digital parts of receive ADCs
Ground connection for digital noise isolation
1.8 V Power supply connection for digital noise isolation
Asynchronous, active low digital reset
Ground connection for digital core and pads
Substrate connection for digital pads
Substrate connection for digital modules
3.3 V Power supply for digital I/Os
1.8 V Power supply for digital core
SFD (Start of Frame Delimiter) / digital mux output
CCA (Clear Channel Assessment) / digital mux output
Active when number of bytes in FIFO exceeds threshold /
serial RF clock output in test mode
CCA
FIFOP
FIFO
30
Digital I/O
Active when data in FIFO /
serial RF data input / output in test mode
CSn
SCLK
SI
31
32
33
34
Digital input
Digital input
Digital input
Digital output
(tristate)
SPI Chip select, active low
SPI Clock input, up to 10 MHz
SPI Slave Input. Sampled on the positive edge of SCLK
SPI Slave Output. Updated on the negative edge of SCLK.
Tristate when CSn high.
SO
DVDD_RAM
NC
AVDD_XOSC16
XOSC16_Q2
XOSC16_Q1
NC
35
36
37
38
39
40
41
Power (digital)
-
Power (analog)
Analog I/O
Analog I/O
-
1.8 V Power supply for digital RAM
Not Connected
1.8 V crystal oscillator power supply
16 MHz Crystal oscillator pin 2
16 MHz Crystal oscillator pin 1 or external clock input
Not Connected
Voltage regulator enable, active high, held at VREG_IN
voltage level when active. Note that VREG_EN is relative
VREG_IN, not DVDD3.3.
VREG_EN
Digital input
VREG_OUT
VREG_IN
AVDD_IF1
R_BIAS
ATEST2
ATEST1
42
43
44
45
46
47
48
Power output
Power (analog)
Power (analog)
Analog output
Analog I/O
Voltage regulator 1.8 V power supply output
Voltage regulator 2.1 to 3.6 V power supply input
1.8 V Power supply for transmit / receive IF chain
External precision resistor, 43 kΩ, ± 1 %
Analog test I/O for prototype and production testing
Analog test I/O for prototype and production testing
1.8 V Power supply for phase detector and charge pump
Analog I/O
Power (analog)
AVDD_CHP
NOTES:
The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the
chip.
SWRS041B
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CC2420
8
Circuit Description
AUTOMATIC GAIN CONTROL
DIGITAL
DEMODULATOR
ADC
- Digital RSSI
Serial
voltage
regulator
- Gain Control
- Image Suppression
- Channel Filtering
- Demodulation
- Frame
LNA
ADC
synchronization
TX/RX CONTROL
DIGITAL
INTERFACE
WITH FIFO
BUFFERS,
CRC AND
®
SmartRF
0
FREQ
SYNTH
90
CC2420
ENCRYPTION
TX POWER CONTROL
DAC
DIGITAL
MODULATOR
Power
Control
Digital and
Analog test
interface
- Data spreading
- Modulation
PA
Σ
XOSC
On-chip
DAC
BIAS
R
16 MHz
Figure 2. CC2420 simplified block diagram
A simplified block diagram of CC2420 is
The CC2420 transmitter is based on direct
up-conversion. The data is buffered in a
128 byte transmit FIFO (separate from the
receive FIFO). The preamble and start of
frame delimiter are generated by
hardware. Each symbol (4 bits) is spread
using the IEEE 802.15.4 spreading
sequence to 32 chips and output to the
digital-to-analog converters (DACs).
CC2420 features a low-IF receiver. The
received RF signal is amplified by the low-
noise amplifier (LNA) and down-converted
in quadrature (I and Q) to the intermediate
frequency (IF). At IF (2 MHz), the complex
I/Q signal is filtered and amplified, and
then digitized by the ADCs. Automatic
gain control, final channel filtering, de-
spreading, symbol correlation and byte
synchronisation are performed digitally.
An analog low pass filter passes the signal
to the quadrature (I and Q) upconversion
mixers. The RF signal is amplified in the
power amplifier (PA) and fed to the
antenna.
When the SFD pin goes active, this
indicates that a start of frame delimiter has
been detected. CC2420 buffers the
received data in a 128 byte receive FIFO.
The user may read the FIFO through an
SPI interface. CRC is verified in hardware.
RSSI and correlation values are appended
to the frame. CCA is available on a pin in
receive mode. Serial (unbuffered) data
modes are also available for test
purposes.
The internal T/R switch circuitry makes the
antenna interface and matching easy. The
RF connection is differential. A balun may
be used for single-ended antennas. The
biasing of the PA and LNA is done by
connecting TXRX_SWITCH to RF_P and
RF_Nthrough an external DC path.
The frequency synthesizer includes a
completely on-chip LC VCO and a 90
degrees phase splitter for generating the I
SWRS041B
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CC2420
and Q LO signals to the down-conversion
mixers in receive mode and up-conversion
mixers in transmit mode. The VCO
operates in the frequency range 4800 –
4966 MHz, and the frequency is divided by
two when split in I and Q.
The 4-wire SPI serial interface is used for
configuration and data buffering.
An on-chip voltage regulator delivers the
regulated 1.8 V supply voltage. The
voltage regulator may be enabled
disabled through a separate pin.
/
A
crystal must be connected to
XOSC16_Q1 and XOSC16_Q2 and
provides the reference frequency for the
synthesizer. digital lock signal is
A battery monitor may optionally be used
to monitor the unregulated power supply
A
voltage.
The
battery
monitor
is
available from the PLL.
configurable through the SPI interface.
The digital baseband includes support for
frame handling, address recognition, data
buffering and MAC security.
SWRS041B
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CC2420
9
Application Circuit
Few external components are required for
the operation of CC2420. typical
If a balanced antenna such as a folded
dipole is used, the balun can be omitted. If
the antenna also provides a DC path from
the TXRX_SWITCH pin to the RF pins,
inductors are not needed for DC bias.
A
application circuit is shown in Figure 4.
The external components shown are
described in Table 1 and typical values
decoupling capacitors are not shown on
the application circuits. For the complete
reference design please refer to Texas
circuit using a differential antenna. The
antenna type is a standard folded dipole.
The dipole has a virtual ground point;
hence
bias
is
provided
without
degradation in antenna performance.
9.1 Input / output matching
The RF input/output is high impedance
and differential. The optimum differential
load for the RF port is 95+j187 Ω.
9.2 Bias resistor
The bias resistor R451 is used to set an
accurate bias current.
When using an unbalanced antenna such
as a monopole, a balun should be used in
order to optimise performance. The balun
can be implemented using low-cost
discrete inductors and capacitors only or
in combination with transmission lines.
9.3 Crystal
An external crystal with two loading
capacitors (C381 and C391) is used for
details.
Figure 3 shows the balun implemented in
a two-layer reference design. It consists of
a half wave transmission line, C81, L61,
L71 and L81. The circuit will present the
optimum RF termination to CC2420 with a
50 Ω load on the antenna connection. This
circuit has improved EVM performance,
sensitivity and harmonic suppression
Please refer to the input/output matching
9.4 Voltage regulator
The on chip voltage regulator supplies all
1.8 V power supply inputs. C42 is required
for stability of the regulator. A series
resistor may be used to comply with the
ESR requirement.
9.5 Power supply decoupling and
filtering
The balun in Figure 4 consists of C61,
C62, C71, C81, L61, L62 and L81, and will
present the optimum RF termination to
CC2420 with a 50 Ω load on the antenna
connection. A low pass filter may be
added to add margin to the FCC
requirement on second harmonic level.
Proper power supply decoupling must be
used for optimum performance. The
placement and size of the decoupling
capacitors and the power supply filtering
are very important to achieve the best
performance in an application. Texas
Instruments provides a compact reference
design that should be followed very
closely..
SWRS041B
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CC2420
Ref
Description
C42
C61
C62
C71
C81
C381
C391
L61
Voltage regulator load capacitance
Balun and match
DC block to antenna and match
Front-end bias decoupling and match
Balun and match
16MHz crystal load capacitor, see page 53
16MHz crystal load capacitor, see page 53
DC bias and match
L62
DC bias and match
L71
DC bias and match
L81
Balun and match
R451
XTAL
Precision resistor for current reference generator
16MHz crystal, see page 53
Table 1. Overview of external components
3.3 V
Power
supply
C391 C381
C42
R451
XTAL
1
2
3
4
36
35
34
33
32
VCO_GUARD
AVDD_VCO
AVDD_PRE
NC
DVDD_RAM
SO
Antenna
(50 Ohm)
SI
AVDD_RF1
GND
λ/2
λ/2
SCLK
5
CC2420
L71
6
RF_P
RF
CSn 31
C81
L81
L61
7
FIFO 30
TXRX_SWITCH
RF_N
Transceiver
8
29
28
27
26
25
FIFOP
9
GND
CCA
SFD
AVDD_SW
NC
10
11
12
DVDD1.8
DVDD3.3
NC
Figure 3. Typical application circuit with transmission line balun for single-ended
operation
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CC2420
3.3 V
Power
supply
C391
XTAL
C381
R451
C42
1
2
3
4
36
NC
VCO_GUARD
AVDD_VCO
AVDD_PRE
DVDD_RAM
SO
35
34
33
32
Antenna
(50 Ohm)
SI
AVDD_RF1
GND
C61
C71
SCLK
5
CC2420
RF_P
L62
6
CSn 31
L61
C62
RF
7
FIFO 30
TXRX_SWITCH
RF_N
Transceiver
8
29
28
27
26
25
FIFOP
CCA
L81
C81
9
GND
AVDD_SW
NC
10
11
12
SFD
DVDD1.8
DVDD3.3
NC
Figure 4. Typical application circuit with discrete balun for single-ended operation
SWRS041B
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CC2420
3.3 V
Power
supply
C391
XTAL
C381
R451
C42
1
2
3
4
36
35
34
33
32
VCO_GUARD
AVDD_VCO
AVDD_PRE
NC
DVDD_RAM
SO
SI
AVDD_RF1
SCLK
5 GND
6 RF_P
7
CC2420
RF
CSn 31
Folded
dipole
antenna
L61
FIFO 30
TXRX_SWITCH
L71
Transceiver
8
29
28
27
26
25
FIFOP
CCA
RF_N
9 GND
AVDD_SW
10
11
12
SFD
NC
NC
DVDD1.8
DVDD3.3
Figure 5. Suggested application circuit with differential antenna (folded dipole)
SWRS041B
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CC2420
Item
Single
ended
output, Single
ended
output, Differential antenna
transmission line balun
10 µF, 0.5Ω < ESR < 5Ω
Not used
discrete balun
C42
C61
C62
C71
C81
C381
C391
L61
10 µF, 0.5Ω < ESR < 5Ω
0.5 pF, +/- 0.25pF, NP0, 0402
5.6 pF, +/- 0.25pF, NP0, 0402
5.6 pF, 10%, X5R, 0402
0.5 pF, +/- 0.25pF, NP0, 0402
27 pF, 5%, NP0, 0402
10 µF, 0.5Ω < ESR < 5Ω
Not used
Not used
Not used
Not used
Not used
5.6 pF, +/- 0.25pF, NP0, 0402
27 pF, 5%, NP0, 0402
27 pF, 5%, NP0, 0402
Not used
27 pF, 5%, NP0, 0402
27 pF, 5%, NP0, 0402
27 pF, 5%, NP0, 0402
8.2 nH, 5%,
Monolithic/multilayer, 0402
7.5 nH, 5%,
Monolithic/multilayer, 0402
27 nH, 5%, Monolithic/multilayer,
0402
L62
L71
L81
Not used
5.6 nH, 5%,
Monolithic/multilayer, 0402
Not used
22 nH, 5%,
Monolithic/multilayer, 0402
Not used
12 nH, 5%, Monolithic/multilayer,
0402
1.8 nH, +/- 0.3nH,
7.5 nH, 5%,
Not used
Monolithic/multilayer, 0402
Monolithic/multilayer, 0402
R451
XTAL
43 kΩ, 1%, 0402
43 kΩ, 1%, 0402
43 kΩ, 1%, 0402
16 MHz crystal, 16 pF load
(CL),
ESR < 60 Ω
16 MHz crystal, 16 pF load
(CL),
ESR < 60 Ω
16 MHz crystal, 16 pF load (CL),
ESR < 60 Ω
Table 2. Bill of materials for the application circuits
SWRS041B
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CC2420
10 IEEE 802.15.4 Modulation Format
This section is meant as an introduction to
the 2.4 GHz direct sequence spread
spectrum (DSSS) RF modulation format
defined in IEEE 802.15.4. For a complete
description, please refer to [1].
least significant byte is transmitted first,
except for security related fields where the
most significant byte it transmitted first.
Each symbol is mapped to one out of 16
pseudo-random sequences, 32 chips
each. The symbol to chip mapping is
shown in Table 3. The chip sequence is
then transmitted at 2 MChips/s, with the
least significant chip (C0) transmitted first
for each symbol.
The modulation and spreading functions
are illustrated at block level in Figure 6 [1].
Each byte is divided into two symbols, 4
bits each. The least significant symbol is
transmitted first. For multi-byte fields, the
Transmitted
bit-stream
(LSB first)
Bit-to-
Symbol
Symbol-
to-Chip
O-QPSK
Modulator
Modulated
Signal
Figure 6. Modulation and spreading functions [1]
Symbol
Chip sequence (C0, C1, C2, … , C31)
0
1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0
1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0
0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0
0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1
0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1
0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0
1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1
1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1
1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1
1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1
0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1
0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0
0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0
0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1
1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0
1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0
Table 3. IEEE 802.15.4 symbol-to-chip mapping [1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
The modulation format is Offset
–
is shaped as a half-sine, transmitted
alternately in the I and Q channels with
one half chip period offset. This is
Quadrature Phase Shift Keying (O-QPSK)
with half-sine chip shaping. This is
equivalent to MSK modulation. Each chip
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CC2420
TC
1
0
1
1
0
1
0
1
0
1
0
0
0
0
1
1
I-phase
Q-phase
1
1
0
1
1
0
0
1
1
1
0
0
0
0
1
0
2TC
Figure 7. I / Q Phases when transmitting a zero-symbol chip sequence, TC = 0.5 µs
11 Configuration Overview
CC2420 can be configured to achieve the
best performance for different
applications. Through the programmable
configuration registers the following key
parameters can be programmed:
•
•
Power-down / power-up mode
Crystal oscillator power-up / power
down
Clear Channel Assessment mode
Packet handling hardware support
Encryption / Authentication modes
•
•
•
•
•
•
Receive / transmit mode
RF channel selection
RF output power
SWRS041B
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CC2420
12 Evaluation Software
Texas Instruments (TI) provides users of
Studio can be downloaded from TI’s web
the user interface of the CC2420
configuration software.
CC2420 with
a
software program,
SmartRF® Studio (Windows interface)
which may be used for radio performance
and functionality evaluation. SmartRF®
Figure 8. SmartRF Studio user interface
SWRS041B
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CC2420
13 4-wire Serial Configuration and Data Interface
RAM/Register bit (set to 0 for register
access), followed by the R/W bit (0 for
write, 1 for read). The following 6 bits are
the address-bits (A5:0). A5 is the most
significant bit of the address and is sent
first. The 16 data-bits are then transferred
an illustration.
CC2420 is configured via a simple 4-wire
SPI-compatible interface (pins SI, SO,
SCLKand CSn) where CC2420 is the slave.
This interface is also used to read and
address and data transfer on the SPI
interface is done most significant bit first.
13.1 Pin configuration
The configuration registers can also be
read by the microcontroller via the same
configuration interface. The R/W bit must
be set high to initiate the data read-back.
CC2420 then returns the data from the
addressed register on the 16 clock cycles
following the register address. The SO pin
is used as the data output and must be
configured as an input by the
microcontroller.
The digital inputs SCLK, SI and CSn are
high-impedance inputs (no internal pull-
up) and should have external pull-ups if
not driven. SO is high-impedance when
CSnis high. An external pull-up should be
used at SO to prevent floating input at
microcontroller. Unused I/O pins on the
MCU can be set to outputs with a fixed ‘0’
level to avoid leakage currents.
The timing for the programming is also
CC2420 is done on the positive edge of
SCLK. When the last bit, D0, of the 16
data-bits has been written, the data word
is loaded in the internal configuration
register.
13.2 Register access
There are 33 16-bit configuration and
status registers, 15 command strobe
registers, and two 8-bit registers to access
the separate transmit and receive FIFOs.
Each of the 50 registers is addressed by a
6-bit address. The RAM/Register bit (bit 7)
must be cleared for register access. The
Read/Write bit (bit 6) selects a read or a
write operation and makes up the 8-bit
address field together with the 6-bit
address.
Multiple registers may be written without
The register data will be retained during
power down mode, but not when the
power-supply is turned off (e.g. by
disabling the voltage regulator using the
VREG_EN pin). The registers can be
programmed in any order.
In each register read or write cycle, 24 bits
are sent on the SI-line. The CSnpin (Chip
Select, active low) must be kept low during
this transfer. The bit to be sent first is the
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CC2420
tsp
tch
thd
tcl
tsd
tns
SCLK
CSn
Write to register / RXFIFO:
0
A5
S5
A4
S4
A3
S3
A2
S2
A1
A0
S0
X
X
DW15 DW14 DW13 DW12 DW11 DW10 DW
9
1
DW
8
0
X
DW
7
7
DW
6
6
DW
5
5
DW
4
4
DW
3
3
DW
2
DW
1
DW
0
X
0
SI
S7
S6
S1
X
SO
Write to TXFIFO:
0
A5
S5
A4
S4
A3
S3
A2
S2
A1
S1
A0
S0
DW
S7
7
DW
6
DW
5
DW
4
DW
3
DW
2
DW
S1
DW
S0
X
DW
S7
DW
DW
DW
DW
DW
2
DW
1
DW
0
X
0
SI
S7
S6
S6
S5
S4
S3
S2
S6
S5
S4
S3
S2
S1
S0
S7
SO
Read from register / RXFIFO:
1
A5
S5
A4
S4
A3
S3
A2
S2
A1
S1
A0
S0
X
0
SI
S7
S6
DR15
DR14 DR13 DR12 DR11 DR10 DR
9
DR
8
DR
7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
DR15
SO
Read and write one byte to RAM: (multiple read / writes also possible)
A6
S6
A5
S5
A4
S4
A3
S3
A2
S2
A1
S1
A0
S0
X
B1
B0
0
X
X
X
X
X
X
X
X
X
DW
7
DW
6
DW
5
DW
4
DW
3
DW
2
DW
1
DW
0
X
7
SI
1
S7
X
DR
7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
DR
SO
Read one byte from RAM: (multiple reads also possible)
A6
S6
A5
S5
A4
S4
A3
S3
A2
S2
A1
S1
A0
S0
X
B1
B0
1
X
X
X
SI
1
S7
X
DR
7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
DR
7
SO
Figure 9. SPI timing diagram
Parameter
Symbol
FSCLK
tcl
Min
Max
Units
MHz
ns
Conditions
SCLK, clock
frequency
10
SCLKlow
pulse
duration
25
25
25
The minimum time SCLKmust be low.
SCLKhigh
pulse
duration
tch
ns
ns
The minimum time SCLKmust be high.
CSnsetup
tsp
The minimum time CSnmust be low before the first
time
positive edge of SCLK.
CSnhold time tns
25
25
ns
ns
The minimum time CSnmust be held low after the
last negative edge of SCLK.
SIsetup time tsd
The minimum time data on SImust be ready
before the positive edge of SCLK.
SIhold time
thd
25
ns
The minimum time data must be held at SI, after
the positive edge of SCLK.
Rise time
Fall time
trise
tfall
100
100
ns
ns
The maximum rise time for SCLKand CSn
The maximum fall time for SCLKand CSn
Note: The set-up- and hold-times refer to 50% of VDD.
Table 4. SPI timing specification
Issuing a SNOP (no operation) command
strobe may be used to read the status
byte. It may also be read during access to
chip functions such as register or FIFO
access.
13.3 Status byte
During transfer of the register access byte,
command strobes, the first RAM address
byte and data transfer to the TXFIFO, the
CC2420 status byte is returned on the SO
pin. The status byte contains 6 status bits
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CC2420
Bit #
Name
Description
7
6
-
Reserved, ignore value
XOSC16M_STABLE
Indicates whether the 16 MHz oscillator is running or not
0 : The 16 MHz crystal oscillator is not running
1 : The 16 MHz crystal oscillator is running
TX_UNDERFLOW
5
Indicates whether an FIFO underflow has occurred during
transmission. Must be cleared manually with a SFLUSHTX
command strobe.
0 : No underflow has occurred
1 : An underflow has occurred
ENC_BUSY
TX_ACTIVE
LOCK
4
3
2
1
Indicates whether the encryption module is busy
0 : Encryption module is idle
1 : Encryption module is busy
Indicates whether RF transmission is active
0 : RF Transmission is idle
1 : RF Transmission is active
Indicates whether the frequency synthesizer PLL is in lock or not
0 : The PLL is out of lock
1 : The PLL is in lock
RSSI_VALID
Indicates whether the RSSI value is valid or not.
0 : The RSSI value is not valid
1 : The RSSI value is valid, always true when reception has been
enabled at least 8 symbol periods (128 us)
0
-
Reserved, ignore value
Table 5. Status byte returned during address transfer and TXFIFO writing
written.
A
command strobe may be
13.4 Command strobes
followed by any other SPI access without
pulling CSn high, and is executed on the
last falling edge on SCLK.
Command strobes may be viewed as
single byte instructions to CC2420. By
addressing a command strobe register
internal sequences will be started. These
commands must be used to enable the
crystal oscillator, enable receive mode,
start decryption etc. All 15 command
13.5 RAM access
The internal 368 byte RAM may be
accessed through the SPI interface. Single
or multiple bytes may be read or written
sending the address part (2 bytes) only
once. The address is then automatically
incremented by the CC2420 hardware for
each new byte. Data is read and written
one byte at a time, unlike register access
where 2 bytes are always required after
each address byte.
When the crystal oscillator is disabled
(Power Down state in Figure 25 on page
may be used. All other command strobes
will be ignored and will have no effect. The
crystal oscillator must stabilise (see the
before other command strobes are
accepted.
The crystal oscillator must be running
when accessing the RAM.
The command strobe register is accessed
in the same way as for a register write
operation, but no data is transferred. That
is, only the RAM/Register bit (set to 0),
R/W bit (set to 0) and the 6 address bits
(in the range 0x00 through 0x0E) are
The RAM/Register bit must be set high to
enable RAM access. The 9 bit RAM
address consists of two parts, B1:0 (MSB)
selecting one of the three memory banks
and A6:0 (LSB) selecting the address
within the selected bank. The RAM is
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CC2420
divided into three memory banks: TXFIFO
(bank 0), RXFIFO (bank 1) and security
(bank 2). The FIFO banks are 128 bytes
each, while the security bank is 112 bytes.
For RAM read, the selected byte(s) are
output on the SO pin directly after the
second address byte.
See Figure 10 for an illustration on how
multiple RAM bytes may be read or written
in one operation.
A6:0 is transmitted directly after the
RAM/Register bit as shown in Figure 9.
For RAM access, a second byte is also
required before the data transfer. This
byte contains B1:0 in bits 7 and 6,
followed by the R/W bit (0 for read+write, 1
for read). Bits 4 through 0 are don’t care
The RAM memory space is shown in
Table 6. The lower 256 bytes are used to
store FIFO data. Note that RAM access
should never be used for FIFO write
operations because the FIFO counter will
not be updated. Use RXFIFO and TXFIFO
access instead as described in section
For RAM write, data to be written must be
input on the SI pin directly after the
second address byte. RAM data read is
output on the SO pin simultaneously, but
may be ignored by the user if only writing
is of interest.
As with register data, data stored in RAM
will be retained during power down mode,
but not when the power-supply is turned
off (e.g. by disabling the voltage regulator
using the VREG_ENpin).
CSn:
ADDR
Command strobe:
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
...
...
ADDR
ADDR
Multiple command strobes:
Read or write a whole register (16 bit):
Read 8 MSB of a register:
DATA8MSB DATA8LSB
DATA8MSB
DATA8MSB DATA8LSB
ADDR
DATA8MSB ...
ADDR
DATA8MSB DATA8LSB
Multiple register read or write
ADDRFIFO DATAbyte0 DATAbyte1 DATAbyte2 DATAbyte3
... DATAbyte n-3 DATAbyte n-2 DATAbyte n-1
Read or write n bytes from/to RF FIFO:
Read or write n bytes from/to RAM:
ADDRLRAM ADDRHRAM DATAADDR DATAADDR+1 DATAADDR+2 ...
DATAADDR+n
Note:
FIFO and RAM access must be terminated with setting the CSn pin high.
Command strobes and register access may be followed by any other access,
since they are completed on the last negative edge on SCLK. They may however also be
terminated with setting CSn high, if desirable, e.g. for reading only 8 bits from a configuration
register.
Figure 10. Configuration registers write and read operations via SPI
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CC2420
Address
Byte Ordering
Name
Description
0x16F –
0x16C
-
-
Not used
SHORTADR
PANID
0x16B –
0x16A
MSB
LSB
16-bit Short address, used for address recognition.
16-bit PAN identifier, used for address recognition.
0x169 –
0x168
MSB
LSB
IEEEADR
CBCSTATE
TXNONCE / TXCTR
KEY1
0x167 –
0x160
MSB
LSB
64-bit IEEE address of current node, used for address
recognition.
0x15F –
0x150
MSB
LSB
Temporary storage for CBC-MAC calculations
0x14F –
0x140
MSB (Flags)
LSB
Transmitter nonce for in-line authentication and
transmitter counter for in-line encryption.
0x13F –
0x130
MSB
LSB
Encryption key 1
SABUF
0x12F –
0x120
MSB
LSB
Stand-alone encryption buffer, for plaintext input and
ciphertext output
RXNONCE / RXCTR
KEY0
0x11F –
0x110
MSB (Flags)
LSB
Receiver nonce for in-line authentication or
receiver counter for in-line decryption.
0x10F –
0x100
MSB
LSB
Encryption key 0
RXFIFO
0x0FF –
0x080
MSB
LSB
128 bytes receive FIFO
128 bytes transmit FIFO
TXFIFO
0x07F –
0x000
MSB
LSB
Table 6. CC2420 RAM Memory Space
setting the CSn pin high once it has been
13.6 FIFO access
started.
The TXFIFO and RXFIFO may be
accessed through the TXFIFO (0x3E) and
RXFIFO (0x3F) registers.
The FIFO and FIFOP pins also provide
additional information on the data in the
receive FIFO, as will be described in the
The TXFIFO is write only, but may be read
back using RAM access as described in
the previous section. Data is read and
written one byte at a time, as with RAM
access. The RXFIFO is both writeable and
readable. Writing to the RXFIFO should
however only be done for debugging or for
using the RXFIFO for security operations
(decryption / authentication).
the FIFO and FIFOP pins only apply to
the RXFIFO. The TXFIFO has its
underflow flag in the status byte.
The TXFIFO may be flushed by issuing a
SFLUSHTX command strobe. Similarly, a
SFLUSHRX command strobe will flush the
receive FIFO.
The crystal oscillator must be running
when accessing the FIFOs.
13.7 Multiple SPI access
When writing to the TXFIFO, the status
This could be used to detect TXFIFO
underflow (see section RF Data Buffering
the TXFIFO.
Register access, command strobes, FIFO
access and RAM access may be issued
continuously without setting CSn high.
E.g. the user may issue a command
strobe, a register write and writing 3 bytes
to the TXFIFO in one operation, as
illustrated in Figure 11. The only exception
is that FIFO and RAM access must be
terminated by setting CSnhigh.
Multiple FIFO bytes may be accessed in
one operation, as with the RAM access.
FIFO access can only be terminated by
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CC2420
CSn
SI
SO
ADDR
Status
ADDR
Status
-
-
ADDRTXFIFO DATAADDR DATAADDR+1 DATAADDR+2
Status Status Status Status
DATA8MSB DATA8LSB
Command
Strobe
Register
Read
TXFIFO
Write
Figure 11. Multiple SPI Access Example
14 Microcontroller Interface and Pin Description
configuration interface (SI, SO, SCLK and
CSn). SOshould be connected to an input
at the microcontroller. SI, SCLK and CSn
When used in a typical system, CC2420 will
interface to microcontroller. This
microcontroller must be able to:
a
must
be
microcontroller
outputs.
Preferably the microcontroller should have
a hardware SPI interface.
• Program CC2420 into different modes,
read and write buffered data, and read
back status information via the 4-wire
SPI-bus configuration interface (SI, SO,
SCLKand CSn).
The microcontroller pins connected to SI,
SO and SCLK can be shared with other
SPI-interface devices. SO is
a
high
impedance output as long as CSn is not
activated (active low).
• Interface to the receive and transmit
FIFOs using the FIFO and FIFOP
status pins.
CSn should have an external pull-up
resistor or be set to a high level when the
voltage regulator is turned off in order to
prevent the input from floating. SI and
SCLK should be set to a defined level to
prevent the inputs from floating.
• Interface to the CCA pin for clear
channel assessment.
• Interface to the SFD pin for timing
information (particularly for beaconing
networks).
14.1 Configuration interface
A
CC2420 to microcontroller interface
microcontroller uses 4 I/O pins for the SPI
µC
CC2420
FIFO
FIFOP
CCA
GIO0
Interrupt
GIO1
SFD
Timer Capture
CSn
SI
GIO2
MOSI
MISO
SCLK
SO
SCLK
Figure 12. Microcontroller interface example
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CC2420
recognition. This may be handled by using
the FIFOP pin, since this pin does not go
active until the frame passes address
recognition.
14.2 Receive mode
In receive mode, the SFD pin goes active
after the start of frame delimiter (SFD)
field has been completely received. If
address recognition is disabled or is
successful, the SFD pin goes inactive
again only after the last byte of the MPDU
has been received. If the received frame
fails address recognition, the SFDpin goes
inactive immediately. This is illustrated in
Figure 14 shows an example of pin activity
when reading a packet from the RXFIFO.
In this example, the packet size is 8 bytes,
IOCFG0.FIFOP_THR
=
3
and
MODEMCTRL0.AUTOCRCis set. The length
will be 8 bytes, RSSI will contain the
average RSSI level during reception of the
packet and FCS/corr contains information
of FCS check result and the correlation
levels.
The FIFOpin is active when there are one
or more data bytes in the RXFIFO. The
first byte to be stored in the RXFIFO is the
length field of the received frame, i.e. the
FIFOpin goes active when the length field
is written to the RXFIFO. The FIFO pin
then remains active until the RXFIFO is
empty.
14.3 RXFIFO overflow
The RXFIFO can only contain a maximum
of 128 bytes at a given time. This may be
divided between multiple frames, as long
as the total number of bytes is 128 or less.
If an overflow occurs in the RXFIFO, this
is signalled to the microcontroller by
making the FIFOpin go inactive while the
FIFOP pin is active. Data already in the
RXFIFO will not be affected by the
overflow, i.e. frames already received may
be read out.
If
a
previously received frame is
completely or partially inside the RXFIFO,
the FIFO pin will remain active until the
RXFIFO is empty.
The FIFOPpin is active when the number
of unread bytes in the RXFIFO exceeds
A SFLUSHRX command strobe is required
after an RXFIFO overflow to enable
reception of new data. Note that the
SFLUSHRX command strobe should be
issued twice to ensure that the SFD pin
goes back to its inactive state.
the
threshold
programmed
into
IOCFG0.FIFOP_THR. When address
recognition is enabled the FIFOP pin will
remain inactive until the incoming frame
passes address recognition, even if the
number of bytes in the RXFIFO exceeds
the programmed threshold.
For security enabled frames, the MAC
layer must read the source address of the
received frame before it can decide which
key to use to decrypt or authenticate. This
data must therefore not be overwritten
even if it has been read out of the RXFIFO
The FIFOP pin will also go active when
the last byte of a new packet is received,
even if the threshold is not exceeded. If
so, the FIFOP pin will go inactive once
one byte has been read out of the
RXFIFO.
by
the
microcontroller.
If
the
SECCTRL0.RXFIFO_PROTECTIONcontrol
bit is set, CC2420 also protects the frame
header of security enabled frames until
decryption has been performed. If no MAC
security is used or if it is implemented
outside the CC2420, this bit may be cleared
to achieve optimal use of the RXFIFO.
When address recognition is enabled,
data should not be read out of the RXFIFO
before the address is completely received,
since the frame may be automatically
flushed by CC2420 if it fails address
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CC2420
Data received over RF
SFD Pin
Preamble
SFD Length
MAC Protocol Data Unit (MPDU) with correct address
Address
recognition OK
FIFO Pin
FIFOP Pin, if threshold
higher than frame length
FIFOP Pin, if threshold
lower than frame length
Data received over RF
Preamble
SFD Length
MAC Protocol Data Unit (MPDU) with wrong address
Address
recognition fails
SFD Pin
FIFO Pin
FIFOP Pin
Figure 13. Pin activity examples during receive
SCLK
SFD
CSn
SI
ADDRTXFIFO
Status
-
-
-
-
-
-
-
-
-
SO
Length
PSDU0
PSDU1
PSDU2
PSDU3
PSDU5
RSSI
PSDU4
FCS/Corr
FIFOP
FIFO
Figure 14. Example of pin activity when reading RXFIFO.
detected. See the RF Data Buffering
section on page 39 for more information
on TXFIFO underflow.
14.4 Transmit mode
During transmit the FIFOand FIFOPpins
are still only related to the RXFIFO. The
SFD pin is however active during
transmission of a data frame, as shown in
similarly during reception and transmission
of a data frame. If the SFD pins of the
transmitter and the receiver are compared
during the transmission of a data frame, a
small delay of approximately 2 µs can be
seen because of bandwidth limitations in
both the transmitter and the receiver.
The SFD pin goes active when the SFD
field has been completely transmitted. It
goes inactive again when the complete
MPDU (as defined by the length field) has
been transmitted or if an underflow is
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CC2420
Data transmitted
over RF
Preamble
SFD Length
MAC Protocol Data Unit (MPDU)
SFD Pin
CRC generated
by CC2420
12 symbol periods
Automatically generated
preamble and SFD
Data fetched
from TXFIFO
Figure 15. Pin activity example during transmit
received data frames. The SFDpin will go
active when a start of frame delimiter has
been completely detected / transmitted.
The SFD pin should preferably be
connected to a timer capture pin on the
microcontroller.
14.5 General control and status pins
In receive mode, the FIFOP pin can be
used to interrupt the microcontroller when
a threshold has been exceeded or a
complete frame has been received. This
pin should then be connected to a
microcontroller interrupt pin.
For debug purposes, the SFD and CCA
pins can be used to monitor several status
signals as selected by the IOCFG1
available signals.
In receive mode, the FIFO pin can be
used to detect if there is data at all in the
receive FIFO.
The SFD pin can be used to extract the
timing information of transmitted and
The polarity of FIFO, FIFOP, SFDand CCA
can be controlled by the IOCFG0 register
(address 0x1C).
15 Demodulator, Symbol Synchroniser and Data Decision
synchronisation is achieved by
a
continuous start of frame delimiter (SFD)
search.
The block diagram for the CC2420
demodulator is shown in Figure 16.
Channel filtering and frequency offset
compensation is performed digitally. The
signal level in the channel is estimated to
generate the RSSI level (see the RSSI /
more information). Data filtering is also
included for enhanced performance.
When a SFD is detected, data is written to
the RXFIFO and may be read out by the
microcontroller at a lower bit rate than the
250 kbps generated by the receiver.
The CC2420 demodulator also handles
With the ±40 ppm frequency accuracy
requirement from [1], a compliant receiver
must be able to compensate for up to 80
ppm or 200 kHz. The CC2420 demodulator
tolerates up to 300 kHz offset without
significant degradation of the receiver
performance.
symbol rate errors in excess of 120 ppm
without
Resynchronisation
performance
is
degradation.
performed
continuously to adjust for error in the
incoming symbol rate.
The RXCTRL1.RXBPF_LOCUR control bit
should be written to 1.
Soft decision is used at the chip level, i.e.
the demodulator does not make a decision
for each chip, only for each received
symbol. De-spreading is performed using
over sampled symbol correlators. Symbol
The MDMCTRL1.CORR_THR control bits
are by default set to 20 defining the
threshold for detecting IEEE 802.15.4 start
of frame delimiters.
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CC2420
Digital
IF Channel
Filtering
Frequency
Offset
Compensation
Digital
Data
Filtering
Symbol
Correlators and
Synchronisation
Data
Symbol
Output
I / Q Analog
IF signal
ADC
Average
Correlation
Value (may be
used for LQI)
RSSI
Generator
RSSI
Figure 16. Demodulator Simplified Block Diagram
16 Frame Format
Figure 17 [1] shows a schematic view of
the IEEE 802.15.4 frame format. Similar
figures describing specific frame formats
CC2420 has hardware support for parts of
the IEEE 802.15.4 frame format. This
section gives a brief summary to the IEEE
802.15.4 frame format, and describes how
CC2420 is set up to comply with this.
(data
frames,
beacon
frames,
acknowledgment frames and MAC
command frames) are included in [1].
Bytes:
2
1
Data
Sequence
Number
0 to 20
n
2
Frame
Control Field
(FCF)
Frame Check
Sequence
(FCS)
MAC Footer
(MFR)
MAC
Layer
Address
Information
Frame payload
MAC Payload
MAC Header (MHR)
Bytes:
4
1
1
5 + (0 to 20) + n
Start of frame
Delimiter
(SFD)
MAC Protocol
Data Unit
(MPDU)
PHY
Layer
Preamble
Sequence
Frame
Length
Synchronisation Header
PHY Header
(PHR)
PHY Service Data Unit
(SHR)
(PSDU)
11 + (0 to 20) + n
PHY Protocol Data Unit
(PPDU)
Figure 17. Schematic view of the IEEE 802.15.4 Frame Format [1]
The preamble sequence length can be set
16.1 Synchronisation header
by MDMCTRL0.PREAMBLE_LENGTH, while
the SFD is programmed in the SYNCWORD
register. SYNCWORDis 2 bytes long, which
gives the user some extra flexibility as
described below. Figure 18 shows how the
CC2420 synchronisation header relates to
the IEEE 802.15.4 specification.
The synchronisation header (SHR)
consists of the preamble sequence
followed by the start of frame delimiter
(SFD). In [1], the preamble sequence is
defined to be 4 bytes of 0x00. The SFD is
one byte, set to 0xA7.
In CC2420, the preamble length and SFD is
configurable. The default values are
compliant with [1]. Changing these values
will make the system non-compliant to
IEEE 802.15.4.
The programmable preamble length only
applies to transmission, it does not affect
receive mode. The preamble length
should not be set shorter than the default
value. Note that 2 of the 8 zero-symbols in
the preamble sequence required by [1] are
included in the SYNCWORD register so that
the CC2420 preamble sequence is only 6
symbols long for compliance with [1]. Two
A
synchronisation header is always
transmitted first in all transmit modes.
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CC2420
additional zero symbols in SYNCWORD
make CC2420 compliant with [1].
right) 0 7 A. If SYNCWORD = 0xA70F,
CC2420 will require the incoming symbol
sequence of (from left to right) 0 0 7 A. If
SYNCWORD = 0xA700, CC2420 will require
the incoming symbol sequence of (from
left to right) 0 0 0 7 A.
In reception, CC2420 synchronises to
received zero-symbols and searches for
the SFD sequence defined by the
SYNCWORD register. The least significant
symbols in SYNCWORD set to 0xF will be
ignored, while symbols different from 0xF
will be required for synchronisation. The
default setting of 0xA70F thereby requires
In receive mode CC2420 uses the
preamble
sequence
for
symbol
synchronisation and frequency offset
adjustments. The SFD is used for byte
synchronisation, and is not part of the data
stored in the receive buffer (RXFIFO).
one
additional
zero-symbol
for
synchronisation. This will reduce the
number of false frames detected due to
noise.
The following illustrates how the
programmed synch word is interpreted
during reception by CC2420: If SYNCWORD
=
0xA7FF, CC2420 will require the
incoming symbol sequence of (from left to
Synchronisation Header
Preamble
SFD
IEEE 802.15.4
0
0
0
0
0
0
0
0
7
A
CC2420
2·(PREAMBLE_LENGTH+ 1) zero symbols
SW0 SW1 SW2 SW3
Each box corresponds to 4 bits. Hence the preamble corresponds to 8 x 4 ''0' s or 4 bytes with the value 0.
SW0 = SYNCWORD[3:0] if different from 'F', else '0'
SW1 = SYNCWORD[7:4] if different from 'F', else '0'
SW2 = SYNCWORD[11:8] if different from 'F', else '0'
SW3 = SYNCWORD[15:12]if different from 'F', else '0'
Figure 18. Transmitted Synchronisation Header
must always be included. In transmit
mode, the length field is used for
16.2 Length field
underflow detection, as described in the
The frame length field shown in Figure 17
defines the number of bytes in the MPDU.
Note that the length field does not include
the length field itself. It does however
16.3 MAC protocol data unit
include
the
FCS
(Frame
Check
Sequence), even if this is inserted
automatically by CC2420 hardware. It also
includes the MIC if authentication is used.
The FCF, data sequence number and
address information follows the length field
as shown in Figure 17. Together with the
MAC data payload and Frame Check
Sequence, they form the MAC Protocol
Data Unit (MPDU).
The length field is 7 bits and has a
maximum value of 127. The most
significant bit in the length field is reserved
[1], and should be set to zero.
The format of the FCF is shown in Figure
19. Please refer to [1] for details.
CC2420 uses the length field both for
transmission and reception, so this field
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CC2420
There is no hardware support for the data
sequence number, this field must be
inserted and verified by software.
CC2420 includes hardware address
recognition, as described in the Address
Bits: 0-2
3
4
5
6
7-9
10-11
12-13
14-15
Frame
Type
Security
Enabled
Frame
Pending
Acknowledge
request
Intra
PAN
Reserved
Destination
addressing
mode
Reserved
Source
addressing
mode
Figure 19. Format of the Frame Control Field (FCF) [1]
interested in the correctness of the FCS,
not the FCS sequence itself. The FCS
sequence itself is therefore not written to
the RXFIFO during receive.
16.4 Frame check sequence
A 2-byte frame check sequence (FCS)
follows the last MAC payload byte as
shown in Figure 17. The FCS is calculated
over the MPDU, i.e. the length field is not
part of the FCS. This field is automatically
generated and verified by hardware when
the MODEMCTRL0.AUTOCRC control bit is
set. It is recommended to always have this
enabled, except possibly for debug
purposes. If cleared, CRC generation and
verification must be performed by
software.
Instead, when MODEMCTRL0.AUTOCRC is
set the two FCS bytes are replaced by the
RSSI value, average correlation value
(used for LQI) and CRC OK/not OK. This
The first FCS byte is replaced by the 8-bit
RSSI value. This RSSI value is measured
over the first 8 symbols following the SFD.
details.
The FCS polynomial is [1]:
x16 + x12 + x5 + 1
The 7 least significant bits in the last FCS
byte are replaced by the average
correlation value of the 8 first symbols of
the received PHY header (length field) and
PHY Service Data Unit (PSDU). This
correlation value may be used as a basis
for calculating the LQI. See the Link
details.
The CC2420 hardware implementation is
shown in Figure 20. Please refer to [1] for
further details.
In transmit mode the FCS is appended at
the correct position defined by the length
field. The FCS is not written to the
TXFIFO, but stored in a separate 16-bit
register.
The most significant bit in the last byte of
each frame is set high if the CRC of the
received frame is correct and low
otherwise.
In receive mode the FCS is verified by
hardware. The user is normally only
Data
input
(LSB
first)
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12 r13
r14
r15
Figure 20. CC2420 Frame Check Sequence (FCS) hardware implementation [1]
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CC2420
Length byte
n
MPDU
RSSI
(signed)
Data in RXFIFO
MPDU1
MPDU2
MPDUn-2
CRC / Corr
Bit number
7
6
5
4
3
2
1
0
CRC
OK
Correlation value (unsigned)
Figure 21. Data in RXFIFO when MDMCTRL0.AUTOCRCis set
17 RF Data Buffering
A TXFIFO underflow is issued if too few
bytes are written to the TXFIFO.
Transmission is then automatically
stopped. The underflow is indicated in the
TX_UNDERFLOW status bit, which is
returned during each address byte and
each byte written to the TXFIFO. The
underflow bit is only cleared by issuing a
SFLUSHTXcommand strobe.
CC2420 can be configured for different
transmit and receive modes, as set in the
MDMCTRL1.TX_MODE
and
MDMCTRL1.RX_MODE
control
bits.
Buffered mode (mode 0) will be used for
normal operation of CC2420, while other
modes are available for test purposes.
17.1 Buffered transmit mode
The TXFIFO can only contain one data
frame at a given time.
In buffered transmit mode (TX_MODE 0),
the 128 byte TXFIFO, located in CC2420
RAM, is used to buffer data before
After complete transmission of a data
frame, the TXFIFO is automatically refilled
with the last transmitted frame. Issuing a
new STXON or STXONCCA command
strobe will then cause CC2420 to retransmit
the last frame.
transmission.
A
preamble sequence
(defined in the Frame Format section
below) is automatically inserted before the
length field during transmission. The
length field must always be the first byte
written to the transmit buffer for all frames.
Writing to the TXFIFO after a frame has
been transmitted will cause the TXFIFO to
be automatically flushed before the new
byte is written. The only exception is if a
TXFIFO underflow has occurred, then a
SFLUSHTXcommand strobe is required.
Writing one or multiple bytes to the
TXFIFO is described in the FIFO access
TXFIFO is possible with RAM access, but
this does not remove the byte from the
FIFO.
Transmission is enabled by issuing a
STXON or STXONCCA command strobe.
how the transmit command strobes affect
the state of CC2420. The STXONCCAstrobe
is ignored if the channel is busy. See the
17.2 Buffered receive mode
In buffered receive mode (RX_MODE 0),
the 128 byte RXFIFO, located in CC2420
RAM, is used to buffer data received by
the demodulator. Accessing data in the
The FIFO and FIFOP pins are used to
assist the microcontroller in supervising
the RXFIFO. Please note that the FIFO
and FIFOP pins are only related to the
RXFIFO, even if CC2420 is in transmit
mode.
The preamble sequence is started 12
symbol periods after the command strobe.
After the programmable start of frame
delimiter has been transmitted, data is
fetched from the TXFIFO.
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CC2420
Multiple data frames may be in the
RXFIFO simultaneously, as long as the
total number of bytes does not exceed
128.
In
serial
transmit
mode
(MDMCTRL1.TX_MODE=1),
a
synchronisation sequence is inserted at
the start of each frame by hardware, as in
buffered mode. Data is sampled by CC2420
on the positive edge of FIFOPand should
be updated by the microcontroller on the
an illustration of the timing in serial
transmit mode. The SFD and CCA pins
retain their normal operation also in serial
mode. CC2420 will remain in serial transmit
mode until transmission is turned off
manually.
33 for details on how a RXFIFO overflow
is detected and signalled.
17.3 Unbuffered, serial mode
Unbuffered mode should be used for
evaluation / debugging purposes only.
Buffered mode is recommended for all
applications.
In
serial
receive
mode
byte
In unbuffered mode, the FIFOand FIFOP
pins are reconfigured as data and data
clock pins. The TXFIFO and RXFIFO
buffers are not used in this mode. A
synchronous data clock is provided by
CC2420 at the FIFOP pin, and the FIFO
pin is used as data input/output. The
FIFOP clock frequency is 250 kHz when
(MDMCTRL1.RX_MODE=1)
synchronisation is still performed by
CC2420. This means that the FIFOP clock
pin will remain inactive until a start of
frame delimiter has been detected.
Incoming / outgoing
Preamble
SFD
4 us
s0
s1
s2
RF data
Transmit mode:
FIFOP
FIFO (from uC)
b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b8 b9 b10 b11
Receive mode:
FIFOP
FIFO (from CC2420)
b0 b1 b2 b3 b4
Figure 22. Unbuffered test mode, pin activity
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CC2420
18 Address Recognition
PAN
macPANId.
identifier
matches
CC2420 includes hardware support for
address recognition, as specified in [1].
Hardware address recognition may be
If any of the above requirements are not
satisfied and address recognition is
enabled, CC2420 will disregard the
incoming frame and flush the data from
the RXFIFO. Only data from the rejected
frame is flushed, data from previously
accepted frames may still be in the
RXFIFO.
enabled
/
disabled
using
the
MDMCTRL0.ADR_DECODEcontrol bit.
Address recognition is based on the
following requirements, listed from section
7.5.6.2 in [1]:
•
•
The frame type subfield shall not
contain an illegal frame type
The IOCFG0.BCN_ACCEPT control bit
must be set when the PAN identifier
programmed into CC2420 RAM is equal to
0xFFFF and cleared otherwise. This
particularly applies to active and passive
scans as defined by [1], which requires all
received beacons to be processed by the
MAC sublayer.
If the frame type indicates that the
frame is a beacon frame, the
source PAN identifier shall match
macPANId unless macPANId is
equal to 0xFFFF, in which case
the beacon frame shall be
accepted regardless of the source
PAN identifier.
Incoming frames with reserved frame
types (FCF frame type subfield is 4, 5, 6 or
•
•
If a destination PAN identifier is
included in the frame, it shall
match macPANId or shall be the
7)
is
however
accepted
if
the
RESERVED_FRAME_MODE control bit in
MDMCTRL0 is set. In this case, no further
address recognition is performed on these
frames. This option is included for future
expansions of the IEEE 802.15.4
standard.
broadcast
(0xFFFF).
PAN
identifier
If a short destination address is
included in the frame, it shall
match either macShortAddress or
the broadcast address (0xFFFF).
If a frame is rejected, CC2420 will only start
searching for a new frame after the
rejected frame has been completely
received (as defined by the length field) to
avoid detecting false SFDs within the
frame.
Otherwise
if
an
extended
destination address is included in
the frame, it shall match
aExtendedAddress.
•
If only source addressing fields
are included in a data or MAC
command frame, the frame shall
only be accepted if the device is a
PAN coordinator and the source
The
MDMCTRL0.PAN_COORDINATOR
control bit must be correctly set, since
parts of the address recognition procedure
requires knowledge about whether the
current device is a PAN coordinator or not.
19 Acknowledge Frames
recognition with the acknowledge request
flag set and a valid CRC. AUTOACK
therefore does not make sense unless
also ADR_DECODE and AUTOCRC are
enabled. The sequence number is copied
from the incoming frame.
CC2420 includes hardware support for
transmitting acknowledge frames, as
format of the acknowledge frame.
If MDMCTRL0.AUTOACK is enabled, an
acknowledge frame is transmitted for all
incoming frames accepted by the address
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CC2420
AUTOACK may be used for non-beacon
systems as long as the frame pending
acknowledge frame is then transmitted 12
symbol periods after the last symbol of the
incoming frame. This is as specified by [1]
for non-beacon networks.
Bytes:
4
1
1
2
1
2
Start of Frame
Delimiter
(SFD)
Frame
Control Field
(FCF)
Data
Sequence
Number
Frame Check
Sequence
(FCS)
Preamble
Sequence
Frame
Length
Synchronisation Header
PHY Header
(PHR)
MAC Header (MHR)
MAC Footer
(MFR)
(SHR)
Figure 23. Acknowledge frame format [1]
Two command strobes, SACK and
SACKPEND are defined to transmit
acknowledge frames with the frame
pending field cleared or set, respectively.
If a SACK or SACKPEND command strobe
is issued while receiving an incoming
frame, the acknowledge frame is
transmitted 12 symbol periods after the
last symbol of the incoming frame. This
should be used to transmit acknowledge
frames in non-beacon networks. This
The
acknowledge
frame
is
only
transmitted if the CRC is valid.
For systems using beacons, there is an
additional timing requirement that the
acknowledge frame transmission should
be started on the first backoff-slot
boundary (20 symbol periods) at least 12
symbol periods after the last symbol of the
incoming frame. This timing must be
controlled by the microcontroller by issuing
the SACKand SACKPENDcommand strobe
12 symbol periods before the following
backoff-slot boundary, as illustrated in
Using SACKPENDwill set the pending data
flag
for
automatically
transmitted
acknowledge frames using AUTOACK. The
pending flag will then be set also for future
acknowledge frames, until a SACK
command strobe is issued.
Acknowledge frames may be manually
transmitted
using
normal
data
transmission if desired.
Beacon
PPDU
Acknowledge
12
network
symbol
periods
tack
12 symbol periods <=
< 32 symbol periods
Non-beacon
network
PPDU
Acknowledge
= 12 symbol periods
tack
Figure 24. Acknowledge frame timing
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CC2420
20 Radio control state machine
For test purposes, the frequency
synthesizer (FS) can also be manually
calibrated and started by using the
STXCAL command strobe register. This
will not start a transmission before a
STXON command strobe is issued. This is
CC2420 has a built-in state machine that is
used to switch between different
operational states (modes). The change of
state is done either by using command
strobes or by internal events such as SFD
detected in receive mode.
The radio control state machine states are
shown in Figure 25. The numbers in
brackets refer to the state number
readable in the FSMSTATEstatus register.
Reading the FSMSTATE status register is
primarily for test / debug purposes.
Enabling transmission is done by issuing a
STXONor STXONCCAcommand strobe.
Turning off RF can be accomplished by
using one of the SRFOFF or SXOSCOFF
command strobe registers.
Before using the radio in either RX or TX
mode, the voltage regulator and crystal
oscillator must be turned on and become
stable. The voltage regulator and crystal
oscillator start-up times are given in the
After reset the CC2420 is in Power Down
mode. All configuration registers can then
be programmed in order to make the chip
ready to operate at the correct frequency
and mode. Due to the very fast start-up
time, CC2420 can remain in Power Down
until a transmission session is requested.
The crystal oscillator is controlled by
accessing the SXOSCON / SXOSCOFF
command strobes. The XOSC16M_STABLE
bit in the status register returned during
address transfer indicates whether the
oscillator is running and stable or not (see
Table 5). This status register can be polled
when waiting for the oscillator to start.
As also described in the 4-wire Serial
Configuration and Data Interface section
running (IDLE) in order to have access to
the RAM and FIFOs.
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CC2420
Voltage Regulator Off
VREG_ENset low
VREG_ENset high
Wait until voltage regulator
has powered up
Chip Reset
(pin or register)
SXOSCOFF
Crystal oscillator disabled,
register access enabled,
FIFO / RAM access disabled
command strobe
Power Down (PD)
[0]
All States
SXOSCON
Wait for the specified crystal oscillator
start-up time, or poll the
XOSC16M_STABLE status bit
SRFOFF
All States
except Power Down (PD)
IDLE
[1]
All RX states
RX_CALIBRATE
[2 and 40]
TX_CALIBRATE
[32]
12 symbol periods
later
8 or 12 symbol
periods later
RX_SFD_SEARCH
[3, 4, 5 and 6]
TX_PREAMBLE
[34, 35 and 36]
Preamble and SFD
is transmitted
SFD
Frame received or
failed address
recognition
found
RX_WAIT
[14]
RX_FRAME
[16 and 40]
TX_FRAME
[37, 38 and 39]
TXFIFO Data
is transmitted
Automatic or manual
acknowledge request
Underflow
RX_OVERFLOW
[17]
TX_ACK_CALIBRATE
[48]
TX_UNDERFLOW
[56]
The transition from
12 symbol
TX_UNDERFLOW to
periods later
RX_CALIBRATE is automatic,
but SFLUSHTXmust be used to
reset underflow indication
TX_ACK_PREAMBLE
[49, 50 and 51]
Acknowledge
completed
TX_ACK
[52, 53 and 54]
Figure 25. Radio control states
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CC2420
21 MAC Security Operations (Encryption and Authentication)
KEY0 is located from address 0x100 and
KEY1 from address 0x130.
CC2420 features hardware IEEE 802.15.4
MAC security operations. This includes
counter mode (CTR) encryption
/
decryption, CBC-MAC authentication and
CCM encryption + authentication. All
security operations are based on AES
encryption [2] using 128 bit keys. Security
operations are performed within the
transmit and receive FIFOs on a frame
basis.
A way of establishing the keys used for
encryption and authentication must be
decided for each particular application.
IEEE 802.15.4 does not define how this is
done, it is left to the higher layer of the
protocol.
ZigBee
uses
an
Elliptic
Curve
CC2420 also includes stand-alone AES
encryption, in which one 128 bit plaintext
is encrypted to a 128 bit ciphertext.
Cryptography (ECC) based approach to
establish keys. For PC based solutions,
more processor intensive solutions such
as Diffie-Hellman may be chosen. Some
The SAES, STXENC and SRXDEC
command strobes are used to start
security operations in CC2420 as will be
described in the following sections. The
used to monitor when a security operation
has been completed. Security command
strobes issued while the security engine is
busy will be ignored, and the ongoing
operation will be completed.
applications
may
also
use
pre-
programmed keys, e.g. for remote keyless
entry where the key and lock are delivered
in pairs. A push-button approach for
loading keys may also be selected.
21.2 Nonce / counter
The receive and transmit nonces used for
encryption / decryption are located in RAM
from addresses 0x110 and 0x140
respectively. They are both 16 bytes.
Table 6 on page 31 shows the CC2420
RAM memory map, including the security
related data located from addresses
0x100 through 0x15F. RAM access (see
used to write or read the keys, nonces and
stand-alone buffer. All security related
data is stored little-endian, i.e. the least
significant byte is transferred first over the
SPI interface during RAM read or write
operations.
The nonce must be correctly initialized
before receive or transmit CTR or CCM
operations are started. The format of the
counter must be set to 1 for compliance
with [1]. The key sequence counter is
controlled by a layer above the MAC layer.
The frame counter must be increased for
each new frame by the MAC layer. The
source address is the 64 bit IEEE address.
For
a
complete description of IEEE
802.15.4 MAC security operations, please
refer to [1].
1 byte 8 bytes
4 bytes
1 byte
2 bytes
Flags
Source
Frame
Key
Block
Address
Counter
Sequence
Counter
Counter
21.1 Keys
All security operations are based on 128
bit keys. The CC2420 RAM space has
storage space for two individual keys
(KEY0 and KEY1). Transmit, receive and
stand-alone encryption may select one of
these two keys individually in the
SEC_TXKEYSEL, SEC_RXKEYSEL and
SEC_SAKEYSELcontrol bits (SECCTRL0).
Table 7. IEEE 802.15.4 Nonce [1]
The block counter bytes are not updated
in RAM, only in a local copy that is
reloaded for each new in-line security
operation. I.e. the block counter part of the
nonce does not need to be rewritten. The
CC2420 block counter should be set to
0x0001 for compliance with [1].
CC2420 gives the user full flexibility in
selecting the flags for both nonces. The
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CC2420
flag setting is stored in the most significant
byte of the nonce. The flag byte used for
encryption and authentication is then
The frame counter part of the nonce must
be incremented for each new packet by
software.
MSB in CC2420 nonce RAM
7
-
6
5
4
3
2
1
L
0
CTR Flag
bits 7:6
CBC Flag
bits 7:6
SECCTRL0.SEC_M
CTR mode flag byte
CBC-MAC flag byte
7
6
5
0
4
3
2
1
L
0
7
6
5
4
3
2
1
L
0
Res
Res
0
0
Res Adata
M
Figure 26. CC2420 Security Flag Byte
The key, nonce (does not apply to CBC-
MAC), and SECCTRL0 and SECCTRL1
control registers must be correctly set
before starting any in-line security
operation.
21.3 Stand-alone encryption
Plain AES encryption, with 128 bit
plaintext and 128 bit keys [2], is available
using
stand-alone
encryption.
The
plaintext is stored in stand-alone buffer
located at RAM location 0x120, as can be
The in-line security mode is set in
SECCTRL0.SEC_MODE to one of the
following modes:
A stand-alone encryption operation is
initiated by using the SAES command
•
•
•
•
Disabled
strobe.
The
selected
key
CBC-MAC (authentication)
CTR (encryption / decryption)
CCM (authentication and encryption /
decryption)
(SECCTRL0.SEC_SAKEYSEL) is then used
to encrypt the plaintext written to the
stand-alone buffer. Upon completion of the
encryption operation, the ciphertext is
written back to the stand-alone buffer,
thereby overwriting the plaintext.
When enabled, TX in-line security is
started in one of two ways:
Note that RAM write operations also
output data currently in RAM, so that a
new plaintext may be written at the same
time as reading out the previous
ciphertext.
•
Issue a STXENC command strobe. In-
line security will be performed within
the TXFIFO, but a RF transmission
will not be started. Ciphertext may be
read back using RAM read operations.
Issue a STXON or STXONCCA
command strobe. In-line security will
be performed within the TXFIFO and a
RF transmission of the ciphertext is
started.
•
21.4 In-line security operations
CC2420 can do MAC security operations
(encryption, decryption and authentication)
on frames within the TXFIFO and
RXFIFO. These operations are called in-
line security operations.
When enabled, RX in-line security is
started as follows:
As with other MAC hardware support
within CC2420, in-line security operation
relies on the length field in the PHY
•
Issue a SRXDECcommand strobe. The
first frame in the RXFIFO is then
decrypted / authenticated as set by
the current security mode.
header.
A
correct length field must
therefore be used for all security
operations.
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CC2420
RX in-line security operations are always
performed on the first frame currently
inside the RXFIFO, even if parts of this
have already been read out over the SPI
interface. This allows the receiver to first
read the source address out to decide
which key to use before doing
authentication of the complete frame. In
CTR or CCM mode it is of course
important that bytes to be decrypted are
not read out before the security operation
is started.
of the RXFIFO is then decrypted as
specified by [1].
21.6 CBC-MAC
CBC-MAC
in-line
authentication
is
provided by CC2420 hardware.
SECCTRL0.SEC_Msets the MIC length M,
encoded as (M-2)/2.
When enabling CBC-MAC in-line TXFIFO
authentication, the generated MIC is
written to the TXFIFO for transmission.
The frame length must include the MIC.
When the SRXDEC command strobe is
issued, the FIFO and FIFOP pins will go
inactive. This is to indicate to the
microcontroller that no further data may be
read out before the next byte to be read
has undergone the requested security
operation.
SECCTRL1.SEC_TXL / SEC_RXL sets the
number of bytes between the length field
and the first byte to be authenticated,
normally set to 0 for MAC authentication.
The frame in the RXFIFO may be received
over RF or it may be written into the
RXFIFO over the SPI interface for
debugging or higher layer security
operations.
SECCTRL0.SEC_CBC_HEAD defines if the
authentication length is used as the first
byte of data to be authenticated or not.
This bit should be set for compliance with
[1].
When enabling CBC-MAC in-line RXFIFO
authentication, the generated MIC is
compared to the MIC in the RXFIFO. The
last byte of the MIC is replaced in the
RXFIFO with:
21.5 CTR
mode
encryption
/
decryption
CTR mode encryption / decryption is
performed by CC2420 on MAC frames
within the TXFIFO / RXFIFO respectively.
•
•
0x00 if the MIC is correct
0xFF if the MIC is incorrect
SECCTRL1.SEC_TXL / SEC_RXL sets the
number of bytes between the length field
and the first byte to be encrypted /
decrypted respectively. This controls the
number of plaintext bytes in the current
The other bytes in the MIC are left
unchanged in the RXFIFO.
frame.
For
IEEE
802.15.4
MAC
encryption, only the MAC payload (see
encrypted, so SEC_TXL / SEC_RXL is set
to 3 + (0 to 20) depending on the address
information in the current frame.
21.7 CCM
CCM combines CTR mode encryption and
CBC-MAC authentication in one operation.
CCM is described in [3].
When encryption is initiated, the plaintext
in the TXFIFO is then encrypted as
specified by [1]. The encryption module
will encrypt all the plaintext currently
available, and wait if not everything is pre-
buffered. The encryption operation may
also be started without any data in the
TXFIFO at all, and data will be encrypted
as it is written to the TXFIFO.
SECCTRL1.SEC_TXL / SEC_RXL sets the
number of bytes after the length field to be
authenticated but not encrypted.
The MIC is generated and verified very
much like with CBC-MAC described
above. The only differences are from the
requirements in [1] for CCM.
When decryption is initiated with
a
SRXDEC command strobe, the ciphertext
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CC2420
used by the security module for different
operations.
21.8 Timing
Mode
l(a)
l(m)
l(MIC)
Time
[us]
CCM
CTR
CBC
50
-
69
15
98
16
8
-
222
99
17
-
12
-
99
Stand-
alone
14
Table 8. Security timing examples
22 Linear IF and AGC Settings
dynamic range by using an analog/digital
feedback loop.
CC2420 is based on a linear IF chain
where the signal amplification is done in
an analog VGA (variable gain amplifier).
The gain of the VGA is digitally controlled.
The AGC characteristics are set through
the AGCCTRL, AGCTST0, AGCTST1 and
AGCTST2 registers. The reset values
should be used for all AGC control and
test registers.
The AGC (Automatic Gain Control) loop
ensures that the ADC operates inside its
23 RSSI / Energy Detection
of –20 from the RSSI register, the RF
input power is approximately –65 dBm.
CC2420 has a built-in RSSI (Received
Signal Strength Indicator) providing a
digital value that can be read from the 8
bit,
signed
2’s
complement
A typical plot of the RSSI_VALreading as
function of input power is shown in Figure
27. It can be seen from the figure that the
RSSI reading from CC2420 is very linear
and has a dynamic range of about 100 dB.
RSSI.RSSI_VALregister.
The RSSI value is always averaged over 8
symbol periods (128 µs), in accordance
with [1]. The RSSI_VALID status bit
valid, meaning that the receiver has been
enabled for at least 8 symbol periods.
The RSSI register value RSSI.RSSI_VAL
is calculated and continuously updated for
each symbol after RSSI has become valid.
The RSSI register value RSSI.RSSI_VAL
can be referred to the power P at the RF
pins by using the following equations:
P = RSSI_VAL+ RSSI_OFFSET[dBm]
where the RSSI_OFFSET is found
empirically during system development
from the front end gain. RSSI_OFFSET is
approximately –45. E.g. if reading a value
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CC2420
60
40
20
0
-100
-80
-60
-40
-20
0
-20
-40
-60
RF Level [dBm]
Figure 27. Typical RSSI value vs. input power
24 Link Quality Indication
The
link
quality
indication
(LQI)
As described in the Frame check
sequence section on page 38, the average
correlation value for the 8 first symbols is
appended to each received frame together
with the RSSI and CRC OK/not OK when
MDMCTRL0.AUTOCRC is set. A correlation
value of ~110 indicates a maximum quality
frame while a value of ~50 is typically the
lowest quality frames detectable by
CC2420.
measurement is a characterisation of the
strength and/or quality of a received
packet, as defined by [1].
The RSSI value described in the previous
section may be used by the MAC software
to produce the LQI value. The LQI value is
required by [1] to be limited to the range 0
through 255, with at least 8 unique values.
Software is responsible for generating the
appropriate scaling of the LQI value for the
given application.
Software must convert the correlation
value to the range 0-255 defined by [1],
e.g. by calculating:
Using the RSSI value directly to calculate
the LQI value has the disadvantage that
e.g. a narrowband interferer inside the
channel bandwidth will increase the LQI
value although it actually reduces the true
link quality. CC2420 therefore also provides
an average correlation value for each
incoming packet, based on the 8 first
symbols following the SFD. This unsigned
7-bit value can be looked upon as a
measurement of the “chip error rate,”
although CC2420 does not do chip
decision.
LQI = (CORR – a) · b
limited to the range 0-255, where a and b
are found empirically based on PER
measurements as
correlation value.
a
function of the
A combination of RSSI and correlation
values may also be used to generate the
LQI value.
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CC2420
25 Clear Channel Assessment
The clear channel assessment signal is
based on the measured RSSI value and a
programmable threshold. The clear
channel assessment function is used to
implement the CSMA-CA functionality
specified in [1]. CCA is valid when the
receiver has been enabled for at least 8
symbol periods.
0
1
Reserved
Clear channel when received energy is below
threshold.
2
3
Clear channel when not receiving valid IEEE
802.15.4 data.
Clear channel when energy is below threshold
and not receiving valid IEEE 802.15.4 data
Carrier
sense
threshold
level
is
Clear channel assessment is available on
the CCAoutput pin. CCAis active high, but
the polarity may be changed by setting the
IOCFG0.CCA_POLARITYcontrol bit.
programmed by RSSI.CCA_THR. The
threshold value can be programmed in
steps of 1 dB. A CCA hysteresis can also
be
programmed
in
the
MDMCTRL0.CCA_HYSTcontrol bits.
Implementing CSMA-CA may easiest be
done by using the STXONCCA command
strobe, as described in the Radio control
state machine section on page 43.
Transmission will then only start if the
channel is clear. The TX_ACTIVE status
bit (see Table 5) may be used to detect
the result of the CCA.
All 3 CCA modes specified by [1] are
implemented in CC2420. They are set in
MDMCTRL0.CCA_MODE, as can be seen in
the register description. The different
modes are:
26 Frequency and Channel Programming
The operating frequency is set by
programming the 10 bit frequency word
located in FSCTRL.FREQ[9:0]. The
operating frequency FC in MHz is given by:
IEEE 802.15.4 specifies 16 channels
within the 2.4 GHz band, in 5 MHz steps,
numbered 11 through 26. The RF
frequency of channel k is given by [1]:
FC = 2405 + 5 (k-11) MHz, k=11, 12, ..., 26
FC = 2048 + FSCTRL.FREQ[9:0]MHz
For operation in channel k, the
FSCTRL.FREQ register should therefore
be set to:
The frequency can be programmed with 1
MHz resolution. In receive mode the
actual LO frequency is FC – 2 MHz, since
a 2 MHz IF is used. Direct conversion is
used for transmission, so here the LO
frequency equals FC. The 2 MHz IF is
automatically set by CC2420, so the
frequency programming is equal for RX
and TX.
FSCTRL.FREQ= 357 + 5 (k-11)
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CC2420
27 VCO and PLL Self-Calibration
In order to ensure reliable operation the
VCO’s bias current and tuning range are
automatically calibrated every time the RX
mode or TX mode is enabled, i.e. in the
RX_CALIBRATE, TX_CALIBRATE and
TX_ACK_CALIBRATE control states in
27.1 VCO
The VCO is completely integrated and
operates at 4800 – 4966 MHz. The VCO
frequency is divided by 2 to generate
frequencies in the desired band (2400-
2483.5 MHz).
27.2 PLL self-calibration
The VCO's characteristics will vary with
temperature, changes in supply voltages,
and the desired operating frequency.
28 Output Power Programming
The RF output power of the device is
programmable and is controlled by the
settings,
including
the
complete
programming of the TXCTRL control
register. The typical current consumption
is also shown.
TXCTRL.PA_LEVEL register. Table
shows the output power for different
PA_LEVEL
TXCTRLregister
0xA0FF
Output Power [dBm]
Current Consumption [mA]
31
27
23
19
15
11
7
0
17.4
16.5
15.2
13.9
12.5
11.2
9.9
0xA0FB
-1
0xA0F7
-3
0xA0F3
-5
0xA0EF
-7
0xA0EB
0xA0E7
-10
-15
-25
3
0xA0E3
8.5
Table 9. Output power settings and typical current consumption @ 2.45 GHz
29 Voltage Regulator
available on the VREG_OUT pin.
simplified schematic of the voltage
A
CC2420 includes a low drop-out voltage
regulator. This is used to provide a 1.8 V
power supply to the CC2420 power
supplies. The voltage regulator should not
be used to provide power to other circuits
because of limited power sourcing
capability and noise considerations.
The voltage regulator requires external
components as described in the
When disabling the voltage regulator, note
that register and RAM programming will
be lost as leakage current reduces the
output voltage on the VREG_OUTpin below
1.6 V. CC2420 should then be reset before
the voltage regulator is disabled.
The voltage regulator input pin VREG_IN
is connected to the unregulated 2.1 to 3.6
V power supply. The voltage regulator is
enabled / disabled using the active high
voltage regulator enable pin VREG_EN.
The regulated 1.8 V voltage output is
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CC2420
In applications where the internal voltage
regulator is not used, connect VREG_EN
and VREG_IN to ground. VREG_OUT shall
be left open. Note that the battery monitor
will not work when the voltage regulator is
not used.
VREG_EN
VREG_IN
Regulator
Enable / disable
Internal
bandgap
voltage
1.25 V
reference
VREG_OUT
Figure 28. Voltage regulator, simplified schematic
30 Battery Monitor
The on-chip battery monitor enables
monitoring the unregulated voltage on the
VREG_IN pin. It gives status information
programmable threshold.
schematic of the battery monitor is shown
A
simplified
on the voltage being above or below a
BATTMON.BATTMON_EN
VREG_IN
Internal
bandgap
voltage
1.25 V
BATTMON.BATTMON_OK
reference
BATTMON.BATTMON_VOLTAGE[4:0]
Figure 29. Battery monitor, simplified schematic
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CC2420
The battery monitor is controlled through
the BATTMON control register. The battery
monitor is enabled and disabled using the
BATTMON.BATTMON_EN control bit. The
voltage regulator must also be enabled
when using the battery monitor.
Alternatively, for a desired toggle voltage,
BATTMON_VOLTAGE
should
be
set
according to:
BATTMON_VOLTAGE= 72 − 27 ⋅ Vtoggle
1.25V
The battery monitor status bit is available
in the BATTMON.BATTMON_OK status bit.
This bit is high when the VREG_IN input
voltage is higher than the toggle voltage
The voltage regulator must be enabled for
at least 100 µs before the first
measurement. After being enabled, the
BATTMON_OK status bit needs 2 µs to
settle for each new toggle voltage
programmed.
Vtoggle
.
The battery monitor toggle voltage is set in
the 5-bit BATTMON.BATTMON_VOLTAGE
control bits. BATTMON_VOLTAGE is an
unsigned, positive number from 0 to 31.
The toggle voltage is given by:
The main performance characteristics of
the battery monitor is shown in the
72 − BATTMON_VOLTAGE
= 1.25V⋅
Vtoggle
27
31 Crystal Oscillator
An external clock signal or the internal
crystal oscillator can be used as main
frequency reference. The reference
frequency must be 16 MHz. Because the
crystal frequency is used as reference for
the data rate as well as other internal
1
CL =
+ Cparasitic
1
1
+
C381 C391
The parasitic capacitance is constituted by
pin input capacitance and PCB stray
capacitance.
signal
processing
functions,
other
frequencies cannot be used.
The
total
parasitic
capacitance is typically 2 pF - 5 pF.
If an external clock signal is used this
should be connected to XOSC16_Q1, while
XOSC16_Q2 should be left open. The
MAIN.XOSC16M_BYPASS bit must be set
when an external clock signal is used.
The crystal oscillator circuit is shown in
Using the internal crystal oscillator, the
crystal must be connected between the
XOSC16_Q1 and XOSC16_Q2 pins. The
oscillator is designed for parallel mode
operation of the crystal. In addition,
loading capacitors (C381 and C391) for the
crystal are required. The loading capacitor
values depend on the total load
capacitance, CL, specified for the crystal.
The total load capacitance seen between
the crystal terminals should equal CL for
the crystal to oscillate at the specified
frequency.
The crystal oscillator is amplitude
regulated. This means that a high current
is used to start up the oscillations. When
the amplitude builds up, the current is
reduced to what is necessary to maintain
a stable oscillation. This ensures a fast
start-up and keeps the drive level to a
minimum. The ESR of the crystal must be
within the specification in order to ensure
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CC2420
XOSC16_Q1
XOSC16_Q2
XTAL
C391
C381
Figure 30. Crystal oscillator circuit
Item
CL= 16 pF
27 pF
C381
C391
27 pF
Table 10. Crystal oscillator component values
32 Input / Output Matching
The RF input / output is differential (RF_N
and RF_P). In addition there is supply
switch output pin (TXRX_SWITCH) that
must have an external DC path to RF_N
and RF_P.
Using a differential antenna, no balun is
required.
If a single ended output is required (for a
single ended connector or a single ended
antenna), a balun should be used for
optimum performance.
In RX mode the TXRX_SWITCH pin is at
ground and will bias the LNA. In TX mode
the TXRX_SWITCH pin is at supply rail
voltage and will properly bias the internal
PA.
The balun adds the signals from the RF_N
and RF_P. This is achieved having two
paths with equal amplitude response, but
180
degrees
phase
difference.
The RF output and DC bias can be done
using different topologies. Some are
33 Transmitter Test Modes
0x1800 to the DACTST register and issue
a STXONcommand strobe. The transmitter
is then enabled while the transmitter I/Q
DACs are overridden to static values. An
unmodulated carrier will then be available
on the RF output pins.
CC2420 can be set into different transmit
test modes for performance evaluation.
The test mode descriptions in the following
sections requires that the chip is first
reset, the crystal oscillator is enabled
using the SXOSCON command strobe and
that the crystal oscillator has stabilised.
A plot of the single carrier output spectrum
33.1 Unmodulated carrier
An
unmodulated
carrier
by
may
be
transmitted
setting
MDMCTRL1.TX_MODE to 2 or 3, writing
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CC2420
RBW
VBW
SWT
10 kHz
10 kHz
50 ms
RF Att
Unit
30 dB
dBm
A
Ref Lvl
3 dBm
3
0
-10
-20
-30
-40
-50
-60
-70
-80
1AVG
1SA
-90
-97
Center 2.45 GHz
200 kHz/
Span 2 MHz
Date:
23.OCT.2003 21:38:33
Figure 31. Single carrier output
sequence for bit error testing. Please note
33.2 Modulated spectrum
that
CC2420
requires
not
symbol
bit
synchronisation,
only
The CC2420 has a built-in test pattern
generator that can generate pseudo
random sequence using the CRC
generator. This is enabled by setting
MDMCTRL1.TX_MODE to 3 and issues an
STXON command strobe. The modulated
spectrum is then available on the RF pins.
The low byte of the CRC word is
transmitted and the CRC is updated with
0xFF for each new byte. The length of the
transmitted data sequence is 65535 bits.
The transmitted data-sequence is then:
synchronisation, for correct reception.
Packet error rate is therefore a better
measurement
performance.
for
the
true
RF
Another option to generate a modulated
spectrum is to fill the TXFIFO with pseudo-
random
data
and
set
MDMCTRL1.TX_MODE to 2. CC2420 will
then transmit data from the FIFO
disregarding a TXFIFO underflow. The
length of the transmitted data sequence is
then 1024 bits (128 bytes).
[Synchronisation header] [0x00, 0x78,
0xb8, 0x4b, 0x99, 0xc3, 0xe9, …]
A plot of the modulated spectrum from
find the output power from the modulated
spectrum, the RBW must be set to 3 MHz
or higher.
Since a synchronisation header (preamble
and SFD) is transmitted in all TX modes,
this test mode may also be used to
transmit
a
known pseudorandom bit
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CC2420
RBW 100 kHz
VBW 100 kHz
RF Att
Unit
30 dB
dBm
A
Ref Lvl
0 dBm
SWT
5 ms
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
1AVG
1SA
Center 2.45 GHz
1 MHz/
Span 10 MHz
Date:
23.OCT.2003 21:34:19
Figure 32. Modulated spectrum plot
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CC2420
34 System Considerations and Guidelines
SRD regulations
34.3 Crystal accuracy and drift
International regulations and national laws
regulate the use of radio receivers and
transmitters. SRDs (Short Range Devices)
for license free operation are allowed to
operate in the 2.4 GHz band worldwide.
The most important regulations are ETSI
EN 300 328 and EN 300 440 (Europe),
FCC CFR-47 part 15.247 and 15.249
(USA), and ARIB STD-T66 (Japan).
A crystal accuracy of ±40 ppm is required
for compliance with IEEE 802.15.4 [1].
This accuracy must also take ageing and
temperature drift into consideration.
A crystal with low temperature drift and
low aging could be used without further
compensation. A trimmer capacitor in the
crystal oscillator circuit (in parallel with C7)
could be used to set the initial frequency
accurately.
34.1 Frequency hopping and multi-
channel systems
For non-IEEE 802.15.4 systems, the
robust demodulator in CC2420 allows up to
120 ppm total frequency offset between
the transmitter and receiver. This could
e.g. relax the accuracy requirement to 60
ppm for each of the devices.
The 2.4 GHz band is shared by many
systems both in industrial, office and home
environments.
CC2420
uses
direct
sequence spread spectrum (DSSS) as
defined by [1] to spread the output power,
thereby making the communication link
more robust even in a noisy environment.
Optionally in a star network topology, the
FFD could be equipped with a more
accurate crystal thereby relaxing the
requirement on the RFD. This can make
sense in systems where the RFDs ship in
higher volumes than the FFDs.
With CC2420 it is also possible to combine
both DSSS and FHSS (frequency hopping
spread spectrum) in a proprietary non-
IEEE 802.15.4 system. This is achieved
by reprogramming the operating frequency
34.4 Communication robustness
enabling RX or TX.
A
frequency
CC2420 provides very good adjacent,
alternate and co channel rejection, image
frequency suppression and blocking
properties. The CC2420 performance is
significantly better than the requirements
imposed by [1]. These are highly important
parameters for reliable operation in the 2.4
GHz band, since an increasing number of
devices/systems are using this license
free frequency band.
synchronisation scheme must then be
implemented within the proprietary MAC
layer to make the transmitter and receiver
operate on the same RF channel.
34.2 Data burst transmissions
The data buffering in CC2420 lets the user
have a lower data rate link between the
microcontroller and the RF device than the
RF bit rate of 250 kbps. This allows the
microcontroller to buffer data at its own
speed, reducing the workload and timing
requirements.
34.5 Communication security
The
hardware
encryption
and
authentication operations in CC2420
enable secure communication, which is
required for many applications. Security
The relatively high data rate of CC2420
also reduces the average power
consumption compared to the 868 / 915
MHz bands defined by [1], where only 20 /
40 kbps are available. CC2420 may be
powered up a smaller portion of the time,
so that the average power consumption is
reduced for a given amount of data to be
transferred.
operations require
a
lot of data
processing, which is costly in an 8-bit
microcontroller system. The hardware
support within CC2420 enables a high level
of security even with a low-cost 8 bit
controller.
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CC2420
required
to
re-gain
34.6 Low-cost systems
synchronisation.
As the CC2420 provides 250 kbps multi-
channel performance without any external
filters, a very low-cost system can be
made.
In an IEEE 802.15.4 system, all
communication is based on packets. The
sensitivity limit specified by [1] is based on
Packet Error Rate (PER) measurements
instead of BER. This is a more accurate
measurement of the true RF performance
since it mirrors the way the actual system
operates.
A differential antenna will eliminate the
need for a balun, and the DC biasing can
be achieved in the antenna topology.
34.7 Battery operated systems
It is recommended to perform PER
In low power applications, the CC2420
should be powered down when not being
active. Extremely low power consumption
may be achieved when disabling also the
voltage regulator. This will require
reprogramming of the register and RAM
configuration.
measurements
measurements
performance of IEEE 802.15.4 systems.
To do PER measurements, the following
may be used as a guideline:
instead
to evaluate
of
BER
the
•
A valid preamble, SFD and length
field must be used for each
packet.
34.8 BER / PER measurements
CC2420 includes test modes where data is
received infinitely and output to pins
may be used for Bit Error Rate (BER)
measurements. However, the following
actions must be taken to do such a
measurement:
•
The PSDU (see Figure 17 on
bytes for sensitivity measurements
as specified by [1].
•
The sensitivity limit specified by [1]
is the RF level resulting in a 1%
PER. The packet sample space
for a given measurement must
•
A preamble and SFD sequence
must be used, even if pseudo
random data is transmitted, since
receiving the DSSS modulated
then be >> 100 to have
a
sufficiently large sample space.
E.g. at least 1000 packets should
be used to measure the
sensitivity.
signal
synchronisation,
requires
symbol
bit
not
synchronisation like e.g. in 2FSK
systems. The SYNCWORD may be
set to another value to fit to the
measurement setup if necessary.
•
The data transmitted over air must
be spread according to [1] and the
generated packets may be used,
although [1] requires that the PER
is averaged over random PSDU
data.
•
The data transmitted over air must
be spread according to [1] and the
description on page 24. This
means that the transmitter used
during measurements must be
able to do spreading of the bit
data to chip data. Remember that
the chip sequence transmitted by
the test setup is not the same as
the bit sequence, which is output
by CC2420.
•
•
The CC2420 receive FIFO may be
used to buffer data received
during PER measurements, since
it is able to buffer up to 128 bytes.
The
control register is by default set to
20, as described in the
MDMCTRL1.CORR_THR
•
When operating at or below the
sensitivity limit, CC2420 may loose
symbol synchronisation in infinite
receive mode. A new SFD and
restart of the receiver may be
section.
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CC2420
signal has the same phase shifts as the O-
QPSK sequence previously defined.
•
The
RXCTRL1.RXBPF_LOCUR
control bit should be set to 1.
For a desired symbol sequence s0, s1, … ,
sn-1 of length n symbols, the desired chip
sequence c0, c1, c2, …, c32n-1 of length 32n
is found using table lookup from Table 3
comparing the phase shifts of the O-QPSK
signal with the frequency of a MSK signal
that the MSK chip sequence is generated
as:
The simplest way of making a PER
measurement will be to use another
CC2420 as the reference transmitter.
However, this makes it difficult to measure
the exact receiver performance.
Using a signal generator, this may either
be set up as O-QPSK with half-sine
shaping or as MSK. If using O-QPSK, the
phases must be selected according to [1].
If using MSK, the chip sequence must be
modified such that the modulated MSK
(c0 xnor c1), (c1 xor c2), (c2 xnor c3), … ,
(c32n-1 xor c32n) where c32n may be
arbitrarily selected.
35 PCB Layout Recommendations
Following Texas Instruments’s reference
design is highly recommended.
separate vias. Supply power filtering is
very important.
In our reference design, the top layer is
used for signal routing, and the open
areas are filled with metallisation
connected to ground using several vias.
Layer 2 has not been used in our CC2420
reference designs. Layer 3 is used for
power routing and the bottom layer serves
as ground plane with a little routing.
The external components should be as
small as possible (0402 is recommended)
and surface mount devices must be used.
Caution should be used when placing the
microcontroller
in
order
to
avoid
interference with the RF circuitry.
A Development Kit with a fully assembled
Evaluation Module is available. It is
strongly advised that this reference layout
is followed very closely in order to get the
best performance.
The area under the chip is used for
grounding and must be well connected to
the ground plane with several vias.
The ground pins should be connected to
ground as close as possible to the
package pin using individual vias. The de-
coupling capacitors should also be placed
as close as possible to the supply pins
and connected to the ground plane by
The schematic, BOM and layout Gerber
files for the reference designs are all
available from the Texas Instruments
website.
36 Antenna Considerations
where f is in MHz, giving the length in cm.
An antenna for 2450 MHz should be 5.8
cm. Each arm is therefore 2.9 cm.
CC2420 can be used together with various
types of antennas. A differential antenna
like a dipole would be the easiest to
interface not needing a balun (balanced to
un-balanced transformation network).
Other commonly used antennas for short-
range communication are monopole,
helical and loop antennas. The single-
ended monopole and helical would require
a balun network between the differential
output and the antenna.
The length of the λ/2-dipole antenna is
given by:
L = 14250 / f
Monopole
antennas
are
resonant
antennas with a length corresponding to
one quarter of the electrical wavelength
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CC2420
of the antenna. Many vendors offer such
antennas intended for PCB mounting.
(λ/4). They are very easy to design and
can be implemented simply as a “piece of
wire” or even integrated into the PCB.
Helical antennas can be thought of as a
combination of a monopole and a loop
antenna. They are a good compromise in
size critical applications. Helical antennas
tend to be more difficult to optimize than
the simple monopole.
The length of the λ/4-monopole antenna is
given by:
L = 7125 / f
Loop antennas are easy to integrate into
the PCB, but are less effective due to
difficult impedance matching because of
their very low radiation resistance.
where f is in MHz, giving the length in cm.
An antenna for 2450 MHz should be 2.9
cm.
For low power applications the differential
antenna is recommended giving the best
range and because of its simplicity.
Non-resonant monopole antennas shorter
than λ/4 can also be used, but at the
expense of range. In size and cost critical
applications such an antenna may very
well be integrated into the PCB.
The antenna should be connected as
close as possible to the IC. If the antenna
is located away from the RF pins the
antenna should be matched to the feeding
transmission line (50 Ω).
Enclosing the antenna in high dielectric
constant material reduces the overall size
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CC2420
37 Configuration Registers
are 33 normal 16-bits registers, also listed
for test purposes only, and need not be
accessed for normal operation of CC2420.
The configuration of CC2420 is done by
programming the 16-bit configuration
registers. Complete descriptions of the
registers are given in the following tables.
After chip reset (from the RESETn pin or
programmable through the MAIN.RESETn
configuration bit), all the registers have
default values as shown in the tables.
The FIFOs are accessed through two 8-bit
registers, TXFIFO and RXFIFO. The
TXFIFO register is write only. Data may
still be read out of the TXFIFO through
access section on page 29), but data is
then not removed from the FIFO. Note that
the crystal oscillator must be active for all
FIFO and RAM access.
Note that the MAIN register is only reset
by using the pin reset RESETn. When
writing to this register, all bits will get the
value written, not the default value. This
also means that the MAIN.RESETn bit
must be written both low and then high to
perform a chip reset through the serial
interface.
During address transfer, and while data is
being written to the TXFIFO, a status byte
is returned on the serial data output pin
15 registers are Strobe Command
Accessing these registers will initiate the
change of an internal state or mode. There
All configuration and status registers are
Address
0x00
Register
SNOP
Register type
Description
S
S
No Operation (has no other effect than reading out status-bits)
SXOSCON
0x01
Turn on the crystal oscillator (set XOSC16M_PD = 0 and
BIAS_PD = 0)
STXCAL
0x02
S
Enable and calibrate frequency synthesizer for TX;
Go from RX / TX to a wait state where only the synthesizer is
running.
SRXON
STXON
0x03
0x04
S
Enable RX
S
Enable TX after calibration (if not already performed)
Start TX in-line encryption if SPI_SEC_MODE ≠ 0
STXONCCA
0x05
S
If CCA indicates a clear channel:
Enable calibration, then TX.
Start in-line encryption if SPI_SEC_MODE ≠ 0
else
do nothing
SRFOFF
0x06
0x07
0x08
S
S
S
Disable RX/TX and frequency synthesizer
Turn off the crystal oscillator and RF
SXOSCOFF
SFLUSHRX
Flush the RX FIFO buffer and reset the demodulator. Always
read at least one byte from the RXFIFO before issuing the
SFLUSHRXcommand strobe
SFLUSHTX
SACK
0x09
0x0A
0x0B
0x0C
S
S
S
S
Flush the TX FIFO buffer
Send acknowledge frame, with pending field cleared.
Send acknowledge frame, with pending field set.
SACKPEND
SRXDEC
Start RXFIFO in-line decryption / authentication (as set by
SPI_SEC_MODE)
STXENC
0x0D
S
Start TXFIFO in-line encryption / authentication (as set by
SPI_SEC_MODE), without starting TX.
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CC2420
Address
Register
Register type
Description
SAES
0x0E
S
AES Stand alone encryption strobe. SPI_SEC_MODE is not
required to be 0, but the encryption module must be idle. If not,
the strobe is ignored.
-
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
-
Not used
MAIN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Main Control Register
MDMCTRL0
MDMCTRL1
RSSI
Modem Control Register 0
Modem Control Register 1
RSSI and CCA Status and Control register
Synchronisation word control register
Transmit Control Register
SYNCWORD
TXCTRL
RXCTRL0
RXCTRL1
FSCTRL
SECCTRL0
SECCTRL1
BATTMON
IOCFG0
IOCFG1
MANFIDL
MANFIDH
FSMTC
Receive Control Register 0
Receive Control Register 1
Frequency Synthesizer Control and Status Register
Security Control Register 0
Security Control Register 1
Battery Monitor Control and Status Register
Input / Output Control Register 0
Input / Output Control Register 1
Manufacturer ID, Low 16 bits
Manufacturer ID, High 16 bits
Finite State Machine Time Constants
Manual signal AND override register
Manual signal OR override register
AGC Control Register
MANAND
MANOR
AGCCTRL
AGCTST0
AGCTST1
AGCTST2
FSTST0
FSTST1
FSTST2
FSTST3
RXBPFTST
FSMSTATE
ADCTST
DACTST
TOPTST
RESERVED
AGC Test Register 0
AGC Test Register 1
AGC Test Register 2
Frequency Synthesizer Test Register 0
Frequency Synthesizer Test Register 1
Frequency Synthesizer Test Register 2
Frequency Synthesizer Test Register 3
Receiver Bandpass Filter Test Register
Finite State Machine State Status Register
ADC Test Register
R/W
R/W
R/W
R/W
DAC Test Register
Top Level Test Register
Reserved for future use control / status register
Not used
0x31-
0x3D
-
-
TXFIFO
RXFIFO
0x3E
0x3F
W
Transmit FIFO Byte Register
Receiver FIFO Byte Register
R/W
R/W - Read/write (control/status), R - Read only, W – Write only, S – Command Strobe (perform action upon access)
Table 11. Configuration registers overview
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CC2420
MAIN (0x10) - Main Control Register
Bit
Field Name
Reset
R/W
Description
15
RESETn
1
R/W
Active low reset of the entire circuit should be applied before
doing anything else. Equivalent to using the RESETnreset pin.
14
13
ENC_RESETn
1
1
R/W
R/W
Active low reset of the encryption module. (Test purposes only)
DEMOD_RESETn
Active low reset of the demodulator module. (Test purposes
only)
12
11
MOD_RESETn
FS_RESETn
1
1
R/W
R/W
Active low reset of the modulator module. (Test purposes only)
Active low reset of the frequency synthesizer module. (Test
purposes only)
10:1
0
-
0
0
W0
Reserved, write as 0
XOSC16M_BYPASS
R/W
Bypasses the crystal oscillator and uses a buffered version of the
signal on Q1 directly. This can be used to apply an external rail-
rail clock signal to the Q1 pin.
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CC2420
MDMCTRL0 (0x11) - Modem Control Register 0
Bit
Field Name
Reset
0
R/W
W0
Description
15:14 -
Reserved, write as 0
13
RESERVED_FRAME_MODE
0
R/W
Mode for accepting reserved IEE 802.15.4 frame types when
address recognition is enabled (MDMCTRL0.ADR_DECODE = 1).
0 : Reserved frame types (100, 101, 110, 111) are rejected by
address recognition.
1 : Reserved frame types (100, 101, 110, 111) are always
accepted by address recognition. No further address decoding is
done.
When address recognition is disabled (MDMCTRL0.ADR_DECODE =
0), all frames are received and RESERVED_FRAME_MODEis don’t
care.
12
11
PAN_COORDINATOR
ADR_DECODE
0
1
R/W
R/W
Should be set high when the device is a PAN Coordinator. Used
for filtering packets with no destination address, as specified in
section 7.5.6.2 in 802.15.4, D18
Hardware Address decode enable.
0 : Address decoding is disabled
1 : Address decoding is enabled
10:8
7:6
CCA_HYST[2:0]
CCA_MODE[1:0]
2
3
R/W
R/W
CCA Hysteresis in dB, values 0 through 7 dB
0 : Reserved
1 : CCA=1 when RSSI_VAL< CCA_THR - CCA_HYST
CCA=0 when RSSI_VAL≥ CCA_THR
2 : CCA=1 when not receiving valid IEEE 802.15.4 data,
CCA=0 otherwise
3 : CCA=1 when RSSI_VAL< CCA_THR - CCA_HYSTand not
receiving valid IEEE 802.15.4 data.
CCA=0 when RSSI_VAL≥ CCA_THRor receiving a packet
5
AUTOCRC
AUTOACK
1
0
2
R/W
R/W
R/W
In packet mode a CRC-16 (ITU-T) is calculated and is
transmitted after the last data byte in TX. In RX CRC is
calculated and checked for validity.
4
If AUTOACK is set, all packets accepted by address recognition
with the acknowledge request flag set and a valid CRC are
acknowledged 12 symbol periods after being received.
3:0
PREAMBLE_LENGTH
[3:0]
The number of preamble bytes (2 zero-symbols) to be sent in TX
mode prior to the SYNCWORD, encoded in steps of 2. The reset
value of 2 is compliant with IEEE 802.15.4, since the 4th zero
byte is included in the SYNCWORD.
0 : 1 leading zero bytes (not recommended)
1 : 2 leading zero bytes (not recommended)
2 : 3 leading zero bytes (IEEE 802.15.4 compliant)
3 : 4 leading zero bytes
…
15 : 16 leading zero bytes
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CC2420
MDMCTRL1 (0x12)– Modem Control Register 1
Bit
Field Name
Reset
0
R/W
W0
Description
15:11 -
Reserved, write as 0.
10:6
CORR_THR[4:0]
20
R/W
Demodulator correlator threshold value, required before SFD
search. Note that on early CC2420 versions the reset value was
0.
5
DEMOD_AVG_MODE
MODULATION_MODE
0
0
R/W
R/W
Frequency offset average filter behaviour.
0 : Lock frequency offset filter after preamble match
1 : Continuously update frequency offset filter.
4
Set one of two RF modulation modes for RX / TX
0 : IEEE 802.15.4 compliant mode
1 : Reversed phase, non-IEEE compliant (could be used to set
up a system which will not receive 802.15.4 packets)
3:2
TX_MODE[1:0]
RX_MODE[1:0]
0
0
R/W
R/W
Set test modes for TX
0 : Buffered mode, use TXFIFO (normal operation)
1 : Serial mode, use transmit data on serial interface, infinite
transmission. For lab testing only.
2 : TXFIFO looping ignore underflow in TXFIFO and read cyclic,
infinite transmission. For lab testing only.
3 : Send random data from CRC, infinite transmission. For lab
testing only.
1:0
Set test mode of RX
0 : Buffered mode, use RXFIFO (normal operation)
1 : Receive serial mode, output received data on pins. Infinite
RX. For lab testing only.
2 : RXFIFO looping ignore overflow in RXFIFO and write cyclic,
infinite reception. For lab testing only.
3 : Reserved
RSSI (0x13) - RSSI and CCA Status and Control Register
Bit
Field Name
Reset
R/W
Description
15:8
CCA_THR[7:0]
-32
R/W
Clear Channel Assessment threshold value, signed number on
2’s complement for comparison with the RSSI.
The unit is 1 dB, offset is the same as for RSSI_VAL. The CCA
signal goes active when the received signal is below this value.
The CCA signal is available on the CCApin.
The reset value is approximately -77 dBm.
7:0
RSSI_VAL[7:0]
-128 R
RSSI estimate on a logarithmic scale, signed number on 2’s
complement.
The RSSI_VALvalue is averaged over 8 symbol periods. The
RSSI_VALIDstatus bit may be checked to verify that the
receiver has been enabled for at least 8 symbol periods.
The reset value of –128 also indicates that the RSSI_VALvalue
is invalid.
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CC2420
SYNCWORD (0x14) - Sync Word
Bit
Field Name
Reset
R/W
Description
15:0
SYNCWORD[15:0]
0xA70F R/W
Synchronisation word. The SYNCWORDis processed from the
least significant nibble (F at reset) to the most significant nibble
(A at reset).
SYNCWORDis used both during modulation (where 0xF’s are
replaced with 0x0’s) and during demodulation (where 0xF’s are
not required for frame synchronisation). In reception an implicit
zero is required before the first symbol required by SYNCWORD.
The reset value is compliant with IEEE 802.15.4.
TXCTRL (0x15) - Transmit Control Register
Bit
Field Name
Reset
R/W
Description
15:14 TXMIXBUF_CUR[1:0]
2
R/W
TX mixer buffer bias current.
0: 690uA
1: 980uA
2: 1.16mA (nominal)
3: 1.44mA
13
TX_TURNAROUND
1
0
R/W
Sets the wait time after STXON before transmission is started.
0 : 8 symbol periods (128 us)
1 : 12 symbol periods (192 us)
12:11 TXMIX_CAP_ARRAY[1:0]
R/W
R/W
Selects varactor array settings in the transmit mixers.
Transmit mixers current:
10:9
8:6
TXMIX_CURRENT[1:0] 0
0: 1.72 mA
1: 1.88 mA
2: 2.05 mA
3: 2.21 mA
PA_CURRENT[2:0]
3
R/W
Current programming of the PA
0: -3 current adjustment
1: -2 current adjustment
2: -1 current adjustment
3: Nominal setting
4: +1 current adjustment
5: +2 current adjustment
6: +3 current adjustment
7: +4 current adjustment
5
-
1
W1
Reserved, write as 1.
4:0
PA_LEVEL[4:0]
31
R/W
Output PA level. (~0 dBm)
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CC2420
RXCTRL0 (0x16) – Receive control register 0
Bit
Field Name
Reset
0
R/W
W0
Description
15:14 -
Reserved, write as 0.
RX mixer buffer bias current.
13:12 RXMIXBUF_CUR[1:0]
1
R/W
0: 690uA
1: 980uA (nominal)
2: 1.16mA
3: 1.44mA
11:10 HIGH_LNA_GAIN[1:0]
0
R/W
Controls current in the LNA gain compensation branch in AGC
High gain mode.
0: Compensation disabled
1: 100 µA compensation current
2: 300 µA compensation current (Nominal)
3: 1000 µA compensation current
9:8
7:6
5:4
MED_LNA_GAIN[1:0]
LOW_LNA_GAIN[1:0]
2
3
R/W
R/W
R/W
Controls current in the LNA gain compensation branch in AGC
Med gain mode.
Controls current in the LNA gain compensation branch in AGC
Low gain mode
HIGH_LNA_CURRENT[1:0] 2
Controls main current in the LNA in AGC High gain mode
0: 240 µA LNA current (x2)
1: 480 µA LNA current (x2)
2: 640 µA LNA current (x2)
3: 1280 µA LNA current (x2)
3:2
1:0
MED_LNA_CURRENT[1:0]
LOW_LNA_CURRENT[1:0]
1
1
R/W
R/W
Controls main current in the LNA in AGC Med gain mode
Controls main current in the LNA in AGC Low gain mode
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CC2420
RXCTRL1 (0x17) - Receive control register 1
Bit
Field Name
Reset
0
R/W
W0
Description
15:14 -
Reserved, write as 0.
13
12
RXBPF_LOCUR
0
R/W
Controls reference bias current to RX bandpass filters:
0: 4 uA (Reset value) Use 1 instead
1: 3 uA Note: Recommended setting
RXBPF_MIDCUR
0
R/W
Controls reference bias current to RX bandpass filters:
0: 4 uA (Default)
1: 3.5 uA
11
10
9
LOW_LOWGAIN
MED_LOWGAIN
HIGH_HGM
1
0
1
0
1
R/W
R/W
R/W
R/W
R/W
LNA low gain mode setting in AGC low gain mode.
LNA low gain mode setting in AGC medium gain mode.
RX Mixers high gain mode setting in AGC high gain mode.
RX Mixers high gain mode setting in AGC medium gain mode.
Selects varactor array setting in the LNA
8
MED_HGM
7:6
LNA_CAP_ARRAY[1:0]
0: OFF
1: 0.1pF (x2) (Nominal)
2: 0.2pF (x2)
3: 0.3pF (x2)
5:4
3:2
1:0
RXMIX_TAIL[1:0]
RXMIX_VCM[1:0]
1
1
2
R/W
R/W
R/W
Control of the receiver mixers output current.
0: 12 µA
1: 16 µA (Nominal)
2: 20 µA
3: 24 µA
Controls VCM level in the mixer feedback loop
0: 8 µA mixer current
1: 12 µA mixer current (Nominal)
2: 16 µA mixer current
3: 20 µA mixer current
RXMIX_CURRENT[1:0]
Controls current in the mixer
0: 360 µA mixer current (x2)
1: 720 µA mixer current (x2)
2: 900 µA mixer current (x2) (Nominal)
3: 1260 µA mixer current (x2)
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CC2420
FSCTRL (0x18) - Frequency Synthesizer Control and Status
Bit
Field Name
Reset
R/W
Description
15:14 LOCK_THR[1:0]
1
R/W
Number of consecutive reference clock periods with successful
synchronisation windows required to indicate lock:
0: 64
1: 128 (recommended)
2: 256
3: 512
13
12
11
CAL_DONE
0
0
0
R
Calibration has been performed since the last time the frequency
synthesizer was turned on.
CAL_RUNNING
LOCK_LENGTH
R
Calibration status, '1' when calibration in progress and ‘0’
otherwise.
R/W
Synchronisation window pulse width:
0: 2 prescaler clock periods (recommended)
1: 4 prescaler clock periods
10
LOCK_STATUS
FREQ[9:0]
0
R
Frequency synthesizer lock status:
0 : Frequency synthesizer is out of lock
1 : Frequency synthesizer is in lock
9:0
357
R/W
Frequency control word, controlling the RF operating frequency
FC. In transmit mode, the local oscillator (LO) frequency equals
FC. In receive mode, the LO frequency is 2 MHz below FC.
(2405
MHz)
FC = 2048 + FREQ[9:0]MHz
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CC2420
SECCTRL0 (0x19) - Security Control Register
Bit
Field Name
Reset
0
R/W
W0
Description
15:10 -
Reserved, write as 0
9
RXFIFO_PROTECTION
1
R/W
Protection enable of the RXFIFO, see description in the RXFIFO
security is not used or is implemented outside CC2420.
8
SEC_CBC_HEAD
1
R/W
Defines what to use for the first byte in CBC-MAC (does not
apply to CBC-MAC part of CCM):
0 : Use the first data byte as the first byte into CBC-MAC
1 : Use the length of the data to be authenticated (calculated as
(the packet length field – SEC_TXL– 2) for TX or using SEC_RXL
for RX) as the first byte into CBC-MAC (before the first data
byte).
This bit should be set high for CBC-MAC 802.15.4 inline security.
Stand Alone Key select
7
SEC_SAKEYSEL
SEC_TXKEYSEL
SEC_RXKEYSEL
SEC_M[2:0]
1
1
0
1
R/W
R/W
R/W
R/W
0 : Key 0 is used
1 : Key 1 is used
6
TX Key select
0 : Key 0 is used
1 : Key 1 is used
5
RX Key select
0 : Key 0 is used
1 : Key 1 is used
4:2
Number of bytes in authentication field for CBC-MAC, encoded
as (M-2)/2
0 : Reserved
1 : 4
2 : 6
3 : 8
4 : 10
5 : 12
6 : 14
7 : 16
1:0
SEC_MODE[1:0]
0
R/W
Security mode
0 : In-line security is disabled
1 : CBC-MAC
2 : CTR
3 : CCM
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CC2420
SECCTRL1 (0x1A) - Security Control Register
Bit
Field Name
-
Reset
0
R/W
W0
Description
15
Reserved, write as 0
14:8
SEC_TXL
0
R/W
Multi-purpose length byte for TX in-line security operations:
CTR : Number of cleartext bytes between length byte and the
first byte to be encrypted
CBC/MAC : Number of cleartext bytes between length byte and
the first byte to be authenticated
CCM : l(a), defining the number of bytes to be authenticated but
not encrypted
Stand-alone : SEC_TXL has no effect
Reserved, write as 0
7
-
0
0
W0
6:0
SEC_RXL
R/W
Multi-purpose length byte for RX in-line security operations:
CTR : Number of cleartext bytes between length byte and the
first byte to be decrypted
CBC/MAC : Number of cleartext bytes between length byte and
the first byte to be authenticated
CCM : l(a), defining the number of bytes to be authenticated but
not decrypted
Stand-alone : SEC_RXL has no effect
BATTMON (0x1B) – Battery Monitor Control register
Bit
15:7
6
Field Name
-
Reset
0
R/W
W0
R
Description
Reserved, write as 0
BATTMON_OK
1
Battery monitor comparator output, read only. BATT_OK is valid
5 us after BATTMON_EN has been asserted and
BATTMON_VOLTAGE has been programmed.
0 : Power supply < Toggle Voltage
1 : Power supply > Toggle Voltage
5
BATTMON_EN
0
0
R/W
R/W
Battery monitor enable
0 : Battery monitor is disabled
1 : Battery monitor is enabled
4:0
BATTMON_VOLTAGE
[4:0]
Battery monitor toggle voltage. The toggle voltage is given by:
72 − BATTMON_VOLTAGE
= 1.25V⋅
Vtoggle
27
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CC2420
IOCFG0 (0x1C) – I/O Configuration Register 0
Bit
Field Name
Reset
0
R/W
W0
Description
15:12 -
Reserved, write as 0
11
BCN_ACCEPT
0
R/W
Accept all beacon frames when address recognition is enabled.
This bit should be set when the PAN identifier programmed into
CC2420 RAM is equal to 0xFFFF and cleared otherwise. This bit
is don't care when MDMCTRL0.ADR_DECODE= 0.
0 : Only accept beacons with a source PAN identifier which
matches the PAN identifier programmed into CC2420 RAM
1 : Accept all beacons regardless of the source PAN identifier
10
9
FIFO_POLARITY
FIFOP_POLARITY
SFD_POLARITY
CCA_POLARITY
0
R/W
R/W
R/W
R/W
R/W
Polarity of the output signal FIFO.
0 : Polarity is active high
1 : Polarity is active low
0
Polarity of the output signal FIFOP.
0 : Polarity is active high
1 : Polarity is active low
8
0
Polarity of the SFDpin.
0 : Polarity is active high
1 : Polarity is active low
7
0
Polarity of the CCApin.
0 : Polarity is active high
1 : Polarity is active low
6:0
FIFOP_THR[6:0]
64
FIFOP_THR sets the threshold in number of bytes in the
RXFIFO for FIFOP to go active.
IOCFG1 (0x1D) – I/O Configuration Register 1
Bit
Field Name
Reset
0
R/W
W0
Description
15:13 -
Reserved, write as 0
12:10 HSSD_SRC[2:0]
0
R/W
The HSSD module is used as follows:
0: Off.
1: Output AGC status (gain setting / peak detector status /
accumulator value)
2: Output ADC I and Q values.
3: Output I/Q after digital down mix and channel filtering.
4: Reserved
5: Reserved
6: Input ADC I and Q values
7: Input DAC I and Q values.
The HSSD module requires that the FS is up and running as it
uses CLK_PRE (~150 MHZ) to produce its ~37.5 MHz data clock
and serialize its output words.
9:5
4:0
SFDMUX[4:0]
CCAMUX[4:0]
0
0
R/W
R/W
Multiplexer setting for the SFDpin.
Multiplexer setting for the CCApin.
MANFIDL (0x1E) - Manufacturer ID, Lower 16 Bit
Bit
Field Name
Reset
R/W
Description
15:12 PARTNUM[3:0]
11:0 MANFID[11:0]
2
R
The device part number. CC2420 has part number 0x002.
0x33D R
Gives the JEDEC manufacturer ID. The actual manufacturer ID
can be found in MANIFID[7:1], the number of continuation bytes
in MANFID[11:8] and MANFID[0]=1.
Chipcon's JEDEC manufacturer ID is 0x7F 0x7F 0x7F 0x9E
(0x1E preceded by three continuation bytes.)
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CC2420
MANFIDH (0x1F) - Manufacturer ID, Upper 16 Bit
Bit
Field Name
Reset
R/W
Description
15:12 VERSION[3:0]
11:0 PARTNUM[15:4]
3
R
Version number. Current version is 3.
Note that previous CC2420 versions will have lower reset values.
0
R
The device part number. CC2420 has part number 0x002.
FSMTC (0x20) - Finite state machine time constants
Bit
Field Name
Reset
R/W
Description
15:13 TC_RXCHAIN2RX[2:0] 3
R/W
The time in 5 us steps between the time the RX chain is enabled
and the demodulator and AGC is enabled. The RX chain is
started when the bandpass filter has been calibrated (after 6.5
symbol periods).
12:10 TC_SWITCH2TX[2:0]
6
R/W
R/W
R/W
R/W
The time in advance the RXTX switch is set high, before
enabling TX. In µs.
9:6
5:3
2:0
TC_PAON2TX[3:0]
TC_TXEND2SWITCH[2:0]
TC_TXEND2PAOFF[2:0]
10
2
The time in advance the PA is powered up before enabling TX.
In µs.
The time after the last chip in the packet is sent, and the TXRX
switch is disabled. In µs.
4
The time after the last chip in the packet is sent, and the PA is
set in power-down. Also the time at which the modulator is
disabled. In µs.
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CC2420
MANAND (0x21) - Manual signal AND override register1
Bit
Field Name
Reset
R/W
Description
15
VGA_RESET_N
1
R/W
The VGA_RESET_N signal is used to reset the peak detectors in
the VGA in the RX chain.
14
13
BIAS_PD
1
1
R/W
R/W
Global bias power down (1)
BALUN_CTRL
The BALUN_CTRL signal controls whether the PA should
receive its required external biasing (1) or not (0) by controlling
the RX/TX output switch.
12
RXTX
1
R/W
RXTX signal: controls whether the LO buffers (0) or PA buffers
(1) should be used.
11
10
9
PRE_PD
1
1
1
R/W
R/W
R/W
Powerdown of prescaler.
PA_N_PD
PA_P_PD
Powerdown of PA (negative path).
Powerdown of PA (positive path). When PA_N_PD=1 and
PA_P_PD=1 the up-conversion mixers are in powerdown.
8
7
6
DAC_LPF_PD
1
1
1
R/W
R/W
R/W
Powerdown of TX DACs.
XOSC16M_PD
RXBPF_CAL_PD
Powerdown control of complex bandpass receive filter calibration
oscillator.
5
4
3
2
1
0
CHP_PD
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
Powerdown control of charge pump.
FS_PD
Powerdown control of VCO, I/Q generator, LO buffers.
Powerdown control of the ADCs.
ADC_PD
VGA_PD
Powerdown control of the VGA.
RXBPF_PD
LNAMIX_PD
Powerdown control of complex bandpass receive filter.
Powerdown control of LNA, down-conversion mixers and front-
end bias.
1 For some important signals the value used by analog and digital modules can be overridden manually. This is done
as follows for the hypothetical important signal IS:
IS_USED = (IS * IS_AND_MASK) + IS_OR_MASK,
using boolean notation.
The AND-mask and OR-mask for the important signals listed resides in the MANAND and MANOR registers,
respectively.
Examples:
•
Writing 0xFFFE to MANAND and 0x0000 to MANOR will force LNAMIX_PD≡0 whereas all other signals will be
unaffected.
•
Writing 0xFFFF to MANAND and 0x0001 to MANOR will force LNAMIX_PD≡1 whereas all other signals will be
unaffected.
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CC2420
MANOR (0x22) - Manual signal OR override register
Bit
Field Name
Reset
R/W
Description
15
VGA_RESET_N
0
R/W
The VGA_RESET_Nsignal is used to reset the peak detectors in
the VGA in the RX chain.
14
13
BIAS_PD
0
0
R/W
R/W
Global Bias power down (1)
BALUN_CTRL
The BALUN_CTRLsignal controls whether the PA should receive
its required external biasing (1) or not (0) by controlling the
RX/TX output switch.
12
RXTX
0
R/W
RXTX signal: controls whether the LO buffers (0) or PA buffers
(1) should be used.
11
10
9
PRE_PD
0
0
0
R/W
R/W
R/W
Powerdown of prescaler.
PA_N_PD
PA_P_PD
Powerdown of PA (negative path).
Powerdown of PA (positive path). When PA_N_PD=1 and
PA_P_PD=1 the up-conversion mixers are in powerdown.
8
7
6
DAC_LPF_PD
0
0
0
R/W
R/W
Powerdown of TX DACs.
XOSC16M_PD
RXBPF_CAL_PD
Powerdown control of complex bandpass receive filter calibration
oscillator.
5
4
3
2
1
0
CHP_PD
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Powerdown control of charge pump.
FS_PD
Powerdown control of VCO, I/Q generator, LO buffers.
Powerdown control of the ADCs.
ADC_PD
VGA_PD
Powerdown control of the VGA.
RXBPF_PD
LNAMIX_PD
Powerdown control of complex bandpass receive filter.
Powerdown control of LNA, down-conversion mixers and front-
end bias.
AGCCTRL (0x23) - AGC Control
Bit
Field Name
Reset
0
R/W
W0
Description
15:12 -
Reserved, write as 0
11
VGA_GAIN_OE
0
R/W
Use the VGA_GAINvalue during RX instead of the AGC value.
10:4
VGA_GAIN [6:0]
0x7F R/W
When written, VGA manual gain override value; when read, the
currently used VGA gain setting.
3:2
1:0
LNAMIX_GAINMODE_O
[1:0]
0
R/W
LNA / Mixer Gain mode override setting
0 : Gain mode is set by AGC algorithm
1 : Gain mode is always low-gain
2 : Gain mode is always med-gain
3 : Gain mode is always high-gain
LNAMIX_GAINMODE
[1:0]
3
R
Status bit, defining the currently selected gain mode selected by
the AGC or overridden by the LNAMIX_GAINMODE_Osetting.
SWRS041B
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CC2420
AGCTST0 (0x24) - AGC Test Register 0
Bit
Field Name
Reset
R/W
Description
15:12 LNAMIX_HYST[3:0]
3
R/W
Hysteresis on the switching between different RF front-end
gain modes, defined in 2 dB steps
11:6
5:0
LNAMIX_THR_H[5:0]
LNAMIX_THR_L[5:0]
25
9
R/W
R/W
Threshold for switching between medium and high RF front-
end gain mode, defined in 2 dB steps
Threshold for switching between low and medium RF front-end
gain mode, defined in 2 dB steps
AGCTST1 (0x25) - AGC Test Register 1
Bit
15
14
Field Name
Reset
0
R/W
W0
Description
-
Reserved, write as 0
AGC_BLANK_MODE
0
R/W
Set the VGA blanking mode when switching out a gain stage
When VGA_GAIN_OE= 0:
0 : Blanking is performed when the AGC algorithm switches
out one or more 14dB gain stages.
1 : Blanking is never performed.
When VGA_GAIN_OE= 1:
Blanking is performed when AGC_BLANK_MODE=1
13
PEAKDET_CUR_BOOST
0
R/W
Doubles the bias current in the peak-detectors in-between the
VGA stages when set.
12:11 AGC_SETTLE_WAIT[1:0] 1
R/W
R/W
Timing for AGC to wait for analog gain to settle.
10:8
AGC_PEAK_DET_MODE
[2:0]
0
Sets the AGC mode for use of the VGA peak detectors:
Bit 2 : Digital ADC peak detector enable / disable
Bit 1 : Analog fixed stages peak detector enable /
disable
Bit 0 : Analog variable gain stage peak detector enable /
disable
7:6
AGC_WIN_SIZE[1:0]
AGC_REF[5:0]
1
R/W
R/W
Window size for the accumulate and dump function in the
AGC.
0 : 8 samples
1 : 16 samples
2 : 32 samples
3 : 64 samples
5:0
20
Target value for the AGC control loop, given in 2 dB steps.
Reset value corresponds to approximately 25% of the ADC
dynamic range in reception.
AGCTST2 (0x26) - AGC Test Register 2
Bit
Field Name
Reset
0
R/W
W0
Description
15:10 -
Reserved, write as 0
9:5
MED2HIGHGAIN[4:0]
9
R/W
MED2HIGHGAIN sets the difference in the receiver
LNA/MIXER gain from medium gain mode to high gain mode,
used by the AGC for setting the correct front-end gain mode.
4:0
LOW2MEDGAIN[4:0]
10
R/W
LOW2MEDGAIN sets the difference in the receiver
LNA/MIXER gain from low gain mode to medium gain mode,
used by the AGC for setting the correct front-end gain mode.
SWRS041B
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CC2420
FSTST0 (0x27) - Frequency Synthesizer Test Register 0
Bit
Field Name
Reset
0
R/W
W0
Description
15:12 -
Reserved, write as 0
11
VCO_ARRAY_SETTLE_LONG
0
R/W
When '1' this control bit doubles the time allowed for VCO
settling during VCO calibration.
10
VCO_ARRAY_OE
0
R/W
R/W
R
VCO array manual override enable.
VCO array override value.
9:5
4:0
VCO_ARRAY_O[4:0]
16
VCO_ARRAY_RES[4:0] 16
The VCO array result holds the register content of the most
recent calibration.
FSTST1 (0x28) - Frequency Synthesizer Test Register 1
Bit
Field Name
Reset
R/W
Description
15
VCO_TX_NOCAL
0
R/W
0 : VCO calibration is always performed when going to RX or
when going to TX.
1 : VCO calibration is only performed when going to RX or when
using the STXCAL command strobe
14
VCO_ARRAY_CAL_LONG
1
4
0
2
R/W
When ‘1’ this control bit doubles the time allowed for VCO
frequency measurements during VCO calibration.
0 : PLL Calibration time is 37 us
1 : PLL Calibration time is 57 us
13:10 VCO_CURRENT_REF[3:0]
R/W
R/W
R/W
The value of the reference current calibrated against during VCO
calibration.
9:4
3
VCO_CURRENT_K[5:0] 0
VCO current calibration constant. (Current B override value
when FSTST2.VCO_CURRENT_OE=1.)
VC_DAC_EN
Controls the source of the VCO VC node in normal operation
(TOPTST.VC_IN_TEST_EN=0):
0: Loop filter (closed loop PLL)
1: VC DAC (open loop PLL)
2:0
VC_DAC_VAL[2:0]
R/W
VC DAC output value
FSTST2 (0x29) - Frequency Synthesizer Test Register 2
Bit
Field Name
Reset
0
R/W
W0
Description
15
-
Reserved, write as 0.
VCO current calibration speed:
14:13 VCO_CURCAL_SPEED[1:0]
0
R/W
0: Normal
1: Double speed
2: Half speed
3: Undefined.
12
VCO_CURRENT_OE
VCO_CURRENT_O[5:0]
VCO_CURRENT_RES[5:0]
0
R/W
R/W
R
VCO current manual override enable.
VCO current override value (current A).
11:6
5:0
24
32
The VCO current result holds the register content of the most
recent calibration.
SWRS041B
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CC2420
FSTST3 (0x2A) - Frequency Synthesizer Test Register 3
Bit
Field Name
Reset
1
R/W
R/W
R/W
Description
15
CHP_CAL_DISABLE
CHP_CURRENT_OE
Disable charge pump during VCO calibration when set.
Charge pump current override enable
14
0
0 : Charge pump current set by calibration
1 : Charge pump current set by START_CHP_CURRENT
13
12
11
CHP_TEST_UP
CHP_TEST_DN
CHP_DISABLE
0
0
0
R/W
R/W
R/W
Forces the CHP to output "up" current when set
Forces the CHP to output "down" current when set
Set to manually disable charge pump by masking the up and
down pulses from the phase-detector.
10
PD_DELAY
0
R/W
Selects short or long reset delay in phase detector:
0: Short reset delay
1: Long reset delay
9:8
CHP_STEP_PERIOD[1:0]
2
R/W
The charge pump current value step period:
0: 0.25 us
1: 0.5 us
2: 1 us
3: 4 us
7:4
3:0
STOP_CHP_CURRENT[3:0]
13
R/W
R/W
The charge pump current to stop at after the current is stepped
down from START_CHP_CURRENT after VCO calibration is
complete. The current is stepped down periodically with intervals
as defined in CHP_STEP_PERIOD.
START_CHP_CURRENT[3:0] 13
The charge pump current to start with after VCO calibration is
complete. The current is then stepped down periodically to the
value STOP_CHP_CURRENT with intervals as defined in
CHP_STEP_PERIOD.
Also used for overriding the charge pump current when
CHP_CURRENT_OE=’1’
RXBPFTST (0x2B) - Receiver Bandpass Filters Test Register
Bit
Field Name
Reset
0
R/W
W0
Description
15
-
Reserved, write as 0.
14
RXBPF_CAP_OE
RXBPF_CAP_O[6:0]
0
R/W
R/W
R
RX bandpass filter capacitance calibration override enable.
RX bandpass filter capacitance calibration override value.
RX bandpass filter capacitance calibration result.
0: Minimum capacitance in the feedback.
1: Second smallest capacitance setting.
…
13:7
6:0
0
RXBPF_CAP_RES[6:0] 0
127: Maximum capacitance in the feedback.
FSMSTATE (0x2C) - Finite state machine information
Bit
15:6
5:0
Field Name
Reset
R/W
W0
R
Description
-
0
Reserved, write as 0.
FSM_CUR_STATE[5:0] 0
Provides the current state of the FIFO and Frame Control
SWRS041B
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CC2420
ADCTST (0x2D) - ADC Test Register
Bit
Field Name
Reset
R/W
Description
15
ADC_CLOCK_DISABLE
0
R/W
ADC Clock Disable
0 : Clock enabled when ADC enabled
1 : Clock disabled, even if ADC is enabled
14:8
7
ADC_I[6:0]
-
0
0
0
R
Read the current ADC I-branch value.
Reserved, write as 0.
W0
R
6:0
ADC_Q[6:0]
Read the current ADC Q-branch value.
DACTST (0x2E) - DAC Test Register
Reset
Bit
Field Name
R/W
Description
15
-
0
0
W0
Reserved, write as 0.
14:12 DAC_SRC[2:0]
R/W
The TX DACs data source is selected by DAC_SRC according
to:
0: Normal operation (from modulator).
1: The DAC_I_O and DAC_Q_O override values below.-
2: From ADC, most significant bits
3: I/Q after digital down mixing and channel filtering.
4: Full-spectrum White Noise (from CRC)
5: From ADC, least significant bits
6: RSSI / Cordic Magnitude Output
7: HSSD module.
This feature will often require the DACs to be manually turned on
in MANOR and TOPTST.ATESTMOD_MODE=4.
11:6
5:0
DAC_I_O[5:0]
DAC_Q_O[5:0]
0
0
R/W
R/W
I-branch DAC override value.
Q-branch DAC override value.
SWRS041B
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CC2420
TOPTST (0x2F) - Top Level Test Register
Bit
15:8
7
Field Name
-
Reset
0
R/W
W0
Description
Reserved, write as 0.
Enable BIST of the RAM
RAM_BIST_RUN
0
R/W
0 : RAM BIST disabled, normal operation
1 : RAM BIST Enabled. Result output to pin, as set in IOCFG1.
6
5
TEST_BATTMON_EN
VC_IN_TEST_EN
0
0
R/W
R/W
Enable test output of the battery monitor.
When ATESTMOD_MODE=7 this controls whether the ATEST2
in is used to output the VC node voltage (0) or to control the VC
node voltage (1).
4
ATESTMOD_PD
1
0
R/W
Powerdown of analog test module.
0 : Power up
1 : Power down
3:0
ATESTMOD_MODE[3:0]
When ATESTMOD_PD=0, the function of the analog test module
is as follows:
0: Outputs “I” (ATEST1) and “Q” (ATEST2) from RxMIX.
1: Inputs “I” (ATEST2) and “Q” (ATEST1) to BPF.
2: Outputs “I” (ATEST1) and “Q” (ATEST2) from VGA.
3: Inputs “I” (ATEST2) and “Q” (ATEST1) to ADC.
4: Outputs “I” (ATEST1) and “Q” (ATEST2) from LPF.
5: Inputs “I” (ATEST2) and “Q” (ATEST1) to TxMIX.
6: Outputs “P” (ATEST1) and “N” (ATEST2) from Prescaler. Must
be terminated externally.
7: Connects TX IF to RX IF and simultaneously the ATEST1pin
to the internal VC node (see VC_IN_TEST_EN).
8. Connect ATEST1(input) to ATEST2(output) through
single2diff and diff2single buffers, used for measurements on the
test-interface
RESERVED (0x30) - Reserved register containing spare control and status bits
Bit
Field Name
Reset
R/W
Description
15:0
RES[15:0]
0
R/W
Reserved for future use
TXFIFO (0x3E) – Transmit FIFO Byte register
Bit
Field Name
Reset
R/W
Description
7:0
TXFIFO[7:0]
0
W
Transmit FIFO byte register, write only. Reading the TXFIFO is
only possible using RAM read. Note that the crystal oscillator
must be running for writing to the TXFIFO.
RXFIFO (0x3F) – Receive FIFO Byte register
Bit
Field Name
Reset
R/W
Description
7:0
RXFIFO[7:0]
0
R/W
Receive FIFO byte register, read / write. Note that the crystal
oscillator must be running for accessing the RXFIFO.
SWRS041B
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CC2420
38 Test Output Signals
The two digital output pins CCA and SFD,
IOCFG1.SFDMUX. This is summarized in
can be set up to output test signals
defined
by IOCFG1.CCAMUX
and
CCAMUX
Signal output on CCApin
CCA
Description
0
1
2
Normal operation
ADC_Q[0]
ADC, Q-branch, LSB used for random number generation
DEMOD_RESYNC_LATE
High one 16 MHz clock cycle each time the demodulator
resynchronises late
3
LOCK_STATUS
Lock status, same as FSCTRL.LOCK_STATUS
Chip rate clock signal during transmission
Bit rate clock signal during transmission
Frequency synthesizer power down, active high
ADC power down, active high
4
MOD_CHIPCLK
5
MOD_SERIAL_CLK
FFCTRL_FS_PD
FFCTRL_ADC_PD
FFCTRL_VGA_PD
FFCTRL_RXBPF_PD
FFCTRL_LNAMIX_PD
FFCTRL_PA_P_PD
AGC_UPDATE
6
7
8
VGA power down, active high
9
Receiver bandpass filter power down, active high
Receiver LNA / Mixer power down, active high
Power amplifier power down, active high
10
11
12
High one 16 MHz clock cycle each time the AGC updates its gain
setting
13
14
15
16
17
18
19
20
21
22
23
24
VGA_PEAK_DET[1]
VGA Peak detector, gain stage 1
VGA Peak detector, gain stage 3
RF receiver front-end gain mode, bit 1
VGA gain setting, bit 1
VGA peak-detector reset sign, active low.
Reserved
VGA_PEAK_DET[3]
AGC_LNAMIX_GAINMODE[1]
AGC_VGA_GAIN[1]
VGA_RESET_N
-
-
Reserved
-
Reserved
-
Reserved
-
Reserved
CLK_8M
8 MHz clock signal output
XOSC16M_STABLE
16 MHz crystal oscillator stabilised, same as the status bit in Table
25
26
27
28
29
30
31
FSDIG_FREF
FSDIG_FPLL
FSDIG_LOCK_WINDOW
WINDOW_SYNC
CLK_ADC
Frequency synthesizer, 4 MHz reference signal
Frequency synthesizer, 4 MHz divided signal
Frequency synthesizer, lock window
Frequency synthesizer, synchronized lock window
ADC clock signal 1
ZERO
Low
ONE
High
Table 12. CCA test signal select table
SWRS041B
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CC2420
SFDMUX
Signal output on SFDpin
SFD
Description
0
1
2
Normal operation
ADC_I[0]
ADC, I-branch, LSB used for random number generation
DEMOD_RESYNCH_EARLY
High one 16 MHz clock cycle each time the demodulator
resynchronises early
3
LOCK_STATUS
MOD_CHIP
Lock status, same as FSCTRL.LOCK_STATUS
Chip rate data signal during transmission
Bit rate data signal during transmission
Frequency synthesizer power down, active high
ADC power down, active high
VGA power down, active high
Receiver bandpass filter power down, active high
Receiver LNA / Mixer power down, active high
Power amplifier power down, active high
VGA Peak detector, gain stage 0
VGA Peak detector, gain stage 2
VGA Peak detector, gain stage 4
RF receiver front-end gain mode, bit 0
VGA gain setting, bit 0
4
5
MOD_SERIAL_DATA_OUT
FFCTRL_FS_PD
FFCTRL_ADC_PD
FFCTRL_VGA_PD
FFCTRL_RXBPF_PD
FFCTRL_LNAMIX_PD
FFCTRL_PA_P_PD
VGA_PEAK_DET[0]
VGA_PEAK_DET[2]
VGA_PEAK_DET[4]
AGC_LNAMIX_GAINMODE[0]
AGC_VGA_GAIN[0]
RXBPF_CAL_CLK
-
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Receiver bandpass filter calibration clock
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
PD_F_COMP
FSDIG_FREF
FSDIG_FPLL
FSDIG_LOCK_WINDOW
WINDOW_SYNC
CLK_ADC_DIG
ZERO
Frequency synthesizer frequency comparator value
Frequency synthesizer, 4 MHz reference signal
Frequency synthesizer, 4 MHz divided signal
Frequency synthesizer, lock window
Frequency synthesizer, synchronized lock window
ADC clock signal 2
Low
ONE
High
Table 13. SFD test signal select table
SWRS041B
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CC2420
39 Package Description (QLP 48)
Note: The figure is an illustration only and not to scale.
Quad Leadless Package (QLP)
D
D1
E
E1
e
b
L
D2
E2
QLP 48
Min
6.9
7.0
7.1
6.65
6.75
6.85
6.9
7.0
7.1
6.65
6.75
6.85
0.18
0.3
0.4
0.5
5.05
5.10
5.15
5.05
5.10
5.15
0.5
Max
0.30
The overall packet height is 0.85 +/- 0.05
All dimensions in mm
The package is compliant to JEDEC standard MO-220.
SWRS041B
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CC2420
40 Recommended layout for package (QLP 48)
Note: The figure is an illustration only and not to scale. There are nine 14 mil diameter via
holes distributed symmetrically in the ground pad under the package. See also the CC2420
EM reference design.
40.1 Package thermal properties
Thermal resistance
Air velocity [m/s]
Rth,j-a [K/W]
0
25.6
40.2 Soldering information
Recommended soldering profile is according to IPC/JEDEC J-STD-020C.
SWRS041B
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CC2420
40.3 Plastic tube specification
QLP 7x7mm antistatic tube.
Tube Specification
Package
QLP 48
Tube Width
Tube Height
Tube Length
Units per Tube
43
2.2 +0.2/-0.1 mm
8.5 ± 0.2 mm
315 ± 1.25 mm
40.4 Carrier tape and reel specification
Carrier tape and reel is in accordance with EIA Specification 481.
Tape and Reel Specification
Package
Tape Width
Component
Pitch
Hole
Pitch
Reel
Diameter
Units per Reel
4000
QLP 48
16 mm
12 mm
4 mm
13 inch
41 Ordering Information
Chipcon Part
Number
TI Part Number
CC2420RTC
Description
Minimum Order
Quantity (MOQ)
CC2420-RTB1
CC2420-RTR1
CC2420Z-RTB1
Single-chip RF Transceiver. CC2420, QLP48 package, RoHS
compliant Pb-free assembly in tubes with 43 pcs per tube.
43 (tube)
CC2420RTCR
CC2420ZRTC
Single-chip RF Transceiver.. CC2420, QLP48 package, RoHS
compliant Pb-free assembly, T&R with 4000 pcs per reel.
4000 (tape and reel)
43 (tube)
Single-chip RF Transceiver including royalty for using TI’s
ZigBee Software Stack, Z-Stack™, in an end product. CC2420,
QLP48 package, RoHS compliant Pb-free assembly in tubes
with 43 pcs per tube.
CC2420Z-RTR1
CC2420ZRTCR
Single-chip RF Transceiver including royalty for using TI’s
ZigBee Software Stack, Z-Stack™, in an end product. CC2420,
QLP48 package, RoHS compliant Pb-free assembly, T&R with
4000 pcs per reel
4000 (tape and reel)
CC2420ZDK
CC2420ZDK-Pro
CC2420DBK
CC2420DK
CC2420ZDK
CC2420ZDK-Pro
CC2420DBK
CC2420DK
CC2420ZDK ZigBee Development Kit
CC2420ZDK-Pro ZigBee Development Kit Pro
CC2420DBK Demonstration Board Kit
CC2420DK Development Kit
1
1
1
1
1
CC2420EMK
CC2420EMK
CC2420DBK Evaluation Module Kit
SWRS041B
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CC2420
42 General Information
42.1 Document History
Revision
Date
Description/Changes
SWRS041b
2007-03-19 Slightly changed optimum load impedance on Page 9 and 19 to better describe the
Application circuit.
SWRS041a
2006-12-18 Updated ordering information.
Updated address information.
Typical data latency changed from 2 to 3 us.
Updates reflecting the programmable polarity of FIFO, FIFOP, SFD and CCA pins.
Clarification relating to VREG_EN as digital input.
BATT_OK changed to BATTMON_OK for consistency.
MANFIDH.VERSIONregister, reset value changed to ”current version is 3”.
Added reset values for several registers.
Some typographical changes.
Removed Chipcon specific Disclaimer, Trademarks and Life Support Policy sections.
SWRS041
(1.4)
2006-04-06 Ordering part number changed from CC2420-RTB2 and CC2420-RTR2 to CC2420Z-
RTB1 and CC2420Z-RTR1 respectively.
1.3
2005-10-03 Important: New recommended setting for RXBPF_LOCURin RXCTRL1 (0x17)use 1
instead of reset value 0.
Updated address information.
Added new balun circuit with transmission lines in section Application Circuit.
Updated electrical specifications with measured data on CC2420 EM with new balun.
Updated values and figure for suggested application circuit with folded dipole
antenna.
Corrected values for capacitors in Table 2, discrete balun.
Added data latency figure in receiver specification.
Updated crystal oscillator start up time.
Updated PLL loop filter bandwidth.
Updated adjacent channel rejection figures.
Updated current consumption for RX mode.
Typographical errors corrected in text and figures.
Removed comment about tuning capacitor for crystal oscillator.
Added statement that RAM access shall not be used for FIFO access.
Added more details about RSSI.
Clarified the interpretation of a programmed synchronisation word.
Updated purchasing information.
Updated soldering standard.
Added chapter numbering and split table for electrical specifications for readability.
Gathered and added information related to pin configurations in section 13.
Included TX_UNDERFLOW and RX_UNDERFLOW in state diagram.
Disclaimer updated to include Z-stack TM information.
Product status changed to “Full Production”.
SWRS041B
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CC2420
Revision
Date
Description/Changes
1.2
2004-06-09 Output power range: 24 dB (was 40 dB).
Deleted option for single ended external PA.
Adjacent channel rejection corrected to 46 dB for + 5MHz (was 39 dB), 39 dB for –5
MHz (was 46 dB) 58 dB for +10 MHz (was 53 dB) and 55 dB for-10 MHz (was 57 dB).
“image channel” deleted in text for In band spurious reception.
Revision for reference [1] updated.
CSMA-CA added to abbreviations.
Schematic view of the IEEE 802.15.4 Frame Format corrected, address field 0 to 20
bits.
Changed blocking specifications to relate to EN 300 440 class 2.
Updated addresses for Chipcon offices.
Added section Operating Conditions.
Section RAM access: A6:0 (LSB).
IOCFG0.BCN_ACCEPTbit added and described in section Address recognition and
the IOCFG0register.
The previous IDLE mode has been renamed to power down to be consistent with
other Chipcon data sheets. Three power modes defined: Voltage regulator off (OFF),
Power down (PD) (Voltage regulator enabled), IDLE (XOSC running) and used
throughout the document.
Default TXMIXBUF_CUR[1:0]in table for TXCTRLset to 2.
Added information: compliance with EN 300 328 og EN 300 440 (Class 2).
Added more information about FIFOPin section Receive mode.
Removed text about SO programmable pull up from entire document.
In Voltage regulator section of Electrical Specifications: voltage regulator may only
supply CC2420.
MANFIDH.VERSIONregister, changed to ”current version is 2”.
Included package height in package drawing.
Included layout drawing for package.
Power supply pins defined clearer in Absolute maximum ratings.
Third harmonic level corrected to –51dBm in Electrical specifications, second
harmonic to –37dBm.
Table with Crystal oscillator component values corrected.
Link to reference [3] corrected.
Corrected spelling grammar and references to tables and figures.
Figure showing SmartRF Studio user interface included.
Added figure to describe pin activity during RXFIFO read out.
Added description on how to connect pins when not using internal regulator.
1.1
1.0
2004-03-22 Application circuits: Pin 20 and pin 37 connected to 1.8 V from VREG_OUT.
IOCFG0.SO_PULLUPdeleted.
Added document history table.
2003-11-17 Initial release.
42.2 Product Status Definitions
Data Sheet Identification
Product Status
Definition
Advance Information
Planned or Under
Development
This data sheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
Engineering Samples This data sheet contains preliminary data, and
and First Production
supplementary data will be published at a later date.
Chipcon reserves the right to make changes at any
time without notice in order to improve design and
supply the best possible product.
No Identification Noted
Obsolete
Full Production
This data sheet contains the final specifications.
Chipcon reserves the right to make changes at any
time without notice in order to improve design and
supply the best possible product.
Not In Production
This data sheet contains specifications on a product
that has been discontinued by Chipcon. The data
sheet is printed for reference information only.
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43 Address Information
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44 TI Worldwide Technical Support
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