Texas Instruments Computer Hardware TVP5154EVM User Manual

TVP5154EVM  
User's Guide  
Literature Number: SLEU069A  
February 2006Revised July 2006  
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Contents  
1
2
Functional Description................................................................................................. 6  
1.1  
Description Overview ............................................................................................ 6  
Board Level Description .............................................................................................. 7  
2.1  
2.2  
2.3  
2.4  
Test Points and Jumpers........................................................................................ 7  
Common Board Interface ....................................................................................... 8  
Video Input Description.......................................................................................... 8  
Video Output Description ....................................................................................... 8  
3
4
5
6
7
8
System-Level Description ............................................................................................ 9  
Required Hardware and Equipment............................................................................... 9  
Hardware Setup .......................................................................................................... 9  
Software Installation .................................................................................................. 10  
WinVCC Quick Start................................................................................................... 10  
WinVCC in Depth....................................................................................................... 13  
8.1  
8.2  
8.3  
8.4  
8.5  
8.6  
Starting WinVCC................................................................................................ 13  
WinVCC Configuration Dialog Box ........................................................................... 14  
I2C System Test................................................................................................. 14  
Real-Time Polling............................................................................................... 15  
Main Menu....................................................................................................... 16  
TVP5154 Property Sheets..................................................................................... 23  
9
Programming the TMS320DM642................................................................................. 25  
9.1  
Development and Purpose of DM642 Code ................................................................ 25  
Details of the DM642 Code and Control Registers ........................................................ 26  
9.2  
10  
11  
Troubleshooting........................................................................................................ 33  
10.1 Troubleshooting Guide......................................................................................... 33  
10.2 Corrective Action Dialogs...................................................................................... 35  
TVP5154EVM Schematics........................................................................................... 37  
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Table of Contents  
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List of Figures  
1
TVP5154EVM Block Diagram.............................................................................................. 7  
Anti-Aliasing Filter Selection................................................................................................ 8  
TVP5154EVM System-Level Block Diagram............................................................................. 9  
WinVCC – I2C Configuration Screen .................................................................................... 11  
Real-Time Polling Dialog .................................................................................................. 12  
Decoder I2C Write and Read Enable .................................................................................... 12  
WinVCC – Main Screen ................................................................................................... 12  
WinVCC – System Initialization .......................................................................................... 13  
WinVCC Multiple Occurrences Error Message......................................................................... 13  
WinVCC I2C Address Configuration ..................................................................................... 14  
I2C System Failure ......................................................................................................... 15  
Real-Time Polling Dialog .................................................................................................. 16  
WinVCC – Main Screen ................................................................................................... 16  
Decoder I2C Write and Read Enable .................................................................................... 17  
System Initialization........................................................................................................ 18  
TVP5154 Register Map Editor............................................................................................ 20  
7311 Encoder Module Register Map Editor ............................................................................ 21  
Generic I2C Register Map Editor ......................................................................................... 22  
Memory Map Editor ........................................................................................................ 22  
TVP5154 Property Sheets ................................................................................................ 24  
DM642 Control Window ................................................................................................... 26  
I2C System Failure Dialog Box ........................................................................................... 35  
Corrective Action Dialog Box ............................................................................................. 35  
Corrective Action Required ............................................................................................... 36  
Corrective Action Required ............................................................................................... 36  
I2C Error ..................................................................................................................... 37  
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List of Figures  
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List of Tables  
1
I2C Address Selection Jumpers (I2CSEL1, JP9 and I2CSEL2, JP10)................................................ 7  
Power-Down-Mode Selection Jumper (PDN, JP11) .................................................................... 7  
Main Menu Summary ...................................................................................................... 16  
TVP5154 Register Map Editor Controls................................................................................. 21  
Memory Map Editor Controls ............................................................................................. 23  
Use of Property Sheet Controls .......................................................................................... 25  
Property Sheet Button Controls .......................................................................................... 25  
DM642 Control Window Controls ........................................................................................ 27  
DM642 Virtual I2C Register Map ......................................................................................... 27  
Decoder 1 Register ........................................................................................................ 28  
Decoder 2 Register ........................................................................................................ 29  
Decoder 3 Register ........................................................................................................ 30  
Decoder 4 Register ........................................................................................................ 30  
Decoder 1 Input Format Register ........................................................................................ 31  
Decoder 2 Input Format Register ........................................................................................ 31  
Decoder 3 Input Format Register ........................................................................................ 32  
Decoder 4 Input Format Register ........................................................................................ 32  
LED Control Register ...................................................................................................... 32  
Flash Major Version Register............................................................................................. 32  
Flash Minor Version Register............................................................................................. 32  
TVP5154EVM Troubleshooting........................................................................................... 33  
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21  
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List of Tables  
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User's Guide  
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TVP5154EVM User's Guide  
1
Functional Description  
The TVP5154EVM evaluation module is a printed circuit board designed for evaluation of the TVP5154  
quad video decoder. The board includes the TMS320DM642 digital signal processor (DSP) and is  
designed with a 120-pin connector, which allows a connection to multiple backends; the evaluation module  
(EVM) is shipped with a professional encoder module. The board is designed to provide ease of use, while  
allowing full evaluation of the video decoder.  
1.1 Description Overview  
The TVP5154EVM uses the PC parallel port to emulate the I2C bus, which provides communication with  
the TVP5154 video decoder, DM642, and the video encoder. The Windows™ Video Control Center  
(WinVCC) application software that communicates with the devices via the I2C is provided on the EVM  
CD-ROM.  
The analog video inputs supported by the TVP5154EVM include composite video and S-video. More detail  
about the video inputs is discussed in section 2.3 Video Input Description. In general, the video decoder  
converts the analog video input signal into digital component data. This data and the associated clocks  
from the video decoder are sent to the DM642, which provides various image capture and display modes.  
The DM642 is setup in I2C slave mode and is controlled through virtual I2C registers. The video encoder  
then converts the digital data from the DM642 back into analog video. The analog video outputs supported  
by the EVM include composite video, S-video, and component video. These are all output simultaneously.  
To experiment with the programmable features of the TVP5154 video decoder and the video encoder, the  
parallel port of the TVP5154 is connected to the parallel port of a PC. WinVCC, a Windows-compatible  
application provides the user interface for performing register-level and high-level control of the TVP5154  
video decoder and the video encoder.  
Code Composer Studio is a trademark of Texas Intruments.  
All other trademarks are the property of their respective owners.  
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Board Level Description  
2
Board Level Description  
The TVP5154EVM consists of the TVP5154EVM module and the encoder EVM module. A 4-row 120-pin  
connector connects the boards. The block diagram of the EVM set is shown in Figure 1.  
Figure 1. TVP5154EVM Block Diagram  
2.1 Test Points and Jumpers  
The TVP5154EVM was designed with test points and jumpers to help in evaluation and troubleshooting.  
Each jumper is set by default in its preferred state for the TVP5154EVM. There are test points for SCL,  
SDA, 3.3 V, and 1.8 V. All digital video data for each decoder core are brought out to a dual-row header,  
which allows easy hookup to test equipment. The I2C address selection is made with two shunt jumpers,  
which are only read after a reset or at power up. The default address is 0xB8. If the address needs to be  
changed, the TVP5154 must receive a reset.  
Table 1. I2C Address Selection Jumpers  
(I2CSEL1, JP9 and I2CSEL2, JP10)  
JP9  
2-3  
1-2  
2-3  
1-0  
JP10  
2-3  
I2C ADDRESS  
0xB8  
2-3  
0xBA  
1-2  
0xBC  
1-2  
0xBE  
Table 2. Power-Down-Mode Selection Jumper  
(PDN, JP11)  
PWDN  
1-2  
2-3  
Normal operation  
Power down  
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Board Level Description  
Note: If the I2C address is changed on either the TVP5154 board or the encoder board while the  
TVP5154EVM is powered up, that device will not recognize the new I2C address. The reset  
button on the TVP5154EVM must be pressed and WinVCC must be reconfigured for the new  
I2C address.  
2.2 Common Board Interface  
The TVP5154EVM uses a 4-row 120-pin connector to share common signals and the 5-V power supply  
between the boards. This connection allows multiple backends to be connected to the TVP5154EVM. The  
EVM package is shipped with an encoder module. This connector shares all digital video bits (Y[7:0]), all  
video clocks (VS, HS, GLCO/FID, and DATACLK), 5 V, ground, I2C bus (SCL and SDA), and reset.  
2.3 Video Input Description  
The TVP5154EVM decoder has an analog input channel that accepts two video inputs for each decoder  
core. The decoder supports a maximum input voltage range of 0.75 V, therefore, an attenuation of  
one-half is needed for most input signals with a peak-to-peak variation of 1.5 V. The parallel termination  
before the input to the device is 75 . The two analog inputs can be connected as either two selectable  
composite video inputs, or one S-video input.  
The TVP5154EVM allows the user to have up to two composite inputs or one S-video input for each of the  
four-channels. The EVM software sets up and controls this input selection. The S-video input uses two  
connectors, one for the luma channel and one for the chroma channel.  
The EVM has a resistor network on each of the inputs. These networks attenuate the signal and allow a  
75-resistor to ground to be placed after the anti-alias filter for termination.  
Each input has an anti-alias filter that can be in-circuit or bypassed by jumpers (JP1–JP8). To select the  
filter, the shunts need to be positioned to short positions 1-3 and 2-4. To bypass the filter, the shunts need  
to be moved to short positions 1-2 and 3-4 as shown in Figure 2. The boards are shipped with the filter  
bypassed.  
Figure 2. Anti-Aliasing Filter Selection  
2.4 Video Output Description  
The 8-bit digital video outputs of the TVP5154 are routed to the four 32-pin headers (H2–H5), the DM642,  
and finally to the 120-pin edge connector along with all video clocks on the TVP5154 module. The  
encoder module connects to the 120-pin connector, and is capable of receiving digital video with or  
without embedded syncs. The analog outputs of the encoder module are composite, S-video, and  
component. For the user’s convenience, all of these outputs come out of the encoder module  
simultaneously.  
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System-Level Description  
3
System-Level Description  
A system-level block diagram incorporating the TVP5154 is shown in Figure 3. Typical  
commercially-available test equipment is also shown. The primary features of this configuration are:  
Power is provided by a single 5-V power supply provided with the EVM and is shared between both  
modules via the 120-pin connector.  
Supported analog inputs include composite video and S-video.  
Re-encoded composite video and S-video are output via the encoder module.  
Component (YPbPr) video is output via the encoder module.  
I2C bus initializes the video devices via a PC parallel port.  
The TVP5154 video decoder performance parameters may be measured with a video analyzer.  
Figure 3. TVP5154EVM System-Level Block Diagram  
4
Required Hardware and Equipment  
The required hardware and equipment necessary to use the TVP5154EVM are:  
TVP5154EVM (provided)  
Universal 5-V power supply (provided)  
Parallel cable (provided)  
Windows-based PC with CD-ROM drive and Win95™ or later  
Composite or S-video cables for inputs  
Composite, S-video, or component cable for output  
Video sources (security camera, pattern generator, Quantum generator, DVD player, etc.)  
Display monitor that supports composite, S-video, or component video input  
5
Hardware Setup  
Figure 1 shows the TVP5154EVM layout and indicates the location of the power supply and the  
appropriate connectors. All connectors are labeled according to their function. To prepare the EVM for  
evaluation, connect the following:  
1. TVP5154 module to encoder module  
2. Parallel port cable from TVP5154EVM to the PC  
3. Analog video sources to TVP5154EVM inputs  
4. Analog video out from TVP5154EVM to monitor  
5. 5-V power supply to the dc jack on the TVP5154 board. A green LED on each board should now be lit.  
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Software Installation  
The system comes with the anti-alias filters bypassed. To connect the filters, you must rotate the  
appropriate jumpers (JP1–JP8) as described in section 2.3.  
The I2C slave address can be selected with jumpers JP9 and JP10. There are four possible addresses:  
B8, BA, BC, and BE. The default setting for these jumpers is for the shunt to short pins 2-3, which selects  
0xB8. These are connected to pins 117 and 118, which are read at power up. If you move both the  
jumpers to positions 1-2 and reset the board, the video decoder now responds to I2C slave address 0xBE.  
If you choose to change the address, you must exit, restart WinVCC, and configure the software to use  
the new I2C slave address.  
6
Software Installation  
WinVCC is a Windows application that uses the PC parallel port to emulate I2C, providing access to each  
device on the I2C bus. WinVCC makes use of CMD files, a text editable file that allows preset video  
setups to be programmed easily.  
This feature allows the user to easily set multiple I2C registers with the press of a button. WinVCC also  
has property sheets for the TVP5154, which allows the user to control the I2C registers with a GUI.  
All necessary software for the TVP5154EVM is provided on the enclosed CD. Perform the following steps  
to install WinVCC:  
1. Explore the provided TVP5154EVM Software CD.  
2. Install Port95NT.exe. This is the parallel port driver used by WinVCC. This driver must be installed and  
the PC must be rebooted before WinVCC operates correctly. This does not affect normal parallel port  
operation.  
3. Install Setup.exe. Click Next at all prompts and click Finish to complete the installation process. This  
installs WinVCC onto the PC. No reboot is required.  
4. Run WinVCC.exe.  
Note: A shortcut to WinVCC should now be available on the desktop. WinVCC and additional  
TVP5154-related documentation can also be found at StartProgramsTVP5154EVM  
Software.  
7
WinVCC Quick Start  
Perform the following steps in order to see a video output from the TVP5154EVM.  
1. Once WinVCC is executed, the WinVCC Configuration screen appears, as shown in Figure 4. This  
dialog box configures the I2C bus. Next to VID_DEC, select the TVP5154 and ensure the I2C address  
is set to 0xB8 (default setting on EVM.) This must match the I2C ADDR jumper on the TVP5154 board.  
2. Next to VID_ENC, select the 7311 Encoder and ensure the I2C address is set to 0x54 (default setting  
on EVM.) This must match the I2C ADDR jumper on the encoder board.  
Note: If WinVCC is running and the TVP5154 or encoder board I2C address is changed, power  
must be cycled on the EVM.  
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WinVCC Quick Start  
Figure 4. WinVCC – I2C Configuration Screen  
3. Ensure that all other boxes are selected as “Not Used” and that all program options buttons are set to  
ENABLE. Click OK.  
4. If there are no I2C communication issues, the Real-Time Polling dialog window displays next as shown  
in Figure 5. If there are I2C issues, an I2C Test Report box displays. Completely exit out of WinVCC,  
double-check the parallel port cable connections, I2C address settings, cycle power on the  
TVP5154EVM, and re-run WinVCC.  
5. When using the TVP5154 EVM with a composite output from the 7311 encoder, it is required to disable  
auto-switch polling in the Real-Time Polling dialog box by clicking on the ENABLED button. Click OK  
and then the Main Control Window is seen, as shown in Figure 7.  
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WinVCC Quick Start  
Figure 5. Real-Time Polling Dialog  
6. The TVP5154 I2C Write Enable(s) and Read Enable pop-up window is displayed as shown in Figure 6.  
This is used to select which decoder or decoders (any combination of all four) will receive I2C Write  
commands, and which decoder (only one) will receive I2C Read commands. Decoder 1 is Enabled by  
default; enable the other three decoders by clicking on each decoder’s enable button.  
Figure 6. Decoder I2C Write and Read Enable  
7. Load the provided Initialization command (CMD) file into WinVCC by clicking on ToolsSystem  
InitializationBrowse. The default directory is C:\Program Files\Texas  
Instruments\TVP5154EVM\Initialization.  
Figure 7. WinVCC – Main Screen  
8. In the System Initialization Window (see Figure 8), click the “TVP5154 ROM – Initialize for NTSC...” or  
“TVP5154 ROM – Initialize for PAL...” dataset in the window and then click the PROGRAM Device(s)  
Using Selected Dataset button to initialize the TVP5154EVM.  
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WinVCC in Depth  
Figure 8. WinVCC – System Initialization  
9. With video sources provided at the BNC connectors and the EVM output connected to a monitor, video  
from the source connected to CH1 should be viewable on the display monitor.  
10. The other datasets in the command file are provided to demonstrate examples of 5154 scaling  
performance. Refer to the TVP5154 data sheet (SLES163) or Scaler application report for more details  
on programming the TVP5154 scaler. The DM642 settings can be controlled by using the DM642  
Control Window, which is found by clicking on ToolsDM642 Control. Refer to Chapter 9 for details on  
programming the DM642 through this window or through the Generic I2C registers.  
8
WinVCC in Depth  
The following sections describe how to use Windows™ Video Control Center (WinVCC) in depth. It  
discusses various features and screens that the user may encounter while evaluating the TVP5154EVM.  
8.1 Starting WinVCC  
The Port95NT parallel port driver must be installed before using WinVCC. WinVCC may be started by  
clicking on StartAll ProgramsTVP5154EVM SoftwareWinVCC.  
If the dialog box shown in Figure 9 is displayed, it means one of two things:  
WinVCC did not run to completion the last time it ran. In this case, click OK to exit the program and  
restart WinVCC.  
There is more than one instance of WinVCC running at the same time. In this case, click OK to exit the  
program. Then, press CTRL-ALT-DELETE to bring up the Task Manager. Select and click End Task  
on all occurrences of WinVCC or WinVCC CONFIGURATION. Then restart WinVCC.  
Figure 9. WinVCC Multiple Occurrences Error Message  
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WinVCC in Depth  
8.2 WinVCC Configuration Dialog Box  
The WinVCC Configuration dialog box (see Figure 10) should now be visible. This dialog box configures  
the I2C bus on the TVP5154EVM. All settings from this dialog box are stored in the Windows registry and  
are restored the next time the program is started. After initial installation, VID_DEC is set to TVP5154 and  
VID_ENC is set to 7311 Encoder.  
The I2C slave address for each device must match the I2C slave address selected by jumpers on the  
TVP5154EVM. These jumpers are set by the factory to use 0xB8 for the TVP5154 and 0x54 for the  
Encoder. It is also important to select the correct Specific Device type for the video decoder. TVP5154 and  
7311 Encoder must be selected for this EVM.  
All Program Options must be enabled. Disabling these options is only required if debugging a problem  
with the I2C bus.  
Clicking OK begins I2C communication with the selected devices.  
Figure 10. WinVCC I2C Address Configuration  
8.3 I2C System Test  
The I2C system test of selected registers runs immediately after closing the WinVCC Configuration dialog  
box with OK (unless the I2C system test program options button was disabled).  
If the I2C system test passes, only a PASS message appears. If the test failed, a dialog box like the one  
shown in Figure 11 appears. See Section 10, Troubleshooting, for details on how to resolve this issue.  
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WinVCC in Depth  
The I2C system test can be run at anytime by clicking Run System I2C Test in the Tools menu.  
Figure 11. I2C System Failure  
8.4 Real-Time Polling  
Real-time polling provides polling functions that execute continuously in the background, when enabled via  
the Real-Time Polling dialog. There are two polling functions. The function that applies to the TVP5154 is  
VIDEO-STANDARD AUTO-SWITCH POLLING.  
When the TVP5154 detects a change in the input video standard, it automatically switches to operation in  
the detected standard (which includes all necessary I2C register initialization) for proper decoding of the  
input video. To enable auto-switch on the TVP5154, the Set Video Standard register must be set to  
auto-switch mode (Reg 0x28 = 0x00).  
If the WinVCC auto-switch polling function is enabled, the detected video standard status from the  
TVP5154 is polled until a change in the input video standard (or in the TVP5154 sampling mode) is  
detected. When a change is detected, the video encoder is reprogrammed as needed for the detected  
standard. Using this feature, the video source can change its video standard and the system displays  
using the new standard, without user intervention.  
When using the TVP5154 EVM with the DM642 and a composite output from the 7311 encoder, it is  
required to disable auto-switch polling by clicking on the ENABLED button in the Real-Time Polling dialog  
box as shown in Figure 12.  
The real-time polling dialog can also be accessed once WinVCC is up and running by clicking Real-Time  
Polling in the Tools menu.  
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WinVCC in Depth  
Figure 12. Real-Time Polling Dialog  
8.5 Main Menu  
After closing the real-time polling dialog, the main menu is displayed as shown in Figure 13. The menus,  
which are used to operate WinVCC, are File, Edit, Tools, Window, and Help. The File menu’s only function  
is Exit, which terminates the program. Table 3 summarizes the main menu contents.  
Figure 13. WinVCC – Main Screen  
Table 3. Main Menu Summary  
MENU  
File  
CONTENTS  
Exit  
Edit  
Register Map  
TVP5154  
7311 Encoder Module  
Generic I2C  
Memory Map  
TVP5154  
7311 Encoder Module  
Property Sheets  
TVP5154  
7311 Encoder Module  
Tools  
System Initialization  
Real-time Polling  
TV Tuner Control (FQ12xx series only)  
Multiple-Byte I2C Transfers  
Set I2C Bit Rate  
Run System I2C Test  
Run Continuous I2C Test  
Read VBI FIFO  
Capture Live VBI Data  
DM642 Control  
Window Allows selection of the active window. Multiple windows can be open at the same time.  
Help Displays program version  
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WinVCC in Depth  
The TVP5154 I2C Write Enable(s) and Read Enable pop-up window is displayed as shown in Figure 14.  
This is used to select which decoder or decoders (any combination of all four) will receive I2C Write  
commands, and which decoder (only one) will receive I2C Read commands. Decoder 1 is Enabled by  
default; enable the other three decoders by clicking on each decoder’s enable button.  
Figure 14. Decoder I2C Write and Read Enable  
System Initialization  
8.5.1  
Clicking System Initialization in the Tools menu displays the dialog box shown in Figure 15. This dialog  
box provides the means for initializing the TVP5154 decoder(s) and/or video encoder for a particular video  
mode, as well as programming settings for the DM642 through the Generic I2C registers. The details of  
the initialization are contained in the command file (with a CMD file extension).  
The command file is loaded using the Browsebutton. Once the command file is opened, a text list  
displays descriptions of the individual datasets contained within the command file.  
Click once on the desired dataset description to select it. Click the Program Device(s) Using Selected  
Dataset button to run the selected dataset, which loads the devices via the I2C bus. When the device  
initialization has completed, the status indicator reads Ready.  
Note: If Ready does not display, the devices are not initialized and the I2C bus is not  
communicating. See Chapter 10, Troubleshooting, for possible solutions.  
Click the OK button to close the dialog box. Each time the System Initialization dialog box is closed, the  
initialization file pathname and the dataset selection number are saved in the Windows registry to allow  
these settings to be retained for the next time WinVCC runs.  
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WinVCC in Depth  
Figure 15. System Initialization  
8.5.1.1  
Adding a Custom Dataset  
After programming the EVM via the System Initialization tool using the factory-supplied command file, you  
can customize the device register settings to fit your needs. Perform the following steps to save your  
custom settings:  
1. Reopen the System Initialization dialog box via the Tools menu.  
2. Click the Append Current Device Settings to Command File button. A dialog box requesting a  
description of the new dataset appears.  
3. Optionally, click the drop-down box and select one of the existing descriptions.  
4. Modify the description text or type your own description.  
5. Click OK. All nondefault register values from the TVP5154, DM642, and encoder are appended to the  
current command file as an additional dataset.  
Now, you can select your custom dataset and send it with a press of the Programbutton.  
By using the same procedure above with the Replace Selected Dataset with Current Device Settings  
button you can overwrite an existing dataset with the current settings.  
Note: If editing the command file (.CMD) using a standard editor, the file must be saved as plain  
text.  
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8.5.1.2  
Command Files  
The command file is a text file that can be generated using any common editor; however, it must be saved  
as plain text. Command files are especially useful for quickly switching between the various system  
configurations. These .CMD files are unrelated to the typical Windows .CMD files.  
A default command file is provided on the CD. This command file contains many examples of the desired  
setups. This command file is located at:  
c:\Program Files\Texas Instruments\TVP5154EVM\Initialization\  
A command file can contain up to 250 datasets. A dataset is a set of register settings to initialize the  
TVP5154 decoder, 7311 encoder, and/or DM642 for a particular video mode. Each dataset includes a  
description that is displayed in one row of the dataset descriptions list. The register settings may be  
located in the command file itself and/or may be stored in separate include file(s) (with an .INC file  
extension) and be included into the command file using the INCLUDE statement.  
8.5.1.3  
Example Command File  
An example of one dataset within a command file is shown below.  
BEGIN_DATASET  
DATASET_NAME,”TVP5154, Auto–switch, Stable Sync, Fast-lock, 656 Out”  
// Initialize video encoder using an include file  
INCLUDE, EncoderNTSC656_RTC.INC  
// Program TVP5154 registers  
WR_REG,VID_DEC,1,0x7F,0x00 // Reset 5154 microprocessor  
WR_REG,VID_DEC,1,0x03,0x0D // Enable YCbCr outputs and syncs  
WR_REG,VID_DEC,1,0x15,0x81 // Enable Stable Sync mode  
WR_REG,VID_DEC,1,0x02,0x80 // Enable Fast-lock mode  
END_DATASET  
Each command file may contain individual write-to-register (WR_REG) commands.  
The comment indicator is the double-slash //.  
The command file is not case sensitive and ignores all white-space characters.  
All numbers can be entered as hexadecimal (beginning with 0x) or as decimal.  
Every dataset in a command file begins with BEGIN_DATASET and ends with END_DATASET. The  
maximum number of datasets is 250.  
The dataset text description is entered between double quotes using the DATASET_NAME command.  
The enclosed text can be up to 128 characters in length. This text appears in the System Initialization  
dialog box when the command file is opened.  
The INCLUDE command inserts the contents of an include file (with an .INC file extension) in-line in  
place of the INCLUDE command. Therefore, the include file must not contain the BEGIN_DATASET,  
END_DATASET, and DATASET_NAME commands.  
Note: All included files must be located in the same directory as the command (CMD) file.  
The write-to-register command is written as:  
WR_REG, <DeviceFamily>, <Number of data bytes (N)>, <subaddress>, <Data1>,, <DataN>  
or  
WR_REG, <Literal slave address>, <Number of data bytes (N)>, <subaddress>, <Data1>,, <DataN>  
The valid device family mnemonics are:  
VID_DEC for the video decoders  
VID_ENC for the video encoders  
THS8200 for the THS8200 device  
WinVCC translates the device family mnemonic to the slave address that was selected in the WinVCC  
Configuration dialog box upon program startup. This eliminates having to edit command files if the  
alternate slave address must be used.  
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If the literal slave address method is used, the slave address entered is used directly. This method is  
normally used for programming the video encoder.  
The slave address 0x40h is used to access the DM642.  
A delay may be inserted between commands using the WAIT command, which is written as:  
WAIT,<# milliseconds>  
8.5.2  
Register Editing  
The next section describes the five available modes of register editing: TVP5154 Register Map editor,  
7311 Encoder Module Register Map editor, Generic I2C Register Map editor, TVP5154 memory map  
editor, and TVP5154 Property Sheets. Each of these functions can be selected from the Edit menu.  
8.5.2.1  
Register Map Editor  
The TVP5154 Register Map editor (see Figure 16) allows the display and editing of the entire used  
register space of the device within a simple scrolling text box. To open this, click on Edit Register Map in  
the Edit menu and click on the device type to edit. Table 4 describes how to use each of the controls in  
the TVP5154 Register Map editor.  
Figure 16. TVP5154 Register Map Editor  
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Table 4. TVP5154 Register Map Editor Controls  
CONTROL  
DEFINITION  
Register Window Scrolling text box that displays the address and data for the I2C registers that are defined for the device  
Contains the I2C subaddress that will be accessed using the Write and Read buttons. Clicking on a row selects  
an address, which then appears in the address edit box.  
Address Edit Box  
NOTE: After clicking on a row, the Data Edit box contains the data that was in the register window. The device  
has not yet been read.  
The address up/down arrows are used to jump to the next/previous subaddress that is defined for the device. If  
an address is not defined for the device, it can still be accessed by typing the subaddress in the Address Edit  
box.  
Data Edit Box  
Write Button  
Contains the data which will be written to, or was read from, the I2C subaddress.  
The data up/down arrows increment/decrement the data value by 1.  
Writes the byte in the Data Edit box to the address in the Address Edit box.  
The I2C register is written to whether or not the data is different from the last time the register was read.  
Reads the data from the address in the Address Edit box into the Data Edit box and the register window.  
Reads all defined readable registers from the device and updates the register window.  
Converts all values in the register window and address and data edit boxes to hexadecimal.  
Converts all values in the register window and address and data edit boxes to decimal.  
Closes the dialog.  
Read Button  
Read All Button  
Hex Button  
Dec Button  
Close Button  
NOTE: Multiple edit register map windows can be open at the same time (one for each device). Use the  
Window menu to navigate.  
Causes subsequent write, read, or read all operations to be performed N times. N is entered as a decimal  
number from 1 to 999.  
Loop Count  
8.5.2.2  
Encoder Module Register Map Editor  
The Encoder Module Register Map editor (see Figure 17) allows the display and editing of the video  
encoder registers. This editor works like the TVP5154 Register Map editor.  
To open this, click on Register Map in the Edit menu and click on 7311 Encoder Module.  
Figure 17. 7311 Encoder Module Register Map Editor  
8.5.2.3  
Generic I2C Register Editor  
The Generic I2C Register editor (see Figure 18) allows the display and editing of any device on the I2C  
bus. This editor works like the TVP5154 Register Map editor, except that the I2C slave address must be  
entered and the Read All button is disabled.  
To open this, click on Register Map in the Edit menu and then click on Generic I2C.  
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The DM642 I2C registers can be edited using I2C sub-address 0x40. See Section 9 for details about the  
DM642 registers.  
The video encoder module registers can be edited using I2C sub-address 0x54 (default) or 0x56 if the  
alternate slave address is being used.  
Figure 18. Generic I2C Register Map Editor  
8.5.2.4  
Memory Map Editor  
The memory map editor (see Figure 19) allows the display and editing of the data memory and hardware  
registers of the device, such as the scaler setting registers.  
To open this, click on Memory Map in the Edit menu and click on the device type to edit. The operation of  
the memory map editor controls are explained in Table 5.  
Figure 19. Memory Map Editor  
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Table 5. Memory Map Editor Controls  
CONTROL  
DEFINITION  
Base Address Selector  
Address Offset Edit Box  
Data Edit Boxes  
The hardware registers use a 10-bit address internally. The base address selector allows quick entry  
of the base address. The list contains base addresses for the major functional blocks of the  
TVP5154.  
Contains the lowest byte of the 10-bit internal address. The full 10-bit address is formed by adding  
the base address to the address offset. The address up/down arrows increment/decrement the  
address offset by 1.  
Contains the 16-bit data word that is written to or read from the register address. The LSB data is at  
the lowest address. The data is written/read LSB first. The data up/down arrows  
increment/decrement the data value by 1.  
Write Button  
Read Button  
Writes the (2) bytes in the data edit boxes starting at the 10-bit register address BASE+OFFSET.  
Reads (2) consecutive data bytes starting at the 10-bit register address BASE+OFFSET to the data  
edit boxes.  
Loop Count Edit Box  
Causes subsequent write or read operations to be performed N times. N is entered as a decimal  
number from 1 to 999.  
Histogram on  
Creates a histogram of the results from the Loop Count Reads.  
Loop Count Reads  
Close Button  
Closes the dialog.  
Note: The memory map editor can remain open with other  
windows. Use the Window menu to navigate.  
8.6 TVP5154 Property Sheets  
The property sheets represent the register data in a user-friendly format. The data is organized by  
function, with each function having its own page and being selectable via tabs at the top (see Figure 20).  
To open this, click on Edit Property Sheets in the Edit menu and select the device type to edit.  
When the property sheet function is started or whenever the user tabs to a different page, all readable  
registers in the device are read from hardware to initialize the dialog pages. Values on the page are  
changed by manipulating the various dialog controls as described in Table 6.  
OK, Cancel, and Apply buttons are at the bottom of each property page. These are described in Table 7.  
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Figure 20. TVP5154 Property Sheets  
8.6.1  
Property Sheet Refresh  
The property sheets are designed so that the data displayed is always current. Certain actions cause the  
entire register map to be read from the device and to update the property sheets. This happens when:  
Property sheets are initially opened.  
When tabbing from one page to another.  
When Read All is clicked.  
When making the TVP5154 Property Sheets window the active window (by clicking on it).  
When making a TVP5154 Register Map editor window the active window (by clicking on it).  
8.6.1.1  
Auto-Update From Device  
The last two items in the Property Sheet Refresh list (see section 8.6.1) are referred to as the  
Auto-Update feature. Auto-Update can be disabled by setting its program option button to DISABLED.  
This button is located on the initial dialog box (WinVCC Configuration).  
With Auto-Update enabled (default), the user can open both the TVP5154 Property Sheets and the  
TVP5154 Register Map editor at the same time. Changes made to the property sheets (and applied) are  
updated in the register map window as soon as the Register Map window is clicked on. Additionally,  
changes made in the TVP5154 Register Map editor are updated in the TVP5154 Property Sheets as soon  
as the property sheets window is clicked on.  
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Programming the TMS320DM642  
Table 6. Use of Property Sheet Controls  
PROPERTY SHEETS  
DIALOG CONTROL  
WHAT DO I DO WITH IT?  
When is Hardware Updated?  
Read-Only Edit Box  
Check Box  
Read status information  
Toggle a single bit  
Select from a text list  
Type a number  
N/A  
After Apply  
After Apply  
After Apply  
Drop-Down List  
Edit Box  
Up/Down arrows: Immediately  
Type a number: After Apply  
Edit Box with Up/Down arrows  
Use up/down arrows or type a number  
Slider  
Slide a lever  
Immediately  
Immediately  
Pushbutton  
Initiate an action  
Table 7. Property Sheet Button Controls  
BUTTON  
CONTROL  
DEFINITION  
OK  
Writes to all writeable registers whose data has changed. A register is flagged as changed if the value to be  
written is different from the value last read from that address.  
Closes the dialog.  
Cancel  
Causes all changes made to the property page since the last Apply to be discarded. Changes made to dialog  
controls with ‘immediate hardware update’ are not discarded, since they have already been changed in  
hardware.  
Does not write to hardware.  
Closes the dialog.  
Apply  
Writes to all writeable registers whose data has changed. A register is flagged as changed if the value to be  
written is different from the value last read from that address.  
9
Programming the TMS320DM642  
This chapter discusses how to change settings for the TMS320DM642 on this EVM. The DM642 settings  
can be controlled by using the DM642 Control Window, which is found by clicking on ToolsDM642  
Control, or through the Generic I2C registers.  
9.1 Development and Purpose of DM642 Code  
The TVP5154EVM was developed by the TI Digital Video Department, which is responsible for the  
TVP5146 and TVP5150AM1 video decoders currently used on the DM642EVM released by Spectrum  
Digital. The TVP5154EVM hardware and software are both based on this DM642EVM.  
The TVP5154EVM was designed specifically for security customers interested in a quad video decoder.  
The TVP5154EVM showcases the TVP5154 with various scaled/unscaled display modes, while making  
the DM642 transparent to the customer during evaluation. This is made possible by placing the DM642  
into an I2C slave mode and controlling the capture/display modes using virtual I2C registers. The entire  
TVP5154EVM is controlled by a PC emulating I2C via the parallel port. By downloading the DM642 code  
from flash at power up, it is not required to use Code Composer Studio™ software to program the DM642;  
all relevant DM642 control registers can be accessed and controlled through a generic I2C address.  
In addition to the command file provided with this EVM, additional command files to be used with TI’s EVM  
control software (WinVCC) can be provided from TI to support easy programming of the TVP5154 and  
DM642 registers to show the most common scaling configurations for both NTSC and PAL formats. When  
using these command files or when setting the register values through a standard I2C bus interface, it is  
important to enable and program the 5154 outputs before configuring the DM642 registers. The DM642  
portion of the TVP5154EVM consists only of the DM642, SDRAM, and flash memory.  
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Programming the TMS320DM642  
9.2 Details of the DM642 Code and Control Registers  
Details of the DM642 code and control registers are:  
The DM642 device address is 0x40h by default. The DM642 is setup as an I2C slave.  
The DM642 executes code on power up from the flash using the PCI GPIO to control the address  
MSB.  
Virtual I2C registers are created within the DM642 in order to control the capture and display of the  
scaled/unscaled data from the TVP5154 video decoder. These registers are described in Table 9.  
The virtual I2C registers support scaled and unscaled video outputs independently for each of the four  
video decoders, with the option to overlay scaled video onto unscaled video, and to define the  
quadrant location of each scaled channel.  
The virtual I2C registers provide easy control/access to the GPIOs currently tied to LEDs. Please refer  
to the TVP5154EVM schematics for options to associate an LED on/off with a register setting.  
The DM642 is not responsible for any scaling. All video scaling is performed by the TVP5154. The  
DM642 is only responsible for image capture and display.  
The DM642 virtual registers can be controlled by using the DM642 Control Window or through the  
Generic I2C registers.  
9.2.1  
DM642 Control Window  
The DM642 settings can be easily controlled by using the DM642 Control window. This window represents  
the DM642 register data in a user-friendly format. The data is organized for each of the four decoders (see  
Figure 21).  
To open this, click on DM642 Control in the Tools menu.  
Figure 21. DM642 Control Window  
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Programming the TMS320DM642  
When the DM642 Control window is opened, all readable registers for the device are read from software  
to initialize the dialog page. Register details are given in Table 8. Values on the page are changed by  
manipulating the various dialog controls as described in Table 8. The data is organized for each of the  
four decoders, allowing independent control of each decoder.  
Table 8. DM642 Control Window Controls  
CONTROL  
Read All  
DEFINITION  
Reads all defined readable registers from the device and updates the register window.  
Causes all changes made to the page since the last Apply to be discarded. Changes made to dialog controls  
with ‘immediate register update’ are not discarded, since they have already been changed in the DM642  
Close  
registers.  
Does not write to registers.  
Closes the dialog.  
Image Capture  
Enables image capture in the DM642 for that given decoder (1–4). Immediate register update.  
Used to inform the DM642 of the input color standard for that given decoder (1–4). No change in register until  
Video Standard Apply is clicked.  
Does not change the video standard setting for the TVP5154.  
Used to inform the DM642 of the input image size for that given decoder (1–4). No change in register until Apply  
Image Size  
is clicked.  
Actual scaling is done in the TVP5154.  
Image Position  
Defines the quadrant location for the input of that given decoder (1–4). Immediate register update.  
Immediately changes DM642 registers for input image size and input color standard for that given decoder  
(1–4).  
Enables TVP5154 scaler and programs correct scaling register settings into TVP5154 based on selected input  
standard and image size for that given decoder (1–4).  
Apply  
Flash  
Major/Minor  
Reads the data from the Flash Version registers and writes it into the register window.  
LED Control  
Changes LED (1–7) status. Checked: LED is ON. Unchecked: LED is OFF. Immediate register update.  
9.2.2  
DM642 Virtual I2C Register Map  
Table 9. DM642 Virtual I2C Register Map  
REGISTER DESCRIPTION  
Decoder 1 Register  
ADDRESS  
00h  
DATA (DEFAULT)  
02h  
12h  
22h  
32h  
01h  
01h  
01h  
01h  
00h  
01h  
00h  
Decoder 2 Register  
01h  
Decoder 3 Register  
02h  
Decoder 4 Register  
03h  
Decoder 1 Input Format Register  
Decoder 2 Input Format Register  
Decoder 3 Input Format Register  
Decoder 4 Input Format Register  
LED Control  
04h  
05h  
06h  
07h  
08h  
Flash Version: Major  
09h  
Flash Version: Minor  
0Ah  
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Programming the TMS320DM642  
9.2.3  
DM642 Virtual I2C Register Details  
Table 10. Decoder 1 Register  
Address  
Default  
7
00h  
02h  
6
5
4
3
2
1
0
Capture  
Enable  
Reserved  
Position  
Capture Size  
Capture Size  
Unscaled  
Bit 2  
Bit 1  
Bit 0  
0
0
0
0
0
1
QSIF – 176 × 120  
SIF – 352 × 240 (1/4 NTSC)  
(default)  
0
1
0
QCIF – 176 × 144  
CIF – 352 × 288 (1/4 PAL)  
QVGA – 320 × 240  
VGA – 640 × 480  
Reserved  
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Capture Enable  
Disable (default)  
Enable  
Bit 3  
0
1
Position  
Bit 5  
Bit 4  
Quadrant 1 (default)  
Quadrant 2  
0
0
1
0
1
0
Quad 1 Quad 2  
Quadrant 3  
Quad 3  
Quad 4  
Quadrant 4  
1
1
Scaled capture sizes always take priority over unscaled capture sizes.  
Decoder priorities are always such that Decoder 1 is the highest priority, Decoder 2 is the second highest,  
etc.  
For example, if Decoders 1 and 4 are scaled to 1/4 size and Decoders 2 and 3 are unscaled, this display  
results:  
Decoder 1  
Scaled  
Decoder 2  
Unscaled  
Decoder 2  
Unscaled  
Decoder 4  
Scaled  
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Programming the TMS320DM642  
Note: The unscaled Decoder 2 displays in both Quadrant 2 and 3 since Decoder 2 takes priority  
over Decoder 3 when both are unscaled.  
Table 11. Decoder 2 Register  
Address  
Default  
7
01h  
12h  
6
5
4
3
2
1
0
Capture  
Enable  
Reserved  
Position  
Capture Size  
Capture Size  
Unscaled  
Bit 2  
Bit 1  
Bit 0  
0
0
0
0
0
1
QSIF – 176 × 120  
SIF – 352 × 240 (1/4 NTSC)  
(default)  
0
1
0
QCIF – 176 × 144  
CIF – 352 × 288 (1/4 PAL)  
QVGA – 320 × 240  
VGA – 640 × 480  
Reserved  
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Capture Enable  
Disable (default)  
Enable  
Bit 3  
0
1
Position  
Bit 5  
Bit 4  
Quadrant 1  
0
0
1
0
1
0
Quad 1 Quad 2  
Quadrant 2 (default)  
Quadrant 3  
Quad 3  
Quad 4  
Quadrant 4  
1
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Table 12. Decoder 3 Register  
Address  
Default  
7
01h  
22h  
6
5
4
3
2
1
0
Capture  
Enable  
Reserved  
Position  
Capture Size  
Capture Size  
Unscaled  
Bit 2  
Bit 1  
Bit 0  
0
0
0
0
0
1
QSIF – 176 × 120  
SIF – 352 × 240 (1/4 NTSC)  
(default)  
0
1
0
QCIF – 176 × 144  
CIF – 352 × 288 (1/4 PAL)  
QVGA – 320 × 240  
VGA – 640 × 480  
Reserved  
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Capture Enable  
Disable (default)  
Enable  
Bit 3  
0
1
Position  
Bit 5  
Bit 4  
Quadrant 1  
0
0
1
0
1
0
Quad 1 Quad 2  
Quadrant 2  
Quadrant 3 (default)  
Quad 3  
Quad 4  
Quadrant 4  
1
1
Table 13. Decoder 4 Register  
Address  
Default  
7
01h  
32h  
6
5
4
3
2
1
0
Capture  
Enable  
Reserved  
Position  
Capture Size  
Capture Size  
Unscaled  
Bit 2  
Bit 1  
Bit 0  
0
0
0
0
0
1
QSIF – 176 × 120  
SIF – 352 × 240 (1/4 NTSC)  
(default)  
0
1
0
QCIF – 176 × 144  
CIF – 352 × 288 (1/4 PAL)  
QVGA – 320 × 240  
VGA – 640 × 480  
Reserved  
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
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Capture Enable  
Disable (default)  
Enable  
Bit 3  
0
1
Position  
Bit 5  
Bit 4  
Quadrant 1  
Quadrant 2  
Quadrant 3  
0
0
1
0
1
0
Quad 1 Quad 2  
Quad 3  
Quad 4  
Quadrant 4 (default)  
1
1
Table 14. Decoder 1 Input Format Register  
Address  
Default  
7
04h  
01h  
6
5
4
3
2
1
0
Reserved  
Input Color Standard  
Input Color Standard  
NTSC  
Bit 2  
0
Bit 1  
0
Bit 0  
0
(B, D, G, H, I, N) PAL  
(default)  
0
0
1
Reserved  
. . .  
The Input Color Standard register is used to inform the DM642 of the input color standard for that given  
decoder (1–4). The output format of the DM642 is set to the standard with the largest majority based on  
Registers 04h–07h. If the number of input color standards is equal, the DM642 automatically default to  
PAL output.  
Table 15. Decoder 2 Input Format Register  
Address  
Default  
7
05h  
01h  
6
5
4
3
2
1
0
Reserved  
Input Color Standard  
Input Color Standard  
NTSC  
Bit 2  
0
Bit 1  
0
Bit 0  
0
(B, D, G, H, I, N) PAL  
(default)  
0
0
1
Reserved  
. . .  
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Programming the TMS320DM642  
Table 16. Decoder 3 Input Format Register  
Address  
Default  
7
06h  
01h  
6
5
4
3
2
1
0
Reserved  
Input Color Standard  
Input Color Standard  
NTSC  
Bit 2  
0
Bit 1  
0
Bit 0  
0
(B, D, G, H, I, N) PAL  
(default)  
0
0
1
Reserved  
. . .  
Table 17. Decoder 4 Input Format Register  
Address  
Default  
7
07h  
01h  
6
5
4
3
2
1
0
Reserved  
Input Color Standard  
Input Color Standard  
NTSC  
Bit 2  
0
Bit 1  
0
Bit 0  
0
(B, D, G, H, I, N) PAL  
(default)  
0
0
1
Reserved  
. . .  
Table 18. LED Control Register  
Address  
Default  
7
08h  
00h  
6
5
4
3
2
1
0
Reserved  
LED 7 Status LED 6 Status LED 5 Status LED 4 Status LED 3 Status LED 2 Status LED 1 Status  
LED (1–7) Status  
= 0 (LED off)  
= 1 (LED on)  
Table 19. Flash Major Version Register  
Address  
Default  
7
09h  
01h  
6
5
4
3
2
1
0
Flash Major Version  
Table 20. Flash Minor Version Register  
Address  
Default  
7
0Ah  
00h  
6
5
4
3
2
1
0
Flash Minor Version  
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Troubleshooting  
10  
Troubleshooting  
This chapter discusses ways to troubleshoot the TVP5154EVM.  
10.1 Troubleshooting Guide  
If you are experiencing problems with the TVP5154EVM hardware or the WinVCC software, see Table 21  
for available solutions.  
Table 21. TVP5154EVM Troubleshooting  
SYMPTOM  
CAUSE  
SOLUTION  
At startup, the error message Cannot find The parallel port driver supplied with the  
Run Port95NT.EXE on the CD to install  
the driver.  
DLL file DLPORTIO.DLL appears.  
EVM has not been installed.  
Wrong video input is selected.  
Go to EditProperty SheetsTVP5154,  
Analog Video page, select the correct  
video input(s) and click Apply.  
(The composite video input 1 is selected  
by default.)  
Blank screen  
Source is connected to the wrong input  
connector.  
Connect source to the correct input  
connector.  
Go to EditProperty SheetsTVP5154,  
Output Control page, check the enable  
YCbCr outputs and enable clock outputs  
check boxes and click Apply.  
YCbCr outputs or clock output is disabled.  
Go to EditProperty SheetsTVP5154,  
Synchronization page, set the Fsc control  
format to RTC and click Apply.  
Wrong mode is selected for color  
subcarrier genlock output.  
No color  
Go to EditProperty SheetsTVP5154,  
Output Control page, set the drop down  
box labeled FID/GLCO (pin 23) to genlock  
output (GLCO) and click Apply.  
GLCO pin is not set to output the GLCO  
signal.  
Go to EditProperty SheetsTVP5154,  
Output Control page, set the YCbCr  
output format to 8-bit 4:2:2 YCbCr  
w/ITU-R BT.656 embedded sync mode  
and click Apply.  
Screen colors are only magenta and  
green.  
Wrong YCbCr output format  
Go to EditProperty SheetsTVP5154,  
Mode Selection page, uncheck all  
standards to be included in auto-switch  
processing and click Apply.  
Auto-switch masks are not set correctly.  
Video standard auto-switch does not work  
on the video decoder side.  
Go to EditProperty SheetsTVP5154,  
Video decoder is not in auto-switch mode. Mode Selection page, set the drop-down  
box to multistandard and click Apply.  
Click real-time polling in the Tools menu.  
Click Enable All and OK. This should be  
disabled if using a composite output.  
Video standard auto-switch does not work  
on the video encoder side.  
Auto-switch polling is not enabled.  
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Troubleshooting  
Table 21. TVP5154EVM Troubleshooting (continued)  
SYMPTOM  
CAUSE  
SOLUTION  
Make sure I2C slave address jumpers on  
the TVP5154 decoder module are across  
pins 2 and 3.  
Decoder I2C slave address is wrong.  
Encoder I2C slave address is wrong.  
Slave address is hard coded to be 0x54 in  
the command file. Make sure the I2C slave  
address jumper on encoder module is  
across pins 2 and 3.  
Parallel cable is not connected from PC  
parallel port to the TVP5154 decoder  
module DB25 connector.  
Connect cable  
Power supply must be plugged into a  
100-V to 240-V/47-Hz to 63-Hz power  
source, and the cord must be plugged into  
the power connector on the EVM.  
EVM is not powered on.  
Some parallel cables are not wired  
straight through pin for pin. Use the cable  
supplied with the EVM.  
Wrong type of parallel cable.  
No I2C communication  
Press the Reset button on the TVP5154  
Decoder Module.  
Device was placed in power-down mode.  
EVM was configured for an external I2C  
master.  
Reinstall 0-resistors R5 and R6. Control  
EVM using the PC parallel port.  
DO THIS AS A LAST RESORT. Reboot  
PC, enter BIOS setup program, and set  
parallel port LPT1 mode (Addr 378h) to  
ECP mode or bidirectional mode  
(sometimes called PS/2 mode or byte  
mode). If already set to one of these two  
modes, switch to the other setting (see  
Section 10.2).  
PC parallel port mode is not set correctly.  
PC may not be capable of operating in the  
required parallel port mode. This is true of  
some laptop computers. Use a different  
computer, preferably a desktop PC.  
Still no I2C communication  
When WinVCC is started and the WinVCC Configuration dialog box is closed with OK, the I2C system test  
is performed (unless the I2C System Test program options button was disabled).  
If the I2C system test fails, a dialog box (see Figure 22) appears. This example reports that a read from  
TVP5154 failed, using slave address 0xB8, sub-address 0xD0. The data read was 0x78. The expected  
data was 0x00.  
After noting which device had a problem, click OK to continue. Next, the Corrective Action Dialog box  
appears to fix the problem.  
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Troubleshooting  
Figure 22. I2C System Failure Dialog Box  
10.2 Corrective Action Dialogs  
After closing the I2C system test report dialog box, a dialog box (see Figure 23) appears.  
Figure 23. Corrective Action Dialog Box  
1. If the parallel port cable is NOT connected between to PC and the TVP5154EVM, or if the EVM power  
is not on:  
a. Click NO.  
b. The dialog box shown in Figure 23 appears instructing you to correct the problem.  
c. Correct the problem.  
d. Click OK to continue. The Real-Time Polling dialog appears.  
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Troubleshooting  
Figure 24. Corrective Action Required  
2. If the cable is connected from the PC parallel port to the TVP5154EVM and the EVM power is on:  
a. Click Yes.  
b. The dialog box shown in Figure 24 appears. This dialog box appears if the PC parallel  
port mode setting may need to be changed.  
Note: Only run the PC BIOS setup program if the I2C communication problem cannot be  
resolved in another way (correct slave address settings, reset or power cycle the  
EVM, and/or check that the device type selected was TVP5154).  
c. Click OK to continue.  
d. The real-time polling dialog appears. Click OK to close it and get to the main menu.  
e. Click Exit in the File menu to exit the program.  
f. See the troubleshooting guide in Table 21.  
Figure 25. Corrective Action Required  
10.2.1 Setting the PC Parallel Port Mode  
Note: Only run the PC BIOS setup program if the I2C communication problem cannot be  
resolved in another way (correct slave address settings, reset or power cycle the EVM,  
and/or check that the device type selected was TVP5154).  
1. Restart the PC.  
2. During the boot process, enter the BIOS setup program by pressing the required key (usually the initial  
text screen indicates which key to press).  
3. Find the place where the parallel port settings are made.  
4. Set the parallel port LPT1 at address 378h to ECP mode or bidirectional mode (sometimes called PS/2  
mode or byte mode). If one of these two modes is already selected, change to the opposite mode.  
5. Exit and save changes.  
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TVP5154EVM Schematics  
10.2.2 General I2C Error Report  
The I2C Error Report shown in Figure 26 appears when an I2C error occurs at any time other than after  
the I2C system test. In this example, there is acknowledge error at slave address 0x54 (the video encoder  
module). The error occurred on Read Cycle Phase 1 on the device (slave) address byte.  
Figure 26. I2C Error  
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1
2
3
4
5
6
D
C
B
A
D
C
B
A
TVP5154EVMDVB REV 1.2  
I2C  
page 17 - I2C  
Power  
page 7 - Power  
SDA  
SCL  
/RESET  
Anti-Aliasing Filters  
page 11 - Anti-Aliasing Filters  
TVP5154  
page 2 - TVP5154  
DM642  
page 4 - DM642  
Connector  
page 16 - Connector  
1A_IN  
1B_IN  
1A_IN  
1B_IN  
/RESET  
SCL  
SDA  
/RESET  
SCL  
SDA  
SDA  
SCL  
/RESET  
2A_IN  
2B_IN  
2A_IN  
2B_IN  
CH1_OUT[7..0]  
SCKS1  
SCK1  
CH1_OUT[7..0]  
SCKS1  
ENC_Y[7..0]  
ENC_C[7..0]  
ENC_Y[7..0]  
ENC_C[7..0]  
3A_IN  
3B_IN  
3A_IN  
3B_IN  
HS1  
VS1  
AV1  
FID1  
ENC_SCLK  
ENC_HS  
ENC_VS  
ENC_SCLK  
ENC_HS  
ENC_VS  
4A_IN  
4B_IN  
4A_IN  
4B_IN  
AV1  
ENC_FID  
ENC_FID  
VB1  
1A_OUT  
1B_OUT  
1A_OUT  
1B_OUT  
CH2_OUT[7..0]  
SCKS2  
SCK2  
CH2_OUT[7..0]  
SCKS2  
2A_OUT  
2B_OUT  
2A_OUT  
2B_OUT  
HS2  
VS2  
AV2  
FID2  
3A_OUT  
3B_OUT  
3A_OUT  
3B_OUT  
AV2  
VB2  
4A_OUT  
4B_OUT  
4A_OUT  
4B_OUT  
CH3_OUT[7..0]  
SCKS3  
SCK3  
CH3_OUT[7..0]  
SCKS3  
JTAG  
page 15 - JTAG  
HS3  
VS3  
AV3  
FID3  
AV3  
DSP_TDO  
DSP_TDI  
DSP_TMS  
DSP_TDO  
DSP_TDI  
DSP_TMS  
DSP_TCLK  
DSP_TRST#  
DSP_EMU[11..0]  
VB3  
DSP_TCLK  
DSP_TRST#  
DSP_EMU[11..0]  
CH4_OUT[7..0]  
SCKS4  
SCK4  
CH4_OUT[7..0]  
SCKS4  
HS4  
VS4  
AV4  
FID4  
AV4  
VB4  
Daughtercard Interface  
page 3 - Daughtercard Interface  
F&V Bit Breakout  
Flash Memory  
SDRAM  
page 13 - SDRAM  
page 12 - F&V Bit Breakout  
page 14 - Flash Memory  
TEXAS INSTRUMENTS, INC.  
12500 TI BLVD  
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TVP5154EVM BLOCK DIAGRAM  
Size  
C
FCSM No.  
DWG No.  
Rev  
1
Scale  
Sheet  
1 of 17  
6
1
2
3
4
5
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2
3
4
5
6
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C
B
A
D
C
B
A
DM642 Clocks and Reset  
page 6 - DM642 Clocks and Reset  
DM642 Power Pins  
page 9 - DM642 Power Pins  
/RESET  
SCL  
SDA  
/RESET  
SCL  
SDA  
DM642 Video Ports  
page 5 - DM642 Video Ports  
CH1_OUT[7..0]  
SCKS1  
AV1  
CH1_OUT[7..0]  
SCKS1  
AV1  
CH2_OUT[7..0]  
SCKS2  
AV2  
CH2_OUT[7..0]  
SCKS2  
AV2  
ENC_Y[7..0]  
ENC_C[7..0]  
ENC_Y[7..0]  
ENC_C[7..0]  
ENC_SCLK  
ENC_HS  
ENC_VS  
ENC_SCLK  
ENC_HS  
ENC_VS  
CH3_OUT[7..0]  
SCKS3  
AV3  
CH3_OUT[7..0]  
SCKS3  
AV3  
ENC_FID  
ENC_FID  
CH4_OUT[7..0]  
SCKS4  
AV4  
CH4_OUT[7..0]  
SCKS4  
AV4  
DM642 EMIF and JTAG  
page 10 - DM642 EMIF and JTAG  
TED[63..0]  
TEA[22..3]  
TED[63..0]  
TEA[22..3]  
TECLKOUT1  
TSDCKE  
TSDRAS#  
TSDCAS#  
TSDWE#  
TCE0#  
TCE1#  
TBE7#  
TBE6#  
TBE5#  
TECLKOUT1  
TSDCKE  
TSDRAS#  
TSDCAS#  
TSDWE#  
TCE0#  
TCE1#  
TBE7#  
TBE6#  
TBE5#  
TBE4#  
TBE3#  
TBE2#  
TBE1#  
TBE4#  
TBE3#  
TBE2#  
TBE1#  
TBE0#  
TBE0#  
DSP_EMU[11..0]  
DSP_TDI  
DSP_TDO  
DSP_TMS  
DSP_TCLK  
DSP_TRST#  
DSP_EMU[11..0]  
DSP_TDI  
DSP_TDO  
DSP_TMS  
DSP_TCLK  
DSP_TRST#  
DM642 PCI_HPI_EMAC  
page 8 - DM642 PCI_HPI_EMAC  
GP13_A19  
GP14_A20  
GP15_A21  
GP13_A19  
GP15_A21  
GP14_A20  
TEXAS INSTRUMENTS, INC.  
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DWG No.  
Rev  
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C
B
A
D
C
B
A
U25B  
VP0_CLK0  
RPACK4-33  
AF14  
AF12  
AF18  
AE18  
CH1_OUT[7..0]  
VP0_D00  
VP0_D01  
CH1_OUT[7..0]  
1
2
3
4
8
SCKS1  
SCKS2  
AV1  
VP0_CLK1  
7
6
5
AF17 CH1_OUT0  
AF16 CH1_OUT1  
AE16 CH1_OUT2  
AD16 CH1_OUT3  
AC16 CH1_OUT4  
AB16 CH1_OUT5  
AE15 CH1_OUT6  
AD15 CH1_OUT7  
AC15  
CLKX0/VP0_D02  
FSX0/VP0_D03  
DX0/VP0_D04  
CLKS0/VP0_D05  
DR0/VP0_D06  
AE17  
AC17  
AD17  
VP0_CTL0  
VP0_CTL1  
VP0_CTL2  
AV2  
RN25  
FSR0/VP0_D07  
Video Port 0 / McBSP0 / McASP Control  
CLKR0/VP0_D08  
VP0_D09  
VP0_D10  
VP0_D11  
CH2_OUT[7..0]  
CH2_OUT[7..0]  
AB15  
AD14 CH2_OUT0  
AC14 CH2_OUT1  
AB14 CH2_OUT2  
AD13 CH2_OUT3  
AC13 CH2_OUT4  
AB13 CH2_OUT5  
AD12 CH2_OUT6  
AC12 CH2_OUT7  
ACLKR0/VP0_D12  
AFSR0/VP0_D13  
AHCLKR0/VP0_D14  
AMUTEIN/VP0_D15  
AMUTE/VP0_D16  
ACLKX0/VP0_D17  
AFSX0/VP0_D18  
AHCLKX0/VP0_D19  
RPACK4-33  
AF8  
AF10  
AF5  
AF6  
CH3_OUT[7..0]  
VP1_CLK0  
VP1_CLK1  
VP1_D00  
VP1_D01  
CH3_OUT[7..0]  
1
2
3
4
8
SCKS3  
SCKS4  
AV3  
7
6
5
AE6 CH3_OUT0  
AD6 CH3_OUT1  
AC6 CH3_OUT2  
AE7 CH3_OUT3  
AD7 CH3_OUT4  
AC7 CH3_OUT5  
AD8 CH3_OUT6  
AC8 CH3_OUT7  
AE9  
CLKX1/VP1_D02  
FSX1/VP1_D03  
DX1/VP1_D04  
CLKS1/VP1_D05  
DR1/VP1_D06  
FSR1/VP1_D07  
AF4  
AE5  
AD5  
VP1_CTL0  
VP1_CTL1  
VP1_CTL2  
AV4  
RN26  
CLKR1/VP1_D08  
Video Port 1 / McBSP1 / McASP Data  
VP1_D09  
VP1_D10  
VP1_D11  
CH4_OUT[7..0]  
CH4_OUT[7..0]  
AD9  
AC9 CH4_OUT0  
AD10 CH4_OUT1  
AC10 CH4_OUT2  
AE11 CH4_OUT3  
AD11 CH4_OUT4  
AC11 CH4_OUT5  
AB11 CH4_OUT6  
AB12 CH4_OUT7  
AXR0/VP1_D12  
AXR1/VP1_D13  
AXR2/VP1_D14  
AXR3/VP1_D15  
AXR4/VP1_D16  
AXR5/VP1_D17  
AXR6/VP1_D18  
AXR7/VP1_D19  
D3.3V  
L1  
BLM21P221SN  
Y1  
EN  
C1  
0.1uF  
C2  
1000pF  
1
2
4
3
VCC  
R1 33  
A7  
A13  
C8  
D8  
A9  
B9  
C9  
D9  
GND OUT  
VP2_CLK0  
VP2_CLK1  
VP2_D00  
VP2_D01  
VP2_D02  
VP2_D03  
VP2_D04  
VP2_D05  
VP2_D06  
VP2_D07  
VP2_D08  
VP2_D09  
VP2_D10  
VP2_D11  
VP2_D12  
VP2_D13  
VP2_D14  
VP2_D15  
VP2_D16  
VP2_D17  
VP2_D18  
VP2_D19  
RPACK4-33  
ENC_Y[7..0]  
ENC_Y[7..0]  
27MHz_MIH_MMD  
1
2
3
4
8
ENC_Y0  
ENC_Y1  
ENC_Y2  
ENC_Y3  
ENC_SCLK  
ENC_HS  
ENC_VS  
7
6
5
B8  
D7  
C7  
VP2_CTL0  
VP2_CTL1  
VP2_CTL2  
ENC_FID  
A10 ENC_Y4  
B10 ENC_Y5  
C10 ENC_Y6  
D10 ENC_Y7  
A11  
RN27  
Video Port 2  
B11  
ENC_C[7..0]  
ENC_C[7..0]  
C11 ENC_C0  
D11 ENC_C1  
E11 ENC_C2  
B12 ENC_C3  
C12 ENC_C4  
D12 ENC_C5  
E12 ENC_C6  
E13 ENC_C7  
TP1  
TP  
TP2  
TP  
D3.3V  
R6  
PCI FREQ CONFIGURATION  
NO POP  
VIC  
R6/R27  
MODE SELECTED  
AC1  
AD1  
STCLK  
VDAC / GP08  
0
1
66MHz (DEFAULT)  
33MHz  
TMX320DM642CGDK  
R29  
1k  
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D3.3V  
D3.3V  
L2  
D3.3V  
R72  
150  
R73  
150  
R74  
150  
R75  
150  
BLM21P221SN  
TP3  
TP  
Y2  
EN  
RN1  
RPACK4-10k  
D
C
B
A
D
C
B
A
C3  
0.1uF  
C166  
1000pF  
1
2
4
3
VCC  
R61  
33  
GND OUT  
50.00MHz  
1
2
3
4
C168  
NO POP  
BLUE_LED BLUE_LED BLUE_LED BLUE_LED  
TP4  
TP  
TP5  
TP  
TP6  
TP  
TP7  
TP  
TP8  
TP  
TP9  
TP  
D3.3V  
U25E  
CLKIN  
GP04  
GP05  
GP06  
GP07  
R7  
R39  
10k  
DSP_CLKIN  
AC2  
NO POP  
DSP_ECLKIN  
H25  
ECLKIN  
AA2  
AE4  
CLKMODE0  
CLKMODE1  
R70 360  
M5  
L5  
D6  
C6  
GP00 / DM641SEL  
GP03 / PCIEEAI  
GP01 / CLKOUT4  
GP02 / CLKOUT6  
R30  
1k  
R8  
NO POP  
PCI_EEAI  
R12  
R71 360  
GP04  
GP05  
GP06  
GP07  
F4  
F3  
F2  
E1  
D3.3V  
EXTINT4 / GP04  
EXTINT5 / GP05  
EXTINT6 / GP06  
EXTINT7 / GP07  
NO POP  
A4  
C5  
TINP0  
EMACEN / TOUT0  
EMAC_ENABLE  
LENDIAN_MODE  
B4  
P4  
R80  
2.2k  
NMI  
A5  
B5  
R81  
2.2k  
TINP1  
LENDIAN / TOUT1  
/RESET  
RESET  
D3.3V  
L3  
R31  
1k  
DSP_PLL_VDD  
E4  
D3  
SCL0  
SDA0  
SCL  
SDA  
V6  
PLL_VDD  
BLM21P221SN  
Y3  
Clocks / Interrupts / Timers / IIC  
C4  
C167  
1000pF  
1
2
4
3
EN  
VCC  
0.1uF  
R3  
33  
GND OUT  
25.00MHz  
AB3  
AA3  
E14  
CLKINF  
AMUX1  
TSTSTRB  
PLL_LD  
RESERVED  
AD3  
AC4  
CLKOUTT  
CLKOUTF  
AF3  
D3.3V  
TMX320DM642CGDK  
TP10  
TP  
R13  
NO POP  
R9  
NO POP  
R10  
NO POP  
1
7
8
D3.3V  
X1/ICLK X2  
R2 33  
EXCCET103U  
E1  
5
4
DSP_ECLKIN  
S1  
S0  
CLK  
REF  
6
DSP_PLL_VDD  
1
3
I
O
D3.3V  
R40  
10k  
R11  
3
2
C169  
10uF  
C5  
0.1uF  
GND  
VDD  
+
NO POP  
U3  
ICS512  
C6  
0.1uF  
Place all PLL external components as close to the DSP. All PLL external components must be on a single side of the board.  
S1  
S0  
MULTIPLY OUTPUT  
0
0
0
OPEN  
1
4X  
100 MHz  
D3.3V  
5.33X  
5X  
133.25 MHz  
125 MHz  
62.5 MHz  
50 MHz  
R14  
R32  
R15  
NO POP  
1k  
EMAC_ENABLE  
PCI_EEAI  
0
PCI EEPROM AUTO-INIT CONFIGURATION  
OPEN  
0
2.5X  
2X  
R16/R32  
MODE SELECTED  
NO POP  
LENDIAN_MODE  
OPEN OPEN  
0
1
PCI EEPROM DISABLED(DEFAULT)  
PCI EEPROM ENABLED; PCIEN=1  
OPEN  
1
0
3.33X  
6X  
83.25 MHz  
150 MHz  
75 MHz  
1
1
1
R33  
1k  
R16  
R34  
1k  
OPEN  
1
3X  
NO POP  
8X  
200 MHz  
ENDIAN MODE CONFIGURATION  
R15/R34  
MODE SELECTED  
0
1
BIG ENDIAN MODE  
LITTLE ENDIAN MODE (DEFAULT)  
EMAC MODE CONFIGURATION  
R14/R33  
MODE SELECTED  
0
1
ETHERNET MAC DISABLED  
ETHERNET MAC ENABLED  
TEXAS INSTRUMENTS, INC.  
12500 TI BLVD  
DALLAS, TEXAS 75243  
DM642 CLOCKS & RESET  
Size  
C
FCSM No.  
DWG No.  
Rev  
1
Scale  
Sheet  
6 of 17  
6
1
2
3
4
5
Download from Www.Somanuals.com. All Manuals Search And Download.  
1
2
3
4
5
6
D3.3V  
R17  
NO POP  
R19  
NO POP  
EMIF_ECLKINSEL[1:0]  
TEA20  
TEA19  
MODE SELECTED  
RN4  
RPACK8-33  
RN5  
RPACK8-33  
TEA19  
TEA20  
D
C
B
A
D
C
B
A
RN2  
RPACK8-33  
0
0
1
1
0
1
0
1
ECLKIN( DEFAULT)  
CPU CLOCK /4 EMIF CLOCK  
CPU CLOCK /6 EMIF CLOCK  
RESERVED  
R18  
NO POP  
R20  
NO POP  
U25A  
RN6  
RPACK8-33  
TEA3  
M24EA3  
M23EA4  
N26EA5  
N24EA6  
N23EA7  
P26EA8  
P24EA9  
P23EA10  
EA3  
EA4  
EA5  
EA7  
EA6  
EA10  
EA9  
EA8  
8
7
6
5
4
3
2
1
9
EA03  
EA04  
EA05  
EA06  
EA07  
EA08  
EA09  
EA10  
10 TEA4  
11 TEA5  
12 TEA7  
13 TEA6  
14 TEA10  
15 TEA9  
16 TEA8  
DSP_TMS  
DSP_TRST#  
DSP_TDI  
DSP_TDO  
DSP_TCLK  
E15  
DSP_TMS  
DSP_TRST#  
DSP_TDI  
DSP_TDO  
DSP_TCLK  
TMS  
TRST  
TDI  
TDO  
TCLK  
D14  
A18  
B18  
A16  
RN7 RPACK8-33  
16 TEA11  
R24  
R23  
T25  
T24  
U26  
U25  
U24  
V23  
1
2
3
4
5
6
7
8
EA11  
EA12  
EA13  
EA14  
EA15  
EA16  
EA17  
EA18  
15 TEA12  
14 TEA13  
13 TEA14  
12 TEA15  
11 TEA16  
10 TEA17  
DSP_EMU[11..0]  
DSP_EMU[11..0]  
DSP_EMU11  
DSP_EMU10  
D17  
C17  
EMU11  
EMU10  
DSP_EMU9  
DSP_EMU8  
DSP_EMU7  
DSP_EMU6  
DSP_EMU5  
DSP_EMU4  
B17  
D16  
A17  
C16  
B16  
D15  
EMU9  
EMU8  
EMU7  
EMU6  
EMU5  
EMU4  
9
TEA18  
TEA[22..3]  
TEA[22..3]  
RN13 RPACK4-33  
TP12  
TP  
TP13  
TP  
TP14  
TP  
TP15  
TP  
TP16  
TP  
TP17  
TP  
TP18  
TP  
V26  
V25  
V24  
U23  
1
2
3
4
8
7
6
5
TEA19  
ECLKINSEL0 / EA19  
ECLKINSEL1 / EA20  
BOOTMODE0 / EA21  
BOOTMODE1 / EA22  
TEA20  
TEA21  
TEA22  
DSP_EMU3  
DSP_EMU2  
DSP_EMU1  
DSP_EMU0  
C15  
B15  
C14  
A15  
EMU3  
EMU2  
EMU1  
EMU0  
TCE0#  
TCE1#  
TCE2#  
TCE3#  
PDT#  
RN14 RPACK4-33  
K25  
K24  
K23  
L26  
1
2
3
4
8
7
6
5
TCE0#  
TCE1#  
TCE2#  
TCE3#  
CE0  
CE1  
CE2  
CE3  
TCE0#  
TCE1#  
TP11  
TP  
D3.3V  
TSOE3#  
TECLKOUT2  
J24  
J25  
K26  
L25  
R22  
M22  
33  
33  
33  
33  
33  
33  
R62  
R63  
R64  
R65  
R66  
R67  
SDRAS/AOE  
SDCAS/ARE  
SDWE/AWE  
SDCKE  
TSDRAS#  
R89  
4.7k  
TSDCAS#  
TSDWE#  
TSDCKE  
L22  
TSOE3#  
PDT#  
ARDY  
HOLD  
SOE3  
PDT  
R41  
10k  
J26  
J23  
33  
33  
R68  
R69  
ECLKOUT1  
ECLKOUT2  
TECLKOUT1  
TECLKOUT2  
W24  
N22  
P22  
HOLDA  
BUSREQ  
RN12  
RPACK8-33  
L24  
L23  
M26  
M25  
R26  
R25  
T23  
T22  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
BE0  
BE1  
BE2  
BE3  
BE4  
BE5  
BE6  
BE7  
TBE0#  
TBE1#  
TBE2#  
TBE3#  
TBE4#  
TBE5#  
TBE6#  
TBE7#  
EMIF and Emulation  
TMX320DM642CGDK  
TED[63..0]  
TED[63..0]  
BOOT_MODE[1:0]  
TEA22  
TEA21  
MODE SELECTED  
D3.3V  
0
0
1
1
0
1
0
1
NO BOOT (DEFAULT)  
HPI/PCI BOOT MODE (PCIEN)  
RESERVED  
R35  
1k  
R36  
1k  
NOTE: PLACE ALL 33-OHM RESISTORS AND RESISTOR NETWORKS AS CLOSE AS POSSIBLE TO THE CORRESPONDING U25 PINS.  
EMIF 8 BIT ROM BOOT  
TEA21  
TEA22  
R21  
NO POP  
R22  
NO POP  
TEXAS INSTRUMENTS, INC.  
12500 TI BLVD  
DALLAS, TEXAS 75243  
DM642 EMIF & JTAF  
FCSM No.  
Size  
C
DWG No.  
Rev  
1
Scale  
Sheet  
10 of 17  
6
1
2
3
4
5
Download from Www.Somanuals.com. All Manuals Search And Download.  
1
2
3
4
5
6
D3.3V  
D
C
B
A
D
C
B
A
R77  
150  
R78  
150  
R79  
150  
R42 R43 R44 R45  
10k 10k 10k 10k  
U25D  
5
6
7
V4  
Y3  
AA1  
Y4  
Y2  
W3  
Y1  
W4  
W2  
V2  
V3  
V1  
U4  
U2  
U3  
U1  
T3  
M3  
M2  
M4  
L2  
L3  
K2  
L4  
PCBE0  
HD00 / AD00  
HD01 / AD01  
HD02 / AD02  
HD03 / AD03  
HD04 / AD04  
T2  
M1  
J2  
PCBE1 / HDS2  
PCBE2 / HR/W  
PCBE3 / GP10  
BLUE_LED BLUE_LED BLUE_LED  
N4  
N3  
N1  
R3  
P1  
P3  
HWDTHSEL  
PFRAME / HINT  
PTRDY / HHWIL  
PIRDY / HRDY  
PSTOP / HCNTL0  
PDEVSEL / HCNTL1  
PPAR / HAS  
HWDTHSEL / HD05 / AD05  
HD06 / AD06  
HD07 / AD07  
HD08 / AD08  
HD09 / AD09  
HD10 / AD10  
HD11 / AD11  
HD12 / AD12  
HD13 / AD13  
HD14 / AD14  
R1  
R2  
PPERR / HCS  
PSERR / HDS1  
HPI WIDTH SELECTION  
F1  
H4  
PREQ / GP11  
PGNT / GP12  
HD15 / AD15  
HWDTHSEL  
MODE SELECTED  
16 BITS  
32-BITS  
MTXD0 / HD16 / AD16  
MTXD1 / HD17 / AD17  
MTXD2 / HD18 / AD18  
MTXD3 / HD19 / AD19  
MTXEN / HD20 / AD20  
MCOL / HD21 / AD21  
MTCLK / HD22 / AD22  
HD23 / AD23  
MRXD0 / HD24 / AD24  
MRXD1 / HD25 / AD25  
MRXD2 / HD26 / AD26  
MRXD3 / HD27 / AD27  
MRXDV / HD28 / AD28  
MRXER / HD29 / AD29  
MCRS / HD30 / AD30  
MRCLK / HD31 / AD31  
0
K3  
G4  
PIDSEL / GP9  
1
GP13_A19  
GP15_A21  
PINTA / GP13  
K1  
K4  
J1  
J3  
H2  
J4  
G2  
H3  
G1  
PCI SELECTION  
PCIEN MODE SELECTED  
G3  
PRST / GP15  
PCIEN  
E2  
C1  
PCIEN  
0
1
PCI DISABLED  
PCI ENABLED  
GP14_A20  
PCLK / GP14  
T4  
R4  
P5  
R5  
XSPCS  
XSPDI  
XSPDO / MDIO  
XSPCLK / MDCLK  
R76  
10k  
TMX320DM642CGDK  
D3.3V  
R24  
NO POP  
D3.3V  
HWDTHSEL  
R25  
NO POP  
R23  
NO POP  
PCIEN  
R37  
1k  
TEXAS INSTRUMENTS, INC.  
12500 TI BLVD  
DALLAS, TEXAS 75243  
DM642 PCI/HPI/EMAC  
Size  
FCSM No.  
DWG No.  
Rev  
1
Orcad B  
Scale  
Sheet  
8 of 17  
1
2
3
4
5
6
Download from Www.Somanuals.com. All Manuals Search And Download.  
1
2
3
4
5
6
D
C
B
A
D
C
B
A
CORE CAPACITORS ARE 0402 SIZE  
D3.3V  
DSP_CVDD  
C7  
0.1uF  
C8  
C9  
C10  
C11  
C12  
U25C  
D3.3V  
DSP_CVDD  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
C16  
C20  
C21  
C25  
C29  
C32  
A2  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
DVDD  
0.01uF  
0.01uF  
0.01uF  
0.01uF  
0.01uF  
0.01uF  
F6  
F7  
F20  
F21  
G6  
A25  
B1  
CVDD  
D3.3V  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
CVDD  
B2  
DSP_CVDD  
B14  
B25  
B26  
C3  
C24  
D4  
G7  
G8  
C37  
C40  
C43  
C46  
C13  
C17  
C22  
C26  
C30  
C33  
G10  
G11  
G13  
G14  
G16  
G17  
G19  
G20  
G21  
H20  
K7  
K20  
L7  
L20  
M12  
M14  
N7  
N13  
N15  
N20  
P7  
P12  
P14  
P20  
R13  
R15  
T7  
T20  
U7  
U20  
W20  
Y6  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
0.01uF  
0.01uF  
0.01uF  
0.01uF  
0.01uF  
0.01uF  
D23  
E5  
E7  
E8  
D3.3V  
DSP_CVDD  
E10  
E17  
E19  
E20  
E22  
F9  
F12  
F15  
F18  
C35  
C38  
C41  
C44  
C48  
C49  
C14  
C19  
C23  
C27  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
0.01uF 0.01uF  
0.01uF  
0.01uF  
G5  
D3.3V  
G22  
H5  
H22  
J6  
DSP_CVDD  
C36  
C39  
C42  
C45  
C47  
C50  
C15  
C18  
C24  
C28  
C31  
C34  
J21  
K5  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
0.01uF 0.01uF  
0.01uF  
0.01uF  
0.01uF  
0.01uF  
K22  
M6  
M21  
N2  
P25  
R21  
U5  
U22  
V21  
W5  
D3.3V  
DSP_CVDD  
C57  
C59  
C63  
0.1uF  
C66  
0.1uF  
C69  
C51  
C52  
C53  
C54  
C55  
C56  
0.1uF  
0.1uF  
0.1uF  
0.01uF 0.01uF  
0.01uF  
0.01uF  
0.01uF  
0.01uF  
Y7  
Y8  
W22  
W25  
Y5  
Y10  
Y11  
Y13  
Y14  
Y16  
Y17  
Y19  
Y20  
Y21  
AA6  
AA7  
AA20  
AA21  
DSP_CVDD  
Y22  
AA9  
AA12  
AA15  
AA18  
AB5  
AB7  
AB8  
AB10  
AB17  
AB19  
AB20  
AB22  
AC23  
AD24  
AE1  
AE2  
AE13  
AE25  
AE26  
AF2  
AF25  
D3.3V  
C170  
+
C171  
+
C172  
+
C58  
C60  
C61  
0.1uF  
C64  
C67  
C71  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
10uF  
10uF  
10uF  
D3.3V  
C62  
C65  
C68  
C70  
0.1uF  
D3.3V  
DSP_CVDD  
0.1uF  
0.1uF  
0.1uF  
D3.3V  
R90  
R91  
0
0
H7  
R6  
CVDDMON  
DVDDMON  
VSSMON  
W7  
C173  
+
C174  
C175  
+
+
33uF  
33uF  
33uF  
TMX320DM642CGDK  
101562-0001  
TEXAS INSTRUMENTS, INC.  
12500 TI BLVD  
DALLAS, TEXAS 75243  
DM642 POWER PINS  
FCSM No.  
Size  
C
DWG No.  
Rev  
1
Scale  
Sheet  
9 of 17  
6
1
2
3
4
5
Download from Www.Somanuals.com. All Manuals Search And Download.  
1
2
3
4
5
6
D
C
B
A
D
C
B
A
TED[31..0]  
TEA[22..3]  
TED[31..0]  
TEA[22..3]  
D3.3V  
C72  
C73  
0.1uF  
0.1uF  
U4  
TEA3  
TEA4  
TEA5  
TEA6  
TEA7  
TEA8  
TEA9  
TEA10 14  
TEA11  
TEA12  
TEA13 36  
TEA14  
TEA15  
TEA16  
TEA17  
TEA18  
TEA19  
21  
20  
19  
18  
17  
16  
15  
25  
TED0  
TED1  
TED2  
TED3  
TED4  
TED5  
TED6  
TED7  
A0  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
26  
27  
28  
32  
33  
34  
35  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
8
7
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
6
5
4
3
2
1
D3.3V  
R49  
10k  
R50  
10k  
R51  
10k  
R52  
10k  
TEA20 40  
TEA21 13  
37  
38  
29  
GP13_A19  
GP14_A20  
GP15_A21  
12  
RDY-BY  
22  
24  
9
TCE1#  
TSDCAS#  
TSDWE#  
CE  
OE  
WE  
10  
/RESET  
RESET  
ACC  
D3.3V  
R53  
10k  
11  
R26  
NO POP  
AM29LV033C-90EI  
TEXAS INSTRUMENTS, INC.  
12500 TI BLVD  
DALLAS, TEXAS 75243  
FLASH MEMORY  
FCSM No.  
Size  
C
DWG No.  
Rev  
1
Scale  
Sheet  
14 of 17  
6
1
2
3
4
5
Download from Www.Somanuals.com. All Manuals Search And Download.  
1
2
3
4
5
6
D
C
B
A
D
C
B
A
3.3V_SUPPLY  
D5V  
C74  
0.1uF  
C75  
0.1uF  
C76  
0.1uF  
C77  
0.1uF  
C78  
0.1uF  
3.3V_SUPPLY  
TP19  
TP  
TP20  
TP  
TP21  
TP  
TP22  
TP  
U5  
Vcc  
Vcc  
42  
31  
7
18  
Vcc  
Vcc  
D5V  
U6  
CLK/I0 VCC  
I1  
I2  
I3  
I4  
I5  
I6  
I7  
I8  
I9  
I10  
GND  
47  
46  
44  
43  
41  
40  
38  
37  
36  
35  
33  
32  
30  
29  
27  
26  
2
3
5
6
8
9
11  
12  
13  
14  
16  
17  
19  
20  
22  
23  
SCLK  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
SCK4  
1A1  
1A2  
1A3  
1A4  
1A5  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
2A4  
2A5  
2A6  
2A7  
2A8  
1B1  
1B2  
1B3  
1B4  
1B5  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
2B4  
2B5  
2B6  
2B7  
2B8  
CH4_OUT0  
CH4_OUT1  
CH4_OUT2  
CH4_OUT3  
CH4_OUT4  
CH4_OUT5  
CH4_OUT6  
CH4_OUT7  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
I/O9  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
I/O2  
I/O1  
I/O0  
I11  
CH4_OUT[7..0]  
10  
11  
12  
CH4_OUT[7..0]  
PALCE22V10H-10PC/5  
3.3V_SUPPLY  
48  
1
25  
24  
1OE  
1DIR  
2OE  
2DIR  
4
10  
15  
21  
28  
34  
39  
45  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
SN74LVT16245BDGGR  
#OE DIR OPERATION  
L
L
H
L
H
X
A <--- B  
A ---> B  
ISOLATION  
TEXAS INSTRUMENTS, INC.  
12500 TI BLVD  
DALLAS, TEXAS 75243  
F&V BIT BREAKOUT  
FCSM No.  
Size  
C
DWG No.  
Rev  
1
Scale  
Sheet  
12 of 17  
6
1
2
3
4
5
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2
3
4
5
6
D
C
B
A
D
C
B
A
D5V  
H1  
1
3
5
7
9
2
4
6
8
10  
12  
SCL  
SDA  
SCL  
SDA  
11  
HEADER 6X2  
/RESET  
CH1_OUT[7..0]  
H2  
CH1_OUT[7..0]  
CH1_OUT0  
1
3
5
7
2
4
6
CH1_OUT1  
CH1_OUT2  
CH1_OUT3  
CH1_OUT4  
CH1_OUT5  
CH1_OUT6  
CH1_OUT7  
8
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
SCKS1  
SCK1  
VB1  
AV1  
HS1  
SCKS1  
SCK1  
VB1  
AV1  
HS1  
VS1  
FID1  
VS1  
FID1  
HEADER 16X2  
CH2_OUT[7..0]  
CH3_OUT[7..0]  
CH4_OUT[7..0]  
H3  
CH2_OUT[7..0]  
CH2_OUT0  
CH2_OUT1  
CH2_OUT2  
CH2_OUT3  
CH2_OUT4  
CH2_OUT5  
CH2_OUT6  
CH2_OUT7  
1
3
5
7
2
4
6
8
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
SCKS2  
SCK2  
VB2  
AV2  
HS2  
SCKS2  
SCK2  
VB2  
AV2  
HS2  
VS2  
FID2  
VS2  
FID2  
HEADER 16X2  
H4  
CH3_OUT[7..0]  
CH3_OUT0  
CH3_OUT1  
CH3_OUT2  
CH3_OUT3  
CH3_OUT4  
CH3_OUT5  
CH3_OUT6  
CH3_OUT7  
1
3
5
7
2
4
6
8
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
SCKS3  
SCK3  
VB3  
AV3  
HS3  
VS3  
FID3  
SCKS3  
SCK3  
VB3  
AV3  
HS3  
VS3  
FID3  
HEADER 16X2  
H5  
CH4_OUT[7..0]  
CH4_OUT0  
CH4_OUT1  
CH4_OUT2  
CH4_OUT3  
CH4_OUT4  
CH4_OUT5  
CH4_OUT6  
CH4_OUT7  
1
3
5
7
2
4
6
8
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
SCKS4  
SCK4  
VB4  
AV4  
HS4  
SCKS4  
SCK4  
VB4  
AV4  
HS4  
VS4  
FID4  
VS4  
FID4  
HEADER 16X2  
TEXAS INSTRUMENTS, INC.  
12500 TI BLVD  
DALLAS, TEXAS 75243  
DAUGHTERCARD INTERFACE  
Size  
C
FCSM No.  
DWG No.  
Rev  
1
Scale  
Sheet  
3 of 17  
6
1
2
3
4
5
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3
4
5
6
CH1_AVDD CH2_AVDD CH3_AVDD CH4_AVDD AVDD_REF  
IOVDD  
C79  
0.1uF  
C81  
0.1uF  
C83  
0.1uF  
C85  
0.1uF  
C86  
0.1uF  
C88  
0.1uF  
C90  
0.1uF  
C92  
0.1uF  
C94  
0.1uF  
C96  
0.1uF  
P1  
SMA_PCB_MT_MOD  
R92  
0
1
CH1_PLL_VDD CH2_PLL_VDD CH3_PLL_VDD CH4_PLL_VDD  
DVDD  
50  
R101  
R93  
0
RN16  
RPACK8-33  
R102  
100k  
C80  
C82  
C84  
C87  
C89  
C91  
C93  
C95  
C97  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
CH1_D0  
CH1_D1  
CH1_D2  
CH1_D3  
CH1_D4  
CH1_D5  
CH1_D6  
CH1_D7  
CH1_OUT0  
CH1_OUT1  
CH1_OUT2  
CH1_OUT3  
CH1_OUT4  
CH1_OUT5  
CH1_OUT6  
CH1_OUT7  
D
C
B
A
D
C
B
A
Y4  
14.31818MHz  
C176  
33pF  
C177  
33pF  
CH1_D0  
CH1_D1  
CH1_D2  
CH1_D3  
CH1_D4  
CH1_D5  
CH1_D6  
CH1_D7  
CH1_OUT[7..0]  
CH1_OUT[7..0]  
CH2_OUT[7..0]  
CH3_OUT[7..0]  
CH4_OUT[7..0]  
CH4_AVDD  
INPUT V DIVIDER NETWORK  
FOR 0-0.75V INPUT RANGE  
CH3_PLL_VDD  
CH3_AVDD  
AVDD_REF  
RN15  
SCLKS1  
SCLK1  
GPCL1/VBLK1  
AVID1  
HSYNC1  
SCKS1  
SCK1  
VB1  
AV1  
HS1  
SCKS1  
SCK1  
VB1  
AV1  
HS1  
IOVDD  
DVDD  
SCLKS1  
SCLK1  
GPCL1/VBLK1  
AVID1  
CH1_AVDD  
REMEMBER 75ohm TERMINATION  
CH2_PLL_VDD  
HSYNC1  
VSYNC1/PALI1  
FID1/GLCO1  
VSYNC1/PALI1  
FID1/GLCO1  
VS1  
FID1  
VS1  
FID1  
CH2_AVDD  
CH4_PLL_VDD CH1_PLL_VDD  
RPACK8-33  
BNC1  
BNC_RA  
BNC5  
BNC_RA  
JP1  
JP5  
R10437.4  
R11237.4  
RN18  
RPACK8-33  
1
1A_IN  
1
2
CH1_A  
1
2
CH1_B  
U1  
R108  
37.4  
R116  
37.4  
CH2_D0  
CH2_D1  
CH2_D2  
CH2_D3  
CH2_D4  
CH2_D5  
CH2_D6  
CH2_D7  
CH2_OUT0  
CH2_OUT1  
CH2_OUT2  
CH2_OUT3  
CH2_OUT4  
CH2_OUT5  
CH2_OUT6  
CH2_OUT7  
1A_OUT  
1B_IN  
1B_OUT  
CH1_A C98  
CH1_B C99  
0.1uF  
0.1uF  
1
2
3
4
5
6
7
8
9
96  
95  
94  
93  
92  
91  
90  
89  
88  
87  
86  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
1A_IN  
2A_IN  
3A_IN  
4A_IN  
1A_OUT  
1B_IN  
2B_IN  
3B_IN  
4B_IN  
1B_OUT  
AI1GND  
AI1A  
AI1B  
IOGND  
VSYNC1/PALI1  
FID1/GLCO1  
CH2OUT0  
CH2OUT1  
CH2OUT2  
CH2OUT3  
CH2OUT4  
CH2OUT5  
CH2OUT6  
CH2OUT7  
SCLK2  
CH2_D0  
BNC2  
BNC_RA  
BNC6  
BNC_RA  
PLL_VDD  
PLL_GND  
REFM2  
REFP2  
AVDD  
AGND  
AI2GND  
AI2A  
JP2  
JP3  
JP4  
JP6  
JP7  
JP8  
CH2_D1  
CH2_D2  
CH2_D3  
CH2_D4  
CH2_D5  
CH2_D6  
CH2_D7  
R10537.4  
R11337.4  
2
CH2_A  
1
2
CH2_B  
REFM2  
CH2_OUT[7..0]  
REFP2  
R109  
37.4  
R117  
37.4  
RN17  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
SCLKS2  
SCLK2  
GPCL2/VBLK2  
AVID2  
HSYNC2  
VSYNC2/PALI2  
FID2/GLCO2  
SCKS2  
SCK2  
VB2  
AV2  
HS2  
VS2  
FID2  
SCKS2  
SCK2  
VB2  
AV2  
HS2  
VS2  
FID2  
2A_IN  
2A_OUT  
2B_IN  
2B_OUT  
CH2_A C100 0.1uF  
CH2_B C101 0.1uF  
2A_OUT  
2B_OUT  
SCLKS2  
SCLK2  
GPCL2/VBLK2  
AI2B  
PLL_VDD  
PLL_GND  
AVDD  
AGND  
REFM3  
REFP3  
AVDD  
AGND  
AI3GND  
AI3A  
CLK2  
INT2/GPCL2/VBLK2  
DGND  
BNC3  
BNC_RA  
BNC7  
BNC_RA  
R10637.4  
R11437.4  
1
2
CH3_A  
1
2
CH3_B  
DVDD  
IOVDD  
IOGND  
AVID2  
REFM3  
REFP3  
R110  
37.4  
R118  
37.4  
AVID2  
HSYNC2  
VSYNC2/PALI2  
FID2/GLCO2  
RPACK8-33  
HSYNC2  
3A_IN  
3A_OUT  
3B_IN  
3B_OUT  
CH3_A C102 0.1uF  
CH3_B C103 0.1uF  
3A_OUT  
3B_OUT  
VSYNC2/PALI2  
FID2/GLCO2  
CH3OUT0  
CH3OUT1  
CH3OUT2  
CH3OUT3  
CH3OUT4  
CH3OUT5  
CH3OUT6  
CH3OUT7  
DGND  
RN19  
RPACK8-33  
CH3_D0  
CH3_D1  
CH3_D2  
CH3_D3  
CH3_D4  
CH3_D5  
CH3_D6  
CH3_D7  
AI3B  
BNC4  
BNC_RA  
BNC8  
BNC_RA  
PLL_VDD  
PLL_GND  
REFM4  
REFP4  
AVDD  
AGND  
AI4GND  
AI4A  
CH3_D0  
CH3_D1  
CH3_D2  
CH3_D3  
CH3_D4  
CH3_D5  
CH3_D6  
CH3_D7  
CH3_OUT0  
R10737.4  
R11537.4  
1
2
CH4_A  
1
2
CH4_B  
REFM4  
REFP4  
CH3_OUT1  
CH3_OUT2  
CH3_OUT3  
CH3_OUT4  
CH3_OUT5  
CH3_OUT6  
CH3_OUT7  
R111  
37.4  
R119  
37.4  
4A_IN  
4A_OUT  
4B_IN  
4B_OUT  
CH4_A C104 0.1uF  
CH4_B C105 0.1uF  
4A_OUT  
4B_OUT  
AI4B  
DVDD  
CH3_OUT[7..0]  
RN20  
SCLKS3  
SCLK3  
GPCL3/VBLK3  
AVID3  
HSYNC3  
SCKS3  
SCK3  
VB3  
AV3  
HS3  
SCKS3  
SCK3  
VB3  
AV3  
HS3  
TVP5154PNP  
VSYNC3/PALI3  
FID3/GLCO3  
VS3  
FID3  
VS3  
FID3  
SCLKS3  
SCLK3  
GPCL3/VBLK3  
AVID3  
HSYNC3  
RPACK8-33  
RN22  
RPACK8-33  
I2C ADDRESS SELECTION  
POWERDOWN  
1-2 Normal Operation - Default  
VSYNC3/PALI3  
FID3/GLCO3  
CH4_D0  
CH4_D1  
CH4_D2  
CH4_D3  
CH4_D4  
CH4_D5  
CH4_D6  
CH4_D7  
CH4_OUT0  
CH4_D0  
CH4_OUT1  
CH4_OUT2  
CH4_OUT3  
CH4_OUT4  
CH4_OUT5  
CH4_OUT6  
CH4_OUT7  
CH4_D1  
CH4_D2  
CH4_D3  
CH4_D4  
CH4_D5  
CH4_D6  
CH4_D7  
2-3 Base Addr 0xB8 - Default  
2-3 Powerdown  
IOVDD  
IOVDD  
IOVDD  
CH4_OUT[7..0]  
SCLKS4  
SCLK4  
GPCL4/VBLK4  
AVID4  
HSYNC4  
R54  
10k  
R55  
10k  
R56  
10k  
RN21  
SCLKS4  
SCLK4  
GPCL4/VBLK4  
AVID4  
HSYNC4  
SCKS4  
SCK4  
VB4  
AV4  
HS4  
SCKS4  
SCK4  
VB4  
AV4  
HS4  
VSYNC4/PALI4  
FID4/GLCO4  
I2CSEL1  
2
JP9  
I2CSEL2  
2
JP10  
I2C ADR  
PDN  
2
JP11  
I2C ADR  
/PDN  
VSYNC4/PALI4  
FID4/GLCO4  
VS4  
FID4  
VS4  
FID4  
R57  
10k  
R58  
10k  
RPACK8-33  
SDA  
SCL  
SDA  
SCL  
C178  
1uF  
C180  
1uF  
C181  
1uF  
C183  
1uF  
C184  
1uF  
C186  
1uF  
C187  
1uF  
C189  
1uF  
/RESET  
/RESET  
C179  
C182  
C185  
1uF  
C188  
IOVDD  
TEXAS INSTRUMENTS, INC.  
12500 TI BLVD  
1uF  
1uF  
1uF  
DALLAS, TEXAS 75243  
R120  
100  
TMS  
TVP5154  
R59  
10k  
Size  
C
FCSM No.  
DWG No.  
Rev  
1
Scale  
Sheet  
2 of 17  
6
1
2
3
4
5
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1
2
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6
NOTE: FILTERS DESIGNED FOR CVBS INPUTS (ADC SAMPLING RATE = 27MHz)  
D
C
B
A
C202 8.2pF  
C203 8.2pF  
D
C
B
A
2.2uH  
2.2uH  
L4  
L5  
1A_IN  
1A_OUT  
2A_IN  
2A_OUT  
C210  
330pF  
C211  
330pF  
C212  
330pF  
C213  
330pF  
C204 8.2pF  
C206 8.2pF  
2.2uH  
2.2uH  
L6  
L7  
1B_IN  
1B_OUT  
2B_IN  
2B_OUT  
C214  
330pF  
C215  
330pF  
C216  
330pF  
C217  
330pF  
C205 8.2pF  
C2078.2pF  
2.2uH  
2.2uH  
L8  
L10  
3A_IN  
3A_OUT  
4A_IN  
4A_OUT  
C218  
330pF  
C220  
330pF  
C222  
330pF  
C224  
330pF  
C208 8.2pF  
C209 8.2pF  
2.2uH  
2.2uH  
L9  
L11  
3B_IN  
3B_OUT  
4B_IN  
4B_OUT  
C219  
330pF  
C221  
330pF  
C223  
330pF  
C225  
330pF  
TEXAS INSTRUMENTS, INC.  
12500 TI BLVD  
DALLAS, TEXAS 75243  
ANTI-ALIASING FILTERS  
Size  
B
FCSM No.  
DWG No.  
Rev  
1
Scale  
Sheet  
11 of 17  
1
2
3
4
5
6
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1
2
3
4
5
6
D
C
B
A
D
C
B
A
D3.3V  
C106  
0.1uF  
R83  
2.2k  
R84  
2.2k  
2.2k  
R82  
TP23  
TP  
P2  
U2C  
U2D  
R94  
0
1
14  
2
15  
3
16  
4
17  
5
18  
6
19  
7
20  
8
6
5
8
9
SCL  
SCL  
SN74AHC05DR  
SN74AHC05DR  
DB15  
DB17  
U2F  
13  
12  
D3.3V  
SN74AHC05DR  
R87  
2.2k  
R88  
2.2k  
21  
9
U2A  
DB9  
1
2
22  
10  
23  
11  
24  
12  
25  
13  
SN74AHC05DR  
TP24  
TP  
DB11  
U2B  
0
4
3
SDA  
SDA  
DB25F_182-25F-ND  
R95  
R85  
2.2k  
R86  
2.2k  
SN74AHC05DR  
U2E  
11  
10  
SN74AHC05DR  
TEXAS INSTRUMENTS, INC.  
12500 TI BLVD  
DALLAS, TEXAS 75243  
I2C  
Size  
C
FCSM No.  
DWG No.  
Rev  
1
Scale  
Sheet  
17 of 17  
6
1
2
3
4
5
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1
2
3
4
5
6
D3.3V  
D3.3V  
C107  
0.1uF  
C109  
0.1uF  
C111  
0.1uF  
C113  
0.1uF  
C115  
0.1uF  
C117  
0.1uF  
C119  
0.1uF  
C121  
0.1uF  
C123  
0.1uF  
C125  
0.1uF  
C127  
0.1uF  
C129  
0.1uF  
C108  
0.1uF  
C110  
0.1uF  
C112  
0.1uF  
C114  
0.1uF  
C116  
0.1uF  
C118  
0.1uF  
C120  
0.1uF  
C122  
0.1uF  
C124  
0.1uF  
C126  
0.1uF  
C128  
0.1uF  
C130  
0.1uF  
D
C
B
A
D
C
B
A
TED[63..0]  
TED[63..0]  
D3.3V  
D3.3V  
U7  
VDD  
D0  
VDDQ  
D1  
D2  
VSSQ  
D3  
D4  
VDDQ  
D5  
U8  
VDD  
D0  
VDDQ  
D1  
D2  
VSSQ  
D3  
D4  
VDDQ  
D5  
1
2
3
4
5
6
7
8
9
86  
1
2
3
4
5
6
7
8
9
86  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
VSS  
D15  
VSSQ  
D14  
D13  
VDDQ  
D12  
D11  
VSSQ  
D10  
D9  
VDDQ  
D8  
NC  
VSS  
DQM1  
NC  
VSS  
D15  
VSSQ  
D14  
D13  
VDDQ  
D12  
D11  
VSSQ  
D10  
D9  
VDDQ  
D8  
NC  
VSS  
DQM1  
NC  
TED7  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
TED15  
TED39  
TED47  
TED6  
TED5  
TED14  
TED13  
TED38  
TED37  
TED46  
TED45  
TED4  
TED3  
TED12  
TED11  
TED36  
TED35  
TED44  
TED43  
TED2  
TED1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
TED10  
TED9  
TED34  
TED33  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
TED42  
TED41  
D6  
VSSQ  
D7  
D6  
VSSQ  
D7  
TED0  
TED8  
TED32  
TED40  
NC  
NC  
VDD  
DQM0  
/WE  
/CAS  
/RAS  
/CS  
VDD  
DQM0  
/WE  
/CAS  
/RAS  
/CS  
TBE0#  
TBE1#  
TBE4#  
TSDWE#  
TSDCAS#  
TSDRAS#  
TCE0#  
TEA14  
TEA15  
TEA16  
TEA13  
TEA3  
TBE5#  
TBE0#  
TSDWE#  
TSDCAS#  
TSDRAS#  
TCE0#  
TSDWE#  
TSDCAS#  
TSDRAS#  
TCE0#  
NC  
NC  
TECLKOUT1  
TSDCKE  
TECLKOUT1  
TSDCKE  
CLK  
CKE  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
CLK  
CKE  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
TEA14  
TEA12  
TEA11  
TEA10  
TEA9  
TEA8  
TEA7  
TEA6  
TEA12  
TEA11  
TEA10  
TEA9  
TEA8  
TEA7  
TEA6  
A11  
A11  
TEA15  
TEA16  
TEA13  
TEA3  
TEA4  
TEA5  
BA0  
BA1  
A10/AP  
A0  
A1  
A2  
DQM2  
VDD  
NC  
D16  
VSSQ  
D17  
D18  
VDDQ  
D19  
D20  
VSSQ  
D21  
D22  
VDDQ  
D23  
BA0  
BA1  
A10/AP  
A0  
A1  
A2  
DQM2  
VDD  
NC  
D16  
VSSQ  
D17  
D18  
VDDQ  
D19  
D20  
VSSQ  
D21  
D22  
VDDQ  
D23  
TEA4  
TEA5  
TBE6#  
TBE2#  
TBE1#  
TBE3#  
TBE4#  
TBE5#  
TBE6#  
TBE7#  
TBE3#  
TBE7#  
TBE2#  
TBE1#  
TBE3#  
TBE4#  
TBE5#  
TBE6#  
TBE7#  
DQM3  
VSS  
NC  
DQM3  
VSS  
NC  
TED16  
TED31  
TED48  
TED63  
D31  
VDDQ  
D30  
D29  
VSSQ  
D28  
D27  
VDDQ  
D26  
D25  
VSSQ  
D24  
VSS  
D31  
VDDQ  
D30  
D29  
VSSQ  
D28  
D27  
VDDQ  
D26  
D25  
VSSQ  
D24  
VSS  
TED17  
TED18  
TED30  
TED29  
TED49  
TED50  
TED62  
TED61  
TSDCKE  
TED19  
TED20  
TED28  
TED27  
TED51  
TED52  
TED60  
TED59  
TSDCKE  
TECLKOUT1  
TECLKOUT1  
TED21  
TED22  
TED26  
TED25  
TED53  
TED54  
TED58  
TED57  
TED23  
TED24  
TED55  
TED56  
VDD  
VDD  
MT48LC4M32B2TG-6  
MT48LC4M32B2TG-6  
TEA[22..3]  
TEA[22..3]  
TEXAS INSTRUMENTS, INC.  
12500 TI BLVD  
DALLAS, TEXAS 75243  
SDRAM  
Size  
C
FCSM No.  
DWG No.  
Rev  
1
Scale  
Sheet  
13 of 17  
6
1
2
3
4
5
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1
2
3
4
5
6
D
C
B
A
D
C
B
A
ROUTE TRACES AS ONE GROUP. MATCH SIGNAL LENGTH.  
P3  
C2  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
EMU18  
B3  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
TYPE0  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
EMU17  
C4  
C5  
B5  
C6  
B6  
C7  
C9  
B9  
C10  
B10  
C11  
B11  
C12  
C13  
B13  
C14  
B14  
LOCATE R-PACK NEAR DSP  
EMU16  
EMU15  
EMU14  
EMU13  
EMU12  
EMU11  
EMU10  
EMU9  
EMU8  
EMU7  
EMU6  
EMU5  
EMU4  
EMU3  
EMU2  
EMU1  
EMU0  
TCKRTN  
TCLK  
TDO  
TDI  
TMS  
TRSTn  
ID3  
ID2  
ID1  
ID0  
TVD  
D3.3V  
DSP_EMU[11..0]  
RN23RPACK8-39  
DSP_EMU[11..0]  
DSP_EMU11  
DSP_EMU10  
DSP_EMU9  
DSP_EMU8  
DSP_EMU7  
DSP_EMU6  
DSP_EMU5  
DSP_EMU4  
H6  
A9  
XDS_TMS  
XDS_TDI  
1
3
5
7
9
2
4
XDS_TRST#  
XDS_EMU1  
A10  
A11  
A12  
A13  
A14  
A15  
XDS_TDO  
XDS_TCKRET  
XDS_TCK  
XDS_EMU0 13  
8
10  
12  
14  
11  
DSP_EMU3  
DSP_EMU2  
DSP_EMU1  
DSP_EMU0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
TYPE1  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
HEADER 7x2, Emulation  
XDS_EMU1  
XDS_EMU0  
XDS_TCKRET C8  
XDS_TCK  
XDS_TDO  
XDS_TDI  
XDS_TMS  
XDS_TRST#  
B12  
B7  
B4  
B2  
C3  
C15  
C1  
B15  
B1  
DSP_TDO  
D9  
RN24RPACK8-39  
D3.3V  
D10  
D11  
D12  
D13  
D14  
D15  
R38  
1k  
B8  
XDS_TDI  
XDS_TMS  
XDS_TRST#  
DSP_TDI  
DSP_TMS  
Samtec SOLC-115-02-S-Q-A  
DSP_TRST#  
D3.3V  
C131  
0.1uF  
U9  
XDS_TCK  
1
2
4
R4  
DSP_TCLK  
33  
SN74LVC1G32DCKR  
D3.3V  
C132  
0.1uF  
C226  
R121 100 1%  
U10  
1
2
4
R5  
XDS_TCKRET  
33  
18pF  
SN74LVC1G32DCKR  
TEXAS INSTRUMENTS, INC.  
12500 TI BLVD  
DALLAS, TEXAS 75243  
JTAG  
Size  
C
FCSM No.  
DWG No.  
Rev  
1
Scale  
Sheet  
15 of 17  
6
1
2
3
4
5
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1
2
3
4
5
6
7
8
RESET ON POWER UP  
POWER ON LED (+5V)  
5V, 3.0A DC INPUT  
D3.3V  
R103  
D
C
B
A
D5V  
D
C
B
A
100k  
D5V  
F1 FUSE  
L12  
U11  
1
C1330.1uF  
R122  
330  
P4  
PJ-002BH  
8
7
6
5
CONTROL  
/RESIN  
CT  
VDD  
SENSE  
RESET  
/RESET  
C227  
47uF  
C228  
22uF  
H7  
+
2
3
4
D1  
ZENER  
S1  
PB  
1
3
2
3
2
1
/RESET  
GND  
/RESET  
SS26  
C190  
1uF  
TLC7733IPWR  
LED1  
GRN_LED  
HEADER 3  
VOUT1 IS 3.3V 1A  
VOUT2 IS 1.8V 2A  
FB1  
FERRITE  
R123  
249k  
R96  
0
U12  
Connect at pin 1  
3.3 sq in AGND, min thermal pad  
R27  
NO POP  
D5V  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
GND  
GND  
VOUT1A  
VOUT1B  
VSENSE1/FB1  
NC  
3.3V_SUPPLY  
Sets Voltage  
VIN1A  
VIN1B  
NC  
/MR  
/EN1  
/EN2  
/RESET  
GND  
VIN2A  
VIN2B  
GND  
L13  
L14  
C229  
22uF  
C136  
0.1uF  
C231  
22uF  
C141  
0.1uF  
R124249k  
R125249k  
R129  
3.74k 1%  
PG1  
PG2  
NC  
R126  
1.8V_SUPPLY  
R127  
2k 1%  
C263  
8200pF  
VSENSE2/FB2  
VOUT2A  
VOUT2B  
GND  
10  
11  
12  
71.5k 1%  
EMI SUPPRESION. LOCATE NEAR EACH REGULATOR.  
C145  
C256  
TP25  
TP  
C260  
470pF  
D3.3V  
C230  
22uF  
C137  
0.1uF  
R28  
NO POP  
C232  
22uF  
C142  
0.1uF  
0.1uF  
0.039uF  
U13  
POWERPAD  
3300pF  
C266  
107 1%  
6 VIAS FROM PAD TO PLANE OR DIRECT TIE.  
0
R97  
TPS70451PWP  
21  
20  
19  
18  
17  
R132  
1
2
3
4
5
R60  
10k  
RT  
AGND  
VSENSE  
COMP  
PWRGD  
BOOT  
SYNC  
SS/ENA  
VBIAS  
1.8V_SUPPLY  
10k 1% R130  
J1  
L15  
JUMPER  
D5V  
C261  
16  
15  
14  
L17 2.7uH  
D3.3V  
C272  
VIN3  
VIN2  
VIN1  
0.047uF  
+
C255  
47uF  
BLM41P750SPT  
C258  
6
7
8
9
NO POP  
PH1  
PH2  
PH3  
PH4  
PH5  
+
C144  
0.1uF  
C146  
0.1uF  
+
H8  
CH1_AVDD  
13  
12  
11  
C270  
PGND3  
PGND2  
PGND1  
FB2  
10uF LESR  
C268  
1000pF  
D13  
100 uF  
1
2
10  
C264  
FERRITE  
C134  
C191  
C138  
0.1uF  
100uF  
MURS120T3  
C233  
C235  
HEADER 2  
TPS54310PWP  
3.3V @1.5Amp Max  
22uF 0.1uF  
22uF 1uF  
J2  
2
1
D14  
OPTIONAL CROSS COUPLE  
1.8V_SUPPLY  
MURS120T3  
J3  
JUMPER  
JUMPER  
1.4V -> 17.4K 1%  
1.2V -> 28.0K 1%  
1.1V -> 42.2K 1%  
Connect at pin 1  
3.3 sq in AGND, min thermal pad  
D15  
H9  
CH2_AVDD  
MURS120T3  
FB3  
H10  
CH1_PLL_VDD  
1
2
FB4  
R128  
17.4k 1%  
FERRITE  
1
2
C135  
C234  
C192  
C139  
0.1uF  
D16  
FERRITE  
C236  
C140  
C193  
C143  
0.1uF  
HEADER 2  
22uF 0.1uF  
22uF 1uF  
C237  
C238  
22uF 1uF  
HEADER 2  
R134  
71.5k 1%  
R135  
C274  
0.01uF  
MURS120T3  
22uF 0.1uF  
J4  
2
1.65k 1%  
J7  
2
1
C160  
0.1uF  
C257  
0.039uF  
C273  
560pF  
R133  
107 1%  
1
U14  
POWERPAD  
JUMPER  
21  
20  
19  
18  
17  
C267  
3300pF  
D17  
JUMPER  
1
2
3
4
5
RT  
AGND  
VSENSE  
COMP  
PWRGD  
BOOT  
MURS120T3  
SYNC  
SS/ENA  
VBIAS  
R131  
10k 1%  
L16  
H11  
CH3_AVDD  
C262  
FB5  
1.4V @1.5Amp Max  
DSP_CVDD  
H14  
CH2_PLL_VDD  
16  
15  
14  
L18 2.7uH  
1
2
VIN3  
VIN2  
VIN1  
FB8  
0.047uF  
FERRITE  
1
2
C147  
C239  
C194  
C150  
0.1uF  
BLM41P750SPT  
C259  
6
7
8
9
FERRITE  
PH1  
PH2  
PH3  
PH4  
PH5  
+
C242  
C153  
C245  
22uF 0.1uF  
C197  
C156  
0.1uF  
HEADER 2  
C159  
0.1uF  
C161  
0.1uF  
22uF 0.1uF  
22uF 1uF  
C248  
22uF 1uF  
HEADER 2  
13  
12  
11  
C271  
PGND3  
PGND2  
PGND1  
+
J5  
2
10uF LESR  
C269  
1000pF  
J8  
2
10  
C265  
100 uF  
100uF  
1
TPS54310PWP  
JUMPER  
1
JUMPER  
FB11  
FERRITE  
H12  
CH4_AVDD  
FB6  
H15  
CH3_PLL_VDD  
1
2
POWER ESTIMATES BASED ON SPRU190  
1.4V@600MHz 1.09 W 0.778A  
3.3V@600MHz 0.52 W 0.157A ( no emif clk)  
FB9  
FERRITE  
1
2
C148  
C240  
C195  
C151  
0.1uF  
FERRITE  
C243  
C154  
C246  
22uF 0.1uF  
C198  
C157  
0.1uF  
HEADER 2  
22uF 0.1uF  
22uF 1uF  
C249  
22uF 1uF  
HEADER 2  
J6  
2
J9  
2
MEASURED CURRENT ON C6416TEB, ~0.7A@5V  
1
1
EACH REGULATOR CAN SUPPLY UP TO 3A OF CURRENT. HOWEVER COMPONENT VALUES HAVE BEEN SELECTED FOR 1.5A OPERATION.  
JUMPER  
JUMPER  
VALUES CALCULATED WITH SWIFT DESIGN TOOL 2.0.  
FOLLOW TPS54310 EVM LAYOUT  
H13  
AVDD_REF  
H16  
CH4_PLL_VDD  
FB7  
FB10  
1
2
1
2
FERRITE  
FERRITE  
C149  
C241  
C196  
C152  
0.1uF  
C155  
C247  
22uF 0.1uF  
C199  
C158  
0.1uF  
C244  
C250  
22uF 1uF  
HEADER 2  
HEADER 2  
22uF 0.1uF  
22uF 1uF  
3.3V_SUPPLY  
J10  
JUMPER  
TP26  
TP29  
TP  
TP32  
TP  
TP35  
TP  
TP38  
TP  
FB14  
FB16  
FB18  
TP  
D3.3V  
D5V  
FERRITE  
FERRITE  
FERRITE  
H17  
IOVDD  
FB12  
1
2
FB15  
FB17  
FERRITE  
FB19  
TP27  
TP  
TP30  
TP  
TP33  
TP  
TP36  
TP  
TP39  
TP  
FERRITE  
C162  
C251  
C200  
C164  
0.1uF  
FERRITE  
FERRITE  
C253  
HEADER 2  
22uF 0.1uF  
22uF 1uF  
1.8V_SUPPLY  
J11  
JUMPER  
TP28  
TP  
TP31  
TP  
TP34  
TP  
TP37  
TP  
TP40  
TP  
DSP_CVDD  
H18  
DVDD  
FB13  
1
2
FERRITE  
C163  
C252  
C201  
C165  
0.1uF  
C254  
HEADER 2  
22uF 0.1uF  
22uF 1uF  
TEXAS INSTRUMENTS, INC.  
12500 TI BLVD  
DALLAS, TEXAS 75243  
POWER  
Size  
D
FCSM No.  
DWG No.  
Rev  
1
Scale  
Sheet  
7 of 17  
1
2
3
4
5
6
7
8
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1
2
3
4
5
6
D
C
B
A
D
C
B
A
D5V  
D5V  
D5V  
D5V  
P5  
30  
60  
90  
120  
119  
118  
117  
116  
115  
114  
113  
112  
111  
110  
109  
108  
107  
106  
105  
104  
103  
102  
101  
100  
99  
5V  
5V  
GND  
GND  
5V  
5V  
GND  
GND  
5V  
GND  
GND ENC_C[7..0]  
RCr9  
RCr8  
RCr7  
RCr6  
RCr5  
RCr4  
RCr3  
RCr2  
RCr1  
RCr0  
GND ENC_Y[7..0]  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
GND  
RESET  
PALI  
HSYNC  
AVID  
PREF  
5V  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
89  
88  
87  
86  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
GND  
GND  
BCb9  
BCb8  
BCb7  
BCb6  
BCb5  
BCb4  
BCb3  
BCb2  
BCb1  
BCb0  
GND  
GY9  
GY8  
GY7  
GY6  
GY5  
GY4  
GY3  
GY2  
GY1  
ENC_C[7..0]  
ENC_C7  
ENC_C6  
ENC_C5  
ENC_C4  
ENC_C3  
ENC_C2  
ENC_C1  
ENC_C0  
GND  
GND  
SCL  
SDA  
SCL/PHI_ACK  
SDA/PHI_RWW  
PHI_DS/RD  
PHI_CS  
PHI_A1  
PHI_A0  
PHI_D7  
PHI_D6  
PHI_D5  
PHI_D4  
PHI_D3  
PHI_D2  
PHI_D1  
PHI_D0  
AMXCLK  
ALRCLK  
ASCLK  
AMCLK  
GND  
GPIO7  
GPIO6  
GPIO5  
GPIO4  
GND  
GPIO3  
GPIO2  
GPIO1  
GPIO0  
INTREQ  
GPCL  
ENC_Y[7..0]  
ENC_Y7  
ENC_Y6  
ENC_Y5  
ENC_Y4  
ENC_Y3  
ENC_Y2  
ENC_Y1  
ENC_Y0  
GND  
CLK5/M1  
FPDAT/VSYA/M2  
FFRSTW/CBFLAG  
FSY/HC/HSYA/~BLNK  
VGAV/SYNC_T  
FFIE/CCVALID  
FFWE/DVALID  
FFRSTWIN/~SCLK  
FFRE/DIG_H  
GND  
8
7
6
5
4
3
2
1
98  
97  
96  
95  
94  
93  
92  
91  
ITRDY  
SOGOUT  
VACTIVE  
D_SCLK  
D_RDY  
D_PREF  
D_HS  
GY0  
GND  
FID  
GLCO  
VSYNC  
PCLK  
SCLK  
R99  
0
0
/RESET  
ENC_FID  
ENC_VS  
ENC_SCLK  
R100  
ENC_HS  
0
R98  
FFOE/DIG_V  
D_VS  
SAMTEC_TMMS_120PIN_M_RA  
TEXAS INSTRUMENTS, INC.  
12500 TI BLVD  
DALLAS, TEXAS 75243  
CONNECTOR  
FCSM No.  
Size  
C
DWG No.  
Rev  
1
Scale  
Sheet  
16 of 17  
6
1
2
3
4
5
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amplifier.ti.com  
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dsp.ti.com  
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power.ti.com  
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microcontroller.ti.com  
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