Texas Instruments Computer Hardware MSP430x1xx User Manual

Digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.1

9.2

Digital I/O Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

Digital I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.2.1 Input Register PnIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.2.2 Output Registers PnOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.2.3 Direction Registers PnDIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.2.4 Function Select Registers PnSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9.2.5 P1 and P2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.2.6 Configuring Unused Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

Digital I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

9.3

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Contents

10 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.1 Watchdog Timer Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.2 Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

10.2.1 Watchdog Timer Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

10.2.2 Watchdog Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

10.2.3 Interval Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

10.2.4 Watchdog Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.2.5 Operation in Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

10.2.6 Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

10.3 Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

11 Timer_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.1 Timer_A Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.2 Timer_A Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

11.2.1 16-Bit Timer Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

11.2.2 Starting the Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.2.3 Timer Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.2.4 Capture/Compare Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11

11.2.5 Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13

11.2.6 Timer_A Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17

11.3 Timer_A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19

12 Timer_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

12.1 Timer_B Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

12.1.1 Similarities and Differences From Timer_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

12.2 Timer_B Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

12.2.1 16-Bit Timer Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

12.2.2 Starting the Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5

12.2.3 Timer Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5

12.2.4 Capture/Compare Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11

12.2.5 Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14

12.2.6 Timer_B Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18

12.3 Timer_B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20

13 USART Peripheral Interface, UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1

13.1 USART Introduction: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

13.2 USART Operation: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4

13.2.1 USART Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4

13.2.2 Character Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4

13.2.3 Asynchronous Communication Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5

13.2.4 USART Receive Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9

13.2.5 USART Transmit Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10

13.2.6 UART Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11

13.2.7 USART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17

13.3 USART Registers: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21

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Contents

14 USART Peripheral Interface, SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

14.1 USART Introduction: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

14.2 USART Operation: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4

14.2.1 USART Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4

14.2.2 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5

14.2.3 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6

14.2.4 SPI Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7

14.2.5 Serial Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9

14.2.6 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11

14.3 USART Registers: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13

15 USART Peripheral Interface, I C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1

15.1 I C Module Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2

15.2 I C Module Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

15.2.1 I C Module Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5

15.2.2 I C Serial Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6

15.2.3 I C Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7

15.2.4 I C Module Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8

15.2.5 The I C Data Register I2CDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15

15.2.6 I C Clock Generation and Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16

15.2.7 Using the I C Module with Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . 15-17

15.2.8 I C Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18

15.3 I C Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20

16 Comparator_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1

16.1 Comparator_A Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2

16.2 Comparator_A Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4

16.2.1 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4

16.2.2 Input Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4

16.2.3 Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5

16.2.4 Voltage Reference Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5

16.2.5 Comparator_A, Port Disable Register CAPD . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6

16.2.6 Comparator_A Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6

16.2.7 Comparator_A Used to Measure Resistive Elements . . . . . . . . . . . . . . . . . . . . 16-7

16.3 Comparator_A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9

17 ADC12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1

17.1 ADC12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

17.2 ADC12 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

17.2.1 12-Bit ADC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

17.2.2 ADC12 Inputs and Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5

17.2.3 Voltage Reference Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6

17.2.4 Auto Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6

17.2.5 Sample and Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7

17.2.6 Conversion Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10

17.2.7 ADC12 Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10

17.2.8 Using the Integrated Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16

17.2.9 ADC12 Grounding and Noise Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 17-17

17.2.10 ADC12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18

17.3 ADC12 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20

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Contents

18 ADC10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1

18.1 ADC10 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2

18.2 ADC10 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4

18.2.1 10-Bit ADC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4

18.2.2 ADC10 Inputs and Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5

18.2.3 Voltage Reference Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6

18.2.4 Auto Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6

18.2.5 Sample and Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7

18.2.6 Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9

18.2.7 ADC10 Data Transfer Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15

18.2.8 Using the Integrated Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21

18.2.9 ADC10 Grounding and Noise Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 18-22

18.2.10 ADC10 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-23

18.3 ADC10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24

19 DAC12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1

19.1 DAC12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

19.2 DAC12 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4

19.2.1 DAC12 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4

19.2.2 DAC12 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5

19.2.3 Updating the DAC12 Voltage Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5

19.2.4 DAC12_xDAT Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6

19.2.5 DAC12 Output Amplifier Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7

19.2.6 Grouping Multiple DAC12 Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8

19.2.7 DAC12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9

19.3 DAC12 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10

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Chapter 1

Introduction

This chapter describes the architecture of the MSP430.

Topic

Page

1.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 Flexible Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.3 Embedded Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.4 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Introduction

1-1

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Architecture

1.1 Architecture

The MSP430 incorporates a 16-bit RISC CPU, peripherals, and a flexible clock

system that interconnect using a von-Neumann common memory address

bus (MAB) and memory data bus (MDB). Partnering a modern CPU with

modular memory-mapped analog and digital peripherals, the MSP430 offers

solutions for demanding mixed-signal applications.

Key features of the MSP430x1xx family include:

- Ultralow-power architecture extends battery life

0.1-µA RAM retention

0.8-µA real-time clock mode

250-µA / MIPS active

- High-performance analog ideal for precision measurement

12-bit or 10-bit ADC — 200 ksps, temperature sensor, V

12-bit dual-DAC

Ref

Comparator-gated timers for measuring resistive elements

Supply voltage supervisor

- 16-bit RISC CPU enables new applications at a fraction of the code size.

Large register file eliminates working file bottleneck

Compact core design reduces power consumption and cost

Optimized for modern high-level programming

Only 27 core instructions and seven addressing modes

Extensive vectored-interrupt capability

- In-system programmable Flash permits flexible code changes, field

upgrades and data logging

1.2 Flexible Clock System

The clock system is designed specifically for battery-powered applications. A

low-frequency auxiliary clock (ACLK) is driven directly from a common 32-kHz

watch crystal. The ACLK can be used for a background real-time clock self

wake-up function. An integrated high-speed digitally controlled oscillator

(DCO) can source the master clock (MCLK) used by the CPU and high-speed

peripherals. By design, the DCO is active and stable in less than 6 µs.

MSP430-based solutions effectively use the high-performance 16-bit RISC

CPU in very short bursts.

- Low-frequency auxiliary clock = Ultralow-power stand-by mode

- High-speed master clock = High performance signal processing

1-2

Introduction

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Embedded Emulation

Figure 1−1. MSP430 Architecture

ACLK

Clock

System

Flash/

ROM

RAM

Peripheral

SMCLK

MCLK

MAB 16-Bit

RISC CPU

16-Bit

Bus

Conv.

MDB 16-Bit

MDB 8-Bit

JTAG

ACLK

SMCLK

Peripheral

Watchdog Peripheral

1.3 Embedded Emulation

Dedicated embedded emulation logic resides on the device itself and is

accessed via JTAG using no additional system resources.

The benefits of embedded emulation include:

- Unobtrusive development and debug with full-speed execution,

breakpoints, and single-steps in an application are supported.

- Development is in-system subject to the same characteristics as the final

application.

- Mixed-signal integrity is preserved and not subject to cabling interference.

Introduction

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Address Space

1.4 Address Space

The MSP430 von-Neumann architecture has one address space shared with

special function registers (SFRs), peripherals, RAM, and Flash/ROM memory

as shown in Figure 1−2. See the device-specific data sheets for specific

memory maps. Code access are always performed on even addresses. Data

can be accessed as bytes or words.

The addressable memory space is 64 KB with future expansion planned.

Figure 1−2. Memory Map

Access

0FFFFh

Word/Byte

Interrupt Vector Table

Flash/ROM

0FFE0h

0FFDFh

Word/Byte

Word

RAM

0200h

01FFh

16-Bit Peripheral Modules

0100h

0FFh

Byte

8-Bit Peripheral Modules

Special Function Registers

010h

0Fh

1.4.1 Flash/ROM

The start address of Flash/ROM depends on the amount of Flash/ROM

present and varies by device. The end address for Flash/ROM is 0FFFFh.

Flash can be used for both code and data. Word or byte tables can be stored

and used in Flash/ROM without the need to copy the tables to RAM before

using them.

The interrupt vector table is mapped into the upper 16 words of Flash/ROM

address space, with the highest priority interrupt vector at the highest

Flash/ROM word address (0FFFEh).

1.4.2 RAM

RAM starts at 0200h. The end address of RAM depends on the amount of RAM

present and varies by device. RAM can be used for both code and data.

1-4

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Address Space

1.4.3 Peripheral Modules

Peripheral modules are mapped into the address space. The address space

from 0100 to 01FFh is reserved for 16-bit peripheral modules. These modules

should be accessed with word instructions. If byte instructions are used, only

even addresses are permissible, and the high byte of the result is always 0.

The address space from 010h to 0FFh is reserved for 8-bit peripheral modules.

These modules should be accessed with byte instructions. Read access of

byte modules using word instructions results in unpredictable data in the high

byte. If word data is written to a byte module only the low byte is written into

the peripheral register, ignoring the high byte.

1.4.4 Special Function Registers (SFRs)

Some peripheral functions are configured in the SFRs. The SFRs are located

in the lower 16 bytes of the address space, and are organized by byte. SFRs

must be accessed using byte instructions only. See the device-specific data

sheets for applicable SFR bits.

1.4.5 Memory Organization

Bytes are located at even or odd addresses. Words are only located at even

addresses as shown in Figure 1−3. When using word instructions, only even

addresses may be used. The low byte of a word is always an even address.

The high byte is at the next odd address. For example, if a data word is located

at address xxx4h, then the low byte of that data word is located at address

xxx4h, and the high byte of that word is located at address xxx5h.

Figure 1−3. Bits, Bytes, and Words in a Byte-Organized Memory

xxxAh

xxx9h

xxx8h

. . Bits . .

Byte

xxx7h

xxx6h

Byte

Word (High Byte)

Word (Low Byte)

xxx5h

xxx4h

xxx3h

Introduction

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1-6

Introduction

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Chapter 2

System Resets, Interrupts,

and Operating Modes

This chapter describes the MSP430x1xx system resets, interrupts, and

operating modes.

Topic

Page

2.1 System Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.4 Principles for Low-Power Applications . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.5 Connection of Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

System Resets, Interrupts, and Operating Modes

2-1

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System Reset and Initialization

2.1 System Reset and Initialization

The system reset circuitry shown in Figure 2−1 sources both a power-on reset

(POR) and a power-up clear (PUC) signal. Different events trigger these reset

signals and different initial conditions exist depending on which signal was

generated.

Figure 2−1. Power-On Reset and Power-Up Clear Schematic

Brownout

Reset

POR

DDeetteecctt

POR

Delay

‡

POR

Latch

POR

0 V

~ 50us

Delay

SVS_POR^§

RST/NMI

†

WDTNMI

†

WDTSSEL

WDTQn

WDTIFG

PUC

Latch

Resetwd1

PUC

†

Resetwd2

EQU

KEYV

(from flash module)

MCLK

† From watchdog timer peripheral module

‡ Devices with BOR only

# Devices without BOR only

§ Devices with SVS only

A POR is a device reset. A POR is only generated by the following three

events:

- Powering up the device

- A low signal on the RST/NMI pin when configured in the reset mode

- An SVS low condition when PORON = 1.

A PUC is always generated when a POR is generated, but a POR is not

generated by a PUC. The following events trigger a PUC:

- A POR signal

- Watchdog timer expiration when in watchdog mode only

- Watchdog timer security key violation

- A Flash memory security key violation

2-2

System Resets, Interrupts, and Operating Modes

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System Reset and Initialization

2.1.1 Power-On Reset (POR)

When the V

rise time is slow, the POR detector holds the POR signal active

until V

has risen above the V

level, as shown in Figure 2−2. When the

POR

supply provides a fast rise time the POR delay, t

, provides

(POR_DELAY)

active time on the POR signal to allow the MSP430 to initialize.

If power to the MSP430 is cycled, the supply voltage V must fall below V

min

to ensure that another POR signal occurs when V

is powered up again. If

does not fall below V

during a cycle or a glitch, a POR is not generated

min

and power-up conditions do not set correctly. See device-specific datasheet

for parameters.

Figure 2−2. POR Timing

CC(min)

POR

No POR

min

Set Signal for

POR circuitry

(POR_DELAY)

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System Reset and Initialization

2.1.2 Brownout Reset (BOR)

Some devices have a brownout reset circuit (see device-specific datasheet)

that replaces the POR detect and POR delay circuits. The brownout reset

circuit detects low supply voltages such as when a supply voltage is applied

to or removed from the V

terminal. The brownout reset circuit resets the

device by triggering a POR signal when power is applied or removed. The

operating levels are shown in Figure 2−3.

The POR signal becomes active when V

crosses the V

level. It

CC(start)

remains active until V

crosses the V

threshold and the delay t

(B_IT+) (BOR)

elapses. The delay t

is adaptive being longer for a slow ramping V

The

(BOR)

CC.

hysteresis V

ensures that the supply voltage must drop below

hys(B_ IT−)

to generate another POR signal from the brownout reset circuitry.

(B_IT−)

Figure 2−3. Brownout Timing

hys(B_IT−)

(B_IT+)

(B_IT−)

CC(start)

Set Signal for

POR circuitry

(BOR)

As the V

level is significantly above the V

level of the POR circuit, the

(B_IT−)

min

BOR provides a reset for power failures where V

does not fall below V

min.

See device-specific datasheet for parameters.

2-4

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System Reset and Initialization

2.1.3 Device Initial Conditions After System Reset

After a POR, the initial MSP430 conditions are:

- The RST/NMI pin is configured in the reset mode.

- I/O pins are switched to input mode as described in the Digital I/O chapter.

- Other peripheral modules and registers are initialized as described in their

respective chapters in this manual.

- Status register (SR) is reset.

- The watchdog timer powers up active in watchdog mode.

- Program counter (PC) is loaded with address contained at reset vector

location (0FFFEh). CPU execution begins at that address.

Software Initialization

After a system reset, user software must initialize the MSP430 for the

application requirements. The following must occur:

- Initialize the SP, typically to the top of RAM.

- Initialize the watchdog to the requirements of the application.

- Configure peripheral modules to the requirements of the application.

Additionally, the watchdog timer, oscillator fault, and flash memory flags can

be evaluated to determine the source of the reset.

System Resets, Interrupts, and Operating Modes

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System Reset and Initialization

2.2 Interrupts

The interrupt priorities are fixed and defined by the arrangement of the

modules in the connection chain as shown in Figure 2−4. The nearer a module

is to the CPU/NMIRS, the higher the priority. Interrupt priorities determine what

interrupt is taken when more than one interrupt is pending simultaneously.

There are three types of interrupts:

- System reset

- (Non)-maskable NMI

- Maskable

Figure 2−4. Interrupt Priority

Priority

High

Low

GMIRS

GIE

Module

WDT

Timer

Module

CPU

NMIRS

PUC

Bus

Grant

PUC

OSCfault

Circuit

Flash ACCV

Reset/NMI

WDT Security Key

Flash Security Key

MAB − 5LSBs

2-6

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System Reset and Initialization

2.2.1 (Non)-Maskable Interrupts (NMI)

(Non)-maskable NMI interrupts are not masked by the general interrupt enable

bit (GIE), but are enabled by individual interrupt enable bits (NMIIE, ACCVIE,

OFIE). When a NMI interrupt is accepted, all NMI interrupt enable bits are

automatically reset. Program execution begins at the address stored in the

(non)-maskable interrupt vector, 0FFFCh. User software must set the required

NMI interrupt enable bits for the interrupt to be re-enabled. The block diagram

for NMI sources is shown in Figure 2−5.

A (non)-maskable NMI interrupt can be generated by three sources:

- An edge on the RST/NMI pin when configured in NMI mode

- An oscillator fault occurs

- An access violation to the flash memory

Reset/NMI Pin

At power-up, the RST/NMI pin is configured in the reset mode. The function

of the RST/NMI pins is selected in the watchdog control register WDTCTL. If

the RST/NMI pin is set to the reset function, the CPU is held in the reset state

as long as the RST/NMI pin is held low. After the input changes to a high state,

the CPU starts program execution at the word address stored in the reset

vector, 0FFFEh.

If the RST/NMI pin is configured by user software to the NMI function, a signal

edge selected by the WDTNMIES bit generates an NMI interrupt if the NMIIE

bit is set. The RST/NMI flag NMIIFG is also set.

Note: Holding RST/NMI Low

When configured in the NMI mode, a signal generating an NMI event should

not hold the RST/NMI pin low. If a PUC occurs from a different source while

the NMI signal is low, the device will be held in the reset state because a PUC

changes the RST/NMI pin to the reset function.

Note: Modifying WDTNMIES

When NMI mode is selected and the WDTNMIES bit is changed, an NMI can

be generated, depending on the actual level at the RST/NMI pin. When the

NMI edge select bit is changed before selecting the NMI mode, no NMI is

generated.

System Resets, Interrupts, and Operating Modes

2-7

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System Reset and Initialization

Figure 2−5. Block Diagram of (Non)-Maskable Interrupt Sources

ACCV

ACCVIFG

FCTL1.1

ACCVIE

IE1.5

Clear

Flash Module

PUC

RST/NMI

POR

PUC

KEYV

PUC

POR

System Reset

Generator

NMIIFG

NMIRS

IFG1.4

WDTTMSEL

WDTNMI

Clear

WDTQn

EQU

PUC

POR

WDTNMIES

PUC

NMIIE

WDTIFG

IE1.4

IRQ

Clear

IFG1.0

Clear

PUC

WDT

Counter

OSCFault

POR

OFIFG

OFIE

IFG1.1

IRQA

WDTTMSEL

WDTIE

IE1.1

PUC

Clear

IE1.0

Clear

PUC

NMI_IRQA

Watchdog Timer Module

IRQA: Interrupt Request Accepted

2-8

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System Reset and Initialization

Flash Access Violation

The flash ACCVIFG flag is set when a flash access violation occurs. The flash

access violation can be enabled to generate an NMI interrupt by setting the

ACCVIE bit. The ACCVIFG flag can then be tested by NMI the interrupt service

routine to determine if the NMI was caused by a flash access violation.

Oscillator Fault

The oscillator fault signal warns of a possible error condition with the crystal

oscillator. The oscillator fault can be enabled to generate an NMI interrupt by

setting the OFIE bit. The OFIFG flag can then be tested by NMI the interrupt

service routine to determine if the NMI was caused by an oscillator fault.

A PUC signal can trigger an oscillator fault, because the PUC switches the

LFXT1 to LF mode, therefore switching off the HF mode. The PUC signal also

switches off the XT2 oscillator.

System Resets, Interrupts, and Operating Modes

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System Reset and Initialization

Example of an NMI Interrupt Handler

The NMI interrupt is a multiple-source interrupt. An NMI interrupt automatically

resets the NMIIE, OFIE and ACCVIE interrupt-enable bits. The user NMI

service routine resets the interrupt flags and re-enables the interrupt-enable

bits according to the application needs as shown in Figure 2−6.

Figure 2−6. NMI Interrupt Handler

Start of NMI Interrupt Handler

Reset by HW:

OFIE, NMIIE, ACCVIE

OFIFG=1

ACCVIFG=1

yes

NMIIFG=1

yes

Reset OFIFG

Reset ACCVIFG

Reset NMIIFG

User’s Software,

Oscillator Fault

Handler

User’s Software,

Flash Access

Violation Handler

User’s Software,

External NMI

Handler

Optional

Set NMIIE, OFIE,

ACCVIE Within One

Instruction

Example 1:

BIS #(NMIIE+OFIE+ACCVIE), &IE1

Example 2:

BIS Mask,&IE1 ; Mask enables only

; interrupt sources

RETI

End of NMI Interrupt

Handler

Note: Enabling NMI Interrupts with ACCVIE, NMIIE, and OFIE

The ACCVIE, NMIIE, and OFIE enable bits should not be set inside of an NMI

interrupt service routine, unless they are set by the last instruction of the

routine before the RETI instruction. Otherwise, nested NMI interrupts may

occur, causing stack overflow and unpredictable operation.

2.2.2 Maskable Interrupts

Maskable interrupts are caused by peripherals with interrupt capability

including the watchdog timer overflow in interval-timer mode. Each maskable

interrupt source can be disabled individually by an interrupt enable bit, or all

maskable interrupts can be disabled by the general interrupt enable (GIE) bit

in the status register (SR).

2-10

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System Reset and Initialization

Each individual peripheral interrupt is discussed in the associated peripheral

module chapter in this manual.

2.2.3 Interrupt Processing

When an interrupt is requested from a peripheral and the peripheral interrupt

enable bit and GIE bit are set, the interrupt service routine is requested. Only

the individual enable bit must be set for (non)-maskable interrupts to be

requested.

Interrupt Acceptance

The interrupt latency is 6 cycles, starting with the acceptance of an interrupt

request, and lasting until the start of execution of the first instruction of the

interrupt-service routine, as shown in Figure 2−7. The interrupt logic executes

the following:

1) Any currently executing instruction is completed.

2) The PC, which points to the next instruction, is pushed onto the stack.

3) The SR is pushed onto the stack.

4) The interrupt with the highest priority is selected if multiple interrupts

occurred during the last instruction and are pending for service.

5) The interrupt request flag resets automatically on single-source flags.

Multiple source flags remain set for servicing by software.

6) The SR is cleared with the exception of SCG0, which is left unchanged.

This terminates any low-power mode. Because the GIE bit is cleared,

further interrupts are disabled.

7) The content of the interrupt vector is loaded into the PC: the program

continues with the interrupt service routine at that address.

Figure 2−7. Interrupt Processing

Before

After

Interrupt

Item1

Item2

Item1

Item2

TOS

System Resets, Interrupts, and Operating Modes

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System Reset and Initialization

Return From Interrupt

The interrupt handling routine terminates with the instruction:

RETI (return from an interrupt service routine)

The return from the interrupt takes 5 cycles to execute the following actions

and is illustrated in Figure 2−8.

1) The SR with all previous settings pops from the stack. All previous settings

of GIE, CPUOFF, etc. are now in effect, regardless of the settings used

during the interrupt service routine.

2) The PC pops from the stack and begins execution at the point where it was

interrupted.

Figure 2−8. Return From Interrupt

Before

After

Return From Interrupt

Item1

Item2

Item1

Item2

TOS

Interrupt Nesting

Interrupt nesting is enabled if the GIE bit is set inside an interrupt service

routine. When interrupt nesting is enabled, any interrupt occurring during an

interrupt service routine will interrupt the routine, regardless of the interrupt

priorities.

2-12

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System Reset and Initialization

2.2.4 Interrupt Vectors

The interrupt vectors and the power-up starting address are located in the

address range 0FFFFh − 0FFE0h as described in Table 2−1. A vector is

programmed by the user with the 16-bit address of the corresponding interrupt

service routine. See the device-specific data sheet for the complete interrupt

vector list.

Table 2−1.Interrupt Sources,Flags, and Vectors

INTERRUPT

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

PRIORITY

FLAG

Power-up, external

reset, watchdog,

flash password

WDTIFG

KEYV

Reset

0FFFEh

15, highest

NMI, oscillator fault,

flash memory access

violation

(non)-maskable

(non)-maskable 0FFFCh

(non)-maskable

NMIIFG

OFIFG

ACCVIFG

device-specific

Watchdog timer

device-specific

0FFFAh

0FFF8h

0FFF6h

WDTIFG

maskable

0FFF4h

0FFF2h

0FFF0h

0FFEEh

0FFECh

0FFEAh

0FFE8h

0FFE6h

0FFE4h

0FFE2h

0FFE0h

0, lowest

Some module enable bits, interrupt enable bits, and interrupt flags are located

in the SFRs. The SFRs are located in the lower address range and are

implemented in byte format. SFRs must be accessed using byte instructions.

See the device-specific datasheet for the SFR configuration.

System Resets, Interrupts, and Operating Modes

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Operating Modes

2.3 Operating Modes

The MSP430 family is designed for ultralow-power applications and uses

different operating modes shown in Figure 2−10.

The operating modes take into account three different needs:

- Ultralow-power

- Speed and data throughput

- Minimization of individual peripheral current consumption

The MSP430 typical current consumption is shown in Figure 2−9.

Figure 2−9. Typical Current Consumption of 13x and 14x Devices vs Operating Modes

340

315

270

225

= 3 V

180

135

= 2.2 V

LPM2

Operating Modes

0.1 0.1

LPM4

LPM0

LPM3

The low-power modes 0−4 are configured with the CPUOFF, OSCOFF, SCG0,

and SCG1 bits in the status register The advantage of including the CPUOFF,

OSCOFF, SCG0, and SCG1 mode-control bits in the status register is that the

present operating mode is saved onto the stack during an interrupt service

routine. Program flow returns to the previous operating mode if the saved SR

value is not altered during the interrupt service routine. Program flow can be

returned to a different operating mode by manipulating the saved SR value on

the stack inside of the interrupt service routine. The mode-control bits and the

stack can be accessed with any instruction.

When setting any of the mode-control bits, the selected operating mode takes

effect immediately. Peripherals operating with any disabled clock are disabled

until the clock becomes active. The peripherals may also be disabled with their

individual control register settings. All I/O port pins and RAM/registers are

unchanged. Wake up is possible through all enabled interrupts.

2-14

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Operating Modes

Figure 2−10. MSP430x1xx Operating Modes For Basic Clock System

RST/NMI

Reset Active

POR

WDTIFG = 0

WDT

Time Expired, Overflow

WDTIFG = 1

PUC

RST/NMI is Reset Pin

WDT is Active

WDTIFG = 1

RST/NMI

NMI Active

WDT Active,

Security Key Violation

Active Mode

CPU Is Active

Peripheral Modules Are Active

CPUOFF = 1

OSCOFF = 1

SCG0 = 1

CPUOFF = 1

SCG0 = 0

SCG1 = 0

SCG1 = 1

LPM0

CPU Off, MCLK Off,

SMCLK On, ACLK On

LPM4

CPU Off, MCLK Off, DCO

Off, ACLK Off

CPUOFF = 1

SCG0 = 1

DC Generator Off

CPUOFF = 1

SCG1 = 0

SCG0 = 1

SCG1 = 1

CPUOFF = 1

SCG0 = 0

LPM3

LPM1

CPU Off, MCLK Off,

SMCLK On, ACLK On

SCG1 = 1

CPU Off, MCLK Off, SMCLK

Off, DCO Off, ACLK On

LPM2

CPU Off, MCLK Off, SMCLK

Off, DCO Off, ACLK On

DC Generator Off if DCO

not used in active mode

DC Generator Off

SCG1

SCG0 OSCOFF CPUOFF

Mode

CPU and Clocks Status

Active

LPM0

CPU is active, all enabled clocks are active

CPU, MCLK are disabled

SMCLK , ACLK are active

LPM1

CPU, MCLK, DCO osc. are disabled

DC generator is disabled if the DCO is not used for

MCLK or SMCLK in active mode

SMCLK , ACLK are active

LPM2

LPM3

LPM4

CPU, MCLK, SMCLK, DCO osc. are disabled

DC generator remains enabled

ACLK is active

CPU, MCLK, SMCLK, DCO osc. are disabled

DC generator disabled

ACLK is active

CPU and all clocks disabled

System Resets, Interrupts, and Operating Modes

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Operating Modes

2.3.1 Entering and Exiting Low-Power Modes

An enabled interrupt event wakes the MSP430 from any of the low-power

operating modes. The program flow is:

- Enter interrupt service routine:

The PC and SR are stored on the stack

The CPUOFF, SCG1, and OSCOFF bits are automatically reset

- Options for returning from the interrupt service routine:

The original SR is popped from the stack, restoring the previous

operating mode.

The SR bits stored on the stack can be modified within the interrupt

service routine returning to a different operating mode when the RETI

instruction is executed.

; Enter LPM0 Example

BIS #GIE+CPUOFF,SR

; Enter LPM0

; ...

;

; Program stops here

; Exit LPM0 Interrupt Service Routine

BIC #CPUOFF,0(SP)

RETI

; Exit LPM0 on RETI

; Enter LPM3 Example

BIS #GIE+CPUOFF+SCG1+SCG0,SR ; Enter LPM3

; ...

; Program stops here

;

; Exit LPM3 Interrupt Service Routine

BIC #CPUOFF+SCG1+SCG0,0(SP) ; Exit LPM3 on RETI

RETI

Extended Time in Low-Power Modes

The negative temperature coefficient of the DCO should be considered when

the DCO is disabled for extended low-power mode periods. If the temperature

changes significantly, the DCO frequency at wake-up may be significantly

different from when the low-power mode was entered and may be out of the

specified operating range. To avoid this, the DCO can be set to it lowest value

before entering the low-power mode for extended periods of time where

temperature can change.

; Enter LPM4 Example with lowest DCO Setting

BIC #RSEL2+RSEL1+RSEL0,&BCSCTL1

BIS #GIE+CPUOFF+OSCOFF+SCG1+SCG0,SR; Enter LPM4

; ... ; Program stops

; Lowest RSEL

;

; Interrupt Service Routine

BIC #CPUOFF+OSCOFF+SCG1+SCG0,0(SR); Exit LPM4 on RETI

RETI

2-16

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Principles for Low-Power Applications

2.4 Principles for Low-Power Applications

Often, the most important factor for reducing power consumption is using the

MSP430’s clock system to maximize the time in LPM3. LPM3 power

consumption is less than 2 µA typical with both a real-time clock function and

all interrupts active. A 32-kHz watch crystal is used for the ACLK and the CPU

is clocked from the DCO (normally off) which has a 6-µs wake-up.

- Use interrupts to wake the processor and control program flow.

- Peripherals should be switched on only when needed.

- Use low-power integrated peripheral modules in place of software driven

functions. For example Timer_A and Timer_B can automatically generate

PWM and capture external timing, with no CPU resources.

- Calculated branching and fast table look-ups should be used in place of

flag polling and long software calculations.

- Avoid frequent subroutine and function calls due to overhead.

- For longer software routines, single-cycle CPU registers should be used.

2.5 Connection of Unused Pins

The correct termination of all unused pins is listed in Table 2−2.

Table 2−2.Connection of Unused Pins

Potential

Comment

Open

REF+

/Ve

REF− REF−

XIN

XOUT

Open

XT2IN

13x, 14x, 15x and 16x devices

Switched to port function, output direction

Pullup resistor 47 kΩ

XT2OUT

Px.0 to Px.7

RST/NMI

Open

or V

Test/V

Test

P11x devices

Pulldown resistor 30K 11x1 devices

11x1A, 11x2, 12x, 12x2 devices

Open

TDO

TDI

TMS

TCK

System Resets, Interrupts, and Operating Modes

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Chapter 3

RISC 16ĆBit CPU

This chapter describes the MSP430 CPU, addressing modes, and instruction

set.

Topic

Page

3.1 CPU Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.2 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

RISC 16-Bit CPU

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CPU Introduction

3.1 CPU Introduction

The CPU incorporates features specifically designed for modern

programming techniques such as calculated branching, table processing and

the use of high-level languages such as C. The CPU can address the complete

address range without paging.

The CPU features include:

- RISC architecture with 27 instructions and 7 addressing modes.

- Orthogonal architecture with every instruction usable with every

addressing mode.

- Full register access including program counter, status registers, and stack

pointer.

- Single-cycle register operations.

- Large 16-bit register file reduces fetches to memory.

- 16-bit address bus allows direct access and branching throughout entire

memory range.

- 16-bit data bus allows direct manipulation of word-wide arguments.

- Constant generator provides six most used immediate values and

reduces code size.

- Direct memory-to-memory transfers without intermediate register holding.

- Word and byte addressing and instruction formats.

The block diagram of the CPU is shown in Figure 3−1.

3-2

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CPU Introduction

Figure 3−1. CPU Block Diagram

MDB − Memory Data Bus

Memory Address Bus − MAB

R0/PC Program Counter

R1/SP Stack Pointer

R2/SR/CG1 Status

R3/CG2 Constant Generator

General Purpose

R10

R11

R12

R13

R14

R15

Zero, Z

Carry, C

dst

src

MCLK

16−bit ALU

Overflow, V

Negative, N

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CPU Registers

3.2 CPU Registers

The CPU incorporates sixteen 16-bit registers. R0, R1, R2 and R3 have

dedicated functions. R4 to R15 are working registers for general use.

3.2.1 Program Counter (PC)

The 16-bit program counter (PC/R0) points to the next instruction to be

executed. Each instruction uses an even number of bytes (two, four, or six),

and the PC is incremented accordingly. Instruction accesses in the 64-KB

address space are performed on word boundaries, and the PC is aligned to

even addresses. Figure 3−2 shows the program counter.

Figure 3−2. Program Counter

Program Counter Bits 15 to 1

The PC can be addressed with all instructions and addressing modes. A few

examples:

MOV #LABEL,PC; Branch to address LABEL

MOV LABEL,PC ; Branch to address contained in LABEL

MOV @R14,PC ; Branch indirect to address in R14

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CPU Registers

3.2.2 Stack Pointer (SP)

The stack pointer (SP/R1) is used by the CPU to store the return addresses

of subroutine calls and interrupts. It uses a predecrement, postincrement

scheme. In addition, the SP can be used by software with all instructions and

addressing modes. Figure 3−3 shows the SP. The SP is initialized into RAM

by the user, and is aligned to even addresses.

Figure 3−4 shows stack usage.

Figure 3−3. Stack Pointer

Stack Pointer Bits 15 to 1

MOV 2(SP),R6 ; Item I2 −> R6

MOV R7,0(SP) ; Overwrite TOS with R7

PUSH #0123h

POP R8

; Put 0123h onto TOS

; R8 = 0123h

Figure 3−4. Stack Usage

Address

POP R8

PUSH #0123h

0xxxh

0xxxh − 2

0xxxh − 4

0xxxh − 6

0xxxh − 8

0123h

The special cases of using the SP as an argument to the PUSH and POP

instructions are described and shown in Figure 3−5.

Figure 3−5. PUSH SP - POP SP Sequence

PUSH SP

POP SP

old

The stack pointer is changed after The stack pointer is not changed after a POP SP

a PUSH SP instruction.

instruction. The POP SP instruction places SP1 into the

stack pointer SP (SP2=SP1)

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CPU Registers

3.2.3 Status Register (SR)

The status register (SR/R2), used as a source or destination register, can be

used in the register mode only addressed with word instructions. The remain-

ing combinations of addressing modes are used to support the constant gen-

erator. Figure 3−6 shows the SR bits.

Figure 3−6. Status Register Bits

OSC CPU

OFF OFF

SCG1 SCG0

GIE

Reserved

rw-0

Table 3−1 describes the status register bits.

Table 3−1.Description of Status Register Bits

Bit

Description

Overflow bit. This bit is set when the result of an arithmetic operation

overflows the signed-variable range.

ADD(.B),ADDC(.B)

Set when:

Positive + Positive = Negative

Negative + Negative = Positive,

otherwise reset

SUB(.B),SUBC(.B),CMP(.B)

Set when:

Positive − Negative = Negative

Negative − Positive = Positive,

otherwise reset

SCG1

SCG0

System clock generator 1. This bit, when set, turns off the SMCLK.

System clock generator 0. This bit, when set, turns off the DCO dc

generator, if DCOCLK is not used for MCLK or SMCLK.

OSCOFF Oscillator Off. This bit, when set, turns off the LFXT1 crystal oscillator,

when LFXT1CLK is not use for MCLK or SMCLK

CPUOFF CPU off. This bit, when set, turns off the CPU.

GIE

General interrupt enable. This bit, when set, enables maskable

interrupts. When reset, all maskable interrupts are disabled.

Negative bit. This bit is set when the result of a byte or word operation

is negative and cleared when the result is not negative.

Word operation:

N is set to the value of bit 15 of the

result

Byte operation:

N is set to the value of bit 7 of the

result

Zero bit. This bit is set when the result of a byte or word operation is 0

and cleared when the result is not 0.

Carry bit. This bit is set when the result of a byte or word operation

produced a carry and cleared when no carry occurred.

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CPU Registers

3.2.4 Constant Generator Registers CG1 and CG2

Six commonly-used constants are generated with the constant generator

registers R2 and R3, without requiring an additional 16-bit word of program

code. The constants are selected with the source-register addressing modes

(As), as described in Table 3−2.

Table 3−2.Values of Constant Generators CG1, CG2

Constant

Remarks

− − − − −

(0)

Absolute address mode

+4, bit processing

+8, bit processing

0, word processing

00004h

00008h

00000h

00001h

00002h

0FFFFh

+2, bit processing

−1, word processing

The constant generator advantages are:

- No special instructions required

- No additional code word for the six constants

- No code memory access required to retrieve the constant

The assembler uses the constant generator automatically if one of the six

constants is used as an immediate source operand. Registers R2 and R3,

used in the constant mode, cannot be addressed explicitly; they act as

source-only registers.

Constant Generator − Expanded Instruction Set

The RISC instruction set of the MSP430 has only 27 instructions. However, the

constant generator allows the MSP430 assembler to support 24 additional,

emulated instructions. For example, the single-operand instruction:

CLR

is emulated by the double-operand instruction with the same length:

MOV R3,dst

where the #0 is replaced by the assembler, and R3 is used with As=00.

dst

INC

is replaced by:

ADD

dst

0(R3),dst

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CPU Registers

3.2.5 General−Purpose Registers R4 - R15

The twelve registers, R4−R15, are general-purpose registers. All of these

registers can be used as data registers, address pointers, or index values and

can be accessed with byte or word instructions as shown in Figure 3−7.

Figure 3−7. Register-Byte/Byte-Register Operations

High Byte Low Byte

Unused

Byte-Register Operation

High Byte

Low Byte

Byte

Memory

Byte

Example Register-Byte Operation

R5 = 0A28Fh

Example Byte-Register Operation

R5 = 01202h

R6 = 0203h

R6 = 0223h

Mem(0203h) = 012h

Mem(0223h) = 05Fh

ADD.B

R5,0(R6)

ADD.B

@R6,R5

08Fh

+ 012h

0A1h

05Fh

+ 002h

00061h

Mem (0203h) = 0A1h

C = 0, Z = 0, N = 1

R5 = 00061h

C = 0, Z = 0, N = 0

(Low byte of register)

+ (Addressed byte)

−>(Addressed byte)

(Addressed byte)

+ (Low byte of register)

−>(Low byte of register, zero to High byte)

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Addressing Modes

3.3 Addressing Modes

Seven addressing modes for the source operand and four addressing modes

for the destination operand can address the complete address space with no

exceptions. The bit numbers in Table 3−3 describe the contents of the As

(source) and Ad (destination) mode bits.

Table 3−3.Source/Destination Operand Addressing Modes

As/Ad

00/0

Addressing Mode

Syntax

Description

01/1

Indexed mode

X(Rn)

(Rn + X) points to the operand. X

is stored in the next word.

01/1

Symbolic mode

ADDR

(PC + X) points to the operand. X

is stored in the next word. Indexed

mode X(PC) is used.

01/1

Absolute mode

&ADDR The word following the instruction

contains the absolute address. X

is stored in the next word. Indexed

mode X(SR) is used.

10/−

11/−

Indirect register

mode

@Rn

Rn is used as a pointer to the

operand.

Indirect

autoincrement

@Rn+

Rn is used as a pointer to the

operand. Rn is incremented

afterwards by 1 for .B instructions

and by 2 for .W instructions.

11/−

Immediate mode

The word following the instruction

contains the immediate constant

N. Indirect autoincrement mode

@PC+ is used.

The seven addressing modes are explained in detail in the following sections.

Most of the examples show the same addressing mode for the source and

destination, but any valid combination of source and destination addressing

modes is possible in an instruction.

Note: Use of Labels EDE, TONI, TOM, and LEO

Throughout MSP430 documentation EDE, TONI, TOM, and LEO are used

as generic labels. They are only labels. They have no special meaning.

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Addressing Modes

3.3.1 Register Mode

The register mode is described in Table 3−4.

Table 3−4.Register Mode Description

Assembler Code

Content of ROM

MOV R10,R11

Length:

One or two words

Operation:

Comment:

Example:

Move the content of R10 to R11. R10 is not affected.

Valid for source and destination

MOV R10,R11

Before:

After:

R10

R11

0A023h

R10

R11

0A023h

0FA15h

0A023h

PC + 2

old

Note: Data in Registers

The data in the register can be accessed using word or byte instructions. If

byte instructions are used, the high byte is always 0 in the result. The status

bits are handled according to the result of the byte instruction.

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Addressing Modes

3.3.2 Indexed Mode

The indexed mode is described in Table 3−5.

Table 3−5.Indexed Mode Description

Assembler Code

Content of ROM

MOV 2(R5),6(R6)

MOV X(R5),Y(R6)

X = 2

Y = 6

Length:

Two or three words

Operation:

Move the contents of the source address (contents of R5 + 2)

to the destination address (contents of R6 + 6). The source

and destination registers (R5 and R6) are not affected. In

indexed mode, the program counter is incremented

automatically so that program execution continues with the

next instruction.

Comment:

Example:

Valid for source and destination

MOV 2(R5),6(R6);

Before:

After:

Address

Space

0xxxxh PC

0FF16h

00006h

R5 01080h

R6 0108Ch

0FF16h 00006h

0FF14h 00002h

04596h

0FF12h

R5 01080h

R6 0108Ch

0FF14h 00002h

04596h PC

0FF12h

0108Ch

+0006h

01092h

01094h

01092h

01090h

0xxxxh

05555h

0xxxxh

01094h 0xxxxh

01092h 01234h

0xxxxh

01090h

01080h

+0002h

01082h

01084h

0xxxxh

01084h 0xxxxh

01082h 01234h

0xxxxh

01080h

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Addressing Modes

3.3.3 Symbolic Mode

The symbolic mode is described in Table 3−6.

Table 3−6.Symbolic Mode Description

Assembler Code

Content of ROM

MOV X(PC),Y(PC)

X = EDE − PC

MOV EDE,TONI

Y = TONI − PC

Length:

Two or three words

Operation:

Move the contents of the source address EDE (contents of

PC + X) to the destination address TONI (contents of PC + Y).

The words after the instruction contain the differences

between the PC and the source or destination addresses.

The assembler computes and inserts offsets X and Y

automatically. With symbolic mode, the program counter (PC)

is incremented automatically so that program execution

continues with the next instruction.

Comment:

Example:

Valid for source and destination

MOV EDE,TONI ;Source address EDE = 0F016h

;Dest. address TONI=01114h

Before:

After:

Address

Space

Address

Space

0xxxxh PC

0FF16h

0FF14h

0FF12h

011FEh

0FF16h

0FF14h

0FF12h

011FEh

0F102h

04090h

0F102h

04090h PC

0FF14h

+0F102h

0F016h

0F018h

0F016h

0F014h

0xxxxh

0A123h

0xxxxh

0F018h

0F016h

0F014h

0xxxxh

0A123h

0xxxxh

0FF16h

+011FEh

01114h

01116h

01114h

01112h

0xxxxh

05555h

0xxxxh

01116h

01114h

01112h

0xxxxh

0A123h

0xxxxh

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Addressing Modes

3.3.4 Absolute Mode

The absolute mode is described in Table 3−7.

Table 3−7.Absolute Mode Description

Assembler Code

Content of ROM

MOV &EDE,&TONI

MOV X(0),Y(0)

X = EDE

Y = TONI

Length:

Two or three words

Operation:

Move the contents of the source address EDE to the

destination address TONI. The words after the instruction

contain the absolute address of the source and destination

addresses. With absolute mode, the PC is incremented

automatically so that program execution continues with the

next instruction.

Comment:

Example:

Valid for source and destination

MOV &EDE,&TONI ;Source address EDE=0F016h,

;dest. address TONI=01114h

Before:

After:

Address

Space

Address

Space

0xxxxh PC

0FF16h

0FF14h

0FF12h

01114h

0FF16h

0FF14h

0FF12h

01114h

0F016h

04292h

0F016h

04292h PC

0F018h

0F016h

0F014h

0xxxxh

0A123h

0xxxxh

0F018h

0F016h

0F014h

0xxxxh

0A123h

0xxxxh

01116h

01114h

01112h

0xxxxh

01234h

0xxxxh

01116h

01114h

01112h

0xxxxh

0A123h

0xxxxh

This address mode is mainly for hardware peripheral modules that are located

at an absolute, fixed address. These are addressed with absolute mode to

ensure software transportability (for example, position-independent code).

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Addressing Modes

3.3.5 Indirect Register Mode

The indirect register mode is described in Table 3−8.

Table 3−8.Indirect Mode Description

Assembler Code

Content of ROM

MOV @R10,0(R11)

Length:

One or two words

Operation:

Move the contents of the source address (contents of R10) to

the destination address (contents of R11). The registers are

not modified.

Comment:

Example:

Valid only for source operand. The substitute for destination

operand is 0(Rd).

MOV.B @R10,0(R11)

Before:

After:

Address

Space

0xxxxh

0000h

Address

Space

0xxxxh PC

0FF16h

R10 0FA33h

R11 002A7h

0FF16h 0000h

0FF14h 04AEBh

0xxxxh

0FF12h

R10 0FA33h

R11 002A7h

0FF14h 04AEBh

0FF12h

0xxxxh

0FA34h

0FA32h

0FA30h

0xxxxh

05BC1h

0xxxxh

0FA34h 0xxxxh

0FA32h 05BC1h

0xxxxh

0FA30h

002A8h

002A7h

002A6h

0xxh

012h

0xxh

002A8h

002A7h

002A6h

0xxh

05Bh

0xxh

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Addressing Modes

3.3.6 Indirect Autoincrement Mode

The indirect autoincrement mode is described in Table 3−9.

Table 3−9.Indirect Autoincrement Mode Description

Assembler Code

Content of ROM

MOV @R10+,0(R11)

Length:

One or two words

Operation:

Move the contents of the source address (contents of R10) to

the destination address (contents of R11). Register R10 is

incremented by 1 for a byte operation, or 2 for a word

operation after the fetch; it points to the next address without

any overhead. This is useful for table processing.

Comment:

Valid only for source operand. The substitute for destination

operand is 0(Rd) plus second instruction INCD Rd.

Example:

Before:

MOV @R10+,0(R11)

After:

Address

Space

Address

Space

0xxxxh

0FF18h

0FF16h 00000h

0FF14h 04ABBh

0FF12h 0xxxxh

R10 0FA32h 0FF16h 00000h

R10 0FA34h

R11 010A8h

0FF14h 04ABBh

0FF12h 0xxxxh

0FA34h 0xxxxh

0FA32h 05BC1h

0FA34h 0xxxxh

0FA32h 05BC1h

0xxxxh

0FA30h

010AAh 0xxxxh

010A8h 01234h

010AAh 0xxxxh

010A8h 05BC1h

0xxxxh

010A6h

The autoincrementing of the register contents occurs after the operand is

fetched. This is shown in Figure 3−8.

Figure 3−8. Operand Fetch Operation

Instruction

Address

Operand

+1/ +2

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Addressing Modes

3.3.7 Immediate Mode

The immediate mode is described in Table 3−10.

Table 3−10.Immediate Mode Description

Assembler Code

Content of ROM

MOV @PC+,X(PC)

MOV #45h,TONI

X = TONI − PC

Length:

Two or three words

It is one word less if a constant of CG1 or CG2 can be used.

Operation:

Move the immediate constant 45h, which is contained in the

word following the instruction, to destination address TONI.

When fetching the source, the program counter points to the

word following the instruction and moves the contents to the

destination.

Comment:

Valid only for a source operand.

Example:

Before:

MOV #45h,TONI

After:

Address

Space

Address

Space

0xxxxh PC

0FF18h

0FF16h

0FF14h

0FF12h

01192h

00045h

040B0h

00045h

0FF14h

0FF12h

040B0h PC

0FF16h

+01192h

010A8h

010AAh

010A8h

010A6h

0xxxxh

01234h

0xxxxh

010AAh

010A8h

010A6h

0xxxxh

00045h

0xxxxh

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Instruction Set

3.4 Instruction Set

The complete MSP430 instruction set consists of 27 core instructions and 24

emulated instructions. The core instructions are instructions that have unique

op-codes decoded by the CPU. The emulated instructions are instructions that

make code easier to write and read, but do not have op-codes themselves,

instead they are replaced automatically by the assembler with an equivalent

core instruction. There is no code or performance penalty for using emulated

instruction.

There are three core-instruction formats:

- Dual-operand

- Single-operand

- Jump

All single-operand and dual-operand instructions can be byte or word

instructions by using .B or .W extensions. Byte instructions are used to access

byte data or byte peripherals. Word instructions are used to access word data

or word peripherals. If no extension is used, the instruction is a word

instruction.

The source and destination of an instruction are defined by the following fields:

src

The source operand defined by As and S-reg

The destination operand defined by Ad and D-reg

dst

The addressing bits responsible for the addressing mode used

for the source (src)

S-reg

The working register used for the source (src)

The addressing bits responsible for the addressing mode used

for the destination (dst)

D-reg

B/W

The working register used for the destination (dst)

Byte or word operation:

0: word operation

1: byte operation

Note: Destination Address

Destination addresses are valid anywhere in the memory map. However,

when using an instruction that modifies the contents of the destination, the

user must ensure the destination address is writable. For example, a

masked-ROM location would be a valid destination address, but the contents

are not modifiable, so the results of the instruction would be lost.

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Instruction Set

3.4.1 Double-Operand (Format I) Instructions

Figure 3−9 illustrates the double-operand instruction format.

Figure 3−9. Double Operand Instruction Format

S-Reg

Ad B/W

D-Reg

Op-code

Table 3−11 lists and describes the double operand instructions.

Table 3−11.Double Operand Instructions

Mnemonic S-Reg,

D-Reg

Operation

Status Bits

−

MOV(.B) src,dst src → dst

ADD(.B) src,dst src + dst → dst

ADDC(.B) src,dst src + dst + C → dst

SUB(.B) src,dst dst + .not.src + 1 → dst

SUBC(.B) src,dst dst + .not.src + C → dst

CMP(.B) src,dst dst − src

DADD(.B) src,dst src + dst + C → dst (decimally)

BIT(.B) src,dst src .and. dst

−

BIC(.B) src,dst .not.src .and. dst → dst

BIS(.B) src,dst src .or. dst → dst

XOR(.B) src,dst src .xor. dst → dst

AND(.B) src,dst src .and. dst → dst

−

The status bit is affected

The status bit is not affected

The status bit is cleared

The status bit is set

−

Note: Instructions CMP and SUB

The instructions CMP and SUB are identical except for the storage of the

result. The same is true for the BITand ANDinstructions.

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Instruction Set

3.4.2 Single-Operand (Format II) Instructions

Figure 3−10 illustrates the single-operand instruction format.

Figure 3−10. Single Operand Instruction Format

Op-code

B/W

D/S-Reg

Table 3−12 lists and describes the single operand instructions.

Table 3−12.Single Operand Instructions

S-Reg,

D-Reg

Mnemonic

Operation

Status Bits

RRC(.B) dst

RRA(.B) dst

PUSH(.B) src

C → MSB →.......LSB → C

MSB → MSB →....LSB → C

SP − 2 → SP, src → @SP

Swap bytes

−

SWPB

CALL

dst

SP − 2 → SP, PC+2 → @SP

dst → PC

RETI

SXT

TOS → SR, SP + 2 → SP

TOS → PC,SP + 2 → SP

Bit 7 → Bit 8........Bit 15

dst

The status bit is affected

The status bit is not affected

The status bit is cleared

The status bit is set

−

All addressing modes are possible for the CALL instruction. If the symbolic

mode (ADDRESS), the immediate mode (#N), the absolute mode (&EDE) or

the indexed mode x(RN) is used, the word that follows contains the address

information.

RISC 16-Bit CPU

3-19

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Instruction Set

3.4.3 Jumps

Figure 3−11 shows the conditional-jump instruction format.

Figure 3−11. Jump Instruction Format

Op-code

10-Bit PC Offset

Table 3−13 lists and describes the jump instructions.

Table 3−13.Jump Instructions

Mnemonic

S-Reg, D-Reg

Label

Operation

JEQ/JZ

JNE/JNZ

Jump to label if zero bit is set

Jump to label if zero bit is reset

Jump to label if carry bit is set

Jump to label if carry bit is reset

Jump to label if negative bit is set

Jump to label if (N .XOR. V) = 0

Jump to label if (N .XOR. V) = 1

Jump to label unconditionally

Label

JNC

Label

JGE

Label

JMP

Label

Conditional jumps support program branching relative to the PC and do not

affect the status bits. The possible jump range is from −511 to +512 words

relative to the PC value at the jump instruction. The 10-bit program-counter

offset is treated as a signed 10-bit value that is doubled and added to the

program counter:

= PC + 2 + PC

× 2

new

old

offset

3-20

RISC 16-Bit CPU

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Instruction Set

ADC[.W]

ADC.B

Add carry to destination

Syntax

ADC

ADC.B

dst or ADC.W dst

dst

Operation

Emulation

dst + C −> dst

ADDC

#0,dst

ADDC.B #0,dst

Description

Status Bits

The carry bit (C) is added to the destination operand. The previous contents

of the destination are lost.

N: Set if result is negative, reset if positive

Z: Set if result is zero, reset otherwise

C: Set if dst was incremented from 0FFFFh to 0000, reset otherwise

Set if dst was incremented from 0FFh to 00, reset otherwise

V: Set if an arithmetic overflow occurs, otherwise reset

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

The 16-bit counter pointed to by R13 is added to a 32-bit counter pointed to

by R12.

ADD

ADC

@R13,0(R12)

2(R12)

; Add LSDs

; Add carry to MSD

Example

The 8-bit counter pointed to by R13 is added to a 16-bit counter pointed to by

R12.

ADD.B

ADC.B

@R13,0(R12)

1(R12)

; Add LSDs

; Add carry to MSD

RISC 16−Bit CPU

3-21

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Instruction Set

ADD[.W]

ADD.B

Add source to destination

Syntax

ADD

ADD.B

src,dst

ADD.W src,dst

Operation

src + dst −> dst

Description

The source operand is added to the destination operand. The source operand

is not affected. The previous contents of the destination are lost.

Status Bits

N: Set if result is negative, reset if positive

Z: Set if result is zero, reset otherwise

C: Set if there is a carry from the result, cleared if not

V: Set if an arithmetic overflow occurs, otherwise reset

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

R5 is increased by 10. The jump to TONI is performed on a carry.

ADD

......

#10,R5

TONI

; Carry occurred

; No carry

Example

R5 is increased by 10. The jump to TONI is performed on a carry.

ADD.B

......

#10,R5

TONI

; Add 10 to Lowbyte of R5

; Carry occurred, if (R5) ≥ 246 [0Ah+0F6h]

; No carry

RISC 16−Bit CPU

3-22

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Instruction Set

ADDC[.W]

ADDC.B

Add source and carry to destination

Syntax

ADDC

ADDC.B

src,dst

ADDC.W src,dst

Operation

src + dst + C −> dst

Description

The source operand and the carry bit (C) are added to the destination operand.

The source operand is not affected. The previous contents of the destination

are lost.

Status Bits

N: Set if result is negative, reset if positive

Z: Set if result is zero, reset otherwise

C: Set if there is a carry from the MSB of the result, reset otherwise

V: Set if an arithmetic overflow occurs, otherwise reset

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

The 32-bit counter pointed to by R13 is added to a 32-bit counter, eleven words

(20/2 + 2/2) above the pointer in R13.

ADD

ADDC

...

@R13+,20(R13) ; ADD LSDs with no carry in

@R13+,20(R13) ; ADD MSDs with carry

; resulting from the LSDs

Example

The 24-bit counter pointed to by R13 is added to a 24-bit counter, eleven words

above the pointer in R13.

ADD.B

ADDC.B

...

@R13+,10(R13) ; ADD LSDs with no carry in

@R13+,10(R13) ; ADD medium Bits with carry

@R13+,10(R13) ; ADD MSDs with carry

; resulting from the LSDs

RISC 16−Bit CPU

3-23

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Instruction Set

AND[.W]

AND.B

Source AND destination

Syntax

AND

AND.B

src,dst

or AND.W src,dst

Operation

src .AND. dst −> dst

Description

The source operand and the destination operand are logically ANDed. The

result is placed into the destination.

Status Bits

N: Set if result MSB is set, reset if not set

Z: Set if result is zero, reset otherwise

C: Set if result is not zero, reset otherwise ( = .NOT. Zero)

V: Reset

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

The bits set in R5 are used as a mask (#0AA55h) for the word addressed by

TOM. If the result is zero, a branch is taken to label TONI.

MOV

AND

#0AA55h,R5

R5,TOM

TONI

; Load mask into register R5

; mask word addressed by TOM with R5

;

......

; Result is not zero

;

AND

#0AA55h,TOM

TONI

Example

The bits of mask #0A5h are logically ANDed with the low byte TOM. If the result

is zero, a branch is taken to label TONI.

AND.B

#0A5h,TOM

TONI

; mask Lowbyte TOM with 0A5h

;

......

; Result is not zero

RISC 16−Bit CPU

3-24

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Instruction Set

BIC[.W]

BIC.B

Clear bits in destination

Syntax

BIC

BIC.B

src,dst

or BIC.W src,dst

Operation

.NOT.src .AND. dst −> dst

Description

The inverted source operand and the destination operand are logically

ANDed. The result is placed into the destination. The source operand is not

affected.

Status Bits

Mode Bits

Example

Status bits are not affected.

OSCOFF, CPUOFF, and GIE are not affected.

The six MSBs of the RAM word LEO are cleared.

BIC

The five MSBs of the RAM byte LEO are cleared.

BIC.B #0F8h,LEO ; Clear 5 MSBs in Ram location LEO

#0FC00h,LEO

; Clear 6 MSBs in MEM(LEO)

Example

RISC 16−Bit CPU

3-25

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Instruction Set

BIS[.W]

BIS.B

Set bits in destination

Syntax

BIS

BIS.B

src,dst

or BIS.W

src,dst

Operation

src .OR. dst −> dst

Description

The source operand and the destination operand are logically ORed. The

result is placed into the destination. The source operand is not affected.

Status Bits

Mode Bits

Example

Status bits are not affected.

OSCOFF, CPUOFF, and GIE are not affected.

The six LSBs of the RAM word TOM are set.

BIS

The three MSBs of RAM byte TOM are set.

BIS.B #0E0h,TOM ; set the 3 MSBs in RAM location TOM

#003Fh,TOM; set the six LSBs in RAM location TOM

Example

RISC 16−Bit CPU

3-26

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Instruction Set

BIT[.W]

BIT.B

Test bits in destination

Syntax

BIT

src,dst

or BIT.W src,dst

Operation

Description

src .AND. dst

The source and destination operands are logically ANDed. The result affects

only the status bits. The source and destination operands are not affected.

Status Bits

N: Set if MSB of result is set, reset otherwise

Z: Set if result is zero, reset otherwise

C: Set if result is not zero, reset otherwise (.NOT. Zero)

V: Reset

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

If bit 9 of R8 is set, a branch is taken to label TOM.

BIT

JNZ

...

#0200h,R8

TOM

; bit 9 of R8 set?

; Yes, branch to TOM

; No, proceed

Example

If bit 3 of R8 is set, a branch is taken to label TOM.

BIT.B

#8,R8

TOM

A serial communication receive bit (RCV) is tested. Because the carry bit is

equal to the state of the tested bit while using the BIT instruction to test a single

bit, the carry bit is used by the subsequent instruction; the read information is

shifted into register RECBUF.

;

; Serial communication with LSB is shifted first:

; xxxx xxxx

xxxx

BIT.B

RRC

#RCV,RCCTL

RECBUF

; Bit info into carry

; Carry −> MSB of RECBUF

; cxxx xxxx

......

; repeat previous two instructions

; 8 times

; cccc cccc

; ^

; MSB

LSB

; Serial communication with MSB shifted first:

BIT.B

RLC.B

#RCV,RCCTL

RECBUF

; Bit info into carry

; Carry −> LSB of RECBUF

; xxxx

xxxc

......

; repeat previous two instructions

; 8 times

; cccc

; |

cccc

LSB

; MSB

RISC 16−Bit CPU

3-27

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Instruction Set

* BR, BRANCH

Syntax

Branch to .......... destination

dst

Operation

Emulation

Description

dst −> PC

MOV

dst,PC

An unconditional branch is taken to an address anywhere in the 64K address

space. All source addressing modes can be used. The branch instruction is

a word instruction.

Status Bits

Example

Status bits are not affected.

Examples for all addressing modes are given.

#EXEC

;Branch to label EXEC or direct branch (e.g. #0A4h)

; Core instruction MOV @PC+,PC

EXEC

; Branch to the address contained in EXEC

; Core instruction MOV X(PC),PC

; Indirect address

&EXEC ; Branch to the address contained in absolute

; address EXEC

; Core instruction MOV X(0),PC

; Indirect address

; Branch to the address contained in R5

; Core instruction MOV R5,PC

; Indirect R5

@R5

; Branch to the address contained in the word

; pointed to by R5.

; Core instruction MOV @R5,PC

; Indirect, indirect R5

@R5+

; Branch to the address contained in the word pointed

; to by R5 and increment pointer in R5 afterwards.

; The next time—S/W flow uses R5 pointer—it can

; alter program execution due to access to

; next address in a table pointed to by R5

; Core instruction MOV @R5,PC

; Indirect, indirect R5 with autoincrement

X(R5)

; Branch to the address contained in the address

; pointed to by R5 + X (e.g. table with address

; starting at X). X can be an address or a label

; Core instruction MOV X(R5),PC

; Indirect, indirect R5 + X

RISC 16−Bit CPU

3-28

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Instruction Set

CALL

Subroutine

CALL

Syntax

Operation

dst

−> tmp

−> SP

−> @SP

−> PC

dst is evaluated and stored

SP − 2

tmp

PC updated to TOS

dst saved to PC

Description

A subroutine call is made to an address anywhere in the 64K address space.

All addressing modes can be used. The return address (the address of the

following instruction) is stored on the stack. The call instruction is a word

instruction.

Status Bits

Example

Status bits are not affected.

Examples for all addressing modes are given.

CALL

#EXEC

; Call on label EXEC or immediate address (e.g. #0A4h)

; SP−2 → SP, PC+2 → @SP, @PC+ → PC

CALL

EXEC

; Call on the address contained in EXEC

; SP−2 → SP, PC+2 → @SP, X(PC) → PC

; Indirect address

CALL

&EXEC ; Call on the address contained in absolute address

; EXEC

; SP−2 → SP, PC+2 → @SP, X(0) → PC

; Indirect address

CALL

; Call on the address contained in R5

; SP−2 → SP, PC+2 → @SP, R5 → PC

; Indirect R5

@R5

; Call on the address contained in the word

; pointed to by R5

; SP−2 → SP, PC+2 → @SP, @R5 → PC

; Indirect, indirect R5

CALL

@R5+

; Call on the address contained in the word

; pointed to by R5 and increment pointer in R5.

; The next time—S/W flow uses R5 pointer—

; it can alter the program execution due to

; access to next address in a table pointed to by R5

; SP−2 → SP, PC+2 → @SP, @R5 → PC

; Indirect, indirect R5 with autoincrement

X(R5)

; Call on the address contained in the address pointed

; to by R5 + X (e.g. table with address starting at X)

; X can be an address or a label

; SP−2 → SP, PC+2 → @SP, X(R5) → PC

; Indirect, indirect R5 + X

RISC 16−Bit CPU

3-29

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Instruction Set

* CLR[.W]

* CLR.B

Clear destination

Syntax

CLR

CLR.B

dst

or CLR.W dst

Operation

Emulation

0 −> dst

MOV

MOV.B

#0,dst

Description

Status Bits

Example

The destination operand is cleared.

Status bits are not affected.

RAM word TONI is cleared.

CLR

CLR R5

RAM byte TONI is cleared.

CLR.B TONI

TONI

; 0 −> TONI

Example

; 0 −> TONI

RISC 16−Bit CPU

3-30

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Instruction Set

* CLRC

Clear carry bit

CLRC

Syntax

Operation

Emulation

Description

Status Bits

0 −> C

BIC

#1,SR

The carry bit (C) is cleared. The clear carry instruction is a word instruction.

N: Not affected

Z: Not affected

C: Cleared

V: Not affected

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

The 16-bit decimal counter pointed to by R13 is added to a 32-bit counter

pointed to by R12.

CLRC

DADD

DADC

; C=0: defines start

@R13,0(R12) ; add 16-bit counter to low word of 32-bit counter

2(R12)

; add carry to high word of 32-bit counter

RISC 16−Bit CPU

3-31

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Instruction Set

* CLRN

Clear negative bit

CLRN

Syntax

Operation

0 → N

(.NOT.src .AND. dst −> dst)

Emulation

BIC

#4,SR

Description

The constant 04h is inverted (0FFFBh) and is logically ANDed with the

destination operand. The result is placed into the destination. The clear

negative bit instruction is a word instruction.

Status Bits

N: Reset to 0

Z: Not affected

C: Not affected

V: Not affected

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

The Negative bit in the status register is cleared. This avoids special treatment

with negative numbers of the subroutine called.

CLRN

CALL

......

SUBR

SUBRET

; If input is negative: do nothing and return

......

RET

SUBRET

RISC 16−Bit CPU

3-32

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Instruction Set

* CLRZ

Clear zero bit

CLRZ

Syntax

Operation

0 → Z

(.NOT.src .AND. dst −> dst)

Emulation

BIC

#2,SR

Description

The constant 02h is inverted (0FFFDh) and logically ANDed with the

destination operand. The result is placed into the destination. The clear zero

bit instruction is a word instruction.

Status Bits

N: Not affected

Z: Reset to 0

C: Not affected

V: Not affected

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

The zero bit in the status register is cleared.

CLRZ

RISC 16−Bit CPU

3-33

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Instruction Set

CMP[.W]

CMP.B

Compare source and destination

Syntax

CMP

CMP.B

src,dst

CMP.W

src,dst

Operation

dst + .NOT.src + 1

(dst − src)

Description

Status Bits

The source operand is subtracted from the destination operand. This is

accomplished by adding the 1s complement of the source operand plus 1. The

two operands are not affected and the result is not stored; only the status bits

are affected.

N: Set if result is negative, reset if positive (src >= dst)

Z: Set if result is zero, reset otherwise (src = dst)

C: Set if there is a carry from the MSB of the result, reset otherwise

V: Set if an arithmetic overflow occurs, otherwise reset

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

R5 and R6 are compared. If they are equal, the program continues at the label

EQUAL.

CMP

JEQ

R5,R6

EQUAL

; R5 = R6?

; YES, JUMP

Example

Two RAM blocks are compared. If they are not equal, the program branches

to the label ERROR.

MOV #NUM,R5

; number of words to be compared

; BLOCK1 start address in R6

; BLOCK2 start address in R7

; Are Words equal? R6 increments

; No, branch to ERROR

MOV #BLOCK1,R6

MOV #BLOCK2,R7

CMP @R6+,0(R7)

L$1

JNZ

ERROR

INCD R7

DEC R5

; Increment R7 pointer

; Are all words compared?

; No, another compare

JNZ

L$1

Example

The RAM bytes addressed by EDE and TONI are compared. If they are equal,

the program continues at the label EQUAL.

CMP.B EDE,TONI

JEQ EQUAL

; MEM(EDE) = MEM(TONI)?

; YES, JUMP

RISC 16−Bit CPU

3-34

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Instruction Set

* DADC[.W]

* DADC.B

Add carry decimally to destination

Syntax

DADC

DADC.B

dst or DADC.W src,dst

dst

Operation

Emulation

dst + C −> dst (decimally)

DADD

#0,dst

DADD.B

Description

Status Bits

The carry bit (C) is added decimally to the destination.

N: Set if MSB is 1

Z: Set if dst is 0, reset otherwise

C: Set if destination increments from 9999 to 0000, reset otherwise

Set if destination increments from 99 to 00, reset otherwise

V: Undefined

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

The four-digit decimal number contained in R5 is added to an eight-digit deci-

mal number pointed to by R8.

CLRC

; Reset carry

; next instruction’s start condition is defined

; Add LSDs + C

; Add carry to MSD

DADD

DADC

R5,0(R8)

2(R8)

Example

The two-digit decimal number contained in R5 is added to a four-digit decimal

number pointed to by R8.

CLRC

; Reset carry

; next instruction’s start condition is defined

; Add LSDs + C

; Add carry to MSDs

DADD.B

DADC

R5,0(R8)

1(R8)

RISC 16−Bit CPU

3-35

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Instruction Set

DADD[.W]

DADD.B

Source and carry added decimally to destination

Syntax

DADD

DADD.B

src,dst

or DADD.W src,dst

Operation

src + dst + C −> dst (decimally)

Description

The source operand and the destination operand are treated as four binary

coded decimals (BCD) with positive signs. The source operand and the carry

bit (C) are added decimally to the destination operand. The source operand

is not affected. The previous contents of the destination are lost. The result is

not defined for non-BCD numbers.

Status Bits

N: Set if the MSB is 1, reset otherwise

Z: Set if result is zero, reset otherwise

C: Set if the result is greater than 9999

Set if the result is greater than 99

V: Undefined

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

The eight-digit BCD number contained in R5 and R6 is added decimally to an

eight-digit BCD number contained in R3 and R4 (R6 and R4 contain the

MSDs).

CLRC

DADD

; clear carry

; add LSDs

; add MSDs with carry

R5,R3

R6,R4

OVERFLOW ; If carry occurs go to error handling routine

Example

The two-digit decimal counter in the RAM byte CNT is incremented by one.

CLRC

; clear carry

DADD.B

#1,CNT

#0,CNT

; increment decimal counter

SETC

DADD.B

; ≡ DADC.B

CNT

RISC 16−Bit CPU

3-36

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Instruction Set

* DEC[.W]

* DEC.B

Decrement destination

Syntax

DEC

DEC.B

dst

DEC.W

dst

Operation

dst − 1 −> dst

Emulation

SUB

SUB.B

#1,dst

Description

The destination operand is decremented by one. The original contents are

lost.

Status Bits

N: Set if result is negative, reset if positive

Z: Set if dst contained 1, reset otherwise

C: Reset if dst contained 0, set otherwise

V: Set if an arithmetic overflow occurs, otherwise reset.

Set if initial value of destination was 08000h, otherwise reset.

Set if initial value of destination was 080h, otherwise reset.

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

R10 is decremented by 1

DEC

R10

; Decrement R10

; Move a block of 255 bytes from memory location starting with EDE to memory location starting with

;TONI. Tables should not overlap: start of destination address TONI must not be within the range EDE

; to EDE+0FEh

;

MOV

MOV.B

DEC

#EDE,R6

#255,R10

@R6+,TONI−EDE−1(R6)

R10

L$1

JNZ

; Do not transfer tables using the routine above with the overlap shown in Figure 3−12.

Figure 3−12. Decrement Overlap

EDE

TONI

EDE+254

TONI+254

RISC 16−Bit CPU

3-37

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Instruction Set

* DECD[.W]

* DECD.B

Double-decrement destination

Syntax

DECD

DECD.B

dst or DECD.W dst

dst

Operation

dst − 2 −> dst

Emulation

SUB

SUB.B

#2,dst

Description

Status Bits

The destination operand is decremented by two. The original contents are lost.

N: Set if result is negative, reset if positive

Z: Set if dst contained 2, reset otherwise

C: Reset if dst contained 0 or 1, set otherwise

V: Set if an arithmetic overflow occurs, otherwise reset.

Set if initial value of destination was 08001 or 08000h, otherwise reset.

Set if initial value of destination was 081 or 080h, otherwise reset.

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

R10 is decremented by 2.

DECD

R10

; Decrement R10 by two

; Move a block of 255 words from memory location starting with EDE to memory location

; starting with TONI

; Tables should not overlap: start of destination address TONI must not be within the

; range EDE to EDE+0FEh

;

MOV

DECD

JNZ

#EDE,R6

#510,R10

@R6+,TONI−EDE−2(R6)

R10

L$1

Example

Memory at location LEO is decremented by two.

DECD.B LEO ; Decrement MEM(LEO)

Decrement status byte STATUS by two.

DECD.B STATUS

RISC 16−Bit CPU

3-38

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Instruction Set

* DINT

Disable (general) interrupts

DINT

Syntax

Operation

0 → GIE

(0FFF7h .AND. SR → SR

.NOT.src .AND. dst −> dst)

Emulation

BIC

#8,SR

Description

All interrupts are disabled.

The constant 08h is inverted and logically ANDed with the status register (SR).

The result is placed into the SR.

Status Bits

Mode Bits

Example

Status bits are not affected.

GIE is reset. OSCOFF and CPUOFF are not affected.

The general interrupt enable (GIE) bit in the status register is cleared to allow

a nondisrupted move of a 32-bit counter. This ensures that the counter is not

modified during the move by any interrupt.

DINT

NOP

MOV

EINT

; All interrupt events using the GIE bit are disabled

COUNTHI,R5 ; Copy counter

COUNTLO,R6

; All interrupt events using the GIE bit are enabled

Note: Disable Interrupt

If any code sequence needs to be protected from interruption, the DINT

should be executed at least one instruction before the beginning of the

uninterruptible sequence, or should be followed by a NOP instruction.

RISC 16−Bit CPU

3-39

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Instruction Set

* EINT

Enable (general) interrupts

EINT

Syntax

Operation

1 → GIE

(0008h .OR. SR −> SR / .src .OR. dst −> dst)

Emulation

BIS

#8,SR

Description

All interrupts are enabled.

The constant #08h and the status register SR are logically ORed. The result

is placed into the SR.

Status Bits

Mode Bits

Example

Status bits are not affected.

GIE is set. OSCOFF and CPUOFF are not affected.

The general interrupt enable (GIE) bit in the status register is set.

; Interrupt routine of ports P1.2 to P1.7

; P1IN is the address of the register where all port bits are read. P1IFG is the address of

; the register where all interrupt events are latched.

;

PUSH.B &P1IN

BIC.B

EINT

@SP,&P1IFG ; Reset only accepted flags

; Preset port 1 interrupt flags stored on stack

; other interrupts are allowed

BIT

#Mask,@SP

MaskOK

JEQ

......

BIC

......

INCD

; Flags are present identically to mask: jump

MaskOK

#Mask,@SP

; Housekeeping: inverse to PUSH instruction

; at the start of interrupt subroutine. Corrects

; the stack pointer.

RETI

Note: Enable Interrupt

The instruction following the enable interrupt instruction (EINT) is always

executed, even if an interrupt service request is pending when the interrupts

are enable.

RISC 16−Bit CPU

3-40

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Instruction Set

* INC[.W]

* INC.B

Increment destination

Syntax

INC

INC.B

dst

or INC.W dst

Operation

Emulation

Description

Status Bits

dst + 1 −> dst

ADD #1,dst

The destination operand is incremented by one. The original contents are lost.

N: Set if result is negative, reset if positive

Z: Set if dst contained 0FFFFh, reset otherwise

Set if dst contained 0FFh, reset otherwise

C: Set if dst contained 0FFFFh, reset otherwise

Set if dst contained 0FFh, reset otherwise

V: Set if dst contained 07FFFh, reset otherwise

Set if dst contained 07Fh, reset otherwise

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

The status byte, STATUS, of a process is incremented. When it is equal to 11,

a branch to OVFL is taken.

INC.B

CMP.B

JEQ

STATUS

#11,STATUS

OVFL

RISC 16−Bit CPU

3-41

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Instruction Set

* INCD[.W]

* INCD.B

Double-increment destination

Syntax

INCD

INCD.B

dst

or INCD.W

dst

Operation

dst + 2 −> dst

Emulation

ADD

ADD.B

#2,dst

Example

The destination operand is incremented by two. The original contents are lost.

Status Bits

N: Set if result is negative, reset if positive

Z: Set if dst contained 0FFFEh, reset otherwise

Set if dst contained 0FEh, reset otherwise

C: Set if dst contained 0FFFEh or 0FFFFh, reset otherwise

Set if dst contained 0FEh or 0FFh, reset otherwise

V: Set if dst contained 07FFEh or 07FFFh, reset otherwise

Set if dst contained 07Eh or 07Fh, reset otherwise

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

The item on the top of the stack (TOS) is removed without using a register.

.......

PUSH

; R5 is the result of a calculation, which is stored

; in the system stack

INCD

; Remove TOS by double-increment from stack

; Do not use INCD.B, SP is a word-aligned

; register

RET

Example

The byte on the top of the stack is incremented by two.

INCD.B 0(SP) ; Byte on TOS is increment by two

RISC 16−Bit CPU

3-42

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Instruction Set

* INV[.W]

* INV.B

Invert destination

Syntax

INV

INV.B

dst

Operation

.NOT.dst −> dst

Emulation

XOR

XOR.B

#0FFFFh,dst

#0FFh,dst

Description

Status Bits

The destination operand is inverted. The original contents are lost.

N: Set if result is negative, reset if positive

Z: Set if dst contained 0FFFFh, reset otherwise

Set if dst contained 0FFh, reset otherwise

C: Set if result is not zero, reset otherwise ( = .NOT. Zero)

Set if result is not zero, reset otherwise ( = .NOT. Zero)

V: Set if initial destination operand was negative, otherwise reset

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

Content of R5 is negated (twos complement).

MOV

INV

INC

#00AEh,R5 ;

R5 = 000AEh

R5 = 0FF51h

R5 = 0FF52h

; Invert R5,

; R5 is now negated,

Example

Content of memory byte LEO is negated.

MOV.B

INV.B

#0AEh,LEO ;

LEO

MEM(LEO) = 0AEh

MEM(LEO) = 051h

; Invert LEO,

INC.B

LEO

; MEM(LEO) is negated,MEM(LEO) = 052h

RISC 16−Bit CPU

3-43

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Instruction Set

Jump if carry set

JHS

Jump if higher or same

Syntax

JHS

label

Operation

Description

If C = 1: PC + 2 × offset −> PC

If C = 0: execute following instruction

The status register carry bit (C) is tested. If it is set, the 10-bit signed offset

contained in the instruction LSBs is added to the program counter. If C is reset,

the next instruction following the jump is executed. JC (jump if carry/higher or

same) is used for the comparison of unsigned numbers (0 to 65536).

Status Bits

Example

Status bits are not affected.

The P1IN.1 signal is used to define or control the program flow.

BIT

......

#01h,&P1IN

PROGA

; State of signal −> Carry

; If carry=1 then execute program routine A

; Carry=0, execute program here

Example

R5 is compared to 15. If the content is higher or the same, branch to LABEL.

CMP

JHS

......

#15,R5

LABEL

; Jump is taken if R5 ≥ 15

; Continue here if R5 < 15

RISC 16−Bit CPU

3-44

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Instruction Set

JEQ, JZ

Syntax

Jump if equal, jump if zero

JEQ label, JZ

label

Operation

If Z = 1: PC + 2 × offset −> PC

If Z = 0: execute following instruction

Description

The status register zero bit (Z) is tested. If it is set, the 10-bit signed offset

contained in the instruction LSBs is added to the program counter. If Z is not

set, the instruction following the jump is executed.

Status Bits

Example

Status bits are not affected.

Jump to address TONI if R7 contains zero.

TST

TONI

; Test R7

; if zero: JUMP

Example

Jump to address LEO if R6 is equal to the table contents.

CMP

R6,Table(R5) ; Compare content of R6 with content of

; MEM (table address + content of R5)

JEQ

......

LEO

; Jump if both data are equal

; No, data are not equal, continue here

Branch to LABEL if R5 is 0.

TST

LABEL

......

RISC 16−Bit CPU

3-45

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Instruction Set

JGE

Jump if greater or equal

JGE label

Syntax

Operation

If (N .XOR. V) = 0 then jump to label: PC + 2 × offset −> PC

If (N .XOR. V) = 1 then execute the following instruction

Description

The status register negative bit (N) and overflow bit (V) are tested. If both N

and V are set or reset, the 10-bit signed offset contained in the instruction LSBs

is added to the program counter. If only one is set, the instruction following the

jump is executed.

This allows comparison of signed integers.

Status bits are not affected.

Status Bits

Example

When the content of R6 is greater or equal to the memory pointed to by R7,

the program continues at label EDE.

CMP

JGE

......

@R7,R6

EDE

; R6 ≥ (R7)?, compare on signed numbers

; Yes, R6 ≥ (R7)

; No, proceed

......

RISC 16−Bit CPU

3-46

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Instruction Set

Jump if less

Syntax

Operation

label

If (N .XOR. V) = 1 then jump to label: PC + 2 × offset −> PC

If (N .XOR. V) = 0 then execute following instruction

Description

The status register negative bit (N) and overflow bit (V) are tested. If only one

is set, the 10-bit signed offset contained in the instruction LSBs is added to the

program counter. If both N and V are set or reset, the instruction following the

jump is executed.

This allows comparison of signed integers.

Status bits are not affected.

Status Bits

Example

When the content of R6 is less than the memory pointed to by R7, the program

continues at label EDE.

CMP

@R7,R6

EDE

; R6 < (R7)?, compare on signed numbers

; Yes, R6 < (R7)

......

; No, proceed

RISC 16−Bit CPU

3-47

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Instruction Set

JMP

Jump unconditionally

JMP label

Syntax

Operation

Description

PC + 2 × offset −> PC

The 10-bit signed offset contained in the instruction LSBs is added to the

program counter.

Status Bits

Status bits are not affected.

Hint:

This one-word instruction replaces the BRANCH instruction in the range of

−511 to +512 words relative to the current program counter.

RISC 16−Bit CPU

3-48

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Instruction Set

Jump if negative

JN label

Syntax

Operation

if N = 1: PC + 2 × offset −> PC

if N = 0: execute following instruction

Description

The negative bit (N) of the status register is tested. If it is set, the 10-bit signed

offset contained in the instruction LSBs is added to the program counter. If N

is reset, the next instruction following the jump is executed.

Status Bits

Example

Status bits are not affected.

The result of a computation in R5 is to be subtracted from COUNT. If the result

is negative, COUNT is to be cleared and the program continues execution in

another path.

SUB

R5,COUNT

L$1

; COUNT − R5 −> COUNT

; If negative continue with COUNT=0 at PC=L$1

; Continue with COUNT≥0

......

CLR

......

L$1

COUNT

RISC 16−Bit CPU

3-49

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Instruction Set

JNC

JLO

Jump if carry not set

Jump if lower

Syntax

JNC

JLO

label

Operation

Description

if C = 0: PC + 2 × offset −> PC

if C = 1: execute following instruction

The status register carry bit (C) is tested. If it is reset, the 10-bit signed offset

contained in the instruction LSBs is added to the program counter. If C is set,

the next instruction following the jump is executed. JNC (jump if no carry/lower)

is used for the comparison of unsigned numbers (0 to 65536).

Status Bits

Example

Status bits are not affected.

The result in R6 is added in BUFFER. If an overflow occurs, an error handling

routine at address ERROR is used.

ADD

JNC

......

R6,BUFFER

CONT

; BUFFER + R6 −> BUFFER

; No carry, jump to CONT

; Error handler start

ERROR

CONT

; Continue with normal program flow

Example

Branch to STL2 if byte STATUS contains 1 or 0.

CMP.B

JLO

#2,STATUS

STL2

; STATUS < 2

......

; STATUS ≥ 2, continue here

RISC 16−Bit CPU

3-50

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Instruction Set

JNE

JNZ

Jump if not equal

Jump if not zero

Syntax

JNE

JNZ

label

Operation

Description

If Z = 0: PC + 2 × offset −> PC

If Z = 1: execute following instruction

The status register zero bit (Z) is tested. If it is reset, the 10-bit signed offset

contained in the instruction LSBs is added to the program counter. If Z is set,

the next instruction following the jump is executed.

Status Bits

Example

Status bits are not affected.

Jump to address TONI if R7 and R8 have different contents.

CMP

JNE

......

R7,R8

TONI

; COMPARE R7 WITH R8

; if different: jump

; if equal, continue

RISC 16−Bit CPU

3-51

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Instruction Set

MOV[.W]

MOV.B

Move source to destination

Syntax

MOV

MOV.B

src,dst

MOV.W

src,dst

Operation

src −> dst

Description

The source operand is moved to the destination.

The source operand is not affected. The previous contents of the destination

are lost.

Status Bits

Mode Bits

Example

Status bits are not affected.

OSCOFF, CPUOFF, and GIE are not affected.

The contents of table EDE (word data) are copied to table TOM. The length

of the tables must be 020h locations.

MOV #EDE,R10

MOV #020h,R9

; Prepare pointer

; Prepare counter

Loop

MOV @R10+,TOM−EDE−2(R10) ; Use pointer in R10 for both tables

DEC R9

; Decrement counter

JNZ

......

Loop

; Counter ≠ 0, continue copying

; Copying completed

Example

The contents of table EDE (byte data) are copied to table TOM. The length of

the tables should be 020h locations

MOV #EDE,R10

MOV #020h,R9

; Prepare pointer

; Prepare counter

Loop

MOV.B @R10+,TOM−EDE−1(R10) ; Use pointer in R10 for

; both tables

DEC R9

; Decrement counter

; Counter ≠ 0, continue

; copying

JNZ

Loop

......

; Copying completed

RISC 16−Bit CPU

3-52

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Instruction Set

* NOP

No operation

NOP

Syntax

Operation

Emulation

Description

None

MOV

#0, R3

No operation is performed. The instruction may be used for the elimination of

instructions during the software check or for defined waiting times.

Status Bits

Status bits are not affected.

The NOP instruction is mainly used for two purposes:

- To fill one, two, or three memory words

- To adjust software timing

Note: Emulating No-Operation Instruction

Other instructions can emulate the NOP function while providing different

numbers of instruction cycles and code words. Some examples are:

Examples:

MOV

BIC

JMP

BIC

#0,R3

; 1 cycle, 1 word

; 6 cycles, 3 words

; 5 cycles, 2 words

; 4 cycles, 2 words

; 2 cycles, 1 word

; 1 cycle, 1 word

0(R4),0(R4)

@R4,0(R4)

#0,EDE(R4)

$+2

#0,R5

However, care should be taken when using these examples to prevent

unintended results. For example, if MOV 0(R4), 0(R4) is used and the value

in R4 is 120h, then a security violation will occur with the watchdog timer

(address 120h) because the security key was not used.

RISC 16−Bit CPU

3-53

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Instruction Set

* POP[.W]

* POP.B

Pop word from stack to destination

Pop byte from stack to destination

Syntax

POP

POP.B

dst

Operation

@SP −> temp

SP + 2 −> SP

temp −> dst

Emulation

MOV

MOV.B

@SP+,dst

MOV.W

@SP+,dst

Description

The stack location pointed to by the stack pointer (TOS) is moved to the

destination. The stack pointer is incremented by two afterwards.

Status Bits

Example

Status bits are not affected.

The contents of R7 and the status register are restored from the stack.

POP

; Restore R7

; Restore status register

Example

The contents of RAM byte LEO is restored from the stack.

POP.B LEO ; The low byte of the stack is moved to LEO.

The contents of R7 is restored from the stack.

POP.B

; The low byte of the stack is moved to R7,

; the high byte of R7 is 00h

Example

The contents of the memory pointed to by R7 and the status register are

restored from the stack.

POP.B

0(R7)

; The low byte of the stack is moved to the

; the byte which is pointed to by R7

: Example: R7 = 203h

;

Mem(R7) = low byte of system stack

: Example: R7 = 20Ah

;

Mem(R7) = low byte of system stack

POP

; Last word on stack moved to the SR

Note: The System Stack Pointer

The system stack pointer (SP) is always incremented by two, independent

of the byte suffix.

RISC 16−Bit CPU

3-54

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Instruction Set

PUSH[.W]

PUSH.B

Push word onto stack

Push byte onto stack

Syntax

PUSH

PUSH.B

src

PUSH.W

src

Operation

Description

SP − 2 → SP

src → @SP

The stack pointer is decremented by two, then the source operand is moved

to the RAM word addressed by the stack pointer (TOS).

Status Bits

Mode Bits

Example

Status bits are not affected.

OSCOFF, CPUOFF, and GIE are not affected.

The contents of the status register and R8 are saved on the stack.

PUSH

; save status register

; save R8

Example

The contents of the peripheral TCDAT is saved on the stack.

PUSH.B

&TCDAT

; save data from 8-bit peripheral module,

; address TCDAT, onto stack

Note: The System Stack Pointer

The system stack pointer (SP) is always decremented by two, independent

of the byte suffix.

RISC 16−Bit CPU

3-55

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Instruction Set

* RET

Return from subroutine

RET

Syntax

Operation

@SP→ PC

SP + 2 → SP

Emulation

MOV

@SP+,PC

Description

The return address pushed onto the stack by a CALL instruction is moved to

the program counter. The program continues at the code address following the

subroutine call.

Status Bits

Status bits are not affected.

RISC 16−Bit CPU

3-56

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Instruction Set

RETI

Return from interrupt

RETI

Syntax

Operation

TOS

→ SR

→ SP

→ PC

→ SP

SP + 2

TOS

SP + 2

Description

The status register is restored to the value at the beginning of the interrupt

service routine by replacing the present SR contents with the TOS contents.

The stack pointer (SP) is incremented by two.

The program counter is restored to the value at the beginning of interrupt

service. This is the consecutive step after the interrupted program flow.

Restoration is performed by replacing the present PC contents with the TOS

memory contents. The stack pointer (SP) is incremented.

Status Bits

N: restored from system stack

Z: restored from system stack

C: restored from system stack

V: restored from system stack

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are restored from system stack.

Figure 3−13 illustrates the main program interrupt.

Figure 3−13. Main Program Interrupt

PC −6

PC −4

PC −2

Interrupt Request

Interrupt Accepted

PC+2 is Stored

Onto Stack

PC +2

PC +4

PC +6

PC +8

PC = PCi

PCi +2

PCi +4

PCi +n−4

PCi +n−2

PCi +n

RETI

RISC 16−Bit CPU

3-57

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Instruction Set

* RLA[.W]

* RLA.B

Rotate left arithmetically

Syntax

RLA

RLA.B

dst

RLA.W

dst

Operation

Emulation

C <− MSB <− MSB−1 .... LSB+1 <− LSB <− 0

ADD

dst,dst

ADD.B

Description

The destination operand is shifted left one position as shown in Figure 3−14.

The MSB is shifted into the carry bit (C) and the LSB is filled with 0. The RLA

instruction acts as a signed multiplication by 2.

An overflow occurs if dst ≥ 04000h and dst < 0C000h before operation is

performed: the result has changed sign.

Figure 3−14. Destination Operand—Arithmetic Shift Left

Word

Byte

An overflow occurs if dst ≥ 040h and dst < 0C0h before the operation is

performed: the result has changed sign.

Status Bits

N: Set if result is negative, reset if positive

Z: Set if result is zero, reset otherwise

C: Loaded from the MSB

V: Set if an arithmetic overflow occurs:

the initial value is 04000h ≤ dst < 0C000h; reset otherwise

Set if an arithmetic overflow occurs:

the initial value is 040h ≤ dst < 0C0h; reset otherwise

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

R7 is multiplied by 2.

RLA

; Shift left R7 (× 2)

Example

The low byte of R7 is multiplied by 4.

RLA.B

; Shift left low byte of R7 (× 2)

; Shift left low byte of R7 (× 4)

Note: RLA Substitution

The assembler does not recognize the instruction:

RLA

It must be substituted by:

ADD @R5+,−2(R5)

@R5+

nor

RLA.B

@R5+.

ADD.B @R5+,−1(R5).

RISC 16−Bit CPU

3-58

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Instruction Set

* RLC[.W]

* RLC.B

Rotate left through carry

Syntax

RLC

RLC.B

dst

RLC.W

dst

Operation

Emulation

Description

C <− MSB <− MSB−1 .... LSB+1 <− LSB <− C

ADDC dst,dst

The destination operand is shifted left one position as shown in Figure 3−15.

The carry bit (C) is shifted into the LSB and the MSB is shifted into the carry

bit (C).

Figure 3−15. Destination Operand—Carry Left Shift

Word

Byte

Status Bits

N: Set if result is negative, reset if positive

Z: Set if result is zero, reset otherwise

C: Loaded from the MSB

V: Set if an arithmetic overflow occurs

the initial value is 04000h ≤ dst < 0C000h; reset otherwise

Set if an arithmetic overflow occurs:

the initial value is 040h ≤ dst < 0C0h; reset otherwise

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

R5 is shifted left one position.

RLC

; (R5 x 2) + C −> R5

Example

The input P1IN.1 information is shifted into the LSB of R5.

BIT.B

RLC

#2,&P1IN

; Information −> Carry

; Carry=P0in.1 −> LSB of R5

The MEM(LEO) content is shifted left one position.

RLC.B LEO ; Mem(LEO) x 2 + C −> Mem(LEO)

Note: RLC and RLC.B Substitution

The assembler does not recognize the instruction:

RLC

@R5+.

It must be substituted by:

ADDC @R5+,−2(R5).

RISC 16−Bit CPU

3-59

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Instruction Set

RRA[.W]

RRA.B

Rotate right arithmetically

Syntax

RRA

RRA.B

dst

RRA.W dst

Operation

MSB −> MSB, MSB −> MSB−1, ... LSB+1 −> LSB, LSB −> C

Description

The destination operand is shifted right one position as shown in Figure 3−16.

The MSB is shifted into the MSB, the MSB is shifted into the MSB−1, and the

LSB+1 is shifted into the LSB.

Figure 3−16. Destination Operand—Arithmetic Right Shift

Word

Byte

Status Bits

N: Set if result is negative, reset if positive

Z: Set if result is zero, reset otherwise

C: Loaded from the LSB

V: Reset

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

R5 is shifted right one position. The MSB retains the old value. It operates

equal to an arithmetic division by 2.

RRA

; R5/2 −> R5

;

The value in R5 is multiplied by 0.75 (0.5 + 0.25).

PUSH

RRA

ADD

RRA

......

; Hold R5 temporarily using stack

; R5 × 0.5 −> R5

@SP+,R5 ; R5 × 0.5 + R5 = 1.5 × R5 −> R5

R5 ; (1.5 × R5) × 0.5 = 0.75 × R5 −> R5

Example

The low byte of R5 is shifted right one position. The MSB retains the old value.

It operates equal to an arithmetic division by 2.

RRA.B

; R5/2 −> R5: operation is on low byte only

; High byte of R5 is reset

PUSH.B

RRA.B

ADD.B

......

@SP

; R5 × 0.5 −> TOS

; TOS × 0.5 = 0.5 × R5 × 0.5 = 0.25 × R5 −> TOS

@SP+,R5 ; R5 × 0.5 + R5 × 0.25 = 0.75 × R5 −> R5

RISC 16−Bit CPU

3-60

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Instruction Set

RRC[.W]

RRC.B

Rotate right through carry

Syntax

RRC

dst

RRC.W dst

Operation

C −> MSB −> MSB−1 .... LSB+1 −> LSB −> C

Description

The destination operand is shifted right one position as shown in Figure 3−17.

The carry bit (C) is shifted into the MSB, the LSB is shifted into the carry bit (C).

Figure 3−17. Destination Operand—Carry Right Shift

Word

Byte

Status Bits

N: Set if result is negative, reset if positive

Z: Set if result is zero, reset otherwise

C: Loaded from the LSB

V: Set if initial destination is positive and initial carry is set, otherwise reset

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

R5 is shifted right one position. The MSB is loaded with 1.

SETC

RRC

; Prepare carry for MSB

; R5/2 + 8000h −> R5

Example

R5 is shifted right one position. The MSB is loaded with 1.

SETC

; Prepare carry for MSB

RRC.B

; R5/2 + 80h −> R5; low byte of R5 is used

RISC 16−Bit CPU

3-61

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Instruction Set

* SBC[.W]

* SBC.B

Subtract source and borrow/.NOT. carry from destination

Syntax

SBC

SBC.B

dst

SBC.W

dst

Operation

Emulation

Description

Status Bits

dst + 0FFFFh + C −> dst

dst + 0FFh + C −> dst

SUBC

#0,dst

SUBC.B #0,dst

The carry bit (C) is added to the destination operand minus one. The previous

contents of the destination are lost.

N: Set if result is negative, reset if positive

Z: Set if result is zero, reset otherwise

C: Set if there is a carry from the MSB of the result, reset otherwise.

Set to 1 if no borrow, reset if borrow.

V: Set if an arithmetic overflow occurs, reset otherwise.

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

The 16-bit counter pointed to by R13 is subtracted from a 32-bit counter

pointed to by R12.

SUB

SBC

@R13,0(R12)

2(R12)

; Subtract LSDs

; Subtract carry from MSD

Example

The 8-bit counter pointed to by R13 is subtracted from a 16-bit counter pointed

to by R12.

SUB.B

SBC.B

@R13,0(R12)

1(R12)

; Subtract LSDs

; Subtract carry from MSD

Note: Borrow Implementation.

The borrow is treated as a .NOT. carry :

Borrow

Yes

Carry bit

RISC 16−Bit CPU

3-62

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Instruction Set

* SETC

Set carry bit

SETC

Syntax

Operation

Emulation

Description

Status Bits

1 −> C

BIS

#1,SR

The carry bit (C) is set.

N: Not affected

Z: Not affected

C: Set

V: Not affected

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

Emulation of the decimal subtraction:

Subtract R5 from R6 decimally

Assume that R5 = 03987h and R6 = 04137h

DSUB

ADD

INV

#06666h,R5

; Move content R5 from 0−9 to 6−0Fh

; R5 = 03987h + 06666h = 09FEDh

; Invert this (result back to 0−9)

; R5 = .NOT. R5 = 06012h

; Prepare carry = 1

; Emulate subtraction by addition of:

; (010000h − R5 − 1)

SETC

DADD

R5,R6

; R6 = R6 + R5 + 1

; R6 = 0150h

RISC 16−Bit CPU

3-63

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Instruction Set

* SETN

Set negative bit

SETN

Syntax

Operation

Emulation

Description

Status Bits

1 −> N

BIS

#4,SR

The negative bit (N) is set.

N: Set

Z: Not affected

C: Not affected

V: Not affected

Mode Bits

OSCOFF, CPUOFF, and GIE are not affected.

RISC 16−Bit CPU

3-64

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Instruction Set

* SETZ

Set zero bit

SETZ

Syntax

Operation

Emulation

Description

Status Bits

1 −> Z

BIS

#2,SR

The zero bit (Z) is set.

N: Not affected

Z: Set

C: Not affected

V: Not affected

Mode Bits

OSCOFF, CPUOFF, and GIE are not affected.

RISC 16−Bit CPU

3-65

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Instruction Set

SUB[.W]

SUB.B

Subtract source from destination

Syntax

SUB

SUB.B

src,dst

SUB.W

src,dst

Operation

dst + .NOT.src + 1 −> dst

[(dst − src −> dst)]

Description

Status Bits

The source operand is subtracted from the destination operand by adding the

source operand’s 1s complement and the constant 1. The source operand is

not affected. The previous contents of the destination are lost.

N: Set if result is negative, reset if positive

Z: Set if result is zero, reset otherwise

C: Set if there is a carry from the MSB of the result, reset otherwise.

Set to 1 if no borrow, reset if borrow.

V: Set if an arithmetic overflow occurs, otherwise reset

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

See example at the SBC instruction.

See example at the SBC.B instruction.

Note: Borrow Is Treated as a .NOT.

The borrow is treated as a .NOT. carry :

Borrow

Yes

Carry bit

RISC 16−Bit CPU

3-66

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Instruction Set

SUBC[.W]SBB[.W]

SUBC.B,SBB.B

Subtract source and borrow/.NOT. carry from destination

Syntax

SUBC

SBB

SUBC.B src,dst

src,dst

SUBC.W

SBB.W

SBB.B

src,dst or

src,dst

Operation

Description

Status Bits

dst + .NOT.src + C −> dst

(dst − src − 1 + C −> dst)

The source operand is subtracted from the destination operand by adding the

source operand’s 1s complement and the carry bit (C). The source operand

is not affected. The previous contents of the destination are lost.

N: Set if result is negative, reset if positive.

Z: Set if result is zero, reset otherwise.

C: Set if there is a carry from the MSB of the result, reset otherwise.

Set to 1 if no borrow, reset if borrow.

V: Set if an arithmetic overflow occurs, reset otherwise.

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

Two floating point mantissas (24 bits) are subtracted.

LSBs are in R13 and R10, MSBs are in R12 and R9.

SUB.W

R13,R10 ; 16-bit part, LSBs

SUBC.B R12,R9 ; 8-bit part, MSBs

Example

The 16-bit counter pointed to by R13 is subtracted from a 16-bit counter in R10

and R11(MSD).

SUB.B

SUBC.B @R13,R11

...

@R13+,R10

; Subtract LSDs without carry

; Subtract MSDs with carry

; resulting from the LSDs

Note: Borrow Implementation

The borrow is treated as a .NOT. carry :

Borrow

Yes

Carry bit

RISC 16−Bit CPU

3-67

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Instruction Set

SWPB

Swap bytes

Syntax

SWPB

dst

Operation

Description

Bits 15 to 8 <−> bits 7 to 0

The destination operand high and low bytes are exchanged as shown in

Figure 3−18.

Status Bits

Mode Bits

Status bits are not affected.

OSCOFF, CPUOFF, and GIE are not affected.

Figure 3−18. Destination Operand Byte Swap

Example

MOV

SWPB

#040BFh,R7

; 0100000010111111 −> R7

; 1011111101000000 in R7

Example

The value in R5 is multiplied by 256. The result is stored in R5,R4.

SWPB

MOV

BIC

R5,R4

#0FF00h,R5

#00FFh,R4

;

;Copy the swapped value to R4

;Correct the result

BIC

RISC 16−Bit CPU

3-68

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Instruction Set

SXT

Extend Sign

Syntax

SXT

dst

Operation

Description

Status Bits

Bit 7 −> Bit 8 ......... Bit 15

The sign of the low byte is extended into the high byte as shown in Figure 3−19.

N: Set if result is negative, reset if positive

Z: Set if result is zero, reset otherwise

C: Set if result is not zero, reset otherwise (.NOT. Zero)

V: Reset

Mode Bits

OSCOFF, CPUOFF, and GIE are not affected.

Figure 3−19. Destination Operand Sign Extension

Example

R7 is loaded with the P1IN value. The operation of the sign-extend instruction

expands bit 8 to bit 15 with the value of bit 7.

R7 is then added to R6.

MOV.B

SXT

&P1IN,R7

; P1IN = 080h:

; R7 = 0FF80h:

. . . . . . . . 1000 0000

1111 1111 1000 0000

RISC 16−Bit CPU

3-69

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Instruction Set

* TST[.W]

* TST.B

Test destination

Syntax

TST

TST.B

dst

or TST.W dst

Operation

Emulation

Description

Status Bits

dst + 0FFFFh + 1

dst + 0FFh + 1

CMP

CMP.B

#0,dst

The destination operand is compared with zero. The status bits are set accord-

ing to the result. The destination is not affected.

N: Set if destination is negative, reset if positive

Z: Set if destination contains zero, reset otherwise

C: Set

V: Reset

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero,

continue at R7POS.

TST

R7NEG

R7ZERO

; Test R7

; R7 is negative

; R7 is zero

R7POS

R7NEG

R7ZERO

......

; R7 is positive but not zero

; R7 is negative

; R7 is zero

Example

The low byte of R7 is tested. If it is negative, continue at R7NEG; if it is positive

but not zero, continue at R7POS.

TST.B

R7NEG

R7ZERO

; Test low byte of R7

; Low byte of R7 is negative

; Low byte of R7 is zero

R7POS

R7NEG

R7ZERO

......

.....

......

; Low byte of R7 is positive but not zero

; Low byte of R7 is negative

; Low byte of R7 is zero

RISC 16−Bit CPU

3-70

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Instruction Set

XOR[.W]

XOR.B

Exclusive OR of source with destination

Syntax

XOR

XOR.B

src,dst

XOR.W

src,dst

Operation

src .XOR. dst −> dst

Description

The source and destination operands are exclusive ORed. The result is placed

into the destination. The source operand is not affected.

Status Bits

N: Set if result MSB is set, reset if not set

Z: Set if result is zero, reset otherwise

C: Set if result is not zero, reset otherwise ( = .NOT. Zero)

V: Set if both operands are negative

Mode Bits

Example

OSCOFF, CPUOFF, and GIE are not affected.

The bits set in R6 toggle the bits in the RAM word TONI.

XOR

R6,TONI

; Toggle bits of word TONI on the bits set in R6

Example

The bits set in R6 toggle the bits in the RAM byte TONI.

XOR.B

R6,TONI

; Toggle bits of byte TONI on the bits set in

; low byte of R6

Reset to 0 those bits in low byte of R7 that are different from bits in RAM byte

EDE.

XOR.B

INV.B

EDE,R7

; Set different bit to “1s”

; Invert Lowbyte, Highbyte is 0h

RISC 16−Bit CPU

3-71

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Instruction Set

3.4.4 Instruction Cycles and Lengths

The number of CPU clock cycles required for an instruction depends on the

instruction format and the addressing modes used - not the instruction itself.

The number of clock cycles refers to the MCLK.

Interrupt and Reset Cycles

Table 3−14 lists the CPU cycles for interrupt overhead and reset.

Table 3−14.Interrupt and Reset Cycles

No. of

Cycles

Length of

Instruction

Action

Return from interrupt (RETI)

−

Interrupt accepted

WDT reset

Reset (RST/NMI)

Format-II (Single Operand) Instruction Cycles and Lengths

Table 3−15 lists the length and CPU cycles for all addressing modes of

format-II instructions.

Table 3−15.Format-II Instruction Cycles and Lengths

No. of Cycles

RRA, RRC

Addressing

Mode

Length of

Instruction

SWPB, SXT

PUSH

CALL

Example

SWPB R5

@Rn

@Rn+

RRC @R9

SWPB @R10+

CALL #0F000h

CALL 2(R7)

PUSH EDE

(See note)

X(Rn)

EDE

&EDE

SXT &EDE

Note: Instruction Format II Immediate Mode

Do not use instructions RRA, RRC, SWPB, and SXTwith the immediate

mode in the destination field. Use of these in the immediate mode results in

an unpredictable program operation.

Format-III (Jump) Instruction Cycles and Lengths

All jump instructions require one code word, and take two CPU cycles to

execute, regardless of whether the jump is taken or not.

RISC 16−Bit CPU

3-72

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Instruction Set

Format-I (Double Operand) Instruction Cycles and Lengths

Table 3−16 lists the length and CPU cycles for all addressing modes of format-I

instructions.

Table 3−16.Format 1 Instruction Cycles and Lengths

No. of

Cycles

Length of

Instruction

Addressing Mode

Src Dst

Example

R5,R8

MOV

x(Rm)

EDE

&EDE

ADD

XOR

MOV

AND

R5,4(R6)

R8,EDE

R5,&EDE

@R4,R5

@Rn

@Rn+

@R8

x(Rm)

EDE

&EDE

XOR

MOV

XOR

ADD

@R5,8(R6)

@R5,EDE

@R5,&EDE

@R5+,R6

@R9+

x(Rm)

EDE

&EDE

XOR

MOV

@R5,8(R6)

@R9+,EDE

@R9+,&EDE

#20,R9

#2AEh

x(Rm)

EDE

&EDE

MOV

ADD

MOV

#0300h,0(SP)

#33,EDE

#33,&EDE

2(R5),R7

2(R6)

x(Rn)

EDE

TONI

x(Rm)

&TONI

MOV

ADD

MOV

AND

4(R7),TONI

4(R4),6(R9)

2(R4),&TONI

EDE,R6

EDE

TONI

x(Rm)

&TONI

CMP

MOV

BRA

MOV

EDE,TONI

EDE,0(SP)

EDE,&TONI

&EDE,R8

&EDE

TONI

x(Rm)

&TONI

&EDE,TONI

&EDE,0(SP)

&EDE,&TONI

RISC 16−Bit CPU

3-73

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Instruction Set

3.4.5 Instruction Set Description

The instruction map is shown in Figure 3−20 and the complete instruction set

is summarized in Table 3−17.

Figure 3−20. Core Instruction Map

380 3C0

000 040 080 0C0 100 140 180 1C0 200 240 280 2C0 300 340

0xxx

4xxx

8xxx

Cxxx

1xxx RRC

14xx

18xx

1Cxx

20xx

24xx

28xx

2Cxx

30xx

34xx

38xx

3Cxx

4xxx

5xxx

6xxx

7xxx

8xxx

9xxx

Axxx

Bxxx

Cxxx

Dxxx

Exxx

Fxxx

RRC.B SWPB

RRA RRA.B

SXT

PUSH PUSH.B CALL

RETI

JNE/JNZ

JEQ/JZ

JNC

JGE

JMP

MOV, MOV.B

ADD, ADD.B

ADDC, ADDC.B

SUBC, SUBC.B

SUB, SUB.B

CMP, CMP.B

DADD, DADD.B

BIT, BIT.B

BIC, BIC.B

BIS, BIS.B

XOR, XOR.B

AND, AND.B

RISC 16−Bit CPU

3-74

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Instruction Set

Table 3−17.MSP430 Instruction Set

Mnemonic

Description

†

ADC(.B)

dst

Add C to destination

Add source to destination

Add source and C to destination

AND source and destination

Clear bits in destination

Set bits in destination

Test bits in destination

Branch to destination

Call destination

dst + C → dst

src + dst → dst

src + dst + C → dst

src .and. dst → dst

.not.src .and. dst → dst

src .or. dst → dst

src .and. dst

ADD(.B)

ADDC(.B)

AND(.B)

BIC(.B)

BIS(.B)

BIT(.B)

src,dst

dst

−

†

dst → PC

−

CALL

dst

PC+2 → stack, dst → PC

0 → dst

†

CLR(.B)

dst

Clear destination

†

CLRC

Clear C

0 → C

†

CLRN

Clear N

0 → N

†

CLRZ

Clear Z

0 → Z

CMP(.B)

src,dst

dst

Compare source and destination

Add C decimally to destination

Add source and C decimally to dst.

Decrement destination

Double-decrement destination

Disable interrupts

dst − src

†

DADC(.B)

dst + C → dst (decimally)

src + dst + C → dst (decimally)

dst − 1 → dst

dst − 2 → dst

0 → GIE

DADD(.B)

src,dst

dst

†

DEC(.B)

†

DECD(.B)

dst

†

DINT

−

†

EINT

Enable interrupts

1 → GIE

†

INC(.B)

dst

Increment destination

Double-increment destination

Invert destination

dst +1 → dst

†

INCD(.B)

dst

dst+2 → dst

†

INV(.B)

dst

.not.dst → dst

JC/JHS

JEQ/JZ

JGE

label

src,dst

Jump if C set/Jump if higher or same

Jump if equal/Jump if Z set

Jump if greater or equal

Jump if less

−

JMP

Jump

PC + 2 x offset → PC

Jump if N set

JNC/JLO

JNE/JNZ

MOV(.B)

Jump if C not set/Jump if lower

Jump if not equal/Jump if Z not set

Move source to destination

No operation

src → dst

†

NOP

POP(.B)

†

dst

src

Pop item from stack to destination

Push source onto stack

Return from subroutine

Return from interrupt

Rotate left arithmetically

Rotate left through C

Rotate right arithmetically

Rotate right through C

Subtract not(C) from destination

Set C

@SP → dst, SP+2 → SP

SP − 2 → SP, src → @SP

@SP → PC, SP + 2 → SP

PUSH(.B)

†

RET

RETI

†

RLA(.B)

RLC(.B)

RRA(.B)

RRC(.B)

SBC(.B)

dst

†

dst + 0FFFFh + C → dst

1 → C

†

SETC

−

†

SET

Set N

1 → N

†

SETZ

Set Z

1 → C

SUB(.B)

src,dst

dst

Subtract source from destination

Subtract source and not(C) from dst.

Swap bytes

dst + .not.src + 1 → dst

dst + .not.src + C → dst

SUBC(.B)

SWPB

−

SXT

dst

Extend sign

†

TST(.B)

dst

Test destination

dst + 0FFFFh + 1

XOR(.B)

src,dst

Exclusive OR source and destination

src .xor. dst → dst

† Emulated Instruction

RISC 16−Bit CPU

3-75

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Chapter 4

Basic Clock Module

The basic clock module provides the clocks for MSP430x1xx devices. This

chapter describes the operation of the basic clock module. The basic clock

module is implemented in all MSP430x1xx devices.

Topic

Page

4.1 Basic Clock Module Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−2

4.2 Basic Clock Module Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−4

4.3 Basic Clock Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−14

Basic Clock Module

4-1

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Basic Clock Module Introduction

4.1 Basic Clock Module Introduction

The basic clock module supports low system cost and ultralow-power

consumption. Using three internal clock signals, the user can select the best

balance of performance and low power consumption. The basic clock module

can be configured to operate without any external components, with one

external resistor, with one or two external crystals, or with resonators, under

full software control.

The basic clock module includes two or three clock sources:

- LFXT1CLK: Low-frequency/high-frequency oscillator that can be used

either with low-frequency 32768-Hz watch crystals, or standard crystals

or resonators in the 450-kHz to 8-MHz range.

- XT2CLK: Optional high-frequency oscillator that can be used with

standard crystals, resonators, or external clock sources in the 450-kHz to

8-MHz range.

- DCOCLK: Internal digitally controlled oscillator (DCO) with RC-type

characteristics.

Three clock signals are available from the basic clock module:

- ACLK: Auxiliary clock. The ACLK is the buffered LFXT1CLK clock source

divided by 1, 2, 4, or 8. ACLK is software selectable for individual

peripheral modules.

- MCLK: Master clock. MCLK is software selectable as LFXT1CLK,

XT2CLK (if available), or DCOCLK. MCLK is divided by 1, 2, 4, or 8. MCLK

is used by the CPU and system.

- SMCLK: Sub-main clock. SMCLK is software selectable as LFXT1CLK,

XT2CLK (if available on-chip), or DCOCLK. SMCLK is divided by 1, 2, 4,

or 8. SMCLK is software selectable for individual peripheral modules.

The block diagram of the basic clock module is shown in Figure 4−1.

4-2

Basic Clock Module

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Basic Clock Module Introduction

Figure 4−1. Basic Clock Block Diagram

DIVAx

LFXT1CLK

Divider

/1/2/4/8

OSCOFF XTS

ACLK

Auxillary Clock

0 V

XIN

12pF

LFOff

XT1Off

12pF

0 V

XOUT

SELMx

LFXT1 Oscillator

DIVMx

CPUOFF

Divider

/1/2/4/8

XT2CLK

MCLK

XT2OFF

XT2IN

Main System Clock

XT2OUT

XT2 Oscillator

MODx

VCC

Modulator

DCOR SCG0 RSELx

off

DCOx

SELS

DIVSx

SCG1

DCOCLK

DCO

n+1

Divider

/1/2/4/8

Generator

P2.5/Rosc

SMCLK

Sub System Clock

Note: XT2 Oscillator

The XT2 Oscillator is not present on MSP430x11xx or MSP430x12xx

devices. The LFXT1CLK is used in place of XT2CLK.

Basic Clock Module

4-3

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Basic Clock Module Operation

4.2 Basic Clock Module Operation

After a PUC, MCLK and SMCLK are sourced from DCOCLK at ~800 kHz (see

device-specific datasheet for parameters) and ACLK is sourced from LFXT1

in LF mode.

Status register control bits SCG0, SCG1, OSCOFF, and CPUOFF configure

the MSP430 operating modes and enable or disable portions of the basic clock

module. See Chapter System Resets, Interrupts and Operating Modes. The

DCOCTL, BCSCTL1, and BCSCTL2 registers configure the basic clock

module

The basic clock can be configured or reconfigured by software at any time

during program execution, for example:

BIS.B #RSEL2+RSEL1+RSEL0,&BCSCTL1 ;

BIS.B #DCO2+DCO1+DCO0,&DCOCTL

; Set max DCO frequency

4.2.1 Basic Clock Module Features for Low-Power Applications

Conflicting requirements typically exist in battery-powered MSP430x1xx

applications:

- Low clock frequency for energy conservation and time keeping

- High clock frequency for fast reaction to events and fast burst processing

capability

The basic clock module addresses the above conflicting requirements by

allowing the user to select from the three available clock signals: ACLK, MCLK,

and SMCLK. For optimal low-power performance, the ACLK can be

configured to oscillate with a low-power 32,786-Hz watch crystal, providing a

stable time base for the system and low power stand-by operation. The MCLK

can be configured to operate from the on-chip DCO that can be only activated

when requested by interrupt-driven events. The SMCLK can be configured to

operate from a crystal or the DCO, depending on peripheral requirements. A

flexible clock distribution and divider system is provided to fine tune the

individual clock requirements.

4-4

Basic Clock Module

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Basic Clock Module Operation

4.2.2 LFXT1 Oscillator

The LFXT1 oscillator supports ultralow-current consumption using a

32,768-Hz watch crystal in LF mode (XTS = 0). A watch crystal connects to XIN

and XOUT without any other external components. Internal 12-pF load

capacitors are provided for LFXT1 in LF mode. The capacitors add serially,

providing a match for standard 32,768-Hz crystals requiring a 6-pF load.

Additional capacitors can be added if necessary.

The LFXT1 oscillator also supports high-speed crystals or resonators when in

HF mode (XTS = 1). The high-speed crystal or resonator connects to XIN and

XOUT and requires external capacitors on both terminals. These capacitors

should be sized according to the crystal or resonator specifications.

LFXT1 may be used with an external clock signal on the XIN pin in either LF

or HF mode. When used with an external signal, the external frequency must

meet the datasheet parameters for the chosen mode.

Software can disable LFXT1 by setting OSCOFF, if this signal does not source

SMCLK or MCLK, as shown in Figure 4−2.

Figure 4−2. Off Signals for the LFXT1 Oscillator

XTS

LFoff

OSCOFF

CPUOFF

SELM0

SELM1

XT1off

XT2

XT2 is an Internal Signal

XT2 = 0: MSP430x11xx, MSP430x12xx devices

XT2 = 1: MSP430x13x, MSP430x14x

SCG1

SELS

MSP430x15x, and MSP430x16x devices

Note: LFXT1 Oscillator Characteristics

Low-frequency crystals often require hundreds of milliseconds to start up,

depending on the crystal.

Ultralow-power oscillators such as the LFXT1 in LF mode should be guarded

from noise coupling from other sources. The crystal should be placed as

close as possible to the MSP430 with the crystal housing grounded and the

crystal traces guarded with ground traces.

The LFXT1 oscillator in LF mode requires a 5.1-MΩ resistor from XOUT to

when V

< 2.5 V.

Basic Clock Module

4-5

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Basic Clock Module Operation

4.2.3 XT2 Oscillator

Some devices have a second crystal oscillator, XT2. XT2 sources XT2CLK

and its characteristics are identical to LFXT1 in HF mode. The XT2OFF bit

disables the XT2 oscillator if XT2CLK is not used for MCLK or SMCLK as

shown in Figure 4−3.

XT2 may be used with external clock signals on the XT2IN pin. When used with

an external signal, the external frequency must meet the datasheet

parameters for XT2.

Figure 4−3. Off Signals for Oscillator XT2

XT2OFF

CPUOFF

SELM1

XT2Off (Internal signal)

SELM0

SCG1

SELS

4.2.4 Digitally-Controlled Oscillator (DCO)

The DCO is an integrated ring oscillator with RC-type characteristics. As with

any RC-type oscillator, frequency varies with temperature, voltage, and from

device to device. The DCO frequency can be adjusted by software using the

DCOx, MODx, and RSELx bits. The digital control of the oscillator allows

frequency stabilization despite its RC-type characteristics.

Disabling the DCO

Software can disable DCOCLK by setting SCG0 when it is not used to source

SMCLK or MCLK in active mode, as shown in Figure 4−4.

Figure 4−4. On/Off Control of DCO

CPUOFF

XSELM1

DCOCLK_on

1: on

0: off

SCG1

SELS

SCG0

DCOCLK

POR

DCO_Gen_on

SMCLK

1: on

0: off

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Basic Clock Module Operation

Adjusting the DCO frequency

After a PUC, the internal resistor is selected for the DC generator, RSELx =

4, and DCOx = 3, allowing the DCO to start at a mid-range frequency. MCLK

and SMCLK are sourced from DCOCLK. Because the CPU executes code

from MCLK, which is sourced from the fast-starting DCO, code execution

begins from PUC in less than 6 µs. The typical DCOx and RSELx ranges and

steps are shown in Figure 4−5.

The frequency of DCOCLK is set by the following functions:

- The current injected into the DC generator by either the internal or external

resistor defines the fundamental frequency. The DCOR bit selects the

internal or external resistor.

- The three RSELx bits select one of eight nominal frequency ranges for the

DCO. These ranges are defined for an individual device in the

device-specific data sheet.

- The three DCOx bits divide the DCO range selected by the RSELx bits into

8 frequency steps, separated by approximately 10%.

- The five MODx bits, switch between the frequency selected by the DCOx

bits and the next higher frequency set by DCOx+1. When DCOx = 07h,

the MODx bits have no effect because the DCO is already at the highest

setting for the selected RSELx range.

Figure 4−5. Typical DCOx Range and RSELx Steps

DCO

10000 kHz

RSEL=7

RSEL=6

RSEL=5

RSEL=4

1000 kHz

RSEL=3

RSEL=2

RSEL=1

RSEL=0

100 kHz

DCO=0 DCO=1 DCO=2 DCO=3 DCO=4 DCO=5 DCO=6 DCO=7

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Basic Clock Module Operation

Using an External Resistor (R

) for the DCO

OSC

The DCO temperature coefficient can be reduced by using an external resistor

tied to DV to source the current for the DC generator. Figure 4−6

OSC

shows the typical relationship of f

vs. temperature for both the internal and

DCO

external resistor options. Using an external R

reduces the DCO

OSC

temperature coefficient to approximately 0.1%/C. See the device-specific data

sheet for parameters.

also allows the DCO to operate at higher frequencies. For example, the

OSC

internal resistor nominal value is approximately 300 kΩ, allowing the DCO to

operate up to approximately 5 MHz. When using an external R of

OSC

approximately 100 kΩ the DCO can operate up to approximately 10 MHz. The

user should take care to not exceed the maximum MCLK frequency specified

in the datasheet, even though the DCO is capable of exceeding it.

Figure 4−6. DCO Frequency vs. Temperature

DCO

25%

External

Internal

−25%

Celsius

−50

100

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Basic Clock Module Operation

4.2.5 DCO Modulator

The modulator mixes two DCO frequencies, f

and f

to produce an

DCO

DCO+1

intermediate effective frequency between f

and f

and spread the

DCO

DCO+1

clock energy, reducing electromagnetic interference (EMI) The modulator

mixes f

and f

for 32 DCOCLK clock cycles and is configured with the

DCO

DCO+1

MODx bits. When MODx = 0 the modulator is off.

The modulator mixing formula is:

t =(32− MODx) × t

+ MODx × t

DCO+1

DCO

Because f

is lower than the effective frequency and f

is higher than

DCO

DCO+1

the effective frequency, the error of the effective frequency integrates to zero.

It does not accumulate. The error of the effective frequency is zero every 32

DCOCLK cycles. Figure 4−7 illustrates the modulator operation.

The modulator settings and DCO control are configured with software. The

DCOCLK can be compared to a stable frequency of known value and adjusted

with the DCOx, RSELx, and MODx bits. See http://www.msp430.com for

application notes and example code on configuring the DCO.

Figure 4−7. Modulator Patterns

MODx

Lower DCO Tap Frequency f

DCO

Upper DCO Tap Frequency f

DCO+1

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Basic Clock Module Operation

4.2.6 Basic Clock Module Fail-Safe Operation

The basic clock module incorporates an oscillator-fault detection fail-safe

feature. The oscillator fault detector is an analog circuit that monitors the

LFXT1CLK (in HF mode) and the XT2CLK. An oscillator fault is detected when

either clock signal is not present for approximately 50 µs. When an oscillator

fault is detected, and when MCLK is sourced from either LFXT1 in HF mode

or XT2, MCLK is automatically switched to the DCO for its clock source. This

allows code execution to continue, even though the crystal oscillator has

stopped.

When OFIFG is set and OFIE is set, an NMI interrupt is requested. The NMI

interrupt service routine can test the OFIFG flag to determine if an oscillator

fault occurred. The OFIFG flag must be cleared by software.

Note: No Oscillator Fault Detection for LFXT1 in LF Mode

Oscillator fault detection is only applicable for LFXT1 in HF mode and XT2.

There is no oscillator fault detection for LFXT1 in LF mode.

OFIFG is set by the oscillator fault signal, XT_OscFault. XT_OscFault is set

at POR, when LFXT1 has an oscillator fault in HF mode, or when XT2 has an

oscillator fault. When XT2 or LFXT1 in HF mode is stopped with software the

XT_OscFault signal becomes active immediately, remains active until the

oscillator is re-started, and becomes inactive approximately 50 µs after the

oscillator re-starts as shown in Figure 4−8.

Figure 4−9. Oscillator-Fault Signal

software enables OSC

software disables OSC

XT1OFF/

XT2OFF

OSC faults

LFXT1CLK/

XT2CLK

50 us

XT_OscFault

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Basic Clock Module Operation

Oscillator Fault Detection

Signal XT_OscFault triggers the OFIFG flag as shown in Figure 4−10. The

LFXT1_OscFault signal is low when LFXT1 is in LF mode.

On devices without XT2, the OFIFG flag cannot be cleared when LFXT1 is in

LF mode. MCLK may be sourced by LFXT1CLK in LF mode by setting the

SELMx bits, even though OFIFG remains set.

On devices with XT2, the OFIFG flag can be cleared by software when LFXT1

is in LF mode and it remains cleared. MCLK may be sourced by LFXT1CLK

in LF mode regardless of the state of the OFIFG flag.

Figure 4−10. Oscillator-Fault-Interrupt

Oscillator Fault Interrupt Request

XT_OscFault

XT1off

LFXT1_OscFault

POR

OFIFG

XT2off

XT2_OscFault

OF_IRQ_NMI

IFG1.1

IE1.1

XT2

OFIE

Clear

PUC IRQA

Oscillator Fault Fail-Safe Logic

XTS

XSELM1

SELM1

SELM0

Fault_from

XT2

Fault_from

XT1

XDCOR

DCOR

XT2 Is an internal signal. XT2 = 0 on devices without XT2 (MSP430x11xx and MSP430x12xx).

XT2 = 1 on devices with XT2 (MSP430F13x, MSP430F14x, MSP430F15x, and(MSP430F16x)

IRQA: Interrupt request accepted

LFXT1_OscFault: Only applicable to LFXT1 oscillator in HF mode.

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Basic Clock Module Operation

Sourcing MCLK from a Crystal

After a PUC, the basic clock module uses DCOCLK for MCLK. If required,

MCLK may be sourced from LFXT1 or XT2.

The sequence to switch the MCLK source from the DCO clock to the crystal

clock (LFXT1CLK or XT2CLK) is:

1) Switch on the crystal oscillator

2) Clear the OFIFG flag

3) Wait at least 50 µs

4) Test OFIFG, and repeat steps 1-4 until OFIFG remains cleared.

; Select LFXT1 (HF mode) for MCLK

BIC #OSCOFF,SR

BIS.B #XTS,BCSCTL1

L1 BIC.B #OFIFG,&IFG1

MOV #0FFh,R15

L2 DEC R15

; Turn on osc.

; HF mode

; Clear OFIFG

; Delay

;

JNZ L2

;

BIT.B #OFIFG,&IFG1

JNZ L1

; Re−test OFIFG

; Repeat test if needed

BIS.B #SELM1+SELM0,&BCSCTL2 ; Select LFXT1CLK

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Basic Clock Module Operation

4.2.7 Synchronization of Clock Signals

When switching MCLK or SMCLK from one clock source to the another, the

switch is synchronized to avoid critical race conditions as shown in

Figure 4−11:

1) The current clock cycle continues until the next rising edge.

2) The clock remains high until the next rising edge of the new clock.

3) The new clock source is selected and continues with a full high period.

Figure 4−11. Switch MCLK from DCOCLK to LFXT1CLK

Select

LFXT1CLK

DCOCLK

LFXT1CLK

MCLK

Wait for

LFXT1CLK

DCOCLK

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Basic Clock Module Registers

4.3 Basic Clock Module Registers

The basic clock module registers are listed in Table 4−1:

Table 4−1.Basic Clock Module Registers

Short Form

Initial State

DCO control register

DCOCTL

BCSCTL1

BCSCTL2

IE1

Read/write

056h

057h

058h

000h

002h

060h with PUC

084h with PUC

Reset with POR

Reset with PUC

Basic clock system control 1

Basic clock system control 2

SFR interrupt enable register 1

SFR interrupt flag register 1

IFG1

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Basic Clock Module Registers

DCOCTL, DCO Control Register

DCOx

rw−1

MODx

rw−0

rw−1

rw−0

DCOx

MODx

Bits

7-5

DCO frequency select. These bits select which of the eight discrete DCO

frequencies of the RSELx setting is selected.

Bits

4-0

Modulator selection. These bits define how often the f

frequency is

DCO+1

used within a period of 32 DCOCLK cycles. During the remaining clock

cycles (32−MOD) the f frequency is used. Not useable when DCOx=7.

DCO

BCSCTL1, Basic Clock System Control Register 1

XT2OFF

rw−(1)

XTS

DIVAx

XT5V

rw−0

RSELx

rw−0

rw−(0)

rw−1

rw−0

XT2OFF

Bit 7

XT2 off. This bit turns off the XT2 oscillator

XT2 is on

XT2 is off if it is not used for MCLK or SMCLK.

XTS

Bit 6

LFXT1 mode select.

Low frequency mode

High frequency mode

DIVAx

Bits

5-4

Divider for ACLK

00 /1

01 /2

10 /4

11 /8

XT5V

Bit 3

Unused. XT5V should always be reset.

RSELx

Bits

2-0

Resistor Select. The internal resistor is selected in eight different steps.

The value of the resistor defines the nominal frequency. The lowest

nominal frequency is selected by setting RSELx=0.

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Basic Clock Module Registers

BCSCTL2, Basic Clock System Control Register 2

SELMx

DIVMx

SELS

rw−0

DIVSx

DCOR

rw−0

rw−(0)

rw−0

SELMx

Bits

7-6

Select MCLK. These bits select the MCLK source.

00 DCOCLK

01 DCOCLK

10 XT2CLK when XT2 oscillator present on-chip. LFXT1CLK when XT2

oscillator not present on-chip.

11 LFXT1CLK

DIVMx

BitS

5-4

Divider for MCLK

00 /1

01 /2

10 /4

11 /8

SELS

Bit 3

Select SMCLK. This bit selects the SMCLK source.

DCOCLK

XT2CLK when XT2 oscillator present on-chip. LFXT1CLK when XT2

oscillator not present on-chip.

DIVSx

BitS

2-1

Divider for SMCLK

00 /1

01 /2

10 /4

11 /8

DCOR

Bit 0

DCO resistor select

Internal resistor

External resistor

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Basic Clock Module Registers

IE1, Interrupt Enable Register 1

OFIE

rw−0

Bits

7-2

These bits may be used by other modules. See device-specific datasheet.

OFIE

Bit 1

Oscillator fault interrupt enable. This bit enables the OFIFG interrupt.

Because other bits in IE1 may be used for other modules, it is recommended

to set or clear this bit using BIS.Bor BIC.Binstructions, rather than MOV.B

or CLR.Binstructions.

Interrupt not enabled

Interrupt enabled

Bits 0

This bit may be used by other modules. See device-specific datasheet.

IFG1, Interrupt Flag Register 1

OFIFG

rw−1

Bits

7-2

These bits may be used by other modules. See device-specific datasheet.

OFIFG

Bit 1

Oscillator fault interrupt flag. Because other bits in IFG1 may be used for other

modules, it is recommended to set or clear this bit using BIS.Bor BIC.B

instructions, rather than MOV.Bor CLR.Binstructions.

No interrupt pending

Interrupt pending

Bits 0

This bit may be used by other modules. See device-specific datasheet.

Basic Clock Module

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Chapter 5

Flash Memory Controller

This chapter describes the operation of the MSP430 flash memory controller.

Topic

Page

5.1 Flash Memory Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.2 Flash Memory Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.3 Flash Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.4 Flash Memory Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17

Flash Memory Controller

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Flash Memory Introduction

5.1 Flash Memory Introduction

The MSP430 flash memory is bit-, byte-, and word-addressable and

programmable. The flash memory module has an integrated controller that

controls programming and erase operations. The controller has three

registers, a timing generator, and a voltage generator to supply program and

erase voltages.

MSP430 flash memory features include:

- Internal programming voltage generation

- Bit, byte or word programmable

- Ultralow-power operation

- Segment erase and mass erase

The block diagram of the flash memory and controller is shown in Figure 5−1.

Note: Minimum V

During Flash Write or Erase

The minimum V

voltage during a flash write or erase operation is 2.7 V.

If V

falls below 2.7 V during a write or erase, the result of the write or erase

will be unpredictable.

Figure 5−1. Flash Memory Module Block Diagram

MAB

MDB

FCTL1

FCTL2

FCTL3

Address Latch

Data Latch

Enable

Address

Latch

Flash

Memory

Array

Timing

Generator

Enable

Data Latch

Programming

Voltage

Generator

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Flash Memory Segmentation

5.2 Flash Memory Segmentation

MSP430 flash memory is partitioned into segments. Single bits, bytes, or

words can be written to flash memory, but the segment is the smallest size of

flash memory that can be erased.

The flash memory is partitioned into main and information memory sections.

There is no difference in the operation of the main and information memory

sections. Code or data can be located in either section. The differences

between the two sections are the segment size and the physical addresses.

The information memory has two 128-byte segments (MSP430F1101 devices

have only one). The main memory has two or more 512-byte segments. See

the device-specific datasheet for the complete memory map of a device.

The segments are further dividing into blocks. A block is 64 bytes, starting at

0xx00h, 0xx40h, 0xx80h, or 0xxC0h, and ending at 0xx3Fh, 0xx7Fh, 0xxBFh,

or 0xxFFh.

Figure 5−2 shows the flash segmentation using an example of 4-KB flash that

has eight main segments and both information segments.

Figure 5−2. Flash Memory Segments, 4-KB Example

4 KB + 256 byte

xxFFh

FFFFh

FE00h

FDFFh

FC00h

Block

Segment0

xxC0h

xxBFh

4-kbyte

Flash

Main Memory

Segment1

Segment2

Segment3

Segment4

Segment5

Segment6

Segment7

xx80h

xx7Fh

F000h

10FFh

1000h

xx40h

xx3Fh

256-byte

Flash

Information Memory

xx00h

F000h

10FFh

SegmentA

SegmentB

1000h

Flash Memory Controller

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Flash Memory Operation

5.3 Flash Memory Operation

The default mode of the flash memory is read mode. In read mode, the flash

memory is not being erased or written, the flash timing generator and voltage

generator are off, and the memory operates identically to ROM.

MSP430 flash memory is in-system programmable (ISP) without the need for

additional external voltage. The CPU can program its own flash memory. The

flash memory write/erase modes are selected with the BLKWRT, WRT,

MERAS, and ERASE bits and are:

- Byte/word write

- Block write

- Segment Erase

- Mass Erase (all main memory segments)

- All Erase (all segments)

Reading or writing to flash memory while it is being programmed or erased is

prohibited. If CPU execution is required during the write or erase, the code to

be executed must be in RAM. Any flash update can be initiated from within

flash memory or RAM.

5.3.1 Flash Memory Timing Generator

Write and erase operations are controlled by the flash timing generator shown

in Figure 5−3. The flash timing generator operating frequency, f , must be

(FTG)

in the range from ~ 257 kHz to ~ 476 kHz (see device-specific datasheet).

Figure 5−3. Flash Memory Timing Generator Block Diagram

FSSELx

...........

PUC

EMEX

FN5

FN0

ACLK

MCLK

FTG

Reset

Flash Timing Generator

Divider, 1−64

SMCLK

BUSY

WAIT

The flash timing generator can be sourced from ACLK, SMCLK, or MCLK. The

selected clock source should be divided using the FNx bits to meet the

frequency requirements for f

. If the f

frequency deviates from the

FTG

specification during the write or erase operation, the result of the write or erase

may be unpredictable, or the flash memory may be stressed above the limits

of reliable operation.

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Flash Memory Operation

5.3.2 Erasing Flash Memory

The erased level of a flash memory bit is 1. Each bit can be programmed from

1 to 0 individually but to reprogram from 0 to 1 requires an erase cycle. The

smallest amount of flash that can be erased is a segment. There are three

erase modes selected with the ERASE and MERAS bits listed in Table 5−1.

Table 5−1.Erase Modes

Erase Mode

MERAS ERASE

Segment erase

Mass erase (all main memory segments)

Erase all flash memory (main and information segments)

Any erase is initiated by a dummy write into the address range to be erased.

The dummy write starts the flash timing generator and the erase operation.

Figure 5−4 shows the erase cycle timing. The BUSY bit is set immediately after

the dummy write and remains set throughout the erase cycle. BUSY, MERAS,

and ERASE are automatically cleared when the cycle completes. The erase

cycle timing is not dependent on the amount of flash memory present on a

device. Erase cycle times are equivalent for all MSP430F1xx devices.

Figure 5−4. Erase Cycle Timing

Erase Operation Active

Remove

Programming Voltage

Generate

Programming Voltage

Erase Time, V

Current Consumption is Increased

BUSY

= t

= 5297/f

, t

= 4819/f

All Erase

Mass Erase

FTG Seg Erase FTG

A dummy write to an address not in the range to be erased does not start the

erase cycle, does not affect the flash memory, and is not flagged in any way.

This errant dummy write is ignored.

Interrupts should be disabled before a flash erase cycle. After the erase cycle

has completed, interrupts may be re-enabled. Any interrupt that occurred

during the erase cycle will have its associated flag set, and will generate an

interrupt request when re-enabled.

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Flash Memory Operation

Initiating an Erase from Within Flash Memory

Any erase cycle can be initiated from within flash memory or from RAM. When

a flash segment erase operation is initiated from within flash memory, all timing

is controlled by the flash controller, and the CPU is held while the erase cycle

completes. After the erase cycle completes, the CPU resumes code execution

with the instruction following the dummy write.

When initiating an erase cycle from within flash memory, it is possible to erase

the code needed for execution after the erase. If this occurs, CPU execution

will be unpredictable after the erase cycle.

The flow to initiate an erase from flash is shown in Figure 5−5.

Figure 5−5. Erase Cycle from Within Flash Memory

Disable all interrupts and watchdog

Setup flash controller and erase

mode

Dummy write

Set LOCK=1, re-enable Interrupts

and watchdog

; Segment Erase from flash. 514 kHz < SMCLK < 952 kHz

; Assumes ACCVIE = NMIIE = OFIE = 0.

MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT

DINT

; Disable interrupts

MOV #FWKEY+FSSEL1+FN0,&FCTL2 ; SMCLK/2

MOV #FWKEY,&FCTL3

MOV #FWKEY+ERASE,&FCTL1

CLR &0FC10h

MOV #FWKEY+LOCK,&FCTL3

...

; Clear LOCK

; Enable segment erase

; Dummy write, erase S1

; Done, set LOCK

; Re-enable WDT?

EINT

; Enable interrupts

5-6

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Flash Memory Operation

Initiating an Erase from RAM

Any erase cycle may be initiated from RAM. In this case, the CPU is not held

and can continue to execute code from RAM. The BUSY bit must be polled to

determine the end of the erase cycle before the CPU can access any flash

address again. If a flash access occurs while BUSY=1, it is an access violation,

ACCVIFG will be set, and the erase results will be unpredictable.

The flow to initiate an erase from flash from RAM is shown in Figure 5−6.

Figure 5−6. Erase Cycle from Within RAM

Disable all interrupts and watchdog

yes

BUSY = 1

Setup flash controller and

erase mode

Dummy write

yes

BUSY = 1

Set LOCK = 1, re-enable

interrupts and watchdog

; Segment Erase from RAM. 514 kHz < SMCLK < 952 kHz

; Assumes ACCVIE = NMIIE = OFIE = 0.

MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT

DINT

; Disable interrupts

; Test BUSY

L1 BIT #BUSY,&FCTL3

JNZ L1

; Loop while busy

MOV #FWKEY+FSSEL1+FN0,&FCTL2 ; SMCLK/2

MOV #FWKEY,&FCTL3

MOV #FWKEY+ERASE,&FCTL1

CLR &0FC10h

; Clear LOCK

; Enable erase

; Dummy write, erase S1

; Test BUSY

L2 BIT #BUSY,&FCTL3

JNZ L2

; Loop while busy

; Done, set LOCK

; Re-enable WDT?

; Enable interrupts

MOV #FWKEY+LOCK,&FCTL3

...

EINT

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Flash Memory Operation

5.3.3 Writing Flash Memory

The write modes, selected by the WRT and BLKWRT bits, are listed in

Table 5−1.

Table 5−2.Write Modes

Write Mode

Byte/word write

Block write

BLKWRT WRT

Both write modes use a sequence of individual write instructions, but using the

block write mode is approximately twice as fast as byte/word mode, because

the voltage generator remains on for the complete block write. Any instruction

that modifies a destination can be used to modify a flash location in either

byte/word write mode or block write mode.

The BUSY bit is set while a write operation is active and cleared when the

operation completes. If the write operation is initiated from RAM, the CPU must

not access flash while BUSY=1. Otherwise, an access violation occurs,

ACCVIFG is set, and the flash write is unpredictable.

Byte/Word Write

A byte/word write operation can be initiated from within flash memory or from

RAM. When initiating from within flash memory, all timing is controlled by the

flash controller, and the CPU is held while the write completes. After the write

completes, the CPU resumes code execution with the instruction following the

write. The byte/word write timing is shown in Figure 5−7.

Figure 5−7. Byte/Word Write Timing

Programming Operation Active

Remove

Programming Voltage

Generate

Programming Voltage

Programming Time, V

Current Consumption is Increased

BUSY

= 35/f

FTG

Word

When a byte/word write is executed from RAM, the CPU continues to execute

code from RAM. The BUSY bit must be zero before the CPU accesses flash

again, otherwise an access violation occurs, ACCVIFG is set, and the write

result is unpredictable.

5-8

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Flash Memory Operation

In byte/word mode, the internally-generated programming voltage is applied

to the complete 64-byte block, each time a byte or word is written, for 32 of the

35 f

cycles. With each byte or word write, the amount of time the block is

FTG

subjected to the programming voltage accumulates. The cumulative

programming time, t must not be exceeded for any block. If the cumulative

CPT,

programming time is met, the block must be erased before performing any

further writes to any address within the block. See the device-specific

datasheet for specifications.

Initiating a Byte/Word Write from Within Flash Memory

The flow to initiate a byte/word write from flash is shown in Figure 5−8.

Figure 5−8. Initiating a Byte/Word Write from Flash

Disable all interrupts and watchdog

Setup flash controller

and set WRT=1

Write byte or word

Set WRT=0, LOCK=1,

re-enable interrupts and watchdog

; Byte/word write from flash. 514 kHz < SMCLK < 952 kHz

; Assumes 0FF1Eh is already erased

; Assumes ACCVIE = NMIIE = OFIE = 0.

MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT

DINT

; Disable interrupts

MOV #FWKEY+FSSEL1+FN0,&FCTL2 ; SMCLK/2

MOV #FWKEY,&FCTL3

MOV #FWKEY+WRT,&FCTL1

MOV #0123h,&0FF1Eh

MOV #FWKEY,&FCTL1

MOV #FWKEY+LOCK,&FCTL3

...

; Clear LOCK

; Enable write

; 0123h

−> 0FF1Eh

; Done. Clear WRT

; Set LOCK

; Re-enable WDT?

; Enable interrupts

EINT

Flash Memory Controller

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Flash Memory Operation

Initiating a Byte/Word Write from RAM

The flow to initiate a byte/word write from RAM is shown in Figure 5−9.

Figure 5−9. Initiating a Byte/Word Write from RAM

Disable all interrupts and watchdog

yes

BUSY = 1

Setup flash controller

and set WRT=1

Write byte or word

yes

BUSY = 1

Set WRT=0, LOCK = 1

re-enable interrupts and watchdog

; Byte/word write from RAM. 514 kHz < SMCLK < 952 kHz

; Assumes 0FF1Eh is already erased

; Assumes ACCVIE = NMIIE = OFIE = 0.

MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT

DINT

; Disable interrupts

L1 BIT #BUSY,&FCTL3

JNZ L1

; Test BUSY

; Loop while busy

MOV #FWKEY+FSSEL1+FN0,&FCTL2 ; SMCLK/2

MOV #FWKEY,&FCTL3

MOV #FWKEY+WRT,&FCTL1

MOV #0123h,&0FF1Eh

L2 BIT #BUSY,&FCTL3

JNZ L2

; Clear LOCK

; Enable write

; 0123h −> 0FF1Eh

; Test BUSY

; Loop while busy

; Clear WRT

MOV #FWKEY,&FCTL1

MOV #FWKEY+LOCK,&FCTL3

...

; Set LOCK

; Re-enable WDT?

; Enable interrupts

EINT

5-10

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Flash Memory Operation

Block Write

The block write can be used to accelerate the flash write process when many

sequential bytes or words need to be programmed. The flash programming

voltage remains on for the duration of writing the 64-byte block. The

cumulative programming time t

a block write.

must not be exceeded for any block during

CPT

A block write cannot be initiated from within flash memory. The block write

must be initiated from RAM only. The BUSY bit remains set throughout the

duration of the block write. The WAIT bit must be checked between writing

each byte or word in the block. When WAIT is set the next byte or word of the

block can be written. When writing successive blocks, the BLKWRT bit must

be cleared after the current block is complete. BLKWRT can be set initiating

the next block write after the required flash recovery time given by t

. BUSY

End

is cleared following each block write completion indicating the next block can

be written. Figure 5−10 shows the block write timing.

Figure 5−10. Block-Write Cycle Timing

BLKWRT bit

Write to Flash e.g., MOV #123h, &Flash

Remove

Programming Voltage

Programming Operation Active

Generate

Programming Voltage

Cumulative Programming Time t

∼=< 4ms, V Current Consumption is Increased

CPT

BUSY

= 30/f

= 21/f

= 6/f

Block, 0

FTG

Block 1-63

FTG

Block, 1-63

FTG

End FTG

WAIT

Flash Memory Controller

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Flash Memory Operation

Block Write Flow and Example

A block write flow is shown in Figure 5−8 and the following example.

Figure 5−11. Block Write Flow

Disable all interrupts and watchdog

yes

BUSY = 1

Setup flash controller

Set BLKWRT=WRT=1

Write byte or word

WAIT=0?

yes

Block Border?

Set BLKWRT=0

yes

BUSY = 1

Another

Block?

Set WRT=0, LOCK=1

re-enable interrupts and WDT

5-12

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Flash Memory Operation

; Write one block starting at 0F000h.

; Must be executed from RAM, Assumes Flash is already erased.

; 514 kHz < SMCLK < 952 kHz

; Assumes ACCVIE = NMIIE = OFIE = 0.

MOV #32,R5

MOV #0F000h,R6

; Use as write counter

; Write pointer

; Disable WDT

; Disable interrupts

; Test BUSY

MOV

DINT

#WDTPW+WDTHOLD,&WDTCTL

L1 BIT

JNZ

#BUSY,&FCTL3

; Loop while busy

MOV #FWKEY+FSSEL1+FN0,&FCTL2 ; SMCLK/2

MOV

#FWKEY,&FCTL3

; Clear LOCK

#FWKEY+BLKWRT+WRT,&FCTL1 ; Enable block write

L2 MOV

L3 BIT

Write_Value,0(R6)

#WAIT,&FCTL3

; Write location

; Test WAIT

; Loop while WAIT=0

; Point to next word

; Decrement write counter

; End of block?

INCD R6

DEC

JNZ

MOV

#FWKEY,&FCTL1

#BUSY,&FCTL3

; Clear WRT,BLKWRT

; Test BUSY

L4 BIT

JNZ

; Loop while busy

; Set LOCK

MOV

#FWKEY+LOCK,&FCTL3

...

EINT

; Re-enable WDT if needed

; Enable interrupts

Flash Memory Controller

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Flash Memory Operation

5.3.4 Flash Memory Access During Write or Erase

When any write or any erase operation is initiated from RAM and while

BUSY=1, the CPU may not read or write to or from any flash location.

Otherwise, an access violation occurs, ACCVIFG is set, and the result is

unpredictable. Also if a write to flash is attempted with WRT=0, the ACCVIFG

interrupt flag is set, and the flash memory is unaffected.

When a byte/word write or any erase operation is initiated from within flash

memory, the flash controller returns op-code 03FFFh to the CPU at the next

instruction fetch. Op-code 03FFFh is the JMP PCinstruction. This causes the

CPU to loop until the flash operation is finished. When the operation is finished

and BUSY=0, the flash controller allows the CPU to fetch the proper op-code

and program execution resumes.

The flash access conditions while BUSY=1 are listed in Table 5−3.

Table 5−3.Flash Access While BUSY = 1

Flash

WAIT

Result

Operation

Access

Read

Write

ACCVIFG = 0. 03FFFh is the value read

ACCVIFG = 1. Write is ignored

Any erase, or

Byte/word write

Instruction

fetch

ACCVIFG = 0. CPU fetches 03FFFh. This

is the JMP PCinstruction.

Any

Read

Write

ACCVIFG = 1, LOCK = 1

ACCVIFG = 0, 03FFFh is the value read

ACCVIFG = 0, Write is ignored

ACCVIFG = 1, LOCK = 1

Block write

Instruction

fetch

All interrupt sources should be disabled before initiating any flash operation.

If an enabled interrupt were to occur during a flash operation, the CPU would

fetch 03FFFh as the address of the interrupt service routine. The CPU would

then execute the JMP PCinstruction while BUSY=1. When the flash operation

finished, the CPU would begin executing code at address 03FFFh, not the

correct address for interrupt service routine.

5-14

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Flash Memory Operation

5.3.5 Stopping a Write or Erase Cycle

Any write or erase operation can be stopped before its normal completion by

setting the emergency exit bit EMEX. Setting the EMEX bit stops the active

operation immediately and stops the flash controller. All flash operations

cease, the flash returns to read mode, and all bits in the FCTL1 register are

reset. The result of the intended operation is unpredictable.

5.3.6 Configuring and Accessing the Flash Memory Controller

The FCTLx registers are 16-bit, password-protected, read/write registers. Any

read or write access must use word instructions and write accesses must

include the write password 0A5h in the upper byte. Any write to any FCTLx

violation, sets the KEYV flag and triggers a PUC system reset. Any read of any

FCTLx registers reads 096h in the upper byte.

Any write to FCTL1 during an erase or byte/word write operation is an access

violation and sets ACCVIFG. Writing to FCTL1 is allowed in block write mode

when WAIT=1, but writing to FCTL1 in block write mode when WAIT=0 is an

access violation and sets ACCVIFG.

Any write to FCTL2 when the BUSY=1 is an access violation.

Any FCTLx register may be read when BUSY=1. A read will not cause an

access violation.

5.3.7 Flash Memory Controller Interrupts

The flash controller has two interrupt sources, KEYV, and ACCVIFG.

ACCVIFG is set when an access violation occurs. When the ACCVIE bit is

re-enabled after a flash write or erase, a set ACCVIFG flag will generate an

interrupt request. ACCVIFG sources the NMI interrupt vector, so it is not

necessary for GIE to be set for ACCVIFG to request an interrupt. ACCVIFG

may also be checked by software to determine if an access violation occurred.

ACCVIFG must be reset by software.

The key violation flag KEYV is set when any of the flash control registers are

written with an incorrect password. When this occurs, a PUC is generated

immediately resetting the device.

5.3.8 Programming Flash Memory Devices

There are three options for programming an MSP430 flash device. All options

support in-system programming:

- Program via JTAG

- Program via the Bootstrap Loader

- Program via a custom solution

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Flash Memory Operation

Programming Flash Memory via JTAG

MSP430 devices can be programmed via the JTAG port. The JTAG interface

requires four signals (5 signals on 20- and 28-pin devices), ground and

optionally V and RST/NMI.

The JTAG port is protected with a fuse. Blowing the fuse completely disables

the JTAG port and is not reversible. Further access to the device via JTAG is

not possible For more details see the Application report Programming a

Flash-Based MSP430 Using the JTAG Interface at www.ti.com/sc/msp430.

Programming Flash Memory via the Bootstrap loader (BSL)

Every MSP430 flash device contains a bootstrap loader. The BSL enables

users to read or program the flash memory or RAM using a UART serial

interface. Access to the MSP430 flash memory via the BSL is protected by a

256-bit, user-defined password. For more details see the Application report

Features of the MSP430 Bootstrap Loader at www.ti.com/sc/msp430.

Programming Flash Memory via a Custom Solution

The ability of the MSP430 CPU to write to its own flash memory allows for

in-system and external custom programming solutions as shown in

Figure 5−12. The user can choose to provide data to the MSP430 through any

means available (UART, SPI, etc.). User-developed software can receive the

data and program the flash memory. Since this type of solution is developed

by the user, it can be completely customized to fit the application needs for

programming, erasing, or updating the flash memory.

Figure 5−12. User-Developed Programming Solution

Flash Memory

Commands, data, etc.

UART,

Px.x,

SPI,

etc.

CPU executes

user software

Host

MSP430

Read/write flash memory

5-16

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Flash Memory Registers

5.4 Flash Memory Registers

The flash memory registers are listed in Table 5−4.

Table 5−4.Flash Memory Registers

Short Form

Initial State

Flash memory control register 1

Flash memory control register 2

Flash memory control register 3

Interrupt Enable 1

FCTL1

FCTL2

FCTL3

IE1

Read/write

0128h

012Ah

012Ch

000h

09600h with PUC

09642h with PUC

09618h with PUC

Reset with PUC

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Flash Memory Registers

FCTL1, Flash Memory Control Register

FRKEY, Read as 096h

FWKEY, Must be written as 0A5h

Reserved

BLKWRT

rw−0

WRT

rw−0

MERAS

rw−0

ERASE

rw−0

FRKEY/

FWKEY

Bits

15-8

FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC

will be generated.

BLKWRT

Bit 7

Block write mode. WRT must also be set for block write mode. BLKWRT is

automatically reset when EMEX is set.

Block-write mode is off

Block-write mode is on

WRT

Bit 6

Write. This bit is used to select any write mode. WRT is automatically reset

when EMEX is set.

Write mode is off

Write mode is on

Reserved

Bits

5-3

Reserved. Always read as 0.

MERAS

ERASE

Bit 2

Bit 1

Mass erase and erase. These bits are used together to select the erase mode.

MERAS and ERASE are automatically reset when EMEX is set.

MERAS ERASE

Erase Cycle

No erase

Erase individual segment only

Erase all main memory segments

Erase all main and information memory segments

Reserved

Bit 0

Reserved. Always read as 0.

5-18

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Flash Memory Registers

FCTL2, Flash Memory Control Register

FWKEYx, Read as 096h

Must be written as 0A5h

FSSELx

FNx

rw−0

rw−1

rw-0

rw−0

rw-1

rw−0

FWKEYx

FSSELx

Bits

15-8

FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC

will be generated.

Bits

7−6

Flash controller clock source select

00 ACLK

01 MCLK

10 SMCLK

11 SMCLK

FNx

Bits

5-0

Flash controller clock divider. These six bits select the divider for the flash

controller clock. The divisor value is FNx + 1. For example, when FNx=00h,

the divisor is 1. When FNx=03Fh the divisor is 64.

Flash Memory Controller

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Flash Memory Registers

FCTL3, Flash Memory Control Register FCTL3

FWKEYx, Read as 096h

Must be written as 0A5h

Reserved

EMEX

rw-0

LOCK

rw-1

WAIT

r-1

ACCVIFG

rw−0

KEYV

rw-(0)

BUSY

r(w)−0

FWKEYx

Bits

15-8

FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC

will be generated.

Reserved

EMEX

Bits

7-6

Reserved. Always read as 0.

Bit 5

Emergency exit

No emergency exit

Emergency exit

LOCK

Bit 4

Lock. This bit unlocks the flash memory for writing or erasing. The LOCK bit

can be set anytime during a byte/word write or erase operation and the

operation will complete normally. In the block write mode if the LOCK bit is set

while BLKWRT=WAIT=1, then BLKWRT and WAIT are reset and the mode

ends normally.

Unlocked

Locked

WAIT

Bit 3

Bit 2

Bit 1

Wait. Indicates the flash memory is being written to.

The flash memory is not ready for the next byte/word write

The flash memory is ready for the next byte/word write

ACCVIFG

KEYV

Access violation interrupt flag

No interrupt pending

Interrupt pending

Flash security key violation. This bit indicates an incorrect FCTLx password

was written to any flash control register and generates a PUC when set. KEYV

must be reset with software.

FCTLx password was written correctly

FCTLx password was written incorrectly

BUSY

Bit 0

Busy. This bit indicates the status of the flash timing generator.

Not Busy

Busy

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Flash Memory Registers

IE1, Interrupt Enable Register 1

ACCVIE

rw−0

Bits

7-6,

4-0

These bits may be used by other modules. See device-specific datasheet.

ACCVIE

Bit 5

Flash memory access violation interrupt enable. This bit enables the

ACCVIFG interrupt. Because other bits in IE1 may be used for other modules,

it is recommended to set or clear this bit using BIS.Bor BIC.Binstructions,

rather than MOV.Bor CLR.Binstructions.

Interrupt not enabled

Interrupt enabled

Flash Memory Controller

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5-22

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Chapter 6

Supply Voltage Supervisor

This chapter describes the operation of the SVS. The SVS is implemented in

MSP430x15x and MSP430x16x devices.

Topic

Page

6.1 SVS Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−2

6.2 SVS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−4

6.3 SVS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−7

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SVS Introduction

6.1 SVS Introduction

The supply voltage supervisor (SVS) is used to monitor the AV

supply

voltage or an external voltage. The SVS can be configured to set a flag or

generate a POR reset when the supply voltage or external voltage drops below

a user-selected threshold.

The SVS features include:

- AV

monitoring

- Selectable generation of POR

- Output of SVS comparator accessible by software

- Low-voltage condition latched and accessible by software

- 14 selectable threshold levels

- External channel to monitor external voltage

The SVS block diagram is shown in Figure 6−1.

6-2

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SVS Introduction

Figure 6−1. SVS Block Diagram

VCC

Brownout

Reset

SVSIN

~ 50us

1111

1101

−

SVS_POR

SVSOUT

1100

0011

~ 50us

Reset

0010

0001

1.25V

Set SVSFG

SVSFG

Reset

VLD

PORON

SVSON

SVSOP

SVSCTL Bits

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SVS Operation

6.2 SVS Operation

The SVS detects if the AV

voltage drops below a selectable level. It can be

configured to provide a POR or set a flag, when a low-voltage condition occurs.

The SVS is disabled after a brownout reset to conserve current consumption.

6.2.1 Configuring the SVS

The VLDx bits are used to enable/disable the SVS and select one of 14

threshold levels (V ) for comparison with AV The SVS is off when

(SVS_IT−)

CC.

VLDx = 0 and on when VLDx > 0. The SVSON bit does not turn on the SVS.

Instead, it reflects the on/off state of the SVS and can be used to determine

when the SVS is on.

When VLDx = 1111, the external SVSIN channel is selected. The voltage on

SVSIN is compared to an internal level of approximately 1.2 V.

6.2.2 SVS Comparator Operation

A low-voltage condition exists when AV

drops below the selected threshold

or when the external voltage drops below its 1.2-V threshold. Any low-voltage

condition sets the SVSFG bit.

The PORON bit enables or disables the device-reset function of the SVS. If

PORON = 1, a POR is generated when SVSFG is set. If PORON = 0, a

low-voltage condition sets SVSFG, but does not generate a POR.

The SVSFG bit is latched. This allows user software to determine if a

low-voltage condition occurred previously. The SVSFG bit must be reset by

user software. If the low-voltage condition is still present when SVSFG is reset,

it will be immediately set again by the SVS.

6-4

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SVS Operation

6.2.3 Changing the VLDx Bits

When the VLDx bits are changed, two settling delays are implemented to

allows the SVS circuitry to settle. During each delay, the SVS will not set

SVSFG. The delays, t

and t

are shown in Figure 6−2. The

d(SVSon)

settle,

delay takes affect when VLDx is changed from zero to any non-zero

d(SVSon)

value and is a approximately 50 µs. The t

delay takes affect when the

settle

VLDx bits change from any non-zero value to any other non-zero value and

is a maximum of ~12 µs. See the device-specific datasheet for the delay

parameters.

During the delays, the SVS will not flag a low-voltage condition or reset the

device, and the SVSON bit is cleared. Software can test the SVSON bit to

determine when the delay has elapsed and the SVS is monitoring the voltage

properly.

Figure 6−2. SVSON state When Changing VLDx

VLDx

VLD vs Time

settle

d(SVSon)

settle

SVSON

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SVS Operation

6.2.4 SVS Operating Range

Each SVS level has hysteresis to reduce sensitivity to small supply voltage

changes when AV is close to the threshold. The SVS operation and

SVS/Brownout interoperation are shown in Figure 6−3.

Figure 6−3. Operating Levels for SVS and Brownout/Reset Circuit

Software Sets VLD>0

hys(SVS_IT−)

(SVS_IT−)

(SVSstart)

hys(B_IT−)

(B_IT−)

CC(start)

Brown-

Out

Region

Brownout

Region

Brownout

SVSOUT

d(BOR)

SVS Circuit Active

d(SVSon)

d(SVSR)

Set POR

undefined

6-6

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SVS Registers

6.3 SVS Registers

The SVS registers are listed in Table 6−1.

Table 6−1.SVS Registers

Short Form

Read/write 055h

Initial State

Reset with BOR

SVS Control Register

SVSCTL

SVSCTL, SVS Control Register

PORON

SVSFG

VLDx

SVSON

SVSOP

†

rw−0

†

rw−0

†

rw−0

†

rw−0

†

rw−0

†

Reset by a brownout reset only, not by a POR or PUC.

VLDx

Bits

7-4

Voltage level detect. These bits turn on the SVS and select the nominal SVS

threshold voltage level. See the device−specific datasheet for parameters.

0000 SVS is off

0001 1.9 V

0010 2.1 V

0011 2.2 V

0100 2.3 V

0101 2.4 V

0110 2.5 V

0111 2.65 V

1000 2.8 V

1001 2.9 V

1010 3.05

1011 3.2 V

1100 3.35 V

1101 3.5 V

1110 3.7 V

1111 Compares external input voltage SVSIN to 1.2 V.

PORON

SVSON

Bit 3

Bit 2

POR on. This bit enables the SVSFG flag to cause a POR device reset.

SVSFG does not cause a POR

SVSFG causes a POR

SVS on. This bit reflects the status of SVS operation. This bit DOES NOT turn

on the SVS. The SVS is turned on by setting VLDx > 0.

SVS is Off

SVS is On

SVSOP

SVSFG

Bit 1

Bit 0

SVS output. This bit reflects the output value of the SVS comparator.

SVS comparator output is high

SVS comparator output is low

SVS flag. This bit indicates a low voltage condition. SVSFG remains set after

a low voltage condition until reset by software or a brownout reset.

No low voltage condition occurred

A low condition is present or has occurred

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Chapter 7

Hardware Multiplier

This chapter describes the hardware multiplier. The hardware multiplier is

implemented in MSP430x14x and MSP430x16x devices.

Topic

Page

7.1 Hardware Multiplier Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

7.2 Hardware Multiplier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.3 Hardware Multiplier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

Hardware Multiplier

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Hardware Multiplier Introduction

7.1 Hardware Multiplier Introduction

The hardware multiplier is a peripheral and is not part of the MSP430 CPU.

This means, its activities do not interfere with the CPU activities. The multiplier

registers are peripheral registers that are loaded and read with CPU

instructions.

The hardware multiplier supports:

- Unsigned multiply

- Signed multiply

- Unsigned multiply accumulate

- Signed multiply accumulate

- 16×16 bits, 16×8 bits, 8×16 bits, 8×8 bits

The hardware multiplier block diagram is shown in Figure 7−1.

Figure 7−1. Hardware Multiplier Block Diagram

MPY 130h

MPYS 132h

MAC 134h

MACS 136h

OP1

OP2 138h

16 x 16 Multipiler

Accessible

MPY = 0000

MACS MPYS

MAC

32−bit Adder

MPY, MPYS

MAC, MACS

Multiplexer

32−bit Multiplexer

SUMEXT 13Eh

RESHI 13Ch

RESLO 13Ah

7-2

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Hardware Multiplier Operation

7.2 Hardware Multiplier Operation

The hardware multiplier supports unsigned multiply, signed multiply, unsigned

multiply accumulate, and signed multiply accumulate operations. The type of

operation is selected by the address the first operand is written to.

The hardware multiplier has two 16-bit operand registers, OP1 and OP2, and

three result registers, RESLO, RESHI, and SUMEXT. RESLO stores the low

word of the result, RESHI stores the high word of the result, and SUMEXT

stores information about the result. The result is ready in three MCLK cycles

and can be read with the next instruction after writing to OP2, except when

using an indirect addressing mode to access the result. When using indirect

addressing for the result, a NOPis required before the result is ready.

7.2.1 Operand Registers

The operand one register OP1 has four addresses, shown in Table 7−1, used

to select the multiply mode. Writing the first operand to the desired address

selects the type of multiply operation but does not start any operation. Writing

the second operand to the operand two register OP2 initiates the multiply

operation. Writing OP2 starts the selected operation with the values stored in

OP1 and OP2. The result is written into the three result registers RESLO,

RESHI, and SUMEXT.

Repeated multiply operations may be performed without reloading OP1 if the

OP1 value is used for successive operations. It is not necessary to re-write the

OP1 value to perform the operations.

Table 7−1.OP1 addresses

OP1 Address

0130h

MPY

Operation

Unsigned multiply

0132h

MPYS

Signed multiply

0134h

MAC

Unsigned multiply accumulate

Signed multiply accumulate

0136h

MACS

Hardware Multiplier

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Hardware Multiplier Operation

7.2.2 Result Registers

The result low register RESLO holds the lower 16-bits of the calculation result.

The result high register RESHI contents depend on the multiply operation and

are listed in Table 7−2.

Table 7−2.RESHI Contents

Mode

RESHI Contents

MPY

Upper 16-bits of the result

MPYS

The MSB is the sign of the result. The remaining bits are the

upper 15-bits of the result. Two’s complement notation is used

for the result.

MAC

Upper 16-bits of the result

MACS

Upper 16-bits of the result. Two’s complement notation is used

for the result.

The sum extension registers SUMEXT contents depend on the multiply

operation and are listed in Table 7−3.

Table 7−3.SUMEXT Contents

Mode

SUMEXT

MPY

SUMEXT is always 0000h

MPYS

SUMEXT contains the extended sign of the result

00000h Result was positive or zero

0FFFFh Result was negative

MAC

SUMEXT contains the carry of the result

0000h No carry for result

0001h Result has a carry

MACS

SUMEXT contains the extended sign of the result

00000h Result was positive or zero

0FFFFh Result was negative

MACS Underflow and Overflow

The multiplier does not automatically detect underflow or overflow in the

MACS mode. The accumulator range for positive numbers is 0 to 7FFF FFFFh

and for negative numbers is 0FFFF FFFFh to 8000 0000h. An overflow occurs

when the sum of two negative numbers yields a result that is in the range for

a positive number. An underflow occurs when the sum of two positive numbers

yields a result that is in the range for a negative number. In both of these cases,

the SUMEXT register contains the correct sign of the result, 0FFFFh for

overflow and 0000h for underflow. User software must detect and handle

these conditions appropriately.

7-4

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Hardware Multiplier Operation

7.2.3 Software Examples

Examples for all multiplier modes follow. All 8x8 modes use the absolute

address for the registers because the assembler will not allow .B access to

word registers when using the labels from the standard definitions file.

; 16x16 Unsigned Multiply

MOV #01234h,&MPY; Load first operand

MOV #05678h,&OP2; Load second operand

; ...

; Process results

; 8x8 Unsigned Multiply. Absolute addressing.

MOV.B #012h,&0130h; Load first operand

MOV.B #034h,&0138h; Load 2nd operand

; ...

; Process results

; 16x16 Signed Multiply

MOV #01234h,&MPYS ; Load first operand

MOV #05678h,&OP2; Load 2nd operand

; ...

; Process results

; 8x8 Signed Multiply. Absolute addressing.

MOV.B #012h,&0132h; Load first operand

SXT &MPYS

MOV.B #034h,&0138h; Load 2nd operand

SXT &OP2 ; Sign extend 2nd operand

; Sign extend first operand

; (triggers 2nd multiplication)

; Process results

; ...

; 16x16 Unsigned Multiply Accumulate

MOV #01234h,&MAC; Load first operand

MOV #05678h,&OP2; Load 2nd operand

; ...

; Process results

; 8x8 Unsigned Multiply Accumulate. Absolute addressing

MOV.B #012h,&0134h; Load first operand

MOV.B #034h,&0138h; Load 2nd operand

; ...

; Process results

; 16x16 Signed Multiply Accumulate

MOV #01234h,&MACS ; Load first operand

MOV #05678h,&OP2; Load 2nd operand

; ...

; Process results

; 8x8 Signed Multiply Accumulate. Absolute addressing

MOV.B #012h,&0136h; Load first operand

SXT &MACS

MOV.B #034h,R5

SXT R5

; Sign extend first operand

; Temp. location for 2nd operand

; Sign extend 2nd operand

; Load 2nd operand

MOV R5,&OP2

; ...

; Process results

Hardware Multiplier

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Hardware Multiplier Operation

7.2.4 Indirect Addressing of RESLO

When using indirect or indirect autoincrement addressing mode to access the

result registers, At least one instruction is needed between loading the second

operand and accessing one of the result registers:

; Access multiplier results with indirect addressing

MOV #RESLO,R5

; RESLO address in R5 for indirect

MOV &OPER1,&MPY ; Load 1st operand

MOV &OPER2,&OP2 ; Load 2nd operand

NOP

; Need one cycle

; Move RESLO

MOV @R5+,&xxx

MOV @R5,&xxx

; Move RESHI

7.2.5 Using Interrupts

If an interrupt occurs after writing OP1, but before writing OP2, and the

multiplier is used in servicing that interrupt, the original multiplier mode

selection is lost and the results are unpredictable. To avoid this, disable

interrupts before using the hardware multiplier or do not use the multiplier in

interrupt service routines.

; Disable interrupts before using the hardware multiplier

DINT

NOP

; Disable interrupts

; Required for DINT

MOV #xxh,&MPY; Load 1st operand

MOV #xxh,&OP2; Load 2nd operand

EINT

; Interrupts may be enable before

; Process results

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Hardware Multiplier Registers

7.3 Hardware Multiplier Registers

The hardware multiplier registers are listed in Table 7−4.

Table 7−4.Hardware Multiplier Registers

Short Form

Initial State

Unchanged

Undefined

Operand one - multiply

Operand one - signed multiply

Operand one - multiply accumulate

MPY

Read/write

Read

0130h

0132h

0134h

0136h

0138h

013Ah

013Ch

013Eh

MPYS

MAC

Operand one - signed multiply accumulate MACS

Operand two

OP2

Result low word

Result high word

Sum Extension register

RESLO

RESHI

SUMEXT

Hardware Multiplier

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Chapter 8

DMA Controller

The DMA controller module transfers data from one address to another

without CPU intervention. This chapter describes the operation of the DMA

controller. The DMA controller is implemented in MSP430x15x and

MSP430x16x devices.

Topic

Page

8.1 DMA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

8.2 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.3 DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18

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8.1 DMA Introduction

The direct memory access (DMA) controller transfers data from one address

to another, without CPU intervention, across the entire address range. For

example, the DMA controller can move data from the ADC12 conversion

memory to RAM.

Using the DMA controller can increase the throughput of peripheral modules.

It can also reduce system power consumption by allowing the CPU to remain

in a low-power mode without having to awaken to move data to or from a

peripheral.

The DMA controller features include:

- Three independent transfer channels

- Configurable DMA channel priorities

- Requires only two MCLK clock cycles

- Byte or word and mixed byte/word transfer capability

- Block sizes up to 65535 bytes or words

- Configurable transfer trigger selections

- Selectable edge or level-triggered transfer

- Four addressing modes

- Single, block, or burst-block transfer modes

The DMA controller block diagram is shown in Figure 8−1.

8-2

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Figure 8−1. DMA Controller Block Diagram

DMA0TSELx

JTAG Active

NMI Interrupt Request

ENNMI

Halt

DMAREQ

TACCR2_CCIFG

TBCCR2_CCIFG

USART0 data received

USART0 transmit ready

DAC12_0IFG

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

ROUNDROBIN

DMADSTINCRx DMADTx

DMADSTBYTE

ADC12IFGx

DMA Channel 0

DMA0SA

TACCR0_CCIFG

TBCCR0_CCIFG

USART1 data received

USART1 transmit ready

Multiplier ready

No trigger

DMA0DA

−−−

DMA0SZ

No trigger

DMA2IFG

DMAE0

1110

1111

DMASRSBYTE

DMASRCINCRx DMAEN

DMA1TSELx

DMADSTINCRx DMADTx

DMAREQ

TACCR2_CCIFG

TBCCR2_CCIFG

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

DMADSTBYTE

USART0 data received

USART0 transmit ready

DAC12_0IFG

ADC12IFGx

TACCR0_CCIFG

TBCCR0_CCIFG

USART1 data received

USART1 transmit ready

Multiplier ready

No trigger

DMA Channel 1

DMA1SA

Address

Space

DMA1DA

DMA1SZ

DMASRSBYTE

−−−

No trigger

DMASRCINCRx DMAEN

DMA0IFG

DMAE0

1110

1111

DMADSTINCRx DMADTx

DMA2TSELx

DMADSTBYTE

DMA Channel 2

DMAREQ

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

TACCR2_CCIFG

TBCCR2_CCIFG

USART0 data received

USART0 transmit ready

DAC12_0IFG

ADC12IFGx

TACCR0_CCIFG

TBCCR0_CCIFG

USART1 data received

USART1 transmit ready

Multiplier ready

No trigger

DMA2SA

DMA2DA

DMA2SZ

DMASRSBYTE

DMASRCINCRx DMAEN

DMAONFETCH

Halt CPU

−−−

No trigger

DMA1IFG

DMAE0

1110

1111

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8.2 DMA Operation

The DMA controller is configured with user software. The setup and operation

of the DMA is discussed in the following sections.

8.2.1 DMA Addressing Modes

The DMA controller has four addressing modes. The addressing mode for

each DMA channel is independently configurable. For example, channel 0

may transfer between two fixed addresses, while channel 1 transfers between

two blocks of addresses. The addressing modes are shown in Figure 8−2. The

addressing modes are:

- Fixed address to fixed address

- Fixed address to block of addresses

- Block of addresses to fixed address

- Block of addresses to block of addresses

The addressing modes are configured with the DMASRCINCRx and

DMADSTINCRx control bits. The DMASRCINCRx bits select if the source

address is incremented, decremented, or unchanged after each transfer. The

DMADSTINCRx bits select if the destination address is incremented,

decremented, or unchanged after each transfer.

Transfers may be byte-to-byte, word-to-word, byte-to-word, or word-to-byte.

When transferring word-to-byte, only the lower byte of the source-word

transfers. When transferring byte-to-word, the upper byte of the

destination-word is cleared when the transfer occurs.

Figure 8−2. DMA Addressing Modes

DMA

Controller

DMA

Controller

Address Space

Fixed Address To Fixed Address

Fixed Address To Block Of Addresses

DMA

Address Space

Controller

Address Space

Controller

Block Of Addresses To Fixed Address

Block Of Addresses To Block Of Addresses

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8.2.2 DMA Transfer Modes

The DMA controller has six transfer modes selected by the DMADTx bits as

listed in Table 8−1. Each channel is individually configurable for its transfer

mode. For example, channel 0 may be configured in single transfer mode,

while channel 1 is configured for burst-block transfer mode, and channel 2

operates in repeated block mode. The transfer mode is configured

independently from the addressing mode. Any addressing mode can be used

with any transfer mode.

Table 8−1.DMA Transfer Modes

DMADTx

Transfer

Mode

Description

000

001

Single transfer Each transfer requires a trigger. DMAEN is

automatically cleared when DMAxSZ transfers have

been made.

Block transfer A complete block is transferred with one trigger.

DMAEN is automatically cleared at the end of the

block transfer.

010, 011 Burst-block

transfer

CPU activity is interleaved with a block transfer.

DMAEN is automatically cleared at the end of the

burst-block transfer.

100

101

Repeated

single transfer enabled.

Each transfer requires a trigger. DMAEN remains

Repeated

A complete block is transferred with one trigger.

block transfer

DMAEN remains enabled.

110, 111 Repeated

burst-block

CPU activity is interleaved with a block transfer.

DMAEN remains enabled.

transfer

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Single Transfer

In single transfer mode, each byte/word transfer requires a separate trigger.

The single transfer state diagram is shown in Figure 8−3.

The DMAxSZ register is used to define the number of transfers to be made.

The DMADSTINCRx and DMASRCINCRx bits select if the destination

address and the source address are incremented or decremented after each

transfer. If DMAxSZ = 0, no transfers occur.

The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary

registers. The temporary values of DMAxSA and DMAxDA are incremented

or decremented after each transfer. The DMAxSZ register is decremented

after each transfer. When the DMAxSZ register decrements to zero it is

reloaded from its temporary register and the corresponding DMAIFG flag is

set. When DMADTx = 0, the DMAEN bit is cleared automatically when

DMAxSZ decrements to zero and must be set again for another transfer to

occur.

In repeated single transfer mode, the DMA controller remains enabled with

DMAEN = 1, and a transfer occurs every time a trigger occurs.

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Figure 8−3. DMA Single Transfer State Diagram

DMAEN = 0

Reset

DMAEN = 0

DMAEN = 1

DMAREQ = 0

T_Size → DMAxSZ

DMAxSZ → T_Size

DMAxSA → T_SourceAdd

[ DMADTx = 0

DMAxDA → T_DestAdd

AND DMAxSZ = 0]

OR DMAEN = 0

DMAABORT = 1

Idle

DMAABORT=0

Wait for Trigger

DMAREQ = 0

DMAxSZ > 0

AND DMAEN = 1

[+Trigger AND DMALEVEL = 0 ]

[Trigger=1 AND DMALEVEL=1]

2 x MCLK

T_Size → DMAxSZ

Hold CPU,

Transfer one word/byte

DMAxSA → T_SourceAdd

DMAxDA → T_DestAdd

[ENNMI = 1

AND NMI event]

[DMALEVEL = 1

AND Trigger = 0]

DMADTx = 4

AND DMAxSZ = 0

AND DMAEN = 1

Decrement DMAxSZ

Modify T_SourceAdd

Modify T_DestAdd

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Block Transfers

In block transfer mode, a transfer of a complete block of data occurs after one

trigger. When DMADTx = 1, the DMAEN bit is cleared after the completion of

the block transfer and must be set again before another block transfer can be

triggered. After a block transfer has been triggered, further trigger signals

occurring during the block transfer are ignored. The block transfer state

diagram is shown in Figure 8−4.

The DMAxSZ register is used to define the size of the block and the

DMADSTINCRx and DMASRCINCRx bits select if the destination address

and the source address are incremented or decremented after each transfer

of the block. If DMAxSZ = 0, no transfers occur.

The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary

registers. The temporary values of DMAxSA and DMAxDA are incremented

or decremented after each transfer in the block. The DMAxSZ register is

decremented after each transfer of the block and shows the number of

transfers remaining in the block. When the DMAxSZ register decrements to

zero it is reloaded from its temporary register and the corresponding DMAIFG

flag is set.

During a block transfer, the CPU is halted until the complete block has been

transferred. The block transfer takes 2 x MCLK x DMAxSZ clock cycles to

complete. CPU execution resumes with its previous state after the block

transfer is complete.

In repeated block transfer mode, the DMAEN bit remains set after completion

of the block transfer. The next trigger after the completion of a repeated block

transfer triggers another block transfer.

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Figure 8−4. DMA Block Transfer State Diagram

DMAEN = 0

Reset

DMAEN = 0

DMAREQ = 0

T_Size → DMAxSZ

DMAEN = 0

DMAEN = 1

DMAxSZ → T_Size

[DMADTx = 1

DMAxSA → T_SourceAdd

DMAxDA → T_DestAdd

AND DMAxSZ = 0]

DMAEN = 0

DMAABORT = 1

Idle

DMAREQ = 0

T_Size → DMAxSZ

DMAABORT=0

Wait for Trigger

DMAxSA → T_SourceAdd

DMAxDA → T_DestAdd

DMADTx = 5

AND DMAxSZ = 0

AND DMAEN = 1

[+Trigger AND DMALEVEL = 0 ]

[Trigger=1 AND DMALEVEL=1]

2 x MCLK

Hold CPU,

Transfer one word/byte

[ENNMI = 1

AND NMI event]

DMAxSZ > 0

[DMALEVEL = 1

AND Trigger = 0]

Decrement DMAxSZ

Modify T_SourceAdd

Modify T_DestAdd

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Burst-Block Transfers

In burst-block mode, transfers are block transfers with CPU activity

interleaved. The CPU executes 2 MCLK cycles after every four byte/word

transfers of the block resulting in 20% CPU execution capacity. After the

burst-block, CPU execution resumes at 100% capacity and the DMAEN bit is

cleared. DMAEN must be set again before another burst-block transfer can be

triggered. After a burst-block transfer has been triggered, further trigger

signals occurring during the burst-block transfer are ignored. The burst-block

transfer state diagram is shown in Figure 8−5.

The DMAxSZ register is used to define the size of the block and the

DMADSTINCRx and DMASRCINCRx bits select if the destination address

and the source address are incremented or decremented after each transfer

of the block. If DMAxSZ = 0, no transfers occur.

The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary

registers. The temporary values of DMAxSA and DMAxDA are incremented

or decremented after each transfer in the block. The DMAxSZ register is

decremented after each transfer of the block and shows the number of

transfers remaining in the block. When the DMAxSZ register decrements to

zero it is reloaded from its temporary register and the corresponding DMAIFG

flag is set.

In repeated burst-block mode the DMAEN bit remains set after completion of

the burst-block transfer and no further trigger signals are required to initiate

another burst-block transfer. Another burst-block transfer begins immediately

after completion of a burst-block transfer. In this case, the transfers must be

stopped by clearing the DMAEN bit, or by an NMI interrupt when ENNMI is set.

In repeated burst-block mode the CPU executes at 20% capacity continuously

until the repeated burst-block transfer is stopped.

8-10

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Figure 8−5. DMA Burst-Block Transfer State Diagram

DMAEN = 0

Reset

DMAEN = 0

DMAREQ = 0

T_Size → DMAxSZ

DMAEN = 0

DMAEN = 1

DMAxSZ → T_Size

[DMADTx = {2, 3}

AND DMAxSZ = 0]

DMAxSA → T_SourceAdd

DMAxDA → T_DestAdd

DMAEN = 0

DMAABORT = 1

Idle

DMAABORT=0

Wait for Trigger

[+Trigger AND DMALEVEL = 0 ]

[Trigger=1 AND DMALEVEL=1]

2 x MCLK

Hold CPU,

Transfer one word/byte

[ENNMI = 1

AND NMI event]

[DMALEVEL = 1

AND Trigger = 0]

T_Size → DMAxSZ

DMAxSA → T_SourceAdd

DMAxDA → T_DestAdd

DMAxSZ > 0

Decrement DMAxSZ

Modify T_SourceAdd

Modify T_DestAdd

DMAxSZ > 0 AND

DMAxSZ > 0

a multiple of 4 words/bytes

were transferred

[DMADTx = {6, 7}

AND DMAxSZ = 0]

2 x MCLK

Burst State

(release CPU for 2xMCLK)

8-11

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8.2.3 Initiating DMA Transfers

Each DMA channel is independently configured for its trigger source with the

DMAxTSELx bits as described in Table 8−2.The DMAxTSELx bits should be

modified only when the DMACTLx DMAEN bit is 0. Otherwise, unpredictable

DMA triggers may occur.

When selecting the trigger, the trigger must not have already occurred, or the

transfer will not take place. For example, if the TACCR2 CCIFG bit is selected

as a trigger, and it is already set, no transfer will occur until the next time the

TACCR2 CCIFG bit is set.

Edge-Sensitive Triggers

When DMALEVEL = 0, edge-sensitive triggers are used and the rising edge

of the trigger signal initiates the transfer. In single-transfer mode, each transfer

requires its own trigger. When using block or burst-block modes, only one

trigger is required to initiate the block or burst-block transfer.

Level-Sensitive Triggers

When DMALEVEL = 1, level-sensitive triggers are used. For proper operation,

level-sensitive triggers can only be used when external trigger DMAE0 is

selected as the trigger. DMA transfers are triggered as long as the trigger

signal is high and the DMAEN bit remains set.

The trigger signal must remain high for a block or burst-block transfer to

complete. If the trigger signal goes low during a block or burst-block transfer,

the DMA controller is held in its current state until the trigger goes back high

or until the DMA registers are modified by software. If the DMA registers are

not modified by software, when the trigger signal goes high again, the transfer

resumes from where it was when the trigger signal went low.

When DMALEVEL = 1, transfer modes selected when DMADTx = {0, 1, 2, 3}

are recommended because the DMAEN bit is automatically reset after the

configured transfer.

Halting Executing Instructions for DMA Transfers

The DMAONFETCH bit controls when the CPU is halted for a DMA transfer.

When DMAONFETCH = 0, the CPU is halted immediately and the transfer

begins when a trigger is received. When DMAONFETCH = 1, the CPU finishes

the currently executing instruction before the DMA controller halts the CPU

and the transfer begins.

Note: DMAONFETCH Must Be Used When The DMA Writes To Flash

If the DMA controller is used to write to flash memory, the DMAONFETCH

bit must be set. Otherwise, unpredictable operation can result.

8-12

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Table 8−2.DMA Trigger Operation

DMAxTSELx Operation

0000

A transfer is triggered when the DMAREQ bit is set. The DMAREQ bit is automatically reset

when the transfer starts

0001

A transfer is triggered when the TACCR2 CCIFG flag is set. The TACCR2 CCIFG flag is

automatically reset when the transfer starts. If the TACCR2 CCIE bit is set, the TACCR2

CCIFG flag will not trigger a transfer.

0010

0011

A transfer is triggered when the TBCCR2 CCIFG flag is set. The TBCCR2 CCIFG flag is

automatically reset when the transfer starts. If the TBCCR2 CCIE bit is set, the TBCCR2

CCIFG flag will not trigger a transfer.

A transfer is triggered when USART0 receives new data. In I C mode, the trigger is the

data-received condition, not the RXRDYIFG flag. RXRDYIFG is not cleared when the transfer

starts, and setting RXRDYIFG with software will not trigger a transfer. If RXRDYIE is set, the

data received condition will not trigger a transfer. In UART or SPI mode, a transfer is triggered

when the URXIFG0 flag is set. URXIFG0 is automatically reset when the transfer starts. If

URXIE0 is set, the URXIFG0 flag will not trigger a transfer.

0100

A transfer is triggered when USART0 is ready to transmit new data. In I C mode, the trigger

is the transmit-ready condition, not the TXRDYIFG flag. TXRDYIFG is not cleared when the

transfer starts, and setting TXRDYIFG with software will not trigger a transfer. If TXRDYIE is

set, the transmit ready condition will not trigger a transfer. In UART or SPI mode, a transfer is

triggered when the UTXIFG0 flag is set. UTXIFG0 is automatically reset when the transfer

starts. If UTXIE0 is set, the UTXIFG0 flag will not trigger a transfer.

0101

0110

A transfer is triggered when the DAC12_0CTL DAC12IFG flag is set. The DAC12_0CTL

DAC12IFG flag is automatically cleared when the transfer starts. If the DAC12_0CTL

DAC12IE bit is set, the DAC12_0CTL DAC12IFG flag will not trigger a transfer.

A transfer is triggered by an ADC12IFGx flag. When single-channel conversions are

performed, the corresponding ADC12IFGx is the trigger. When sequences are used, the

ADC12IFGx for the last conversion in the sequence is the trigger. A transfer is triggered when

the conversion is completed and the ADC12IFGx is set. Setting the ADC12IFGx with software

will not trigger a transfer. All ADC12IFGx flags are automatically reset when the associated

ADC12MEMx register is accessed by the DMA controller.

0111

1000

A transfer is triggered when the TACCR0 CCIFG flag is set. The TACCR0 CCIFG flag is

automatically reset when the transfer starts. If the TACCR0 CCIE bit is set, the TACCR0

CCIFG flag will not trigger a transfer.

A transfer is triggered when the TBCCR0 CCIFG flag is set. The TBCCR0 CCIFG flag is

automatically reset when the transfer starts. If the TBCCR0 CCIE bit is set, the TBCCR0

CCIFG flag will not trigger a transfer.

1001

1010

A transfer is triggered when the URXIFG1 flag is set. URXIFG1 is automatically reset when

the transfer starts. If URXIE1 is set, the URXIFG1 flag will not trigger a transfer.

A transfer is triggered when the UTXIFG1 flag is set. UTXIFG1 is automatically reset when

the transfer starts. If UTXIE1 is set, the UTXIFG1 flag will not trigger a transfer.

1011

1100

1101

1110

A transfer is triggered when the hardware multiplier is ready for a new operand.

No transfer is triggered.

A transfer is triggered when the DMAxIFG flag is set. DMA0IFG triggers channel 1, DMA1IFG

triggers channel 2, and DMA2IFG triggers channel 0. None of the DMAxIFG flags are

automatically reset when the transfer starts.

1111

A transfer is triggered by the external trigger DMAE0.

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8.2.4 Stopping DMA Transfers

There are two ways to stop DMA transfers in progress:

- A single, block, or burst-block transfer may be stopped with an NMI

interrupt, if the ENNMI bit is set in register DMACTL1.

- A burst-block transfer may be stopped by clearing the DMAEN bit.

8.2.5 DMA Channel Priorities

The default DMA channel priorities are DMA0−DMA1−DMA2. If two or three

triggers happen simultaneously or are pending, the channel with the highest

priority completes its transfer (single, block or burst-block transfer) first, then

the second priority channel, then the third priority channel. Transfers in

progress are not halted if a higher priority channel is triggered. The higher

priority channel waits until the transfer in progress completes before starting.

The DMA channel priorities are configurable with the ROUNDROBIN bit.

When the ROUNDROBIN bit is set, the channel that completes a transfer

becomes the lowest priority. The order of the priority of the channels always

stays the same, DMA0−DMA1−DMA2, for example:

DMA Priority

Transfer Occurs

DMA1

New DMA Priority

DMA2 − DMA0 − DMA1

DMA0 − DMA1 − DMA2

DMA1 − DMA2 − DMA0

DMA0 − DMA1 − DMA2

DMA2 − DMA0 − DMA1

DMA0 − DMA1 − DMA2

DMA2

DMA0

When the ROUNDROBIN bit is cleared the channel priority returns to the

default priority.

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8.2.6 DMA Transfer Cycle Time

The DMA controller requires one or two MCLK clock cycles to synchronize

before each single transfer or complete block or burst-block transfer. Each

byte/word transfer requires two MCLK cycles after synchronization, and one

cycle of wait time after the transfer. Because the DMA controller uses MCLK,

the DMA cycle time is dependent on the MSP430 operating mode and clock

system setup.

If the MCLK source is active, but the CPU is off, the DMA controller will use the

MCLK source for each transfer, without re-enabling the CPU. If the MCLK

source is off, the DMA controller will temporarily restart MCLK, sourced with

DCOCLK, for the single transfer or complete block or burst-block transfer. The

CPU remains off, and after the transfer completes, MCLK is turned off. The

maximum DMA cycle time for all operating modes is shown in Table 8−3.

Table 8−3.Maximum Single-Transfer DMA Cycle Time

CPU Operating Mode

Clock Source

Maximum DMA Cycle Time

4 MCLK cycles

Active mode

MCLK=DCOCLK

MCLK=LFXT1CLK

4 MCLK cycles

Low-power mode LPM0/1 MCLK=DCOCLK

Low-power mode LPM3/4 MCLK=DCOCLK

Low-power mode LPM0/1 MCLK=LFXT1CLK

Low-power mode LPM3 MCLK=LFXT1CLK

Low-power mode LPM4 MCLK=LFXT1CLK

5 MCLK cycles

†

5 MCLK cycles + 6 µs

5 MCLK cycles

†

5 MCLK cycles + 6 µs

†

The additional 6 µs are needed to start the DCOCLK. It is the t

(LPMx)

parameter in the data sheet.

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8.2.7 Using DMA with System Interrupts

DMA transfers are not interruptible by system interrupts. System interrupts

remain pending until the completion of the transfer. NMI interrupts can

interrupt the DMA controller if the ENNMI bit is set.

System interrupt service routines are interrupted by DMA transfers. If an

interrupt service routine or other routine must execute with no interruptions,

the DMA controller should be disabled prior to executing the routine.

8.2.8 DMA Controller Interrupts

Each DMA channel has its own DMAIFG flag. Each DMAIFG flag is set in any

mode, when the corresponding DMAxSZ register counts to zero. If the

corresponding DMAIE and GIE bits are set, an interrupt request is generated.

All DMAIFG flags source only one DMA controller interrupt vector and the

interrupt vector is shared with the DAC12 module. Software must check the

DMAIFG and DAC12IFG flags to determine the source of the interrupt. The

DMAIFG flags are not reset automatically and must be reset by software.

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8.2.9 Using the I C Module with the DMA Controller

The I C module provides two trigger sources for the DMA controller. The I C

module can trigger a transfer when new I C data is received and the when the

transmit data is needed.

The TXDMAEN and RXDMAEN bits enable or disable the use of the DMA

controller with the I C module. When RXDMAEN = 1, the DMA controller can

be used to transfer data from the I C module after the I C modules receives

data. When RXDMAEN = 1, RXRDYIE is ignored and RXRDYIFG will not

generate an interrupt.

When TXDMAEN = 1, the DMA controller can be used to transfer data to the

I C module for transmission. When TXDMAEN = 1, TXRDYIE is ignored and

TXRDYIFG will not generate an interrupt.

8.2.10 Using ADC12 with the DMA Controller

MSP430 devices with an integrated DMA controller can automatically move

data from any ADC12MEMx register to another location. DMA transfers are

done without CPU intervention and independently of any low-power modes.

The DMA controller increases throughput of the ADC12 module, and

enhances low-power applications allowing the CPU to remain off while data

transfers occur.

DMA transfers can be triggered from any ADC12IFGx flag. When CONSEQx

= {0,2} the ADC12IFGx flag for the ADC12MEMx used for the conversion can

trigger a DMA transfer. When CONSEQx = {1,3}, the ADC12IFGx flag for the

last ADC12MEMx in the sequence can trigger a DMA transfer. Any

ADC12IFGx flag is automatically cleared when the DMA controller accesses

the corresponding ADC12MEMx.

8.2.11 Using DAC12 With the DMA Controller

MSP430 devices with an integrated DMA controller can automatically move

data to the DAC12_xDAT register. DMA transfers are done without CPU

intervention and independently of any low-power modes. The DMA controller

increases throughput to the DAC12 module, and enhances low-power

applications allowing the CPU to remain off while data transfers occur.

Applications requiring periodic waveform generation can benefit from using

the DMA controller with the DAC12. For example, an application that produces

a sinusoidal waveform may store the sinusoid values in a table. The DMA

controller can continuously and automatically transfer the values to the DAC12

at specific intervals creating the sinusoid with zero CPU execution. The

DAC12_xCTL DAC12IFG flag is automatically cleared when the DMA

controller accesses the DAC12_xDAT register.

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8.3 DMA Registers

The DMA registers are listed in Table 8−4:

Table 8−4.DMA Registers

Short Form

DMACTL0

DMACTL1

DMA0CTL

DMA0SA

DMA0DA

DMA0SZ

DMA1CTL

DMA1SA

DMA1DA

DMA1SZ

DMA2CTL

DMA2SA

DMA2DA

DMA2SZ

Initial State

Reset with POR

Unchanged

DMA control 0

Read/write

0122h

0124h

01E0h

01E2h

01E4h

01E6h

01E8h

01EAh

01ECh

01EEh

01F0h

01F2h

01F4h

01F6h

DMA control 1

DMA channel 0 control

DMA channel 0 source address

DMA channel 0 destination address

DMA channel 0 transfer size

DMA channel 1 control

Unchanged

Reset with POR

Unchanged

DMA channel 1 source address

DMA channel 1 destination address

DMA channel 1 transfer size

DMA channel 2 control

Unchanged

Reset with POR

Unchanged

DMA channel 2 source address

DMA channel 2 destination address

DMA channel 2 transfer size

Unchanged

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DMACTL0, DMA Control Register 0

DMA2TSELx

Reserved

rw−(0)

DMA1TSELx

DMA0TSELx

rw−(0)

Reserved

Bits

Reserved

15−12

DMA2

TSELx

Bits

11−8

DMA trigger select. These bits select the DMA transfer trigger.

0000 DMAREQ bit (software trigger)

0001 TACCR2 CCIFG bit

0010 TBCCR2 CCIFG bit

0011 URXIFG0 (UART/SPI mode), USART0 data received (I C mode)

0100 UTXIFG0 (UART/SPI mode), USART0 transmit ready (I C mode)

0101 DAC12_0CTL DAC12IFG bit

0110 ADC12 ADC12IFGx bit

0111 TACCR0 CCIFG bit

1000 TBCCR0 CCIFG bit

1001 URXIFG1 bit

1010 UTXIFG1 bit

1011 Multiplier ready

1100 No action

1101 No action

1110 DMA0IFG bit triggers DMA channel 1

DMA1IFG bit triggers DMA channel 2

DMA2IFG bit triggers DMA channel 0

1111 External trigger DMAE0

DMA1

TSELx

Bits

7−4

Same as DMA2TSELx

DMA0

TSELx

Bits

3–0

Same as DMA2TSELx

8-19

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DMACTL1, DMA Control Register 1

DMA

ONFETCH

ROUND

ROBIN

ENNMI

rw−(0)

Reserved

Bits

15−3

Reserved. Read only. Always read as 0.

DMA on fetch

DMA

ONFETCH

Bit 2

The DMA transfer occurs immediately

The DMA transfer occurs on next instruction fetch after the trigger

ROUND

ROBIN

Bit 1

Bit 0

Round robin. This bit enables the round-robin DMA channel priorities.

DMA channel priority is DMA0 − DMA1 − DMA2

DMA channel priority changes with each transfer

ENNMI

Enable NMI. This bit enables the interruption of a DMA transfer by an NMI

interrupt. When an NMI interrupts a DMA transfer, the current transfer is

completed normally, further transfers are stopped, and DMAABORT is set.

NMI interrupt does not interrupt DMA transfer

NMI interrupt interrupts a DMA transfer

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DMAxCTL, DMA Channel x Control Register

DMADSTINCRx

rw−(0) rw−(0)

Reserved

rw−(0)

DMADTx

rw−(0)

DMASRCINCRx

rw−(0) rw−(0)

rw−(0)

DMA

DMALEVEL

rw−(0)

DMAEN

rw−(0)

DMAIFG

DMAIE

DMAREQ

DSTBYTE

SRCBYTE

ABORT

rw−(0)

Reserved

DMADTx

Bit 15

Bits

Reserved

DMA Transfer mode.

14−12 000 Single transfer

001 Block transfer

010 Burst-block transfer

011 Burst-block transfer

100 Repeated single transfer

101 Repeated block transfer

110 Repeated burst-block transfer

111 Repeated burst-block transfer

DMA

DSTINCRx

Bits

DMA destination increment. This bit selects automatic incrementing or

11−10 decrementing of the destination address after each byte or word transfer.

When DMADSTBYTE=1, the destination address increments/decrements by

one.

When

DMADSTBYTE=0,

the

destination

address

increments/decrements by two. The DMAxDA is copied into a temporary

is not incremented or decremented.

00 Destination address is unchanged

01 Destination address is unchanged

10 Destination address is decremented

11 Destination address is incremented

DMA

SRCINCRx

Bits

9−8

DMA source increment. This bit selects automatic incrementing or

decrementing of the source address for each byte or word transfer. When

DMASRCBYTE=1, the source address increments/decrements by one.

When DMASRCBYTE=0, the source address increments/decrements by

two. The DMAxSA is copied into a temporary register and the temporary

decremented.

00 Source address is unchanged

01 Source address is unchanged

10 Source address is decremented

11 Source address is incremented

DMA

DSTBYTE

Bit 7

DMA destination byte. This bit selects the destination as a byte or word.

Word

Byte

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DMA

SRCBYTE

Bit 6

Bit 5

DMA source byte. This bit selects the source as a byte or word.

Word

Byte

DMA

LEVEL

DMA level. This bit selects between edge-sensitive and level-sensitive

triggers.

Edge sensitive (rising edge)

Level sensitive (high level)

DMAEN

DMAIFG

DMAIE

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DMA enable

Disabled

Enabled

DMA interrupt flag

No interrupt pending

Interrupt pending

DMA interrupt enable

Disabled

Enabled

DMA

ABORT

DMA Abort. This bit indicates if a DMA transfer was interrupt by an NMI.

DMA transfer not interrupted

DMA transfer was interrupted by NMI

DMAREQ

DMA request. Software-controlled DMA start. DMAREQ is reset

automatically.

No DMA start

Start DMA

DMAxSA, DMA Source Address Register

DMAxSAx

DMAxSAx Bits

DMA source address. The source address register points to the DMA source

address for single transfers or the first source address for block transfers. The

source address register remains unchanged during block and burst-block

transfers.

15−0

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DMAxDA, DMA Destination Address Register

DMAxDAx

DMAxDAx Bits

DMA destination address. The destination address register points to the

destination address for single transfers or the first address for block transfers.

The DMAxDA register remains unchanged during block and burst-block

transfers.

15−0

DMAxSZ, DMA Size Address Register

DMAxSZx

DMAxSZx Bits

DMA size. The DMA size register defines the number of byte/word data per

block transfer. DMAxSZ register decrements with each word or byte transfer.

When DMAxSZ decrements to 0, it is immediately and automatically reloaded

with its previously initialized value.

15−0

00000h Transfer is disabled

00001h One byte or word is transferred

00002h Two bytes or words are transferred

0FFFFh 65535 bytes or words are transferred

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Chapter 9

Digital I/O

This chapter describes the operation of the digital I/O ports. Ports P1-P2 are

implemented in MSP430x11xx devices. Ports P1-P3 are implemented in

MSP430x12xx devices. Ports P1-P6 are implemented in MSP430x13x,

MSP430x14x, MSP430x15x, and MSP430x16x devices.

Topic

Page

9.1 Digital I/O Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.2 Digital I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.3 Digital I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

Digital I/O

9-1

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Digital I/O Introduction

9.1 Digital I/O Introduction

MSP430 devices have up to 6 digital I/O ports implemented, P1 - P6. Each port

has eight I/O pins. Every I/O pin is individually configurable for input or output

direction, and each I/O line can be individually read or written to.

Ports P1 and P2 have interrupt capability. Each interrupt for the P1 and P2 I/O

lines can be individually enabled and configured to provide an interrupt on a

rising edge or falling edge of an input signal. All P1 I/O lines source a single

interrupt vector, and all P2 I/O lines source a different, single interrupt vector.

The digital I/O features include:

- Independently programmable individual I/Os

- Any combination of input or output

- Individually configurable P1 and P2 interrupts

- Independent input and output data registers

9-2

Digital I/O

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Digital I/O Operation

9.2 Digital I/O Operation

The digital I/O is configured with user software. The setup and operation of the

digital I/O is discussed in the following sections.

9.2.1 Input Register PxIN

Each bit in each PxIN register reflects the value of the input signal at the

corresponding I/O pin when the pin is configured as I/O function.

Bit = 0: The input is low

Bit = 1: The input is high

Note: Writing to Read-Only Registers PxIN

Writing to these read-only registers results in increased current consumption

while the write attempt is active.

9.2.2 Output Registers PxOUT

Each bit in each PxOUT register is the value to be output on the corresponding

I/O pin when the pin is configured as I/O function and output direction.

Bit = 0: The output is low

Bit = 1: The output is high

9.2.3 Direction Registers PxDIR

Each bit in each PxDIR register selects the direction of the corresponding I/O

pin, regardless of the selected function for the pin. PxDIR bits for I/O pins that

are selected for other module functions must be set as required by the other

function.

Bit = 0: The port pin is switched to input direction

Bit = 1: The port pin is switched to output direction

Digital I/O

9-3

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Digital I/O Operation

9.2.4 Function Select Registers PxSEL

Port pins are often multiplexed with other peripheral module functions. See the

device-specific data sheet to determine pin functions. Each PxSEL bit is used

to select the pin function − I/O port or peripheral module function.

Bit = 0: I/O Function is selected for the pin

Bit = 1: Peripheral module function is selected for the pin

Setting PxSELx = 1 does not automatically set the pin direction. Other

peripheral module functions may require the PxDIRx bits to be configured

according to the direction needed for the module function. See the pin

schematics in the device-specific datasheet.

;Output ACLK on P2.0 on MSP430F11x1

BIS.B #01h,&P2SEL ; Select ACLK function for pin

BIS.B #01h,&P2DIR ; Set direction to output *Required*

Note: P1 and P2 Interrupts Are Disabled When PxSEL = 1

When any P1SELx or P2SELx bit is set, the corresponding pin’s interrupt

function is disabled. Therefore, signals on these pins will not generate P1 or

P2 interrupts, regardless of the state of the corresponding P1IE or P2IE bit.

When a port pin is selected as an input to a peripheral, the input signal to the

peripheral is a latched representation of the signal at the device pin. While

PxSELx=1, the internal input signal follows the signal at the pin. However, if

the PxSELx=0, the input to the peripheral maintains the value of the input

signal at the device pin before the PxSELx bit was reset.

9-4

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Digital I/O Operation

9.2.5 P1 and P2 Interrupts

Each pin in ports P1 and P2 have interrupt capability, configured with the

PxIFG, PxIE, and PxIES registers. All P1 pins source a single interrupt vector,

and all P2 pins source a different single interrupt vector. The PxIFG register

can be tested to determine the source of a P1 or P2 interrupt.

Interrupt Flag Registers P1IFG, P2IFG

Each PxIFGx bit is the interrupt flag for its corresponding I/O pin and is set

when the selected input signal edge occurs at the pin. All PxIFGx interrupt

flags request an interrupt when their corresponding PxIE bit and the GIE bit

are set. Each PxIFG flag must be reset with software. Software can also set

each PxIFG flag, providing a way to generate a software initiated interrupt.

Bit = 0: No interrupt is pending

Bit = 1: An interrupt is pending

Only transitions, not static levels, cause interrupts. If any PxIFGx flag becomes

set during a Px interrupt service routine, or is set after the RETIinstruction of

a Px interrupt service routine is executed, the set PxIFGx flag generates

another interrupt. This ensures that each transition is acknowledged.

Note: PxIFG Flags When Changing PxOUT or PxDIR

Writing to P1OUT, P1DIR, P2OUT, or P2DIR can result in setting the

corresponding P1IFG or P2IFG flags.

Note: Length of I/O Pin Interrupt Event

Any external interrupt event should be at least 1.5 times MCLK or longer, to

ensure that it is accepted and the corresponding interrupt flag is set.

Digital I/O

9-5

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Digital I/O Operation

Interrupt Edge Select Registers P1IES, P2IES

Each PxIES bit selects the interrupt edge for the corresponding I/O pin.

Bit = 0: The PxIFGx flag is set with a low-to-high transition

Bit = 1: The PxIFGx flag is set with a high-to-low transition

Note: Writing to PxIESx

Writing to P1IES, or P2IES can result in setting the corresponding interrupt

flags.

PxIESx

0 → 1

1 → 0

PxINx

PxIFGx

May be set

Unchanged

May be set

Interrupt Enable P1IE, P2IE

Each PxIE bit enables the associated PxIFG interrupt flag.

Bit = 0: The interrupt is disabled

Bit = 1: The interrupt is enabled

9.2.6 Configuring Unused Port Pins

Unused I/O pins should be configured as I/O function, output direction, and left

unconnected on the PC board, to reduce power consumption. The value of the

PxOUT bit is don’t care, since the pin is unconnected. See chapter System

Resets, Interrupts, and Operating Modes for termination unused pins.

9-6

Digital I/O

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Digital I/O Registers

9.3 Digital I/O Registers

Seven registers are used to configure P1 and P2. Four registers are used to

configure ports P3 - P6. The digital I/O registers are listed in Table 9−1.

Table 9−1.Digital I/O Registers

Port

Short Form

P1IN

Address

020h

021h

022h

023h

024h

025h

026h

028h

029h

02Ah

02Bh

02Ch

02Dh

02Eh

018h

019h

01Ah

01Bh

01Ch

01Dh

01Eh

01Fh

030h

031h

032h

033h

034h

035h

036h

037h

Read only

Read/write

Read only

Read/write

Read only

Read/write

Read only

Read/write

Read only

Read/write

Read only

Read/write

Initial State

−

Input

P1OUT

P1DIR

P1IFG

P1IES

P1IE

Unchanged

Reset with PUC

Unchanged

Reset with PUC

−

Output

Direction

Interrupt Flag

Interrupt Edge Select

Interrupt Enable

Port Select

Input

P1SEL

P2IN

P2OUT

P2DIR

P2IFG

P2IES

P2IE

Unchanged

Reset with PUC

Unchanged

Reset with PUC

−

Output

Direction

Interrupt Flag

Interrupt Edge Select

Interrupt Enable

Port Select

Input

P2SEL

P3IN

P3OUT

P3DIR

P3SEL

P4IN

Unchanged

Reset with PUC

−

Output

Direction

Port Select

Input

P4OUT

P4DIR

P4SEL

P5IN

Unchanged

Reset with PUC

−

Output

Direction

Port Select

Input

P5OUT

P5DIR

P5SEL

P6IN

Unchanged

Reset with PUC

−

Output

Direction

Port Select

Input

P6OUT

P6DIR

P6SEL

Unchanged

Reset with PUC

Output

Direction

Port Select

Digital I/O

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9-8

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Chapter 10

Watchdog Timer

The watchdog timer is a 16-bit timer that can be used as a watchdog or as an

interval timer. This chapter describes the watchdog timer. The watchdog timer

is implemented in all MSP430x1xx devices.

Topic

Page

10.1 Watchdog Timer Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.2 Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

10.2 Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

Watchdog Timer

10-1

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Watchdog Timer Introduction

10.1 Watchdog Timer Introduction

The primary function of the watchdog timer (WDT) module is to perform a

controlled system restart after a software problem occurs. If the selected time

interval expires, a system reset is generated. If the watchdog function is not

needed in an application, the module can be configured as an interval timer

and can generate interrupts at selected time intervals.

Features of the watchdog timer module include:

- Four software-selectable time intervals

- Watchdog mode

- Interval mode

- Access to WDT control register is password protected

- Control of RST/NMI pin function

- Selectable clock source

- Can be stopped to conserve power

The WDT block diagram is shown in Figure 10−1.

Note: Watchdog Timer Powers Up Active

After a PUC, the WDT module is automatically configured in the watchdog

mode with an initial ~32-ms reset interval using the DCOCLK. The user must

setup or halt the WDT prior to the expiration of the initial reset interval.

10-2

Watchdog Timer

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Watchdog Timer Introduction

Figure 10−1. Watchdog Timer Block Diagram

WDTCTL

MDB

MSB

WDTQn

Int.

Flag

Q13

Q15

16−bit

Counter

Password

Compare

Pulse

Generator

16−bit

R / W

Clear

PUC

CLK

(Asyn)

EQU

Write Enable

Low Byte

EQU

SMCLK

ACLK

WDTHOLD

WDTNMIES

WDTNMI

WDTTMSEL

WDTCNTCL

WDTSSEL

WDTIS1

WDTIS0

LSB

Watchdog Timer

10-3

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Watchdog Timer Operation

10.2 Watchdog Timer Operation

The WDT module can be configured as either a watchdog or interval timer with

the WDTCTL register. The WDTCTL register also contains control bits to

configure the RST/NMI pin. WDTCTL is a 16-bit, password-protected,

read/write register. Any read or write access must use word instructions and

write accesses must include the write password 05Ah in the upper byte. Any

write to WDTCTL with any value other than 05Ah in the upper byte is a security

key violation and triggers a PUC system reset regardless of timer mode. Any

read of WDTCTL reads 069h in the upper byte.

10.2.1 Watchdog Timer Counter

The watchdog timer counter (WDTCNT) is a 16-bit up-counter that is not

directly accessible by software. The WDTCNT is controlled and time intervals

selected through the watchdog timer control register WDTCTL.

The WDTCNT can be sourced from ACLK or SMCLK. The clock source is

selected with the WDTSSEL bit.

10.2.2 Watchdog Mode

After a PUC condition, the WDT module is configured in the watchdog mode

with an initial ~32-ms reset interval using the DCOCLK. The user must setup,

halt, or clear the WDT prior to the expiration of the initial reset interval or

another PUC will be generated. When the WDT is configured to operate in

watchdog mode, either writing to WDTCTL with an incorrect password, or

expiration of the selected time interval triggers a PUC. A PUC resets the WDT

to its default condition and configures the RST/NMI pin to reset mode.

10.2.3 Interval Timer Mode

Setting the WDTTMSEL bit to 1 selects the interval timer mode. This mode can

be used to provide periodic interrupts. In interval timer mode, the WDTIFG flag

is set at the expiration of the selected time interval. A PUC is not generated

in interval timer mode at expiration of the selected timer interval and the

WDTIFG enable bit WDTIE remains unchanged.

When the WDTIE bit and the GIE bit are set, the WDTIFG flag requests an

interrupt. The WDTIFG interrupt flag is automatically reset when its interrupt

request is serviced, or may be reset by software. The interrupt vector address

in interval timer mode is different from that in watchdog mode.

Note: Modifying the Watchdog Timer

The WDT interval should be changed together with WDTCNTCL = 1 in a

single instruction to avoid an unexpected immediate PUC or interrupt.

The WDT should be halted before changing the clock source to avoid a

possible incorrect interval.

10-4

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Watchdog Timer Operation

10.2.4 Watchdog Timer Interrupts

The WDT uses two bits in the SFRs for interrupt control.

- The WDT interrupt flag, WDTIFG, located in IFG1.0

- The WDT interrupt enable, WDTIE, located in IE1.0

When using the WDT in the watchdog mode, the WDTIFG flag sources a reset

vector interrupt. The WDTIFG can be used by the reset interrupt service

routine to determine if the watchdog caused the device to reset. If the flag is

set, then the watchdog timer initiated the reset condition either by timing out

or by a security key violation. If WDTIFG is cleared, the reset was caused by

a different source.

When using the WDT in interval timer mode, the WDTIFG flag is set after the

selected time interval and requests a WDT interval timer interrupt if the WDTIE

and the GIE bits are set. The interval timer interrupt vector is different from the

reset vector used in watchdog mode. In interval timer mode, the WDTIFG flag

is reset automatically when the interrupt is serviced, or can be reset with

software.

Watchdog Timer

10-5

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Watchdog Timer Operation

10.2.5 Operation in Low-Power Modes

The MSP430 devices have several low-power modes. Different clock signals

are available in different low-power modes. The requirements of the user’s

application and the type of clocking used determine how the WDT should be

configured. For example, the WDT should not be configured in watchdog

mode with SMCLK as its clock source if the user wants to use low-power mode

3 because SMCLK is not active in LPM3 and the WDT would not function.

When the watchdog timer is not required, the WDTHOLD bit can be used to

hold the WDTCNT, reducing power consumption.

10.2.6 Software Examples

Any write operation to WDTCTL must be a word operation with 05Ah

(WDTPW) in the upper byte:

; Periodically clear an active watchdog

MOV #WDTPW+WDTCNTCL,&WDTCTL

;

; Change watchdog timer interval

MOV #WDTPW+WDTCNTL+SSEL,&WDTCTL

;

; Stop the watchdog

MOV #WDTPW+WDTHOLD,&WDTCTL

;

; Change WDT to interval timer mode, clock/8192 interval

MOV #WDTPW+WDTCNTCL+WDTTMSEL+WDTIS0,&WDTCTL

10-6

Watchdog Timer

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Watchdog Timer Registers

10.3 Watchdog Timer Registers

The watchdog timer module registers are listed in Table 10−1.

Table 10−1.Watchdog Timer Registers

Short Form

Initial State

Watchdog timer control register

SFR interrupt enable register 1

SFR interrupt flag register 1

WDTCTL

IE1

Read/write

0120h

0000h

0002h

06900h with PUC

Reset with PUC

†

IFG1

Reset with PUC

†

WDTIFG is reset with POR

Watchdog Timer

10-7

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Watchdog Timer Registers

WDTCTL, Watchdog Timer Register

Read as 069h

WDTPW, must be written as 05Ah

WDTTMSEL WDTCNTCL WDTSSEL

rw−0 r0(w) rw−0

WDTHOLD WDTNMIES

WDTNMI

rw−0

WDTISx

rw−0

WDTPW

Bits

15-8

Watchdog timer password. Always read as 069h. Must be written as 05Ah, or

a PUC will be generated.

WDTHOLD

Bit 7

Watchdog timer hold. This bit stops the watchdog timer. Setting WDTHOLD

= 1 when the WDT is not in use conserves power.

Watchdog timer is not stopped

Watchdog timer is stopped

WDTNMIES

Bit 6

Watchdog timer NMI edge select. This bit selects the interrupt edge for the

NMI interrupt when WDTNMI = 1. Modifying this bit can trigger an NMI. Modify

this bit when WDTNMI = 0 to avoid triggering an accidental NMI.

NMI on rising edge

NMI on falling edge

WDTNMI

Bit 5

Bit 4

Bit 3

Watchdog timer NMI select. This bit selects the function for the RST/NMI pin.

Reset function

NMI function

WDTTMSEL

WDTCNTCL

Watchdog timer mode select

Watchdog mode

Interval timer mode

Watchdog timer counter clear. Setting WDTCNTCL = 1 clears the count value

to 0000h. WDTCNTCL is automatically reset.

No action

WDTCNT = 0000h

WDTSSEL

WDTISx

Bit 2

Watchdog timer clock source select

SMCLK

ACLK

Bits

1-0

Watchdog timer interval select. These bits select the watchdog timer interval

to set the WDTIFG flag and/or generate a PUC.

00 Watchdog clock source /32768

01 Watchdog clock source /8192

10 Watchdog clock source /512

11 Watchdog clock source /64

10-8

Watchdog Timer

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Watchdog Timer Registers

IE1, Interrupt Enable Register 1

NMIIE

rw−0

WDTIE

rw−0

Bits

7-5

These bits may be used by other modules. See device-specific datasheet.

NMIIE

Bit 4

NMI interrupt enable. This bit enables the NMI interrupt. Because other bits

in IE1 may be used for other modules, it is recommended to set or clear this

bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B

instructions.

Interrupt not enabled

Interrupt enabled

Bits

3-1

These bits may be used by other modules. See device-specific datasheet.

WDTIE

Bit 0

Watchdog timer interrupt enable. This bit enables the WDTIFG interrupt for

interval timer mode. It is not necessary to set this bit for watchdog mode.

Because other bits in IE1 may be used for other modules, it is recommended

to set or clear this bit using BIS.Bor BIC.Binstructions, rather than MOV.B

or CLR.Binstructions.

Interrupt not enabled

Interrupt enabled

Watchdog Timer

10-9

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Watchdog Timer Registers

IFG1, Interrupt Flag Register 1

NMIIFG

rw−(0)

WDTIFG

rw−(0)

Bits

7-5

These bits may be used by other modules. See device-specific datasheet.

NMIIFG

Bit 4

NMI interrupt flag. NMIIFG must be reset by software. Because other bits in

IFG1 may be used for other modules, it is recommended to clear NMIIFG by

using BIS.Bor BIC.Binstructions, rather than MOV.Bor CLR.Binstructions.

No interrupt pending

Interrupt pending

Bits

3-1

These bits may be used by other modules. See device-specific datasheet.

WDTIFG

Bit 0

Watchdog timer interrupt flag. In watchdog mode, WDTIFG remains set until

reset by software. In interval mode, WDTIFG is reset automatically by

servicing the interrupt, or can be reset by software. Because other bits in IFG1

may be used for other modules, it is recommended to clear WDTIFG by using

BIS.Bor BIC.Binstructions, rather than MOV.Bor CLR.Binstructions.

No interrupt pending

Interrupt pending

10-10

Watchdog Timer

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Chapter 11

Timer_A

Timer_A is a 16-bit timer/counter with three capture/compare registers. This

chapter describes Timer_A. Timer_A is implemented in all MSP430x1xx

devices.

Topic

Page

11.1 Timer_A Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.2 Timer_A Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

11.3 Timer_A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19

Timer_A

11-1

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Timer_A Introduction

11.1 Timer_A Introduction

Timer_A is a 16-bit timer/counter with three capture/compare registers.

Timer_A can support multiple capture/compares, PWM outputs, and interval

timing. Timer_A also has extensive interrupt capabilities. Interrupts may be

generated from the counter on overflow conditions and from each of the

capture/compare registers.

Timer_A features include:

- Asynchronous 16-bit timer/counter with four operating modes

- Selectable and configurable clock source

- Three configurable capture/compare registers

- Configurable outputs with PWM capability

- Asynchronous input and output latching

- Interrupt vector register for fast decoding of all Timer_A interrupts

The block diagram of Timer_A is shown in Figure 11−1.

Note: Use of the Word Count

Count is used throughout this chapter. It means the counter must be in the

process of counting for the action to take place. If a particular value is directly

written to the counter, then an associated action will not take place.

11-2

Timer_A

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Timer_A Introduction

Figure 11−1. Timer_A Block Diagram

Timer Block

Timer Clock

TASSELx

IDx

MCx

16−bit Timer

TAR

TACLK

ACLK

Divider

1/2/4/8

Count

Mode

EQU0

Clear

SMCLK

INCLK

Set TAIFG

TACLR

CCR0

CCR1

CCR2

CCISx

CMx

logic

Sync

COV

SCS

CCI2A

CCI2B

GND

Capture

Mode

TACCR2

Timer Clock

VCC

Compararator 2

CCI

EQU2

CAP

SCCI

Set TACCR2

CCIFG

OUT

Output

Unit2

Set

OUT2 Signal

EQU0

Timer Clock

POR

Reset

OUTMODx

Timer_A

11-3

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Timer_A Operation

11.2 Timer_A Operation

The Timer_A module is configured with user software. The setup and

operation of Timer_A is discussed in the following sections.

11.2.1 16-Bit Timer Counter

The 16-bit timer/counter register, TAR, increments or decrements (depending

on mode of operation) with each rising edge of the clock signal. TAR can be

read or written with software. Additionally, the timer can generate an interrupt

when it overflows.

TAR may be cleared by setting the TACLR bit. Setting TACLR also clears the

clock divider and count direction for up/down mode.

Note: Modifying Timer_A Registers

It is recommended to stop the timer before modifying its operation (with

exception of the interrupt enable, interrupt flag, and TACLR) to avoid errant

operating conditions.

When the TACLK is asynchronous to the CPU clock, any read from TAR

should occur while the timer is not operating or the results may be

unpredictable. Alternatively, the timer may be read multiple times while

operating, and a majority vote taken in software to determine the correct

reading. Any write to TAR will take effect immediately.

Clock Source Select and Divider

The timer clock TACLK can be sourced from ACLK, SMCLK, or externally via

TACLK or INCLK. The clock source is selected with the TASSELx bits. The

selected clock source may be passed directly to the timer or divided by 2, 4,

or 8, using the IDx bits. The TACLK divider is reset when TACLR is set.

11-4

Timer_A

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Timer_A Operation

11.2.2 Starting the Timer

The timer may be started, or restarted in the following ways:

- The timer counts when MCx > 0 and the clock source is active.

- When the timer mode is either up or up/down, the timer may be stopped

by writing 0 to TACCR0. The timer may then be restarted by writing a

nonzero value to TACCR0. In this scenario, the timer starts incrementing

in the up direction from zero.

11.2.3 Timer Mode Control

The timer has four modes of operation as described in Table 11−1: stop, up,

continuous, and up/down. The operating mode is selected with the MCx bits.

Table 11−1.Timer Modes

MCx

Mode

Stop

Description

The timer is halted.

The timer repeatedly counts from zero to the value of

TACCR0

Continuous The timer repeatedly counts from zero to 0FFFFh.

Up/down

The timer repeatedly counts from zero up to the value of

TACCR0 and back down to zero.

Timer_A

11-5

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Timer_A Operation

Up Mode

The up mode is used if the timer period must be different from 0FFFFh counts.

The timer repeatedly counts up to the value of compare register TACCR0,

which defines the period, as shown in Figure 11−2. The number of timer counts

in the period is TACCR0+1. When the timer value equals TACCR0 the timer

restarts counting from zero. If up mode is selected when the timer value is

greater than TACCR0, the timer immediately restarts counting from zero.

Figure 11−2. Up Mode

0FFFFh

TACCR0

The TACCR0 CCIFG interrupt flag is set when the timer counts to the TACCR0

value. The TAIFG interrupt flag is set when the timer counts from TACCR0 to

zero. Figure 11−3 shows the flag set cycle.

Figure 11−3. Up Mode Flag Setting

Timer Clock

Timer

Set TAIFG

CCR0−1

CCR0

CCR0−1

CCR0

Set TACCR0 CCIFG

Changing the Period Register TACCR0

When changing TACCR0 while the timer is running, if the new period is greater

than or equal to the old period, or greater than the current count value, the timer

counts up to the new period. If the new period is less than the current count

value, the timer rolls to zero. However, one additional count may occur before

the counter rolls to zero.

11-6

Timer_A

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Timer_A Operation

Continuous Mode

In the continuous mode, the timer repeatedly counts up to 0FFFFh and restarts

from zero as shown in Figure 11−4. The capture/compare register TACCR0

works the same way as the other capture/compare registers.

Figure 11−4. Continuous Mode

0FFFFh

The TAIFG interrupt flag is set when the timer counts from 0FFFFh to zero.

Figure 11−5 shows the flag set cycle.

Figure 11−5. Continuous Mode Flag Setting

Timer Clock

Timer

FFFEh

FFFFh

FFFEh

FFFFh

Set TAIFG

Timer_A

11-7

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Timer_A Operation

Use of the Continuous Mode

The continuous mode can be used to generate independent time intervals and

output frequencies. Each time an interval is completed, an interrupt is

generated. The next time interval is added to the TACCRx register in the

interrupt service routine. Figure 11−6 shows two separate time intervals t and

t being added to the capture/compare registers. In this usage, the time

interval is controlled by hardware, not software, without impact from interrupt

latency. Up to three independent time intervals or output frequencies can be

generated using all three capture/compare registers.

Figure 11−6. Continuous Mode Time Intervals

TACCR1b

TACCR0b

TACCR1c

TACCR0c

TACCR0d

TACCR1d

0FFFFh

TACCR1a

TACCR0a

Time intervals can be produced with other modes as well, where TACCR0 is

used as the period register. Their handling is more complex since the sum of

the old TACCRx data and the new period can be higher than the TACCR0

value. When the previous TACCRx value plus t is greater than the TACCR0

data, the TACCR0 value must be subtracted to obtain the correct time interval.

11-8

Timer_A

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Timer_A Operation

Up/Down Mode

The up/down mode is used if the timer period must be different from 0FFFFh

counts, and if symmetrical pulse generation is needed. The timer repeatedly

counts up to the value of compare register TACCR0 and back down to zero,

as shown in Figure 11−7. The period is twice the value in TACCR0.

Figure 11−7. Up/Down Mode

0FFFFh

TACCR0

The count direction is latched. This allows the timer to be stopped and then

restarted in the same direction it was counting before it was stopped. If this is

not desired, the TACLR bit must be set to clear the direction. The TACLR bit

also clears the TAR value and the TACLK divider.

In up/down mode, the TACCR0 CCIFG interrupt flag and the TAIFG interrupt

flag are set only once during a period, separated by 1/2 the timer period. The

TACCR0 CCIFG interrupt flag is set when the timer counts from TACCR0−1

to TACCR0, and TAIFG is set when the timer completes counting down from

0001h to 0000h. Figure 11−8 shows the flag set cycle.

Figure 11−8. Up/Down Mode Flag Setting

Timer Clock

Timer

CCR0−1

CCR0

CCR0−1 CCR0−2

Up/Down

Set TAIFG

Set TACCR0 CCIFG

Timer_A

11-9

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Timer_A Operation

Changing the Period Register TACCR0

When changing TACCR0 while the timer is running, and counting in the down

direction, the timer continues its descent until it reaches zero. The new period

takes affect after the counter counts down to zero.

When the timer is counting in the up direction, and the new period is greater

than or equal to the old period, or greater than the current count value, the timer

counts up to the new period before counting down. When the timer is counting

in the up direction, and the new period is less than the current count value, the

timer begins counting down. However, one additional count may occur before

the counter begins counting down.

Use of the Up/Down Mode

The up/down mode supports applications that require dead times between

output signals (See section Timer_A Output Unit). For example, to avoid

overload conditions, two outputs driving an H-bridge must never be in a high

state simultaneously. In the example shown in Figure 11−9 the t

is:

dead

= t

× (TACCR1 − TACCR2)

dead

timer

With:

Time during which both outputs need to be inactive

Cycle time of the timer clock

TACCRx Content of capture/compare register x

The TACCRx registers are not buffered. They update immediately when

written to. Therefore, any required dead time will not be maintained

automatically.

Figure 11−9. Output Unit in Up/Down Mode

0FFFFh

TACCR0

TACCR1

TACCR2

Dead Time

Output Mode 6: Toggle/Set

Output Mode 2: Toggle/Reset

Interrupt Events

EQU1

TAIFG

EQU2

TAIFG

EQU2 EQU2

EQU0

EQU2

11-10

Timer_A

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Timer_A Operation

11.2.4 Capture/Compare Blocks

Three identical capture/compare blocks, TACCRx, are present in Timer_A.

Any of the blocks may be used to capture the timer data, or to generate time

intervals.

Capture Mode

The capture mode is selected when CAP = 1. Capture mode is used to record

time events. It can be used for speed computations or time measurements.

The capture inputs CCIxA and CCIxB are connected to external pins or internal

signals and are selected with the CCISx bits. The CMx bits select the capture

edge of the input signal as rising, falling, or both. A capture occurs on the

selected edge of the input signal. If a capture occurs:

- The timer value is copied into the TACCRx register

- The interrupt flag CCIFG is set

The input signal level can be read at any time via the CCI bit. MSP430x1xx

family devices may have different signals connected to CCIxA and CCIxB.

Refer to the device-specific datasheet for the connections of these signals.

The capture signal can be asynchronous to the timer clock and cause a race

condition. Setting the SCS bit will synchronize the capture with the next timer

clock. Setting the SCS bit to synchronize the capture signal with the timer clock

is recommended. This is illustrated in Figure 11−10.

Figure 11−10.Capture Signal (SCS=1)

Timer Clock

Timer

CCI

n−2

n−1

n+1

n+2

n+3

n+4

Capture

Set TACCRx CCIFG

Overflow logic is provided in each capture/compare register to indicate if a

second capture was performed before the value from the first capture was

read. Bit COV is set when this occurs as shown in Figure 11−11. COV must

be reset with software.

Timer_A

11-11

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Timer_A Operation

Figure 11−11.Capture Cycle

Idle

Capture

Capture Read

Capture

Taken

Read

Taken

Capture

Taken

Capture

Capture Read and No Capture

Capture

Clear Bit COV

in Register TACCTLx

Second

Capture

Taken

Idle

COV = 1

Capture Initiated by Software

Captures can be initiated by software. The CMx bits can be set for capture on

both edges. Software then sets CCIS1 = 1 and toggles bit CCIS0 to switch the

capture signal between V

changes state:

and GND, initiating a capture each time CCIS0

MOV #CAP+SCS+CCIS1+CM_3,&TACCTLx; Setup TACCTLx

XOR #CCIS0,&TACCTLx ; TACCTLx = TAR

Compare Mode

The compare mode is selected when CAP = 0. The compare mode is used to

generate PWM output signals or interrupts at specific time intervals. When

TAR counts to the value in a TACCRx:

- Interrupt flag CCIFG is set

- Internal signal EQUx = 1

- EQUx affects the output according to the output mode

- The input signal CCI is latched into SCCI

11-12

Timer_A

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Timer_A Operation

11.2.5 Output Unit

Output Modes

Each capture/compare block contains an output unit. The output unit is used

to generate output signals such as PWM signals. Each output unit has eight

operating modes that generate signals based on the EQU0 and EQUx signals.

The output modes are defined by the OUTMODx bits and are described in

Table 11−2. The OUTx signal is changed with the rising edge of the timer clock

for all modes except mode 0. Output modes 2, 3, 6, and 7 are not useful for

output unit 0 because EQUx = EQU0.

Table 11−2.Output Modes

OUTMODx

Mode

Description

000

Output

The output signal OUTx is defined by the

OUTx bit. The OUTx signal updates

immediately when OUTx is updated.

001

Set

The output is set when the timer counts

to the TACCRx value. It remains set until

a reset of the timer, or until another

output mode is selected and affects the

output.

010

Toggle/Reset The output is toggled when the timer

counts to the TACCRx value. It is reset

when the timer counts to the TACCR0

value.

011

100

101

Set/Reset

The output is set when the timer counts

to the TACCRx value. It is reset when the

timer counts to the TACCR0 value.

Toggle

The output is toggled when the timer

counts to the TACCRx value. The output

period is double the timer period.

Reset

The output is reset when the timer counts

to the TACCRx value. It remains reset

until another output mode is selected and

affects the output.

110

111

Toggle/Set

Reset/Set

The output is toggled when the timer

counts to the TACCRx value. It is set

when the timer counts to the TACCR0

value.

The output is reset when the timer counts

to the TACCRx value. It is set when the

timer counts to the TACCR0 value.

Timer_A

11-13

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Timer_A Operation

Output Example—Timer in Up Mode

The OUTx signal is changed when the timer counts up to the TACCRx value,

and rolls from TACCR0 to zero, depending on the output mode. An example

is shown in Figure 11−12 using TACCR0 and TACCR1.

Figure 11−12.Output Example—Timer in Up Mode

0FFFFh

TACCR0

TACCR1

Output Mode 1: Set

Output Mode 2: Toggle/Reset

Output Mode 3: Set/Reset

Output Mode 4: Toggle

Output Mode 5: Reset

Output Mode 6: Toggle/Set

Output Mode 7: Reset/Set

EQU0

TAIFG

EQU1

EQU0

TAIFG

EQU1

EQU0

TAIFG

Interrupt Events

11-14

Timer_A

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Timer_A Operation

Output Example—Timer in Continuous Mode

The OUTx signal is changed when the timer reaches the TACCRx and

TACCR0 values, depending on the output mode. An example is shown in

Figure 11−13 using TACCR0 and TACCR1.

Figure 11−13.Output Example—Timer in Continuous Mode

0FFFFh

TACCR0

TACCR1

Output Mode 1: Set

Output Mode 2: Toggle/Reset

Output Mode 3: Set/Reset

Output Mode 4: Toggle

Output Mode 5: Reset

Output Mode 6: Toggle/Set

Output Mode 7: Reset/Set

Interrupt Events

TAIFG EQU1 EQU0 TAIFG EQU1 EQU0

Timer_A

11-15

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Timer_A Operation

Output Example—Timer in Up/Down Mode

The OUTx signal changes when the timer equals TACCRx in either count

direction and when the timer equals TACCR0, depending on the output mode.

An example is shown in Figure 11−14 using TACCR0 and TACCR2.

Figure 11−14.Output Example—Timer in Up/Down Mode

0FFFFh

TACCR0

TACCR2

Output Mode 1: Set

Output Mode 2: Toggle/Reset

Output Mode 3: Set/Reset

Output Mode 4: Toggle

Output Mode 5: Reset

Output Mode 6: Toggle/Set

Output Mode 7: Reset/Set

Interrupt Events

EQU2

TAIFG EQU0

EQU2

TAIFG

EQU0

Note: Switching Between Output Modes

When switching between output modes, one of the OUTMODx bits should

remain set during the transition, unless switching to mode 0. Otherwise,

output glitching can occur because a NOR gate decodes output mode 0. A

safe method for switching between output modes is to use output mode 7 as

a transition state:

BIS #OUTMOD_7,&TACCTLx ; Set output mode=7

BIC #OUTMODx,&TACCTLx ; Clear unwanted bits

11-16

Timer_A

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Timer_A Operation

11.2.6 Timer_A Interrupts

Two interrupt vectors are associated with the 16-bit Timer_A module:

- TACCR0 interrupt vector for TACCR0 CCIFG

- TAIV interrupt vector for all other CCIFG flags and TAIFG

In capture mode any CCIFG flag is set when a timer value is captured in the

associated TACCRx register. In compare mode, any CCIFG flag is set if TAR

counts to the associated TACCRx value. Software may also set or clear any

CCIFG flag. All CCIFG flags request an interrupt when their corresponding

CCIE bit and the GIE bit are set.

TACCR0 Interrupt

The TACCR0 CCIFG flag has the highest Timer_A interrupt priority and has

a dedicated interrupt vector as shown in Figure 11−15. The TACCR0 CCIFG

flag is automatically reset when the TACCR0 interrupt request is serviced.

Figure 11−15.Capture/Compare TACCR0 Interrupt Flag

Capture

CCIE

Set

EQU0

CAP

IRQ, Interrupt Service Requested

IRACC, Interrupt Request Accepted

Timer Clock

Reset

POR

TAIV, Interrupt Vector Generator

The TACCR1 CCIFG, TACCR2 CCIFG, and TAIFG flags are prioritized and

combined to source a single interrupt vector. The interrupt vector register TAIV

is used to determine which flag requested an interrupt.

The highest priority enabled interrupt generates a number in the TAIV register

(see register description). This number can be evaluated or added to the

program counter to automatically enter the appropriate software routine.

Disabled Timer_A interrupts do not affect the TAIV value.

Any access, read or write, of the TAIV register automatically resets the highest

pending interrupt flag. If another interrupt flag is set, another interrupt is

immediately generated after servicing the initial interrupt. For example, if the

TACCR1 and TACCR2 CCIFG flags are set when the interrupt service routine

accesses the TAIV register, TACCR1 CCIFG is reset automatically. After the

RETI instruction of the interrupt service routine is executed, the TACCR2

CCIFG flag will generate another interrupt.

Timer_A

11-17

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Timer_A Operation

TAIV Software Example

The following software example shows the recommended use of TAIV and the

handling overhead. The TAIV value is added to the PC to automatically jump

to the appropriate routine.

The numbers at the right margin show the necessary CPU cycles for each

instruction. The software overhead for different interrupt sources includes

interrupt latency and return-from-interrupt cycles, but not the task handling

itself. The latencies are:

- Capture/compare block TACCR0

- Capture/compare blocks TACCR1, TACCR2

- Timer overflow TAIFG

11 cycles

16 cycles

14 cycles

; Interrupt handler for TACCR0 CCIFG.

CCIFG_0_HND

Cycles

;

...

; Start of handler Interrupt latency 6

RETI

; Interrupt handler for TAIFG, TACCR1 and TACCR2 CCIFG.

TA_HND

...

; Interrupt latency

ADD &TAIV,PC

RETI

; Add offset to Jump table ā3

; Vector 0: No interrupt

JMP CCIFG_1_HND ; Vector 2: TACCR1

JMP CCIFG_2_HND ; Vector 4: TACCR2

RETI

; Vector 6: Reserved

; Vector 8: Reserved

TAIFG_HND

; Vector 10: TAIFG Flag

; Task starts here

...

RETI

CCIFG_2_HND

...

RETI

; Vector 4: TACCR2

; Task starts here

; Back to main program

CCIFG_1_HND

; Vector 2: TACCR1

; Task starts here

; Back to main program

...

RETI

11-18

Timer_A

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Timer_A Registers

11.3 Timer_A Registers

The Timer_A registers are listed in Table 11−3:

Table 11−3.Timer_A Registers

Short Form

TACTL

Initial State

Timer_A control

Read/write

Read only

0160h

0170h

0162h

0172h

0164h

0174h

0166h

0176h

012Eh

Reset with POR

Timer_A counter

TAR

Timer_A capture/compare control 0

Timer_A capture/compare 0

Timer_A capture/compare control 1

Timer_A capture/compare 1

Timer_A capture/compare control 2

Timer_A capture/compare 2

Timer_A interrupt vector

TACCTL0

TACCR0

TACCTL1

TACCR1

TACCTL2

TACCR2

TAIV

Timer_A

11-19

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Timer_A Registers

TACTL, Timer_A Control Register

Unused

TASSELx

rw−(0)

IDx

MCx

Unused

rw−(0)

TACLR

w−(0)

TAIE

rw−(0)

TAIFG

rw−(0)

Unused

Bits

Unused

15-10

TASSELx

Bits

9-8

Timer_A clock source select

00 TACLK

01 ACLK

10 SMCLK

11 INCLK

IDx

Bits

7-6

Input divider. These bits select the divider for the input clock.

00 /1

01 /2

10 /4

11 /8

MCx

Bits

5-4

Mode control. Setting MCx = 00h when Timer_A is not in use conserves

power.

00 Stop mode: the timer is halted

01 Up mode: the timer counts up to TACCR0

10 Continuous mode: the timer counts up to 0FFFFh

11 Up/down mode: the timer counts up to TACCR0 then down to 0000h

Unused

TACLR

Bit 3

Bit 2

Unused

Timer_A clear. Setting this bit resets TAR, the TACLK divider, and the count

direction. The TACLR bit is automatically reset and is always read as zero.

TAIE

Bit 1

Bit 0

Timer_A interrupt enable. This bit enables the TAIFG interrupt request.

Interrupt disabled

Interrupt enabled

TAIFG

Timer_A interrupt flag

No interrupt pending

Interrupt pending

11-20

Timer_A

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Timer_A Registers

TAR, Timer_A Register

TARx

rw−(0)

TARx

Bits

15-0

Timer_A register. The TAR register is the count of Timer_A.

Timer_A

11-21

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Timer_A Registers

TACCTLx, Capture/Compare Control Register

CMx

CCISx

SCS

SCCI

r−(0)

Unused

r−(0)

CAP

rw−(0)

CCI

OUTMODx

CCIE

rw−(0)

OUT

rw−(0)

COV

rw−(0)

CCIFG

rw−(0)

CMx

Bit

Capture mode

15-14

00 No capture

01 Capture on rising edge

10 Capture on falling edge

11 Capture on both rising and falling edges

CCISx

Bit

Capture/compare input select. These bits select the TACCRx input signal.

13-12

See the device-specific datasheet for specific signal connections.

00 CCIxA

01 CCIxB

10 GND

SCS

Bit 11

Bit 10

Synchronize capture source. This bit is used to synchronize the capture input

signal with the timer clock.

Asynchronous capture

Synchronous capture

SCCI

Synchronized capture/compare input. The selected CCI input signal is

latched with the EQUx signal and can be read via this bit

Unused

CAP

Bit 9

Bit 8

Unused. Read only. Always read as 0.

Capture mode

Compare mode

Capture mode

OUTMODx

Bits

7-5

Output mode. Modes 2, 3, 6, and 7 are not useful for TACCR0 because EQUx

= EQU0.

000 OUT bit value

001 Set

010 Toggle/reset

011 Set/reset

100 Toggle

101 Reset

110 Toggle/set

111 Reset/set

11-22

Timer_A

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Timer_A Registers

CCIE

Bit 4

Capture/compare interrupt enable. This bit enables the interrupt request of

the corresponding CCIFG flag.

Interrupt disabled

Interrupt enabled

CCI

Bit 3

Bit 2

Capture/compare input. The selected input signal can be read by this bit.

Output. For output mode 0, this bit directly controls the state of the output.

OUT

Output low

Output high

COV

Bit 1

Bit 0

Capture overflow. This bit indicates a capture overflow occurred. COV must

be reset with software.

No capture overflow occurred

Capture overflow occurred

CCIFG

Capture/compare interrupt flag

No interrupt pending

Interrupt pending

TAIV, Timer_A Interrupt Vector Register

TAIVx

r−(0)

TAIVx

Bits

15-0

Timer_A Interrupt Vector value

Interrupt

Priority

TAIV Contents

Interrupt Source

Interrupt Flag

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

No interrupt pending

Capture/compare 1

Capture/compare 2

Reserved

−

TACCR1 CCIFG

Highest

TACCR2 CCIFG

−

Reserved

−

Timer overflow

Reserved

TAIFG

−

Reserved

Lowest

Timer_A

11-23

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11-24

Timer_A

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Chapter 12

Timer_B

Timer_B is a 16-bit timer/counter with multiple capture/compare registers. This

chapter describes Timer_B. Timer_B3 (three capture/compare registers) is

implemented in MSP430x13x and MSP430x15x devices. Timer_B7 (seven

capture/compare registers) is implemented in MSP430x14x and

MSP430x16x devices.

Topic

Page

12.1 Timer_B Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

12.2 Timer_B Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

12.3 Timer_B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20

Timer_B

12-1

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Timer_B Introduction

12.1 Timer_B Introduction

Timer_B is a 16-bit timer/counter with three or seven capture/compare

registers. Timer_B can support multiple capture/compares, PWM outputs, and

interval timing. Timer_B also has extensive interrupt capabilities. Interrupts

may be generated from the counter on overflow conditions and from each of

the capture/compare registers.

Timer_B features include :

- Asynchronous 16-bit timer/counter with four operating modes and four

selectable lengths

- Selectable and configurable clock source

- Three or seven configurable capture/compare registers

- Configurable outputs with PWM capability

- Double-buffered compare latches with synchronized loading

- Interrupt vector register for fast decoding of all Timer_B interrupts

The block diagram of Timer_B is shown in Figure 12−1.

Note: Use of the Word Count

Count is used throughout this chapter. It means the counter must be in the

process of counting for the action to take place. If a particular value is directly

written to the counter, then an associated action does not take place.

12.1.1 Similarities and Differences From Timer_A

Timer_B is identical to Timer_A with the following exceptions:

The length of Timer_B is programmable to be 8, 10, 12, or 16 bits.

- Timer_B TBCCRx registers are double-buffered and can be grouped.

- All Timer_B outputs can be put into a high-impedance state.

- The SCCI bit function is not implemented in Timer_B.

12-2

Timer_B

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Timer_B Introduction

Figure 12−1. Timer_B Block Diagram

Timer Block

Timer Clock

TBSSELx

IDx

MCx

16−bit Timer

TBR

TBCLK

ACLK

Divider

1/2/4/8

Count

Mode

10 12 16

EQU0

Clear

SMCLK

CNTLx

TBCLR

TBCLGRPx

Set TBIFG

Group

Load Logic

CCR0

CCR1

CCR2

CCR3

CCR4

CCR5

CCR6

CCISx

CMx

logic

Sync

COV

SCS

CCI6A

Capture

Mode

CCI6B

GND

VCC

TBCCR6

Timer Clock

CLLDx

Load

Group

Load Logic

CCI

VCC

Compare Latch TBCL6

Compararator 6

TBR=0

EQU0

UP/DOWN

CCR5

EQU6

CAP

CCR4

CCR1

Set TBCCR6

CCIFG

OUT

Output

Unit6

Set

OUT6 Signal

EQU0

Timer Clock

POR

Reset

OUTMODx

Timer_B

12-3

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Timer_B Operation

12.2 Timer_B Operation

The Timer_B module is configured with user software. The setup and

operation of Timer_B is discussed in the following sections.

12.2.1 16-Bit Timer Counter

The 16-bit timer/counter register, TBR, increments or decrements (depending

on mode of operation) with each rising edge of the clock signal. TBR can be

read or written with software. Additionally, the timer can generate an interrupt

when it overflows.

TBR may be cleared by setting the TBCLR bit. Setting TBCLR also clears the

clock divider and count direction for up/down mode.

Note: Modifying Timer_B Registers

It is recommended to stop the timer before modifying its operation (with

exception of the interrupt enable, interrupt flag, and TBCLR) to avoid errant

operating conditions.

When the TBCLK is asynchronous to the CPU clock, any read from TBR

should occur while the timer is not operating or the results may be

unpredictable. Alternatively, the timer may be read multiple times while

operating, and a majority vote taken in software to determine the correct

reading. Any write to TBR will take effect immediately.

TBR Length

Timer_B is configurable to operate as an 8-, 10-, 12-, or 16-bit timer with the

CNTLx bits. The maximum count value, TBR

, for the selectable lengths

(max)

is 0FFh, 03FFh, 0FFFh, and 0FFFFh, respectively. Data written to the TBR

Clock Source Select and Divider

The timer clock TBCLK can be sourced from ACLK, SMCLK, or externally via

TBCLK or INCLK. The clock source is selected with the TBSSELx bits. The

selected clock source may be passed directly to the timer or divided by 2,4,

or 8, using the IDx bits. The TBCLK divider is reset when TBCLR is set.

12-4

Timer_B

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Timer_B Operation

12.2.2 Starting the Timer

The timer may be started or restarted in the following ways:

- The timer counts when MCx > 0 and the clock source is active.

- When the timer mode is either up or up/down, the timer may be stopped

by loading 0 to TBCL0. The timer may then be restarted by loading a

nonzero value to TBCL0. In this scenario, the timer starts incrementing in

the up direction from zero.

12.2.3 Timer Mode Control

The timer has four modes of operation as described in Table 12−1: stop, up,

continuous, and up/down. The operating mode is selected with the MCx bits.

Table 12−1.Timer Modes

MCx

Mode

Stop

Description

The timer is halted.

The timer repeatedly counts from zero to the value of

compare register TBCL0.

Continuous The timer repeatedly counts from zero to the value se-

lected by the TBCNTLx bits.

Up/down

The timer repeatedly counts from zero up to the value of

TBCL0 and then back down to zero.

Timer_B

12-5

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Timer_B Operation

Up Mode

The up mode is used if the timer period must be different from TBR

counts.

(max)

The timer repeatedly counts up to the value of compare latch TBCL0, which

defines the period, as shown in Figure 12−2. The number of timer counts in

the period is TBCL0+1. When the timer value equals TBCL0 the timer restarts

counting from zero. If up mode is selected when the timer value is greater than

TBCL0, the timer immediately restarts counting from zero.

Figure 12−2. Up Mode

TBR

(max)

TBCL0

The TBCCR0 CCIFG interrupt flag is set when the timer counts to the TBCL0

value. The TBIFG interrupt flag is set when the timer counts from TBCL0 to

zero. Figure 11−3 shows the flag set cycle.

Figure 12−3. Up Mode Flag Setting

Timer Clock

Timer

Set TBIFG

TBCL0−1 TBCL0

Set TBCCR0 CCIFG

Changing the Period Register TBCL0

When changing TBCL0 while the timer is running and when the TBCL0 load

mode is immediate, if the new period is greater than or equal to the old period,

or greater than the current count value, the timer counts up to the new period.

If the new period is less than the current count value, the timer rolls to zero.

However, one additional count may occur before the counter rolls to zero.

12-6

Timer_B

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Timer_B Operation

Continuous Mode

In continuous mode the timer repeatedly counts up to TBR

and restarts

(max)

from zero as shown in Figure 12−4. The compare latch TBCL0 works the same

way as the other capture/compare registers.

Figure 12−4. Continuous Mode

TBR

(max)

The TBIFG interrupt flag is set when the timer counts from TBR

to zero.

(max)

Figure 12−5 shows the flag set cycle.

Figure 12−5. Continuous Mode Flag Setting

Timer Clock

Timer

TBR

−1 TBR

(max)

TBR

−1 TBR

(max)

Set TBIFG

Timer_B

12-7

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Timer_B Operation

Use of the Continuous Mode

The continuous mode can be used to generate independent time intervals and

output frequencies. Each time an interval is completed, an interrupt is

generated. The next time interval is added to the TBCLx latch in the interrupt

service routine. Figure 12−6 shows two separate time intervals t and t being

added to the capture/compare registers. The time interval is controlled by

hardware, not software, without impact from interrupt latency. Up to three

(Timer_B3) or 7 (Timer_B7) independent time intervals or output frequencies

can be generated using capture/compare registers.

Figure 12−6. Continuous Mode Time Intervals

TBCL1b

TBCL0b

TBCL1c

TBCL0c

TBCL0d

TBCL1d

TBR

(max)

TBCL1a

TBCL0a

EQU0 Interrupt

EQU1 Interrupt

Time intervals can be produced with other modes as well, where TBCL0 is

used as the period register. Their handling is more complex since the sum of

the old TBCLx data and the new period can be higher than the TBCL0 value.

When the sum of the previous TBCLx value plus t is greater than the TBCL0

data, the old TBCL0 value must be subtracted to obtain the correct time

interval.

12-8

Timer_B

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Timer_B Operation

Up/Down Mode

The up/down mode is used if the timer period must be different from TBR

(max)

counts, and if symmetrical pulse generation is needed. The timer repeatedly

counts up to the value of compare latch TBCL0, and back down to zero, as

shown in Figure 12−7. The period is twice the value in TBCL0.

Note: TBCL0 > TBR(max)

If TBCL0 > TBR

continuous mode. It does not count down from TBR

the counter operates as if it were configured for

(max),

to zero.

(max)

Figure 12−7. Up/Down Mode

TBCL0

The count direction is latched. This allows the timer to be stopped and then

restarted in the same direction it was counting before it was stopped. If this is

not desired, the TBCLR bit must be used to clear the direction. The TBCLR bit

also clears the TBR value and the TBCLK divider.

In up/down mode, the TBCCR0 CCIFG interrupt flag and the TBIFG interrupt

flag are set only once during the period, separated by 1/2 the timer period. The

TBCCR0 CCIFG interrupt flag is set when the timer counts from TBCL0−1 to

TBCL0, and TBIFG is set when the timer completes counting down from 0001h

to 0000h. Figure 12−8 shows the flag set cycle.

Figure 12−8. Up/Down Mode Flag Setting

Timer Clock

Timer

TBCL0−1 TBCL0

TBCL0−1 TBCL0−2

Up/Down

Set TBIFG

Set TBCCR0 CCIFG

Timer_B

12-9

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Timer_B Operation

Changing the Value of Period Register TBCL0

When changing TBCL0 while the timer is running, and counting in the down

direction, and when the TBCL0 load mode is immediate, the timer continues

its descent until it reaches zero. The new period takes effect after the counter

counts down to zero.

If the timer is counting in the up direction when the new period is latched into

TBCL0, and the new period is greater than or equal to the old period, or greater

than the current count value, the timer counts up to the new period before

counting down. When the timer is counting in the up direction, and the new

period is less than the current count value when TBCL0 is loaded, the timer

begins counting down. However, one additional count may occur before the

counter begins counting down.

Use of the Up/Down Mode

The up/down mode supports applications that require dead times between

output signals (see section Timer_B Output Unit). For example, to avoid

overload conditions, two outputs driving an H-bridge must never be in a high

state simultaneously. In the example shown in Figure 12−9 the t

is:

dead

= t

× (TBCL1 − TBCL3)

dead

timer

With:

Time during which both outputs need to be inactive

Cycle time of the timer clock

TBCLx Content of compare latch x

The ability to simultaneously load grouped compare latches assures the dead

times.

Figure 12−9. Output Unit in Up/Down Mode

TBR

(max)

TBCL0

TBCL1

TBCL3

Dead Time

Output Mode 6: Toggle/Set

Output Mode 2: Toggle/Reset

Interrupt Events

EQU1

TBIFG

EQU3

TBIFG

EQU3 EQU3

EQU0

EQU3

12-10

Timer_B

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Timer_B Operation

12.2.4 Capture/Compare Blocks

Three or seven identical capture/compare blocks, TBCCRx, are present in

Timer_B. Any of the blocks may be used to capture the timer data or to

generate time intervals.

Capture Mode

The capture mode is selected when CAP = 1. Capture mode is used to record

time events. It can be used for speed computations or time measurements.

The capture inputs CCIxA and CCIxB are connected to external pins or internal

signals and are selected with the CCISx bits. The CMx bits select the capture

edge of the input signal as rising, falling, or both. A capture occurs on the

selected edge of the input signal. If a capture is performed:

- The timer value is copied into the TBCCRx register

- The interrupt flag CCIFG is set

The input signal level can be read at any time via the CCI bit. MSP430x1xx

family devices may have different signals connected to CCIxA and CCIxB.

Refer to the device-specific datasheet for the connections of these signals.

The capture signal can be asynchronous to the timer clock and cause a race

condition. Setting the SCS bit will synchronize the capture with the next timer

clock. Setting the SCS bit to synchronize the capture signal with the timer clock

is recommended. This is illustrated in Figure 12−10.

Figure 12−10. Capture Signal (SCS=1)

Timer Clock

Timer

CCI

n−2

n−1

n+1

n+2

n+3

n+4

Capture

Set TBCCRx CCIFG

Overflow logic is provided in each capture/compare register to indicate if a

second capture was performed before the value from the first capture was

read. Bit COV is set when this occurs as shown in Figure 12−11. COV must

be reset with software.

Timer_B

12-11

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Timer_B Operation

Figure 12−11.Capture Cycle

Idle

Capture

Capture Read

Capture

Taken

Read

Taken

Capture

Taken

Capture

Capture Read and No Capture

Capture

Clear Bit COV

in Register TBCCTLx

Second

Capture

Taken

Idle

COV = 1

Capture Initiated by Software

Captures can be initiated by software. The CMx bits can be set for capture on

both edges. Software then sets bit CCIS1=1 and toggles bit CCIS0 to switch

the capture signal between V

CCIS0 changes state:

and GND, initiating a capture each time

MOV #CAP+SCS+CCIS1+CM_3,&TBCCTLx; Setup TBCCTLx

XOR #CCIS0,&TBCCTLx ; TBCCTLx = TBR

Compare Mode

The compare mode is selected when CAP = 0. Compare mode is used to

generate PWM output signals or interrupts at specific time intervals. When

TBR counts to the value in a TBCLx:

- Interrupt flag CCIFG is set

- Internal signal EQUx = 1

- EQUx affects the output according to the output mode

12-12

Timer_B

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Timer_B Operation

Compare Latch TBCLx

The TBCCRx compare latch, TBCLx, holds the data for the comparison to the

timer value in compare mode. TBCLx is buffered by TBCCRx. The buffered

compare latch gives the user control over when a compare period updates.

The user cannot directly access TBCLx. Compare data is written to each

TBCCRx and automatically transferred to TBCLx. The timing of the transfer

from TBCCRx to TBCLx is user-selectable with the CLLDx bits as described

in Table 12−2.

Table 12−2.TBCLx Load Events

CLLDx

Description

New data is transferred from TBCCRx to TBCLx immediately when

TBCCRx is written to.

New data is transferred from TBCCRx to TBCLx when TBR counts to 0

for up and continuous modes. New data is transferred to from TBCCRx

to TBCLx when TBR counts to the old TBCL0 value or to 0 for up/down

mode

New data is transferred from TBCCRx to TBCLx when TBR

counts to the old TBCLx value.

Grouping Compare Latches

Multiple compare latches may be grouped together for simultaneous updates

with the TBCLGRPx bits. When using groups, the CLLDx bits of the lowest

numbered TBCCRx in the group determine the load event for each compare

latch of the group, except when TBCLGRP = 3, as shown in Table 12−3. The

CLLDx bits of the controlling TBCCRx must not be set to zero. When the

CLLDx bits of the controlling TBCCRx are set to zero, all compare latches

update immediately when their corresponding TBCCRx is written - no

compare latches are grouped.

Two conditions must exist for the compare latches to be loaded when grouped.

First, all TBCCRx registers of the group must be updated, even when new

TBCCRx data = old TBCCRx data. Second, the load event must occur.

Table 12−3.Compare Latch Operating Modes

TBCLGRPx

Grouping

Update Control

None

Individual

TBCL1+TBCL2

TBCL3+TBCL4

TBCL5+TBCL6

TBCCR1

TBCCR3

TBCCR5

TBCL1+TBCL2+TBCL3

TBCL4+TBCL5+TBCL6

TBCCR1

TBCCR4

TBCL0+TBCL1+TBCL2+

TBCCR1

TBCL3+TBCL4+TBCL5+TBCL6

Timer_B

12-13

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Timer_B Operation

12.2.5 Output Unit

Each capture/compare block contains an output unit. The output unit is used

to generate output signals such as PWM signals. Each output unit has eight

operating modes that generate signals based on the EQU0 and EQUx signals.

The TBOUTH pin function can be used to put all Timer_B outputs into a

high-impedance state. When the TBOUTH pin function is selected for the pin,

and when the pin is pulled high, all Timer_B outputs are in a high-impedance

state.

Output Modes

The output modes are defined by the OUTMODx bits and are described in

Table 12−4. The OUTx signal is changed with the rising edge of the timer clock

for all modes except mode 0. Output modes 2, 3, 6, and 7 are not useful for

output unit 0 because EQUx = EQU0.

Table 12−4.Output Modes

OUTMODx

Mode

Description

000

Output

The output signal OUTx is defined by the

OUTx bit. The OUTx signal updates

immediately when OUTx is updated.

001

Set

The output is set when the timer counts

to the TBCLx value. It remains set until a

reset of the timer, or until another output

mode is selected and affects the output.

010

Toggle/Reset The output is toggled when the timer

counts to the TBCLx value. It is reset

when the timer counts to the TBCL0

value.

011

100

101

Set/Reset

The output is set when the timer counts

to the TBCLx value. It is reset when the

timer counts to the TBCL0 value.

Toggle

The output is toggled when the timer

counts to the TBCLx value. The output

period is double the timer period.

Reset

The output is reset when the timer counts

to the TBCLx value. It remains reset until

another output mode is selected and

affects the output.

110

111

Toggle/Set

Reset/Set

The output is toggled when the timer

counts to the TBCLx value. It is set when

the timer counts to the TBCL0 value.

The output is reset when the timer counts

to the TBCLx value. It is set when the

timer counts to the TBCL0 value.

12-14

Timer_B

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Timer_B Operation

Output Example—Timer in Up Mode

The OUTx signal is changed when the timer counts up to the TBCLx value, and

rolls from TBCL0 to zero, depending on the output mode. An example is shown

in Figure 12−12 using TBCL0 and TBCL1.

Figure 12−12. Output Example—Timer in Up Mode

TBR

(max)

TBCL0

TBCL1

Output Mode 1: Set

Output Mode 2: Toggle/Reset

Output Mode 3: Set/Reset

Output Mode 4: Toggle

Output Mode 5: Reset

Output Mode 6: Toggle/Set

Output Mode 7: Reset/Set

EQU0

TBIFG

EQU1

EQU0

TBIFG

EQU1

EQU0

TBIFG

Interrupt Events

Timer_B

12-15

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Timer_B Operation

Output Example—Timer in Continuous Mode

The OUTx signal is changed when the timer reaches the TBCLx and TBCL0

values, depending on the output mode, An example is shown in Figure 12−13

using TBCL0 and TBCL1.

Figure 12−13. Output Example—Timer in Continuous Mode

TBR

(max)

TBCL0

TBCL1

Output Mode 1: Set

Output Mode 2: Toggle/Reset

Output Mode 3: Set/Reset

Output Mode 4: Toggle

Output Mode 5: Reset

Output Mode 6: Toggle/Set

Output Mode 7: Reset/Set

Interrupt Events

TBIFG EQU1 EQU0 TBIFG EQU1 EQU0

12-16

Timer_B

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Timer_B Operation

Output Example − Timer in Up/Down Mode

The OUTx signal changes when the timer equals TBCLx in either count

direction and when the timer equals TBCL0, depending on the output mode.

An example is shown in Figure 12−14 using TBCL0 and TBCL3.

Figure 12−14. Output Example—Timer in Up/Down Mode

TBR

(max)

TBCL0

TBCL3

Output Mode 1: Set

Output Mode 2: Toggle/Reset

Output Mode 3: Set/Reset

Output Mode 4: Toggle

Output Mode 5: Reset

Output Mode 6: Toggle/Set

Output Mode 7: Reset/Set

Interrupt Events

EQU3

TBIFG EQU0

EQU3

TBIFG

EQU0

Note: Switching Between Output Modes

When switching between output modes, one of the OUTMODx bits should

remain set during the transition, unless switching to mode 0. Otherwise,

output glitching can occur because a NOR gate decodes output mode 0. A

safe method for switching between output modes is to use output mode 7 as

a transition state:

BIS #OUTMOD_7,&TBCCTLx ; Set output mode=7

BIC #OUTMODx,&TBCCTLx ; Clear unwanted bits

Timer_B

12-17

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Timer_B Operation

12.2.6 Timer_B Interrupts

Two interrupt vectors are associated with the 16-bit Timer_B module:

- TBCCR0 interrupt vector for TBCCR0 CCIFG

- TBIV interrupt vector for all other CCIFG flags and TBIFG

In capture mode, any CCIFG flag is set when a timer value is captured in the

associated TBCCRx register. In compare mode, any CCIFG flag is set when

TBR counts to the associated TBCLx value. Software may also set or clear any

CCIFG flag. All CCIFG flags request an interrupt when their corresponding

CCIE bit and the GIE bit are set.

TBCCR0 Interrupt Vector

The TBCCR0 CCIFG flag has the highest Timer_B interrupt priority and has

a dedicated interrupt vector as shown in Figure 12−15. The TBCCR0 CCIFG

flag is automatically reset when the TBCCR0 interrupt request is serviced.

Figure 12−15. Capture/Compare TBCCR0 Interrupt Flag

Capture

CCIE

Set

EQU0

CAP

IRQ, Interrupt Service Requested

IRACC, Interrupt Request Accepted

Timer Clock

Reset

POR

TBIV, Interrupt Vector Generator

The TBIFG flag and TBCCRx CCIFG flags (excluding TBCCR0 CCIFG) are

prioritized and combined to source a single interrupt vector. The interrupt

vector register TBIV is used to determine which flag requested an interrupt.

The highest priority enabled interrupt (excluding TBCCR0 CCIFG) generates

a number in the TBIV register (see register description). This number can be

evaluated or added to the program counter to automatically enter the

appropriate software routine. Disabled Timer_B interrupts do not affect the

TBIV value.

Any access, read or write, of the TBIV register automatically resets the highest

pending interrupt flag. If another interrupt flag is set, another interrupt is

immediately generated after servicing the initial interrupt. For example, if the

TBCCR1 and TBCCR2 CCIFG flags are set when the interrupt service routine

accesses the TBIV register, TBCCR1 CCIFG is reset automatically. After the

RETI instruction of the interrupt service routine is executed, the TBCCR2

CCIFG flag will generate another interrupt.

12-18

Timer_B

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Timer_B Operation

TBIV, Interrupt Handler Examples

The following software example shows the recommended use of TBIV and the

handling overhead. The TBIV value is added to the PC to automatically jump

to the appropriate routine.

The numbers at the right margin show the necessary CPU clock cycles for

each instruction. The software overhead for different interrupt sources

includes interrupt latency and return-from-interrupt cycles, but not the task

handling itself. The latencies are:

- Capture/compare block CCR0

- Capture/compare blocks CCR1 to CCR6

- Timer overflow TBIFG

11 cycles

16 cycles

14 cycles

The following software example shows the recommended use of TBIV for

Timer_B3.

; Interrupt handler for TBCCR0 CCIFG.

CCIFG_0_HND

Cycles

...

; Start of handler Interrupt latency 6

RETI

; Interrupt handler for TBIFG, TBCCR1 and TBCCR2 CCIFG.

TB_HND

...

; Interrupt latency

ADD &TBIV,PC

RETI

; Add offset to Jump table ā3

; Vector 0: No interrupt 5

JMP CCIFG_1_HND ; Vector 2: Module 1

JMP CCIFG_2_HND ; Vector 4: Module 2

RETI

; Vector 6

; Vector 8

; Vector 10

; Vector 12

TBIFG_HND

; Vector 14: TIMOV Flag

; Task starts here

...

RETI

CCIFG_2_HND

...

RETI

; Vector 4: Module 2

; Task starts here

; Back to main program

; The Module 1 handler shows a way to look if any other

; interrupt is pending: 5 cycles have to be spent, but

; 9 cycles may be saved if another interrupt is pending

CCIFG_1_HND

...

JMP TB_HND

; Vector 6: Module 3

; Task starts here

; Look for pending ints

Timer_B

12-19

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Timer_B Registers

12.3 Timer_B Registers

The Timer_B registers are listed in Table 12−5:

Table 12−5.Timer_B Registers

Short Form

TBCTL

Initial State

Timer_B control

Read/write

Read only

0180h

0190h

0182h

0192h

0184h

0194h

0186h

0196h

0188h

0198h

018Ah

019Ah

018Ch

019Ch

018Eh

019Eh

011Eh

Reset with POR

Timer_B counter

TBR

Timer_B capture/compare control 0

Timer_B capture/compare 0

Timer_B capture/compare control 1

Timer_B capture/compare 1

Timer_B capture/compare control 2

Timer_B capture/compare 2

Timer_B capture/compare control 3

Timer_B capture/compare 3

Timer_B capture/compare control 4

Timer_B capture/compare 4

Timer_B capture/compare control 5

Timer_B capture/compare 5

Timer_B capture/compare control 6

Timer_B capture/compare 6

Timer_B Interrupt Vector

TBCCTL0

TBCCR0

TBCCTL1

TBCCR1

TBCCTL2

TBCCR2

TBCCTL3

TBCCR3

TBCCTL4

TBCCR4

TBCCTL5

TBCCR5

TBCCTL6

TBCCR6

TBIV

12-20

Timer_B

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Timer_B Registers

Timer_B Control Register TBCTL

Unused

rw−(0)

TBCLGRPx

CNTLx

Unused

rw−(0)

TBSSELx

rw−(0)

IDx

MCx

Unused

rw−(0)

TBCLR

w−(0)

TBIE

rw−(0)

TBIFG

rw−(0)

Unused

TBCLGRP

Bit 15

Unused

TBCLx group

Bit

14-13

00 Each TBCLx latch loads independently

01 TBCL1+TBCL2 (TBCCR1 CLLDx bits control the update)

TBCL3+TBCL4 (TBCCR3 CLLDx bits control the update)

TBCL5+TBCL6 (TBCCR5 CLLDx bits control the update)

TBCL0 independent

10 TBCL1+TBCL2+TBCL3 (TBCCR1 CLLDx bits control the update)

TBCL4+TBCL5+TBCL6 (TBCCR4 CLLDx bits control the update)

TBCL0 independent

11 TBCL0+TBCL1+TBCL2+TBCL3+TBCL4+TBCL5+TBCL6

(TBCCR1 CLLDx bits control the update)

CNTLx

Bits

Counter Length

12-11

00 16-bit, TBR

01 12-bit, TBR

10 10-bit, TBR

= 0FFFFh

= 0FFFh

= 03FFh

(max)

11 8-bit, TBR

= 0FFh

(max)

Unused

Bit 10

Unused

TBSSELx

Bits

9-8

Timer_B clock source select.

00 TBCLK

01 ACLK

10 SMCLK

11 Inverted TBCLK

IDx

Bits

7-6

Input divider. These bits select the divider for the input clock.

00 /1

01 /2

10 /4

11 /8

MCx

Bits

5-4

Mode control. Setting MCx = 00h when Timer_B is not in use conserves

power.

00 Stop mode: the timer is halted

01 Up mode: the timer counts up to TBCL0

10 Continuous mode: the timer counts up to the value set by TBCNTLx

11 Up/down mode: the timer counts up to TBCL0 and down to 0000h

Timer_B

12-21

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Timer_B Registers

Unused

TBCLR

Bit 3

Bit 2

Unused

Timer_B clear. Setting this bit resets TBR, the TBCLK divider, and the count

direction. The TBCLR bit is automatically reset and is always read as zero.

TBIE

Bit 1

Bit 0

Timer_B interrupt enable. This bit enables the TBIFG interrupt request.

Interrupt disabled

Interrupt enabled

TBIFG

Timer_B interrupt flag.

No interrupt pending

Interrupt pending

TBR, Timer_B Register

TBRx

rw−(0)

TBRx

Bits

Timer_B register. The TBR register is the count of Timer_B.

15-0

12-22

Timer_B

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Timer_B Registers

TBCCTLx, Capture/Compare Control Register

CMx

CCISx

SCS

CLLDx

CAP

rw−(0)

r−(0)

CCI

OUTMODx

CCIE

rw−(0)

OUT

rw−(0)

COV

rw−(0)

CCIFG

rw−(0)

CMx

Bit

Capture mode

15-14

00 No capture

01 Capture on rising edge

10 Capture on falling edge

11 Capture on both rising and falling edges

CCISx

Bit

Capture/compare input select. These bits select the TBCCRx input signal.

13-12

See the device-specific datasheet for specific signal connections.

00 CCIxA

01 CCIxB

10 GND

SCS

Bit 11

Synchronize capture source. This bit is used to synchronize the capture input

signal with the timer clock.

Asynchronous capture

Synchronous capture

CLLDx

Bit

10-9

Compare latch load. These bits select the compare latch load event.

00 TBCLx loads on write to TBCCRx

01 TBCLx loads when TBR counts to 0

10 TBCLx loads when TBR counts to 0 (up or continuous mode)

TBCLx loads when TBR counts to TBCL0 or to 0 (up/down mode)

11 TBCLx loads when TBR counts to TBCLx

CAP

Bit 8

Capture mode

Compare mode

Capture mode

OUTMODx

Bits

7-5

Output mode. Modes 2, 3, 6, and 7 are not useful for TBCL0 because EQUx

= EQU0.

000 OUT bit value

001 Set

010 Toggle/reset

011 Set/reset

100 Toggle

101 Reset

110 Toggle/set

111 Reset/set

Timer_B

12-23

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Timer_B Registers

CCIE

Bit 4

Capture/compare interrupt enable. This bit enables the interrupt request of

the corresponding CCIFG flag.

Interrupt disabled

Interrupt enabled

CCI

Bit 3

Bit 2

Capture/compare input. The selected input signal can be read by this bit.

Output. For output mode 0, this bit directly controls the state of the output.

OUT

Output low

Output high

COV

Bit 1

Bit 0

Capture overflow. This bit indicates a capture overflow occurred. COV must

be reset with software.

No capture overflow occurred

Capture overflow occurred

CCIFG

Capture/compare interrupt flag

No interrupt pending

Interrupt pending

12-24

Timer_B

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Timer_B Registers

TBIV, Timer_B Interrupt Vector Register

TBIVx

r−(0)

TBIVx

Bits

15-0

Timer_B interrupt vector value

Interrupt

Priority

TBIV Contents

Interrupt Source

No interrupt pending

Capture/compare 1

Capture/compare 2

Interrupt Flag

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

−

TBCCR1 CCIFG

TBCCR2 CCIFG

TBCCR3 CCIFG

TBCCR4 CCIFG

TBCCR5 CCIFG

TBCCR6 CCIFG

TBIFG

Highest

†

Capture/compare 3

†

Capture/compare 4

†

Capture/compare 5

†

Capture/compare 6

Timer overflow

Lowest

†

MSP430x14x, MSP430x16x devices only

Timer_B

12-25

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12-26

Timer_B

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Chapter 13

USART Peripheral Interface, UART Mode

The universal synchronous/asynchronous receive/transmit (USART)

peripheral interface supports two serial modes with one hardware module.

This chapter discusses the operation of the asynchronous UART mode.

USART0 is implemented on the MSP430x12xx, MSP430x13xx, and

MSP430x15x devices. In addition to USART0, the MSP430x14x and

MSP430x16x devices implement a second identical USART module,

USART1.

Topic

Page

13.1 USART Introduction: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

13.2 USART Operation: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4

13.3 USART Registers: UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21

USART Peripheral Interface, UART Mode

13-1

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USART Introduction: UART Mode

13.1 USART Introduction: UART Mode

In asynchronous mode, the USART connects the MSP430 to an external

system via two external pins, URXD and UTXD. UART mode is selected when

the SYNC bit is cleared.

UART mode features include:

- 7- or 8-bit data with odd, even, or non-parity

- Independent transmit and receive shift registers

- Separate transmit and receive buffer registers

- LSB-first data transmit and receive

- Built-in idle-line and address-bit communication protocols for

multiprocessor systems

- Receiver start-edge detection for auto-wake up from LPMx modes

- Programmable baud rate with modulation for fractional baud rate support

- Status flags for error detection and suppression and address detection

- Independent interrupt capability for receive and transmit

Figure 13−1 shows the USART when configured for UART mode.

13-2

USART Peripheral Interface, UART Mode

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USART Introduction: UART Mode

Figure 13−1. USART Block Diagram: UART Mode

SWRST URXEx* URXEIE URXWIE

SYNC= 0

URXIFGx*

Receive Control

FE PE OE BRK

Receive Status

Receiver Buffer UxRXBUF

Receiver Shift Register

LISTEN

SYNC

SOMI

RXERR

RXWAKE

SSEL1 SSEL0

URXD

CHAR

PEV

PENA

UCLKS

Baud−Rate Generator

UCLKI

ACLK

STE

Prescaler/Divider UxBRx

Modulator UxMCTL

SMCLK

UTXD

CHAR

PEV

PENA

WUT

Transmit Shift Register

SIMO

TXWAKE

UTXIFGx*

Transmit Buffer UxTXBUF

Transmit Control

SYNC CKPH CKPL

SWRST UTXEx* TXEPT

UCLKI

STC

UCLK

Clock Phase and Polarity

* Refer to the device-specific datasheet for SFR locations

USART Peripheral Interface, UART Mode

13-3

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USART Operation: UART Mode

13.2 USART Operation: UART Mode

In UART mode, the USART transmits and receives characters at a bit rate

asynchronous to another device. Timing for each character is based on the

selected baud rate of the USART. The transmit and receive functions use the

same baud rate frequency.

13.2.1 USART Initialization and Reset

The USART is reset by a PUC or by setting the SWRST bit. After a PUC, the

SWRST bit is automatically set, keeping the USART in a reset condition. When

set, the SWRST bit resets the URXIEx, UTXIEx, URXIFGx, RXWAKE,

TXWAKE, RXERR, BRK, PE, OE, and FE bits and sets the UTXIFGx and

TXEPT bits. The receive and transmit enable flags, URXEx and UTXEx, are

not altered by SWRST. Clearing SWRST releases the USART for operation.

See also chapter USART Module, I2C mode for USART0 when reconfiguring

from I C mode to UART mode.

Note: Initializing or Re-Configuring the USART Module

The required USART initialization/re-configuration process is:

1) Set SWRST (BIS.B #SWRST,&UxCTL)

2) Initialize all USART registers with SWRST = 1 (including UxCTL)

3) Enable USART module via the MEx SFRs (URXEx and/or UTXEx)

4) Clear SWRST via software (BIC.B #SWRST,&UxCTL)

5) Enable interrupts (optional) via the IEx SFRs (URXIEx and/or UTXIEx)

Failure to follow this process may result in unpredictable USART behavior.

13.2.2 Character Format

The UART character format, shown in Figure 13−2, consists of a start bit,

seven or eight data bits, an even/odd/no parity bit, an address bit (address-bit

mode), and one or two stop bits. The bit period is defined by the selected clock

source and setup of the baud rate registers.

Figure 13−2. Character Format

Mark

ST D0

D6 D7 AD PA SP SP

Space

[2nd Stop Bit, SP = 1]

[Parity Bit, PENA = 1]

[Address Bit, MM = 1]

[Optional Bit, Condition]

[8th Data Bit, CHAR = 1]

13-4

USART Peripheral Interface, UART Mode

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USART Operation: UART Mode

13.2.3 Asynchronous Communication Formats

When two devices communicate asynchronously, the idle-line format is used

for the protocol. When three or more devices communicate, the USART

supports the idle-line and address-bit multiprocessor communication formats.

Idle-Line Multiprocessor Format

When MM = 0, the idle-line multiprocessor format is selected. Blocks of data

are separated by an idle time on the transmit or receive lines as shown in

Figure 13−3. An idle receive line is detected when 10 or more continuous ones

(marks) are received after the first stop bit of a character. When two stop bits

are used for the idle line the second stop bit is counted as the first mark bit of

the idle period.

The first character received after an idle period is an address character. The

RXWAKE bit is used as an address tag for each block of characters. In the

idle-line multiprocessor format, this bit is set when a received character is an

address and is transferred to UxRXBUF.

Figure 13−3. Idle-Line Format

Blocks of

Characters

UTXDx/URXDx

Idle Periods of 10 Bits or More

UTXDx/URXDx Expanded

UTXDx/URXDx

Address

SP ST

Data

Character Within Block

First Character Within Block

Is Address. It Follows Idle

Period of 10 Bits or More

Idle Period Less Than 10 Bits

USART Peripheral Interface, UART Mode

13-5

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USART Operation: UART Mode

The URXWIE bit is used to control data reception in the idle-line

multiprocessor format. When the URXWIE bit is set, all non-address

characters are assembled but not transferred into the UxRXBUF, and

interrupts are not generated. When an address character is received, the

receiver is temporarily activated to transfer the character to UxRXBUF and

sets the URXIFGx interrupt flag. Any applicable error flag is also set. The user

can then validate the received address.

If an address is received, user software can validate the address and must

reset URXWIE to continue receiving data. If URXWIE remains set, only

address characters will be received. The URXWIE bit is not modified by the

USART hardware automatically.

For address transmission in idle-line multiprocessor format, a precise idle

period can be generated by the USART to generate address character

identifiers on UTXDx. The wake-up temporary (WUT) flag is an internal flag

double-buffered with the user-accessible TXWAKE bit. When the transmitter

is loaded from UxTXBUF, WUT is also loaded from TXWAKE resetting the

TXWAKE bit.

The following procedure sends out an idle frame to indicate an address

character will follow:

1) Set TXWAKE, then write any character to UxTXBUF. UxTXBUF must be

ready for new data (UTXIFGx = 1).

The TXWAKE value is shifted to WUT and the contents of UxTXBUF are

shifted to the transmit shift register when the shift register is ready for new

data. This sets WUT, which suppresses the start, data, and parity bits of a

normal transmission, then transmits an idle period of exactly 11 bits. When

two stop bits are used for the idle line, the second stop bit is counted as the

first mark bit of the idle period. TXWAKE is reset automatically.

2) Write desired address character to UxTXBUF. UxTXBUF must be ready

for new data (UTXIFGx = 1).

The new character representing the specified address is shifted out

following the address-identifying idle period on UTXDx. Writing the first

“don’t care” character to UxTXBUF is necessary in order to shift the

TXWAKE bit to WUT and generate an idle-line condition. This data is

discarded and does not appear on UTXDx.

13-6

USART Peripheral Interface, UART Mode

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USART Operation: UART Mode

Address-Bit Multiprocessor Format

When MM = 1, the address-bit multiprocessor format is selected. Each

processed character contains an extra bit used as an address indicator shown

in Figure 13−4. The first character in a block of characters carries a set

address bit which indicates that the character is an address. The USART

RXWAKE bit is set when a received character is a valid address character and

is transferred to UxRXBUF.

The URXWIE bit is used to control data reception in the address-bit

multiprocessor format. If URXWIE is set, data characters (address bit = 0) are

assembled by the receiver but are not transferred to UxRXBUF and no

interrupts are generated. When a character containing a set address bit is

received, the receiver is temporarily activated to transfer the character to

UxRXBUF and set URXIFGx. All applicable error status flags are also set.

If an address is received, user software must reset URXWIE to continue

receiving data. If URXWIE remains set, only address characters (address bit

= 1) will be received. The URXWIE bit is not modified by the USART hardware

automatically.

Figure 13−4. Address-Bit Multiprocessor Format

Blocks of

Characters

UTXDx/URXDx

Idle Periods of No Significance

UTXDx/URXDx

Expanded

UTXDx/URXDx

Address

1 SP ST

Data

AD Bit Is 0 for

Data Within Block.

First Character Within Block

Is an Address. AD Bit Is 1

Idle Time Is of No Significance

For address transmission in address-bit multiprocessor mode, the address bit

of a character can be controlled by writing to the TXWAKE bit. The value of the

TXWAKE bit is loaded into the address bit of the character transferred from

UxTXBUF to the transmit shift register, automatically clearing the TXWAKE bit.

TXWAKE must not be cleared by software. It is cleared by USART hardware

after it is transferred to WUT or by setting SWRST.

USART Peripheral Interface, UART Mode

13-7

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USART Operation: UART Mode

Automatic Error Detection

Glitch suppression prevents the USART from being accidentally started. Any

low-level on URXDx shorter than the deglitch time t (approximately 300 ns)

will be ignored. See the device-specific datasheet for parameters.

When a low period on URXDx exceeds t a majority vote is taken for the start

bit. If the majority vote fails to detect a valid start bit the USART halts character

reception and waits for the next low period on URXDx. The majority vote is also

used for each bit in a character to prevent bit errors.

The USART module automatically detects framing errors, parity errors,

overrun errors, and break conditions when receiving characters. The bits FE,

PE, OE, and BRK are set when their respective condition is detected. When

any of these error flags are set, RXERR is also set. The error conditions are

described in Table 13−1.

Table 13−1.Receive Error Conditions

Error Condition

Description

A framing error occurs when a low stop bit is

detected. When two stop bits are used, only the first

stop bit is checked for framing error. When a

framing error is detected, the FE bit is set.

Framing error

Parity error

A parity error is a mismatch between the number of

1s in a character and the value of the parity bit.

When an address bit is included in the character, it

is included in the parity calculation. When a parity

error is detected, the PE bit is set.

An overrun error occurs when a character is loaded

Receive overrun error into UxRXBUF before the prior character has been

read. When an overrun occurs, the OE bit is set.

A break condition is a period of 10 or more low bits

received on URXDx after a missing stop bit. When a

break condition is detected, the BRK bit is set. A

break condition can also set the interrupt flag

URXIFGx.

Break condition

When URXEIE = 0 and a framing error, parity error, or break condition is

detected, no character is received into UxRXBUF. When URXEIE = 1,

characters are received into UxRXBUF and any applicable error bit is set.

When any of the FE, PE, OE, BRK, or RXERR bits is set, the bit remains set

until user software resets it or UxRXBUF is read.

13-8

USART Peripheral Interface, UART Mode

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USART Operation: UART Mode

13.2.4 USART Receive Enable

The receive enable bit, URXEx, enables or disables data reception on URXDx

as shown in Figure 13−5. Disabling the USART receiver stops the receive

operation following completion of any character currently being received or

immediately if no receive operation is active. The receive-data buffer,

UxRXBUF, contains the character moved from the RX shift register after the

character is received.

Figure 13−5. State Diagram of Receiver Enable

No Valid Start Bit

URXEx = 0

Not Completed

URXEx = 1

Valid Start Bit

URXEx = 1

URXEx = 0

Idle State

(Receiver

Enabled)

Receiver

Collects

Character

Handle Interrupt

Conditions

Receive

Disable

Character

Received

URXEx = 1

URXEx = 0

Note: Re-Enabling the Receiver (Setting URXEx): UART Mode

When the receiver is disabled (URXEx = 0), re-enabling the receiver (URXEx

= 1) is asynchronous to any data stream that may be present on URXDx at

the time. Synchronization can be performed by testing for an idle line

condition before receiving a valid character (see URXWIE).

USART Peripheral Interface, UART Mode

13-9

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USART Operation: UART Mode

13.2.5 USART Transmit Enable

When UTXEx is set, the UART transmitter is enabled. Transmission is initiated

by writing data to UxTXBUF. The data is then moved to the transmit shift

transmission begins. This process is shown in Figure 13−6.

When the UTXEx bit is reset the transmitter is stopped. Any data moved to

UxTXBUF and any active transmission of data currently in the transmit shift

completed.

Figure 13−6. State Diagram of Transmitter Enable

No Data Written

to Transmit Buffer

UTXEx = 0

Not Completed

UTXEx = 1

Data Written to

Transmit Buffer

UTXEx = 1

UTXEx = 0

Idle State

(Transmitter

Enabled)

Handle Interrupt

Conditions

Transmit

Disable

Transmission

Active

Character

Transmitted

UTXEx = 1

UTXEx = 0 And Last Buffer Entry Is Transmitted

When the transmitter is enabled (UTXEx = 1), data should not be written to

UxTXBUF unless it is ready for new data indicated by UTXIFGx = 1. Violation

can result in an erroneous transmission if data in UxTXBUF is modified as it

is being moved into the TX shift register.

It is recommended that the transmitter be disabled (UTXEx = 0) only after any

active transmission is complete. This is indicated by a set transmitter empty

bit (TXEPT = 1). Any data written to UxTXBUF while the transmitter is disabled

will be held in the buffer but will not be moved to the transmit shift register or

transmitted. Once UTXEx is set, the data in the transmit buffer is immediately

loaded into the transmit shift register and character transmission resumes.

13-10

USART Peripheral Interface, UART Mode

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USART Operation: UART Mode

13.2.6 UART Baud Rate Generation

The USART baud rate generator is capable of producing standard baud rates

from non-standard source frequencies. The baud rate generator uses one

prescaler/divider and a modulator as shown in Figure 13−7. This combination

supports fractional divisors for baud rate generation. The maximum USART

baud rate is one-third the UART source clock frequency BRCLK.

Figure 13−7. MSP430 Baud Rate Generator

...

SSEL1 SSEL0

N =

...

UxBR1

UxBR0

UCLKI

ACLK

BRCLK

16−Bit Counter

............

SMCLK

Q15

Toggle

Compare (0 or 1)

+0 or 1

BITCLK

Modulation Data Shift Register

(LSB first)

Bit Start

UxMCTL

Timing for each bit is shown in Figure 13−8. For each bit received, a majority

vote is taken to determine the bit value. These samples occur at the N/2−1,

N/2, and N/2+1 BRCLK periods, where N is the number of BRCLKs per

BITCLK.

Figure 13−8. BITCLK Baud Rate Timing

(m= 0)

Majority Vote:

(m= 1)

Bit Start

BRCLK

N/2 N/2−1 N/2−2

N/2 N/2−1

N/2

Counter

BITCLK

N/2 N/2−1 N/2−2

N/2 N/2−1

: INT(N/2)

EVEN

INT(N/2) + m(= 0)

: INT(N/2) + R(= 1)

INT(N/2) + m(= 1)

ODD

Bit Period

m: corresponding modulation bit

R: Remainder from N/2 division

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USART Operation: UART Mode

Baud Rate Bit Timing

The first stage of the baud rate generator is the 16-bit counter and comparator.

At the beginning of each bit transmitted or received, the counter is loaded with

INT(N/2) where N is the value stored in the combination of UxBR0 and UxBR1.

The counter reloads INT(N/2) for each bit period half-cycle, giving a total bit

period of N BRCLKs. For a given BRCLK clock source, the baud rate used

determines the required division factor N:

BRCLK

baud rate

N =

The division factor N is often a non-integer value of which the integer portion

can be realized by the prescaler/divider. The second stage of the baud rate

generator, the modulator, is used to meet the fractional part as closely as

possible. The factor N is then defined as:

1 ^n*1

N + UxBR ) S m_i

n _i+0

Where:

Target division factor

UxBR: 16-bit representation of registers UxBR0 and UxBR1

Bit position in the character

Total number of bits in the character

Data of each corresponding modulation bit (1 or 0)

m :

BRCLK

¹ⁿȍ^–1

Baud rate +

UxBR ) _nm_i

i+0

The BITCLK can be adjusted from bit to bit with the modulator to meet timing

requirements when a non-integer divisor is needed. Timing of each bit is

expanded by one BRCLK clock cycle if the modulator bit m is set. Each time

a bit is received or transmitted, the next bit in the modulation control register

determines the timing for that bit. A set modulation bit increases the division

factor by one while a cleared modulation bit maintains the division factor given

by UxBR.

The timing for the start bit is determined by UxBR plus m0, the next bit is

determined by UxBR plus m1, and so on. The modulation sequence begins

with the LSB. When the character is greater than 8 bits, the modulation

sequence restarts with m0 and continues until all bits are processed.

Determining the Modulation Value

Determining the modulation value is an interactive process. Using the timing

error formula provided, beginning with the start bit , the individual bit errors are

calculated with the corresponding modulator bit set and cleared. The

modulation bit setting with the lower error is selected and the next bit error is

calculated. This process is continued until all bit errors are minimized. When

a character contains more than 8 bits, the modulation bits repeat. For example,

the 9th bit of a character uses modulation bit 0.

13-12

USART Peripheral Interface, UART Mode

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USART Operation: UART Mode

Transmit Bit Timing

The timing for each character is the sum of the individual bit timings. By

modulating each bit, the cumulative bit error is reduced. The individual bit error

can be calculated by:

baud rate

BRCLK

(

)

(

ƫ_{* j ) 1}

)

Error [%] +

j ) 1 UxBR ) S m_i

ǋ 100%

i+0

With:

baud rate: Desired baud rate

BRCLK: Input frequency − UCLKI, ACLK, or SMCLK

Bit position - 0 for the start bit, 1 for data bit D0, and so on

Division factor in registers UxBR1 and UxBR0

UxBR:

For example, the transmit errors for the following conditions are calculated:

Baud rate =

BRCLK =

UxBR =

2400

32,768 Hz (ACLK)

13, since the ideal division factor is 13.65

6Bh: m7=0, m6=1, m5=1, m4=0, m3=1, m2=0,

m1=1, and m0=1. The LSB of UxMCTL is used first.

UxMCTL =

baud rate

BRCLK

_{0 ) 1 UxBR ) 1 –1}Ǔ_{100% + 2.54%}

)

((

)

Start bit Error [%] +

baud rate

BRCLK

_{1 ) 1 UxBR ) 2 –2}Ǔ_{100% + 5.08%}

)

((

)

Data bit D0 Error [%] +

baud rate

BRCLK

_{2 ) 1 UxBR ) 2 –3}Ǔ_{100% + 0.29%}

((

)

Data bit D1 Error [%] +

Data bit D2 Error [%] +

Data bit D3 Error [%] +

baud rate

BRCLK

_{3 ) 1 UxBR ) 3 –4}Ǔ_{100% + 2.83%}

)

baud rate

BRCLK

_{4 ) 1 UxBR ) 3 –5}Ǔ_{100% +*1.95%}

)

baud rate

BRCLK

_{5 ) 1 UxBR ) 4 –6}Ǔ_{100% + 0.59%}

)

((

)

Data bit D4 Error [%] +

Data bit D5 Error [%] +

Data bit D6 Error [%] +

Data bit D7 Error [%] +

baud rate

BRCLK

_{6 ) 1 UxBR ) 5 –7}Ǔ_{100% + 3.13%}

)

((

)

baud rate

BRCLK

_{7 ) 1 UxBR ) 5 –8}Ǔ_{100% + *1.66%}

)

baud rate

BRCLK

_{8 ) 1 UxBR ) 6 –9}Ǔ_{100% + 0.88%}

)

baud rate

BRCLK

_{9 ) 1 UxBR ) 7 –10}Ǔ_{100% + 3.42%}

)

((

)

Parity bit Error [%] +

baud rate

BRCLK

_{10 ) 1 UxBR ) 7 –11}Ǔ_{100% + *1.37%}

)

((

)

Stop bit 1 Error [%] +

The results show the maximum per-bit error to be 5.08% of a BITCLK period.

USART Peripheral Interface, UART Mode

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USART Operation: UART Mode

Receive Bit Timing

Receive timing consists of two error sources. The first is the bit-to-bit timing

error. The second is the error between a start edge occurring and the start

edge being accepted by the USART. Figure 13−9 shows the asynchronous

timing errors between data on the URXDx pin and the internal baud-rate clock.

Figure 13−9. Receive Error

ideal

9 10 11 12 13 14 1

BRCLK

URXDx

URXDS

actual

Synchronization Error 0.5x BRCLK

Sample

URXDS

Int(UxBR/2)+m0 =

UxBR +m1 = 13+1 = 14

UxBR +m2 = 13+0 = 13

Int (13/2)+1 = 6+1 = 7

Majority Vote Taken

The ideal start bit timing t

is half the baud-rate timing t

because

ideal(0)

baud rate

the bit is tested in the middle of its period. The ideal baud rate timing t

for

ideal(i)

the remaining character bits is the baud rate timing t

errors can be calculated by:

. The individual bit

baud rate

ȡ_{baud rate}

ǒ^UxBRǓ

₂ƪ_{m0 ) int}

Error [%] +

) i UxBR ) S m_iǋ* 1 * j 100%

i+1

Ȣ ^BRCLK

Where:

baud rate is the required baud rate

BRCLK is the input frequency—selected for UCLK, ACLK, or SMCLK

j = 0 for the start bit, 1 for data bit D0, and so on

UxBR is the division factor in registers UxBR1 and UxBR0

13-14

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USART Operation: UART Mode

For example, the receive errors for the following conditions are calculated:

Baud rate = 2400

BRCLK =

UxBR =

32,768 Hz (ACLK)

13, since the ideal division factor is 13.65

UxMCTL = 6B:m7=0, m6=1, m5=1, m4=0, m3=1, m2=0, m1=1 and

m0=1 The LSB of UxMCTL is used first.

baud rate

BRCLK

_{2x 1 ) 6 ) (0 UxBR ) 0) * 1 * 0}Ǔ_{100% + 2.54%}

]

[

(

)

Start bit Error [%] +

baud rate

BRCLK

_{2x 1 ) 6 ) (1 UxBR ) 1) –1–1}Ǔ_{100% + 5.08%}

)

[

(

]

Data bit D0 Error [%] +

baud rate

BRCLK

_{2x 1 ) 6 ) (2 UxBR ) 1) –1–2}Ǔ_{100% + 0.29%}

[

(

)

]

Data bit D1 Error [%] +

Data bit D2 Error [%] +

Data bit D3 Error [%] +

Data bit D4 Error [%] +

baud rate

BRCLK

_{2x 1 ) 6 ) (3 UxBR ) 2) –1–3}Ǔ_{100% + 2.83%}

[

(

)

]

baud rate

BRCLK

_{2x 1 ) 6 ) (4 UxBR ) 2) –1–4}Ǔ_{100% + –1.95%}

[

(

)

]

baud rate

BRCLK

_{2x 1 ) 6 ) (5 UxBR ) 3) –1–5}Ǔ_{100% + 0.59%}

[

(

)

]

baud rate

BRCLK

_{2x 1 ) 6 ) (6 UxBR ) 4) –1–6}Ǔ_{100% + 3.13%}

[

(

)

]

Data bit D5 Error [%] +

baud rate

BRCLK

_{2x 1 ) 6 ) (7 UxBR ) 4) –1–7}Ǔ_{100% + –1.66%}

[

(

)

]

Data bit D6 Error [%] +

baud rate

BRCLK

_{2x 1 ) 6 ) (8 UxBR ) 5) –1–8}Ǔ_{100% + 0.88%}

]

[

(

)

Data bit D7 Error [%] +

baud rate

BRCLK

_{2x 1 ) 6 ) (9 UxBR ) 6) –1–9}Ǔ_{100% + 3.42%}

]

[

(

)

Parity bit Error [%] +

baud rate

BRCLK

_{2x 1 ) 6 ) (10 UxBR ) 6) –1–10}Ǔ_{100% + –1.37%}

[

(

)

]

Stop bit 1 Error [%] +

The results show the maximum per-bit error to be 5.08% of a BITCLK period.

USART Peripheral Interface, UART Mode

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USART Operation: UART Mode

Typical Baud Rates and Errors

Standard baud rate frequency data for UxBRx and UxMCTL are listed in

Table 13−2 for a 32,768-Hz watch crystal (ACLK) and a typical 1,048,576-Hz

SMCLK.

The receive error is the accumulated time versus the ideal scanning time in the

middle of each bit. The transmit error is the accumulated timing error versus

the ideal time of the bit period.

Table 13−2.Commonly Used Baud Rates, Baud Rate Data, and Errors

Divide by

A: BRCLK = 32,768 Hz

B: BRCLK = 1,048,576 Hz

Max.

Synchr.

Max.

Error % Error %

Max.

Baud

Rate

Error % Error % Error %

UxBR1 UxBR0 UxMCTL

1200 27.31 873.81

2400 13.65 436.91

−4/3

−6/3

−4/3

−6/3

0/0.3

0/0.4

−0.4/1

−0.2/2

−4/3

4800

9600

6.83 218.45

3.41 109.23

54.61

−9/11

−21/12 −21/12

19,200

38,400

76,800

115,200

27.31

13.65

−6/3

9.1

−5/7

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USART Operation: UART Mode

13.2.7 USART Interrupts

The USART has one interrupt vector for transmission and one interrupt vector

for reception.

USART Transmit Interrupt Operation

The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF

is ready to accept another character. An interrupt request is generated if

UTXIEx and GIE are also set. UTXIFGx is automatically reset if the interrupt

request is serviced or if a character is written to UxTXBUF.

UTXIFGx is set after a PUC or when SWRST = 1. UTXIEx is reset after a PUC

or when SWRST = 1. The operation is shown is Figure 13−10.

Figure 13−10. Transmit Interrupt Operation

UTXIEx

Clear

PUC or SWRST

Interrupt Service Requested

Set

UTXIFGx

Character Moved From

Buffer to Shift Register

SWRST

Clear

Data written to UxTXBUF

IRQA

USART Peripheral Interface, UART Mode

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USART Operation: UART Mode

USART Receive Interrupt Operation

The URXIFGx interrupt flag is set each time a character is received and loaded

into UxRXBUF. An interrupt request is generated if URXIEx and GIE are also

set. URXIFGx and URXIEx are reset by a system reset PUC signal or when

SWRST = 1. URXIFGx is automatically reset if the pending interrupt is served

(when URXSE = 0) or when UxRXBUF is read. The operation is shown in

Figure 13−11.

Figure 13−11.Receive Interrupt Operation

SYNC

Valid Start Bit

URXS

Receiver Collects Character

URXSE

From URXD

Clear

Erroneous Character Rejection

URXEIE

Interrupt Service

Requested

URXIEx

BRK

URXIFGx

Clear

URXWIE

RXWAKE

SWRST

PUC

UxRXBUF Read

URXSE

Character Received

Break Detected

Non-Address Character Rejection

IRQA

URXEIE is used to enable or disable erroneous characters from setting

URXIFGx. When using multiprocessor addressing modes, URXWIE is used

to auto-detect valid address characters and reject unwanted data characters.

Two types of characters do not set URXIFGx:

- Erroneous characters when URXEIE = 0

- Non-address characters when URXWIE = 1

When URXEIE = 1 a break condition will set the BRK bit and the URXIFGx flag.

13-18

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USART Operation: UART Mode

Receive-Start Edge Detect Operation

The URXSE bit enables the receive start-edge detection feature. The

recommended usage of the receive-start edge feature is when BRCLK is

sourced by the DCO and when the DCO is off because of low-power mode

operation. The ultra-fast turn-on of the DCO allows character reception after

the start edge detection.

When URXSE, URXIEx and GIE are set and a start edge occurs on URXDx,

the internal signal URXS will be set. When URXS is set, a receive interrupt

request is generated but URXIFGx is not set. User software in the receive

interrupt service routine can test URXIFGx to determine the source of the

interrupt. When URXIFGx = 0 a start edge was detected and when URXIFGx

= 1 a valid character (or break) was received.

When the ISR determines the interrupt request was from a start edge, user

software toggles URXSE, and must enable the BRCLK source by returning

from the ISR to active mode or to a low-power mode where the source is active.

If the ISR returns to a low-power mode where the BRCLK source is inactive,

the character will not be received. Toggling URXSE clears the URXS signal

and re-enables the start edge detect feature for future characters. See chapter

System Resets, Interrupts, and Operating Modes for information on entering

and exiting low-power modes.

The now active BRCLK allows the USART to receive the balance of the

character. After the full character is received and moved to UxRXBUF,

URXIFGx is set and an interrupt service is again requested. Upon ISR entry,

URXIFGx = 1 indicating a character was received. The URXIFGx flag is

cleared when user software reads UxRXBUF.

; Interrupt handler for start condition and

; Character receive. BRCLK = DCO.

U0RX_Int BIT.B #URXIFG0,&IFG2 ; Test URXIFGx to determine

JNE ST_COND

; If start or character

MOV.B &UxRXBUF,dst

; Read buffer

...

;

RETI

ST_COND BIC.B #URXSE,&U0TCTL ; Clear URXS signal

BIS.B #URXSE,&U0TCTL ; Re-enable edge detect

BIC #SCG0+SCG1,0(SP) ; Enable BRCLK = DCO

RETI

;

Note: Break Detect With Halted UART Clock

When using the receive start-edge detect feature a break condition cannot

be detected when the BRCLK source is off.

USART Peripheral Interface, UART Mode

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USART Operation: UART Mode

Receive-Start Edge Detect Conditions

When URXSE = 1, glitch suppression prevents the USART from being

accidentally started. Any low-level on URXDx shorter than the deglitch time t

(approximately 300 ns) will be ignored by the USART and no interrupt request

will be generated as shown in Figure 13−12. See the device-specific

datasheet for parameters.

Figure 13−12. Glitch Suppression, USART Receive Not Started

URXDx

URXS

When a glitch is longer than t or a valid start bit occurs on URXDx, the USART

τ,

receive operation is started and a majority vote is taken as shown in

Figure 13−13. If the majority vote fails to detect a start bit the USART halts

character reception.

If character reception is halted, an active BRCLK is not necessary. A time-out

period longer than the character receive duration can be used by software to

indicate that a character was not received in the expected time and the

software can disable BRCLK.

Figure 13−13. Glitch Suppression, USART Activated

Majority Vote Taken

URXDx

URXS

13-20

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USART Registers: UART Mode

13.3 USART Registers: UART Mode

Table 13−3 lists the registers for all devices implementing a USART module.

Table 13−4 applies only to devices with a second USART module, USART1.

Table 13−3.USART0 Control and Status Registers

Short Form

U0CTL

U0TCTL

U0RCTL

U0MCTL

U0BR0

U0BR1

U0RXBUF

U0TXBUF

ME1

Initial State

USART control register

Transmit control register

Receive control register

Modulation control register

Baud rate control register 0

Baud rate control register 1

Receive buffer register

Read/write

Read

070h

071h

072h

073h

074h

075h

076h

077h

004h

000h

002h

001h with PUC

000h with PUC

Unchanged

Transmit buffer register

SFR module enable register 1†

SFR interrupt enable register 1†

SFR interrupt flag register 1†

Read/write

Unchanged

000h with PUC

082h with PUC

IE1

IFG1

†

Does not apply to ’12xx devices. Refer to the register definitions for registers and bit positions for these devices.

Table 13−4.USART1 Control and Status Registers

Short Form

U1CTL

U1TCTL

U1RCTL

U1MCTL

U1BR0

U1BR1

U1RXBUF

U1TXBUF

ME2

Initial State

USART control register

Transmit control register

Receive control register

Modulation control register

Baud rate control register 0

Baud rate control register 1

Receive buffer register

Transmit buffer register

SFR module enable register 2

SFR interrupt enable register 2

SFR interrupt flag register 2

Read/write

Read

078h

079h

07Ah

07Bh

07Ch

07Dh

07Eh

07Fh

005h

001h

003h

001h with PUC

000h with PUC

Unchanged

Read/write

Unchanged

000h with PUC

020h with PUC

IE2

IFG2

Note: Modifying SFR bits

To avoid modifying control bits of other modules, it is recommended to set

or clear the IEx and IFGx bits using BIS.Bor BIC.Binstructions, rather than

MOV.Bor CLR.Binstructions.

USART Peripheral Interface, UART Mode

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USART Registers: UART Mode

UxCTL, USART Control Register

PENA

rw−0

PEV

rw−0

SPB

rw−0

CHAR

rw−0

LISTEN

rw−0

SYNC

rw−0

SWRST

rw−1

PENA

Bit 7

Parity enable

Parity disabled.

Parity enabled. Parity bit is generated (UTXDx) and expected

(URXDx). In address-bit multiprocessor mode, the address bit is

included in the parity calculation.

PEV

SPB

Bit 6

Bit 5

Parity select. PEV is not used when parity is disabled.

Odd parity

Even parity

Stop bit select. Number of stop bits transmitted. The receiver always

checks for one stop bit.

One stop bit

Two stop bits

CHAR

LISTEN

SYNC

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Character length. Selects 7-bit or 8-bit character length.

7-bit data

8-bit data

Listen enable. The LISTEN bit selects loopback mode.

Disabled

Enabled. UTXDx is internally fed back to the receiver.

Synchronous mode enable

UART mode

SPI Mode

Multiprocessor mode select

Idle-line multiprocessor protocol

Address-bit multiprocessor protocol

SWRST

Software reset enable

Disabled. USART reset released for operation

Enabled. USART logic held in reset state

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USART Registers: UART Mode

UxTCTL, USART Transmit Control Register

Unused

rw−0

CKPL

rw−0

SSELx

URXSE

rw−0

TXWAKE

rw−0

Unused

rw−0

TXEPT

rw−1

rw−0

Unused

Bit 7

Unused

Clock polarity select

CKPL

Bit 6

UCLKI = UCLK

UCLKI = inverted UCLK

SSELx

Bits

5-4

Source select. These bits select the BRCLK source clock.

00 UCLKI

01 ACLK

10 SMCLK

11 SMCLK

URXSE

Bit 3

Bit 2

UART receive start-edge. The bit enables the UART receive start-edge

feature.

Disabled

Enabled

TXWAKE

Transmitter wake

Next character transmitted is data

Next character transmitted is an address

Unused

TXEPT

Bit 1

Bit 0

Unused

Transmitter empty flag

UART is transmitting data and/or data is waiting in UxTXBUF

Transmitter shift register and UxTXBUF are empty or SWRST=1

USART Peripheral Interface, UART Mode

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USART Registers: UART Mode

UxRCTL, USART Receive Control Register

BRK

rw−0

URXEIE

rw−0

URXWIE

rw−0

RXWAKE

rw−0

RXERR

rw−0

Bit 7

Framing error flag

No error

Character received with low stop bit

Bit 6

Bit 5

Parity error flag. When PENA = 0, PE is read as 0.

No error

Character received with parity error

Overrun error flag. This bit is set when a character is transferred into

UxRXBUF before the previous character was read.

No error

Overrun error occurred

BRK

Bit 4

Bit 3

Bit 2

Break detect flag

No break condition

Break condition occurred

URXEIE

URXWIE

Receive erroneous-character interrupt-enable

Erroneous characters rejected and URXIFGx is not set

Erroneous characters received will set URXIFGx

Receive wake-up interrupt-enable. This bit enables URXIFGx to be set

when an address character is received. When URXEIE = 0, an address

character will not set URXIFGx if it is received with errors.

All received characters set URXIFGx

Only received address characters set URXIFGx

RXWAKE

RXERR

Bit 1

Bit 0

Receive wake-up flag

Received character is data

Received character is an address

Receive error flag. This bit indicates a character was received with error(s).

When RXERR = 1, on or more error flags (FE,PE,OE, BRK) is also set.

RXERR is cleared when UxRXBUF is read.

No receive errors detected

Receive error detected

13-24

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USART Registers: UART Mode

UxBR0, USART Baud Rate Control Register 0

UxBR1, USART Baud Rate Control Register 1

UxBRx

The valid baud-rate control range is 3 ≤ UxBR < 0FFFFh, where UxBR =

{UxBR1+UxBR0}. Unpredictable receive and transmit timing occurs if

UxBR <3.

UxMCTL, USART Modulation Control Register

UxMCTLx

Bits

7−0

Modulation bits. These bits select the modulation for BRCLK.

USART Peripheral Interface, UART Mode

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USART Registers: UART Mode

UxRXBUF, USART Receive Buffer Register

UxRXBUFx

Bits

7−0

The receive-data buffer is user accessible and contains the last received

character from the receive shift register. Reading UxRXBUF resets the

receive-error bits, the RXWAKE bit, and URXIFGx. In 7-bit data mode,

UxRXBUF is LSB justified and the MSB is always reset.

UxTXBUF, USART Transmit Buffer Register

UxTXBUFx

Bits

7−0

The transmit data buffer is user accessible and holds the data waiting to be

moved into the transmit shift register and transmitted on UTXDx. Writing to

the transmit data buffer clears UTXIFGx. The MSB of UxTXBUF is not

used for 7-bit data and is reset.

13-26

USART Peripheral Interface, UART Mode

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USART Registers: UART Mode

ME1, Module Enable Register 1

†

UTXE0

rw−0

URXE0

rw−0

†

UTXE0

Bit 7

USART0 transmit enable. This bit enables the transmitter for USART0.

Module not enabled

Module enabled

†

URXE0

Bit 6

USART0 receive enable. This bit enables the receiver for USART0.

Module not enabled

Module enabled

Bits

5-0

These bits may be used by other modules. See device-specific datasheet.

†

Does not apply to MSP430x12xx devices. See ME2 for the MSP430x12xx USART0 module enable bits

ME2, Module Enable Register 2

‡

UTXE1

rw−0

URXE1

rw−0

UTXE0

rw−0

URXE0

rw−0

Bits

7-6

These bits may be used by other modules. See device-specific datasheet.

USART1 transmit enable. This bit enables the transmitter for USART1.

UTXE1

Bit 5

Module not enabled

Module enabled

URXE1

Bit 4

USART1 receive enable. This bit enables the receiver for USART1.

Module not enabled

Module enabled

Bits

3-2

These bits may be used by other modules. See device-specific datasheet.

‡

UTXE0

Bit 1

USART0 transmit enable. This bit enables the transmitter for USART0.

Module not enabled

Module enabled

‡

URXE0

Bit 0

USART0 receive enable. This bit enables the receiver for USART0.

Module not enabled

Module enabled

‡

MSP430x12xx devices only

USART Peripheral Interface, UART Mode

13-27

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USART Registers: UART Mode

IE1, Interrupt Enable Register 1

†

UTXIE0

rw−0

URXIE0

rw−0

†

UTXIE0

Bit 7

USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt.

Interrupt not enabled

Interrupt enabled

†

URXIE0

Bit 6

USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt.

Interrupt not enabled

Interrupt enabled

Bits

5-0

These bits may be used by other modules. See device-specific datasheet.

†

Does not apply to MSP430x12xx devices. See IE2 for the MSP430x12xx USART0 interrupt enable bits

IE2, Interrupt Enable Register 2

‡

UTXIE1

rw−0

URXIE1

rw−0

UTXIE0

rw−0

URXIE0

rw−0

Bits

7-6

These bits may be used by other modules. See device-specific datasheet.

USART1 transmit interrupt enable. This bit enables the UTXIFG1 interrupt.

UTXIE1

URXIE1

Bit 5

Interrupt not enabled

Interrupt enabled

Bit 4

USART1 receive interrupt enable. This bit enables the URXIFG1 interrupt.

Interrupt not enabled

Interrupt enabled

Bits

3-2

These bits may be used by other modules. See device-specific datasheet.

‡

UTXIE0

Bit 1

USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt.

Interrupt not enabled

Interrupt enabled

‡

URXIE0

Bit 0

USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt.

Interrupt not enabled

Interrupt enabled

‡

MSP430x12xx devices only

13-28

USART Peripheral Interface, UART Mode

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USART Registers: UART Mode

IFG1, Interrupt Flag Register 1

†

UTXIFG0

rw−1

URXIFG0

rw−0

†

UTXIFG0

Bit 7

Bit 6

USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty.

No interrupt pending

Interrupt pending

†

URXIFG0

USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received

a complete character.

No interrupt pending

Interrupt pending

Bits

5-0

These bits may be used by other modules. See device-specific datasheet.

†

Does not apply to MSP430x12xx devices. See IFG2 for the MSP430x12xx USART0 interrupt flag bits

IFG2, Interrupt Flag Register 2

‡

UTXIFG1

rw−1

URXIFG1

rw−0

UTXIFG0

rw−1

URXIFG0

rw−0

Bits

7-6

These bits may be used by other modules. See device-specific datasheet.

USART1 transmit interrupt flag. UTXIFG1 is set when U1TXBUF empty.

UTXIFG1

URXIFG1

Bit 5

No interrupt pending

Interrupt pending

Bit 4

USART1 receive interrupt flag. URXIFG1 is set when U1RXBUF has received

a complete character.

No interrupt pending

Interrupt pending

Bits

3-2

These bits may be used by other modules. See device-specific datasheet.

USART Peripheral Interface, UART Mode

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USART Registers: UART Mode

‡

UTXIFG0

Bit 1

Bit 0

USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty.

No interrupt pending

Interrupt pending

‡

URXIFG0

USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received

a complete character.

No interrupt pending

Interrupt pending

‡

MSP430x12xx devices only

13-30

USART Peripheral Interface, UART Mode

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USART Peripheral Interface, UART Mode

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Chapter 14

USART Peripheral Interface, SPI Mode

The universal synchronous/asynchronous receive/transmit (USART)

peripheral interface supports two serial modes with one hardware module.

This chapter discusses the operation of the synchronous peripheral interface

or SPI mode. USART0 is implemented on the MSP430x12xx, MSP430x13xx,

and MSP430x15x devices. In addition to USART0, the MSP430x14x and

MSP430x16x devices implement a second identical USART module,

USART1.

Topic

Page

14.1 USART Introduction: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

14.2 USART Operation: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4

14.3 USART Registers: SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13

USART Peripheral Interface, SPI Mode

14-1

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USART Introduction: SPI Mode

14.1 USART Introduction: SPI Mode

In synchronous mode, the USART connects the MSP430 to an external

system via three or four pins: SIMO, SOMI, UCLK, and STE. SPI mode is

selected when the SYNC bit is set and the I2C bit is cleared.

SPI mode features include:

- 7- or 8-bit data length

- 3-pin and 4-pin SPI operation

- Master or slave modes

- Independent transmit and receive shift registers

- Separate transmit and receive buffer registers

- Selectable UCLK polarity and phase control

- Programmable UCLK frequency in master mode

- Independent interrupt capability for receive and transmit

Figure 14−1 shows the USART when configured for SPI mode.

14-2

USART Peripheral Interface, SPI Mode

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USART Introduction: SPI Mode

Figure 14−1. USART Block Diagram: SPI Mode

SWRST USPIEx* URXEIE URXWIE

SYNC= 1

URXIFGx*

Receive Control

FE PE OE BRK

Receive Status

Receiver Buffer UxRXBUF

Receiver Shift Register

LISTEN

SYNC

SOMI

URXD

STE

RXERR

RXWAKE

SSEL1 SSEL0

CHAR

PEV

PENA

UCLKS

Baud−Rate Generator

UCLKI

ACLK

Prescaler/Divider UxBRx

Modulator UxMCTL

SMCLK

UTXD

SIMO

CHAR

PEV

PENA

WUT

Transmit Shift Register

TXWAKE

UTXIFGx*

Transmit Buffer UxTXBUF

Transmit Control

SYNC CKPH CKPL

SWRST USPIEx* TXEPT

UCLKI

STC

UCLK

Clock Phase and Polarity

* Refer to the device-specific datasheet for SFR locations

USART Peripheral Interface, SPI Mode

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USART Operation: SPI Mode

14.2 USART Operation: SPI Mode

In SPI mode, serial data is transmitted and received by multiple devices using

a shared clock provided by the master. An additional pin, STE, is provided as

to enable a device to receive and transmit data and is controlled by the master.

Three or four signals are used for SPI data exchange:

- SIMO Slave in, master out

Master mode: SIMO is the data output line.

Slave mode: SIMO is the data input line.

- SOMI Slave out, master in

Master mode: SOMI is the data input line.

Slave mode: SOMI is the data output line.

- UCLK USART SPI clock

Master mode: UCLK is an output.

Slave mode: UCLK is an input.

- STE

Slave transmit enable. Used in 4-pin mode to allow multiple

masters on a single bus. Not used in 3-pin mode.

4-Pin master mode:

When STE is high, SIMO and UCLK operate normally.

When STE is low, SIMO and UCLK are set to the input direction.

4-pin slave mode:

When STE is high, RX/TX operation of the slave is disabled and

SOMI is forced to the input direction.

When STE is low, RX/TX operation of the slave is enabled and

SOMI operates normally.

14.2.1 USART Initialization and Reset

The USART is reset by a PUC or by the SWRST bit. After a PUC, the SWRST

bit is automatically set, keeping the USART in a reset condition. When set, the

SWRST bit resets the URXIEx, UTXIEx, URXIFGx, OE, and FE bits and sets

the UTXIFGx flag. The USPIEx bit is not altered by SWRST. Clearing SWRST

releases the USART for operation. See also chapter USART Module, I2C

mode for USART0 when reconfiguring from I C mode to SPI mode.

Note: Initializing or Re-Configuring the USART Module

The required USART initialization/re-configuration process is:

1) Set SWRST (BIS.B #SWRST,&UxCTL)

2) Initialize all USART registers with SWRST=1 (including UxCTL)

3) Enable USART module via the MEx SFRs (USPIEx)

4) Clear SWRST via software (BIC.B #SWRST,&UxCTL)

5) Enable interrupts (optional) via the IEx SFRs (URXIEx and/or UTXIEx)

Failure to follow this process may result in unpredictable USART behavior.

14-4

USART Peripheral Interface, SPI Mode

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USART Operation: SPI Mode

14.2.2 Master Mode

Figure 14−2. USART Master and External Slave

MASTER

SLAVE

SIMO

Receive Buffer UxRXBUF

Transmit Buffer UxTXBUF

SPI Receive Buffer

Px.x

STE

Port.x

SOMI

Receive Shift Register

LSB

MSP430 USART

Transmit Shift Register

Data Shift Register (DSR)

LSB

UCLK

LSB

MSB

SCLK

COMMON SPI

Figure 14−2 shows the USART as a master in both 3-pin and 4-pin

configurations. The USART initiates data transfer when data is moved to the

transmit data buffer UxTXBUF. The UxTXBUF data is moved to the TX shift

starting with the most-significant bit. Data on SOMI is shifted into the receive

shift register on the opposite clock edge, starting with the most-significant bit.

When the character is received, the receive data is moved from the RX shift

URXIFGx, is set, indicating the RX/TX operation is complete.

A set transmit interrupt flag, UTXIFGx, indicates that data has moved from

UxTXBUF to the TX shift register and UxTXBUF is ready for new data. It does

not indicate RX/TX completion.

To receive data into the USART in master mode, data must be written to

UxTXBUF because receive and transmit operations operate concurrently.

Four-Pin SPI Master Mode

In 4-pin master mode, STE is used to prevent conflicts with another master.

The master operates normally when STE is high. When STE is low:

- SIMO and UCLK are set to inputs and no longer drive the bus

- The error bit FE is set indicating a communication integrity violation to be

handled by the user

A low STE signal does not reset the USART module. The STE input signal is

not used in 3-pin master mode.

USART Peripheral Interface, SPI Mode

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USART Operation: SPI Mode

14.2.3 Slave Mode

Figure 14−3. USART Slave and External Master

MASTER

SLAVE

SIMO

SPI Receive Buffer

Transmit Buffer UxTXBUF

Receive Buffer UxRXBUF

Px.x

STE

Port.x

SOMI

Data Shift Register DSR

Transmit Shift Register

Receive Shift Register

MSB

UCLK

MSB

LSB

SCLK

COMMON SPI

MSP430 USART

Figure 14−3 shows the USART as a slave in both 3-pin and 4-pin

configurations. UCLK is used as the input for the SPI clock and must be

supplied by the external master. The data-transfer rate is determined by this

clock and not by the internal baud rate generator. Data written to UxTXBUF

and moved to the TX shift register before the start of UCLK is transmitted on

SOMI. Data on SIMO is shifted into the receive shift register on the opposite

edge of UCLK and moved to UxRXBUF when the set number of bits are

received. When data is moved from the RX shift register to UxRXBUF, the

URXIFGx interrupt flag is set, indicating that data has been received. The

overrun error bit, OE, is set when the previously received data is not read from

UxRXBUF before new data is moved to UxRXBUF.

Four-Pin SPI Slave Mode

In 4-pin slave mode, STE is used by the slave to enable the transmit and

receive operations and is provided by the SPI master. When STE is low, the

slave operates normally. When STE is high:

- Any receive operation in progress on SIMO is halted

- SOMI is set to the input direction

A high STE signal does not reset the USART module. The STE input signal

is not used in 3-pin slave mode.

14-6

USART Peripheral Interface, SPI Mode

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USART Operation: SPI Mode

14.2.4 SPI Enable

The SPI transmit/receive enable bit USPIEx enables or disables the USART

in SPI mode. When USPIEx = 0, the USART stops operation after the current

transfer completes, or immediately if no operation is active. A PUC or set

SWRST bit disables the USART immediately and any active transfer is

terminated.

Transmit Enable

When USPIEx = 0, any further write to UxTXBUF does not transmit. Data

written to UxTXBUF will begin to transmit when USPIEx = 1 and the BRCLK

source is active. Figure 14−4 and Figure 14−5 show the transmit enable state

diagrams.

Figure 14−4. Master Mode Transmit Enable

No Data Written

to Transfer Buffer

USPIEx = 0

Not Completed

USPIEx = 1,

Data Written to

Transmit Buffer

USPIEx = 1

Idle State

Handle Interrupt

Conditions

Transmit

Disable

Transmission

Active

(Transmitter

Enabled)

USPIEx = 0

Character

Transmitted

SWRST

PUC

USPIEx = 1

USPIEx = 0 And Last Buffer

Entry Is Transmitted

Figure 14−5. Slave Transmit Enable State Diagram

No Clock at UCLK

USPIEx = 0

Not Completed

USPIEx = 1

USPIEx = 0

Idle State

(Transmitter

Enabled)

USPIEx = 1

Handle Interrupt

Conditions

Transmit

Disable

Transmission

Active

External Clock

Present

Character

Transmitted

SWRST

USPIEx = 1

PUC

USPIEx = 0

USART Peripheral Interface, SPI Mode

14-7

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USART Operation: SPI Mode

Receive Enable

The SPI receive enable state diagrams are shown in Figure 14−6 and

Figure 14−7. When USPIEx = 0, UCLK is disabled from shifting data into the

RX shift register.

Figure 14−6. SPI Master Receive-Enable State Diagram

No Data Written

to UxTXBUF

USPIEx = 0

Not Completed

USPIEx = 1

Receiver

Collects

Character

Idle State

(Receiver

Enabled)

USPIEx = 1

Handle Interrupt

Conditions

Receive

Disable

Data Written

to UxTXBUF

USPIEx = 0

SWRST

Character

Received

USPIEx = 1

USPIEx = 0

PUC

Figure 14−7. SPI Slave Receive-Enable State Diagram

No Clock at UCLK

USPIEx = 0

Not Completed

USPIEx = 1

Receiver

Collects

Character

Idle State

(Receive

Enabled)

USPIEx = 1

Handle Interrupt

Conditions

Receive

Disable

External Clock

Present

USPIEx = 0

SWRST

Character

Received

USPIEx = 1

PUC

USPIEx = 0

14-8

USART Peripheral Interface, SPI Mode

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USART Operation: SPI Mode

14.2.5 Serial Clock Control

UCLK is provided by the master on the SPI bus. When MM = 1, BITCLK is

provided by the USART baud rate generator on the UCLK pin as shown in

Figure 14−8. When MM = 0, the USART clock is provided on the UCLK pin by

the master and, the baud rate generator is not used and the SSELx bits are

don’t care. The SPI receiver and transmitter operate in parallel and use the

same clock source for data transfer.

Figure 14−8. SPI Baud Rate Generator

SSEL1 SSEL0

...

N =

...

UxBR1

UxBR0

UCLKI

ACLK

BRCLK

16−Bit Counter

............

SMCLK

Q15

Toggle

Compare (0 or 1)

BITCLK

Modulation Data Shift Register

(LSB first)

Bit Start

UxMCTL

The 16-bit value of UxBR0+UxBR1 is the division factor of the USART clock

source, BRCLK. The maximum baud rate that can be generated in master

mode is BRCLK/2. The maximum baud rate that can be generated in slave

mode is BRCLK. The modulator in the USART baud rate generator is not used

for SPI mode and is recommended to be set to 000h. The UCLK frequency is

given by:

BRCLK

UxBR

Baud rate =

with UxBR= [UxBR1, UxBR0]

USART Peripheral Interface, SPI Mode

14-9

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USART Operation: SPI Mode

Serial Clock Polarity and Phase

The polarity and phase of UCLK are independently configured via the CKPL

and CKPH control bits of the USART. Timing for each case is shown in

Figure 14−9.

Figure 14−9. USART SPI Timing

Cycle#

UCLK

CKPH CKPL

UCLK

STE

SIMO/

SOMI

MSB

LSB

SIMO/

SOMI

Move to UxTXBUF

TX Data Shifted Out

RX Sample Points

14-10

USART Peripheral Interface, SPI Mode

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USART Operation: SPI Mode

14.2.6 SPI Interrupts

The USART has one interrupt vector for transmission and one interrupt vector

for reception.

SPI Transmit Interrupt Operation

The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF

is ready to accept another character. An interrupt request is generated if

UTXIEx and GIE are also set. UTXIFGx is automatically reset if the interrupt

request is serviced or if a character is written to UxTXBUF.

UTXIFGx is set after a PUC or when SWRST = 1. UTXIEx is reset after a PUC

or when SWRST = 1. The operation is shown is Figure 14−10.

Figure 14−10. Transmit Interrupt Operation

UTXIEx

SYNC = 1

Clear

PUC or SWRST

Interrupt Service Requested

Set

UTXIFGx

Character Moved From

Buffer to Shift Register

SWRST

Clear

Data moved to UxTXBUF

IRQA

Note: Writing to UxTXBUF in SPI Mode

Data written to UxTXBUF when UTXIFGx = 0 and USPIEx = 1 may result in

erroneous data transmission.

USART Peripheral Interface, SPI Mode

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USART Operation: SPI Mode

SPI Receive Interrupt Operation

The URXIFGx interrupt flag is set each time a character is received and loaded

into UxRXBUF as shown in Figure 14−11 and Figure 14−12. An interrupt

request is generated if URXIEx and GIE are also set. URXIFGx and URXIEx

are reset by a system reset PUC signal or when SWRST = 1. URXIFGx is

automatically reset if the pending interrupt is served or when UxRXBUF is

read.

Figure 14−11.Receive Interrupt Operation

SYNC

Valid Start Bit

SYNC = 1

URXS

Receiver Collects Character

URXSE

From URXD

Clear

URXIEx

Interrupt Service

Requested

BRK

(S)

URXEIE

URXIFGx

URXWIE

RXWAKE

Clear

SWRST

PUC

Character Received

UxRXBUF Read

URXSE

IRQA

Figure 14−12. Receive Interrupt State Diagram

SWRST = 1

URXIFGx = 0

URXIEx = 0

Wait For Next

Start

SWRST = 1

USPIEx = 0

Receive

Character

USPIEx = 0

USPIEx = 1

PUC

Interrupt

Service Started,

GIE = 0

Receive

Character

Completed

USPIEx = 1 and

URXIFGx = 1

Priority

URXIEx = 1 and

GIE = 1 and

URXIFGx = 0

Priority Valid

GIE = 0

Too

Low

14-12

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USART Registers: SPI Mode

14.3 USART Registers: SPI Mode

The USART registers, shown in Table 14−1 and Table 14−2, are byte

structured and should be accessed using byte instructions.

Table 14−1.USART0 Control and Status Registers

Short Form

U0CTL

U0TCTL

U0RCTL

U0MCTL

U0BR0

U0BR1

U0RXBUF

U0TXBUF

ME1

Initial State

USART control register

Transmit control register

Receive control register

Modulation control register

Baud rate control register 0

Baud rate control register 1

Receive buffer register

Transmit buffer register

SFR module enable register 1

Read/write

Read

070h

071h

072h

073h

074h

075h

076h

077h

004h

000h

002h

001h with PUC

000h with PUC

Unchanged

Read/write

Unchanged

†

000h with PUC

082h with PUC

†

SFR interrupt enable register 1

IE1

†

SFR interrupt flag register 1

IFG1

†

Does not apply to MSP430x12xx devices. Refer to the register definitions for registers and bit positions for these devices.

Table 14−2.USART1 Control and Status Registers

Short Form

U1CTL

U1TCTL

U1RCTL

U1MCTL

U1BR0

U1BR1

U1RXBUF

U1TXBUF

ME2

Initial State

USART control register

Transmit control register

Receive control register

Modulation control register

Baud rate control register 0

Baud rate control register 1

Receive buffer register

Transmit buffer register

SFR module enable register 2

SFR interrupt enable register 2

SFR interrupt flag register 2

Read/write

Read

078h

079h

07Ah

07Bh

07Ch

07Dh

07Eh

07Fh

005h

001h

003h

001h with PUC

000h with PUC

Unchanged

Read/write

Unchanged

000h with PUC

020h with PUC

IE2

IFG2

Note: Modifying the SFR bits

To avoid modifying control bits for other modules, it is recommended to set

or clear the IEx and IFGx bits using BIS.Bor BIC.Binstructions, rather than

MOV.Bor CLR.Binstructions.

USART Peripheral Interface, SPI Mode

14-13

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USART Registers: SPI Mode

UxCTL, USART Control Register

†

Unused

rw−0

Unused

rw−0

I2C

CHAR

rw−0

LISTEN

rw−0

SYNC

rw−0

SWRST

rw−1

rw−0

Unused

Bits

7−6

Unused

I2C mode enable. This bit selects I2C or SPI operation when SYNC = 1.

†

I2C

Bit 5

SPI mode

I C mode

CHAR

LISTEN

SYNC

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Character length

7-bit data

8-bit data

Listen enable. The LISTEN bit selects the loopback mode

Disabled

Enabled. The transmit signal is internally fed back to the receiver

Synchronous mode enable

UART mode

SPI mode

Master mode

USART is slave

USART is master

SWRST

Software reset enable

Disabled. USART reset released for operation

Enabled. USART logic held in reset state

†

Applies to USART0 on MSP430x15x and MSP430x16x devices only.

14-14

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USART Registers: SPI Mode

UxTCTL, USART Transmit Control Register

CKPH

rw−0

CKPL

rw−0

SSELx

Unused

rw−0

Unused

rw−0

STC

rw−0

TXEPT

rw−1

rw−0

CKPH

Bit 7

Clock phase select. Controls the phase of UCLK.

Normal UCLK clocking scheme

UCLK is delayed by one half cycle

CKPL

Bit 6

Clock polarity select

The inactive level is low; data is output with the rising edge of UCLK;

input data is latched with the falling edge of UCLK.

The inactive level is high; data is output with the falling edge of

UCLK; input data is latched with the rising edge of UCLK.

SSELx

Bits

5-4

Source select. These bits select the BRCLK source clock.

00 External UCLK (valid for slave mode only)

01 ACLK (valid for master mode only)

10 SMCLK (valid for master mode only)

11 SMCLK (valid for master mode only)

Unused

STC

Bit 3

Bit 2

Bit 1

Unused

Slave transmit control.

4-pin SPI mode: STE enabled.

3-pin SPI mode: STE disabled.

TXEPT

Bit 0

Transmitter empty flag. The TXEPT flag is not used in slave mode.

Transmission active and/or data waiting in UxTXBUF

UxTXBUF and TX shift register are empty

USART Peripheral Interface, SPI Mode

14-15

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USART Registers: SPI Mode

UxRCTL, USART Receive Control Register

Unused

rw−0

Unused

rw−0

Unused

rw−0

Unused

rw−0

Unused

rw−0

Unused

rw−0

Bit 7

Framing error flag. This bit indicates a bus conflict when MM = 1 and STC

= 0. FE is unused in slave mode.

No conflict detected

A negative edge occurred on STE, indicating bus conflict

Undefined

Bit 6

Bit 5

Unused

Overrun error flag. This bit is set when a character is transferred into

UxRXBUF before the previous character was read. OE is automatically

reset when UxRXBUF is read, when SWRST = 1, or can be reset by

software.

No error

Overrun error occurred

Unused

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Unused

14-16

USART Peripheral Interface, SPI Mode

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USART Registers: SPI Mode

UxBR0, USART Baud Rate Control Register 0

UxBR1, USART Baud Rate Control Register 1

UxBRx

The baud-rate generator uses the content of {UxBR1+UxBR0} to set the

baud rate. Unpredictable SPI operation occurs if UxBR < 2.

UxMCTL, USART Modulation Control Register

UxMCTLx

Bits

7−0

The modulation control register is not used for SPI mode and should be set

to 000h.

USART Peripheral Interface, SPI Mode

14-17

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USART Registers: SPI Mode

UxRXBUF, USART Receive Buffer Register

UxRXBUFx

Bits

7−0

The receive-data buffer is user accessible and contains the last received

character from the receive shift register. Reading UxRXBUF resets the OE

bit and URXIFGx flag. In 7-bit data mode, UxRXBUF is LSB justified and

the MSB is always reset.

UxTXBUF, USART Transmit Buffer Register

UxTXBUFx

Bits

7−0

The transmit data buffer is user accessible and contains current data to be

transmitted. When seven-bit character-length is used, the data should be

MSB justified before being moved into UxTXBUF. Data is transmitted MSB

first. Writing to UxTXBUF clears UTXIFGx.

14-18

USART Peripheral Interface, SPI Mode

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USART Registers: SPI Mode

ME1, Module Enable Register 1

†

USPIE0

rw−0

Bit 7

This bit may be used by other modules. See device-specific datasheet.

USART0 SPI enable. This bit enables the SPI mode for USART0.

†

USPIE0

Bit 6

Module not enabled

Module enabled

Bits

5-0

These bits may be used by other modules. See device-specific datasheet.

†

Does not apply to MSP430x12xx devices. See ME2 for the MSP430x12xx USART0 module enable bit

ME2, Module Enable Register 2

‡

USPIE1

rw−0

USPIE0

rw−0

Bits

7-5

These bits may be used by other modules. See device-specific datasheet.

USART1 SPI enable. This bit enables the SPI mode for USART1.

USPIE1

USPIE0

Bit 4

Module not enabled

Module enabled

Bits

3-1

These bits may be used by other modules. See device-specific datasheet.

‡

Bit 0

USART0 SPI enable. This bit enables the SPI mode for USART0.

Module not enabled

Module enabled

‡

MSP430x12xx devices only

USART Peripheral Interface, SPI Mode

14-19

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USART Registers: SPI Mode

IE1, Interrupt Enable Register 1

†

UTXIE0

rw−0

URXIE0

rw−0

†

UTXIE0

Bit 7

USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt.

Interrupt not enabled

Interrupt enabled

†

URXIE0

Bit 6

USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt.

Interrupt not enabled

Interrupt enabled

Bits

5-0

These bits may be used by other modules. See device-specific datasheet.

†

Does not apply to MSP430x12xx devices. See IE2 for the MSP430x12xx USART0 interrupt enable bits

IE2, Interrupt Enable Register 2

‡

UTXIE1

rw−0

URXIE1

rw−0

UTXIE0

rw−0

URXIE0

rw−0

Bits

7-6

These bits may be used by other modules. See device-specific datasheet.

USART1 transmit interrupt enable. This bit enables the UTXIFG1 interrupt.

UTXIE1

URXIE1

Bit 5

Interrupt not enabled

Interrupt enabled

Bit 4

USART1 receive interrupt enable. This bit enables the URXIFG1 interrupt.

Interrupt not enabled

Interrupt enabled

Bits

3-2

These bits may be used by other modules. See device-specific datasheet.

14-20

USART Peripheral Interface, SPI Mode

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USART Registers: SPI Mode

‡

UTXIE0

Bit 1

Bit 0

USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt.

Interrupt not enabled

Interrupt enabled

URXIE0

USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt for

USART0.

Interrupt not enabled

Interrupt enabled

‡

MSP430x12xx devices only

USART Peripheral Interface, SPI Mode

14-21

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USART Registers: SPI Mode

IFG1, Interrupt Flag Register 1

†

UTXIFG0

rw−1

URXIFG0

rw−0

†

UTXIFG0

Bit 7

Bit 6

USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty.

No interrupt pending

Interrupt pending

†

URXIFG0

USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received

a complete character.

No interrupt pending

Interrupt pending

Bits

5-0

These bits may be used by other modules. See device-specific datasheet.

†

Does not apply to MSP430x12xx devices. See IFG2 for the MSP430x12xx USART0 interrupt flag bits

IFG2, Interrupt Flag Register 2

‡

UTXIFG1

rw−1

URXIFG1

rw−0

UTXIFG0

rw−1

URXIFG0

rw−0

Bits

7-6

These bits may be used by other modules. See device-specific datasheet.

USART1 transmit interrupt flag. UTXIFG1 is set when U1TXBUF is empty.

UTXIFG1

URXIFG1

Bit 5

No interrupt pending

Interrupt pending

Bit 4

USART1 receive interrupt flag. URXIFG1 is set when U1RXBUF has received

a complete character.

No interrupt pending

Interrupt pending

Bits

3-2

These bits may be used by other modules. See device-specific datasheet.

‡

UTXIFG0

Bit 1

USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty.

No interrupt pending

Interrupt pending

‡

URXIFG0

Bit 0

USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received

a complete character.

No interrupt pending

Interrupt pending

‡

MSP430x12xx devices only

14-22

USART Peripheral Interface, SPI Mode

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USART Peripheral Interface, SPI Mode

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Chapter 15

USART Peripheral Interface, I²C Mode

The universal synchronous/asynchronous receive/transmit (USART)

peripheral interface supports I C communication in USART0. This chapter

describes the I C mode. The I C mode is implemented on the MSP430x15x

and MSP430x16x devices.

Topic

Page

15.1 I C Module Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2

15.2 I C Module Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

15.3 I C Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20

USART Peripheral Interface, I C Mode

15-1

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I C Module Introduction

15.1 I C Module Introduction

The inter-IC control (I C) module provides an interface between the MSP430

and I C-compatible devices connected by way of the two-wire I C serial bus.

External components attached to the I C bus serially transmit and/or receive

serial data to/from the USART through the 2-wire I C interface.

The I C module has the following features:

- Compliance to the Philips Semiconductor I C specification v2.1

Byte/word format transfer

7-bit and 10-bit device addressing modes

General call

START/RESTART/STOP

Multi-master transmitter/slave receiver mode

Multi-master receiver/slave transmitter mode

Combined master transmit/receive and receive/transmit mode

Standard mode up to100 kbps and fast mode up to 400 kbps support

- Built-in FIFO for buffered read and write

- Programmable clock generation

- 16-bit wide data access to maximize bus throughput

- Automatic data byte counting

- Designed for low power

- Slave receiver START detection for auto-wake up from LPMx modes

- Extensive interrupt capability

- Implemented on USART0 only

The I C block diagram is shown in Figure 15−1.

15-2

USART Peripheral Interface, I C Mode

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I C Module Introduction

Figure 15−1. USART Block Diagram: I C Mode

I2CEN

I2CSSELx

SYNC = 1

I2C = 1

I2CBUSY

I2C Clock Generator

No clock

ACLK

I2CIN

I2CPSC

I2CSCLL

I2CSCLH

I2CSCLLOW

SCL

SMCLK

I2CCLK

R/W

MST

I2CTRX

LISTEN

I2CRXOVR

Receive Shift Register

I2CSTP

I2CSTT

I2CSTB

SDA

Transmit Shift Register

I2CWORD

I2CSBD

I2CTXUDF

I2CNDATx

I2CDRW

I2COA

I2CSA

I2CRM

USART Peripheral Interface, I C Mode

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I C Module Operation

15.2 I C Module Operation

The I C module supports any slave or master I C-compatible device.

Figure 15−2 shows an example of an I C bus. Each I C device is recognized

by a unique address and can operate as either a transmitter or a receiver. A

device connected to the I C bus can be considered as the master or the slave

when performing data transfers. A master initiates a data transfer and gener-

ates the clock signal SCL. Any device addressed by a master is considered

a slave.

I C data is communicated using the serial data pin (SDA) and the serial clock

pin (SCL). Both SDA and SCL are bidirectional, and must be connected to a

positive supply voltage using a pull-up resistor.

Figure 15−2. I C Bus Connection Diagram

Device A

MSP430

Serial Data (SDA)

Serial Clock (SCL)

Device C

Device B

Note: SDA and SCL Levels

The MSP430 SDA and SCL pins must not be pulled up above the MSP430

level.

15-4

USART Peripheral Interface, I C Mode

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I C Module Operation

15.2.1 I C Module Initialization

The I C module is part of the USART peripheral. Individual bit definitions when

using USART0 in I C mode are different from that in SPI or UART mode. The

default value for the U0CTL register is the UART mode. To select I C operation

the SYNC and I2C bits must be set. After module initialization, the I C module

is ready for transmit or receive operation. Setting I2CEN releases the I C

module for operation.

Configuring and re-configuring the I C module must be done when I2CEN =

0 to avoid unpredictable behavior. Setting I2CEN = 0 has the following effects:

- I C communication stops

- SDA and SCL are high impedance

- I2CTCTL, bits 3-0 are cleared and bits 7-4 are unchanged

- I2CDCTL and I2CDR register is cleared

- Transmit and receive shift registers are cleared

- U0CTL, I2CNDAT, I2CPSC, I2CSCLL, I2CSCLH registers are unchanged

- I2COA, I2CSA, I2CIE, I2CIFG, and I2CIV registers are unchanged

When re-configuring the USART from I C mode to UART or SPI mode the I2C,

SYNC, and I2CEN bits must first be cleared, then the SWRST must be set and

the UART or SPI initialization procedure must be followed. Failure to follow this

procedure could result in unpredictable operation.

Note: Configuring the USART Module for I C Operation After Reset

The required I C configuration process is:

1) Select I C mode with SWRST = 1 (BIS.B #I2C + SYNC,&U0CTL)

2) Disable the I C module (BIC.B #I2CEN,&U0CTL)

3) Configure the I C module with I2CEN = 0

4) Set I2CEN via software (BIS.B #I2CEN,&U0CTL)

Failure to follow this process may result in unpredictable USART behavior.

Note: Re-Configuring the USART Module for UART or SPI Operation

When re-configuring the USART module for UART or SPI operation from I C

operation, the required process is:

1) Clear I2C, SYNC, and I2CEN (CLR.B &U0CTL)

2) Set SWRST (MOV.B #SWRST,&U0CTL)

3) Continue with UART or SPI initialization procedure.

Failure to follow this process may result in unpredictable USART behavior.

USART Peripheral Interface, I C Mode

15-5

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I C Module Operation

15.2.2 I C Serial Data

One clock pulse is generated by the master device for each data bit

transferred. The I C module operates with byte data. Data is transferred most

significant bit first as shown in Figure 15−3.

The first byte after a START condition consists of a 7-bit slave address and the

R/W bit. When R/W = 0, the master transmits data to a slave. When R/W = 1,

the master receives data from a slave. The ACK bit is sent from the receiver

after each byte on the 9th SCL clock.

Figure 15−3. I C Module Data Transfer

SDA

MSB

Acknowledgement

Signal From Receiver

Acknowledgement

Signal From Receiver

SCL

START

Condition (S)

STOP

R/W ACK

ACK

Condition (P)

START and STOP conditions are generated by the master and are shown in

Figure 15−3. A START condition is a high-to-low transition on the SDA line

while SCL is high. A STOP condition is a low-to-high transition on the SDA line

while SCL is high. The busy bit, I2CBB, is set after a START and cleared after

a STOP.

Data on SDA must be stable during the high period of SCL as shown in

Figure 15−4. The high and low state of SDA can only change when SCL is low,

otherwise START or STOP conditions will be generated.

Figure 15−4. Bit Transfer on the I C Bus

Data Line

Stable Data

SDA

SCL

Change of Data Allowed

15-6

USART Peripheral Interface, I C Mode

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I C Module Operation

15.2.3 I C Addressing Modes

The I C module supports 7-bit and 10-bit addressing modes.

7-Bit Addressing

In the 7-bit addressing format, shown in Figure 15−5, the first byte is the 7-bit

slave address and the R/W bit. The ACK bit is sent from the receiver after each

byte.

Figure 15−5. I C Module 7-Bit Addressing Format

Slave Address

R/W ACK

Data

ACK

Data

ACK

10-Bit Addressing

In the 10-bit addressing format, shown in Figure 15−6, the first byte is made

up of 11110b plus the two MSBs of the 10-bit slave address and the R/W bit.

The ACK bit is sent from the receiver after each byte. The next byte is the

remaining 8 bits of the 10-bit slave address, followed by the ACK bit and the

8-bit data.

Figure 15−6. I C Module 10-Bit Addressing Format

S Slave Address 1st byte R/W ACK Slave Address 2nd byte ACK

Data

ACK

Repeated START Conditions

The direction of data flow on SDA can be changed by the master, without first

stopping a transfer, by issuing a repeated START condition. This is called a

RESTART. After a RESTART is issued, the slave address is again sent out with

the new data direction specified by the R/W bit. The RESTART condition is

shown in Figure 15−7.

Figure 15−7. I C Module Addressing Format with Repeated START Condition

R/W ACK

ACK

R/W ACK

ACK

Slave Address

Data

Slave Address

Data

Any

Number

Any Number

USART Peripheral Interface, I C Mode

15-7

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I C Module Operation

15.2.4 I C Module Operating Modes

The I C module operates in master transmitter, master receiver, slave

transmitter, or slave receiver mode.

Master Mode

In master mode, transmit and receive operation is controlled with the I2CRM,

I2CSTT, and I2CSTP bits as described in Table 15−1. The master transmitter

and master receiver modes are shown in Figure 15−8 and Figure 15−9. SCL

is held low when the intervention of the CPU is required after a byte has been

received or transmitted.

Table 15−1.Master Operation

I2CRM I2CSTP I2CSTT

Condition Or Bus Activity

The I C module is in master mode, but is idle. No

START or STOP condition is generated.

Setting I2CSTT initiates activity. I2CNDAT is used to

determine length of transmission. A STOP condition is

not automatically generated after the I2CNDAT

number of bytes have been transferred. Software must

set I2CSTP to generate a STOP condition at the end

of transmission. This is used for RESTART conditions.

I2CNDAT is used to determine length of transmission.

Setting I2CSTT initiates activity. A STOP condition is

automatically generated after I2CNDAT number of

bytes have been transferred.

I2CNDAT is not used to determine length of

transmission. Software must control the length of the

transmission. Setting the I2CSTT bit initiates activity.

Software must set the I2CSTP bit to initiate a STOP

condition and stop activity. This mode is useful if > 255

bytes are to be transferred.

Setting the I2CSTP bit generates a STOP condition on

the bus after I2CNDAT number of bytes have been

sent, or immediately if I2CNDAT number of bytes have

already been sent.

Setting the I2CSTP bit generates a STOP condition on

the bus after the current transmission completes, or

immediately if no transmission is currently active.

Reserved, no bus activity.

15-8

USART Peripheral Interface, I C Mode

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I C Module Operation

Figure 15−8. Master Transmitter Mode

IDLE

I2CSTT=1

*When I2RM=1, I2CSTP must be set before the last I2CDR value

is written. Othwerwise, correct STOP generation will not occur.

4 x I2CPSC

Generate START

I2CBUSY Is Set

8 x I2CPSC

XA=1

I2CBB Is Set

I2CSTT Is Cleared

8 x SCL

No ACK

Send Slave Address

Bits 9−8 Extended

with R/W = 0

NACKIFG Is Set

XA=0

8 x SCL

Send Slave

Address Bits 6−0

with R/W=0

IDLE

Send Slave Address

Bits 7−0

I2CBUSY Is Cleared

No Ack

Ack

I2CRM=0

Yes

I2CNDAT

Number Of Bytes

Sent?

Repeat Mode?

I2CRM=1

STOP State?

I2CDR Empty

Yes I2CSTP=1

Yes

10 x I2CPSC

STOP State?

I2CDR Loaded?*

I2CDR Written

Generate STOP

I2CBB Is Cleared

Yes

8 x I2CPSC

8 x SCL

Send I2CDR

Low Byte

No Ack

Ack

I2CSTP, I2CMST

Are Cleared

Ack, and

I2CWORD=0

Send I2CDR

High Byte

No Ack

Ack

IDLE

I2CBUSY Is Cleared

New START?

Yes

USART Peripheral Interface, I C Mode

15-9

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I C Module Operation

Figure 15−9. Master Receiver Mode

IDLE

I2CSTT=1

Yes

4 x I2CPSC

Generate START

8 x I2CPSC

New START?

I2CBB Is Set

I2CSTT Is Cleared

XA = 1

8 x SCL

Send Slave Address

Bits 9−8 Extended

With R/W = 0

XA = 0

No Ack

8 x SCL

Send Slave Address

Bits 7−0

NACKIFG Is Set

4 x I2CPSC

Generate 2nd START

IDLE

I2CBUSY Is Cleared

8 x SCL

Send Slave

Send Slave Address

Bits 9−8 Extended

With R/W = 1

Address Bits 6−0

with R/W = 1

I2CRM=0

Repeat Mode?

Ack

No Ack

I2CNDAT

Number Of Bytes

Received?

I2CRM=1

8 x SCL

Receive Data

Low Byte

STOP State?

Yes

STOP State?

1 x SCL

8 x SCL

Generate Ack

For Low Byte

Yes, I2CSTP=1

Generate STOP

10 x I2CPSC

8 x I2CPSC

Receive Data

High Byte

I2CWORD=0

1 x SCL

Generate Ack

For High Byte

I2CBB Is Cleared

New START?

Yes

I2CSTP, I2CMST

Are Cleared

New START?

Yes

IDLE

I2CBUSY Is Cleared

15-10

USART Peripheral Interface, I C Mode

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I C Module Operation

Arbitration

If two or more master transmitters simultaneously start a transmission on the

bus, an arbitration procedure is invoked. Figure 15−10 illustrates the

arbitration procedure between two devices. The arbitration procedure uses

the data presented on SDA by the competing transmitters. The first master

transmitter that generates a logic high is overruled by the opposing master

generating a logic low. The arbitration procedure gives priority to the device

that transmits the serial data stream with the lowest binary value. The master

transmitter that lost arbitration switches to the slave receiver mode, and sets

the arbitration lost flag ALIFG. If two or more devices send identical first bytes,

arbitration continues on the subsequent bytes.

Figure 15−10. Arbitration Procedure Between Two Master Transmitters

Bus Line

SCL

Device #1 Lost Arbitration

and Switches Off

Data From

Device #1

Data From

Device #2

Bus Line

SDA

If the arbitration procedure is in progress when a repeated START condition

or STOP condition is transmitted on SDA, the master transmitters involved in

arbitration must send the repeated START condition or STOP condition at the

same position in the format frame. Arbitration is not allowed between:

- A repeated START condition and a data bit

- A STOP condition and a data bit

- A repeated START condition and a STOP condition

USART Peripheral Interface, I C Mode

15-11

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I C Module Operation

Automatic Data Byte Counting

Automatic data byte counting is supported in master mode with the I2CNDAT

is written to I2CNDAT. A STOP condition is automatically generated after

I2CNDAT number of bytes have been transferred.

Note: I2CNDAT Register

Do not change the I2CNDAT register while I2CBB = 1 and I2CRM = 0.

Otherwise, unpredictable operation may occur.

Slave Mode

In slave mode, transmit and receive operations are controlled automatically by

the I C module. The slave transmitter and slave receiver modes are shown in

Figure 15−11 and Figure 15−12.

In slave receiver mode, serial data bits received on SDA are shifted in with the

clock pulses that are generated by the master device. The slave device does

not generate the clock, but it can hold SCL low if intervention of the CPU is

required after a byte has been received. In slave receiver mode, every byte

received will be acknowledged. There is no way for a slave to generate a

NACK condition for received data.

Slave transmitter mode is entered when the slave address byte transmitted by

the master is the same as its own address and a set R/W bit has been

transmitted indicating a request to send data to the master. The slave

transmitter shifts the serial data out on SDA with the clock pulses that are

generated by the master device. The slave device does not generate the clock,

but it will hold SCL low while intervention of the CPU is required after a byte

has been transmitted.

Note: I2CTRX Bit In Slave Mode

The I2CTRX bit must be cleared for proper slave mode operation.

15-12

USART Peripheral Interface, I C Mode

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I C Module Operation

Figure 15−11.Slave Transmitter

IDLE

OAIFG Set If Not

RESTART

START

Detected?

I2CDR Empty

Yes

I2CDR Loaded?

Yes

STTIFG Is Set

I2CBUSY Is Set

4 x I2CPSC

I2CBB Is Set

XA = 1

8 x SCL

XA = 0

Send Data

Low Byte

To Master

8 x SCL

Receive Slave

Address Bits 9−8

with R/W = 0

Receive Slave

Address Bits 6−0

with R/W = 1

No Ack

Ack

Send Data

High Byte

To Master

Match

Matched I2COA

No Ack

Ack

1 x SCL

8 x SCL

1 x SCL

Ack and

I2CWORD=0

Send

Acknowledge

Send

Acknowledge

STOP Detected?

Match

Receive Slave

Address Bits 7−0

RESTART

Detected?

Matched I2COA

Yes

1 x SCL

4 x I2CPSC

Send

Yes

Acknowledge

Send

Acknowledge

I2CBB Is Cleared

13 x I2CPSC

OAIFG Set If Not

RESTART

8 x SCL

I2CBUSY Is

Cleared

Receive Slave

Address Bits 9−8

with R/W=1

2nd Start

Detected?

Yes

STTIFG Is Set

IDLE

Data

on SDA?

Enter Slave Receive

mode at ”1”

Yes

USART Peripheral Interface, I C Mode

15-13

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I C Module Operation

Figure 15−12. Slave Receiver

IDLE

START

Detected?

RESTART

Detected ?

Yes

STTIFG Is Set

I2CBUSY Is Set

From Slave

Transmit Mode

4 x I2CPSC

I2CBB Is Set

8 x SCL

1 x SCL

Receive Data

Low Byte

From Master

XA = 1

XA = 0

8 x SCL

Receive Slave

Address Bits 6−0

with R/W = 0

Address Bits 9−8

with R/W = 0

Send

Acknowledge

Match

8 x SCL

1 x SCL

Receive Data

High Byte

From Master

Matched I2COA

1 x SCL

8 x SCL

1 x SCL

I2CWORD=0

Byte Mode

Send

Acknowledge

Send

Acknowledge

Send

Acknowledge

Match

Receive Slave

Address Bits 7−0

OAIFG Set If Not

RESTART

Matched I2COA

Stop State?

1 x SCL

Send

Acknowledge

Yes

4 x I2CPSC

1 x I2CPSC

I2CBB Is Cleared

I2CBUSY Is

Cleared

IDLE

15-14

USART Peripheral Interface, I C Mode

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I C Module Operation

15.2.5 The I C Data Register I2CDR

The I2CDR register can be accessed as an 8-bit or 16-bit register selected by

the I2CWORD bit. The I2CDR register functions as described in Table 15−2.

When I2CWORD = 1, any attempt to modify the register with a byte instruction

will fail and the register will not be modified.

Table 15−2.I2CDR Register Function

I2CWORD

I2CDR Function

I2CTRX

Byte mode transmit: Only the low byte is used. The byte is

double buffered. If a new byte is written before the previous

byte has been transmitted, the new byte is held in a

temporary buffer before being latched into the I2CDR low

byte. TXRDYIFG is set when I2CDR is ready to be accessed.

I2CDR should be written after I2CSTT is set.

Byte mode receive: Only the low byte is used. The byte is

double buffered. If a new byte is received before the previous

byte has been read, the new byte is held in a temporary buffer

before being latched into the I2CDR low byte. RXRDYIFG is

set when I2CDR is ready to be read.

Word mode transmit: The low byte of the word is sent first,

then the high byte. The register is double buffered. If a new

word is written before the previous word has been

transmitted, the new word is held in a temporary buffer before

being latched into the I2CDR register. TXRDYIFG is set

when I2CDR is ready to be accessed. I2CDR should be

written after I2CSTT is set.

Word mode receive: The low byte of the word was received

first, then the high byte. The register is double buffered. If a

new word is received before the previous word has been

read, the new word is held in a temporary buffer before being

latched into the I2CDR register. RXRDYIFG is set when

I2CDR is ready to be accessed.

Transmit Underflow

In master mode, underflow occurs when the transmit shift register and the

transmit buffer are empty. In slave mode, underflow occurs when the transmit

shift register and the transmit buffer are empty and the external I C master still

requests data. When transmit underflow occurs, the I2CTXUDF bit is set.

Writing data to the I2CDR register or resetting the I2CEN bit resets I2CTXUDF.

I2CTXUDF is used in transmit mode only.

Receive Overrun

Receive overrun occurs when the receive shift register is full and the receive

buffer is full. The I2CRXOVR bit is set when receive overrun occurs. No data

is lost because SCL is held low in this condition, which stops further bus

activity. Reading the I2CDR register or resetting I2CEN resets I2CRXOVR.

The I2CRXOVR bit is used in receive mode only.

USART Peripheral Interface, I C Mode

15-15

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I C Module Operation

15.2.6 I C Clock Generation and Synchronization

The I C module is operated with the clock source selected by the I2CSSELx

bits. The prescaler, I2CPSC, and the I2CSCLH and I2CSCLL registers

determine the frequency and duty cycle of the SCL clock signal for master

mode as shown in Figure 15−13.

Note: I2CCLK Maximum Frequency

The I C module clock source I2CIN must be at least 10x the SCL frequency

in both master and slave modes. This condition is met automatically in

master mode by the I2CSCLL and I2CSCLH registers.

Note: I2CPSC Value

When I2CPSC > 4, unpredictable operation can result. The I2CSCLL and

I2CSCLH registers should be used to set the SCL frequency.

Figure 15−13. I C Module SCL Generation

I2CIN

I2CPSC

I2CCLK

(I2CPSC +2) x (I2CSCLH + 1) (I2CPSC + 2) x (I2CSCLL + 1)

During the arbitration procedure the clocks from the different masters must be

synchronized. A device that first generates a low period on SCL overrules the

other devices forcing them to start their own low periods. SCL is then held low

by the device with the longest low period. The other devices must wait for SCL

to be released before starting their high periods. Figure 15−14 illustrates the

clock synchronization. This allows a slow slave to slow down a fast master.

Figure 15−14. Synchronization of Two I C Clock Generators During Arbitration

Wait

Start HIGH

State

Period

SCL From

Device #1

SCL From

Device #2

Bus Line

SCL

15-16

USART Peripheral Interface, I C Mode

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I C Module Operation

15.2.7 Using the I C Module with Low Power Modes

The I C module can be used with MSP430 low-power modes. When the

internal clock source for the I C module is present, the module operates

normally regardless of the MSP430 operating mode. When the internal clock

source for the I C module is not present, automatic clock activation is

provided. When the I C module is in the idle state, I2CBUSY = 0, and the I C

clock source I2CIN is disconnected from the I C module state machine, saving

power.

When the I C clock source is inactive, the I C module automatically activates

the selected clock source when needed, regardless of the control-bit settings

for the clock source. The clock source remains active until the I C module

returns to idle condition. After the I C module returns to the idle condition,

control of the clock-source reverts to the settings of its control bits.

Automatic I C clock activation occurs when:

- In master mode, clock activation occurs when I2CSTT = 1 and remains

active until the transfer completes and the I C module returns to the idle

condition.

- In slave mode, clock activation occurs when a START condition is

detected and remains active until the transfer completes and the I C

module returns to the idle condition. After detection of the START

condition, the STTIFG flag is set, and the module holds the SCL line low

until the clock source becomes active. Once the source is active, the I C

module releases the SCL line to the master.

When the I C module activates an inactive clock source, the clock source

becomes active for the whole device and any peripheral configured to use the

clock source may be affected. For example, a timer using SMCLK will

increment while the I C module forces SMCLK active.

USART Peripheral Interface, I C Mode

15-17

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I C Module Operation

15.2.8 I C Interrupts

The I C module has one interrupt vector for eight interrupt flags listed in Table

15−3. Each interrupt flag has its own interrupt enable bit. When an interrupt

is enabled, and the GIE bit is set, the interrupt flag will generate an interrupt

request.

Table 15−3.I C Interrupts

Interrupt Condition

Interrupt

Flag

Arbitration-lost. Arbitration can be lost when two or more transmitters

start a transmission simultaneously, or when the software attempts

to initiate an I C transfer while I2CBB = 1. The ALIFG flag is set when

ALIFG

arbitration has been lost. When ALIFG is set the MST and I2CSTP

bits are cleared and the I C controller becomes a slave receiver.

No-acknowledge interrupt. This flag is set when an acknowledge is

expected but is not received in master mode. NACKIFG is used in

master mode only.

NACKIFG

Own-address interrupt. This flag is set when another master has

addressed the I C module. OAIFG is used in slave mode only.

OAIFG

below conditions.

ARDYIFG

Master transmitter, I2CRM = 0: All data sent

Master transmitter, I2CRM = 1: All data sent and I2CSTP set

Master receiver, I2CRM = 0: I2CNDAT number of bytes received and

all data read from I2CDR

Master receiver, I2CRM = 1: Last byte of data received, I2CSTP set,

and all data read from I2CDR

Slave transmitter: STOP condition detected

Slave receiver: STOP condition detected and all data read from

I2CDR

Receive ready interrupt/status. This flag is set when the I C module

RXRDYIFG

TXRDYIFG

has received new data. RXRDYIFG is automatically cleared when

I2CDR is read and the receive buffer is empty. A receiver overrun is

indicated if bit I2CRXOVR = 1. RXRDYIFG is used in receive mode

only.

Transmit ready interrupt/status. This flag is set when the I C module

is ready for new transmit data (master transmit mode) or when

another master is requesting data (slave transmit mode). TXRDYIFG

is automatically cleared when I2CDR and the transmit buffer are full.

A transmit underflow is indicated if I2CTXUDF = 1. Unused in receive

mode.

General call interrupt. This flag is set when the I C module received

GCIFG

the general call address (00h). GCIFG is used in receive mode only.

START condition detected interrupt. This flag is set when the I C

STTIFG

module detects a START condition while in slave mode. This allows

the MSP430 to be in a low power mode with the I C clock source

inactive until a master initiates I C communication. STTIFG is used

in slave mode only.

15-18

USART Peripheral Interface, I C Mode

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I C Module Operation

I2CIV, Interrupt Vector Generator

The I C interrupt flags are prioritized and combined to source a single interrupt

vector. The interrupt vector register I2CIV is used to determine which flag

requested an interrupt. The highest priority enabled interrupt generates a

number in the I2CIV register that can be evaluated or added to the program

counter to automatically enter the appropriate software routine. Disabled I C

interrupts do not affect the I2CIV value. When RXDMAEN = 1, RXRDYIFG will

not affect the I2CIV value and when TXDMAEN = 1, TXRDYIFG will not affect

the I2CIV value, regardless of the state of RXRDYIE or TXRDYIE.

Any access, read or write, of the I2CIV register automatically resets the highest

pending interrupt flag. If another interrupt flag is set, another interrupt is

immediately generated after servicing the initial interrupt.

I2CIV Software Example

The following software example shows the recommended use of I2CIV. The

I2CIV value is added to the PC to automatically jump to the appropriate routine.

I2C_ISR

ADD &I2CIV, PC ; Add offset to jump table

RETI

JMP ALIFG_ISR

; Vector 0: No interrupt

; Vector 2: ALIFG

JMP NACKIFG_ISR ; Vector 4: NACKIFG

JMP OAIFG_ISR ; Vector 6: OAIFG

JMP ARDYIFG_ISR ; Vector 8: ARDYIFG

JMP RXRDYIFG_ISR; Vector 10: RXRDYIFG

JMP TXRDYIFG_ISR; Vector 12: TXRDYIFG

JMP GCIFG_ISR

STTIFG_ISR

; Vector 14: GCIFG

; Vector 16

...

RETI

; Task starts here

; Return

ALIFG_ISR

; Vector 2

...

RETI

; Task starts here

; Return

NACKIFG_ISR

...

; Vector 4

; Task starts here

; Return

RETI

OAIFG_ISR

; Vector 6

...

RETI

; Task starts here

; Return

ARDYIFG_ISR

...

RETI

RXRDYIFG_ISR

; Vector 8

; Task starts here

; Return

; Vector 10

...

RETI

; Task starts here

; Return

TXRDYIFG_ISR

; Vector 12

...

RETI

; Task starts here

; Return

GCIFG_ISR

; Vector 14

...

RETI

; Task starts here

; Return

USART Peripheral Interface, I C Mode

15-19

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I C Module Registers

15.3 I C Module Registers

The I C module registers are listed in Table 15−4.

Table 15−4.I C Registers

Short Form

I2CIE

Initial State

I C interrupt enable

Read/write

Read only

Read/write

050h

051h

052h

070h

071h

072h

073h

074h

075h

076h

0118h

011Ah

011Ch

Reset with PUC

001h with PUC

Reset with PUC

I C interrupt flag

I2CIFG

I C data count

I2CNDAT

U0CTL

USART control

I C transfer control

I2CTCTL

I2CDCTL

I2CPSC

I2CSCLH

I2CSCLL

I C data control

I C prescaler

I C SCL high

I C SCL low

I C data

I2CDRW/I2CDRB Read/write

I C own address

I2COA

I2CSA

I2CIV

Read/write

Read only

I C slave address

I C interrupt vector

15-20

USART Peripheral Interface, I C Mode

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I C Module Registers

U0CTL, USART0 Control Register-I C Mode

RXDMAEN

rw−0

TXDMAEN

rw−0

I2C

rw−0

LISTEN

rw−0

SYNC

rw−0

MST

I2CEN

rw−1

rw−0

RXDMAEN

TXDMAEN

Bit 7

Receive DMA enable. This bit enables the DMA controller to be used to

transfer data from the I C module after the I C modules receives data. When

RXDMAEN = 1, RXRDYIE is ignored.

Disabled

Enabled

Bit 6

Transmit DMA enable. This bit enables the DMA controller to be used to

provide data to the I C module for transmission. When TXDMAEN = 1,

TXRDYIE, is ignored.

Disabled

Enabled

I2C

Bit 5

Bit 4

Bit 3

I C mode enable. This bit select I C or SPI operation when SYNC = 1.

SPI mode

I C mode

Extended Addressing

7-bit addressing

10-bit addressing

LISTEN

Listen. This bit selects loopback mode. LISTEN is only valid when MST = 1

and I2CTRX = 1 (master transmitter).

Normal mode

SDA is internally fed back to the receiver (loopback).

SYNC

MST

Bit 2

Bit 1

Synchronous mode enable

UART mode

SPI or I C mode

Master. This bit selects master or slave mode. The MST bit is automatically

cleared when arbitration is lost or a STOP condition is generated.

Slave mode

Master mode

I2CEN

Bit 0

I C enable. The bit enables or disables the I C module. The initial condition

for this bit is set, and SWRST function for UART or SPI. When the I2C and

SYNC bits are first set after a PUC, this bit becomes I2CEN function and is

automatically cleared.

I C operation is disabled

I C operation is enabled

USART Peripheral Interface, I C Mode

15-21

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I C Module Registers

I2CTCTL, I C Transmit Control Register

I2CWORD

rw−0

I2CRM

rw−0

I2CSSELx

rw−0

I2CTRX

rw−0

I2CSTB

rw−0

I2CSTP

rw−0

I2CSTT

rw−0

Modifiable only when I2CEN = 0

I2CWORD

I2CRM

Bit 7

Bit 6

I C word mode. Selects byte or word mode for the I C data register.

Byte mode

Word mode

I C repeat mode

I2CNDAT defines the number of bytes transmitted.

Number of bytes transmitted is controlled by software. I2CNDAT is

unused.

I2CSSELx

Bits

5−4

I C clock source select. When MST = 1 and arbitration is lost, the external SCL

signal is automatically used.

00 No clock − I C module is inactive

01 ACLK

10 SMCLK

11 SMCLK

I2CTRX

Bit 3

I C transmit. This bit selects the transmit or receive function for the I C

controller when MST = 1. When MST = 0, the R/W bit of the address byte

defines the data direction. I2CTRX must be reset for proper slave mode

operation.

Receive mode. Data is received on the SDA pin.

Transmit mode. Data transmitted on the SDA pin.

I2CSTB

I2CSTP

I2CSTT

Bit 2

Bit 1

Bit 0

Start byte. Setting the I2CSTB bit when MST = 1 initiates a start byte when

I2CSTT = 1. After the start byte is initiated, I2CSTB is automatically cleared.

No action

Send START condition and start byte (01h), but no STOP condition.

STOP bit. This bit is used to generate STOP condition. After the STOP

condition, the I2CSTP is automatically cleared.

No action

Send STOP condition

START bit. This bit is used to generate a START condition. After the start

condition the I2CSTT is automatically cleared.

No action

Send START condition

15-22

USART Peripheral Interface, I C Mode

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I C Module Registers

I2CDCTL, I C Data Control Register

Unused

I2C

SCLLOW

I2CBUSY

r−0

I2CSBD

r−0

I2CTXUDF

r−0

I2CRXOVR

I2CBB

r−0

Unused

Bits

Unused. Always read as 0.

7−6

I2CBUSY

Bit 5

I C busy

I C module is idle

I C module is not idle

I2C

SCLLOW

Bit 4

Bit 3

Bit 2

I C SCL low. This bit indicates if a slave is holding the SCL line low while the

MSP430 is the master and is unused in slave mode.

SCL is not being held low

SCL is being held low

I2CSBD

I C single byte data. This bit indicates if the receive register I2CDRW holds

a word or a byte. I2CSBD is valid only when I2CWORD = 1.

A complete word was received

Only the lower byte in I2CDR is valid

I2CTXUDF

I C transmit underflow

No underflow occurred

Transmit underflow occurred

I2CRXOVR

I2CBB

Bit 1

Bit 0

I C receive overrun

No receive overrun occurred

Receiver overrun occurred

I C bus busy bit. A START condition sets I2CBB to 1. I2CBB is reset by a

STOP condition or when I2CEN=0.

I C bus not busy

I C bus busy

USART Peripheral Interface, I C Mode

15-23

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I C Module Registers

I2CDRW, I2CDRB, I C Data Register

I2CDRW High Byte

rw−0

I2CDRW Low Byte

I2CDRB

rw−0

I2CDRW/

I2CDRB

Bits

15−8

I C Data. When I2CWORD = 1, the register name is I2CDRW. When

I2CWORD = 0, the name is I2CDRB. When I2CWORD = 1, any attempt to

modify the register with a byte instruction will fail and the register will not be

updated.

I2CNDAT, I C Transfer Byte Count Register

I2CNDATx

rw−0

I2CNDATx

Bits

7−0

I C number of bytes. This register supports automatic data byte counting for

master mode. In word mode, I2CNDATx must be an even value.

15-24

USART Peripheral Interface, I C Mode

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I C Module Registers

I2CPSC, I C Clock Prescaler Register

I2CPSCx

rw−0

Modifiable only when I2CEN = 0

I2CPSCx

Bits

7−0

I C clock prescaler. The I C clock input I2CIN is divided by the I2CPSCx value

to produce the internal I C clock frequency. The division rate is I2CPSCx+1.

I2CPSCx values > 4 are not recommended. The I2CSCLL and I2CSCLH

registers should be used to set the SCL frequency.

000h Divide by 1

001h Divide by 2

0FFh Divide by 256

USART Peripheral Interface, I C Mode

15-25

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I C Module Registers

I2CSCLH, I C Shift Clock High Register

I2CSCLHx

rw−0

Modifiable only when I2CEN = 0

I2CSCLHx

Bits

7−0

I C shift clock high. These bits define the high period of SCL when the I C

controller is in master mode. The SCL high period is (I2CSCLH+2) x (I2CPSC

+ 1).

000h SCL high period = 5 x (I2CPSC + 1)

001h SCL high period = 5 x (I2CPSC + 1)

002h SCL high period = 5 x (I2CPSC + 1)

003h SCL high period = 5 x (I2CPSC + 1)

004h SCL high period = 6 x (I2CPSC + 1)

0FFh SCL high period = 257 x (I2CPSC + 1)

I2CSCLL, I C Shift Clock Low Register

I2CSCLLx

rw−0

Modifiable only when I2CEN = 0

I2CSCLLx

Bits

7−0

I C shift clock low. These bits define the low period of SCL when the I C

controller is in master mode. The SCL low period is (I2CSCLL+2) x (I2CPSC

+ 1).

000h SCL low period = 5 x (I2CPSC + 1)

001h SCL low period = 5 x (I2CPSC + 1)

002h SCL low period = 5 x (I2CPSC + 1)

003h SCL low period = 5 x (I2CPSC + 1)

004h SCL low period = 6 x (I2CPSC + 1)

0FFh SCL low period = 257 x (I2CPSC + 1)

15-26

USART Peripheral Interface, I C Mode

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I C Module Registers

I2COA, I C Own Address Register, 7-Bit Addressing Mode

I2COAx

rw−0

Modifiable only when I2CEN = 0

I2COAx

Bits

I C own address. The I2COA register contains the local address of the

15-0

MSP430 I C controller. The I2COA register is right-justified. Bit 6 is the MSB.

Bits 15-7 are always 0.

I2COA, I C Own Address Register, 10-Bit Addressing Mode

I2COAx

rw−0

I2COAx

rw−0

Modifiable only when I2CEN = 0

I2COAx

Bits

I C own address. The I2COA register contains the local address of the

15-0

MSP430 I C controller. The I2COA register is right-justified. Bit 9 is the MSB.

Bits 15-10 are always 0.

USART Peripheral Interface, I C Mode

15-27

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I C Module Registers

I2CSA, I C Slave Address Register, 7-Bit Addressing Mode

I2CSAx

rw−0

I2CSAx

Bits

15-0

I C slave address. The I2CSA register contains the slave address of the

external device to be addressed by the MSP430. It is only used in master

mode. The I2CSA register is right-justified. Bit 6 is the MSB. Bits 15-7 are

always 0.

I2CSA, I C Slave Address Register, 10-Bit Addressing Mode

I2CSAx

rw−0

I2CSAx

rw−0

I2CSAx

Bits

15-0

I C slave address. The I2CSA register contains the slave address of the

external device to be addressed by the MSP430. It is only used in master

mode. The I2CSA register is right-justified. Bit 9 is the MSB. Bits 15-10 are

always 0.

15-28

USART Peripheral Interface, I C Mode

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I C Module Registers

I2CIE, I C Interrupt Enable Register

STTIE

rw−0

GCIE

rw−0

TXRDYIE

rw−0

RXRDYIE

rw−0

ARDYIE

rw−0

OAIE

rw−0

NACKIE

ALIE

rw−0

STTIE

Bit 7

START detect interrupt enable

Interrupt disabled

Interrupt enabled

GCIE

Bit 6

Bit 5

General call interrupt enable

Interrupt disabled

Interrupt enabled

TXRDYIE

Transmit ready interrupt enable. When TXDMAEN = 1, TXRDYIE is ignored

and TXRDYIFG will not generate an interrupt.

Interrupt disabled

Interrupt enabled

RXRDYIE

Bit 4

Receive ready interrupt enable. When RXDMAEN = 1, RXRDYIE is ignored

and RXRDYIFG will not generate an interrupt.

Interrupt disabled

Interrupt enabled

ARDYIE

OAIE

Bit 3

Bit 2

Access ready interrupt enable

Interrupt disabled

Interrupt enabled

Own address interrupt enable

Interrupt disabled

Interrupt enabled

NACKIE

ALIE

Bit 1

Bit 0

No acknowledge interrupt enable

Interrupt disabled

Interrupt enabled

Arbitration lost interrupt enable

Interrupt disabled

Interrupt enabled

USART Peripheral Interface, I C Mode

15-29

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I C Module Registers

I2CIFG, I C Interrupt Flag Register

STTIFG

rw−0

GCIFG

rw−0

TXRDYIFG

rw−0

RXRDYIFG

rw−0

ARDYIFG

rw−0

OAIFG

rw−0

NACKIFG

rw−0

ALIFG

rw−0

STTIFG

Bit 7

START detect interrupt flag

No interrupt pending

Interrupt pending

GCIFG

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

General call interrupt flag

No interrupt pending

Interrupt pending

TXRDYIFG

RXRDYIFG

ARDYIFG

OAIFG

Transmit ready interrupt flag

No interrupt pending

Interrupt pending

Receive ready interrupt flag

No interrupt pending

Interrupt pending

Access ready interrupt flag

No interrupt pending

Interrupt pending

Own address interrupt flag

No interrupt pending

Interrupt pending

NACKIFG

ALIFG

Bit 1

Bit 0

No acknowledge interrupt flag

No interrupt pending

Interrupt pending

Arbitration lost interrupt flag

No interrupt pending

Interrupt pending

15-30

USART Peripheral Interface, I C Mode

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I C Module Registers

I2CIV, I C Interrupt Vector Register

I2CIVx

r−0

I2CIVx

Bits

15-0

I C interrupt vector value

I2CIV

Contents

Interrupt

Flag

Interrupt

Priority

Interrupt Source

No interrupt pending

Arbitration lost

000h

−

002h

ALIFG

Highest

004h

No acknowledgement

Own address

NACKIFG

OAIFG

006h

008h

Receive data ready

Transmit data ready

General call

ARDYIFG

RXRDYIFG

TXRDYIFG

GCIFG

00Ah

00Ch

00Eh

010h

START condition received

STTIFG

Lowest

USART Peripheral Interface, I C Mode

15-31

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15-32

USART Peripheral Interface, I C Mode

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Chapter 16

Comparator_A

Comparator_A is an analog voltage comparator. This chapter describes

Comparator_A. Comparator_A is implemented in MSP430x11x1,

MSP430x12x, MSP430x13x, MSP430x14x, MSP430x15x and MSP430x16x

devices.

Topic

Page

16.1 Comparator_A Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2

16.2 Comparator_A Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4

16.3 Comparator_A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9

Comparator_A

16-1

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Comparator_A Introduction

16.1 Comparator_A Introduction

The comparator_A module supports precision slope analog-to-digital

conversions, supply voltage supervision, and monitoring of external analog

signals.

Features of Comparator_A include:

- Inverting and non-inverting terminal input multiplexer

- Software selectable RC-filter for the comparator output

- Output provided to Timer_A capture input

- Software control of the port input buffer

- Interrupt capability

- Selectable reference voltage generator

- Comparator and reference generator can be powered down

The Comparator_A block diagram is shown in Figure 16−1.

16-2

Comparator_A

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Comparator_A Introduction

Figure 16−1. Comparator_A Block Diagram

CAEX

P2CA0

CAON

CAF

CA0

CA1

CCI1B

−

CAOUT

−

Set_CAIFG

Tau ~ 2.0ms

P2CA1

CAREFx

CARSEL

0.5x

CAREF

0.25x

Comparator_A

16-3

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Comparator_A Operation

16.2 Comparator_A Operation

The comparator_A module is configured with user software. The setup and

operation of comparator_A is discussed in the following sections.

16.2.1 Comparator

The comparator compares the analog voltages at the + and – input terminals.

If the + terminal is more positive than the – terminal, the comparator output

CAOUT is high. The comparator can be switched on or off using control bit

CAON. The comparator should be switched off when not in use to reduce

current consumption. When the comparator is switched off, the CAOUT is

always low.

16.2.2 Input Analog Switches

The analog input switches connect or disconnect the two comparator input

terminals to associated port pins using the P2CAx bits. Both comparator

terminal inputs can be controlled individually. The P2CAx bits allow:

- Application of an external signal to the + and – terminals of the comparator

- Routing of an internal reference voltage to an associated output port pin

Internally, the input switch is constructed as a T-switch to suppress distortion

in the signal path.

Note: Comparator Input Connection

When the comparator is on, the input terminals should be connected to a

signal, power, or ground. Otherwise, floating levels may cause unexpected

interrupts and increased current consumption.

The CAEX bit controls the input multiplexer, exchanging which input signals

are connected to the comparator’s + and – terminals. Additionally, when the

comparator terminals are exchanged, the output signal from the comparator

is inverted. This allows the user to determine or compensate for the

comparator input offset voltage.

16-4

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Comparator_A Operation

16.2.3 Output Filter

The output of the comparator can be used with or without internal filtering.

When control bit CAF is set, the output is filtered with an on-chip RC-filter.

Any comparator output oscillates if the voltage difference across the input

terminals is small. Internal and external parasitic effects and cross coupling on

and between signal lines, power supply lines, and other parts of the system

are responsible for this behavior as shown in Figure 16−2. The comparator

output oscillation reduces accuracy and resolution of the comparison result.

Selecting the output filter can reduce errors associated with comparator

oscillation.

Figure 16−2. RC-Filter Response at the Output of the Comparator

+ Terminal

− Terminal

Comparator Inputs

Comparator Output

Unfiltered at CAOUT

Comparator Output

Filtered at CAOUT

16.2.4 Voltage Reference Generator

The voltage reference generator is used to generate V

, which can be

CAREF

applied to either comparator input terminal. The CAREFx bits control the

output of the voltage generator. The CARSEL bit selects the comparator

terminal to which V

is applied. If external signals are applied to both

CAREF

comparator input terminals, the internal reference generator should be turned

off to reduce current consumption. The voltage reference generator can

generate a fraction of the device’s V

of ~ 0.55 V.

or a fixed transistor threshold voltage

Comparator_A

16-5

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Comparator_A Operation

16.2.5 Comparator_A, Port Disable Register CAPD

The comparator input and output functions are multiplexed with the associated

I/O port pins, which are digital CMOS gates. When analog signals are applied

to digital CMOS gates, parasitic current can flow from V to GND. This

parasitic current occurs if the input voltage is near the transition level of the

gate. Disabling the port pin buffer eliminates the parasitic current flow and

therefore reduces overall current consumption.

The CAPDx bits, when set, disable the corresponding P2 input buffer as shown

in Figure 16−3. When current consumption is critical, any P2 pin connected to

analog signals should be disabled with their associated CAPDx bit.

Figure 16−3. Transfer Characteristic and Power Dissipation in a CMOS Inverter/Buffer

CAPD.x = 1

16.2.6 Comparator_A Interrupts

One interrupt flag and one interrupt vector are associated with the

Comparator_A as shown in Figure 16−4. The interrupt flag CAIFG is set on

either the rising or falling edge of the comparator output, selected by the

CAIES bit. If both the CAIE and the GIE bits are set, then the CAIFG flag

generates an interrupt request. The CAIFG flag is automatically reset when

the interrupt request is serviced or may be reset with software.

Figure 16−4. Comparator_A Interrupt System

CAIE

CAIES

IRQ, Interrupt Service Requested

IRACC, Interrupt Request Accepted

SET_CAIFG

Reset

POR

16-6

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Comparator_A Operation

16.2.7 Comparator_A Used to Measure Resistive Elements

The Comparator_A can be optimized to precisely measure resistive elements

using single slope analog-to-digital conversion. For example, temperature can

be converted into digital data using a thermistor, by comparing the thermistor’s

capacitor discharge time to that of a reference resistor as shown in

Figure 16−5. A reference resister Rref is compared to Rmeas.

Figure 16−5. Temperature Measurement System

Rref

Rmeas

CA0

Px.x

Px.y

CCI1B

Capture

Input

−

Of Timer_A

0.25xV

The MSP430 resources used to calculate the temperature sensed by Rmeas

are:

- Two digital I/O pins to charge and discharge the capacitor.

- I/O set to output high (V ) to charge capacitor, reset to discharge.

- I/O switched to high-impedance input with CAPDx set when not in use.

- One output charges and discharges the capacitor via Rref.

- One output discharges capacitor via Rmeas.

- The + terminal is connected to the positive terminal of the capacitor.

- The – terminal is connected to a reference level, for example 0.25 x V

- The output filter should be used to minimize switching noise.

- CAOUT used to gate Timer_A CCI1B, capturing capacitor discharge time.

More than one resistive element can be measured. Additional elements are

connected to CA0 with available I/O pins and switched to high impedance

when not being measured.

Comparator_A

16-7

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Comparator_A Operation

The thermistor measurement is based on a ratiometric conversion principle.

The ratio of two capacitor discharge times is calculated as shown in

Figure 16−6.

Figure 16−6. Timing for Temperature Measurement Systems

meas

ref

0.25 × V

Phase I:

Charge

Phase III:

Charge

Phase II:

Discharge

Phase IV:

Discharge

ref

meas

The V voltage and the capacitor value should remain constant during the

conversion, but are not critical since they cancel in the ratio:

ref

–R

C ln

meas

ref

–R C ln

ref

meas

ref

meas

+ R

meas

ref

16-8

Comparator_A

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Comparator_A Registers

16.3 Comparator_A Registers

The Comparator_A registers are listed in Table 16−1:

Table 16−1.Comparator_A Registers

Short Form

Initial State

Comparator_A control register 1

Comparator_A control register 2

Comparator_A port disable

CACTL1

CACTL2

CAPD

Read/write

059h

05Ah

05Bh

Reset with POR

Comparator_A

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Comparator_A Registers

CACTL1, Comparator_A Control Register 1

CAEX

rw−(0)

CARSEL

rw−(0)

CAREFx

CAON

rw−(0)

CAIES

rw−(0)

CAIE

rw−(0)

CAIFG

rw−(0)

CAEX

Bit 7

Comparator_A exchange. This bit exchanges the comparator inputs and

inverts the comparator output.

CARSEL

Bit 6

Comparator_A reference select. This bit selects which terminal the V

is applied to.

CAREF

When CAEX = 0:

is applied to the + terminal

is applied to the – terminal

CAREF

When CAEX = 1:

is applied to the – terminal

is applied to the + terminal

CAREF

CAON

Bits

5-4

Comparator_A reference. These bits select the reference voltage V

00 Internal reference off. An external reference can be applied.

CAREF.

01 0.25*V

10 0.50*V

11 Diode reference is selected

Bit 3

Comparator_A on. This bit turns on the comparator. When the comparator

is off it consumes no current. The reference circuitry is enabled or disabled

independently.

Off

CAIES

CAIE

Bit 2

Bit 1

Bit 0

Comparator_A interrupt edge select

Rising edge

Falling edge

Comparator_A interrupt enable

Disabled

Enabled

CAIFG

The Comparator_A interrupt flag

No interrupt pending

Interrupt pending

16-10

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Comparator_A Registers

CACTL2, Comparator_A, Control Register

Unused

P2CA1

rw−(0)

P2CA0

rw−(0)

CAF

rw−(0)

CAOUT

r−(0)

rw−(0)

Unused

Bits

7-4

Unused.

Pin to CA1. This bit selects the CA1 pin function.

P2CA1

P2CA0

CAF

Bit 3

The pin is not connected to CA1

The pin is connected to CA1

Bit 2

Bit 1

Bit 0

Pin to CA0. This bit selects the CA0 pin function.

The pin is not connected to CA0

The pin is connected to CA0

Comparator_A output filter

Comparator_A output is not filtered

Comparator_A output is filtered

CAOUT

Comparator_A output. This bit reflects the value of the comparator output.

Writing this bit has no effect.

CAPD, Comparator_A, Port Disable Register

CAPD7

rw−(0)

CAPD6

rw−(0)

CAPD5

rw−(0)

CAPD4

rw−(0)

CAPD3

rw−(0)

CAPD2

rw−(0)

CAPD1

rw−(0)

CAPD0

rw−(0)

CAPDx

Bits

7-0

Comparator_A port disable. These bits individually disable the input buffer

for the pins of the port associated with Comparator_A. For example, if CA0

is on pin P2.3, the CAPDx bits can be used to individually enable or

disable each P2.x pin buffer. CAPD0 disables P2.0, CAPD1 disables P2.1,

etc.

The input buffer is enabled.

The input buffer is disabled.

Comparator_A

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16-12

Comparator_A

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Chapter 17

ADC12

The ADC12 module is a high-performance 12-bit analog-to-digital converter.

This chapter describes the ADC12. The ADC12 is implemented in the

MSP430x13x, MSP430x14x, MSP430x15x, and MSP430x16x devices.

Topic

Page

17.1 ADC12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

17.2 ADC12 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

17.3 ADC12 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20

ADC12

17-1

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ADC12 Introduction

17.1 ADC12 Introduction

The ADC12 module supports fast, 12-bit analog-to-digital conversions. The

module implements a 12-bit SAR core, sample select control, reference

generator and 16 word conversion-and-control buffer. The

conversion-and-control buffer allows up to 16 independent ADC samples to be

converted and stored without any CPU intervention.

ADC12 features include:

- Greater than 200 ksps maximum conversion rate

- Monotonic 12-bit converter with no missing codes

- Sample-and-hold with programmable sampling periods controlled by

software or timers.

- Conversion initiation by software, Timer_A, or Timer_B

- Software selectable on-chip reference voltage generation (1.5 V or 2.5 V)

- Software selectable internal or external reference

- Eight individually configurable external input channels

- Conversion channels for internal temperature sensor, AV , and external

references

- Independent channel-selectable reference sources for both positive and

negative references

- Selectable conversion clock source

- Single-channel, repeat-single-channel, sequence, and repeat-sequence

conversion modes

- ADC core and reference voltage can be powered down separately

- Interrupt vector register for fast decoding of 18 ADC interrupts

- 16 conversion-result storage registers

The block diagram of ADC12 is shown in Figure 17−1.

17-2

ADC12

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ADC12 Introduction

Figure 17−1. ADC12 Block Diagram

REFON

INCHx=0Ah

REF2_5V

REF+

1.5 V or 2.5 V

Reference

REF−

Ref_x

INCHx

SREF1

SREF0

11 10 01 00

ADC12OSC

ADC12SSELx

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

SREF2

ADC12ON

ADC12DIVx

Sample

and

Hold

R−

R+

ACLK

Divider

/1 .. /8

12−bit SAR

MCLK

SMCLK

S/H

Convert

SHP

ADC12CLK

BUSY

SHT0x

SHSx

ISSH

ENC

ADC12SC

TA1

SHI

Sample Timer

/4 .. /1024

Sync

TB0

SAMPCON

TB1

SHT1x

MSC

INCHx=0Bh

Ref_x

ADC12MEM0

ADC12MCTL0

CSTARTADDx

CONSEQx

−

16 x 12

Memory

Buffer

−

16 x 8

Memory

Control

−

ADC12MEM15

ADC12MCTL15

ADC12

17-3

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ADC12 Operation

17.2 ADC12 Operation

The ADC12 module is configured with user software. The setup and operation

of the ADC12 is discussed in the following sections.

17.2.1 12-Bit ADC Core

The ADC core converts an analog input to its 12-bit digital representation and

stores the result in conversion memory. The core uses two

programmable/selectable voltage levels (V and V ) to define the upper and

R+

R−

lower limits of the conversion. The digital output (N

) is full scale (0FFFh)

ADC

when the input signal is equal to or higher than V , and zero when the input

R+

signal is equal to or lower than V . The input channel and the reference

R−

voltage levels (V and V ) are defined in the conversion-control memory.

R+

R−

The conversion formula for the ADC result N

is:

ADC

Vin * V

+ 4095

ADC

* V

The ADC12 core is configured by two control registers, ADC12CTL0 and

ADC12CTL1. The core is enabled with the ADC12ON bit. The ADC12 can be

turned off when not in use to save power. With few exceptions the ADC12

control bits can only be modified when ENC = 0. ENC must be set to 1 before

any conversion can take place.

Conversion Clock Selection

The ADC12CLK is used both as the conversion clock and to generate the

sampling period when the pulse sampling mode is selected. The ADC12

source clock is selected using the ADC12SSELx bits and can be divided from

1-8 using the ADC12DIVx bits. Possible ADC12CLK sources are SMCLK,

MCLK, ACLK, and an internal oscillator ADC12OSC.

The ADC12OSC, generated internally, is in the 5-MHz range, but varies with

individual devices, supply voltage, and temperature. See the device-specific

datasheet for the ADC12OSC specification.

The user must ensure that the clock chosen for ADC12CLK remains active

until the end of a conversion. If the clock is removed during a conversion, the

operation will not complete and any result will be invalid.

17-4

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ADC12 Operation

17.2.2 ADC12 Inputs and Multiplexer

The eight external and four internal analog signals are selected as the channel

for conversion by the analog input multiplexer. The input multiplexer is a

break-before-make type to reduce input-to-input noise injection resulting from

channel switching as shown in Figure 17−2. The input multiplexer is also a

T-switch to minimize the coupling between channels. Channels that are not

selected are isolated from the A/D and the intermediate node is connected to

analog ground (AV ) so that the stray capacitance is grounded to help

eliminate crosstalk.

The ADC12 uses the charge redistribution method. When the inputs are

internally switched, the switching action may cause transients on the input

signal. These transients decay and settle before causing errant conversion.

Figure 17−2. Analog Multiplexer

R ~ 100 Ohm

ADC12MCTLx.0−3

Input

ESD Protection

Analog Port Selection

The ADC12 inputs are multiplexed with the port P6 pins, which are digital

CMOS gates. When analog signals are applied to digital CMOS gates,

parasitic current can flow from V to GND. This parasitic current occurs if the

input voltage is near the transition level of the gate. Disabling the port pin buffer

eliminates the parasitic current flow and therefore reduces overall current

consumption. The P6SELx bits provide the ability to disable the port pin input

and output buffers.

; P6.0 and P6.1 configured for analog input

BIS.B #3h,&P6SEL ; P6.1 and P6.0 ADC12 function

ADC12

17-5

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ADC12 Operation

17.2.3 Voltage Reference Generator

The ADC12 module contains a built-in voltage reference with two selectable

voltage levels, 1.5 V and 2.5 V. Either of these reference voltages may be used

internally and externally on pin V

REF+

Setting REFON=1 enables the internal reference. When REF2_5V = 1, the

internal reference is 2.5 V, the reference is 1.5 V when REF2_5V = 0. The

reference can be turned off to save power when not in use.

For proper operation the internal voltage reference generator must be

supplied with storage capacitance across V

and A

. The recommended

REF+

storage capacitance is a parallel combination of 10-µF and 0.1-µF capacitors

VSS

From turn-on, a maximum of 17 ms must be allowed for the voltage reference

generator to bias the recommended storage capacitors. If the internal

reference generator is not used for the conversion, the storage capacitors are

not required.

Note: Reference Decoupling

Approximately 200 µA is required from any reference used by the ADC12

while the two LSBs are being resolved during a conversion. A parallel

combination of 10-µF and 0.1-µF capacitors is recommended for any

reference used as shown in Figure 17−11.

External references may be supplied for V and V through pins Ve and

REF+

R+

R−

/Ve

respectively.

REF−

17.2.4 Auto Power-Down

The ADC12 is designed for low power applications. When the ADC12 is not

actively converting, the core is automatically disabled and automatically

re-enabled when needed. The ADC12OSC is also automatically enabled

when needed and disabled when not needed. The reference is not

automatically disabled, but can be disabled by setting REFON = 0. When the

core, oscillator, or reference are disabled, they consume no current.

17-6

ADC12

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ADC12 Operation

17.2.5 Sample and Conversion Timing

An analog-to-digital conversion is initiated with a rising edge of the sample

input signal SHI. The source for SHI is selected with the SHSx bits and

includes the following:

- The ADC12SC bit

- The Timer_A Output Unit 1

- The Timer_B Output Unit 0

- The Timer_B Output Unit 1

The polarity of the SHI signal source can be inverted with the ISSH bit. The

SAMPCON signal controls the sample period and start of conversion. When

SAMPCON is high, sampling is active. The high-to-low SAMPCON transition

starts the analog-to-digital conversion, which requires 13 ADC12CLK cycles.

Two different sample-timing methods are defined by control bit SHP, extended

sample mode and pulse mode.

Extended Sample Mode

The extended sample mode is selected when SHP = 0. The SHI signal directly

controls SAMPCON and defines the length of the sample period t When

sample.

SAMPCON is high, sampling is active. The high-to-low SAMPCON transition

starts the conversion after synchronization with ADC12CLK. See Figure 17−3.

Figure 17−3. Extended Sample Mode

Start

Sampling

Stop

Sampling

Start

Conversion

Complete

SHI

13 x ADC12CLK

SAMPCON

sample

convert

sync

ADC12CLK

ADC12

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ADC12 Operation

Pulse Sample Mode

The pulse sample mode is selected when SHP = 1. The SHI signal is used to

trigger the sampling timer. The SHT0x and SHT1x bits in ADC12CTL0 control

the interval of the sampling timer that defines the SAMPCON sample period

The sampling timer keeps SAMPCON high after synchronization with

sample.

AD12CLK for a programmed interval t

. The total sampling time is t

sample

plus t

. See Figure 17−4.

sync

The SHTx bits select the sampling time in 4x multiples of ADC12CLK. SHT0x

selects the sampling time for ADC12MCTL0 to 7 and SHT1x selects the

sampling time for ADC12MCTL8 to 15.

Figure 17−4. Pulse Sample Mode

Start

Sampling

Stop Start

Sampling Conversion

Conversion

Complete

SHI

13 x ADC12CLK

SAMPCON

sample

convert

sync

ADC12CLK

17-8

ADC12

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ADC12 Operation

Sample Timing Considerations

When SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON =

1, the selected Ax input can be modeled as an RC low-pass filter during the

sampling time t

, as shown below in Figure 17−5. An internal MUX-on

sample

input resistance R (max. 2 kΩ) in series with capacitor C (max. 40 pF) is seen

by the source. The capacitor C voltage V must be charged to within 1/2 LSB

of the source voltage V for an accurate 12-bit conversion.

Figure 17−5. Analog Input Equivalent Circuit

MSP430

= Input voltage at pin Ax

= External source voltage

R = External source resistance

R = Internal MUX-on input resistance

C = Input capacitance

= Capacitance-charging voltage

The resistance of the source R and R affect t . The following equation

sample

can be used to calculate the minimum sampling time t

for a 12-bit

sample

conversion:

u (R ) R ) ln(2 ) C ) 800ns

sample

Substituting the values for R and C given above, the equation becomes:

u (R ) 2kW) 9.011 40pF ) 800ns

sample

For example, if R is 10 kΩ, t

must be greater than 5.13 µs.

sample

ADC12

17-9

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ADC12 Operation

17.2.6 Conversion Memory

There are 16 ADC12MEMx conversion memory registers to store conversion

results. Each ADC12MEMx is configured with an associated ADC12MCTLx

control register. The SREFx bits define the voltage reference and the INCHx

bits select the input channel. The EOS bit defines the end of sequence when

a sequential conversion mode is used. A sequence rolls over from

ADC12MEM15 to ADC12MEM0 when the EOS bit in ADC12MCTL15 is not

set.

The CSTARTADDx bits define the first ADC12MCTLx used for any

conversion. If the conversion mode is single-channel or repeat-single-channel

the CSTARTADDx points to the single ADC12MCTLx to be used.

If the conversion mode selected is either sequence-of-channels or

repeat-sequence-of-channels, CSTARTADDx points to the first

ADC12MCTLx location to be used in a sequence. A pointer, not visible to

software, is incremented automatically to the next ADC12MCTLx in a

sequence when each conversion completes. The sequence continues until an

EOS bit in ADC12MCTLx is processed - this is the last control byte processed.

When conversion results are written to a selected ADC12MEMx, the

corresponding flag in the ADC12IFGx register is set.

17.2.7 ADC12 Conversion Modes

The ADC12 has four operating modes selected by the CONSEQx bits as

discussed in Table 17−1.

Table 17−1.Conversion Mode Summary

CONSEQx

Mode

Operation

Single channel

single-conversion

A single channel is converted once.

Sequence-of-

channels

A sequence of channels is converted once.

A single channel is converted repeatedly.

Repeat-single-

channel

Repeat-sequence- A sequence of channels is converted

of-channels repeatedly.

17-10

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ADC12 Operation

Single-Channel Single-Conversion Mode

A single channel is sampled and converted once. The ADC result is written to

the ADC12MEMx defined by the CSTARTADDx bits. Figure 17−6 shows the

flow of the Single-Channel, Single-Conversion mode. When ADC12SC

triggers a conversion, successive conversions can be triggered by the

ADC12SC bit. When any other trigger source is used, ENC must be toggled

between each conversion.

Figure 17−6. Single-Channel, Single-Conversion Mode

CONSEQx = 00

ADC12

off

ADC12ON = 1

ENC =

x = CSTARTADDx

Wait for Enable

ENC =

SHSx = 0

and

ENC =

ENC = 1 or

and

ADC12SC =

Wait for Trigger

SAMPCON =

ENC = 0

SAMPCON = 1

Sample, Input

Channel Defined in

ADC12MCTLx

†

ENC = 0

SAMPCON =

12 x ADC12CLK

1 x ADC12CLK

Convert

†

ENC = 0

Conversion

Completed,

Result Stored Into

ADC12MEMx,

ADC12IFG.x is Set

x = pointer to ADC12MCTLx

†Conversion result is unpredictable

ADC12

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ADC12 Operation

Sequence-of-Channels Mode

A sequence of channels is sampled and converted once. The ADC results are

written to the conversion memories starting with the ADCMEMx defined by the

CSTARTADDx bits. The sequence stops after the measurement of the

channel with a set EOS bit. Figure 17−7 shows the sequence-of-channels

mode. When ADC12SC triggers a sequence, successive sequences can be

triggered by the ADC12SC bit. When any other trigger source is used, ENC

must be toggled between each sequence.

Figure 17−7. Sequence-of-Channels Mode

CONSEQx = 01

ADC12

off

ADC12ON = 1

ENC =

x = CSTARTADDx

Wait for Enable

ENC =

SHSx = 0

and

ENC =

ENC = 1 or

and

ADC12SC =

Wait for Trigger

SAMPCON =

EOS.x = 1

SAMPCON = 1

Sample, Input

Channel Defined in

ADC12MCTLx

If x < 15 then x = x + 1

else x = 0

If x < 15 then x = x + 1

else x = 0

SAMPCON =

12 x ADC12CLK

MSC = 1

(MSC = 0

SHP = 0)

and

SHP = 1

and

Convert

EOS.x = 0

1 x ADC12CLK

Conversion

Completed,

Result Stored Into

ADC12MEMx,

ADC12IFG.x is Set

x = pointer to ADC12MCTLx

17-12

ADC12

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ADC12 Operation

Repeat-Single-Channel Mode

A single channel is sampled and converted continuously. The ADC results are

written to the ADC12MEMx defined by the CSTARTADDx bits. It is necessary

to read the result after the completed conversion because only one

ADC12MEMx memory is used and is overwritten by the next conversion.

Figure 17−8 shows repeat-single-channel mode

Figure 17−8. Repeat-Single-Channel Mode

CONSEQx = 10

ADC12

off

ADC12ON = 1

ENC =

x = CSTARTADDx

Wait for Enable

ENC =

SHSx = 0

and

ENC =

ENC = 1 or

and

ADC12SC =

Wait for Trigger

SAMPCON =

ENC = 0

SAMPCON = 1

Sample, Input

Channel Defined in

ADC12MCTLx

SAMPCON =

12 x ADC12CLK

1 x ADC12CLK

MSC = 1

and

SHP = 1

and

(MSC = 0

SHP = 0)

and

Convert

ENC = 1

Conversion

Completed,

Result Stored Into

ADC12MEMx,

ADC12IFG.x is Set

x = pointer to ADC12MCTLx

ADC12

17-13

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ADC12 Operation

Repeat-Sequence-of-Channels Mode

A sequence of channels is sampled and converted repeatedly. The ADC

results are written to the conversion memories starting with the ADC12MEMx

defined by the CSTARTADDx bits. The sequence ends after the measurement

of the channel with a set EOS bit and the next trigger signal re-starts the

sequence. Figure 17−9 shows the repeat-sequence-of-channels mode.

Figure 17−9. Repeat-Sequence-of-Channels Mode

CONSEQx = 11

ADC12

off

ADC12ON = 1

ENC =

x = CSTARTADDx

Wait for Enable

ENC =

SHSx = 0

and

ENC =

ENC = 1 or

and

ADC12SC =

Wait for Trigger

SAMPCON =

ENC = 0

and

EOS.x = 1

SAMPCON = 1

Sample, Input

Channel Defined in

ADC12MCTLx

If EOS.x = 1 then x =

CSTARTADDx

else {if x < 15 then x = x + 1 else

x = 0}

SAMPCON =

If EOS.x = 1 then x =

CSTARTADDx

else {if x < 15 then x = x + 1 else

x = 0}

12 x ADC12CLK

(MSC = 0

Convert

SHP = 0)

and

(ENC = 1

MSC = 1

and

SHP = 1

and

(ENC = 1

EOS.x = 0)

1 x ADC12CLK

Conversion

Completed,

Result Stored Into

ADC12MEMx,

ADC12IFG.x is Set

EOS.x = 0)

x = pointer to ADC12MCTLx

17-14

ADC12

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ADC12 Operation

Using the Multiple Sample and Convert (MSC) Bit

To configure the converter to perform successive conversions automatically

and as quickly as possible, a multiple sample and convert function is available.

When MSC = 1, CONSEQx > 0, and the sample timer is used, the first rising

edge of the SHI signal triggers the first conversion. Successive conversions

are triggered automatically as soon as the prior conversion is completed.

Additional rising edges on SHI are ignored until the sequence is completed in

the single-sequence mode or until the ENC bit is toggled in

repeat-single-channel, or repeated-sequence modes. The function of the ENC

bit is unchanged when using the MSC bit.

Stopping Conversions

Stopping ADC12 activity depends on the mode of operation. The

recommended ways to stop an active conversion or conversion sequence are:

- Resetting ENC in single-channel single-conversion mode stops a

conversion immediately and the results are unpredictable. For correct

results, poll the busy bit until reset before clearing ENC.

- Resetting ENC during repeat-single-channel operation stops the

converter at the end of the current conversion.

- Resetting ENC during a sequence or repeat-sequence mode stops the

converter at the end of the sequence.

- Any conversion mode may be stopped immediately by setting the

CONSEQx = 0 and resetting ENC bit. Conversion data are unreliable.

Note: No EOS Bit Set For Sequence

If no EOS bit is set and a sequence mode is selected, resetting the ENC bit

does not stop the sequence. To stop the sequence, first select a

single-channel mode and then reset ENC.

ADC12

17-15

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ADC12 Operation

17.2.8 Using the Integrated Temperature Sensor

To use the on-chip temperature sensor, the user selects the analog input

channel INCHx = 1010. Any other configuration is done as if an external

channel was selected, including reference selection, conversion-memory

selection, etc.

The typical temperature sensor transfer function is shown in Figure 17−10.

When using the temperature sensor, the sample period must be greater than

30 µs. The temperature sensor offset error can be large, and may need to be

calibrated for most applications. See device-specific datasheet for

parameters.

Selecting the temperature sensor automatically turns on the on-chip reference

generator as a voltage source for the temperature sensor. However, it does not

enable the V

output or affect the reference selections for the conversion.

REF+

The reference choices for converting the temperature sensor are the same as

with any other channel.

Figure 17−10. Typical Temperature Sensor Transfer Function

Volts

1.300

1.200

1.100

1.000

0.900

0.800

0.700

=0.00355(TEMP )+0.986

TEMP

Celsius

100

−50

17-16

ADC12

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ADC12 Operation

17.2.9 ADC12 Grounding and Noise Considerations

As with any high-resolution ADC, appropriate printed-circuit-board layout and

grounding techniques should be followed to eliminate ground loops, unwanted

parasitic effects, and noise.

Ground loops are formed when return current from the A/D flows through paths

that are common with other analog or digital circuitry. If care is not taken, this

current can generate small, unwanted offset voltages that can add to or

subtract from the reference or input voltages of the A/D converter. The

connections shown in Figure 17−11 help avoid this.

In addition to grounding, ripple and noise spikes on the power supply lines due

to digital switching or switching power supplies can corrupt the conversion

result. A noise-free design using separate analog and digital ground planes

with a single-point connection is recommend to achieve high accuracy.

Figure 17−11.ADC12 Grounding and Noise Considerations

Digital

Power Supply

Decoupling

10 uF

100 nF

Analog

Power Supply

Decoupling

MSP430F13x

MSP430F14x

MSP430F15x

MSP430F16x

10 uF

Using an External

Positive

Reference

REF+

REF−

10 uF

100 nF

Using the Internal

Reference

Generator

10 uF

/ Ve

Using an External

Negative

Reference

REF−

10 uF

ADC12

17-17

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ADC12 Operation

17.2.10 ADC12 Interrupts

The ADC12 has 18 interrupt sources:

- ADC12IFG0-ADC12IFG15

- ADC12OV, ADC12MEMx overflow

- ADC12TOV, ADC12 conversion time overflow

The ADC12IFGx bits are set when their corresponding ADC12MEMx memory

if the corresponding ADC12IEx bit and the GIE bit are set. The ADC12OV

condition occurs when a conversion result is written to any ADC12MEMx

before its previous conversion result was read. The ADC12TOV condition is

generated when another sample-and-conversion is requested before the

current conversion is completed.

ADC12IV, Interrupt Vector Generator

All ADC12 interrupt sources are prioritized and combined to source a single

interrupt vector. The interrupt vector register ADC12IV is used to determine

which enabled ADC12 interrupt source requested an interrupt.

The highest priority enabled ADC12 interrupt generates a number in the

ADC12IV register (see register description). This number can be evaluated or

added to the program counter to automatically enter the appropriate software

routine. Disabled ADC12 interrupts do not affect the ADC12IV value.

Any access, read or write, of the ADC12IV register automatically resets the

ADC12OV condition or the ADC12TOV condition if either was the highest

pending interrupt. Neither interrupt condition has an accessible interrupt flag.

The ADC12IFGx flags are not reset by an ADC12IV access. ADC12IFGx bits

are reset automatically by accessing their associated ADC12MEMx register

or may be reset with software.

If another interrupt is pending after servicing of an interrupt, another interrupt

is generated. For example, if the ADC12OV and ADC12IFG3 interrupts are

pending when the interrupt service routine accesses the ADC12IV register, the

ADC12OV interrupt condition is reset automatically. After the RETI instruction

of the interrupt service routine is executed, the ADC12IFG3 generates another

interrupt.

17-18

ADC12

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ADC12 Operation

ADC12 Interrupt Handling Software Example

The following software example shows the recommended use of ADC12IV

and the handling overhead. The ADC12IV value is added to the PC to

automatically jump to the appropriate routine.

The numbers at the right margin show the necessary CPU cycles for each

instruction. The software overhead for different interrupt sources includes

interrupt latency and return-from-interrupt cycles, but not the task handling

itself. The latencies are:

- ADC12IFG0 - ADC12IFG14, ADC12TOV and ADC12OV 16 cycles

- ADC12IFG15

14 cycles

The interrupt handler for ADC12IFG15 shows a way to check immediately if

a higher prioritized interrupt occurred during the processing of ADC12IFG15.

This saves nine cycles if another ADC12 interrupt is pending.

; Interrupt handler for ADC12.

INT_ADC12

; Enter Interrupt Service Routine

ADD &ADC12IV,PC; Add offset to PC

RETI

; Vector 0: No interrupt

; Vector 2: ADC overflow

; Vector 4: ADC timing overflow

; Vector 6: ADC12IFG0

; Vectors 8-32

JMP ADOV

JMP ADTOV

JMP ADM0

...

JMP ADM14

; Vector 34: ADC12IFG14

;

; Handler for ADC12IFG15 starts here. No JMP required.

;

ADM15

MOV &ADC12MEM15,xxx; Move result, flag is reset

...

; Other instruction needed?

; Check other int pending

JMP INT_ADC12

;

; ADC12IFG14-ADC12IFG1 handlers go here

;

ADM0

MOV &ADC12MEM0,xxx ; Move result, flag is reset

...

; Other instruction needed?

; Return

RETI

;

ADTOV

...

; Handle Conv. time overflow

; Return

RETI

;

ADOV

...

; Handle ADCMEMx overflow

; Return

RETI

ADC12

17-19

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ADC12 Registers

17.3 ADC12 Registers

The ADC12 registers are listed in Table 17−2:

Table 17−2.ADC12 Registers

Short Form

Initial State

ADC12 control register 0

ADC12 control register 1

ADC12 interrupt flag register

ADC12 interrupt enable register

ADC12 interrupt vector word

ADC12 memory 0

ADC12CTL0

Read/write

Read

01A0h

01A2h

01A4h

01A6h

01A8h

0140h

0142h

0144h

0146h

0148h

014Ah

014Ch

014Eh

0150h

0152h

0154h

0156h

0158h

015Ah

015Ch

015Eh

080h

Reset with POR

Unchanged

ADC12CTL1

ADC12IFG

ADC12IE

ADC12IV

ADC12MEM0

ADC12MEM1

ADC12MEM2

ADC12MEM3

ADC12MEM4

ADC12MEM5

ADC12MEM6

ADC12MEM7

ADC12MEM8

ADC12MEM9

ADC12MEM10

ADC12MEM11

ADC12MEM12

ADC12MEM13

ADC12MEM14

ADC12MEM15

ADC12MCTL0

ADC12MCTL1

ADC12MCTL2

ADC12MCTL3

ADC12MCTL4

ADC12MCTL5

ADC12MCTL6

ADC12MCTL7

ADC12MCTL8

ADC12MCTL9

ADC12MCTL10

ADC12MCTL11

ADC12MCTL12

ADC12MCTL13

ADC12MCTL14

ADC12MCTL15

Read/write

ADC12 memory 1

Unchanged

ADC12 memory 2

Unchanged

ADC12 memory 3

Unchanged

ADC12 memory 4

Unchanged

ADC12 memory 5

Unchanged

ADC12 memory 6

Unchanged

ADC12 memory 7

Unchanged

ADC12 memory 8

Unchanged

ADC12 memory 9

Unchanged

ADC12 memory 10

Unchanged

ADC12 memory 11

Unchanged

ADC12 memory 12

Unchanged

ADC12 memory 13

Unchanged

ADC12 memory 14

Unchanged

ADC12 memory 15

Unchanged

ADC12 memory control 0

ADC12 memory control 1

ADC12 memory control 2

ADC12 memory control 3

ADC12 memory control 4

ADC12 memory control 5

ADC12 memory control 6

ADC12 memory control 7

ADC12 memory control 8

ADC12 memory control 9

ADC12 memory control 10

ADC12 memory control 11

ADC12 memory control 12

ADC12 memory control 13

ADC12 memory control 14

ADC12 memory control 15

Reset with POR

081h

082h

083h

084h

085h

086h

087h

088h

089h

08Ah

08Bh

08Ch

08Dh

08Eh

08Fh

17-20

ADC12

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ADC12 Registers

ADC12CTL0, ADC12 Control Register 0

SHT1x

SHT0x

rw−(0)

ADC12

TOVIE

MSC

rw−(0)

REF2_5V

REFON

rw−(0)

ADC12ON

rw−(0)

ADC12OVIE

rw−(0)

ENC

rw−(0)

ADC12SC

rw−(0)

Modifiable only when ENC = 0

SHT1x

Bits

15-12

Sample-and-hold time. These bits define the number of ADC12CLK cycles in

the sampling period for registers ADC12MEM8 to ADC12MEM15.

SHT0x

Bits

11-8

Sample-and-hold time. These bits define the number of ADC12CLK cycles in

the sampling period for registers ADC12MEM0 to ADC12MEM7.

SHTx Bits

ADC12CLK cycles

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

128

192

256

384

512

768

1024

ADC12

17-21

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ADC12 Registers

MSC

Bit 7

Multiple sample and conversion. Valid only for sequence or repeated modes.

The sampling timer requires a rising edge of the SHI signal to trigger

each sample-and-conversion.

The first rising edge of the SHI signal triggers the sampling timer, but

further sample-and-conversions are performed automatically as soon

as the prior conversion is completed.

REF2_5V

REFON

Bit 6

Bit 5

Bit 4

Bit 3

Reference generator voltage. REFON must also be set.

1.5 V

2.5 V

Reference generator on

Reference off

Reference on

ADC12ON

ADC12OVIE

ADC12 on

ADC12 off

ADC12 on

ADC12MEMx overflow-interrupt enable. The GIE bit must also be set to

enable the interrupt.

Overflow interrupt disabled

Overflow interrupt enabled

ADC12

TOVIE

Bit 2

ADC12 conversion-time-overflow interrupt enable. The GIE bit must also be

set to enable the interrupt.

Conversion time overflow interrupt disabled

Conversion time overflow interrupt enabled

ENC

Bit 1

Bit 0

Enable conversion

ADC12 disabled

ADC12 enabled

ADC12SC

Start conversion. Software-controlled sample-and-conversion start.

ADC12SC and ENC may be set together with one instruction. ADC12SC is

reset automatically.

No sample-and-conversion-start

Start sample-and-conversion

17-22

ADC12

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ADC12 Registers

ADC12CTL1, ADC12 Control Register 1

CSTARTADDx

SHSx

SHP

rw−(0)

ISSH

rw−(0)

ADC12

BUSY

ADC12DIVx

rw−(0)

ADC12SSELx

CONSEQx

rw−(0)

r−(0)

Modifiable only when ENC = 0

CSTART

ADDx

Bits

15-12

Conversion start address. These bits select which ADC12

conversion-memory register is used for a single conversion or for the first

conversion in a sequence. The value of CSTARTADDx is 0 to 0Fh,

corresponding to ADC12MEM0 to ADC12MEM15.

SHSx

SHP

Bits

11-10

Sample-and-hold source select

00 ADC12SC bit

01 Timer_A.OUT1

10 Timer_B.OUT0

11 Timer_B.OUT1

Bit 9

Bit 8

Sample-and-hold pulse-mode select. This bit selects the source of the

sampling signal (SAMPCON) to be either the output of the sampling timer or

the sample-input signal directly.

SAMPCON signal is sourced from the sample-input signal.

SAMPCON signal is sourced from the sampling timer.

ISSH

Invert signal sample-and-hold

The sample-input signal is not inverted.

The sample-input signal is inverted.

ADC12DIVx

Bits

7-5

ADC12 clock divider

000 /1

001 /2

010 /3

011 /4

100 /5

101 /6

110 /7

111 /8

ADC12

17-23

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ADC12 Registers

ADC12

SSELx

Bits

4-3

ADC12 clock source select

00 ADC12OSC

01 ACLK

10 MCLK

11 SMCLK

CONSEQx

Bits

2-1

Conversion sequence mode select

00 Single-channel, single-conversion

01 Sequence-of-channels

10 Repeat-single-channel

11 Repeat-sequence-of-channels

ADC12

BUSY

Bit 0

ADC12 busy. This bit indicates an active sample or conversion operation.

No operation is active.

A sequence, sample, or conversion is active.

ADC12MEMx, ADC12 Conversion Memory Registers

Conversion Results

rw rw

Conversion

Results

Bits

15-0

The 12-bit conversion results are right-justified. Bit 11 is the MSB. Bits 15-12

are always 0. Writing to the conversion memory registers will corrupt the

results.

17-24

ADC12

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ADC12 Registers

ADC12MCTLx, ADC12 Conversion Memory Control Registers

EOS

rw−(0)

SREFx

rw−(0)

INCHx

rw−(0)

Modifiable only when ENC = 0

EOS

Bit 7

End of sequence. Indicates the last conversion in a sequence.

Not end of sequence

End of sequence

SREFx

Bits

6-4

Select reference

000 V = AV

and V = AV

R− SS

R+

001 V = V

and V = AV

R+

REF+

R− SS

010 V = Ve

and V = AV

R−

R+

011 V = Ve

and V = AV

R+

R−

100 V = AV

and V = V

/ Ve

R+

R−

REF− REF−

/ Ve

REF− REF−

101 V = V

110 V = Ve

and V = V

R+

REF+

R−

and V = V

R+

REF+

R−

111

= Ve

and V = V

R+

R−

INCHx

Bits

3-0

Input channel select

0000 A0

0001 A1

0010 A2

0011

0100 A4

0101 A5

0110

0111

1000 Ve

REF+

1001

/Ve

REF− REF−

1010 Temperature sensor

1011

1100

1101

1110

1111

(AV

– AV ) / 2

ADC12

17-25

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ADC12 Registers

ADC12IE, ADC12 Interrupt Enable Register

ADC12IE15 ADC12IE14 ADC12IE13 ADC12IE12 ADC12IE11 ADC12IE10

ADC12IE9

rw−(0)

ADC12IE8

rw−(0)

ADC12IE7

rw−(0)

ADC12IE6

rw−(0)

ADC12IE5

rw−(0)

ADC12IE4

rw−(0)

ADC12IE3

rw−(0)

ADC12IE2

rw−(0)

ADC12IE1

rw−(0)

ADC12IE0

rw−(0)

ADC12IEx

Bits

15-0

Interrupt enable. These bits enable or disable the interrupt request for the

ADC12IFGx bits.

Interrupt disabled

Interrupt enabled

ADC12IFG, ADC12 Interrupt Flag Register

ADC12

IFG15

ADC12

IFG14

ADC12

IFG13

ADC12

IFG12

ADC12

IFG11

ADC12

IFG10

ADC12

IFG9

ADC12

IFG8

rw−(0)

ADC12

IFG7

ADC12

IFG6

ADC12

IFG5

ADC12

IFG4

ADC12

IFG3

ADC12

IFG2

ADC12

IFG1

ADC12

IFG0

rw−(0)

ADC12IFGx

Bits

15-0

ADC12MEMx Interrupt flag. These bits are set when corresponding

ADC12MEMx is loaded with a conversion result. The ADC12IFGx bits are

reset if the corresponding ADC12MEMx is accessed, or may be reset with

software.

No interrupt pending

Interrupt pending

17-26

ADC12

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ADC12 Registers

ADC12IV, ADC12 Interrupt Vector Register

ADC12IVx

r−(0)

ADC12IVx

Bits

15-0

ADC12 interrupt vector value

ADC12IV

Interrupt

Contents

000h

002h

004h

006h

008h

00Ah

00Ch

00Eh

010h

012h

014h

016h

018h

01Ah

01Ch

01Eh

020h

022h

024h

Priority

Interrupt Source

No interrupt pending

Interrupt Flag

−

ADC12MEMx overflow

−

Highest

Conversion time overflow

ADC12MEM0 interrupt flag

ADC12MEM1 interrupt flag

ADC12MEM2 interrupt flag

ADC12MEM3 interrupt flag

ADC12MEM4 interrupt flag

ADC12MEM5 interrupt flag

ADC12MEM6 interrupt flag

ADC12MEM7 interrupt flag

ADC12MEM8 interrupt flag

ADC12MEM9 interrupt flag

−

ADC12IFG0

ADC12IFG1

ADC12IFG2

ADC12IFG3

ADC12IFG4

ADC12IFG5

ADC12IFG6

ADC12IFG7

ADC12IFG8

ADC12IFG9

ADC12IFG10

ADC12IFG11

ADC12IFG12

ADC12IFG13

ADC12IFG14

ADC12IFG15

ADC12MEM10 interrupt flag

ADC12MEM11 interrupt flag

ADC12MEM12 interrupt flag

ADC12MEM13 interrupt flag

ADC12MEM14 interrupt flag

ADC12MEM15 interrupt flag

Lowest

ADC12

17-27

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17-28

ADC12

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Chapter 18

ADC10

The ADC10 module is a high-performance 10-bit analog-to-digital converter.

This chapter describes the ADC10. The ADC10 is implemented in the

MSP430x11x2, MSP430x12x2 devices.

Topic

Page

18.1 ADC10 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2

18.2 ADC10 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4

18.3 ADC10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24

ADC10

18-1

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ADC10 Introduction

18.1 ADC10 Introduction

The ADC10 module supports fast, 10-bit analog-to-digital conversions. The

module implements a 10-bit SAR core, sample select control, reference

generator, and data transfer controller (DTC).

The DTC allows ADC10 samples to be converted and stored anywhere in

memory without CPU intervention. The module can be configured with user

software to support a variety of applications.

ADC10 features include:

- Greater than 200 ksps maximum conversion rate

- Monotonic10-bit converter with no missing codes

- Sample-and-hold with programmable sample periods

- Conversion initiation by software or Timer_A

- Software selectable on-chip reference voltage generation (1.5 V or 2.5 V)

- Software selectable internal or external reference

- Eight external input channels

- Conversion channels for internal temperature sensor, V , and external

references

- Selectable conversion clock source

- Single-channel, repeated single-channel, sequence, and repeated

sequence conversion modes

- ADC core and reference voltage can be powered down separately

- Data transfer controller for automatic storage of conversion results

The block diagram of ADC10 is shown in Figure 18−1.

18-2

ADC10

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ADC10 Introduction

Figure 18−1. ADC10 Block Diagram

REFOUT

REFBURST

ADC10SR

REFON

INCHx=0Ah

REF+

REF2_5V

REF+

1.5 V or 2.5 V

Reference

REF−

Ref_x

INCHx

SREF1

SREF0

Auto

CONSEQx

11 10 01 00

ADC10ON

ADC10OSC

ADC10SSELx

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

SREF2

ADC10DIVx

Sample

and

Hold

R−

R+

ACLK

Divider

/1 .. /8

10−bit SAR

Convert

MCLK

SMCLK

S/H

ADC10CLK

ISSH

SHSx

BUSY

ENC

ADC10SC

TA1

SAMPCON

SHI

Sample Timer

/4/8/16/64

Sync

TA0

TA2

ADC10DF

ADC10SHTx MSC

INCHx=0Bh

Ref_x

ADC10MEM

Data Transfer

Controller

RAM, Flash, Peripherials

ADC10SA

Halt CPU

ADC10CT ADC10TB ADC10B1

ADC10

18-3

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ADC10 Operation

18.2 ADC10 Operation

The ADC10 module is configured with user software. The setup and operation

of the ADC10 is discussed in the following sections.

18.2.1 10-Bit ADC Core

The ADC core converts an analog input to its 10-bit digital representation and

stores the result in the ADC10MEM register. The core uses two

programmable/selectable voltage levels (V and V ) to define the upper and

R+

R−

lower limits of the conversion. The digital output (N

) is full scale (03FFh)

ADC

when the input signal is equal to or higher than V , and zero when the input

R+

signal is equal to or lower than V . The input channel and the reference

R−

voltage levels (V and V ) are defined in the conversion-control memory.

R+

R−

Conversion results may be in straight binary format or 2s-complement format.

The conversion formula for the ADC result when using straight binary format

is:

Vin – V

R–

+ 1023

ADC

– V

R–

The ADC10 core is configured by two control registers, ADC10CTL0 and

ADC10CTL1. The core is enabled with the ADC10ON bit. With few exceptions

the ADC10 control bits can only be modified when ENC = 0. ENC must be set

to 1 before any conversion can take place.

Conversion Clock Selection

The ADC10CLK is used both as the conversion clock and to generate the

sampling period. The ADC10 source clock is selected using the ADC10SSELx

bits and can be divided from 1-8 using the ADC10DIVx bits. Possible

ADC10CLK sources are SMCLK, MCLK, ACLK and an internal oscillator

ADC10OSC .

The ADC10OSC, generated internally, is in the 5-MHz range, but varies with

individual devices, supply voltage, and temperature. See the device-specific

datasheet for the ADC10OSC specification.

The user must ensure that the clock chosen for ADC10CLK remains active

until the end of a conversion. If the clock is removed during a conversion, the

operation will not complete, and any result will be invalid.

18-4

ADC10

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ADC10 Operation

18.2.2 ADC10 Inputs and Multiplexer

The eight external and four internal analog signals are selected as the channel

for conversion by the analog input multiplexer. The input multiplexer is a

break-before-make type to reduce input-to-input noise injection resulting from

channel switching as shown in Figure 18−2. The input multiplexer is also a

T-switch to minimize the coupling between channels. Channels that are not

selected are isolated from the A/D and the intermediate node is connected to

analog ground (V ) so that the stray capacitance is grounded to help

eliminate crosstalk.

The ADC10 uses the charge redistribution method. When the inputs are

internally switched, the switching action may cause transients on the input

signal. These transients decay and settle before causing errant conversion.

Figure 18−2. Analog Multiplexer

R ~ 100Ohm

INCHx

Input

ESD Protection

Analog Port Selection

The ADC10 external inputs A0 to A4 and Ve

and V

share terminals

REF+

REF−

with I/O port P2, which are digital CMOS gates. Optional inputs A5 to A7 are

shared on port P3 on selected devices (see device-specific datasheet). When

analog signals are applied to digital CMOS gates, parasitic current can flow

from V to GND. This parasitic current occurs if the input voltage is near the

transition level of the gate. Disabling the port pin buffer eliminates the parasitic

current flow and therefore reduces overall current consumption. The

ADC10AEx bits provide the ability to disable the port pin input and output

buffers.

; P2.3 configured for analog input

BIS.B #08h,&ADC10AE ; P2.3 ADC10 function and enable

ADC10

18-5

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ADC10 Operation

18.2.3 Voltage Reference Generator

The ADC10 module contains a built-in voltage reference with two selectable

voltage levels. Setting REFON = 1 enables the internal reference. When

REF2_5V = 1, the internal reference is 2.5 V. When REF2_5V = 0, the

reference is 1.5 V. The internal reference voltage may be used internally and,

when REFOUT = 0, externally on pin V

REF+

External references may be supplied for V and V through pins A4 and A3

R+

R−

respectively. When external references are used, or when V

is used as the

reference, the internal reference may be turned off to save power.

External storage capacitance is not required for the ADC10 reference source

as on the ADC12.

Internal Reference Low-Power Features

The ADC10 internal reference generator is designed for low power

applications. The reference generator includes a band-gap voltage source

and a separate buffer. The current consumption of each is specified separately

in the device-specific datasheet. When REFON = 1, both are enabled and

when REFON = 0 both are disabled. The total settling time when REFON

becomes set is ^ꢀ30 µs.

When REFON = 1, but no conversion is active, the buffer is automatically

disabled and automatically re-enabled when needed. When the buffer is

disabled, it consumes no current. In this case, the band-gap voltage source

remains enabled.

When REFOUT = 1, the REFBURST bit controls the operation of the internal

reference buffer. When REFBURST = 0, the buffer will be on continuously,

allowing the reference voltage to be present outside the device continuously.

When REFBURST = 1, the buffer is automatically disabled when the ADC10

is not actively converting, and automatically re-enabled when needed.

The internal reference buffer also has selectable speed vs. power settings.

When the maximum conversion rate is below 50 ksps, setting ADC10SR = 1

reduces the current consumption of the buffer approximately 50%.

18.2.4 Auto Power-Down

The ADC10 is designed for low power applications. When the ADC10 is not

actively converting, the core is automatically disabled and automatically

re-enabled when needed The ADC10OSC is also automatically enabled when

needed and disabled when not needed. When the core or oscillator are

disabled, they consume no current.

18-6

ADC10

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ADC10 Operation

18.2.5 Sample and Conversion Timing

An analog-to-digital conversion is initiated with a rising edge of sample input

signal SHI. The source for SHI is selected with the SHSx bits and includes the

following:

- The ADC10SC bit

- The Timer_A Output Unit 1

- The Timer_A Output Unit 0

- The Timer_A Output Unit 2

The polarity of the SHI signal source can be inverted with the ISSH bit. The

SHTx bits select the sample period t

to be 4, 8, 16, or 64 ADC10CLK

sample

cycles. The sampling timer sets SAMPCON high for the selected sample

period after synchronization with ADC10CLK. Total sampling time is t

sample

plus t

.The high-to-low SAMPCON transition starts the analog-to-digital

sync

conversion, which requires 13 ADC10CLK cycles as shown in Figure 18−3.

Figure 18−3. Sample Timing

Start

Sampling

Stop Start

Sampling Conversion

Conversion

Complete

SHI

13 x ADC10CLKs

SAMPCON

sample

convert

sync

ADC10CLK

ADC10

18-7

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ADC10 Operation

Sample Timing Considerations

When SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON =

1, the selected Ax input can be modeled as an RC low-pass filter during the

sampling time t , as shown below in Figure 18−4. An internal MUX-on

sample

input resistance R (max. 2 kΩ) in series with capacitor C (max. 20 pF) is seen

by the source. The capacitor C voltage V must be charged to within ½ LSB

of the source voltage V for an accurate 10-bit conversion.

Figure 18−4. Analog Input Equivalent Circuit

MSP430

= Input voltage at pin Ax

= External source voltage

R = External source resistance

R = Internal MUX-on input resistance

C = Input capacitance

= Capacitance-charging voltage

The resistance of the source R and R affect t .The following equations

sample

can be used to calculate the minimum sampling time t

for a 10-bit

sample

conversion.

When ADC10SR = 0:

u (R ) R ) ln(2 ) C ) 800ns

sample

When ADC10SR = 1:

u (R ) R ) ln(2 ) C ) 2.5ms

sample

Substituting the values for R and C given above, the equation becomes:

u (R ) 2k) 7.625 20pF ) 800ns

(ADC10SR = 0)

sample

u (R ) 2k) 7.625 20pF ) 2.5ms

(ADC10SR = 1)

For example, if R is 10 kΩ, t

must be greater than 2.63 µs when

sample

ADC10SR = 0, or 4.33 µs when ADC10SR = 1.

18-8

ADC10

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ADC10 Operation

18.2.6 Conversion Modes

The ADC10 has four operating modes selected by the CONSEQx bits as

discussed in Table 18−1.

Table 18−1.Conversion Mode Summary

CONSEQx

Mode

Operation

Single channel

single-conversion

A single channel is converted once.

Sequence-of-

channels

A sequence of channels is converted once.

A single channel is converted repeatedly.

Repeat single

channel

Repeat sequence- A sequence of channels is converted

of-channels repeatedly.

ADC10

18-9

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ADC10 Operation

Single-Channel Single-Conversion Mode

A single channel selected by INCHx is sampled and converted once. The ADC

result is written to ADC10MEM. Figure 18−5 shows the flow of the

single-channel, single-conversion mode. When ADC10SC triggers a

conversion, successive conversions can be triggered by the ADC10SC bit.

When any other trigger source is used, ENC must be toggled between each

conversion.

Figure 18−5. Single-Channel Single-Conversion Mode

CONSEQx = 00

ADC10

Off

ENC =

ADC10ON = 1

x = INCHx

Wait for Enable

ENC =

SHS = 0

and

ENC =

ENC = 1 or

and

ADC10SC =

Wait for Trigger

SAMPCON =

ENC = 0

(4/8/16/64) x ADC10CLK

Sample, Input

Channel

†

ENC = 0

12 x ADC10CLK

1 x ADC10CLK

Convert

†

ENC = 0

Conversion

Completed,

Result to

ADC10MEM,

ADC10IFG is Set

x = input channel Ax

†

Conversion result is unpredictable

18-10

ADC10

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ADC10 Operation

Sequence-of-Channels Mode

A sequence of channels is sampled and converted once. The sequence

begins with the channel selected by INCHx and decrements to channel A0.

Each ADC result is written to ADC10MEM. The sequence stops after

conversion of channel A0. Figure 18−6 shows the sequence-of-channels

mode. When ADC10SC triggers a sequence, successive sequences can be

triggered by the ADC10SC bit . When any other trigger source is used, ENC

must be toggled between each sequence.

Figure 18−6. Sequence-of-Channels Mode

CONSEQx = 01

ADC10

Off

ADC10ON = 1

ENC =

x = INCHx

Wait for Enable

ENC =

SHS = 0

and

ENC =

ENC = 1 or

and

ADC10SC =

Wait for Trigger

SAMPCON =

x = 0

(4/8/16/64) x ADC10CLK

Sample,

Input Channel Ax

If x > 0 then x = x −1

12 x ADC10CLK

1 x ADC10CLK

MSC = 1

and

x ≠ 0

Convert

MSC = 0

and

x ≠ 0

Conversion

Completed,

Result to ADC10MEM,

ADC10IFG is Set

x = input channel Ax

ADC10

18-11

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ADC10 Operation

Repeat-Single-Channel Mode

A single channel selected by INCHx is sampled and converted continuously.

Each ADC result is written to ADC10MEM. Figure 18−7 shows the

repeat-single-channel mode.

Figure 18−7. Repeat-Single-Channel Mode

CONSEQx = 10

ADC10

Off

ADC10ON = 1

ENC =

x = INCHx

Wait for Enable

ENC =

SHS = 0

and

ENC =

ENC = 1 or

and

ADC10SC =

Wait for Trigger

SAMPCON =

ENC = 0

(4/8/16/64) × ADC10CLK

Sample,

Input Channel Ax

12 x ADC10CLK

MSC = 1

MSC = 0

Convert

and

ENC = 1

1 x ADC10CLK

Conversion

Completed,

Result to ADC10MEM,

ADC10IFG is Set

x = input channel Ax

18-12

ADC10

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ADC10 Operation

Repeat-Sequence-of-Channels Mode

A sequence of channels is sampled and converted repeatedly. The sequence

begins with the channel selected by INCHx and decrements to channel A0.

Each ADC result is written to ADC10MEM. The sequence ends after

conversion of channel A0, and the next trigger signal re-starts the sequence.

Figure 18−8 shows the repeat-sequence-of-channels mode.

Figure 18−8. Repeat-Sequence-of-Channels Mode

CONSEQx = 11

ADC10

Off

ADC10ON = 1

ENC =

x = INCHx

Wait for Enable

ENC =

SHS = 0

and

ENC =

ENC = 1 or

and

ADC10SC =

Wait for Trigger

SAMPCON =

(4/8/16/64) x ADC10CLK

Sample

Input Channel Ax

If x = 0 then x = INCH

else x = x −1

If x = 0 then x = INCH

else x = x −1

ENC = 0

and

x = 0

12 x ADC10CLK

1 x ADC10CLK

MSC = 0

and

(ENC = 1

Convert

MSC = 1

and

(ENC = 1

x ≠ 0)

Conversion

Completed,

x ≠ 0)

Result to ADC10MEM,

ADC10IFG is Set

x = input channel Ax

ADC10

18-13

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ADC10 Operation

Using the MSC Bit

To configure the converter to perform successive conversions automatically

and as quickly as possible, a multiple sample and convert function is available.

When MSC = 1 and CONSEQx > 0 the first rising edge of the SHI signal

triggers the first conversion. Successive conversions are triggered

automatically as soon as the prior conversion is completed. Additional rising

edges on SHI are ignored until the sequence is completed in the

single-sequence mode or until the ENC bit is toggled in repeat-single-channel,

or repeated-sequence modes. The function of the ENC bit is unchanged when

using the MSC bit.

Stopping Conversions

Stopping ADC10 activity depends on the mode of operation. The

recommended ways to stop an active conversion or conversion sequence are:

- Resetting ENC in single-channel single-conversion mode stops a

conversion immediately and the results are unpredictable. For correct

results, poll the ADC10BUSY bit until reset before clearing ENC.

- Resetting ENC during repeat-single-channel operation stops the

converter at the end of the current conversion.

- Resetting ENC during a sequence or repeat sequence mode stops the

converter at the end of the sequence.

- Any conversion mode may be stopped immediately by setting the

CONSEQx=0 and resetting the ENC bit. Conversion data is unreliable.

18-14

ADC10

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ADC10 Operation

18.2.7 ADC10 Data Transfer Controller

The ADC10 includes a data transfer controller (DTC) to automatically transfer

conversion results from ADC10MEM to other on-chip memory locations. The

DTC is enabled by setting the ADC10DTC1 register to a nonzero value.

When the DTC is enabled, each time the ADC10 completes a conversion and

loads the result to ADC10MEM, a data transfer is triggered. No software

intervention is required to manage the ADC10 until the predefined amount of

conversion data has been transferred. Each DTC transfer requires one CPU

MCLK. To avoid any bus contention during the DTC transfer, the CPU is halted,

if active, for the one MCLK required for the transfer.

A DTC transfer must not be initiated while the ADC10 is busy. Software must

ensure that no active conversion or sequence is in progress when the DTC is

configured:

; ADC10 activity test

BIC.W #ENC,&ADC10CTL0 ;

busy_testBIT.W #BUSY,&ADC10CTL1;

JNZ busy_test

;

MOV.W #xxx,&ADC10SA ; Safe

MOV.B #xx,&ADC10DTC1 ;

; continue setup

ADC10

18-15

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ADC10 Operation

One-Block Transfer Mode

The one-block mode is selected if the ADC10TB is reset. The value n in

ADC10DTC1 defines the total number of transfers for a block. The block start

address is defined anywhere in the MSP430 address range using the 16-bit

transfer mode is shown in Figure 18−9.

Figure 18−9. One-Block Transfer

TB=0

’n’th transfer

ADC10SA+2n−2

ADC10SA+2n−4

DTC

2nd transfer

1st transfer

ADC10SA+2

ADC10SA

The internal address pointer is initially equal to ADC10SA and the internal

transfer counter is initially equal to ‘n’. The internal pointer and counter are not

visible to software. The DTC transfers the word-value of ADC10MEM to the

address pointer ADC10SA. After each DTC transfer, the internal address

pointer is incremented by two and the internal transfer counter is decremented

by one.

The DTC transfers continue with each loading of ADC10MEM, until the

internal transfer counter becomes equal to zero. No additional DTC transfers

will occur until a write to ADC10SA. When using the DTC in the one-block

mode, the ADC10IFG flag is set only after a complete block has been

transferred. Figure 18−10 shows a state diagram of the one-block mode.

18-16

ADC10

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ADC10 Operation

Figure 18−10. State Diagram for Data Transfer Control in One-Block Transfer Mode

n=0 (ADC10DTC1)

DTC reset

n ≠ 0

Wait for write to

ADC10SA

n = 0

Prepare

DTC

Initialize

Start Address in ADC10SA

DTC init

Write to

ADC10SA

x = n

n is latched

in counter ’x’

AD = SA

Write to ADC10SA

n = 0

Wait until ADC10MEM

is written

DTC idle

Write to ADC10MEM

completed

Write to ADC10SA

Wait

for

CPU ready

Synchronize

with MCLK

x > 0

DTC

operation

Write to ADC10SA

1 x MCLK cycle

Transfer data to

Address AD

AD = AD + 2

x = x − 1

ADC10TB = 0

and

ADC10CT = 1

x = 0

ADC10TB = 0

and

ADC10CT = 0

ADC10IFG=1

ADC10

18-17

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ADC10 Operation

Two-Block Transfer Mode

The two-block mode is selected if the ADC10TB bit is set. The value n in

ADC10DTC1 defines the number of transfers for one block. The address

range of the first block is defined anywhere in the MSP430 address range with

the 16-bit register ADC10SA. The first block ends at ADC10SA+2n–2. The

address range for the second block is defined as SA+2n to SA+4n–2. The

two-block transfer mode is shown in Figure 18−11.

Figure 18−11.Two-Block Transfer

TB=1

2 x ’n’th transfer

ADC10SA+4n−2

ADC10SA+4n−4

’n’th transfer

ADC10SA+2n−2

ADC10SA+2n−4

DTC

2nd transfer

1st transfer

ADC10SA+2

ADC10SA

The internal address pointer is initially equal to ADC10SA and the internal

transfer counter is initially equal to ‘n’. The internal pointer and counter are not

visible to software. The DTC transfers the word-value of ADC10MEM to the

address pointer ADC10SA. After each DTC transfer the internal address

pointer is incremented by two and the internal transfer counter is decremented

by one.

The DTC transfers continue, with each loading of ADC10MEM, until the

internal transfer counter becomes equal to zero. At this point, block one is full

and both the ADC10IFG flag the ADC10B1 bit are set. The user can test the

ADC10B1 bit to determine that block one is full.

The DTC continues with block two. The internal transfer counter is

automatically reloaded with ’n’. At the next load of the ADC10MEM, the DTC

begins transferring conversion results to block two. After n transfers have

completed, block two is full. The ADC10IFG flag is set and the ADC10B1 bit

is cleared. User software can test the cleared ADC10B1 bit to determine that

block two is full. Figure 18−12 shows a state diagram of the two-block mode.

18-18

ADC10

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ADC10 Operation

Figure 18−12. State Diagram for Data Transfer Control in Two-Block Transfer Mode

n=0 (ADC10DTC1)

DTC reset

ADC10B1 = 0

ADC10TB = 1

n ≠ 0

n = 0

Wait for write to

ADC10SA

Initialize

Start Address in ADC10SA

Prepare

DTC

DTC init

Write to

ADC10SA

x = n

If ADC10B1 = 0

then AD = SA

n is latched

in counter ’x’

Write to ADC10SA

n = 0

Wait until ADC10MEM

is written

DTC idle

Write to ADC10MEM

completed

Write to ADC10SA

Wait

Synchronize

with MCLK

for

x > 0

CPU ready

DTC

operation

Write to ADC10SA

1 x MCLK cycle

Transfer data to

Address AD

AD = AD + 2

x = x − 1

ADC10B1 = 1

ADC10CT=1

x = 0

ADC10IFG=1

ADC10CT = 0

and

Toggle

ADC10B1

ADC10B1 = 0

ADC10

18-19

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ADC10 Operation

Continuous Transfer

A continuous transfer is selected if ADC10CT bit is set. The DTC will not stop

after block one in (one-block mode) or block two (two-block mode) has been

transferred. The internal address pointer and transfer counter are set equal to

ADC10SA and n respectively. Transfers continue starting in block one. If the

ADC10CT bit is reset, DTC transfers cease after the current completion of

transfers into block one (in the one-block mode) or block two (in the two-block

mode) have been transfer.

DTC Transfer Cycle Time

For each ADC10MEM transfer, the DTC requires one or two MCLK clock

cycles to synchronize, one for the actual transfer (while the CPU is halted), and

one cycle of wait time. Because the DTC uses MCLK, the DTC cycle time is

dependent on the MSP430 operating mode and clock system setup.

If the MCLK source is active, but the CPU is off, the DTC uses the MCLK

source for each transfer, without re-enabling the CPU. If the MCLK source is

off, the DTC temporarily restarts MCLK, sourced with DCOCLK, only during

a transfer. The CPU remains off and after the DTC transfer, MCLK is again

turned off. The maximum DTC cycle time for all operating modes is show in

Table 18−2.

Table 18−2.Maximum DTC Cycle Time

CPU Operating Mode

Clock Source

Maximum DTC Cycle Time

3 MCLK cycles

Active mode

MCLK=DCOCLK

MCLK=LFXT1CLK

3 MCLK cycles

Low-power mode LPM0/1 MCLK=DCOCLK

Low-power mode LPM3/4 MCLK=DCOCLK

Low-power mode LPM0/1 MCLK=LFXT1CLK

Low-power mode LPM3 MCLK=LFXT1CLK

Low-power mode LPM4 MCLK=LFXT1CLK

4 MCLK cycles

†

4 MCLK cycles + 6 µs

4 MCLK cycles

†

4 MCLK cycles + 6 µs

†

The additional 6 µs are needed to start the DCOCLK. It is the t

(LPMx)

parameter in the datasheet.

18-20

ADC10

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ADC10 Operation

18.2.8 Using the Integrated Temperature Sensor

To use the on-chip temperature sensor, the user selects the analog input

channel INCHx = 1010. Any other configuration is done as if an external

channel was selected, including reference selection, conversion-memory

selection, etc.

The typical temperature sensor transfer function is shown in Figure 18−13.

When using the temperature sensor, the sample period must be greater than

30 µs. The temperature sensor offset error can be large, and may need to be

calibrated for most applications. See the device-specific datasheet for the

parameters.

Selecting the temperature sensor automatically turns on the on-chip reference

generator as a voltage source for the temperature sensor. However, it does not

enable the V

output or affect the reference selections for the conversion.

REF+

The reference choices for converting the temperature sensor are the same as

with any other channel.

Figure 18−14. Typical Temperature Sensor Transfer Function

Volts

1.300

1.200

1.100

1.000

0.900

0.800

0.700

=0.00355(TEMP )+0.986

TEMP

Celsius

100

−50

ADC10

18-21

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ADC10 Operation

18.2.9 ADC10 Grounding and Noise Considerations

As with any high-resolution ADC, appropriate printed-circuit-board layout and

grounding techniques should be followed to eliminate ground loops, unwanted

parasitic effects, and noise.

Ground loops are formed when return current from the A/D flows through paths

that are common with other analog or digital circuitry. If care is not taken, this

current can generate small, unwanted offset voltages that can add to or

subtract from the reference or input voltages of the A/D converter. The

connections shown in Figure 18−15 help avoid this.

In addition to grounding, ripple and noise spikes on the power supply lines due

to digital switching or switching power supplies can corrupt the conversion

result. A noise-free design is important to achieve high accuracy.

Figure 18−16. ADC10 Grounding and Noise Considerations

Power Supply

Decoupling

10 uF

100 nF

MSP430F12x2

MSP430F11x2

REF+

External

Reference

REF−

18-22

ADC10

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ADC10 Operation

18.2.10 ADC10 Interrupts

One interrupt and one interrupt vector are associated with the ADC10 as

shown in Figure 18−17. When the DTC is not used (ADC10DTC1 = 0)

ADC10IFG is set when conversion results are loaded into ADC10MEM. When

DTC is used (ADC10DTC1 > 0) ADC10IFG is set when a block transfer

completes and the internal transfer counter ’n’ = 0. If both the ADC10IE and

the GIE bits are set, then the ADC10IFG flag generates an interrupt request.

The ADC10IFG flag is automatically reset when the interrupt request is

serviced or may be reset by software.

Figure 18−17. ADC10 Interrupt System

ADC10IE

Set ADC10IFG

’n’ = 0

IRQ, Interrupt Service Requested

IRACC, Interrupt Request Accepted

ADC10CLK

Reset

POR

ADC10

18-23

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ADC10 Registers

18.3 ADC10 Registers

The ADC10 registers are listed in Table 18−3.

Table 18−3.ADC10 Registers

Short Form

ADC10AE

Initial State

ADC10 Input enable register

ADC10 control register 0

ADC10 control register 1

ADC10 memory

Read/write

Read

04Ah

Reset with POR

Unchanged

ADC10CTL0

ADC10CTL1

ADC10MEM

01B0h

01B2h

01B4h

048h

ADC10 data transfer control register 0 ADC10DTC0

ADC10 data transfer control register 1 ADC10DTC1

Read/write

Reset with POR

0200h with POR

049h

ADC10 data transfer start address

ADC10SA

01BCh

18-24

ADC10

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ADC10 Registers

ADC10CTL0, ADC10 Control Register 0

SREFx

rw−(0)

ADC10SHTx

ADC10SR

rw−(0)

REFOUT

rw−(0)

REFBURST

rw−(0)

MSC

rw−(0)

REF2_5V

rw−(0)

REFON

rw−(0)

ADC10ON

rw−(0)

ADC10IE

rw−(0)

ADC10IFG

rw−(0)

ENC

rw−(0)

ADC10SC

rw−(0)

Modifiable only when ENC = 0

SREFx

Bits

Select reference

15-13

000 V = V

and V = V

R− SS

R+

CC R− SS

001 V = V

R+

REF+

010 V = Ve

and V = V

R+

REF+

R−

/ Ve

011 V = Ve

and V = V

R−

R+

REF+

100 V = V

and V = V

R+

R−

REF− REF−

101 V = V

and V = V

/ Ve

R+

REF+

R−

REF− REF−

110 V = Ve

and V = V

R+

REF+

R−

REF− REF−

/ Ve

REF− REF−

111

= Ve

and V = V

R+

R−

ADC10

SHTx

Bits

12-11

ADC10 sample-and-hold time

00 4 x ADC10CLKs

01 8 x ADC10CLKs

10 16 x ADC10CLKs

11 64 x ADC10CLKs

ADC10SR

Bit 10

ADC10 sampling rate. This bit selects the reference buffer drive capability for

the maximum sampling rate. Setting ADC10SR reduces the current

consumption of the reference buffer.

Reference buffer supports up to ~200 ksps

Reference buffer supports up to ~50 ksps

REFOUT

Bit 9

Bit 8

Reference output

Reference output off

Reference output on

REFBURST

Reference burst. REFOUT must also be set.

Reference buffer on continuously

Reference buffer on only during sample-and-conversion

ADC10

18-25

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ADC10 Registers

MSC

Bit 7

Multiple sample and conversion. Valid only for sequence or repeated modes.

The sampling requires a rising edge of the SHI signal to trigger each

sample-and-conversion.

The first rising edge of the SHI signal triggers the sampling timer, but

further sample-and-conversions are performed automatically as soon

as the prior conversion is completed

REF2_5V

REFON

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Reference-generator voltage. REFON must also be set.

1.5 V

2.5 V

Reference generator on

Reference off

Reference on

ADC10ON

ADC10IE

ADC10IFG

ADC10 on

ADC10 off

ADC10 on

ADC10 interrupt enable

Interrupt disabled

interrupt enabled

ADC10 interrupt flag. This bit is set if ADC10MEM is loaded with a conversion

result. It is automatically reset when the interrupt request is accepted, or it may

be reset by software. When using the DTC this flag is set when a block of

transfers is completed.

No interrupt pending

Interrupt pending

ENC

Bit 1

Bit 0

Enable conversion

ADC10 disabled

ADC10 enabled

ADC10SC

Start conversion. Software-controlled sample-and-conversion start.

ADC10SC and ENC may be set together with one instruction. ADC10SC is

reset automatically.

No sample-and-conversion start

Start sample-and-conversion

18-26

ADC10

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ADC10 Registers

ADC10CTL1, ADC10 Control Register 1

INCHx

SHSx

ADC10DF

ISSH

rw−(0)

ADC10

BUSY

ADC10DIVx

ADC10SSELx

CONSEQx

rw−(0)

r−0

Modifiable only when ENC = 0

INCHx

Bits

Input channel select. These bits select the channel for a single-conversion or

15-12

the highest channel for a sequence of conversions.

0000 A0

0001 A1

0010 A2

0011

0100 A4

0101 A5

0110

0111

1000 Ve

REF+

1001

/Ve

REF− REF−

1010 Temperature sensor

1011

1100

1101

1110

1111

– V ) / 2

SHSx

Bits

11-10

Sample-and-hold source select

00 ADC10SC bit

01 Timer_A.OUT1

10 Timer_A.OUT0

11 Timer_A.OUT2

ADC10DF

ISSH

Bit 9

Bit 8

ADC10 data format

Straight binary

2’s complement

Invert signal sample-and-hold

The sample-input signal is not inverted.

The sample-input signal is inverted.

ADC10

18-27

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ADC10 Registers

ADC10DIVx

Bits

7-5

ADC10 clock divider

000 /1

001 /2

010 /3

011 /4

100 /5

101 /6

110 /7

111 /8

ADC10

SSELx

Bits

4-3

ADC10 clock source select

00 ADC10OSC

01 ACLK

10 MCLK

11 SMCLK

CONSEQx

Bits

2-1

Conversion sequence mode select

00 Single-channel-single-conversion

01 Sequence-of-channels

10 Repeat-single-channel

11 Repeat-sequence-of-channels

ADC10

BUSY

Bit 0

ADC10 busy. This bit indicates an active sample or conversion operation

No operation is active.

A sequence, sample, or conversion is active.

ADC10AE, Analog (Input) Enable Control Register

ADC10AE7

rw−(0)

ADC10AE6

rw−(0)

ADC10AE5

rw−(0)

ADC10AE4

rw−(0)

ADC10AE3

rw−(0)

ADC10AE2

rw−(0)

ADC10AE1

rw−(0)

ADC10AE0

rw−(0)

ADC10AEx

Bits

ADC10 analog enable

7-0

Analog input disabled

Analog input enabled

18-28

ADC10

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ADC10 Registers

ADC10MEM, Conversion-Memory Register, Binary Format

Conversion Results

Conversion

Results

Bits

15-0

The 10-bit conversion results are right justified, straight-binary format. Bit 9

is the MSB. Bits 15-10 are always 0.

ADC10MEM, Conversion-Memory Register, 2’s Complement Format

Conversion Results

Conversion

Results

Bits

15-0

The 10-bit conversion results are left-justified, 2’s complement format. Bit 15

is the MSB. Bits 5-0 are always 0.

ADC10

18-29

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ADC10 Registers

ADC10DTC0, Data Transfer Control Register 0

ADC10

FETCH

Reserved

ADC10TB

rw−(0)

ADC10CT

rw−(0)

ADC10B1

rw−(0)

Reserved

ADC10TB

Bits

7-4

Reserved. Always read as 0.

ADC10 two-block mode.

Bit 3

One-block transfer mode

Two-block transfer mode

ADC10CT

ADC10B1

Bit 2

ADC10 continuous transfer.

Data transfer stops when one block (one-block mode) or two blocks

(two-block mode) have completed.

Data is transferred continuously. DTC operation is stopped only if

ADC10CT cleared, or ADC10SA is written to.

Bit 1

Bit 0

ADC10 block one. This bit indicates for two-block mode which block is filled

with ADC10 conversion results. ADC10B1 is valid only after ADC10IFG has

been set the first time during DTC operation. ADC10TB must also be set

Block 2 is filled

Block 1 is filled

ADC10

FETCH

This bit should normally be reset.

18-30

ADC10

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ADC10 Registers

ADC10DTC1, Data Transfer Control Register 1

DTC Transfers

rw−(0)

DTC

Transfers

Bits

7-0

DTC transfers. These bits define the number of transfers in each block.

DTC is disabled

01h-0FFh Number of transfers per block

ADC10SA, Start Address Register for Data Transfer

ADC10SAx

rw−(0)

rw−(1)

rw−(0)

ADC10SAx

rw−(0)

ADC10SAx

Unused

Bits

15-1

ADC10 start address. These bits are the start address for the DTC. A write

to register ADC10SA is required to initiate DTC transfers.

Bit 0

Unused, Read only. Always read as 0.

ADC10

18-31

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18-32

ADC10

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Chapter 19

DAC12

The DAC12 module is a 12-bit, voltage output digital-to-analog converter. This

chapter describes the DAC12. Two DAC12 modules are implemented in the

MSP430x15x and MSP430x16x devices.

Topic

Page

19.1 DAC12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

19.2 DAC12 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4

19.3 DAC12 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10

DAC12

19-1

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DAC12 Introduction

19.1 DAC12 Introduction

The DAC12 module is a 12-bit, voltage output DAC. The DAC12 can be

configured in 8- or 12-bit mode and may be used in conjunction with the DMA

controller. When multiple DAC12 modules are present, they may be grouped

together for synchronous update operation.

Features of the DAC12 include:

- 12-bit monotonic output

- 8- or 12-bit voltage output resolution

- Programmable settling time vs power consumption

- Internal or external reference selection

- Straight binary or 2’s compliment data format

- Self-calibration option for offset correction

- Synchronized update capability for multiple DAC12s

Note: Multiple DAC12 Modules

Some devices may integrate more than one DAC12 module. In the case

where more than one DAC12 is present on a device, the multiple DAC12

modules operate identically.

Throughout this chapter, nomenclature appears such as DAC12_xDAT or

DAC12_xCTL to describe register names. When this occurs, the x is used

to indicate which DAC12 module is being discussed. In cases where

operation is identical, the register is simply referred to as DAC12_xCTL.

The block diagram of the two DAC12 modules in the MSP430F15x/16x

devices is shown in Figure 19−1.

19-2

DAC12

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DAC12 Introduction

Figure 19−1. DAC12 Block Diagram

REF+

To ADC12 module

REF+

2.5V or 1.5V reference from ADC12

DAC12SREFx

DAC12AMPx

DAC12IR

R+

R−

DAC12LSELx

DAC12_0OUT

DAC12_0

Latch Bypass

TA1

TB2

DAC12RES

DAC12DF

DAC12_0Latch

DAC12_0DAT

DAC12GRP

ENC

DAC12_0DAT Updated

Group

Load

Logic

DAC12SREFx

DAC12AMPx

DAC12IR

R+

R−

DAC12LSELx

DAC12_1OUT

DAC12_1

Latch Bypass

TA1

TB2

DAC12RES

DAC12DF

DAC12_1Latch

DAC12_1DAT

DAC12GRP

ENC

DAC12_1DAT Updated

DAC12

19-3

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DAC12 Operation

19.2 DAC12 Operation

The DAC12 module is configured with user software. The setup and operation

of the DAC12 is discussed in the following sections.

19.2.1 DAC12 Core

The DAC12 can be configured to operate in 8- or 12-bit mode using the

DAC12RES bit. The full-scale output is programmable to be 1x or 3x the

selected reference voltage via the DAC12IR bit. This feature allows the user

to control the dynamic range of the DAC12. The DAC12DF bit allows the user

to select between straight binary data and 2’s compliment data for the DAC.

When using straight binary data format, the formula for the output voltage is

given in Table 19−1.

Table 19−1.DAC12 Full-Scale Range (Vref = V

or V

)

eREF+

REF+

Resolution DAC12RES

DAC12IR

Output Voltage Formula

12 bit

8 bit

DAC12_xDAT

4096

Vout + Vref 3

DAC12_xDAT

Vout + Vref

4096

DAC12_xDAT

256

Vout + Vref 3

8 bit

DAC12_xDAT

Vout + Vref

256

In 8-bit mode the maximum useable value for DAC12_xDAT is 0FFh and in

12-bit mode the maximum useable value for DAC12_xDAT is 0FFFh. Values

greater than these may be written to the register, but all leading bits are

ignored.

DAC12 Port Selection

The DAC12 outputs are multiplexed with the port P6 pins and ADC12 analog

inputs. When DAC12AMPx > 0, the DAC12 function is automatically selected

for the pin, regardless of the state of the associated P6SELx and P6DIRx bits.

19-4

DAC12

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DAC12 Operation

19.2.2 DAC12 Reference

The reference for the DAC12 is configured to use either an external reference

voltage or the internal 1.5-V/2.5-V reference from the ADC12 module with the

DAC12SREFx bits. When DAC12SREFx = {0,1} the V

signal is used as

REF+

the reference and when DAC12SREFx = {2,3} the Ve

reference.

signal is used as the

REF+

To use the ADC12 internal reference, it must be enabled and configured via

the applicable ADC12 control bits (see the ADC12 chapter). Once the ADC12

reference is configured, the reference voltage appears on the V

signal.

REF+

DAC12 Reference Input and Voltage Output Buffers

The reference input and voltage output buffers of the DAC12 can be

configured for optimized settling time vs power consumption. Eight

combinations are selected using the DAC12AMPx bits. In the low/low setting,

the settling time is the slowest, and the current consumption of both buffers is

the lowest. The medium and high settings have faster settling times, but the

current consumption increases. See the device-specific data sheet for

parameters.

19.2.3 Updating the DAC12 Voltage Output

The DAC12_xDAT register can be connected directly to the DAC12 core or

double buffered. The trigger for updating the DAC12 voltage output is selected

with the DAC12LSELx bits.

When DAC12LSELx = 0 the data latch is transparent and the DAC12_xDAT

immediately when new DAC12 data is written to the DAC12_xDAT register,

regardless of the state of the DAC12ENC bit.

When DAC12LSELx = 1, DAC12 data is latched and applied to the DAC12

core after new data is written to DAC12_xDAT. When DAC12LSELx = 2 or 3,

data is latched on the rising edge from the Timer_A CCR1 output or Timer_B

CCR2 output respectively. DAC12ENC must be set to latch the new data when

DAC12LSELx > 0.

DAC12

19-5

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DAC12 Operation

19.2.4 DAC12_xDAT Data Format

The DAC12 supports both straight binary and 2’s compliment data formats.

When using straight binary data format, the full-scale output value is 0FFFh

in 12-bit mode (0FFh in 8-bit mode) as shown in Figure 19−2.

Figure 19−2. Output Voltage vs DAC12 Data, 12-Bit, Straight Binary Mode

Output Voltage

Full-Scale Output

DAC Data

0FFFh

When using 2’s compliment data format, the range is shifted such that a

DAC12_xDAT value of 0800h (0080h in 8-bit mode) results in a zero output

voltage, 0000h is the mid-scale output voltage, and 07FFh (007Fh for 8-bit

mode) is the full-scale voltage output as shown in Figure 19−3.

Figure 19−3. Output Voltage vs DAC12 Data, 12-Bit, 2’s Compliment Mode

Output Voltage

Full-Scale Output

Mid-Scale Output

DAC Data

07FFh (+2047)

0800h (−2048)

19-6

DAC12

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DAC12 Operation

19.2.5 DAC12 Output Amplifier Offset Calibration

The offset voltage of the DAC12 output amplifier can be positive or negative.

When the offset is negative, the output amplifier attempts to drive the voltage

negative, but cannot do so. The output voltage remains at zero until the DAC12

digital input produces a sufficient positive output voltage to overcome the

negative offset voltage, resulting in the transfer function shown in Figure 19−4.

Figure 19−4. Negative Offset

Output Voltage

DAC Data

Negative Offset

When the output amplifier has a positive offset, a digital input of zero does not

result in a zero output voltage. The DAC12 output voltage reaches the

maximum output level before the DAC12 data reaches the maximum code.

This is shown in Figure 19−5.

Figure 19−5. Positive Offset

Output Voltage

DAC Data

Full-Scale Code

The DAC12 has the capability to calibrate the offset voltage of the output

amplifier. Setting the DAC12CALON bit initiates the offset calibration. The

calibration should complete before using the DAC12. When the calibration is

complete, the DAC12CALON bit is automatically reset. The DAC12AMPx bits

should be configured before calibration. For best calibration results, port and

CPU activity should be minimized during calibration.

DAC12

19-7

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DAC12 Operation

19.2.6 Grouping Multiple DAC12 Modules

Multiple DAC12s can be grouped together with the DAC12GRP bit to

synchronize the update of each DAC12 output. Hardware ensures that all

DAC12 modules in a group update simultaneously independent of any

interrupt or NMI event.

On the MSP430x15x and MSP430x16x devices, DAC12_0 and DAC12_1 are

grouped by setting the DAC12GRP bit of DAC12_0. The DAC12GRP bit of

DAC12_1 is don’t care. When DAC12_0 and DAC12_1 are grouped:

- The DAC12_1 DAC12LSELx bits select the update trigger for both DACs

- The DAC12LSELx bits for both DACs must be > 0

- The DAC12ENC bits of both DACs must be set to 1

When DAC12_0 and DAC12_1 are grouped, both DAC12_xDAT registers

must be written to before the outputs update - even if data for one or both of

the DACs is not changed. Figure 19−6 shows a latch-update timing example

for grouped DAC12_0 and DAC12_1.

When DAC12_0 DAC12GRP = 1 and both DAC12_x DAC12LSELx > 0 and

either DAC12ENC = 0, neither DAC12 will update.

Figure 19−6. DAC12 Group Update Example, Timer_A3 Trigger

DAC12_0

DAC12GRP

DAC12_0 and DAC12_1

Updated Simultaneously

DAC12_0

DAC12ENC

TimerA_OUT1

DAC12_0DAT

New Data

DAC12_0 Updated

DAC12_1DAT

New Data

DAC12_0

Latch Trigger

DAC12_0 DAC12LSELx = 2

DAC12_0 DAC12LSELx > 0 AND

DAC12_1 DAC12LSELx = 2

Note: DAC12 Settling Time

The DMA controller is capable of transferring data to the DAC12 faster than

the DAC12 output can settle. The user must assure the DAC12 settling time

is not violated when using the DMA controller. See the device-specific data

sheet for parameters.

19-8

DAC12

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DAC12 Operation

19.2.7 DAC12 Interrupts

The DAC12 interrupt vector is shared with the DMA controller. Software must

check the DAC12IFG and DMAIFG flags to determine the source of the

interrupt.

The DAC12IFG bit is set when DAC12LSELx > 0 and DAC12 data is latched

from the DAC12_xDAT register into the data latch. When DAC12LSELx = 0,

the DAC12IFG flag is not set.

A set DAC12IFG bit indicates that the DAC12 is ready for new data. If both the

DAC12IE and GIE bits are set, the DAC12IFG generates an interrupt request.

The DAC12IFG flag is not reset automatically. It must be reset by software.

DAC12

19-9

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DAC12 Registers

19.3 DAC12 Registers

The DAC12 registers are listed in Table 19−2:

Table 19−2.DAC12 Registers

Short Form

Initial State

DAC12_0 control

DAC12_0 data

DAC12_1 control

DAC12_1 data

DAC12_0CTL

DAC12_0DAT

DAC12_1CTL

DAC12_1DAT

Read/write

01C0h

01C8h

01C2h

01CAh

Reset with POR

19-10

DAC12

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DAC12 Registers

DAC12_xCTL, DAC12 Control Register

DAC12

CALON

Reserved

rw−(0)

DAC12SREFx

DAC12RES

rw−(0)

DAC12LSELx

DAC12IR

rw−(0)

DAC12

DAC12AMPx

rw−(0)

DAC12DF

rw−(0)

DAC12IE

rw−(0)

DAC12IFG

rw−(0)

DAC12ENC

GRP

rw−(0)

Modifiable only when DAC12ENC = 0

Reserved

Bit 15

Reserved

DAC12 select reference voltage

DAC12

SREFx

Bits

14-13

REF+

10 Ve

11 Ve

REF+

DAC12

RES

Bit 12

DAC12 resolution select

12-bit resolution

8-bit resolution

DAC12

LSELx

Bits

11-10

DAC12 load select. Selects the load trigger for the DAC12 latch. DAC12ENC

must be set for the DAC to update, except when DAC12LSELx = 0.

00 DAC12 latch loads when DAC12_xDAT written (DAC12ENC is ignored)

01 DAC12 latch loads when DAC12_xDAT written, or, when grouped,

when all DAC12_xDAT registers in the group have been written.

10 Rising edge of Timer_A.OUT1 (TA1)

11 Rising edge of Timer_B.OUT2 (TB2)

DAC12

CALON

Bit 9

Bit 8

DAC12 calibration on. This bit initiates the DAC12 offset calibration sequence

and is automatically reset when the calibration completes.

Calibration is not active

Initiate calibration/calibration in progress

DAC12IR

DAC12 input range. This bit sets the reference input and voltage output range.

DAC12 full-scale output = 3x reference voltage

DAC12 full-scale output = 1x reference voltage

DAC12

19-11

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DAC12 Registers

DAC12

AMPx

Bits

7-5

DAC12 amplifier setting. These bits select settling time vs. current

consumption for the DAC12 input and output amplifiers.

DAC12AMPx

Input Buffer

Output Buffer

DAC12 off, output high Z

DAC12 off, output 0 V

Low speed/current

000

001

010

011

100

101

110

111

Off

Low speed/current

Medium speed/current

High speed/current

Medium speed/current

High speed/current

Medium speed/current

High speed/current

DAC12DF

DAC12IE

DAC12IFG

Bit 4

Bit 3

Bit 2

Bit 1

DAC12 data format

Straight binary

2’s compliment

DAC12 interrupt enable

Disabled

Enabled

DAC12 Interrupt flag

No interrupt pending

Interrupt pending

DAC12

ENC

DAC12 enable conversion. This bit enables the DAC12 module when

DAC12LSELx > 0. when DAC12LSELx = 0, DAC12ENC is ignored.

DAC12 disabled

DAC12 enabled

DAC12

GRP

Bit 0

DAC12 group. Groups DAC12_x with the next higher DAC12_x. Not used for

DAC12_1 on MSP430x15x and MSP430x16x devices.

Not grouped

Grouped

19-12

DAC12

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DAC12 Registers

DAC12_xDAT, DAC12 Data Register

DAC12 Data

r(0)

rw−(0)

DAC12 Data

rw−(0)

Unused

Bits

15-12

Unused. These bits are always 0 and do not affect the DAC12 core.

DAC12 data

DAC12 Data

Bits

11-0

DAC12 Data Format

12-bit binary

DAC12 Data

The DAC12 data are right-justified. Bit 11 is the MSB.

12-bit 2’s complement

The DAC12 data are right-justified. Bit 11 is the MSB

(sign).

8-bit binary

The DAC12 data are right-justified. Bit 7 is the MSB.

Bits 11-8 are don’t care and do not effect the DAC12

core.

8-bit 2’s complement

The DAC12 data are right-justified. Bit 7 is the MSB

(sign). Bits 11-8 are don’t care and do not effect the

DAC12 core.

DAC12

19-13

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19-14

DAC12

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