MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
Low Supply Voltage Range 1.8 V – 3.6 V
Serial Onboard Programming
Ultralow-Power Consumption
Low Operation Current,
1.3 µA at 4 kHz, 2.2 V
Programmable Code Protection by Security
Fuse (C11x1 Only)
Family Members Include:
160 µA at 1 MHz, 2.2 V
MSP430C1111: 2KB ROM,128B RAM
MSP430C1121: 4KB ROM, 256B RAM
MSP430F1101: 1KB + 128B Flash Memory
(MTP ), 128B RAM
MSP430F1121: 4KB + 256B Flash Memory
(MTP ), 256B RAM
Available in a 20-Pin Plastic Small-Outline
Wide Body (SOWB) Package and 20-Pin
Plastic Thin Shrink Small-Outline Package
(TSSOP)
Five Power Saving Modes:
(Standby Mode: 0.8 µA,
RAM Retention Off Mode: 0.1 µA)
Wake-Up From Standby Mode in 6 µs
16-Bit RISC Architecture, 125 ns
Instruction Cycle Time
Basic Clock Module Configurations:
– Various Internal Resistors
– Single External Resistor
– 32 kHz Crystal
– High Frequency Crystal
– Resonator
DW OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TEST
VCC
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/CA1/TA2
P2.3/CA0/TA1
– External Clock Source
16-Bit Timer With Three Capture/Compare
Registers
P2.5/R
osc
SS
V
XOUT
Slope A/D Converter With External
Components
XIN
RST/NMI
P2.0/ACLK
On-Chip Comparator for Analog Signal
Compare Function or Slope A/D
Conversion
P2.1/INCLK
P2.2/CAOUT/TA0
description
The Texas Instruments MSP430 series is an ultralow-power microcontroller family consisting of several devices
featuringdifferentsetsofmodulestargetedtovariousapplications. Themicrocontrollerisdesignedtobebattery
operated for an extended-application lifetime. With 16-bit RISC architecture, 16 bit integrated registers on the
CPU, and a constant generator, the MSP430 achieves maximum code efficiency. The digitally-controlled
oscillator provides fast wake-up from all low-power modes to active mode in less than 6 s.
Typicalapplicationsincludesensorsystemsthatcaptureanalogsignals, convertthemtodigitalvalues, andthen
process the data and display them or transmit them to a host system. Stand alone RF sensor front end is another
area of application. The I/O port inputs provide single slope A/D conversion capability on resistive sensors. The
MSP430x11x series is an ultralow-power mixed signal microcontroller with a built in 16-bit timer and fourteen
I/O pins. The MSP430x11x1 family adds a versatile analog comparator.
The flash memory provides added flexibility of in-system programming and data storage without significantly
increasing the current consumption of the device. The programming voltage is generated on-chip, thereby
alleviating the need for an additional supply, and even allowing for reprogramming of battery-operated systems.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MTP = Multiple Time Programmable
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
Terminal Functions
TERMINAL
NAME
P1.0/TACLK
I/O
DESCRIPTION
NO.
13
14
15
16
17
I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input
P1.1/TA0
I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output
I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.2/TA1
P1.3/TA2
P1.4/SMCLK/TCK
I/O General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device programming
and test
P1.5/TA0/TMS
18
I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input terminal for
device programming and test
P1.6/TA1/TDI
19
20
I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal
†
P1.7/TA2/TDO/TDI
I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or data input
during programming
P2.0/ACLK
8
9
I/O General-purpose digital I/O pin/ACLK output
P2.1/INCLK
I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/CAOUT/TA0
P2.3/CA0/TA1
P2.4/CA1/TA2
10
11
12
3
I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/comparator_A, output
I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/comparator_A, input
I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/comparator_A, input
I/O General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency
P2.5/R
osc
RST/NMI
TEST
7
I
I
Reset or nonmaskable interrupt input
1
Select of test mode for JTAG pins on Port1. Must be tied low with less than 30 kΩ (F11x1).
VCC
2
Supply voltage
V
SS
4
Ground reference
XIN
6
I
Input terminal of crystal oscillator
XOUT
5
I/O Output terminal of crystal oscillator
†
TDO or TDI is selected via JTAG instruction.
short-form description
processing unit
The processing unit is based on a consistent, and orthogonally-designed CPU and instruction set. This design
structure results in a RISC-like architecture, highly transparent to the application development, and noted for
its programming simplicity. All operations other than program-flow instructions are consequently performed as
register operations in conjunction with seven addressing modes for source, and four modes for destination
operands.
3
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
short-form description (continued)
CPU
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
Program Counter
Stack Pointer
All sixteen registers are located inside the CPU,
providing reduced instruction execution time. This
reduces a register-register operation execution
time to one cycle of the processor.
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
Four registers are reserved for special use as a
program counter, a stack pointer, a status register,
and a constant generator. The remaining twelve
registers are available as general-purpose
registers.
R5
Peripherals are connected to the CPU using a
data address and control buses and can be
handled easily with all instructions for memory
manipulation.
General-Purpose Register
General-Purpose Register
R14
R15
instruction set
The instructions set for this register-register architecture provides a powerful and easy-to-use assembly
language. The instruction set consists of 51 instructions with three formats and seven addressing modes.
Table 1 provides a summation and example of the three types of instruction formats; the addressing modes are
listed in Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destination e.g. ADD R4, R5
R4 + R5 → R5
Single operands, destination only
Relative jump, un-/conditional
e.g. CALL R8
e.g. JNE
PC → (TOS), R8 → PC
Jump-on equal bit = 0
Most instructions can operate on both word and byte data. Byte operations are identified by the suffix B.
Examples:
Instructions for word operation
Instructions for byte operation
MOV
ADD
PUSH
SWPB
EDE,TONI
#235h,&MEM
R5
MOV.B
ADD.B
PUSH.B R5
—
EDE,TONI
#35h,&MEM
R5
Table 2. Address Mode Descriptions
ADDRESS MODE
s
d
SYNTAX
MOV Rs, Rd
EXAMPLE
MOV R10, R11
OPERATION
Register
√
√
√
√
√
√
√
√
√
√
√
R10 → R11
Indexed
MOV X(Rn), Y(Rm)
MOV EDE, TONI
MOV &MEM, &TCDAT
MOV @Rn, Y(Rm)
MOV @Rn+, RM
MOV #X, TONI
MOV 2(R5), 6(R6)
M(2 + R5) → M(6 + R6)
M(EDE) → M(TONI)
Symbolic (PC relative)
Absolute
M(MEM) → M(TCDAT)
M(R10) → M(Tab + R6)
M(R10) → R11, R10 + 2 → R10
#45 → M(TONI)
Indirect
MOV @R10, Tab(R6)
MOV @R10+, R11
MOV #45, TONI
Indirect autoincrement
Immediate
NOTE: s = source d = destination Rs/Rd = source register/destination register Rn = register number
4
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
instruction set (continued)
Computedbranches(BR)andsubroutinecalls(CALL)instructionsusethesameaddressingmodesastheother
instructions. These addressing modes provide indirect addressing, ideally suited for computed branches and
calls. The full use of this programming capability permits a program structure different from conventional 8- and
16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks
instead of using flag type programs for flow control.
operation modes and interrupts
The MSP430 operating modes support various advanced requirements for ultralow-power and ultralow energy
consumption. This is achieved by the intelligent management of the operations during the different module
operation modes and CPU states. The advanced requirements are fully supported during interrupt event
handling. An interrupt event awakens the system from each of the various operating modes and returns with
the RETI instruction to the mode that was selected before the interrupt event. The different requirements of the
CPU and modules, which are driven by system cost and current consumption objectives, necessitate the use
of different clock signals:
Auxiliary clock ACLK (from LFXT1CLK/crystal’s frequency), used by the peripheral modules
Main system clock MCLK, used by the CPU and system
Subsystem clock SMCLK, used by the peripheral modules
low-power consumption capabilities
The various operating modes are controlled by the software through controlling the operation of the internal
clock system. This clock system provides many combinations of hardware and software capabilities to run the
application with the lowest power consumption and with optimized system costs:
Use the internal clock (DCO) generator without any external components.
Select an external crystal or ceramic resonator for lowest frequency or cost.
Select and activate the proper clock signals (LFXT1CLK and/or DCOCLK) and clock pre-divider function.
Apply an external clock source.
Four of the control bits that influence the operation of the clock system and support fast turnon from low power
operating modes are located in the status register SR. The four bits that control the CPU and the system clock
generator are SCG1, SCG0, OscOff, and CPUOff:
5
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
status register R2
15
Reserved For Future
Enhancements
rw-0
9
8
7
6
5
4
3
2
N
1
0
V
SCG1
rw-0
SCG0
rw-0
OscOff
rw-0
CPUOff
rw-0
GIE
rw-0
Z
C
rw-0
rw-0
rw-0
rw-0
The bits CPUOff, SCG1, SCG0, and OscOff are the most important low-power control bits when the basic
function of the system clock generator is established. They are pushed onto the stack whenever an interrupt
is accepted and thereby saved so that the previous mode of operation can be retrieved after the interrupt
request. During execution of an interrupt handler routine, the bits can be manipulated via indirect access of the
data on the stack. That allows the program to resume execution in another power operating mode after the
return from interrupt (RETI).
SCG1:
The clock signal SMCLK, used for peripherals, is enabled when bit SCG1 is reset or disabled if
the bit is set.
SCG0:
The dc-generator is active when SCG0 is reset. The dc-generator can be deactivated only if the
SCG0 bit is set and the DCOCLK signal is not used for MCLK or SMCLK. The current consumed
by the dc-generator defines the basic frequency of the DCOCLK. It is a dc current.
The clock signal DCOCLK is deactivated if it is not used for MCLK or SMCLK or if the SCG0 bit
is set. There are two situations when the SCG0 bit cannot switch off the DCOCLK signal:
1. DCOCLK frequency is used for MCLK (CPUOff=0 and SELM.1=0).
2. DCOCLK frequency is used for SMCLK (SCG1=0 and SELS=0).
NOTE:
When the current is switched off (SCG0=1) the start of the DCOCLK is delayed slightly. The delay
is in the µs-range (see device parameters for details).
OscOff:
CPUOff:
The LFXT1 crystal oscillator is active when the OscOff bit is reset. The LFXT1 oscillator can only
be deactivated if the OscOff bit is set and it is not used for MCLK or SMCLK. The setup time to
start a crystal oscillation needs consideration when oscillator off option is used. Mask
programmable(ROM)devicescandisablethisfeaturesothattheoscillatorcanneverbeswitched
off by software.
The clock signal MCLK, used for the CPU, is active when the CPUOff bit is reset or stopped if it
is set.
6
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the memory with an address range of
0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction
sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
WDTIFG (Note1)
KEYV (Note 1)
Power-up, external reset, watchdog
Reset
0FFFEh
15, highest
(non)-maskable,
(non)-maskable,
(non)-maskable
NMIIFG (Notes 1 and 4)
OFIFG (Notes 1 and 4)
ACCVIFG (Notes 1 and 4)
NMI, oscillator fault, flash memory
access violation
0FFFCh
14
0FFFAh
0FFF8h
0FFF6h
0FFF4h
0FFF2h
13
12
11
10
9
Comparator_A
Watchdog timer
Timer_A
CAIFG
maskable
maskable
maskable
WDTIFG
CCIFG0 (Note 2)
CCIFG1, CCIFG2, TAIFG
(Notes 1 and 2)
Timer_A
maskable
0FFF0h
8
0FFEEh
0FFECh
0FFEAh
0FFE8h
7
6
5
4
P2IFG.0 to P2IFG.7
(Notes 1 and 2)
I/O Port P2 (eight flags – see Note 3)
I/O Port P1 (eight flags)
maskable
maskable
0FFE6h
0FFE4h
3
2
P1IFG.0 to P1IFG.7
(Notes 1 and 2)
0FFE2h
0FFE0h
1
0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module
3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0–5) are implemented on the 11x1 devices.
4. (non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt enable bit will disable an interrupt event.
7
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
7
6
5
4
3
2
1
0
Address
0h
OFIE
WDTIE
ACCVIE
NMIIE
rw-0
rw-0
rw-0
rw-0
WDTIE:
OFIE:
Watchdog timer enable signal
Oscillator fault enable signal
NMIIE:
ACCVIE:
Nonmaskable interrupt enable signal
Access violation at flash memory
7
6
5
4
3
3
2
2
1
0
Address
01h
interrupt flag register 1 and 2
7
6
5
4
1
0
Address
02h
NMIIFG
OFIFG
WDTIFG
rw-0
rw-1
rw-0
WDTIFG:
Set on overflow or security key violation or
Reset on V power-on or reset condition at RST/NMI-pin
Flag set on oscillator fault
Set via RST/NMI-pin
CC
OFIFG:
NMIIFG:
7
6
5
4
3
2
1
0
Address
03h
Legend rw:
Bit can be read and written.
rw-0:
Bit can be read and written. It is reset by PUC
SFR bit is not present in device.
8
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
memory organization
MSP430C1111
MSP430C1121
Int. Vector
MSP430F1101
MSP430F1121
Int. Vector
FFFFh
FFE0h
FFDFh
FFFFh
FFE0h
FFDFh
FFFFh
FFE0h
FFDFh
FFFFh
FFE0h
Int. Vector
2 KB ROM
Int. Vector
1 KB Flash
Segment0,1
FFDFh
4 KB
Flash
Segment0–7
Main
Memory
FC00h
F800h
4 KB
ROM
F000h
10FFh
F000h
10FFh
1080h
128B Flash
SegmentA
2 × 128B
Flash
Information
Memory
SegmentA,B
1000h
0FFFh
0C00h
1 KB
Boot ROM
1 KB
Boot ROM
0FFFh
0C00h
02FFh
0200h
02FFh
256B RAM
256B RAM
027Fh
027Fh
128B RAM
16b Per.
8b Per.
SFR
128B RAM
16b Per.
8b Per.
SFR
0200h
01FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
01FFh
0100h
00FFh
0010h
000Fh
0000h
16b Per.
8b Per.
SFR
16b Per.
8b Per.
SFR
0100h
00FFh
0010h
000Fh
0000h
boot ROM containing bootstrap loader
The intention of the bootstrap loader is to download data into the flash memory module. Various write, read, and
erase operations are needed for a proper download environment. The bootstrap loader is only available on F
devices.
functions of the bootstrap loader:
Definition of read:
write:
apply and transmit data of peripheral registers or memory to pin P1.1 (BSLTX)
read data from pin P2.2 (BSLRX) and write them into flash memory
unprotected functions
Mass erase, erase of the main memory (Segment0 to Segment7)
Access to the MSP430 via the bootstrap loader is protected. It must be enabled before any protected function
can be performed. The 256 bits in 0FFE0h to 0FFFFh provide the access key.
protected functions
All protected functions can be executed only if the access is enabled.
Write/program byte into flash memory; Parameters passed are start address and number of bytes (the
segment-write feature of the flash memory is not supported and not useful with the UART protocol).
Segment erase of Segment0 to Segment7 in the main memory and segment erase of SegmentA and
SegmentB in the information memory.
Read all data in main memory and information memory.
Read and write to all byte peripheral modules and RAM.
Modify PC and start program execution immediately.
NOTE:
Unauthorized readout of code and data is prevented by the user’s definition of the data in the
interrupt memory locations.
9
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
boot ROM containing bootstrap loader (continued)
features of the bootstrap loader are:
UART communication protocol, fixed to 9600 baud
Port pin P1.1 for transmit, P2.2 for receive
TI standard serial protocol definition
Implemented in flash memory version only
Program execution starts with the user vector at 0FFFEh or with the bootstrap loader (start vector is at
address 0C00h)
hardware resources used for serial input/output:
Pins P1.1 and P2.2 for serial data transmission
Test and RST/NMI to start program execution at the reset or bootstrap loader vector
Basic clock module: Rsel=5, DCO=4, MOD=0, DCOCLK for MCLK and SMCLK, clock divider for MCLK
and SMCLK at default: dividing by 1
Timer_A: Timer_A operates in continuous mode with MCLK source selected, input divider set to 1,
using CCR0, and polling of CCIFG0.
WDT:
Watchdog timer is halted
Interrupt: GIE=0, NMIIE=0, OFIFG=0, ACCVIFG=0
Memory allocation and stack pointer:
If the stack pointer points to RAM addresses above 0220h, 6 bytes of the stack are allocated
plus RAM addresses 0200h to 0219h. Otherwise the stack pointer is set to 0220h and allocates
RAM from 0200h to 021Fh.
NOTE:
When writing RAM data via bootstrap loader, take care that the stack is outside the range
of the data being written.
Program execution begins with the user’s reset vector at FFFEh (standard method) if TEST is held low while
RST/NMI goes from low to high:
V
CC
RST/NMI PIN
TEST PIN
User Program Starts
Reset Condition
10
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
boot ROM containing bootstrap loader (continued)
Program execution begins with the bootstrap vector at 0C00h (boot ROM) if a minimum of two positive edges
have been applied to TEST while RST/NMI is low, and TEST is high when RST/NMI goes from low to high. The
TEST signal is normally used internally to switch pins P1.4, P1.5, P1.6, and P1.7 between their application
function and the JTAG function. If the second rising edge at TEST is applied while RST/NMI is held low, the
internal TEST signal is held low and the pins remain in the application mode:
V
CC
RST/NMI PIN
TEST PIN
Bootstrap loader Starts
TEST
(Internal)
Test mode can be entered again after TEST is taken low and then back high.
The bootstrap loader will not be started (via the vector in address 0C00h), if:
There were less than two positive edges at TEST while RST/NMI is low
TEST is low if RST/NMI goes from low to high
JTAG has control over the MSP430 resources
Supply voltage VCC drops and a POR is executed
WARNING:
The bootstrap loader starts correctly only if the RST/NMI pin is in reset mode. If it is switched
to the NMI function, unpredictable program execution may result. However, a
bootstrap-load may be started using software and the bootstrap vector, for example the
instruction BR &0C00h.
11
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
flash memory
0FFFFh
0FE00h
Segment0 w/
Interrupt Vectors
The flash memory consists of 512-byte segments
in the main memory and 128-byte segments in the
information memory. See device memory maps
for specific device information.
0FDFFh
0FC00h
Segment1
Segment2
Segment3
Segment4
Segment5
Segment6
Segment7
SegmentA
SegmentB
0FBFFh
0FA00h
Segment0 to Segment7 can be erased
individually, or altogether as a group.
0F9FFh
0F800h
SegmentA and SegmentB can be erased
individually, or as a group with segments 0–7.
0F7FFh
0F600h
The memory in SegmentA and SegmentB is also
called Information Memory.
0F5FFh
0F400h
VPP is generated internally. VCC current
increases during programming.
0F3FFh
0F200h
0F1FFh
0F000h
During program/erase cycles, VCC must not drop
below the minimum specified for program/erase
operation.
010FFh
01080h
Program and erase timings are controlled by the
flash timing generator—no software intervention
is needed. The input frequency of the flash timing
generator should be in the proper range and must
be applied until the write/program or erase
operation is completed.
0107Fh
01000h
NOTE: All segments not implemented on all devices.
During program or erase, no code can be executed from flash memory and all interrupts must be disabled by
setting the GIE, NMIE, ACCVIE, and OFIE bits to zero. If a user program requires execution concurrent with
a flash program or erase operation, the program must be executed from memory other than the flash memory
(e.g., boot ROM, RAM). In the event a flash program or erase operation is initiated while the program counter
is pointing to the flash memory, the CPU will execute JMP $ instructions until the flash program or erase
operation is completed. Normal execution of the previously running software then resumes.
Unprogrammed, new devices may have some bytes programmed in the information memory (needed for test
during manufacturing). The user should perform an erase of the information memory prior to first use.
flash memory control register FCTL1
All control bits are reset during PUC. PUC is active after V
is applied, a reset condition is applied to the
CC
RST/NMI pin, the watchdog timer expires, a watchdog access violation occurs, or an improper flash operation
hasbeenperformed. Amoredetaileddescriptionofthecontrol-bitfunctionsisfoundintheflashmemorymodule
description (refer to MSP430x1xx User’s Guide, literature number SLAU049). Any write to control register
FCTL1 during erase, mass erase, or write (programming) will end in an access violation with ACCVIFG=1.
Special conditions apply for segment-write mode. Refer to MSP430x1xx User’s Guide, literature number
SLAU049 for details.
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
flash memory control register FCTL1 (continued)
Read access is possible at any time without restrictions.
The control bits of control register FCTL1 are:
15
FCTL1
0128h
8
7
0
SEG
WRT
WRT
res.
res.
res.
MEras
rw–0
Erase
res.
rw–0
rw–0
r0
r0
r0
rw-0
r0
FCTL1 read:
FCTL1 write:
096h
0A5h
Erase
MEras
WRT
0128h, bit1, Erase a segment
0: No segment erase will be started.
1: Erase of one segment is enabled. The segment to be erased is defined by a
dummy write into any address within the segment. The erase bit is
automatically reset when the erase operation is completed.
0128h, bit2, Mass Erase, main memory segments are erased together.
0: No segment erase will be started.
1: Erase of main memory segments is enabled. Erase starts when a dummy
write to any address in main memory is executed. The MEras bit is
automatically reset when the erase operation is completed.
0128h, bit6, Bit WRT must be set for a successful write execution.
If bit WRT is reset and write access to the flash memory is attempted, an
access violation occurs and ACVIFG is set.
SEGWRT 0128h, bit7, Bit SEGWRT may be used to reduce total programming time.
Refer to MSP430x1xx User’s Guide, literature number SLAU049 for details.
0: No segment-write acceleration is selected.
1: Segment-write is used. This bit needs to be reset and set between segment
borders.
Table 3. Allowed Combinations of Control Bits Allowed for Flash Memory Access
FUNCTION PERFORMED
SEGWRT WRT MEras Erase BUSY
WAIT
Lock
Write word or byte
0
1
0
0
1
1
0
0
0
0
0
1
0
0
1
0
0
0 → 1
0
0
0 → 1
0
0
0
0
0
Write word or byte in same segment, segment write mode
Erase one segment by writing to any address in the target segment
Erase all segments (0 to 7) but not the information memory
(segments A and B)
0
0
Erase all segments (0 to 7 and A and B) by writing to any address in
the flash memory module
0
0
1
1
0
0
0
NOTE: The table shows all valid combinations. Any other combination will result in an access violation.
flash memory, timing generator, control register FCTL2
The timing generator (Figure 1) generates all the timing signals necessary for write, erase, and mass erase from
the selected clock source. One of three different clock sources may be selected by control bits SSEL0 and
SSEL1 in control register FCTL2. The selected clock source should be divided to meet the frequency
requirements specified in the recommended operating conditions.
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
flash memory, timing generator, control register FCTL2 (continued)
The flash timing generator is reset with PUC. It is also reset if the emergency exit bit EMEX is set.
Control register FCTL2 may not be written to if the BUSY bit is set; otherwise, an access violation will occur
(ACCVIFG=1).
Read access is possible at any time without restrictions.
SSEL1
SSEL0
Write ’1’ to
EMEX
PUC
FN5.......... FN0
0
1
2
3
ACLK
MCLK
SMCLK
SMCLK
Reset
Flash Timing
Generator
f
X
Divider,
1 .. 64
BUSY
WAIT
Figure 1. Flash Memory Timing Generator Diagram
15
8
7
0
FCTL2
012Ah
SSEL1 SSEL0
FN5
FN4
FN3
FN2
FN1
FN0
rw–0
rw–1
rw-0
rw-0
rw-0
rw–0
rw-1
rw-0
FCTL2 read:
FCTL2 write:
096h
0A5h
The control bits are:
FN0–FN5
012Ah, bit0–5 These six bits define the division rate of the clock signal. The division
rate is 1 to 64, according to the digital value of FN5 to FN0 plus one.
SSEL0, SSEL1
012Ah, bit6,7 Clock source select
0: ACLK
1: MCLK
2: SMCLK
3: SMCLK
The flash timing generator is reset with PUC. It is also reset if the EMEX bit is set.
flash memory control register FCTL3
There are no restrictions to modify this control register.
15
8
7
0
FCTL3
012Ch
ACCV
IFG
res.
res.
EMEX
Lock
WAIT
KEYV
BUSY
r0
r0
rw-0
rw-1
rw-1
rw–0
rw-(0) r(w)-0
FCTL3 read:
FCTL3 write:
096h
0A5h
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
flash memory control register FCTL3 (continued)
BUSY
012Ch, bit0, The BUSY bit shows if an access to the flash memory is allowed (BUSY=0), or
if an access violation occurs. The BUSY bit is read-only, but a write operation is
allowed. The BUSY bit should be tested before each write and erase cycle. The
flash timing-generator hardware immediately sets the BUSY bit after start of a
write, segment-write, erase, or mass erase operation. If the timing generator has
completed the operation, the BUSY bit is reset by the hardware.
No program code can be executed from the busy flash memory during the entire
program or erase cycle.
0: Flash memory is not busy.
1: Flash memory is busy, and remains in busy state if segment write function
is in wait mode.
KEYV,
012Ch, bit1 Key violation
0: Key 0A5h (high byte) was not violated.
1: Key 0A5h (high byte) was violated. Violation occurs when a write access to
registers FCTL1, FCTL2, or FCTL3 is executed and the high byte is not
equal to 0A5h. If the security key is violated, bit KEYV is set and a PUC is
performed.
ACCVIFG, 012Ch, bit2 Access violation interrupt flag
The access-violation flag is set when any combination of control bits other than
those shown in Table 3 is attempted, or an instruction is fetched while a
segment-write operation is active.
Reading the control registers will not set the ACCVIFG bit.
NOTE: The respective interrupt-enable bit ACCVIE is located in the interrupt
enable register IE1 in the special function register. The software can set
the ACCVIFG bit. If set by software, an NMI is also executed.
WAIT,
012CH, bit3 In the segment-write mode, the WAIT bit indicates that data has been written and
the flash memory is prepared to receive the next data for programming. The
WAIT bit is read only, but a write to the WAIT bit is allowed.
0: The segment-write operation has began and programming is in progress.
1: The segment-write operation is active and data programming is complete.
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
flash memory control register FCTL3 (continued)
LOCK
012Ch, bit4, The lock bit may be set during any write, segment-erase, or mass-erase request.
Any active sequence in progress is completed normally. In segment-write mode,
the SEGWRT bit is reset and the WAIT bit is set after the mode ends. The lock
bit is controlled by software or hardware. If an access violation occurs and the
ACCVIFG is set, the LOCK bit is set automatically.
0: Flash memory may be read, programmed, erased, or mass erased.
1: Flash memory may be read but not programmed, erased, or mass erased.
A current program, erase, or mass-erase operation will complete normally.
The access-violation interrupt flag ACCVIFG is set when data are written to
the flash memory module while the lock bit is set.
EMEX,
012Ch, bit5, Emergency exit. The emergency exit should only be used if the flash memory
write or erase operation is out of control.
0: No function.
1: Stops the active operation immediately, and shuts down all internal parts in
the flash memory controller. Current consumption immediately drops back
to the active mode. All bits in control register FCTL1 are reset. Since the
EMEX bit is automatically reset by hardware, the software always reads
EMEX as 0.
flash memory, interrupt and security key violation
One NMI vector is used for three NMI events: RST/NMI (NMIIFG), oscillator fault (OFIFG), and flash-memory
access violation (ACCVIFG). The software can determine the source of the interrupt request since all flags
remain set until they are reset by software. The enable flag(s) should be set simultaneously with one instruction
before the return-from-interrupt RETI instruction. This ensures that the stack remains under control. A pending
NMI interrupt request will not increase stack demand unnecessarily.
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
ACCV
ACCVIFG
ACCVIE
S
FCTL1.1
Flash Module
Flash Module
IE1.5
Clear
Flash Module
PUC
RST/NMI
POR
PUC
VCC
KEYV
PUC
POR
System Reset
Generator
NMIFG
S
NMIRS
IFG1.4
Clear
NMIES TMSEL
NMI
WDTQn
EQU
PUC
POR
PUC
IE1.4
NMIIE
WDTIFG
S
IRQ
Clear
IFG1.0
POR
Clear
PUC
WDT
Counter
OSCFault
OFIFG
OFIF
S
IFG1.1
IRQA
TIMSEL
WDTIE
IE1.1
PUC
Clear
IE1.0
Clear
PUC
NMI_IRQA
Watchdog Timer Module
IRQA: Interrupt Request Accepted
Figure 2. Block Diagram of NMI Interrupt Sources
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled easily with
memory manipulation instructions.
oscillator and system clock
Three clocks are used in the system—the system (master) clock MCLK, the subsystem (master) clock SMCLK,
and the auxiliary clock ACLK:
Main system clock MCLK, used by the CPU and the system
Subsystem clock SMCLK, used by the peripheral modules
Auxiliary clock ACLK, originated by LFXT1CLK (crystal frequency) and used by the peripheral modules
After a POR, the DCOCLK is used by default, the DCOR bit is reset, and the DCO is set to the nominal initial
frequency. Additionally, if LFXT1CLK fails as the source for MCLK, the DCOCLK is automatically selected to
ensure fail-safe operation.
SMCLK can be generated from LFXT1CLK or DCOCLK. ACLK is always generated from LFXT1CLK.
The crystal oscillator can be defined to operate with watch crystals (32768 Hz) or with higher-frequency ceramic
resonators or crystals. The crystal or ceramic resonator is connected across two terminals. No external
components are required for watch-crystal operation. If the high frequency XT1 mode is selected, external
capacitors from XIN to VSS and XOUT to VSS are required as specified by the crystal manufacturer.
The LFXT1 oscillator starts after applying VCC. If the OscOff bit is set to 1, the oscillator stops when it is not
used for MCLK. The clock signals ACLK and SMCLK may be used externally via port pins.
Differentapplicationrequirementsandsystemconditionsdictatedifferentsystemclockrequirements, including:
High frequency for quick reaction to system hardware requests or events
Low frequency to minimize current consumption, EMI, etc.
Stable peripheral clock for timer applications, such as real-time clock (RTC)
Start-stop operation to be enabled with minimum delay
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
oscillator and system clock (continued)
DIVA
2
LFXT1CLK
ACLK
/1, /2, /4, /8
ACLKGEN
Auxiliary Clock
O
Off
XTS
SC
XIN
SELM
DIVM
CPUOff
LFXT1 OSCILLATOR
2
2
3
2
0,1
/1, /2, /4, /8, Off
MCLKGEN
MCLK
XOUT
Main System Clock
DCOCLK
V
V
CC
CC
R
SCG0
DCO
3
MOD
sel
SELS
DIVS
2
SCG1
5
0
Digital Controlled Oscillator (DCO)
0
DC
Generator
+
/1, /2, /4, /8, Off
SMCLKGEN
SMCLK
Modulator (MOD)
Subsystem Clock
1
1
P2.5/Rosc
DCGEN
DCOR
DCOMOD
The DCO-Generator is connected to pin P2.5/Rosc if DCOR control bit is set.
The port pin P2.5/Rosc is selected if DCOR control bit is reset (initial state).
P2.5
Figure 3. Clock Signals
Two clock sources, LFXT1CLK and DCOCLK, can be used to drive the MSP430 system. The LFXT1CLK is
generated from the LFXT1 crystal oscillator. The LFXT1 crystal oscillator can operate in three modes—low
frequency (LF), moderate frequency (XT1), and external input mode. The LFXT1 crystal oscillator may be
switched off when it is not in use.
DCOCLK is generated from the DCO. The nominal DCO frequency is defined by the dc generator and can be
set by one external resistor, or can be set to one of eight values with integrated resistors. Additional adjustments
and modulations of DCOCLK are possible by software manipulation of registers in the DCO module. DCOCLK
is stopped automatically when it is not used by the CPU or peripheral modules. The dc generator can be shut
down with the SCG0 bit to realize additional power savings when DCOCLK is not in use.
NOTE:
The system clock generator always starts with the DCOCLK selected for MCLK (CPU clock) to
ensure proper start of program execution. The software defines the final system clock generation
through control bit manipulation.
digital I/O
There are two eight-bit I/O ports, port P1 and port P2 – implemented (11x1 parts only have six port P2 I/O signals
available on external pins). Both ports, P1 and P2, have seven control registers to give maximum flexibility of
digital input/output to the application:
•
•
•
All individual I/O bits are programmable independently.
Any combination of input, output, and interrupt conditions is possible.
Interrupt processing of external events is fully implemented for all eight bits of port P1 and for six bits of
port P2.
•
Read/write access to all registers with all instructions
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
digital I/O (continued)
The seven registers are:
•
•
•
•
•
•
•
Input register
8 bits at port P1/P2 contains information at the pins
8 bits at port P1/P2 contains output information
8 bits at port P1/P2 controls direction
Output register
Direction register
Interrupt edge select
Interrupt flags
8 bits at port P1/P2 input signal change necessary for interrupt
8 bits at port P1/P2 indicates if interrupt(s) are pending
8 bits at port P1/P2 contains interrupt enable bits
Interrupt enable
Selection (Port or Mod.) 8 bits at port P1/P2 determines if pin(s) have port or module function
All these registers contain eight bits. Two interrupt vectors are implemented: one commonly used for any
interrupt event on ports P1.0 to P1.7, and one commonly used for any interrupt event on ports P2.0 to P2.7.
NOTE:
Six bits of port P2, P2.0 to P2.5, are available on external pins – but all control and data bits for port
P2 are implemented.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem has occurred. If the selected time interval expires, a system reset is generated. If this
watchdog function is not needed in an application, the module can work as an interval timer, which generates
an interrupt after the selected time interval.
The watchdog timer counter (WDTCNT) is a 16-bit up-counter which is not directly accessible by software. The
WDTCNT is controlled through the watchdog timer control register (WDTCTL), which is a 16-bit read/write
register. Writing to WDTCTL is, in both operating modes (watchdog or timer), only possible by using the correct
password in the high-byte. The low-byte stores data written to the WDTCTL. The high-byte must be the
password 05Ah. If any value other than 05Ah is written to the high-byte of the WDTCTL, a system reset PUC
is generated. When the password is read, its value is 069h. This minimizes accidental write operations to the
WDTCTL register. In addition to the watchdog timer control bits, there are two bits included in the WDTCTL
register that configure the NMI pin.
Timer_A (Three capture/compare registers)
The Timer_A module on 11x1 devices offers one sixteen bit counter and three capture/compare registers. The
timer clock source can be selected to come from two external sources TACLK (SSEL=0) or INCLK (SSEL=3),
or from two internal sources, the ACLK (SSEL=1) or SMCLK (SSEL=2). The clock source can be divided by
one, two, four, or eight. The timer can be fully controlled (in word mode) since it can be halted, read, and written.
It can be stopped, run continuously, counted up or up/down, using one compare block to determine the period.
The three capture/compare blocks are configured by the application to run in capture or compare mode.
The capture mode is primarily used to measure external or internal events using any combination of positive,
negative, or both edges of the signal. Capture mode can be started and stopped by software. Three different
external events TA0, TA1, and TA2 can be selected. At capture/compare register CCR2 the ACLK is the capture
signal if CCI2B is selected. Software capture is chosen if CCISx=2 or CCISx=3 (see Figure 4).
The compare mode is primarily used to generate timings for the software or application hardware, or to generate
pulse-width modulated output signals for various purposes like D/A conversion functions or motor control. An
individual output module is assigned to each of the three capture/compare registers. The output modules can
run independently of the compare function, or can be triggered in several ways.
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
Timer_A (3 capture/compare registers) (continued)
Data
16-Bit Timer
32 kHz to 8 MHz
Timer Clock
SSEL1 SSEL0
P1.0
0
1
2
3
0
15
TACLK
16-Bit Timer
CLK
Input
Divider
Mode
Control
ACLK
Equ0
SMCLK
RC
P2.1
INCLK
Set_TAIFG
Carry/Zero
ID1
ID0
MC1
MC0
POR/CLR
Timer Bus
Capture
Capture/Compare Register CCR0
0
0
15
CCIS01 CCIS00
0
OM02 OM01 OM00
Out 0
Capture/Compare
Register CCR0
P1.1
P2.2
CCI0A
P1.1
P1.5
1
2
3
CCI0B
GND
Capture
Mode
15
Output Unit 0
Comparator 0
V
CC
EQU0
CCI0 CCM01 CCM00
Capture/Compare Register CCR1
0
0
15
15
CCIS11 CCIS10
0
OM12 OM11 OM10
Out 1
Capture
Capture/Compare
Register CCR1
P1.2
P1.2
CCI1A
CCI1B
GND
1
2
3
CAOUT
Capture
Mode
P1.6
P2.3
Output Unit 1
Comparator 1
V
CC
EQU1
CCI1 CCM11 CCM10
Capture/Compare Register CCR2
0
0
15
15
CCIS21 CCIS20
0
OM22 OM21 OM20
Out 2
Capture
Capture/Compare
Register CCR2
P1.3
P1.3
CCI2A
CCI2B
GND
1
2
3
ACLK
Capture
Mode
P1.7
P2.4
Output Unit 2
Comparator 2
V
CC
EQU2
CCI2 CCM21 CCM20
Figure 4. Timer_A, MSP430x11x1 Configuration
Two interrupt vectors are used by the Timer_A module. One individual vector is assigned to capture/compare
block CCR0, and one common interrupt vector is implemented for the timer and the other two capture/compare
blocks. The three interrupt events using the same vector are identified by an individual interrupt vector word.
The interrupt vector word is used to add an offset to the program counter to continue the interrupt handler
software at the corresponding program location. This simplifies the interrupt handler and gives each interrupt
event the same overhead of 5 cycles in the interrupt handler.
UART
Serial communication is implemented by using software and one capture/compare block. The hardware
supports the output of the serial-data stream, bit by bit, with the timing determined by the comparator/timer. The
data input uses the capture feature. The capture flag finds the start of a character, while the compare feature
latches the input-data stream, bit by bit. The software/hardware interface connects the mixed-signal controller
to external devices, systems, or networks.
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
Comparator_A
The primary function of the comparator module is to support precision A/D slope conversion applications,
battery voltage supervision, and observation of external analog signals. The comparator is connected to port
pins P2.3/CA0 and to P2.4/CA1. It is controlled via twelve control bits in registers CACTL1 and CACTL2.
0 V
V
CC
0
1
CAF
P2CA0
CAEX
CAON
0
CA0
0
1
Low Pass Filter
CCI1B
P2.3/
CA0/
TA1
1
0
1
0
1
+
_
0
1
CA1
0
1
CAOUT
P2.4/
CA1/
TA2
0 V
Set CAIFG
Flag
0 V
V
0 V
τ ≈ 2.0 µs
CC
P2CA1
0
1
CAON
0
P2.2/
CAOUT/TA0
3
2
1
CAREF
0
2
1
3
CARSEL
0.5 x V
CC
1
0
0.25 x V
CC
V
CAREF
0 V
0 V
Figure 5. Block Diagram of Comparator_A
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MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
Comparator_A (continued)
The control bits are:
CAOUT,
CAF,
05Ah, bit0,
05Ah, bit1,
05Ah, bit2,
Comparator output
The comparator output is transparent or fed through a small filter
CA0,
0: Pin P2.3/CA0/TA1 is not connected to Comparator_A.
1: Pin P2.3/CA0/TA1 is connected to Comparator_A.
CA1,
05Ah, bit3,
05Ah, bit4,
0: Pin P2.4/CA1/TA2 is not connected to Comparator_A.
1: Pin P2.4/CA1/TA2 is connected to Comparator_A.
CACTL2.4
to
Bits are implemented but do not control any hardware in this device.
CATCTL2.7 05Ah, bit7,
CAIFG,
CAIE,
059h, bit0,
059h, bit1,
059h, bit2,
Comparator_A interrupt flag
Comparator_A interrupt enable
CAIES,
Comparator_A interrupt edge select bit
0: The rising edge sets the Comparator_A interrupt flag CAIFG
1: The falling edge set the Comparator_A interrupt flag CAIFG
CAON,
059h, bit3,
The comparator is switched on.
CAREF,
059h, bit4,5, Comparator_A reference
0: Internal reference is switched off, an external reference can be applied.
1: 0.25 × VCC reference selected.
2: 0.50 × VCC reference selected.
3: A diode reference selected.
CARSEL,
CAEX,
059h, bit6,
059h, bit7,
An internal reference V
signal path CA0 or CA1. The signal V
source if the value of CAREF control bits is 1, 2, or 3.
, selected by CAREF bits, can be applied to
CAREF
is only driven by a voltage
CAREF
The comparator inputs are exchanged, used to measure and compensate
the offset of the comparator.
Eight additional bits are implemented into the Comparator_A module and enable the SW to switch off the input
buffer of port P2. A CMOS input buffer would dissipate supply current when the input is not near VSS or VCC.
Comparator_A port disable control bits CAPD0 to CAPD7 are initially reset, and the port input buffer is active.
The port input buffer is disabled if the appropriate control bit is set.
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
Comparator_A (continued)
7
0
CACTL1
059h
CA
RSEL
CA
REF1
CA
REF0
CAEX
rw-(0)
7
CAON
rw-(0)
CAIES
rw-(0)
CAIE
CAIFG
rw-(0)
0
rw-(0)
rw-(0)
rw-(0)
rw-(0)
CACTL2
05Ah
CACTL CACTL CACTL CACTL
CA1
CA0
CAF
CAOUT
r-(0)
2.7
2.6
2.5
2.4
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
7
0
CAPD
05Bh
CAPD7 CAPD6 CAPD5 CAPD4 CAPD3 CAPD2 CAPD1 CAPD0
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
NOTE:
Ensure that the comparator input terminals are connected to signal, power, or ground level.
Otherwise, floating levels may cause unexpected interrupts and current consumption may be
increased.
slope a/d conversion
The Comparator_A is well suited for use in single or multiple-slope conversions. The internal-reference levels
may be used to set a reference during timing measurement of charge or discharge operations. They can also
be used externally to bias analog circuitry.
Voltage, current, and resistive or capacitive sensor measurements are basic functions. The sensors sense
physical conditions like temperature, pressure, acceleration, etc.
24
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
peripheral file map
PERIPHERALS WITH WORD ACCESS
Timer_A
Reserved
Reserved
Reserved
Reserved
Capture/compare register
Capture/compare register
Capture/compare register
Timer_A register
Reserved
Reserved
Reserved
Reserved
Capture/compare control
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
017Eh
017Ch
017Ah
0178h
0176h
0174h
0172h
0170h
016Eh
016Ch
016Ah
0168h
0166h
0164h
0162h
0160h
012Eh
CCR2
CCR1
CCR0
TAR
CCTL2
CCTL1
CCTL0
TACTL
TAIV
Flash Memory
Watchdog
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
Watchdog/timer control
WDTCTL
0120h
PERIPHERALS WITH BYTE ACCESS
Comparator_A
System Clock
Port P2
Comparator_A port disable
Comparator_A control2
Comparator_A control1
CAPD
CACTL2
CACTL1
05Bh
05Ah
059h
Basic clock sys. control2
Basic clock sys. control1
DCO clock freq. control
BCSCTL2 058h
BCSCTL1 057h
DCOCTL
056h
Port P2 selection
P2SEL
P2IE
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
P2IES
P2IFG
P2DIR
P2OUT
P2IN
Port P1
Port P1 selection
P1SEL
P1IE
026h
025h
024h
023h
022h
021h
020h
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
P1IES
P1IFG
P1DIR
P1OUT
P1IN
Special Function
SFR interrupt flag2
SFR interrupt flag1
SFR interrupt enable2
SFR interrupt enable1
IFG2
IFG1
IE2
003h
002h
001h
000h
IE1
25
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
†
absolute maximum ratings
Voltage applied at V
Voltage applied at V
to V (MSP430C11x1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V
SS
CC
CC
to V (MSP430F11x1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.1 V
SS
Voltage applied to any pin (referenced to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V +0.3 V
SS
CC
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, T (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
Storage temperature, T (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to V
.
SS
recommended operating conditions
MIN
1.8
1.8
2.7
NOM
MAX UNITS
MSP430C11x1
MSP430F11x1
MSP430F11x1
3.6
V
3.6
Supply voltage during program execution, V
(see Note 5)
CC
Supply voltage during program/erase flash memory, V
CC
3.6
V
V
Supply voltage, V
0
SS
Operating free-air temperature range, T
MSP430x11x1
Watch crystal
Ceramic resonator
Crystal
–40
85
°C
Hz
A
LF mode selected, XTS=0
32768
LFXT1 crystal frequency,
(see Note 6)
450
8000
8000
f
XT1 mode selected, XTS=1
kHz
(LFXT1)
1000
V
= 1.8 V,
CC
MSP430x11x1
dc
dc
2
5
V
= 2.2 V,
CC
MSP430x11x1
Processor frequency f
(MCLK signal)
MHz
(system)
V
= 3.6 V,
CC
dc
8
476
3
MSP430x11x1
Flash timing generator frequency, f
(FTG)
MSP430F11x1
257
kHz
ms
V
= 2.7 V/3.6 V
CC
MSP430F11x1
Cumulative program time, segment write, t
(CPT)
(see Note 7)
Low-level input voltage (TCK, TMS, TDI, RST/NMI), V
(excluding XIN, XOUT)
IL
V
= 2.2 V/3 V
= 2.2 V/3 V
V
V
SS
+0.6
V
V
CC
CC
SS
High-level input voltage (TCK, TMS, TDI, RST/NMI), V
(excluding XIN, XOUT)
IH
V
0.8V
V
CC
CC
V
V
V
0.2×V
IL(XIN, XOUT)
SS
CC
Input levels at XIN, XOUT
V
CC
= 2.2 V/3 V
V
0.8×V
V
CC
IH(XIN, XOUT)
CC
NOTES: 5. The LFXT1 oscillator in LF-mode requires a resistor of 5.1 MΩ from XOUT to VSS when VCC <2.5 V.
The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 4 MHz at VCC ≥ 2.2 V.
The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 8 MHz at VCC ≥ 2.8 V.
6. The LFXT1 oscillator in LF-mode requires a watch crystal.
The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal.
7. The cumulative program time must not be exceeded during a segment-write operation.
26
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
recommended operating conditions (continued)
MSP430x11x1 Devices
9
8
7
6
5
4
3
2
8 MHz at
3.6 V
5 MHz at
2.2 V
2 MHz at
1.8 V
1
0
0
1
2
3
4
V
CC
– Supply Voltage – V
NOTE: Minimum processor frequency is defined by system clock. Flash
program or erase operations require a minimum V of 2.7 V.
CC
Figure 6. Frequency vs Supply Voltage
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current (into V ) excluding external current (f
= 1 MHz)
CC
(system)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
T
= –40°C +85°C,
V
V
= 2.2 V
= 3 V
160
240
200
300
A
CC
f
f
= f
= 1 MHz,
µA
(MCLK) (SMCLK)
= 32,768 Hz
(ACLK)
CC
C11x1
F11x1
V
V
= 2.2 V
= 3 V
1.3
2.5
2
T
= –40°C +85°C,
CC
A
µA
µA
µA
f
= f
= f
= 4096 Hz
= 4096 Hz
(MCLK) (SMCLK) (ACLK)
3.2
CC
I
Active mode
(AM)
T
= –40°C +85°C,
V
V
= 2.2 V
= 3 V
200
300
250
350
A
CC
f
= f
= 1 MHz,
MCLK (SMCLK)
= 32,768 Hz
CC
f(ACLK)
V
V
= 2.2 V
= 3 V
1.6
3
3
T
= –40°C +85°C,
CC
A
f
= f
= f
(MCLK) (SMCLK) (ACLK)
4.3
CC
T
= –40°C +85°C,
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.2 V
= 3 V
30
51
32
55
11
17
1.2
2
40
60
45
70
14
22
1.7
2.7
A
f
= 0, f
= 1 MHz,
C11x1
F11x1
(MCLK)
(SMCLK)
= 32,768 Hz
f(ACLK)
Low-power mode,
(LPM0)
I
µA
(CPUOff)
T
= –40°C +85°C,
= 2.2 V
= 3 V
A
f
= 0, f
= 32,768 Hz
= 1 MHz,
(MCLK)
(SMCLK)
f(ACLK)
T
= –40°C +85°C,
= 2.2 V
= 3 V
A
f
= f
= 0 MHz,
I
I
Low-power mode, (LPM2)
µA
(MCLK) (SMCLK)
(LPM2)
= 32,768 Hz, SCG0 = 0
f(ACLK)
T
= –40°C +85°C,
= 2.2 V
= 3 V
A
Low-power mode, (LPM3)
(C11x1)
f
= f = 0 MHz,
= 32,768 Hz, SCG0 = 1
µA
(MCLK) (SMCLK)
(LPM3)
f(ACLK)
T
= –40°C
0.8
0.7
1.6
1.8
1.6
2.3
0.1
0.1
0.4
1.2
1
A
T
A
= 25°C
= 85°C
= –40°C
= 25°C
= 85°C
= –40°C
= 25°C
= 85°C
V
= 2.2 V
µA
µA
µA
µA
CC
CC
T
A
2.3
2.2
1.9
3.4
0.5
0.5
0.8
Low-power mode, (LPM3)
(F11x1)
I
(LPM3)
T
A
T
A
V
= 3 V
T
A
T
A
f
f
= 0 MHz,
= 0 MHz,
= 0 Hz, SCG0 = 1
(MCLK)
(SMCLK)
Low-power mode, (LPM4)
(C11x1)
I
I
T
A
V
V
= 2.2 V/3 V
= 2.2 V/3 V
(LPM4)
CC
CC
f(ACLK)
T
A
T
A
= –40°C
= 25°C
= 85°C
0.1
0.1
0.8
0.5
0.5
1.9
Low-power mode, (LPM4)
T
A
(LPM4)
T
A
NOTE: All inputs are tied to 0 V or V . Outputs do not source or sink any current.
CC
current consumption of active mode versus system frequency, C version, F version
= I × f [MHz]
I
AM
AM[1 MHz]
system
current consumption of active mode versus supply voltage, C version
= I + 105 µA/V × (V –3 V)
I
AM
AM[3 V]
CC
current consumption of active mode versus supply voltage, F version
= I + 120 µA/V × (V –3 V)
I
AM
AM[3 V]
CC
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
Schmitt-trigger inputs Port P1 to Port P2; P1.0 to P1.7, P2.0 to P2.5
PARAMETER
TEST CONDITIONS
MIN
1.1
1.5
0.4
.90
0.3
0.5
TYP
MAX
1.3
1.8
0.9
1.2
1
UNIT
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.2 V
= 3 V
V
IT+
V
IT–
V
hys
Positive-going input threshold voltage
V
= 2.2 V
= 3 V
Negative-going input threshold voltage
V
V
= 2.2 V
= 3 V
Input voltage hysteresis, (V
– V
)
IT–
IT+
1.4
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs Port 1 to P2; P1.0 to P1.7, P2.0 to P2.5
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
I
I
I
I
I
I
I
I
I
I
I
= –1.5 mA
= –6 mA
= –1.5 mA
= –6 mA
= –1 mA
= –3.4 mA
= –1 mA
= –3.4 mA
= 1.5 mA
= 6 mA
See Note 8
See Note 9
See Note 8
See Note 9
See Note 10
See Note 10
See Note 10
See Note 10
See Note 8
See Note 9
See Note 8
See Note 9
V
–0.25
V
V
V
V
V
V
V
V
(OHmax)
(OHmax)
(OHmax)
(OHmax)
(OHmax)
(OHmax)
(OHmax)
(OHmax)
(OLmax)
(OLmax)
(OLmax)
(OLmax)
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.2 V
= 3 V
High-level output voltage
Port 1 and Port 2 (C11x1)
Port 1 (F11x1)
V
–0.6
CC
–0.25
V
OH
V
OH
V
OL
V
V
CC
V
–0.6
CC
–0.25
V
CC
= 2.2 V
= 3 V
V
–0.6
CC
–0.25
High-level output voltage
Port 2 (F11x1)
V
V
V
CC
V
–0.6
CC
V
V
+0.25
SS
SS
SS
SS
SS
= 2.2 V
= 3 V
Low-level output voltage
Port 1 and Port 2 (C11x1,
F11x1)
V
V
V
V
+0.6
SS
= 1.5 mA
= 6 mA
V
SS
+0.25
V
+0.6
SS
NOTES: 8. The maximum total current, I
drop specified.
and I
, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage
OHmax
OLmax
9. Themaximum total current, I
drop specified.
and I
, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
OHmax
OLmax
10. One output loaded at a time.
leakage current
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Port P1: P1.x, 0 ≤ ×≤7
(see Notes 11, 12)
V
CC
= 2.2 V/3 V,
±50
I
High-impedance leakage current
nA
lkg(Px.x)
Port P2: P2.x, 0 ≤ ×≤5
(see Notes 11, 12)
V
CC
= 2.2 V/3 V,
±50
NOTES: 11. The leakage current is measured with V
SS
or V
applied to the corresponding pin(s), unless otherwise noted.
CC
12. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional
pullup or pulldown resistor.
29
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
optional resistors, individually programmable with ROM code (see Note 13)
PARAMETER
TEST CONDITIONS
MIN
2.5
3.8
7.6
11.5
23
TYP
5
MAX
10
UNIT
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
R
R
R
R
R
R
R
R
R
R
(opt1)
(opt2)
(opt3)
(opt4)
(opt5)
(opt6)
(opt7)
(opt8)
(opt9)
(opt10)
7.7
15
15
31
23
46
45
90
Resistors, individually programmable with ROM code, all port pins,
values applicable for pulldown and pullup
V
CC
= 2.2 V/3 V
46
90
180
280
460
640
830
70
140
230
320
420
115
160
205
NOTE 13: Optional resistors R
for pulldown or pullup are not available in standard flash memory device MSP430F11x1.
optx
inputs Px.x, TAx
PARAMETER
TEST CONDITIONS
Port P1, P2: P1.x to P2.x,
External trigger signal for the interrupt flag,
(see Note 14)
VCC
2.2 V/3 V
2.2 V
MIN
1.5
62
TYP
MAX
UNIT
cycle
t
External interrupt timing
(int)
ns
cycle
ns
3 V
50
2.2 V/3 V
2.2 V
1.5
62
t
Timer_A, capture timing
TA0, TA1, TA2. (see Note 15)
(cap)
3 V
50
NOTES: 14. The external signal sets the interrupt flag every time the minimum t cycle and time parameters are met. It may be set even with
int
triggersignalsshorterthant .Boththecycleandtimingspecificationsmustbemettoensuretheflagisset.t ismeasuredinMCLK
int
int
cycles.
15. The external capture signal triggers the capture event every time when the minimum t
cycles and time parameters are met. A
cap
capturemay be triggered with capture signals even shorter than t
. Both the cycle and timing specifications must be met to ensure
a correct capture of the 16-bit timer value and to ensure the flag is set.
cap
internal signals TAx, SMCLK at Timer_A
PARAMETER
Input frequency
Timer_A clock frequency
TEST CONDITIONS
Internal TA0, TA1, TA2, t = t
L
VCC
2.2 V
MIN
TYP
MAX
8
UNIT
f
f
MHz
(IN)
H
3 V
10
Internally, SMCLK signal applied
2.2 V/3 V
dc
f
System
(TAint)
30
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs P1.x, P2.x, TAx
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
f
f
P2.0/ACLK,
C
= 20 pF
2.2 V/3 V
f
f
(P20)
L
L
System
Output frequency
MHz
TA0, TA1, TA2,
Internal clock source, SMCLK signal applied (see Note 16)
C
= 20 pF
2.2 V/3 V
2.2 V/3 V
dc
(TAx)
System
f
= f
= f
40%
35%
60%
65%
SMCLK LFXT1 XT1
f
= f
= f
= f
SMCLK
SMCLK
LFXT1 LF
P1.4/SMCLK,
= 20 pF
50%–
15 ns
50%+
15 ns
C
f
f
50%
50%
L
LFXT1/n
DCOCLK
50%–
15 ns
50%+
15 ns
t
t
Duty cycle of O/P
frequency
(Xdc)
= f
2.2 V/3 V
2.2 V/3 V
SMCLK
f
= f
= f
40%
30%
60%
70%
P20 LFXT1 XT1
P2.0/ACLK,
= 20 pF
f
= f
= f
= f
P20
LFXT1 LF
C
L
f
50%
0
P20
LFXT1/n
TA0, TA1, TA2,
C
= 20 pF, Duty cycle = 50% 2.2 V/3 V
±50
ns
(TAdc)
L
NOTE 16: The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies.
Comparator_A (see Note 17)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
V
V
= 2.2 V
= 3 V
25
45
40
µA
60
CC
I
I
CAON=1, CARSEL=0, CAREF=0
(DD)
CC
CAON=1, CARSEL=0,
CAREF=1/2/3, No load at
P2.3/CA0/TA1 and P2.4/CA1/TA2
V
= 2.2 V
= 3 V
30
45
50
µA
71
CC
CC
(Refladder/
RefDiode)
V
Common-mode input
voltage
V
CAON =1
V
= 2.2 V/3 V
= 2.2 V/3 V
0
V –1
CC
V
(IC)
CC
CC
PCA0=1, CARSEL=1, CAREF=1,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2, See Figure 5
Voltage @ 0.25 V
CC
node
V
(Ref025)
V
0.23
0.24
0.48
0.25
0.5
See Figure 5
V
CC
PCA0=1, CARSEL=1, CAREF=2,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2, See Figure 5
Voltage @ 0.5 V
node
V
(Ref050)
See Figure 5
CC
V
CC
= 2.2 V/3 V
0.47
V
CC
PCA0=1, CARSEL=1, CAREF=3,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
V
V
= 2.2 V
= 3 V
430
450
550
565
645
660
CC
V
mV
(RefVT)
CC
V
V
Offset voltage
See Note 18
CAON=1
V
V
V
V
V
V
= 2.2 V/3 V
= 2.2 V/3 V
= 2.2 V
= 3 V
–30
0
30
1.4
300
200
3.4
2.6
mV
mV
(offset)
CC
CC
CC
CC
CC
CC
Input hysteresis
0.7
210
150
1.9
hys
160
90
T
= 25°C, Overdrive 10 mV, With-
A
ns
out filter:
CAF=0
t
(response LH)
(response HL)
= 2.2 V
= 3 V
1.6
1.1
T
filter:
= 25°C, Overdrive 10 mV, With
A
µs
CAF=1
1.5
T
A
= 25°C,
V
CC
V
CC
= 2.2 V
= 3 V
160
90
210
150
300
200
Overdrive 10 mV, without filter:
CAF=0
ns
t
V
V
= 2.2 V
= 3 V
1.6
1.1
1.9
1.5
3.4
2.6
T
= 25°C,
CC
A
µs
Overdrive 10 mV, with filter: CAF=1
CC
NOTES: 17. The leakage current for the Comparator_A terminals is identical to I
specification.
lkg(Px.x)
18. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
31
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
700
Mean –6 Sigma
650
600
550
500
450
Mean –4 Sigma
Mean
Mean +4 Sigma
Mean +6 Sigma
–45
–25
–5
15
35
55
75
95
Temperature [°C]
Figure 7. V
vs Temperature, V
= 3 V, C1121
(RefVT)
CC
700
650
600
550
500
450
Mean –6 Sigma
Mean –4 Sigma
Mean
Mean +4 Sigma
Mean +6 Sigma
–45
–25
–5
15
35
55
75
95
Temperature [°C]
Figure 8. V
vs Temperature, V
= 2.2 V, C1121
(RefVT)
CC
32
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
0 V
V
CC
0
1
CAF
CAON
To Internal
Modules
Low Pass Filter
0
1
0
1
+
_
V+
V–
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 µs
Figure 9. Block Diagram of Comparator_A Module
V
CAOUT
Overdrive
V–
400 mV
V+
t
(response)
Figure 10. Overdrive Definition
PUC/POR
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
250
1.8
UNIT
t
150
µs
(POR_delay)
T
= –40°C
= 25°C
= 85°C
1.4
1.1
0.8
0
V
V
A
V
POR
T
A
1.5
(POR)
V
CC
= 2.2 V/3 V
T
A
1.2
V
V
(min)
0.4
V
t
PUC/POR
Reset is accepted internally
2
µs
(reset)
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
V
VCC
V
(POR)
No POR
POR
POR
V
(min)
t
Figure 11. Power-On Reset (POR) vs Supply Voltage
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.8
1.4
1.5
Max
1.2
0.8
Min
1.1
25°C
–40
–20
0
20
40
60
80
Temperature [°C]
Figure 12. V
vs Temperature
(POR)
crystal oscillator,LFXT1
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
XTS=0; LF mode selected.
= 2.2 V / 3 V
12
V
CC
XTS=1; XT1 mode selected.
= 2.2 V / 3 V (Note 19)
C
C
Input capacitance
pF
(XIN)
2
12
2
V
CC
XTS=0; LF mode selected.
= 2.2 V / 3 V
V
CC
XTS=1; XT1 mode selected.
= 2.2 V / 3 V (Note 19)
Output capacitance
pF
(XOUT)
V
CC
NOTE 19: Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
RAM
PARAMETER
MIN NOM
MAX
UNIT
V
CPU halted (see Note 20)
1.6
V
(RAMh)
NOTE 20: This parameter defines the minimum supply voltage V
when the data in the program memory RAM remains unchanged. No program
CC
execution should happen during this supply voltage condition.
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
DCO
PARAMETER
TEST CONDITIONS
MIN
0.08
0.08
0.14
0.14
0.22
0.22
0.37
0.37
0.61
0.61
TYP
0.12
0.13
0.19
0.18
0.30
0.28
0.49
0.47
0.77
0.75
MAX
0.15
0.16
0.23
0.22
0.36
0.34
0.59
0.56
0.93
0.9
UNIT
V
V
V
V
V
V
V
V
V
V
= 2.2 V
= 3 V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
f
f
f
f
f
f
f
f
f
f
R
R
R
R
R
R
R
R
R
R
= 0, DCO = 3, MOD = 0, DCOR = 0,
= 1, DCO = 3, MOD = 0, DCOR = 0,
= 2, DCO = 3, MOD = 0, DCOR = 0,
= 3, DCO = 3, MOD = 0, DCOR = 0,
= 4, DCO = 3, MOD = 0, DCOR = 0,
= 5, DCO = 3, MOD = 0, DCOR = 0,
= 6, DCO = 3, MOD = 0, DCOR = 0,
= 7, DCO = 3, MOD = 0, DCOR = 0,
= 7, DCO = 7, MOD = 0, DCOR = 0,
= 4, DCO = 7, MOD = 0, DCOR = 0,
T
A
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
MHz
(DCO03)
(DCO13)
(DCO23)
(DCO33)
(DCO43)
(DCO53)
(DCO63)
(DCO73)
(DCO77)
(DCO47)
sel
sel
sel
sel
sel
sel
sel
sel
sel
sel
= 2.2 V
= 3 V
T
A
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ratio
= 2.2 V
= 3 V
T
A
= 2.2 V
= 3 V
T
A
= 2.2 V
= 3 V
T
A
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.2 V
= 3 V
1
1
1.2
1.3
1.9
2
1.5
1.5
T
A
= 2.2 V
= 3 V
1.6
1.69
2.4
2.7
4
2.2
T
A
2.29
3.4
= 2.2 V
= 3 V
2.9
3.2
4.5
4.9
T
A
3.65
4.9
= 2.2 V
= 3 V
T
A
4.4
5.4
F
F
F
DCO40
x1.7
DCO40
x2.1
DCO40
x2.5
T
A
V
CC
= 2.2 V/3 V
S
S
S
S
= f
/f
Rsel+1 Rsel
V
CC
V
CC
V
CC
V
CC
= 2.2 V/3 V
= 2.2 V/3 V
= 2.2 V
1.35
1.07
1.65
1.12
2
1.16
(Rsel)
R
= f /f
(DCO)
DCO DCO+1 DCO
–0.31
–0.33
–0.36
–0.38
–0.40
–0.43
Temperature drift, R
(see Note 21)
= 4, DCO = 3, MOD = 0
sel
D
D
%/°C
t
= 3 V
Drift with V
CC
(see Note 21)
variation, R = 4, DCO = 3, MOD = 0
sel
V
CC
= 2.2 V/3 V
0
5
10
%/V
V
NOTE 21: These parameters are not production tested.
Max
f
f
(DCOx7)
(DCOx0)
Min
Max
Min
0
1
2
3
4
5
6
7
2.2 V
3 V
V
CC
DCO Steps
Figure 13. DCO Characteristics
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
principle characteristics of the DCO
Individual devices have a minimum and maximum operation frequency. The specified parameters for
f
to f
are valid for all devices.
DCOx0
DCOx7
The DCO control bits DCO0, DCO1 and DCO2 have a step size as defined in parameter S
.
DCO
ThemodulationcontrolbitsMOD0toMOD4selecthowoftenf
isusedwithintheperiodof32DCOCLK
MOD/32
DCO+1
cycles. f
is used for the remaining cycles. The frequency is an average = f
× (2
).
DCO
DCO
The ranges selected by R
to R
, R
to R
, and R
to R
are overlapping.
Sel7
Sel4
Sel5 Sel5
Sel6
Sel6
wake-up from lower power modes (LPMx)
PARAMETER
TEST CONDITIONS
= 2.2 V/3 V
MIN
TYP
100
100
MAX
UNIT
t
t
V
V
(LPM0)
CC
ns
= 2.2 V/3 V
(LPM2)
CC
f
f
f
= 1 MHz,
= 2 MHz,
= 3 MHz,
V
V
V
= 2.2 V/3 V
= 2.2 V/3 V
= 2.2 V/3 V
6
6
6
(MCLK)
(MCLK)
(MCLK)
CC
CC
CC
t
t
µs
(LPM3)
Delay time (see Note 22)
f
f
f
= 1 MHz,
= 2 MHz,
= 3 MHz,
V
CC
V
CC
V
CC
= 2.2 V/3 V
= 2.2 V/3 V
= 2.2 V/3 V
6
6
6
(MCLK)
(MCLK)
(MCLK)
µs
(LPM4)
NOTE 22: Parameter applicable only if DCOCLK is used for MCLK.
JTAG/programming
PARAMETER
TEST CONDITIONS
TCK frequency, JTAG/test (see Note 25)
Fuse blow voltage, C versions (see Notes 23 and 24)
MIN
dc
TYP
MAX
5
UNIT
V
CC
V
CC
V
CC
= 2.2 V
= 3 V
f
MHz
(TCK)
dc
10
V
= 2.2 V/3 V
3.5
3.9
100
1
V
(FB)
(FB)
(FB)
I
t
Supply current on TDI during fuse blow (see Note 24) (C11x1)
Time to blow the fuse (see Note 24) (C11x1)
mA
ms
V
= 2.7 V/3.6 V,
CC
I
Current during program cycle (see Note 26)
3
3
5
5
mA
mA
(DD-PGM)
MSP430F11x1
V
CC
= 2.7 V/3.6 V,
I
Current during erase cycle (see Note 26)
Write/erase cycles
(DD-ERASE)
MSP430F11x1
MSP430F11x1
MSP430F11x1
4
5
10
10
t
(retention)
Data retention T = 25°C
100
Year
J
NOTES: 23. The power source to blow the fuse is applied to TDI pin.
24. Once the JTAG fuse is blown, no further access to the MSP430 JTAG/test feature is possible. The JTAG block is switched to bypass
mode.
25.
f
may be restricted to meet the timing requirements of the module selected.
(TCK)
26. Duration of the program/erase cycle is determined by f
applied to the flash timing controller. It can be calculated as follows:
(FTG)
t
t
t
t
t
= 35 x 1/f
(FTG)
(word write)
(segment write, byte 0)
(segment write, byte 1 – 63)
(mass erase)
(page erase)
= 30 × 1/f
(FTG)
= 20 × 1/f
(FTG)
(FTG)
= 5297 x 1/f
= 4819 x 1/f
(FTG)
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
APPLICATION INFORMATION
input/output schematic
Port P1, P1.0 to P1.3, input/output with Schmitt-trigger
V
CC
P1SEL.x
0
(See Note 27)
P1DIR.x
1
0
Direction Control
From Module
(See Note 28)
Pad Logic
P1.0 – P1.3
P1OUT.x
1
Module X OUT
(See Note 28)
(See Note 27)
P1IN.x
GND
EN
D
Module X IN
P1IRQ.x
P1IE.x
Interrupt
Edge
Select
EN
Q
P1IFG.x
Set
Interrupt
Flag
P1IES.x
P1SEL.x
NOTE: x = Bit/identifier, 0 to 3 for port P1
Direction
PnSel.x
PnDIR.x
control from
module
PnOUT.x
Module X OUT
VSS
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
†
P1Sel.0
P1Sel.1
P1Sel.2
P1Sel.3
P1DIR.0
P1DIR.1
P1DIR.2
P1DIR.3
P1DIR.0
P1DIR.1
P1DIR.2
P1DIR.3
P1OUT.0
P1OUT.1
P1OUT.2
P1OUT.3
P1IN.0
P1IN.1
P1IN.2
P1IN.3
TACLK
P1IE.0
P1IE.1
P1IE.2
P1IE.3
P1IFG.0
P1IFG.1
P1IFG.2
P1IFG.3
P1IES.0
P1IES.1
P1IES.2
P1IES.3
†
†
†
†
†
†
Out0 signal
Out1 signal
Out2 signal
CCI0A
CCI1A
CCI2A
†
Signal from or to Timer_A
NOTES: 27. Optional selection of pullup or pulldown resistors with ROM (masked) versions.
28. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
APPLICATION INFORMATION
Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features
V
CC
See Note 27
P1SEL.x
P1DIR.x
0
1
Direction Control
From Module
See Note 28
0
1
Pad Logic
P1OUT.x
P1.4–P1.7
Module X OUT
See Note 28
See Note 27
GND
TST
Bus Keeper
P1IN.x
EN
D
Module X IN
TEST
TST
Fuse
P1IRQ.x
P1IE.x
P1IFG.x
Interrupt
Edge
Select
60 kΩ
Typical
EN
Set
Q
GND
Fuse
Blow
Interrupt
Flag
Control By JTAG
P1IES.x
NOTE: Fuse not implemented
in F11x1
Control
P1SEL.x
P1.x
TDO
Controlled By JTAG
P1.7/TDI/TDO
P1.x
Controlled by JTAG
TDI
TST
TST
P1.6/TDI
P1.x
NOTE: The test pin should be protected from potential EMI
and ESD voltage spikes. This may require a smaller
external pulldown resistor in some applications.
TMS
TCK
P1.5/TMS
P1.x
x = Bit identifier, 4 to 7 for port P1
TST
During programming activity and during blowing
the fuse, the pin TDO/TDI is used to apply the test
input for JTAG circuitry.
P1.4/TCK
Direction
PnSel.x
PnDIR.x
control from
module
PnOUT.x
Module X OUT
SMCLK
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
P1Sel.4
P1Sel.5
P1Sel.6
P1Sel.7
P1DIR.4
P1DIR.5
P1DIR.6
P1DIR.7
P1DIR.4
P1DIR.5
P1DIR.6
P1DIR.7
P1OUT.4
P1OUT.5
P1OUT.6
P1OUT.7
P1IN.4
P1IN.5
P1IN.6
P1IN.7
unused
unused
unused
unused
P1IE.4
P1IE.5
P1IE.6
P1IE.7
P1IFG.4
P1IFG.5
P1IFG.6
P1IFG.7
P1IES.4
P1IES.5
P1IES.6
P1IES.7
†
†
†
Out0 signal
Out1 signal
Out2 signal
†
Signal from or to Timer_A
NOTES: 27. Optional selection of pullup or pulldown resistors with ROM (masked) versions.
28. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
APPLICATION INFORMATION
Port P2, P2.0 to P2.2, input/output with Schmitt-trigger
P2SEL.x
P2DIR.x
V
CC
0
1
0: Input
See Note 27
Direction Control
From Module
1: Output
See Note 28
Pad Logic
0
1
P2.0 – P2.2
P2OUT.x
Module X OUT
See Note 28
See Note 27
GND
Bus Keeper
P2IN.x
EN
D
Module X IN
CAPD.X
P2IRQ.x
P2IE.x
Interrupt
Edge
Select
EN
Q
P2IFG.x
Set
Interrupt
Flag
NOTE: x = Bit Identifier, 0 to 2 for port P2
Direction
P2IES.x
P2SEL.x
PnSel.x
PnDIR.x
control from
module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
unused
PnIE.x
PnIFG.x
PnIES.x
P2Sel.0
P2Sel.1
P2Sel.2
P2DIR.0
P2DIR.1
P2DIR.2
P2DIR.0
P2DIR.1
P2DIR.2
P2OUT.0
P2OUT.1
P2OUT.2
ACLK
VSS
P2IN.0
P2IN.1
P2IN.2
P2IE.0
P2IE.1
P2IE.2
P2IFG.0
P2IFG.1
P2IFG.2
P1IES.0
P1IES.1
P1IES.2
†
INCLK
CCI0B
†
CAOUT
†
Signal from or to Timer_A
NOTES: 27. Optional selection of pullup or pulldown resistors with ROM (masked) versions.
28. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
APPLICATION INFORMATION
Port P2, P2.3 to P2.4, input/output with Schmitt-trigger
P2SEL.3
V
CC
0
P2DIR.3
0: Input
1: Output
Pad Logic
See Note 27
See Note 28
1
Direction Control
From Module
0
1
P2.3
P2OUT.3
Module X
OUT
See Note 28
See Note 27
GND
P2IN.3
Bus Keeper
EN
D
Module X IN
P2IRQ.3
P2IE.3
Interrupt
Edge
Select
EN
Set
Q
CAPD.3
P2IFG.3
Comparator_A
CAREF P2CA CAEX
Interrupt
Flag
P2IES.3 P2SEL.3
CAF
+
_
CCI1B
0 V
P2SEL.4
P2IES.4
Interrupt
Flag
CAREF
Reference Block
CAPD.4
Interrupt
Edge
Select
Set
Q
P2IFG.4
EN
P2IRQ.4
Module X IN
P2IE.4
D
EN
Bus Keeper
V
P2IN.4
CC
See Note 27
See Note 28
Module X OUT
P2OUT.4
1
0
P2.4
Pad Logic
See Note 28
See Note 27
Direction Control
From Module
1: Output
0: Input
1
0
P2DIR.4
P2SEL.4
GND
APPLICATION INFORMATION
PnSel.x PnDIR.x
Direction
PnOUT.x
Module X OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
control from module
†
†
P2Sel.3 P2DIR.3
P2Sel.4 P2DIR.4
Signal from Timer_A
P2DIR.3
P2OUT.3
P2OUT.4
Out1 signal
P2IN.3
P2IN.4
unused
unused
P2IE.3 P2IFG.3
P2IE.4 P2IFG.4
P1IES.3
P1IES.4
P2DIR.4
Out2 signal
†
NOTES: 27. Optional selection of pullup or pulldown resistors with ROM (masked) versions.
28. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
Port P2, P2.5, input/output with Schmitt-trigger and R
function for the Basic Clock module
OSC
V
CC
P2SEL.5
0: Input
Pad Logic
0
1: Output
P2DIR.5
See Note 27
1
Direction Control
From Module
See Note 28
0
1
P2.5
P2OUT.5
Module X OUT
See Note 28
See Note 27
GND
Bus Keeper
P2IN.5
EN
D
Module X IN
P2IRQ.5
Internal to
Basic Clock
Module
P2IE.5
Interrupt
Edge
Select
1
0
V
CC
EN
Q
P2IFG.5
Set
Interrupt
Flag
P2IES.5
DC
Generator
DCOR
P2SEL.5
CAPD.5
NOTE: DCOR: Control bit from Basic Clock Module if it is set, P2.5 Is disconnected from P2.5 pad
Direction
PnSel.x
P2Sel.5
PnDIR.x
P2DIR.5
control from
module
PnOUT.x
P2OUT.5
Module X OUT
VSS
PnIN.x
P2IN.5
Module X IN
unused
PnIE.x
P2IE.5
PnIFG.x
P2IFG.5
PnIES.x
P2IES.5
P2DIR.5
NOTES: 27. Optional selection of pullup or pulldown resistors with ROM (masked) versions.
28. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
APPLICATION INFORMATION
Port P2, unbonded bits P2.6 and P2.7
P2SEL.x
P2DIR.x
0: Input
1: Output
0
1
Direction Control
From Module
0
1
P2OUT.x
Module X OUT
P2IN.x
Node Is Reset With PUC
Bus Keeper
EN
Module X IN
D
P2IRQ.x
P2IE.x
PUC
Interrupt
Edge
Select
EN
Set
Q
P2IFG.x
Interrupt
Flag
P2IES.x
P2SEL.x
NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins
Direction
P2Sel.x
P2DIR.x
control from
module
P2OUT.x
Module X OUT
P2IN.x
Module X IN
P2IE.x
P2IFG.x
P2IES.x
P2Sel.6
P2Sel.7
P2DIR.6
P2DIR.7
P2DIR.6
P2DIR.7
P2OUT.6
P2OUT.7
VSS
VSS
P2IN.6
P2IN.7
unused
unused
P2IE.6
P2IE.7
P2IFG.6
P2IFG.7
P2IES.6
P2IES.7
NOTE: A good use of the unbonded bits 6 and 7 of port P2 is to use the interrupt flags. The interrupt flags can not be influenced from any signal
other than from software. They work then as a soft interrupt.
JTAG fuse check mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of
the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current can flow from the TEST pin to ground if the fuse is not burned. Care must be taken to avoid accidentally
activating the fuse check mode and increasing overall system power consumption.
When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense
currents are terminated.
42
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
0.050 (1,27)
16
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°–8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
20
24
0.610
DIM
0.410
0.510
A MAX
(10,41) (12,95) (15,49)
0.400
0.500
0.600
A MIN
(10,16) (12,70) (15,24)
4040000/D 02/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
43
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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
44
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Copyright 2000, Texas Instruments Incorporated
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