Si4734/35-B20
BROADCAST AM/FM/SW/LW RADIO RECEIVER
Features
„ Worldwide FM band support
(64–108 MHz)
„ No manual alignment necessary
„ Adjustable channel filters
„ Worldwide AM band support
(520–1710 kHz)
„ EN55020 complaint
„ Programmable reference clock
„ Digital volume control
„ Adjustable soft mute control
„ RDS/RBDS processor (Si4735 only)
„ Optional digital audio out (Si4735 only)
„ 2-wire and 3-wire control interface
„ 2.7 to 5.5 V supply voltage
„ Wide range of ferrite loop sticks and air
loop antennas supported
„ 3 x 3 x 0.55 mm 20-pin QFN package
z Pb-free/RoHS compliant
„ SW band support (2.3–21.85 MHz)
„ LW band support (153–279 KHz)
„ Excellent real-world performance
„ Freq synthesizer with integrated VCO
„ Automatic frequency control (AFC)
„ Automatic gain control (AGC)
„ Integrated LDO regulator
„ Digital FM stereo decoder
„ Programmable de-emphasis
„ Adaptive noise suppression
„ AM/FM/SW/LW digital tuning
Ordering Information:
Pin Assignments
Si4734/35-GM
(Top View)
Applications
„
„
„
„
„
„
Table and portable radios
Stereos
Mini/micro systems
CD/DVD players
Portable media players
Boom boxes
„
„
„
„
„
Cellular handsets
Modules
Clock radios
Mini HiFi
Entertainment systems
20 19 18 17
NC
FMI
1
16
2
15 DOUT
14 LOUT
13 ROUT
12 GND
11 VDD
RFGND
AMI
3
4
5
GND
PAD
Description
RST
The Si4734/35 is the first digital CMOS AM/FM/SW/LW radio receiver IC that
integrates the complete tuner function from antenna input to audio output.
6
7
8
9
10
Functional Block Diagram
FM / SW
ANT
Si4734/35
Patents pending
Notes:
FMI
DOUT
RDS
(Si4735)
DIGITAL
AUDIO
(Si4735)
LNA
AGC
1. To ensure proper operation and
receiver performance, follow the
guidelines in “AN383: Antenna
Selection and Universal Layout
Guide.” Silicon Laboratories will
evaluate schematics and layouts for
qualified customers.
2. Place Si4734/35 as close as
possible to antenna jack and keep
the FMI and AMI traces as short as
possible.
DFS
GPO/DCLK
LOW-IF
DSP
ADC
ADC
DAC
DAC
ROUT
LOUT
AM / LW
ANT
AMI
LNA
AGC
RFGND
2.7 - 5.5 V
VDD
GND
CONTROL
INTERFACE
LDO
AFC
VIO
1.5-3.6V
Rev. 1.0 4/08
Copyright © 2008 by Silicon Laboratories
Si4734/35-B20
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Si4734/35-B20
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.4. AM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.5. SW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.6. LW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.7. Digital Audio Interface (Si4735 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.8. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.9. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.10. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.11. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.12. RDS/RBDS Processor (Si4735 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.13. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.14. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.15. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.16. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.17. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.18. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.19. Reset, Power Up, and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.20. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6. Pin Descriptions: Si4734/35-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
8. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8.1. Si4734/35 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
9. Package Outline: Si4734/35 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10. PCB Land Pattern: Si4734/35 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
11. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Rev. 1.0
3
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Si4734/35-B20
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol Test Condition
Min
2.7
1.5
10
Typ
—
Max
5.5
3.6
—
Unit
V
Supply Voltage
V
DD
Interface Supply Voltage
V
—
V
IO
DDRISE
Power Supply Powerup Rise Time
Interface Power Supply Powerup Rise Time
Ambient Temperature
V
—
µs
µs
°C
V
10
—
—
IORISE
T
–20
25
85
A
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at V = 3.3 V and 25 °C unless otherwise stated. Parameters are tested in production unless
DD
otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Supply Voltage
Symbol
Value
–0.5 to 5.8
–0.5 to 3.9
10
Unit
V
V
DD
Interface Supply Voltage
V
V
IO
IN
3
Input Current
I
mA
V
3
Input Voltage
V
T
–0.3 to (VIO + 0.3)
–40 to 95
–55 to 150
0.4
IN
Operating Temperature
Storage Temperature
°C
°C
OP
T
STG
4
RF Input Level
V
pK
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si4734/35 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV
HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. At RF input pins, FMI and AMI.
4
Rev. 1.0
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Si4734/35-B20
Table 3. DC Characteristics
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
FM Mode
Supply Current
Supply Current
I
I
I
—
—
—
—
19.2
19.8
19.9
18.0
22
23
mA
mA
mA
mA
FM
FM
FM
Low SNR level
RDS Supply Current
23
Supply Current
I
Digital Output Mode
20.5
FMD
AM/SW/LW Mode
Supply Current
I
Analog Output Mode
Digital Output Mode
—
—
17.3
15.5
20.5
20.5
mA
mA
AM
Supply Current
I
AMD
Supplies and Interface
Interface Supply Current
I
—
—
320
10
1
600
20
µA
µA
µA
V
IO
V
V
Powerdown Current
I
DDPD
DD
Powerdown Current
I
SCLK, RCLK inactive
—
10
IO
IOPD
High Level Input Voltage
V
0.7 x V
–0.3
–10
—
—
—
—
V
+ 0.3
IO
IH
IO
Low Level Input Voltage
V
0.3 x V
10
V
IL
IO
High Level Input Current
I
V
= V = 3.6 V
µA
µA
IH
IN
IO
Low Level Input Current
I
V
= 0 V,
IN
–10
10
IL
V
= 3.6 V
IO
High Level Output Voltage
V
I
= 500 µA
= –500 µA
0.8 x V
—
—
—
—
V
V
OH
OUT
IO
Low Level Output Voltage
V
I
0.2 x V
OL
OUT
IO
Notes:
1. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions.
2. Specifications are guaranteed by characterization.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, and DFS.
4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.
Rev. 1.0
5
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Si4734/35-B20
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Min
100
30
Typ
—
Max
—
Unit
µs
RST Pulse Width and GPO1, GPO2/INT Setup to RST↑
GPO1, GPO2/INT Hold from RST↑
Important Notes:
t
SRST
t
—
—
ns
HRST
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the first start condition.
3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum t
is only 30 ns. If GPO1 or GPO2 is hi-Z, then
SRST
minimum t
is 100 µs, to provide time for on-chip 1 MΩ devices (active while RST is low) to pull GPO1 high and
SRST
GPO2 low.
tHRST
tSRST
70%
30%
RST
70%
30%
GPO1
70%
30%
GPO2/
INT
Figure 1. Reset Timing Parameters for Busmode Select
6
Rev. 1.0
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Si4734/35-B20
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol Test Condition
Min
0
Typ
—
Max
400
—
Unit
kHz
µs
SCLK Frequency
SCLK Low Time
SCLK High Time
f
SCL
t
1.3
0.6
0.6
—
LOW
t
—
—
µs
HIGH
SCLK Input to SDIO ↓ Setup
t
t
—
—
µs
SU:STA
(START)
SCLK Input to SDIO ↓ Hold (START)
0.6
100
0
—
—
—
—
—
—
—
—
µs
ns
ns
µs
µs
ns
HD:STA
SU:DAT
SDIO Input to SCLK ↑ Setup
t
t
SDIO Input to SCLK ↓ Hold
900
—
HD:DAT
SU:STO
SCLK input to SDIO ↑ Setup (STOP)
STOP to START Time
t
0.6
1.3
t
—
BUF
SDIO Output Fall Time
t
250
f:OUT
Cb
----------
1pF
20 + 0.1
SDIO Input, SCLK Rise/Fall Time
t
t
—
300
ns
f:IN
Cb
r:IN
----------
1pF
20 + 0.1
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
Notes:
C
—
—
—
—
50
50
pF
ns
b
t
SP
1. When V = 0 V, SCLK and SDIO are low impedance.
IO
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high)
does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the first start condition.
4. The Si4734/35 delays SDIO by a minimum of 300 ns from the V threshold of SCLK to comply with the minimum
IH
t
specification.
HD:DAT
5. The maximum t
has only to be met when f
= 400 kHz. At frequencies below 400 KHz, t
may be violated
HD:DAT
HD:DAT
SCL
as long as all other timing parameters are met.
Rev. 1.0
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Si4734/35-B20
tSU:STA tHD:STA
tLOW
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
70%
SCLK
30%
70%
SDIO
30%
tf:IN,
tf:OUT
START
tHD:DAT tSU:DAT
tr:IN
STOP
START
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
SDIO
A6-A0,
R/W
D7-D0
D7-D0
START
ADDRESS + R/W
ACK
DATA
ACK
DATA
ACK
STOP
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
8
Rev. 1.0
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Si4734/35-B20
Table 6. 3-Wire Control Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
SCLK Frequency
SCLK High Time
SCLK Low Time
f
CLK
t
25
25
20
10
10
2
HIGH
t
—
ns
LOW
SDIO Input, SEN to SCLK↑ Setup
SDIO Input to SCLK↑ Hold
t
—
ns
S
t
—
ns
HSDIO
SEN Input to SCLK↓ Hold
t
—
ns
HSEN
SCLK↑ to SDIO Output Valid
SCLK↑ to SDIO Output High Z
SCLK, SEN, SDIO, Rise/Fall time
t
Read
Read
25
25
10
ns
CDV
t
2
ns
CDZ
t , t
—
ns
R
F
Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
70%
SCLK
30%
tR
tF
tHSDIO
tHIGH
tLOW
tHSEN
tS
70%
30%
tS
SEN
A6-A5,
R/W,
A4-A1
70%
30%
A7
A0
D15
D14-D1
D0
SDIO
Address In
Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters
70%
30%
SCLK
SEN
tHSDIO
tCDV
tHSEN
tS
tCDZ
70%
30%
tS
70%
30%
A6-A5,
R/W,
A4-A1
A7
A0
D15
D14-D1
D0
SDIO
½ Cycle Bus
Turnaround
Address In
Data Out
Figure 5. 3-Wire Control Interface Read Timing Parameters
Rev. 1.0
9
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Si4734/35-B20
Table 7. SPI Control Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
SCLK Frequency
SCLK High Time
SCLK Low Time
f
CLK
t
25
25
15
10
5
HIGH
t
—
ns
LOW
SDIO Input, SEN to SCLK↑ Setup
SDIO Input to SCLK↑ Hold
t
—
ns
S
t
—
ns
HSDIO
SEN Input to SCLK↓ Hold
t
—
ns
HSEN
SCLK↓ to SDIO Output Valid
SCLK↓ to SDIO Output High Z
SCLK, SEN, SDIO, Rise/Fall time
t
Read
Read
2
25
25
10
ns
CDV
t
2
ns
CDZ
t , t
—
ns
R
F
Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
70%
SCLK
30%
tR
tF
tHIGH
tLOW
tHSDIO
tHSEN
70%
30%
tS
SEN
tS
70%
30%
C7
C6–C1
C0
D7
D6–D1
D0
SDIO
Control Byte In
8 Data Bytes In
Figure 6. SPI Control Interface Write Timing Parameters
70%
30%
SCLK
tCDV
tS
tHSEN
tHSDIO
70%
30%
tS
SEN
tCDZ
70%
30%
SDIO
C7
C6–C1
C0
D7
D6–D1
D0
16 Data Bytes Out
(SDIO or GPO1)
Bus
Turnaround
Control Byte In
Figure 7. SPI Control Interface Read Timing Parameters
10
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Si4734/35-B20
Table 8. Digital Audio Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol Test Condition
Min
26
10
10
5
Typ
—
Max
1000
—
Unit
ns
DCLK Cycle Time
t
DCT
DCH
DCLK Pulse Width High
t
—
ns
DCLK Pulse Width Low
t
—
—
ns
DCL
DFS Set-up Time to DCLK Rising Edge
DFS Hold Time from DCLK Rising Edge
t
—
—
ns
SU:DFS
HD:DFS
t
5
—
—
ns
DOUT Propagation Delay from DCLK Falling
Edge
t
0
—
12
ns
PD:DOUT
tDCH
tDCL
DCLK
tDCT
DFS
tHD:DFS
tSU:DFS
DOUT
tPD:OUT
Figure 8. Digital Audio Interface Timing Parameters, I2S Mode
Rev. 1.0
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Si4734/35-B20
Table 9. FM Receiver Characteristics1,2
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
76
Typ
—
Max
108
3.5
Unit
MHz
Input Frequency
f
RF
Sensitivity with Headphone
(S+N)/N = 26 dB
(S+N)/N = 26 dB
—
2.2
µV EMF
Network
Sensitivity with 50 Ω Network
—
—
1.1
15
—
—
µV EMF
µV EMF
RDS Sensitivity
Δf = 2 kHz,
RDS BLER < 5%
LNA Input Resistance
3
4
4
5
5
6
kΩ
LNA Input Capacitance
pF
Input IP3
100
40
35
60
35
72
—
—
15
25
55
—
—
70
45
10
—
105
50
50
70
—
80
—
—
—
—
63
58
0.1
75
50
—
—
—
—
—
—
—
90
1
dBµV EMF
m = 0.3
±200 kHz
±400 kHz
In-band
dB
dB
dB
dB
AM Suppression
Adjacent Channel Selectivity
Alternate Channel Selectivity
Spurious Response Rejection
mV
Audio Output Voltage
RMS
dB
Hz
kHz
dB
dB
dB
%
Audio Output L/R Imbalance
–3 dB
–3 dB
30
—
—
—
—
0.5
80
54
—
50
Audio Frequency Response Low
Audio Frequency Response High
Audio Stereo Separation
Audio Mono S/N
Audio Stereo S/N
Audio THD
De-emphasis Time Constant
FM_DEEMPHASIS = 2
FM_DEEMPHASIS = 1
Single-ended
µs
µs
R
kΩ
pF
Audio Output Load Resistance
L
L
C
Single-ended
Audio Output Load Capacitance
Notes:
1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests. Tested at
RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and
Universal Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. Δf = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. V
= 1 mV.
EMF
8. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled. Refer to "6. Pin Descriptions: Si4734/35-GM" on page 30.
2
1
0
1
2
9. Δf = 75 kHz.
10. At L and R
pins.
OUT
OUT
11. Analog audio output mode.
12. At temperature (25°C).
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Table 9. FM Receiver Characteristics1,2 (Continued)
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Seek/Tune Time
RCLK tolerance
= 100 ppm
—
—
80
ms/channel
Powerup Time
From powerdown
—
—
—
110
3
ms
dB
RSSI Offset
Input levels of 8 and
60 dBµV at RF Input
–3
Notes:
1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests. Tested at
RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and
Universal Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. Δf = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Guaranteed by characterization.
7. V
= 1 mV.
EMF
8. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled. Refer to "6. Pin Descriptions: Si4734/35-GM" on page 30.
2
1
0
1
2
9. Δf = 75 kHz.
10. At L and R
pins.
OUT
OUT
11. Analog audio output mode.
12. At temperature (25°C).
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Table 10. 64–75.9 MHz Input Frequency FM Receiver Characteristics1
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
64
Typ
—
Max
75.9
—
Unit
MHz
Input Frequency
f
RF
Sensitivity with Headphone
(S+N)/N = 26 dB
—
4.0
µV EMF
Network
LNA Input Resistance
3
4
4
5
5
6
kΩ
LNA Input Capacitance
pF
dBµV EMF
dB
Input IP3
100
40
—
—
72
—
—
15
55
—
70
45
0.7
10
—
—
105
50
50
70
80
—
—
—
—
—
90
1
m = 0.3
±200 kHz
±400 kHz
AM Suppression
dB
Adjacent Channel Selectivity
dB
Alternate Channel Selectivity
mV
Audio Output Voltage
RMS
dB
Audio Output L/R Imbalance
–3 dB
–3 dB
—
30
—
—
0.5
80
54
0.9
—
50
80
Hz
Audio Frequency Response Low
—
kHz
Audio Frequency Response High
63
0.1
75
50
0.8
—
dB
Audio Mono S/N
%
Audio THD
De-emphasis Time Constant
FM_DEEMPHASIS = 2
FM_DEEMPHASIS = 1
µs
µs
V
kΩ
Audio Common Mode Voltage
R
Single-ended
Single-ended
Audio Output Load Resistance
L
L
C
—
pF
Audio Output Load Capacitance
Seek/Tune Time
RCLK tolerance
= 100 ppm
—
ms/channel
Powerup Time
From powerdown
—
—
—
110
3
ms
dB
RSSI Offset
Input levels of 8 and
60 dBµV EMF
–3
Notes:
1. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and Universal
Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. Tested at
RF = 98.1 MHz.
2. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
3. Δf = 22.5 kHz.
4. B = 300 Hz to 15 kHz, A-weighted.
AF
5. Guaranteed by characterization.
6. V
= 1 mV.
EMF
7. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled. Refer to "6. Pin Descriptions: Si4734/35-GM" on page 30.
2
1
0
1
2
8. Δf = 75 kHz.
9. At LOUT and ROUT pins.
10. At temperature 25 °C.
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Table 11. AM/SW/LW Receiver Characteristics1
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Long Wave (LW)
Medium Wave (AM)
Short Wave (SW)
(S+N)/N = 26 dB
THD < 8%
Min
153
520
2.3
—
Typ
—
Max
279
1710
21.85
35
Unit
kHz
f
—
kHz
Input Frequency
RF
—
MHz
Sensitivity
25
µV EMF
Large Signal Voltage Handling
Power Supply Rejection Ratio
—
300
40
—
mV
RMS
RMS
ΔV = 100 mVRMS, 100 Hz
—
—
dB
DD
Audio Output Voltage
54
60
67
mV
Audio S/N
50
56
—
dB
Audio THD
—
0.1
2800
—
0.5
—
%
Long Wave (LW)
Medium Wave (AM)
From powerdown
—
µH
ms
Antenna Inductance
180
—
450
110
Powerup Time
—
Notes:
1. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and
Universal Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
2. FMOD = 1 kHz, 30% modulation, A-weighted, 2 kHz channel filter.
3. B = 300 Hz to 15 kHz, A-weighted.
AF
4. f = 1000 kHz, Δf = 10 kHz.
RF
5. Guaranteed by characterization.
6. Analog audio output mode.
7. See “AN388: Evaluation Board Test Procedure” for evaluation method.
8. V = 5 mVrms.
IN
9. Stray capacitance on antenna and board must be < 10 pF to achieve full tuning range at higher inductance levels.
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Table 12. Reference Clock and Crystal Characteristics
(V = 2.7 to 5.5 V, V = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
IO
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Reference Clock
*
RCLK Supported Frequencies
RCLK Frequency Tolerance
REFCLK_PRESCALE
REFCLK
31.130
–50
32.768
—
40000.0
50
kHz
ppm
1
—
4095
31.130
32.768
34.406
kHz
Crystal Oscillator
Crystal Oscillator Frequency
Crystal Frequency Tolerance*
Board Capacitance
—
–100
—
32.768
—
—
kHz
ppm
pF
100
3.5
—
*Note: The Si4734/35 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK
frequencies between 31.130 kHz and 40 MHz that are not supported. See AN332, Table 6 for more details.
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2. Typical Application Schematic
GPO1
GPO2/INT
R1
DCLK
DFS
R2
15
R3
DOUT
DOUT
1
NC
Optional: Digital Audio Output
2
FMI
FMI
C4
C5
3
14
13
12
11
RFGND
LOUT
ROUT
LOUT
ROUT
GND
U1
L2
L1
Si4734/35-GM
4
5
AMI
VDD
VBATTERY
2.7 to 5.5 V
RST
C1
RST
SEN
X1
GPO3
RCLK
SCLK
SDIO
RCLK
VIO
C2
C3
Optional: for crystal oscillator option
1.5 to 3.6 V
Notes:
1. Place C1 close to V pin.
DD
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 20 are no connects, leave floating.
4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and Universal
Layout Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
5. Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface.
6. RFGND should be locally isolated from GND.
7. Place Si4734/35 as close as possible to antenna jack and keep the FMI and AMI traces as short as possible.
8. See “AN382: Si4734/35 Designer’s Guide” for further recommendations.
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3. Bill of Materials
Component(s)
Value/Description
Supplier
Murata
C1
C4
C5
L1
Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R
Capacitor, 18 pF, ±20%, Z5U/X7R
Coupling capacitor, 0.47 µF, ±20%, Z5U/X7R
Ferrite loop stick, 180–450 µH
4.7 µH
Murata
Murata
Jiaxin
L2
U1
Coilcraft
Si4734/35 AM/FM Radio Tuner
Optional Components
Silicon Laboratories
C2, C3
Crystal load capacitors, 22 pF, ±5%, COG
(Optional: for crystal oscillator option)
Venkel
X1
R1, R2
R3
32.768 kHz crystal (Optional: for crystal oscillator option)
Epson
Venkel
Venkel
Resistor, 2 kΩ
Resistor, 600 Ω
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4. Functional Description
4.1. Overview
FM / SW
ANT
Si4734/35
FMI
DOUT
RDS
(Si4735)
DIGITAL
AUDIO
(Si4735)
LNA
AGC
DFS
GPO/DCLK
LOW-IF
DSP
ADC
ADC
DAC
DAC
ROUT
LOUT
AM / LW
ANT
AMI
LNA
AGC
RFGND
2.7 - 5.5 V
VDD
GND
CONTROL
INTERFACE
LDO
AFC
VIO
1.5-3.6V
Figure 9. Functional Block Diagram
The Si4734/35 is the industry's first fully integrated, Si4700/01
100% CMOS AM/FM/SW/LW radio receiver IC. Offering interface.
unmatched integration and PCB space savings, the
backwards-compatible
3-wire
control
The Si4734/35 utilizes digital processing to achieve high
fidelity, optimal performance, and design flexibility. The
chip provides excellent pilot rejection, selectivity, and
unmatched audio performance, and offers both the
Si4734/35 requires minimal external components and
2
less than 20 mm of board area, excluding the antenna
inputs. The Si4734/35 AM/FM/SW/LW radio provides
the space savings and low power consumption
necessary for portable devices while delivering the high
performance and design simplicity desired for all
AM/FM/SW/LW solutions.
manufacturer
and
the
end-user
extensive
programmability and flexibility in the listening
experience.
The Si4735 incorporates a digital processor for the
European Radio Data System (RDS) and the North
American Radio Broadcast Data System (RBDS),
including all required symbol decoding, block
synchronization, error detection, and error correction
functions. Using RDS, the Si4735 enables broadcast
data such as station identification and song name to be
displayed to the user.
Leveraging Silicon Laboratories' proven and patented
Si4700/01 FM tuner's digital low intermediate frequency
(low-IF) receiver architecture, the Si4734/35 delivers
superior RF performance and interference rejection in
AM, FM, and short wave and long wave bands. The
high integration and complete system production test
simplifies design-in, increases system quality, and
improves manufacturability.
The Si4734/35 is a feature-rich solution including
advanced seek algorithms, soft mute, auto-calibrated
digital tuning, and FM stereo processing. In addition, the
Si4734/35 provides analog or digital audio output and a
programmable reference clock. The device supports
2
I C-compatible 2-wire control interface, SPI, and a
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The Si4734/35 provides highly accurate digital AM
tuning without factory adjustments. To offer maximum
flexibility, the receiver supports a wide range of ferrite
loop sticks from 180–450 µH. An air loop antenna is
supported by using a transformer to increase the
effective inductance from the air loop. Using a 1:5 turn
ratio inductor, the inductance is increased by 25 times,
easily supporting all typical AM air loop antennas which
generally vary between 10 and 20 µH.
4.2. Operating Modes
The Si4734/35 operates in either an FM receive or an
AM/SW/LW receive mode. In FM mode, radio signals
are received on FMI (pin 2) and processed by the FM
front-end circuitry. In AM/SW/LW mode, radio signals
are received on AMI (pin 4) and processed by the AM
front-end circuitry. In addition to the receiver mode, a
clocking mode allows the Si4734/35 to be clocked from
a reference clock or crystal. On the Si4735, an audio
output mode is available as analog and/or digital audio
output. In the analog audio output mode, pin 13 is
ROUT, pin 14 is LOUT, pin 17 is GPO3. In the digital
audio mode, pin 15 is DOUT, pin 16 is DFS, and pin 17
is DCLK. Concurrent analog/digital audio output mode
requires pins 13, 14, 15,16, and 17. The receiver mode
and the audio output mode are set by the POWER_UP
command listed in Table 12. Si473x Command
Summary.
4.5. SW Receiver
The Si4734/35 is the first fully integrated IC to support
AM and FM, as well as short wave (SW) band reception
from 2.3 to 21.85 MHz fully covering the 120 meter to
13 meter bands. The Si4734/35 offers extensive
shortwave features such as continuous digital tuning
with minimal discrete components and no factory
adjustments. Other SW features include adjustable
channel step sizes in 1 kHz increments, adjustable
channel bandwidth settings, advanced seek algorithm,
and soft mute.
4.3. FM Receiver
The Si4734/35's patented digital low-IF architecture
reduces external components and eliminates the need
for factory adjustments. The Si4734/35 receiver
supports the worldwide FM broadcast band (76 to 108
MHz) as well as an extended FM band (64 to 76 MHz),
which may include region-specific programming such as
educational channels, emergency alerts, and/or
television audio. An automatic gain control (AGC) circuit
controls the gain of the integrated low noise amplifier
(LNA) to optimize sensitivity and rejection of strong
interferers. An image-reject mixer downconverts the RF
signal to low-IF. The quadrature mixer output is
amplified, filtered, and digitized with high resolution
analog-to-digital converters (ADCs). This advanced
The Si4734/35 uses the FM antenna to capture short
wave signals. These signals are then fed directly into
the AMI pin in a wide band configuration. See “AN382:
Si4734/35 Designer’s Guide” for more details.
4.6. LW Receiver
The Si4734/35 supports the long wave (LW) band from
153 to 279 kHz. The highly integrated Si4734/35 offers
continuous digital tuning with minimal discrete
components and no factory adjustments. The Si4734/35
also offers adjustable channel step sizes in 1 kHz
increments, adjustable channel bandwidth settings,
advanced seek algorithm, and soft mute.
architecture allows the Si4734/35 to perform channel The Si4734/35 uses a separate ferrite bar antenna to
selection, FM demodulation, and stereo audio capture long wave signals.
processing to achieve superior performance compared
to traditional analog architectures.
4.4. AM Receiver
The highly integrated Si4734/35 supports worldwide AM
band reception from 520 to 1710 kHz using a digital low-
IF architecture with a minimum number of external
components and no manual alignment required. This
digital low-IF architecture allows for high-precision
filtering, offering excellent selectivity and noise
suppression. The DSP also provides 9 or 10 kHz
channel selection, AM demodulation, soft mute, and
additional features such as adjustable channel
bandwidth settings. Similar to the FM receiver, the
integrated LNA and AGC optimize sensitivity and
rejection of strong interferers allowing better reception
of weak stations.
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4.7. Digital Audio Interface (Si4735 Only)
The digital audio interface operates in slave mode and
supports three different audio data formats:
2
„ I S
„ Left-Justified
„ DSP Mode
4.7.1. Audio Data Formats
2
In I S mode, by default the MSB is captured on the
second rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is low, and the right channel is
transferred when the DFS is high.
In Left-Justified mode, by default the MSB is captured
on the first rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is high, and the right channel is
transferred when the DFS is low.
In DSP mode, the DFS becomes a pulse with a width of
1 DCLK period. The left channel is transferred first,
followed right away by the right channel. When
transferring the digital audio data in DSP mode, the
MSB of the left channel can be transferred on the first
rising edge of DCLK following the DFS pulse or on the
second rising edge.
In all audio formats, depending on the word size, DCLK
frequency, and sample rates, there may be unused
DCLK cycles after the LSB of each word and before the
next DFS transition and MSB of the next word. In
addition, if preferred, the user can configure the MSB to
be captured on the falling edge of DCLK via properties.
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
4.7.2. Audio Sample Rates
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs on the audio
baseband processor.
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INVERTED
(OFALL = 1)
DCLK
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
I2S
RIGHT CHANNEL
(OMODE = 0000)
1 DCLK
1 DCLK
n-2
DOUT
1
2
3
n-1
n
n-2
n-1
1
2
3
n
MSB
LSB
MSB
LSB
Figure 10. I2S Digital Audio Format
INVERTED
DCLK
(OFALL = 1)
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
RIGHT CHANNEL
n-2
Left-Justified
(OMODE = 0110)
DOUT
1
2
3
n-2
n-1
n
n-1
n
1
2
3
MSB
LSB
MSB
LSB
Figure 11. Left-Justified Digital Audio Format
(OFALL = 0)
DCLK
DFS
RIGHT CHANNEL
n-2
LEFT CHANNEL
n-2
DOUT
1
2
3
2
n-1
n
(OMODE = 1100)
(OMODE = 1000)
1
2
3
2
n-1
n
(MSB at 1st rising edge)
MSB
LSB
MSB
LSB
LEFT CHANNEL
n-2
1 DCLK
RIGHT CHANNEL
n-2
DOUT
1
3
n-1
n
1
3
n-1
n
(MSB at 2nd rising edge)
MSB
LSB
MSB
LSB
Figure 12. DSP Digital Audio Format
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4.8. Stereo Audio Processing
4.9. De-emphasis
The output of the FM demodulator is a stereo Pre-emphasis and de-emphasis is a technique used by
multiplexed (MPX) signal. The MPX standard was FM broadcasters to improve the signal-to-noise ratio of
developed in 1961, and is used worldwide. Today's FM receivers by reducing the effects of high-frequency
MPX signal format consists of left + right (L+R) audio, interference and noise. When the FM signal is
left – right (L–R) audio, a 19 kHz pilot tone, and transmitted,
a
pre-emphasis filter is applied to
accentuate the high audio frequencies. The Si4734/35
incorporates a de-emphasis filter which attenuates high
frequencies to restore a flat frequency response. Two
time constants are used in various regions. The de-
emphasis time constant is programmable to 50 or 75 µs
and is set by the FM_DEEMPHASIS property.
Mono Audio
Left + Right
Stereo
Pilot
Stereo Audio
Left - Right
RDS/
RBDS
4.10. Stereo DAC
High-fidelity stereo digital-to-analog converters (DACs)
drive analog audio signals onto the LOUT and ROUT
pins. The audio output may be muted. Volume is
adjusted digitally with the RX_VOLUME property.
0
15 19 23
38
53 57
Frequency (kHz)
4.11. Soft Mute
Figure 13. MPX Signal Spectrum
The soft mute feature is available to attenuate the audio
outputs and minimize audible noise in very weak signal
conditions. The softmute attenuation level is adjustable
using the FM_SOFT_MUTE_MAX_ATTENUATION and
AM_SOFT_MUTE_MAX_ATTENUATION properties.
4.8.1. Stereo Decoder
The Si4734/35's
integrated
stereo
decoder
automatically decodes the MPX signal using DSP
techniques. The 0 to 15 kHz (L+R) signal is the mono
output of the FM tuner. Stereo is generated from the
(L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is
used as a reference to recover the (L–R) signal. Output
left and right channels are obtained by adding and
subtracting the (L+R) and (L–R) signals respectively.
The Si4735 uses frequency information from the 19 kHz
stereo pilot to recover the 57 kHz RDS/RBDS signal.
4.12. RDS/RBDS Processor (Si4735 Only)
The Si4735 implements an RDS/RBDS* processor for
symbol decoding, block synchronization, error
detection, and error correction.
The Si4735 device is user configurable and provides an
optional interrupt when RDS is synchronized, loses
synchronization, and/or the user configurable RDS
FIFO threshold has been met.
4.8.2. Stereo-Mono Blending
Adaptive noise suppression is employed to gradually
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
to maintain optimum sound fidelity under varying
reception conditions. Stereo/mono status can be
monitored with the FM_RSQ_STATUS command. Mono
The Si4735 reports RDS decoder synchronization
status, and detailed bit errors in the information word for
each RDS block with the FM_RDS_STATUS command.
The range of reportable block errors is 0, 1–2, 3–5, or
6+. More than six errors indicates that the
corresponding block information word contains six or
more non-correctable errors, or that the block
checkword contains errors.
operation
can
be
forced
with
the
FM_BLEND_MONO_THRESHOLD property.
*Note: RDS/RBDS is referred to only as RDS throughout the
remainder of this document.
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For best seek/tune results, Silicon Laboratories
recommends that all SDIO data traffic be suspended
during Si4734/35 seek and tune operations. This is
achieved by keeping the bus quiet for all other devices
on the bus, and delaying tuner polling until the tune or
seek operation is complete. The seek/tune complete
(STC) interrupt should be used instead of polling to
determine when a seek/tune operation is complete.
4.13. Tuning
The frequency synthesizer uses Silicon Laboratories’
proven technology, including a completely integrated
VCO. The frequency synthesizer generates the
quadrature local oscillator signal used to downconvert
the RF input to a low intermediate frequency. The VCO
frequency is locked to the reference clock and adjusted
with an automatic frequency control (AFC) servo loop
during reception. The tuning frequency can be directly
programmed using the FM_TUNE_FREQ and
AM_TUNE_FREQ commands. The Si4734/35 supports
channel spacing steps of 10 kHz in FM mode and 1 kHz
in AM/SW/LW mode.
4.16. Control Interface
A serial port slave interface is provided, which allows an
external controller to send commands to the Si4734/35
and receive responses from the device. The serial port
can operate in three bus modes: 2-wire mode, 3-wire
mode, or SPI mode. The Si4734/35 selects the bus
mode by sampling the state of the GPO1 and GPO2
pins on the rising edge of RST. The GPO1 pin includes
an internal pull-up resistor, which is connected while
RST is low, and the GPO2 pin includes an internal pull-
down resistor, which is connected while RST is low.
Therefore, it is only necessary for the user to actively
4.14. Seek
Seek tuning will search up or down for a valid channel.
Valid channels are found when the receive signal
strength indicator (RSSI) and the signal-to-noise ratio
(SNR) values exceed the set threshold. Using the SNR
qualifier rather than solely relying on the more
traditional RSSI qualifier can reduce false stops and
increase the number of valid stations detected. Seek is
initiated
using
the
FM_SEEK_START
and
Table 13. Bus Mode Select on Rising Edge of
RST
AM_SEEK_START commands. The RSSI and SNR
threshold settings are adjustable using properties (see
Bus Mode
2-Wire
SPI
GPO1
GPO2
Two seek options are available. The device will either
wrap or stop at the band limits. If the seek operation is
unable to find a channel, the device will indicate failure
and return to the channel selected before the seek
operation began.
1
0
1
1 (must drive)
0
3-Wire
0 (must drive)
After the rising edge of RST, the pins GPO1 and GPO2
are used as general purpose output (O) pins, as
mode, commands may only be sent after V and V
4.15. Reference Clock
The Si4734/35 reference clock is programmable,
IO
DD
supplies are applied.
voltage
levels
and
“FM
Receiver
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high).
information.
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to "2. Typical Application
Schematic" on page 17. This mode is enabled using the
4.16.1. 2-Wire Control Interface Mode
When selecting 2-wire mode, the user must ensure that
SCLK is high during the rising edge of RST, and stays
high until after the first start condition. Also, a start
condition must not occur within 300 ns before the rising
edge of RST.
The Si4734/35 performance may be affected by data
activity on the SDIO bus when using the integrated
internal oscillator. SDIO activity results from polling the
tuner for status or communicating with other devices
that share the SDIO bus. If there is SDIO bus activity
while the Si4734/35 is performing the seek/tune
function, the crystal oscillator may experience jitter,
which may result in mistunes, false stops, and/or lower
SNR.
The 2-wire bus mode uses only the SCLK and SDIO
pins for signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
high. Next, the user drives an 8-bit control word serially
on SDIO, which is captured by the device on rising
edges of SCLK. The control word consists of a 7-bit
device address, followed by a read/write bit (read = 1,
write = 0). The Si4734/35 acknowledges the control
24
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Si4734/35-B20
word by driving SDIO low on the next falling edge of A transaction ends when the user sets SEN high, then
SCLK.
pulses SCLK high and low one final time. SCLK may
either stop or continue to toggle while SEN is high.
Although the Si4734/35 will respond to only a single
device address, this address can be changed with the In 3-wire mode, commands are sent by first writing each
SEN pin (note that the SEN pin is not used for signaling argument to register(s) 0xA1–0xA3, then writing the
in 2-wire mode). When SEN = 0, the 7-bit device command word to register 0xA0. A response is
address is 0010001b. When SEN = 1, the address is retrieved by reading registers 0xA8–0xAF.
1100011b.
For details on timing specifications and diagrams, refer
For write operations, the user then sends an 8-bit data to Table 6, “3-Wire Control Interface Characteristics,” on
byte on SDIO, which is captured by the device on rising page 9; Figure 4, “3-Wire Control Interface Write Timing
edges of SCLK. The Si4734/35 acknowledges each Parameters,” on page 9, and Figure 5, “3-Wire Control
data byte by driving SDIO low for one cycle, on the next Interface Read Timing Parameters,” on page 9.
falling edge of SCLK. The user may write up to 8 data
4.16.3. SPI Control Interface Mode
bytes in a single 2-wire transaction. The first byte is a
When selecting SPI mode, the user must ensure that a
command, and the next seven bytes are arguments.
rising edge of SCLK does not occur within 300 ns
For read operations, after the Si4734/35 has
before the rising edge of RST.
acknowledged the control byte, it will drive an 8-bit data
SPI bus mode uses the SCLK, SDIO, and SEN pins for
byte on SDIO, changing the state of SDIO on the falling
read/write operations. The system controller can
edge of SCLK. The user acknowledges each data byte
choose to receive read data from the device on either
by driving SDIO low for one cycle, on the next falling
SDIO or GPO1. A transaction begins when the system
edge of SCLK. If a data byte is not acknowledged, the
controller drives SEN = 0. The system controller then
transaction will end. The user may read up to 16 data
pulses SCLK eight times, while driving an 8-bit control
bytes in a single 2-wire transaction. These bytes contain
byte serially on SDIO. The device captures the data on
the response data from the Si4734/35.
rising edges of SCLK. The control byte must have one
A 2-wire transaction ends with the STOP condition,
of five values:
which occurs when SDIO rises while SCLK is high.
„ 0x48 = write a command (controller drives 8
For details on timing specifications and diagrams, refer
additional bytes on SDIO).
„ 0x80 = read a response (device drives 1additional
byte on SDIO).
„ 0xC0 = read a response (device drives 16 additional
bytes on SDIO).
„ 0xA0 = read a response (device drives 1 additional
4.16.2. 3-Wire Control Interface Mode
byte on GPO1).
When selecting 3-wire mode, the user must ensure that
a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
„ 0xE0 = read a response (device drives 16 additional
bytes on GPO1).
For write operations, the system controller must drive
exactly 8 data bytes (a command and seven arguments)
on SDIO after the control byte. The data is captured by
the device on the rising edge of SCLK.
The 3-wire bus mode uses the SCLK, SDIO, and SEN_
pins. A transaction begins when the user drives SEN
low. Next, the user drives a 9-bit control word on SDIO,
which is captured by the device on rising edges of
SCLK. The control word consists of a 9-bit device
address (A7:A5 = 101b), a read/write bit (read = 1, write
= 0), and a 5-bit register address (A4:A0).
For read operations, the controller must read exactly 1
byte (STATUS) after the control byte or exactly 16 data
bytes (STATUS and RESP1–RESP15) after the control
byte. The device changes the state of SDIO (or GPO1, if
specified) on the falling edge of SCLK. Data must be
captured by the system controller on the rising edge of
SCLK.
For write operations, the control word is followed by a
16-bit data word, which is captured by the device on
rising edges of SCLK.
For read operations, the control word is followed by a
delay of one-half SCLK cycle for bus turn-around. Next,
the Si4734/35 will drive the 16-bit read data word
serially on SDIO, changing the state of SDIO on each
rising edge of SCLK.
Keep SEN low until all bytes have transferred. A
transaction may be aborted at any time by setting SEN
high and toggling SCLK high and then low. Commands
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will be ignored by the device if the transaction is
aborted.
4.20. Programming with Commands
To ease development time and offer maximum
For details on timing specifications and diagrams, refer customization, the Si4734/35 provides a simple yet
powerful software interface to program the receiver. The
device is programmed using commands, arguments,
properties and responses.
4.17. GPO Outputs
The Si4734/35 provides five general-purpose output
pins. The GPO pins can be configured to output a
constant low, constant high, or high-impedance. The
GPO pins can be reconfigured as specialized functions.
GPO2/INT can be configured to provide interrupts and
GPO3 can be configured to provide external crystal
support or as DCLK in digital audio output mode. In
digital output mode (Si4735 only), GPO6 and GPO7 can
be configured as DFS and DOUT respectively.
To perform an action, the user writes a command byte
and associated arguments, causing the chip to execute
the given command. Commands control an action such
as power up the device, shut down the device, or tune
to a station. Arguments are specific to a given command
and are used to modify the command. A complete list of
Properties are a special command argument used to
modify the default chip operation and are generally
configured immediately after power up. Examples of
properties are de-emphasis level, RSSI seek threshold,
and soft mute attenuation threshold. A complete list of
4.18. Firmware Upgrades
The Si4734/35 contains on-chip program RAM to
accommodate minor changes to the firmware. This
allows Silicon Labs to provide future firmware updates
to optimize the characteristics of new radio designs and
those already deployed in the field.
Responses provide the user information and are
echoed after a command and associated arguments are
issued. All commands provide a one-byte status update
indicating interrupt and clear-to-send status information.
For a detailed description of the commands and
properties for the Si4734/35, see “AN332: Universal
Programming Guide.”
4.19. Reset, Power Up, and Power Down
Setting the RST pin low will disable analog and digital
circuitry, reset the registers to their default settings, and
disable the bus. Setting the RST pin high will bring the
device out of reset.
A power down mode is available to reduce power
consumption when the part is idle. Putting the device in
power down mode will disable analog and digital
circuitry while keeping the bus active.
26
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5. Commands and Properties
Table 14. Si473x Command Summary
Cmd
Name
Description
Power up device and mode selection. Modes include AM/SW/LW or FM
receive, analog or digital output, and reference clock or crystal support.
0x01
POWER_UP
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x20
0x21
GET_REV
Returns revision information on the device.
Power down device.
POWER_DOWN
SET_PROPERTY
GET_PROPERTY
GET_INT_STATUS
PATCH_ARGS
Sets the value of a property.
Retrieves a property’s value.
Read interrupt status bits.
Reserved command used for firmware file downloads.
Reserved command used for firmware file downloads.
Selects the FM tuning frequency.
Begins searching for a valid frequency
PATCH_DATA
FM_TUNE_FREQ
FM_SEEK_START
Queries the status of previous FM_TUNE_FREQ or FM_SEEK_START
command.
0x22
0x23
FM_TUNE_STATUS
FM_RSQ_STATUS
Queries the status of the Received Signal Quality (RSQ) of the current chan-
nel (Si4735 only).
Returns RDS information for current channel and reads an entry from the
RDS FIFO (Si4735 only).
0x24
0x40
0x41
FM_RDS_STATUS
AM_TUNE_FREQ
AM_SEEK_START
Tunes to a given AM or SW/LW frequency.
Begins searching for a valid AM or SW/LW frequency depending on the
AM_SEEK_BAND_BOTTOM and AM_SEEK_BAND_TOP settings.
Queries the status of the already issued AM_TUNE_FREQ or
AM_SEEK_START command.
0x42
AM_TUNE_STATUS
0x43
0x80
0x81
AM_RSQ_STATUS
GPO_CTL
Queries the status of the RSQ for the current channel.
Configures GPO pins.
GPO_SET
Sets the value of the GPO pins.
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Table 15. Si473x Property Summary
Prop
Name
Description
Default
0x0001
GPO_IEN
Enables interrupt sources.
0x0000
0x0000
0x0102 DIGITAL_OUTPUT_FORMAT Configures the digital output format (Si4735 only).
DIGITAL_OUTPUT_
SAMPLE_RATE
Configures the digital output sample rate in 100 Hz steps. The
digital output sample rate is disabled by default (Si4735 only).
0x0104
0x0201
0x0000
0x8000
Sets frequency of reference clock in Hz. The range is 31130 to
34406 Hz, or 0 to disable the AFC. Default is 32768 Hz.
REFCLK_FREQ
0x0202
0x1100
REFCLK_PRESCALE
FM_DEEMPHASIS
Sets the prescaler value for RCLK input.
0x0001
0x0002
Sets de-emphasis time constant. Default is 75 us.
Sets RSSI threshold for stereo blend (full stereo above thresh-
old, blend below threshold). To force stereo set this to 0. To
force mono set this to 127. Default value is 49 dBuV.
FM_BLEND_STEREO_
THRESHOLD
0x1105
0x1106
0x0031
0x001E
Sets RSSI threshold for mono blend (full mono below threshold,
blend above threshold). To force stereo set this to 0. To force
mono set this to 127. Default value is 30 dBuV.
FM_BLEND_MONO_
THRESHOLD
FM_MAX_TUNE_
ERROR
Sets the maximum freq error allowed before setting the AFC rail
(AFCRL) indicator. Default value is 30 kHz.
0x1108
0x1200
0x1201
0x1202
0x1203
0x1204
0x1207
0x1302
0x1303
0x001E
0x0000
0x007F
0x0000
0x007F
0x0000
0x0081
0x0010
0x0004
FM_RSQ_INT_
SOURCE
Configures interrupt related to RSQ metrics.
Sets high threshold for SNR interrupt.
Sets low threshold for SNR interrupt.
Sets high threshold for RSSI interrupt.
Sets low threshold for RSSI interrupt.
FM_RSQ_SNR_HI_
THRESHOLD
FM_RSQ_SNR_LO_
THRESHOLD
FM_RSQ_RSSI_HI_
THRESHOLD
FM_RSQ_RSSI_LO_
THRESHOLD
FM_RSQ_BLEND_
THRESHOLD
Sets the blend threshold for blend interrupt when boundary is
crossed.
FM_SOFT_MUTE_
MAX_ATTENUATION
Sets maximum attenuation during soft mute (dB). Set to 0 to dis-
able soft mute. Default is 16 dB.
FM_SOFT_MUTE_
SNR_THRESHOLD
Sets SNR threshold to engage soft mute. Default is 4 dB.
FM_SEEK_BAND_
BOTTOM
0x1400
0x1401
0x1402
Sets the bottom of the FM band for seek. Default is 8750.
Sets the top of the FM band for seek. Default is 10790.
Selects frequency spacing for FM seek.
0x222E
0x2A26
0x000A
FM_SEEK_BAND_TOP
FM_SEEK_FREQ_
SPACING
FM_SEEK_TUNE_
SNR_THRESHOLD
Sets the SNR threshold for a valid FM Seek/Tune. Default value
is 3 dB.
0x1403
0x0003
FM_SEEK_TUNE_
RSSI_TRESHOLD
Sets the RSSI threshold for a valid FM Seek/Tune. Default
value is 20 dBuV.
0x1404
0x1500
0x1501
0x0014
0x0000
0x0000
RDS_INT_SOURCE
Configures RDS interrupt behavior.
Sets the minimum number of RDS groups stored in the receive
RDS FIFO required before RDS RECV is set.
RDS_INT_FIFO_COUNT
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Table 15. Si473x Property Summary (Continued)
Prop
Name
Description
Default
0x1502
RDS_CONFIG
Configures RDS setting.
0x0000
Sets de-emphasis time constant. Can be set to 50 us. De-
emphasis is disabled by default.
0x3100
AM_DEEMPHASIS
AM_CHANNEL_FILTER
AM_RSQ_INTERRUPTS
0x0000
Selects the bandwidth of the channel filter for AM/SW/LW recep-
tion. The choices are 6, 4, 3, 2, or 1 (kHz). The default band-
width is 2 kHz.
0x3102
0x0003
Configures interrupt related to RSQ metrics. All interrupts are
disabled by default.
0x3200
0x3201
0x3202
0x3203
0x3204
0x0000
0x007F
0x0000
0x007F
0x0000
0x0040
AM_RSQ_SNR_HIGH_
THRESHOLD
Sets high threshold for SNR interrupt. The default is 0 dB.
Sets low threshold for SNR interrupt. The default is 0 dB.
Sets high threshold for RSSI interrupt. The default is 0 dB.
Sets low threshold for RSSI interrupt. The default is 0 dB.
AM_RSQ_SNR_LOW_
THRESHOLD
AM_RSQ_RSSI_HIGH_
THRESHOLD
AM_RSQ_RSSI_LOW_
THRESHOLD
Sets the rate of attack when entering or leaving soft mute. The
default is 278 dB/s.
0x3300 AM_SOFT_MUTE_RATE
Sets the AM/SW/LW soft mute slope. The bigger the number,
0x3301 AM_SOFT_MUTE_SLOPE the higher the max attenuation level. Default value is a slope of 0x0002
2.
AM_SOFT_MUTE_MAX_ Sets maximum attenuation during soft mute (dB). Set to 0 to dis-
0x3302
0x3303
0x0010
0x000A
ATTENUATION
able soft mute. Default is 16 dB.
AM_SOFT_MUTE_SNR_
THRESHOLD
Sets SNR threshold to engage soft mute. Default is 10 dB.
AM_SEEK_BAND_
BOTTOM
0x3400
0x3401
0x3402
Sets the bottom of the AM/SW/LW band for seek. Default is 520. 0x0208
AM_SEEK_BAND_TOP
Sets the top of the AM/SW/LW band for seek. Default is 1720.
0x06AE
0x000A
AM_SEEK_FREQ_
SPACING
Selects frequency spacing for AM/SW/LW seek. Default is 10
kHz spacing.
Sets the SNR threshold for a valid AM/SW/LW Seek/Tune. If the
value is zero then SNR threshold is not considered when doing 0x0005
a seek. Default value is 5 dB.
AM_SEEK_SNR_
THRESHOLD
0x3403
0x3404
Sets the RSSI threshold for a valid AM/SW/LW Seek/Tune. If
the value is zero then RSSI threshold is not considered when
doing a seek. Default value is 25 dBuV.
AM_SEEK_RSSI_
THRESHOLD
0x0019
0x4000
0x4001
RX_VOLUME
Sets the output volume.
0x003F
0x0000
Mutes the audio output. L and R audio outputs may be muted
independently in FM mode.
RX_HARD_MUTE
Rev. 1.0
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6. Pin Descriptions: Si4734/35-GM
20 19 18 17
NC
FMI
1
16
2
15 DOUT
14 LOUT
13 ROUT
12 GND
11 VDD
RFGND
AMI
3
4
5
GND
PAD
RST
6
7
8
9
10
Pin Number(s)
Name
NC
Description
1, 20
No connect. Leave floating.
FM RF inputs.
2
FMI
3
RFGND
AMI
RF ground. Connect to ground plane on PCB.
AM/SW/LW RF input.
4
5
RST
Device reset (active low) input.
6
SEN
Serial enable input (active low).
7
SCLK
SDIO
RCLK
Serial clock input.
8
Serial data input/output.
9
External reference oscillator input.
I/O supply voltage.
10
V
IO
11
V
Supply voltage. May be connected directly to battery.
Ground. Connect to ground plane on PCB.
Right audio line output in analog output mode.
Left audio line output in analog output mode.
Digital output data in digital output mode.
Digital frame synchronization input in digital output mode.
DD
12, GND PAD
GND
ROUT
LOUT
DOUT
DFS
13
14
15
16
17
GPO3/DCLK General purpose output, crystal oscillator, or digital bit synchronous clock input
in digital output mode.
18
19
GPO2/INT
GPO1
General purpose output or interrupt pin.
General purpose output.
30
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7. Ordering Guide
Part Number*
Description
Package
Type
Operating
Temperature
Si4734-B20-GM AM/FM/SW/LW Broadcast Radio Receiver
QFN
Pb-free
–20 to 85 °C
–20 to 85 °C
Si4735-B20-GM AM/FM/SW/LW Broadcast Radio Receiver with
RDS/RBDS
QFN
Pb-free
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
Rev. 1.0
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Si4734/35-B20
8. Package Markings (Top Marks)
8.1. Si4734/35 Top Mark
3420
BTTT
3520
BTTT
YWW
YWW
8.2. Top Mark Explanation
Mark Method:
YAG Laser
Line 1 Marking:
Part Number
34 = Si4734, 35 = Si4735
Firmware Revision
Die Revision
20 = Firmware Revision 2.0
B = Revision B Die
Line 2 Marking:
Line 3 Marking:
TTT = Internal Code
Internal tracking code.
Circle = 0.5 mm Diameter Pin 1 Identifier
(Bottom-Left Justified)
Y = Year
Assigned by the Assembly House. Corresponds to the last sig-
nificant digit of the year and workweek of the mold date.
WW = Workweek
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9. Package Outline: Si4734/35 QFN
Figure 14 illustrates the package details for the Si4734/35. Table 16 lists the values for the dimensions shown in
the illustration.
Figure 14. 20-Pin Quad Flat No-Lead (QFN)
Table 16. Package Dimensions
Symbol
Millimeters
Nom
Symbol
Millimeters
Nom
Min
Max
Min
Max
A
A1
b
0.50
0.00
0.20
0.27
0.55
0.02
0.60
0.05
0.30
0.37
f
2.53 BSC
L
0.35
0.00
—
0.40
—
0.45
0.10
0.05
0.05
0.08
0.10
0.10
0.25
L1
c
0.32
aaa
bbb
ccc
ddd
eee
—
D
3.00 BSC
1.70
—
—
D2
e
1.65
1.65
1.75
1.75
—
—
0.50 BSC
3.00 BSC
1.70
—
—
E
—
—
E2
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
Rev. 1.0
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10. PCB Land Pattern: Si4734/35 QFN
Figure 15 illustrates the PCB land pattern details for the Si4734/35-GM. Table 17 lists the values for the dimensions
shown in the illustration.
Figure 15. PCB Land Pattern
34
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Table 17. PCB Land Pattern Dimensions
Symbol
Millimeters
Min Max
2.71 REF
1.60 1.80
Symbol
Millimeters
Min
Max
D
D2
e
GE
W
2.10
—
—
0.34
0.28
0.50 BSC
2.71 REF
X
—
E
Y
0.61 REF
E2
f
1.60
2.53 BSC
2.10
1.80
ZE
ZD
—
—
3.31
3.31
GD
—
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for Small Body Components.
Rev. 1.0
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Si4734/35-B20
11. Additional Reference Resources
„ EN55020 Compliance Test Certificate
„ AN231: Si4700/01 Headphone and Antenna Interface
„ AN332: Universal Programming Guide
„ AN383: Antenna Selection and Universal Layout Guidelines
„ AN386: Si473x Ferrite Loop Stick Antenna Interface
„ AN388: Universal Evaluation Board Test Procedure
„ AN389: Si473x EVB Quick-Start Guide
This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA
is required for access. To request access, register at http://www.mysilabs.com and send user’s first and last
name, company, NDA reference number, and mysilabs user name to [email protected]. Silicon Labs
recommends an all lower case user name.
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DOCUMENT CHANGE LIST
Revision 0.4 to Revision 1.0
17.
Rev. 1.0
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CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: [email protected]
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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