USB20H04
4-Port USB 2.0 Hub
Controller
Datasheet
Product Features
General Features
OEM Selectable Features
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ƒ
ƒ
Compliant with USB 2.0 Specification
ƒ
Configure as a bus-powered or self-powered
Hi-Speed USB hub
Hub controller IC with four downstream ports
Four transaction translators ensure maximum USB
throughput
ƒ
Configure port power switching and current
sensing on an individual or ganged basis
ƒ
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Enables bus-powered Hi-Speed hub design
ƒ
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ƒ
Enable LED indicator support
Compatible with On-The-Go (OTG) USB devices
Enable multiple transaction translators
Integrated Session Request Protocol (SRP)
operates with dual-role OTG hosts
Enable compound device support on a port by port
basis
ƒ
ƒ
Default configuration with pin selectable options
ƒ
Enable downstream facing ports on a port by port
basis
Serial interface for configuration from EEPROM or
microcontroller when default is not used
ƒ
ƒ
Flexible OEM configuration options
Available in a 64-pin TQFP package
Pin Selectable Options for Default Configuration
ƒ
Select operation as either a Bus-Powered hub or a
Self-Powered hub
Hardware Features
ƒ
Detects removal of self-power and automatically
changes mode to bus-power
ƒ
Integrated termination and pull-up/pull-down
resistors
ƒ
ƒ
ƒ
Internal short circuit protection of DP and DM lines
On-chip oscillator uses low cost 24MHz crystal
Supports individual or ganged over-current
protection and power control
ƒ
LED drivers for each downstream port
ORDERING INFORMATION
Order Number(s):
USB20H04-JD for 64 pin, 10x10x1.4 TQFP package
USB20H04-JT for 64 pin, 10x10x1.4 TQFP Lead-Free RoHS Compliant Package
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Table of Contents
Chapter 1 General Description .............................................................................................................5
1.1 Applications.........................................................................................................................................5
1.2 OEM Selectable Features...................................................................................................................6
1.3 Pin Selectable Options to the Default Configuration...........................................................................6
Chapter 2 Functional Block Diagram ..................................................................................................7
Chapter 3 Pinout ....................................................................................................................................8
Chapter 4 Interface Signal Definition ..................................................................................................9
4.1 Pin Descriptions ..................................................................................................................................9
4.2 Buffer Type Descriptions...................................................................................................................11
Chapter 5 Limiting Values ..................................................................................................................12
Chapter 6 Electrical Characteristics ..................................................................................................13
6.1 Dynamic Characteristics: Analog I/O Pins (DP/DM) .........................................................................15
Chapter 7 Functional Overview..........................................................................................................16
7.1 Bus-Power Detect .............................................................................................................................16
7.2 Upstream PHY ..................................................................................................................................16
7.3 Clock/PLL..........................................................................................................................................16
7.4 Internal Configuration Select.............................................................................................................16
7.5 Serial Interface ..................................................................................................................................17
7.5.1
7.5.2
SMBus Slave..........................................................................................................................................17
I2C Memory Interface..............................................................................................................................17
7.6 Repeater............................................................................................................................................17
7.7 SIE.....................................................................................................................................................17
7.8 Controller...........................................................................................................................................17
7.9 Transaction Translator (TT) ..............................................................................................................18
7.10
7.11
7.12
Port Controller................................................................................................................................18
Downstream PHY...........................................................................................................................18
OC Sense/Switch Driver ................................................................................................................18
Over-Current Sense............................................................................................................................18
Switch Driver.......................................................................................................................................18
LED Drivers....................................................................................................................................18
7.12.1
7.12.2
7.13
Chapter 8 Implementation Notes........................................................................................................20
8.1 Configuration Implementations .........................................................................................................20
8.1.1
8.1.2
Interfacing a 2-wire Serial EEPROM.......................................................................................................20
Internal Default Configuration .................................................................................................................21
8.2 EEPROM Programming Values........................................................................................................21
8.3 Default Configuration Values ............................................................................................................23
8.4 Reset .................................................................................................................................................24
8.4.1
8.4.2
External Hardware Reset........................................................................................................................24
USB Reset..............................................................................................................................................27
Chapter 9 Hub Descriptors .................................................................................................................28
Chapter 10
Chapter 11
Application Diagrams.....................................................................................................33
Package Outline ..............................................................................................................35
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List of Figures
Figure 2.1 - Block Diagram.............................................................................................................................................7
Figure 3.1– 64 Pin TQFP ...............................................................................................................................................8
Figure 8.1 - 2-Wire EEPROM Interface........................................................................................................................20
Figure 8.2 - Internal Default Mode................................................................................................................................21
Figure 8.3 - Timing for Configuration from SMBus.......................................................................................................25
Figure 8.4 - Timing to Complete Configuration from EEPROM....................................................................................26
Figure 10.1 - High Level Block Diagram of a Self-Powered Hub..................................................................................33
Figure 10.2 - USB Downstream Port Connection.........................................................................................................34
Figure 11.1 - 64 Pin TQFP Package Outline, 10 x 10 x 1.4 Body, 2 MM Footprint ......................................................35
List of Tables
Table 4.1 - System Interface Signals .............................................................................................................................9
Table 4.2 – Configuration Select and Serial Port Interface.............................................................................................9
Table 4.3 - USB I/O Signals.........................................................................................................................................10
Table 4.4 - Biasing and Clock Oscillator Signals..........................................................................................................11
Table 4.5 - Power and Ground Signals ........................................................................................................................11
Table 4.6 – USB20H04 Buffer Type Descriptions ........................................................................................................11
Table 5.1 - Absolute Maximum Ratings (In accordance with the Absolute Maximum Rating system (IEC 60134).......12
Table 5.2 - Recommended Operating Conditions ........................................................................................................12
Table 5.3 - Recommended Crystal/External Clock Conditions.....................................................................................12
Table 6.1 - Electrical Characteristics: Supply Pins.......................................................................................................13
Table 6.2 - DC Electrical Characteristics: Digital Pins..................................................................................................13
Table 6.3 - Pin Capacitance.........................................................................................................................................14
Table 6.4 - DC Electrical Characteristics: Analog I/O Pins (DP/DM)............................................................................15
Table 7.1 - Automatic Mode Port Indicators.................................................................................................................19
Table 7.2 - Manual Mode Port Indicators .....................................................................................................................19
Table 8.1 - Summary of OEM Value Programming......................................................................................................21
Table 8.2 - Address 6; Config_Byte_3..........................................................................................................................22
Table 8.3 - Address 7; Config_Byte_2..........................................................................................................................22
Table 8.4 - Address 8; Config_Byte_1..........................................................................................................................23
Table 8.5 - Addresses 9 - 11........................................................................................................................................23
Table 8.6 - Default Configuration Values......................................................................................................................24
Table 8.7 - Time Values to Configure from SMBus......................................................................................................25
Table 8.8 - Time Values to Configure From EEPROM.................................................................................................26
Table 9.1 - Device Descriptor.......................................................................................................................................28
Table 9.2 - Device Qualifier Descriptor ........................................................................................................................28
Table 9.3 - Standard Configuration Descriptor.............................................................................................................29
Table 9.4 - Other_Speed_Configuration Descriptor .....................................................................................................29
Table 9.5 - Standard Interface Descriptor ....................................................................................................................30
Table 9.6 - Standard Endpoint Descriptor ....................................................................................................................30
Table 9.7 - Interface Descriptor (present if multiple-TT)...............................................................................................31
Table 9.8 - On-The-GO (OTG) Descriptor....................................................................................................................31
Table 9.9 - Class-Specific Hub Descriptor (Full-Speed and High-Speed) ....................................................................31
Table 11.1 - 64 Pin TQFP Package Parameters..........................................................................................................35
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Chapter 1 General Description
The USB20H04 four-port hub controller is fully compliant with the USB 2.0 Specification and does not
require firmware development. When connected to a high-speed host, the four downstream facing ports
can operate at low-speed (1.5Mb/s), full-speed (12Mb/s), or high-speed (480Mb/s). As required by the USB
2.0 Specification, the USB20H04 is fully backward compatible with legacy full-speed hosts. A dedicated
Transaction Translator (TT) is available for each downstream facing port. This architecture ensures
maximum USB throughput for each connected device when operating with mixed-speed peripherals.
The USB20H04 supports both bus-powered and self-powered configurations. For self-powered operation,
an external supply is used to power the downstream facing ports. In bus-powered mode, all power is
derived from the upstream facing port and no external power supply is required. An external USB power
distribution switch device is used to control VBUS switching to downstream ports, and to limit current and
sense over-current conditions.
A default configuration is available in the USB20H04 following a reset. This configuration may be sufficient
for some applications when it is desired to save the expense of an EEPROM. The controller may also be
configured from a microcontroller or an external EEPROM. When using the microcontroller interface, the
USB20H04 appears as an SMBus slave device. The EEPROM interface supports a 2-wire I2C device.
All required resistors on the USB ports are integrated into the USB20H04. This includes all series
termination resistors on D+ and D– pins and all required pull-down and pull-up resistors on D+ and D–
pins. The over-current sense inputs for the downstream facing ports have internal pull-up resistors.
Throughout this document the upstream facing port of the hub will be referred to as the upstream port, and
the four downstream facing ports will be called the downstream ports.
1.1
Applications
The Universal Serial Bus (USB) hub may be used in a number of applications:
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Standalone hubs
Keyboards
Monitors
Motherboard hubs
Docking stations and port replicators
Printers and scanners
External storage devices
Auxiliary battery docks
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1.2
OEM Selectable Features
The 4-Port Hub supports several OEM selectable features:
ƒ
Operation as a bus-powered, self-powered or dynamic-powered hub. (When configured for dynamic
operation, the controller automatically switches to bus-powered mode if a local power source is
unavailable).
ƒ
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Configure downstream facing port power switching on an individual or ganged basis.
Configure downstream facing port over-current sensing on an individual or ganged basis.
Enable downstream facing port LED indicators.
Select multiple or single transaction translator mode.
Select whether the hub is part of a compound device (when any downstream facing port is
permanently hardwired to a USB peripheral device, the hub is part of a compound device).
ƒ
ƒ
ƒ
Select the presence of a permanently hardwired USB peripheral device on a port by port basis.
Enable downstream facing ports a port by port basis.
Enable EOP generation of EOF1 when operating in full-speed mode, as described in Section 11.3.1 of
the USB 2.0 Specification.
ƒ
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Enable USB On-The-Go Session Request Protocol (SRP) support.
Configure the delay time for filtering the over-current sense inputs.
Configure the delay time until port power is good after the SetPortPower command is received.
Indicate the maximum current that the 4-port hub consumes from an upstream port.
Indicate the maximum current required for the hub controller.
1.3
Pin Selectable Options to the Default Configuration
The USB20H04 includes a default configuration for those applications where an external EEPROM or
SMBus device is not available to provide the configuration. This configuration may be adequate in some
applications. A pin selectable feature supports configuration as either a bus-powered hub or a
self-powered hub determined by the logic level of the SELF_PWR pin following reset.
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Chapter 2 Functional Block Diagram
Pin
Selectable
Options
To Upstream
VBUS
Upstream
USB Data
24 MHz
Crystal
To EEPROM or
SMBus Master
SD SCK
Internal
Configuration
Select
Serial
Interface
PLL
Bus-Power
Detect/
VBUS Pulse
Upstream
PHY
SIE
Controller
Repeater
TT
#1
TT
#2
TT
#3
TT
#4
Port
Controller
Routing Logic
Port #1
Port #4
Downstream
PHY #1
OC Sense
Switch Driver
LED Drivers
Downstream
PHY #4
OC Sense
Switch Driver
LED Drivers
Downstream OC Switch/LED
USB Data Sense Drivers
Downstream
USB Data
OC Switch/LED
Sense Drivers
Figure 2.1 - Block Diagram
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Chapter 3 Pinout
48
47
VDDA33
USBDP0
USBDM0
VSS
1
2
TEST_P3
CLKIN_EN
46
45
OCS1_N
3
4
VBUS1_N
OCS2_N
USBDM1
USBDP1
44
43
42
5
6
7
VBUS2_N
VDDA33
USBDP2
VDD18
VSS
USB20H04
8
41
40
39
38
USBDM2
OCS3_N
9
VBUS3_N
VSS
10
USBDM3
OCS4_N
VBUS4_N
CS/EESEL
SCK/SCL
SD/SDA
11
12
13
14
15
16
USBDP3
VDDA33
USBDP4
37
36
35
34
33
USBDM4
VSS
TEST_P2
Figure 3.1– 64 Pin TQFP
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Chapter 4 Interface Signal Definition
4.1
Pin Descriptions
Table 4.1 - System Interface Signals
BUFFER ACTIVE
NAME
DESCRIPTION
TYPE
LEVEL
RESET_N
IS
Low
Chip Reset. The minimum active low pulse is 100ns. See section 8.4 for a
complete description of operation following a reset.
Self-power Detect. Detects availability of local self-power source:
0: Self/local power source is NOT available (i.e., 4- Port Hub gets all power
from Upstream USB VBUS).
SELF_PWR
I
High
1: Self/local power source is available.
TEST_P0
TEST_P1
TEST_P2
TEST_P3
ATEST
IPD
IPD
IPD
IPD
AO
N/A
N/A
N/A
N/A
N/A
Test Pin. Do Not Connect
Test Pin. Do Not Connect
Test Pin. Do Not Connect
Test Pin. Do Not Connect
Test Pin. Do Not Connect
Table 4.2 – Configuration Select and Serial Port Interface
ACTIVE
BUFFER
TYPE
NAME
DESCRIPTION
LEVEL
SMB_SEL_N
I
N/A
SMBus Select. Selects between configuration via the SMBus interface, or
from an external EEPROM or using the internal default, as described in
the table below.
SMB_SEL_N
CS/EE_SEL
SMBus or EEPROM interface
configuration.
0
0
1
1
0
1
0
1
SMBus slave. Address: 0101100
SMBus slave. Address: 0101101
Internal default configuration.
2-wire EEPROM interface.
CS/EE_SEL
IO8
N/A
Chip Select. This multifunction pin is sampled on the rising edge of
RESET_N. If SMB_SEL_N = 1, the internal default configuration will be
used when this pin is low, or the external I2C EEPROM will supply the
configuration when this pin is high. When SMB_SEL_N = 0, this pin
selects the SMBus slave address, as described in the table above.
Connect a 1k ohm resistor in series with the input when connecting this
pin to either VDD or VSS.
SD/SDA
IOSD12
IOSD12
N/A
N/A
Serial Data. Data I/O on the 2-Wire interface.
SCK/SCL
Serial Clock. Clock for the 2-Wire interface.
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Table 4.3 - USB I/O Signals
DESCRIPTION
BUFFER ACTIVE
NAME
TYPE
IO-U
IO-U
IO8
LEVEL
USBDP0
USBDM0
VBUSDET
N/A
Upstream USB Positive Data Pin.
Upstream USB Negative Data Pin.
N/A
N/A
Detects state of upstream VBUS power. When designing a detachable
hub, this pin must be connected to the VBUS power pin of the USB port
that is upstream of the hub.
For self-powered applications with a permanently attached upstream
host, this pin must be connected to either 3.3V or 5.0V (typically
VDD3.3).
The USB20H04 monitors VBUSDET to determine when to assert the
internal D+ pull-up resistor (signaling a connect event). When using the
SRP feature, it is necessary to add a 100k ohm resistor from this pin to
VSS in order to properly dissipate the upstream VBUS Pulse (pulsed with
an 8mA drive capability).
USBDP1
USBDM1
VBUS1_N
OCS1_N
GR1_N
IO-U
IO-U
O8
N/A
N/A
USB Positive Data Pin to downstream port 1.
USB Negative Data Pin to downstream port 1.
Low Enables power to downstream port 1.
IPU
Low Over-Current Sense input. Internal pull-up resistor to 3.3V.
Low Enables green indicator to downstream port 1.
Low Enables amber indicator to downstream port 1.
OD8
OD8
IO-U
IO-U
O8
AM1_N
USBDP2
USBDM2
VBUS2_N
OCS2_N
GR2_N
N/A
N/A
USB Positive Data Pin to downstream port 2.
USB Negative Data Pin to downstream port 2.
Low Enables power to downstream port 2.
IPU
Low Over-Current Sense input. Internal pull-up resistor to 3.3V.
Low Enables green indicator to downstream port 2.
Low Enables amber indicator to downstream port 2.
OD8
OD8
IO-U
IO-U
O8
AM2_N
USBDP3
USBDM3
VBUS3_N
OCS3_N
GR3_N
N/A
N/A
USB Positive Data Pin to downstream port 3.
USB Negative Data Pin to downstream port 3.
Low Enables power to downstream port 3.
IPU
Low Over-Current Sense input. Internal pull-up resistor to 3.3V.
Low Enables green indicator to downstream port 3.
Low Enables amber indicator to downstream port 3.
OD8
OD8
IO-U
IO-U
O8
AM3_N
USBDP4
USBDM4
VBUS4_N
OCS4_N
GR4_N
N/A
N/A
USB Positive Data Pin to downstream port 4.
USB Negative Data Pin to downstream port 4.
Low Enables power to downstream port 4.
IPU
Low Over-Current Sense input. Internal pull-up resistor to 3.3V.
Low Enables green indicator to downstream port 4.
Low Enables amber indicator to downstream port 4.
OD8
OD8
AM4_N
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Table 4.4 - Biasing and Clock Oscillator Signals
DESCRIPTION
BUFFER ACTIVE
NAME
TYPE
LEVEL
RBIAS
I-R
N/A
N/A
External 1% bias resistor. Requires a 12KΩ resistor to ground. Used for
setting HS transmit current level and on-chip termination impedance.
XTAL1/CLKIN
ICLKx
External crystal. 24MHz crystal or external clock input when a crystal is not
used.
Connect a 5M ohm resistor from this pin to XTAL2 when a crystal is used.
XTAL2
OCLKx
I
N/A
External crystal. 24MHz crystal. Not connected when using an external clock.
CLKIN_EN
High Clock Input Enable. When high, an external CMOS clock drives XTAL1.
Table 4.5 - Power and Ground Signals
BUFFER ACTIVE
NAME
DESCRIPTION
3.3V Digital Supply. Powers digital pads.
TYPE
LEVEL
VDD3.3
N/A
N/A
VDD1.8
VSS
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.8V Digital Supply. Powers digital core.
Signal Ground.
VDDA3.3
VDDA1.8
3.3V Analog Supply. Powers analog I/O and 3.3V analog circuitry.
1.8V Analog Supply. Powers 1.8V analog circuitry.
4.2
Buffer Type Descriptions
Table 4.6 – USB20H04 Buffer Type Descriptions
BUFFER
I
DESCRIPTION
Input
IPU
IPD
IS
Input with weak internal pull-up resistor.
Input with weak internal pull-down resistor
Input with Schmitt trigger
IO8
IOSD12
Input/Output with 8mA drive
Open drain with 12mA sink with Schmitt
trigger. Meets I2C-Bus Spec Version 2.1
Output with 8mA drive
Open drain with 8mA sink
XTAL clock input
XTAL clock output
Defined in USB specification
Analog Output
O8
OD8
ICLKx
OCLKx
IO-U
AO
I-R
3.3V Tolerant Analog Pin
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Chapter 5 Limiting Values
Table 5.1 - Absolute Maximum Ratings (In accordance with the Absolute Maximum Rating system (IEC 60134)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
1.8V Supply Voltage
(VDD1.8 and VDDA1.8)
3.3V Supply Voltage
(VDD3.3 and VDDA3.3)
Voltage on any I/O pin
VDD1.8
-0.5
2.5
V
VDD3.3
TSTG
-0.5
4.0
V
-0.3
-0.3
5.5
3.6
V
V
Voltage on XTAL1/CLKIN and
XTAL2
Storage Temperature
-40
+125
oC
Table 5.2 - Recommended Operating Conditions
PARAMETER
1.8V Supply Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
VDD1.8
1.74
1.8
2.0
V
(VDD1.8 and VDDA1.8)
3.3V Supply Voltage
VDD3.3
3.0
3.3
3.6
V
(VDD3.3 and VDDA3.3)
Input Voltage on Digital Pins
VI
0.0
0.0
VDD3.3
VDD3.3
V
V
Input Voltage on Analog I/O
Pins (DP, DM)
VI(I/O)
Ambient Temperature
TA
0
+70
oC
Table 5.3 - Recommended Crystal/External Clock Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Crystal Frequency
24
(+/- 100ppm)
24
MHz
External Clock Frequency
External Clock Duty Cycle
External Clock RMS Jitter
MHz
(+/- 100ppm)
50
XTAL1/CLKIN driven by the
external clock; no connection
at XTAL2; and CLKIN_EN is
high
45
55
%
100
ps
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Chapter 6 Electrical Characteristics
Table 6.1 - Electrical Characteristics: Supply Pins
(VDD1.8 =1.74 to 2.0V; VDD3.3 =3.0 to 3.6V; VSS = 0V; TA = 0 oC to +70oC; unless otherwise specified.)
PARAMETER
SYMBOL
ICC1.8SUS
ICC3.3SUS
ICC1.8FS1
ICC3.3FS1
ICC1.8HS1
ICC3.3HS1
ICC1.8FS2
ICC3.3FS2
ICC1.8HS2
ICC3.3HS2
ICC1.8FS3
ICC3.3FS3
ICC1.8HS3
ICC3.3HS3
ICC1.8FS4
ICC3.3FS4
ICC1.8HS4
ICC3.3HS4
ICC1.8UNC
ICC3.3UNC
ICC1.8CON
ICC3.3CON
CONDITIONS
Suspended
MIN
TYP
100
200
100
55
MAX UNITS
uA
Suspend State
Suspended
uA
1 Port
1 downstream port active
mA
Low-Speed/Full-Speed
mA
1 Port
1 downstream port active
2 downstream ports active
2 downstream ports active
3 downstream ports active
3 downstream ports active
4 downstream ports active
4 downstream ports active
Prior to enumeration
100
75
mA
High-Speed
mA
2 Ports
100
55
mA
Low-Speed/Full-Speed
mA
2 Ports
100
95
mA
High-Speed
mA
3 Ports
100
55
mA
Low-Speed/Full-Speed
mA
3 Ports
105
115
100
55
mA
High-Speed
mA
4 Ports
mA
Low-Speed/Full-Speed
mA
4 Ports
105
135
70
mA
High-Speed
mA
Unconfigured
mA
10
mA
Enumerated State
Upstream port active
Full-Speed/Hi-Speed
70
mA
10
mA
Table 6.2 - DC Electrical Characteristics: Digital Pins
(VDD1.8 =1.74 to 2.0V; VDD3.3 =3.0 to 3.6V; VSS = 0V; TA = 0 oC to +70oC; unless otherwise specified.)
PARAMETER
SYMBOL
COMMENTS
MIN
TYP
MAX UNITS
Refer to Section 4.1 for relationship between buffers and pin names.
IS Input Buffer
Low Input Level
High Input Level
Hysteresis
VILI
VIHI
VHYSI
IIL
TTL Levels
TTL Levels
0.8
V
V
2.0
250
-10
-10
300
350
+10
+10
mV
uA
uA
VIN = 0
Low Input Leakage
High Input Leakage
IIH
VIN = VDD3.3
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PARAMETER
SYMBOL
COMMENTS
MIN
TYP
MAX UNITS
I, IPD, IPU Input Buffer
VILI
VIHI
IIL
TTL Levels
TTL Levels
0.8
V
V
Low Input Level
High Input Level
Low Input Leakage
2.0
-10
-10
VIN = 0
+10
+10
uA
uA
IIH
VIN = VDD3.3
High Input Leakage
ICLK Input Buffer
VILCK
VIHCK
VHYSC
TTL Levels
TTL Levels
0.8
100
0.8
V
V
Low Input Level
High Input Level
Hysteresis
2.0
50
mV
O8 and IO8 Buffer
Low Output Level
High Output Level
Output Leakage
OD8 and IOD8 Buffer
Low Output Level
Output Leakage
IOSD12 Buffer
VOL
VOH
IOL
I
OL = 8 mA @ VDD3.3 = 3.3V
V
V
I
OH = -4mA @ VDD3.3 = 3.3V
2.4
-10
V
IN = 0 to VDD3.3
(Note 6.1)
+10
uA
VOL
IOL
I
OL = 8 mA @ VDD3.3 = 3.3V
0.8
V
V
IN = 0 to VDD3.3
(Note 6.1)
-10
+10
uA
VOL
I
OL = 12 mA @ VDD3.3 = 3.3V
0.8
+10
350
V
Low Output Level
VIN = 0 to VDD3.3
IOL
(Note 6.1)
-10
uA
mV
Output Leakage
Hysteresis
VHYSI
250
300
Note 6.1 - Output Leakage is measured with the current pins in high impedance.
Table 6.3 - Pin Capacitance
PARAMETER
Clock Input Capacitance
Input Capacitance
SYMBOL
CCLKIN
CIN
CONDITIONS
MIN
TYP
MAX UNITS
12
8
pF
pF
pF
All pins – except DPx/DMx pins
All pins – except DPx/DMx pins
Output Capacitance
COUT
12
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Table 6.4 - DC Electrical Characteristics: Analog I/O Pins (DP/DM)
(VDD1.8 =1.74 to 2.0V; VDD3.3 =3.0 to 3.6V; VSS = 0V; TA = 0 oC to +70oC; unless otherwise specified.)
PARAMETER
FS FUNCTIONALITY
Input levels
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Differential Receiver Input
Sensitivity
VDIFS
VCMFS
VILSE
VIHSE
| VI(DP) - VI(DM) |
0.2
0.8
V
Differential Receiver
Common-Mode Voltage
Single-Ended Receiver Low
Level Input Voltage
Single-Ended Receiver High
Level Input Voltage
Output Levels
2.5
0.8
V
V
V
2.0
Low Level Output Voltage
VFSOL
VFSOH
Pull-up resistor on DP;
RL = 1.5kΩ to VDD3.3
Pull-down resistor on DP, DM;
0.3
3.6
V
V
High Level Output Voltage
2.8
RL = 15kΩ to GND
Termination
Driver Output Impedance for
HS and FS
ZHSDRV
Steady state drive
40.5
45
49.5
Ω
Pull-up Resistor Impedance
Termination Voltage For Pull-up
Resistor On Pin DP
ZPU
VTERM
1.425
3.0
1.575
3.6
KΩ
V
HS FUNCTIONALITY
Input levels
HS Differential Input Sensitivity
HS Data Signaling Common
Mode Voltage Range
HS Squelch Detection
Threshold (Differential)
VDIHS
VCMHS
| VI(DP) - VI(DM) |
100
-50
mV
mV
500
100
Squelch Threshold
Unsquelch Threshold
mV
mV
VHSSQ
VHSOL
VHSOH
VOLHS
150
-10
360
-10
700
Output Levels
High Speed Low Level
Output Voltage (DP/DM
referenced to GND)
High Speed High Level
Output Voltage (DP/DM
referenced to GND)
High Speed IDLE Level
Output Voltage (DP/DM
referenced to GND)
Chirp-J Output Voltage
(Differential)
10
440
10
mV
mV
mV
When driven into a precision 45Ω
load
When driven into a precision 45Ω
load
When driven into a precision 45Ω
load
VCHIRPJ
VCHIRPK
HS termination resistor disabled,
pull-up resistor connected.
HS termination resistor disabled, -900
pull-up resistor connected.
1100
-500
mV
mV
Chirp-K Output Voltage
(Differential)
Leakage Current
OFF-State Leakage Current
Port Capacitance
Transceiver Input Capacitance
ILZ
± 1
10
uA
pF
CIN
Pin to GND
5
6.1
Dynamic Characteristics: Analog I/O Pins (DP/DM)
ƒ
Compliant with USB 2.0 Specification. For complete specifications consult the Universal Serial Bus
Specification Revision 2.0.
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Chapter 7 Functional Overview
Figure 2.1 shows the functional block diagram of the USB 2.0 Hub Controller. Each of the functions is
described in detail below.
7.1
Bus-Power Detect
The VBUSDET pin on the USB20H04 monitors the state of the upstream VBUS signal and will not pull-up
the DP0 resistor if VBUS is not active. If VBUS goes from an active to an inactive state (not powered), the
USB20H04 will remove power from the DP0 pull-up resistor within 10 seconds.
To support a dual-role OTG host on the upstream port, the USB20H04 has the ability to pulse the inactive
VBUS line. This is defined as VBUS pulsing in the OTG specification. For a more detailed discussion of the
OTG features of the USB20H04, please see “Application Note 10.4 Using the USB20H04 with an OTG
Host”.
7.2
Upstream PHY
The upstream PHY includes the transmitter and receiver that operate in high-speed or full-speed mode,
depending on the current hub configuration and the host. The required termination resistors are internal to
the USB20H04.
To support a dual-role OTG host on the upstream port, the USB20H04 has the ability to attach a 1.5K ohm
resistor to the DP0 pin for 5 to 10ms. This is defined as data-line pulsing in the OTG specification.
7.3
7.4
Clock/PLL
The USB20H04 requires a 24MHz signal as a reference clock for the internal PLL. An external crystal is
used with the internal oscillator, or an external clock signal can be provided.
Internal Configuration Select
A default configuration for the USB20H04 is present immediately after RESET_N negation. When the
default configuration values will not be used, user defined values must be provided from an external source
via the serial interface. The user defined values to be configured are described in section 8.2.
See Section 8.1 for typical circuit examples showing how to select either the default configuration or an
external EEPROM. The pins used to select the source of configuration values are given in Table 4.2.
The internal default configuration is enabled when SMB_SEL_N is high and CS/EE_SEL is low on the
rising edge of RESET_N. When the SELF_PWR pin is low on the rising edge of RESET_N, the
bus-powered default configuration is loaded. If the SELF_PWR pin is high, the self-powered default
configuration is loaded. This allows the default configuration to be bus-powered or self-powered following a
reset.
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7.5
Serial Interface
External configuration data is loaded via the serial interface. The serial interface appears as either an
SMBus slave, or an I2C memory interface.
7.5.1 SMBus Slave
The USB20H04 conforms to voltage, power, and timing specifications as set forth in the SMBus 1.0
Specification for Slave-Only devices. The SMBus interface shares the same pins as the EEPROM
interface. If the SMB_SEL_N pin is configured to activate the SMBus interface, external EEPROM support
is no longer available and the user-defined configuration values must be downloaded via the SMBus. A
separate Application Note 9.29, "USB20H04 4-Port USB 2.0 Hub Controller - Configuration Programming"
provides details for configuring the USB20H04 via the SMBus.
7.5.2 I2C Memory Interface
A basic I2C-bus interface is provided for reading configuration data from an external EEPROM following a
reset. The USB20H04 acts as the master and generates the serial clock and the START and STOP
conditions.
7.6
Repeater
The hub repeater is responsible for managing connectivity between upstream and downstream facing ports
which are operating at the same speed. The repeater includes both a high-speed repeater function and a
full-/low-speed repeater function. When the upstream port is operating in a high-speed environment, traffic
passes through the high-speed repeater to downstream ports that are operating at high-speed. As detailed
in the USB specification, the repeater is responsible for managing connectivity on a ‘per packet’ basis. It
implements ‘packet signaling’ and ‘resume’ connectivity. If a low-speed device is detected the repeater will
not propagate upstream packets to the corresponding port, unless they are preceded by a PREAMBLE
PID.
7.7
7.8
SIE
Communication with the host is handled by the SIE. The full USB protocol layer is implemented in the SIE,
including Endpoint 0 and Endpoint 1. All standard USB requests from the host are handled by the
hardware without the need for firmware intervention.
Controller
The controller implements protocol handling at a higher level. By responding to SETUP packets it
coordinates enumeration, and it manages suspend/resume operation.
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7.9
Transaction Translator (TT)
The transaction translator supports full-speed and low-speed devices attached to downstream ports in the
high-speed environment. To provide the highest level of performance, the USB20H04 Hub provides one
Transaction Translator (TT) per port (defined as multiple-TT).
7.10 Port Controller
The port controller provides status and control of individual downstream ports. Any port status change is
reported to the host via the hub status change (interrupt) endpoint.
7.11 Downstream PHY
Each of the downstream PHYs include a transmitter and receiver that operate in high-speed, full-speed or
low-speed mode, depending on the attached device. The required termination resistors are internal to the
USB20H04.
7.12 OC Sense/Switch Driver
One output per port is provided to control an external port power switch and one input per port is provided
to sense an external over-current sense. Both ganged and individual (per-port) configurations are
supported. See Figure 10.1 - High Level Block Diagram of a Self-Powered Hub for a typical
implementation.
7.12.1 Over-Current Sense
An external device monitors the current being provided to attached peripherals, and generates an output
during over-current conditions. This output is connected to the OCSx_N input of the USB20H04. This input
pin has an internal pull up resistor.
This input is filtered by the USB20H04 for the amount of time configured in the Over-Current Timer field
(See Table 8.4 - Address 8; Config_Byte_1) If the input continues to be asserted beyond the configured
time, the USB20H04 reports the over-current condition to the host and disables the power switch output
associated with that particular port. For use with typical silicon-based power controllers, configure the timer
to a value greater than zero to avoid glitches when devices are attached.
7.12.2 Switch Driver
Power to downstream ports is controlled by the VBUSx_N (where x stands for the port number) output
connected to an external power switch device. This output may be disabled when an over-current
condition has been reported, as described in Section 7.12.1.
7.13 LED Drivers
As per the specification, each downstream port of the hub supports an optional status indicator. The
USB20H04 provides one output per port for a green LED and one output per port for an amber LED.
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Each port’s indicator must be located in a position that obviously associates the indicator with the port. The
color and state of the LED is used to provide status information to the user.
Two different modes of operation are supported for the port indicators: automatic mode and manual mode.
The USB20H04 defaults to automatic mode upon power-up. In automatic mode, the USB20H04 controls
the color of the indicator LED as described in Table 7.1 - Automatic Mode Port Indicators.
Table 7.1 - Automatic Mode Port Indicators
COLOR
DEFINITION
Off
Disconnected, Disabled, Not
Configured, Resetting, Testing,
Suspending, or Resuming
Amber
Green
Over Current Condition
Enabled, Transmit, or TransmitR
In manual mode, the host controls the color and state of the indicator LED by sending a command to the
USB20H04 to put the LED in a particular state. This is described in Table 7.2 - Manual Mode Port
Indicators.
Table 7.2 - Manual Mode Port Indicators
COLOR
DEFINITION
Not Operational
Off
Amber
Error Condition
Green
Fully Operational
Software Attention
Blinking
Off/Green
Blinking
Off/Amber
Hardware Attention
The USB20H04 can be configured to either support or not support port indicators. If port indicators are not
included in the hub design, disable this feature in the configuration.
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Chapter 8 Implementation Notes
The following sections consist of select functional explanations to aid in implementing the Hub Controller
into a system.
8.1
Configuration Implementations
The USB20H04 is normally configured by an external EEPROM connected directly to the serial interface.
Typical circuit diagrams are shown below. For a more detailed discussion of the serial interface, including
Port USB 2.0 Hub Controller, Configuration Programming". The Application Note also discusses designing
a Hub system that supports In Circuit Programming of the EEPROM.
8.1.1 Interfacing a 2-wire Serial EEPROM
The I2C EEPROM interface is designed to attach to a single “dedicated” I2C EEPROM. It conforms to the
Standard-mode I2C Specification (100kbit/s transfer rate and 7-bit addressing) for protocol and electrical
compatibility. The circuit board designer is required to place external pull-up resistors (10K ohm
recommended) on the SDA & SCL lines (per SMBus 1.0 Specification, and EEPROM manufacturer
guidelines) to VDD in order to assure proper operation.
Figure 8.1 - 2-Wire EEPROM Interface
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8.1.2 Internal Default Configuration
The internal default configuration is enabled when SMB_SEL_N is high and CS/EE_SEL is low on the
rising edge of RESET_N. If SELF_PWR is low, then the bus-powered default settings are loaded.
VDD3.3
USB20H04
Bus/Self
SMB_SEL_N
CS/EE_SEL
SELF_PWR
SCK/SCL
SD/SDA
PowerSelect
0=Bus-Power
1=Self-Power
1k
Figure 8.2 - Internal Default Mode
8.2
EEPROM Programming Values
Configuration data is loaded from an external EEPROM following reset. The values to be programmed into
the EEPROM are summarized in Table 8.1 - Summary of OEM Value Programming.
Table 8.1 - Summary of OEM Value Programming
ADDRESS
FIELD NAME
VID (MSB)
DESCRIPTION
Vendor ID (assigned by USB-IF).
0
1
VID (LSB)
2
PID (MSB)
Product ID (assigned by Manufacturer).
Device ID (assigned by Manufacturer).
3
PID (LSB)
4
DID (MSB)
5
DID (LSB)
6
Config_Byte_3
Config_Byte_2
Config_Byte_1
Max_Power
Configuration options defined in Table 8.2.
Configuration options defined in Table 8.3.
Configuration options defined in Table 8.4.
Maximum current for this configuration, see Table 8.5.
Maximum current for the USB20H04, see Table 8.5.
Time until power is stable, see Table 8.5.
7
8
9
10
11
HubContrCurrent
PwrOn2PwrGood
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Detailed definition of the bits used to program the OEM values are given in Table 8.2 through Table 8.5.
Table 8.2 - Address 6; Config_Byte_3
BIT
FIELD NAME
DESCRIPTION
Selects either self-powered or bus-powered operation:
0: Self-powered operation.
7
Self-/Bus-Power
1: Bus-powered operation.
6
5
4
3
Port Indicators
Selects implementation of port indicators:
0: No port indicators.
1: Port indicators implemented.
High-Speed
Disable
Selects whether high-speed operation is disabled:
0: High-/Full-Speed operation.
1: Full-Speed only (High-Speed disabled).
Multiple TT Support Selects whether multiple transaction translators are available:
0: Single TT for all ports.
1: Each port has one TT available (multiple TTs supported).
EOP Disable
Current Sensing
Power Switching
Selects whether EOP generation of EOF1 is disabled when in
Full-Speed mode:
0: EOP generation at EOF1.
1: EOP generation at EOF1 disabled.
2
1
0
Selects whether current sensing is ganged on all ports, or on an
individual port-by-port basis:
0: Individual port-by-port.
1: Ganged sensing.
Selects whether downstream port power switching is ganged on all
ports, or on an individual port-by-port basis:
0: Individual port-by-port.
1: Ganged switching.
Compound Device Selects whether the hub is part of a compound device:
0: Not a compound device.
1: Yes, USB20H04 is part of a compound device.
Table 8.3 - Address 7; Config_Byte_2
The ports may be individually configured to be inactive. However, the order in which ports are set to
inactive is very specific. Port 4 must be the first port configured to be inactive, followed by port 3.
BIT
FIELD NAME
DESCRIPTION
7:4
Non-Removable
Device
Selects which ports include non-removable devices. A one
indicates that the port is non-removable:
Bit 7: Port 4 is non-removable.
Bit 6: Port 3 is non-removable.
Bit 5: Port 2 is non-removable.
Bit 4: Port 1 is non-removable.
All zeroes sets all ports removable.
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BIT
FIELD NAME
DESCRIPTION
3:0
Port Non-Active
Selects which ports are active. A one indicates that the port is
non-active:
Bit 3: Port 4 is non-active.
Bit 2: Port 3 is non-active.
Bit 1: Port 2 is non-active.
Bit 0: Port 1 is non-active.
All zeroes sets all ports active.
Note: Active ports must be contiguous, and must start with port
number 1.
Table 8.4 - Address 8; Config_Byte_1
FIELD NAME DESCRIPTION
BIT
7
Dynamic Power
Selects the ability to transition to bus-powered operation if the local
power source is removed:
0: No dynamic auto-switching.
1: Dynamic auto-switching ability enabled.
Selects the ability to support an OTG host:
0: No OTG support.
6
On-The-Go
Reserved
1: OTG support enabled.
5:4
3:0
Set to zero.
Over-Current Timer Selects the over-current timer delay in 2 ms increments for the
active ports.
0101: delay is 2ms
1010: delay is 4ms
1111: delay is 6ms
Note: All other values are reserved
Table 8.5 - Addresses 9 - 11
BIT
FIELD NAME
DESCRIPTION
7:0
Max Power
Current in 2mA increments that the 4-port hub consumes from an
upstream port in this configuration.
A value of 50, or 32(h), indicates 100 mA.
7:0
7:0
HubContrCurrent
PwrOn2PwrGood
Absolute maximum current requirement in 2mA increments of the
hub controller electronics.
A value of 50, or 32(h), indicates 100 mA.
Time in 2ms intervals from the time the power on sequence begins
on a port until power is good on that port.
A value of 50, or 32(h), indicates 100 ms.
8.3
Default Configuration Values
Default values for configuration data are loaded as described in section 8.1.2 and 8.1.3 above. The values
programmed are summarized in Table 8.6 - Default Configuration Values.
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Table 8.6 - Default Configuration Values
SELF-POWERED
DEFAULT (HEX)
BUS-POWERED
DEFAULT (HEX)
REGISTER
ADDRESS
REGISTER NAME
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
VID MSB
VID LSB
04
24
**
04
24
**
PID MSB
PID LSB
00
00
00
58
00
05
00
00
80
00
00
00
98
08
05
64
64
80
DID MSB
DID LSB
Config Data Byte 3
Config Data Byte 2
Config Data Byte 1
Max Power
Hub Controller Max Current
Power-on Time
** The default PID value is dependent on the silicon revision.
8.4
Reset
There are two different resets that the USB20H04 will experience. One is a hardware reset (via the
RESET_N pin) and the second a USB Reset.
8.4.1 External Hardware Reset
A valid hardware reset is initiated by the assertion of RESET_N for a minimum of 100ns after all power
supplies are within operating range.
Assertion of RESET_N (external pin) causes the following:
1. All downstream ports are disabled, and VBUS power to downstream devices is removed.
2. The PHYs are disabled, and the differential pairs will be in a high-impedance state
3. All transactions immediately terminate, and no states are saved.
4. All internal registers return to the default state (in most cases, 00(h)).
5. LED indicators are disabled
After RESET_N is negated, the USB20H04 is ready to be configured as an SMBus slave (if SMB_SEL_N
= 0) or it reads OEM specific data from the external EEPROM (if SMB_SEL_N = 1). Default values for
configuration data are loaded if the SELF ONLY default strapping option is selected, or if an EEPROM is
not present. The timing associated with these options is shown in the tables below.
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8.4.1.1 SMBus Configuration Timing
SCK/SCL
t3
t1
t2
t4
RESET_N
GND
First External
SCK/SCL
Activity
Configuration
Finished
Hub Function
Enable
Hardware
Reset Asserted
CS/EE_SEL
& SMB_SEL_N
strapping
options read
Figure 8.3 - Timing for Configuration from SMBus
Table 8.7 - Time Values to Configure from SMBus
NAME
T1
DESCRIPTION
RESET_N asserted
MIN
100
16
TYP
MAX
UNITS
nsec
nsec
T2
USB20H04 recovery/stabilization – until first
external SCK/SCL activity
32
T3
T4
Implementation dependent load time
Configuration finished to Hub enabled
35
70
nsec
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8.4.1.2 EEPROM Configuration Timing
SCK/SCL
t2
t3
t1
t4
RESET_N
GND
Configuration
Finished
First Clock
Rising Edge
Hub Function
Enable
Hardware
Reset Asserted
CS/EE_SEL
& SMB_SEL_N
strapping
options read
Figure 8.4 - Timing to Complete Configuration from EEPROM
Table 8.8 - Time Values to Configure From EEPROM
NAME
T1
DESCRIPTION
RESET_N asserted
MIN
TYP
MAX
UNITS
nsec
100
T2
(I2C) USB20H04 recovery/stabilization – until
first rising edge of SCK/SCL
24
8
30
10
70
μsec
T3
T4
(I2C) EEPROM configuration to final
SCK/SCL activity
msec
nsec
Configuration finished to Hub enabled
35
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8.4.2 USB Reset
When the upstream host signals a reset, the USB20H04 does the following:
Note:
The USB20H04 does not propagate the upstream USB Reset to downstream devices!
1. Sets default address to 0
2. Sets configuration to: un-configured
3. Negates VBUSx_N (where x stands for the port number) to all downstream ports.
4. Clears all TT buffers.
5. Moves device from suspended to active (if suspended).
6. Complies with Section 11.10 of the USB 2.0 specification for behavior after completion of the reset
sequence.
The host then configures the hub, and the hub’s downstream port devices, in accordance with the USB
specification.
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Chapter 9 Hub Descriptors
The USB20H04 will not electrically attach to the USB until after it has loaded valid data for all user-defined
descriptor fields. A default configuration is present immediately after RESET_N negation. User defined
configuration values can be loaded from either an external microcontroller or an external EEPROM.
A hub returns different descriptors based on whether it is operating at high-speed or full-/low-speed. A hub
can report three different sets of the descriptors: one descriptor set for full-/low-speed operation and two
sets for high-speed operation. The descriptors reported by the USB20H04 are summarized in the following
tables. The host retrieves this information by using the GetDescriptor request with the corresponding
descriptor type values.
Table 9.1 - Device Descriptor
FULL
SPEED
12h
01h
0200h
09h
00h
00h
40h
user
user
user
00h
00h
00h
01h
HIGH
SPEED
12h
01h
0200h
09h
00h
01h*
40h
user
user
user
00h
00h
00h
01h
OFFSET
FIELD NAME
DESCRIPTION
0
1
2,3
4
5
6
bLength
bDescriptorType
bcdUSB
bDeviceClass
bDeviceSubClass
bDeviceProtcol
bMaxPacketSize0
idVendor
idProduct
bcdDevice
iManufacturer
iProduct
iSerialNumber
Size of this descriptor in bytes
DEVICE Descriptor Type
USB Specification Number
Class code assigned by USB-IF for Hubs
Class code assigned by USB-IF for Hubs
Protocol code assigned by the USB-IF
64-byte packet size
Vendor ID; OEM value
Product ID; OEM value
Device ID; OEM value
7
8,9
10,11
12,13
14
15
16
17
This optional string is not supported.
This optional string is not supported.
This optional string is not supported.
iNumConfigurations Supports 1 configuration
* 02h for multiple-TT
Table 9.2 - Device Qualifier Descriptor
FULL
HIGH
SPEED
OFFSET
FIELD NAME
DESCRIPTION
SPEED
0Ah
06h
0
1
2
3
4
5
0Ah
06h
00h
02h
09h
00h
bLength
bDescriptorType
bcdUSB
Size of this descriptor in bytes
DEVICE Qualifier Type
00h
USB Specification Version Number (LSB)
USB Specification Version Number (MSB)
Class code assigned by USB-IF for Hubs
Class code assigned by USB-IF for Hubs
Protocol code.
02h
bcdUSB
09h
bDeviceClass
bDeviceSubClass
00h
6
00h
01h*
bDeviceProtcol
7
8
9
40h
01h
00h
40h
01h
00h
bMaxPacketSize0
64-byte packet size for other speed
bNumConfigurations Supports 1 other speed configuration
bReserved
Reserved
* 02h for multiple-TT
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Table 9.3 - Standard Configuration Descriptor
FULL
SPEED SPEED
HIGH
OFFSET
FIELD NAME
DESCRIPTION
0
1
09h
02h
09h
02h
bLength
Size of this descriptor in bytes
bDescriptorType
CONFIGURATION Descriptor Type
Total length of data returned for this
configuration
2,3
yyyyh
yyyyh
wTotalLength
yyyyh = 0019h if OTG support is disabled.
yyyyh = 001Ch if OTG support is enabled.
Number of interfaces supported by this
configuration
4
5
01h
01h
01h
01h
bNumInterfaces
Value to use as an argument to the
SetConfiguration() request to select this
configuration.
bConfigurationValue
Index of string descriptor describing this
configuration (string not supported)
6
7
00h
00h
iConfiguration
bmAttibutes
The following values are derived from the OEM
value:
user/
user/
= A0h for Bus-Powered.
= E0h for Self-Powered.
All other values are reserved.
signal
(Bitmap) (Bitmap)
signal
If Dynamic Power support is disabled, this value
is derived from the OEM value for MaxPower
consumed from the bus by the hub in this
configuration.
If Dynamic Power support is enabled, the
USB20H04 must be configured for a
bus-powered configuration only, and the
following values are reported for this field:
user
(mA)
user
(mA)
8
bMaxPower
SELF_PWR = 0, OEM value reported.
SELF_PWR = 1, 02h (small upstream load for
Self-Powered configuration).
Table 9.4 - Other_Speed_Configuration Descriptor
FULL
SPEED SPEED
HIGH
OFFSET
FIELD NAME
DESCRIPTION
0
1
09h
07h
09h
07h
bLength
Size of this descriptor in bytes
bDescriptorType
Other-Speed Configuration Descriptor Type
Total length of data returned for this
configuration
zzzz = 0019h if single TT and OTG disabled.
zzzz = 001Ch if single TT and OTG enabled.
zzzz = 0029h if multi-TT and OTG disabled.
zzzz = 002Fh if multi-TT and OTG enabled.
2,3
yyyyh*
zzzzh
wTotalLength
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FULL
SPEED SPEED
HIGH
OFFSET
FIELD NAME
DESCRIPTION
Number of interfaces supported by this
configuration
4
5
01h
01h
01h**
01h
bNumInterfaces
bConfigurationValue
Value to use to select configuration.
Index of string descriptor describing this
configuration (string not supported)
6
00h
00h
iConfiguration
user/
user/
7
8
bmAttibutes
bMaxPower
Same as Configuration Descriptor
Same as Configuration Descriptor
signal
(Bitmap) (Bitmap)
signal
user
(mA)
user
(mA)
* Same as Configuration Descriptor
** 02h for multiple-TT
Table 9.5 - Standard Interface Descriptor
FULL
SPEED SPEED
HIGH
OFFSET
FIELD NAME
DESCRIPTION
0
1
2
09h
04h
00h
09h
04h
00h
bLength
Size of this descriptor in bytes
INTERFACE Descriptor Type
Number of this interface
bDescriptorType
bInterfaceNumber
Value used to select this alternate setting for the
interface
3
4
00h
01h
00h
01h
bAlternateSetting
Number of endpoints used by this interface (not
including endpoint 0)
bNumEndpoints
bInterfaceClass
5
6
7
09h
00h
00h
09h
00h
Class code assigned by USB for Hubs
bInterfaceSubClass Subclass code assigned by USB
01h*
bInterfaceProtcol
Protocol code assigned by USB
Index of string descriptor describing this
configuration (string not supported)
8
00h
00h
bInterface
* 02h for multiple-TT
Table 9.6 - Standard Endpoint Descriptor
FULL
SPEED SPEED
HIGH
OFFSET
FIELD NAME
DESCRIPTION
0
1
2
07h
05h
81h
07h
05h
81h
bLength
Size of this descriptor in bytes
bDescriptorType
bEndpointAddress
ENDPOINT Descriptor Type
The address of the endpoint on the USB device.
Describes the endpoint's attributes (interrupt
only, no synchronization, data endpoint).
3
03h
03h
bmAttributes
4,5
6
0001h
FFh
0001h
0Ch
wMaxPacketSize
bInterval
Maximum packet size for this endpoint
Interval for polling endpoint for data transfers.
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Table 9.7 - Interface Descriptor (present if multiple-TT)
HIGH
SPEED
OFFSET
FIELD NAME
DESCRIPTION
0
1
2
09h
04h
00h
bLength
Size of this descriptor in bytes
INTERFACE Descriptor Type
Number of this interface
bDescriptorType
bInterfaceNumber
Value used to select this alternate setting for
the interface
3
4
01h
01h
bAlternateSetting
Number of endpoints used by this interface (not
including endpoint 0)
bNumEndpoints
bInterfaceClass
5
6
7
09h
00h
02h
Class code assigned by USB for Hubs
bInterfaceSubClass Subclass code assigned by USB
bInterfaceProtcol
Protocol code assigned by USB
Index of string descriptor describing this
configuration (string not supported)
8
00h
bInterface
Table 9.8 - On-The-GO (OTG) Descriptor
FULL
SPEED
OFFSET
HIGH SPEED
FIELD NAME
DESCRIPTION
0
1
03h
09h
03h
09h
bLength
Size of this descriptor in bytes
OTG Descriptor Type
Attribute Fields:
bDescriptorType
D[7:2] = Reserved
2
01h
01h
wMaxPacketSize
D1: HNP Support (not supported)
D0: SRP Support.
Table 9.9 - Class-Specific Hub Descriptor (Full-Speed and High-Speed)
OFFSET
FIELD NAME
Length
VALUE
09h
DESCRIPTION
Size of this Descriptor.
0
1
2
Descriptor Type
NbrPorts
29h
Hub Descriptor Type.
user
Number of downstream facing ports this Hub
supports. Derived from OEM value defined in
EEPROM or SMBus load. See Section 11.23.2.1 in
the USB Specification.
Note: If Dynamic Power is enabled, and the
SELF_PWR pin is low (indicating Bus Power
Operation), then ports 3 & 4 are not available and
either a value of 1 is reported if the OEM value is 1
or a value of 2 is reported if the OEM value is 2, 3
or 4.
3,4
5
HubCharacteristics
PwrOn2PwrGood
user
user
Defines several characteristics that are derived
from OEM values. Also defines TT Think Time
(fixed at a value of 00b for 8FS bit times max).
Time (in 2 ms intervals) from the time the power-on
sequence begins on a port until power is good on
that port. Derived from OEM value.
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OFFSET
FIELD NAME
VALUE
DESCRIPTION
6
HubContrCurrent
user
Maximum current requirements of the hub
controller electronics in mA. Derived from OEM
value.
7
8
DeviceRemovable
PortPwrCtrlMask
user
FFh
Indicates if port has a removable device attached.
Derived from OEM value.
Field for backwards USB 1.0 compatibility.
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Chapter 10 Application Diagrams
The highly-integrated USB20H04 Hub Controller is complemented with a minimal number of external
components to create a complete four-port Hi-Speed USB hub application. Figure 10.1 illustrates one
possible hardware configuration, but is not a complete schematic. This block diagram shows a
self-powered hub with individual over-current protection and power switching on each downstream port.
Four
Downstream
USB20H04
Ports
Dual
Voltage
Regulator
5V
Self-Power
5V
Self-Power
VBUS
D+
USBDP1
USBDM1
VBUS1_N
OCS1_N
GR1_N
3.3V
1.8V
D-
OUT1
IN
GND
OUT2
GR
AM
Quad
Power
Switch
XTAL1
XTAL2
AM1_N
USBDP2
USBDM2
VBUS2_N
OCS2_N
GR2_N
Upstream
Port
VBUS
D+
IN
D-
VBUS
D+
VBUSDET
USBDP0
USBDM0
GND
EN1
OC1
EN2
OC2
EN3
OC3
EN4
OC4
OUT1
D-
AM2_N
OUT2
OUT3
OUT4
GR
AM
USBDP3
USBDM3
VBUS3_N
OCS3_N
GR3_N
VBUS
D+
Serial
EEPROM
D-
AM3_N
GND
USBDP4
USBDM4
VBUS4_N
OCS4_N
GR4_N
SCLK
SD
SCK/SCL
SD/SDA
GR
AM
AM4_N
VBUS
D+
D-
GND
GR
AM
Figure 10.1 - High Level Block Diagram of a Self-Powered Hub
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Downstream VBUS
Power Source
USB Type A
Connector
Power Switch
OC Sense
USB20H04
IN
OUT
(Port 1)
VBUS
EN
OC
VBUS1_N
VDD3.3
D+
D-
OCS1_N
USBDP1
USBDM1
AM1_N
Amber Indicator
Green Indicator
GR1_N
Figure 10.2 - USB Downstream Port Connection
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Chapter 11 Package Outline
Figure 11.1 - 64 Pin TQFP Package Outline, 10 x 10 x 1.4 Body, 2 MM Footprint
Table 11.1 - 64 Pin TQFP Package Parameters
MIN
~
NOMINAL
MAX
1.60
0.15
1.45
12.20
10.20
12.20
10.20
0.20
0.75
~
REMARKS
Overall Package Height
Standoff
~
~
~
~
~
~
~
~
A
A1
A2
D
D1
E
E1
H
L
0.05
1.35
11.80
9.80
11.80
9.80
0.09
0.45
~
Body Thickness
X Span
X body Size
Y Span
Y body Size
Lead Frame Thickness
Lead Foot Length
Lead Length
0.60
1.00
0.50 Basic
L1
e
Lead Pitch
Lead Foot Angle
Lead Width
0o
0.17
0.08
0.08
~
~
0.22
~
~
~
7o
0.27
~
0.20
0.08
θ
W
R1
R2
ccc
Lead Shoulder Radius
Lead Foot Radius
Coplanarity
Notes:
1. Controlling Unit: millimeter.
2. Tolerance on the true position of the leads is ± 0.04 mm maximum.
3. Package body dimensions D1 and E1 do not include the mold protrusion.
Maximum mold protrusion is 0.25 mm per side.
4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane.
5. Details of pin 1 identifier are optional but must be located within the zone indicated.
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