Samsung Microscope Magnifier C8249 User Guide
24-S3-C8245/P8245/C8249/P8249-032004  
USER'S MANUAL  
S3C8245/P8245/C8249/P8249  
8-Bit CMOS  
Microcontrollers  
Revision 4  
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REVISION DESCRIPTIONS  
1. DEVICE TYPE  
The S3C8247/C8248 device type should be moved. Product name and document name should be changed into  
'S3C8245/P8245/C8249/P8249'.  
2. FEATURES  
The Operating Temperature Range should be changed '-40°C to 85°C' into '-25°C to 85°C' in the page 1-2, from 19-2  
to 19-12, and from 21-4 to 21-7.  
3. ELECTRICAL DATA  
Table 19-2. D.C. Electrical Characteristics (Concluded) (Page 19-4)  
°
°
(T = -25 C to + 85 C, V = 1.8 V to 5.5 V)  
A
DD  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
(1)  
I
Main stop mode: sub-osc  
–
1
3
mA  
Supply current  
DD5  
stop V = 5 V ± 10 %,  
DD  
°
T = 25 C  
A
°
0.5  
2
V
= 3V ± 10%, T = 25 C  
DD  
A
Table 19-12. D.C. Electrical Characteristics (Concluded) (Page 19-12)  
°
°
(T = -25 C to + 85 C, V = 2.0 V to 5.5 V)  
A
DD  
Oscillator  
Test Condition  
= 2.0 V to 5.5 V  
Min  
Typ  
Max  
Unit  
Crystal  
V
–
–
40  
4
ms  
ms  
DD  
Ceramic  
Stabilization occurs when V is equal to the minimum  
–
–
DD  
oscillator voltage range.  
External clock  
X input high and low level width (t , t  
)
50  
–
500  
ns  
IN  
XH XL  
Table 21-4. D.C. Electrical Characteristics (Continued) (Page 19-3, 21-5)  
°
°
(T = -25 C to +85 C, V = 1.8 V to 5.5 V)  
A
DD  
Parameter  
Symbol  
Conditions  
= 5.0 V T = 25 C  
Min  
300  
Typ  
600  
Max  
1500  
Unit  
°
Oscillator feed back  
resistors  
R
kW  
V
osc1  
A
DD  
X = V , X  
= 0 V  
IN  
DD OUT  
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S3C8245/P8245  
/C8249/P8249  
8-BIT CMOS  
MICROCONTROLLERS  
USER'S MANUAL  
Revision 4  
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Important Notice  
The information in this publication has been carefully  
checked and is believed to be entirely accurate at the  
time of publication. Samsung assumes no  
responsibility, however, for possible errors or  
omissions, or for any consequences resulting from  
the use of the information contained herein.  
"Typical" parameters can and do vary in different  
applications. All operating parameters, including  
"Typicals" must be validated for each customer  
application by the customer's technical experts.  
Samsung products are not designed, intended, or  
authorized for use as components in systems  
intended for surgical implant into the body, for other  
applications intended to support or sustain life, or for  
any other application in which the failure of the  
Samsung product could create a situation where  
personal injury or death may occur.  
Samsung reserves the right to make changes in its  
products or product specifications with the intent to  
improve function or design at any time and without  
notice and is not required to update this  
documentation to reflect such changes.  
This publication does not convey to a purchaser of  
semiconductor devices described herein any license  
under the patent rights of Samsung or others.  
Should the Buyer purchase or use a Samsung  
product for any such unintended or unauthorized  
application, the Buyer shall indemnify and hold  
Samsung and its officers, employees, subsidiaries,  
affiliates, and distributors harmless against all claims,  
costs, damages, expenses, and reasonable attorney  
fees arising out of, either directly or indirectly, any  
claim of personal injury or death that may be  
associated with such unintended or unauthorized use,  
even if such claim alleges that Samsung was  
negligent regarding the design or manufacture of said  
product.  
Samsung makes no warranty, representation, or  
guarantee regarding the suitability of its products for  
any particular purpose, nor does Samsung assume  
any liability arising out of the application or use of any  
product or circuit and specifically disclaims any and  
all liability, including without limitation any  
consequential or incidental damages.  
S3C8245/P8245/C8249/P8249 8-Bit CMOS Microcontrollers  
User's Manual, Revision 4  
Publication Number: 24-S3-C8245/P8245/C8249/P8249-032004  
© 2004 Samsung Electronics  
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any  
form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written  
consent of Samsung Electronics.  
Samsung Electronics' microcontroller business has been awarded full ISO-14001  
certification (BSI Certificate No. FM24653). All semiconductor products are  
designed and manufactured in accordance with the highest quality standards and  
objectives.  
Samsung Electronics Co., Ltd.  
San #24 Nongseo-Ri, Giheung- Eup  
Yongin-City, Gyeonggi-Do, Korea  
C.P.O. Box #37, Suwon 449-900  
TEL: (82)-(031)-209-1934  
FAX: (82)-(331)-209-1889  
Home-Page URL: Http://www.samsungsemi.com  
Printed in the Republic of Korea  
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Preface  
The S3C8245/P8245/C8249/P8249 Microcontroller User's Manual is designed for application designers and  
programmers who are using the S3C8245/P8245/C8249/P8249 microcontroller for application development. It is  
organized in two main parts:  
Part I Programming Model  
Part II Hardware Descriptions  
Part I contains software-related information to familiarize you with the microcontroller's architecture, programming  
model, instruction set, and interrupt structure. It has six chapters:  
Chapter 1  
Chapter 2  
Chapter 3  
Product Overview  
Address Spaces  
Addressing Modes  
Chapter 4  
Chapter 5  
Chapter 6  
Control Registers  
Interrupt Structure  
Instruction Set  
Chapter 1, "Product Overview," is a high-level introduction to S3C8245/P8245/C8249/P8249 with general product  
descriptions, as well as detailed information about individual pin characteristics and pin circuit types.  
Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register  
addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined stack  
operations.  
Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the  
S3C8-series CPU.  
Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register values,  
as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read, alphabetically  
organized, register descriptions as a quick-reference source when writing programs.  
Chapter 5, "Interrupt Structure," describes the S3C8245/P8245/C8249/P8249 interrupt structure in detail and further  
prepares you for additional information presented in the individual hardware module descriptions in Part II.  
Chapter 6, "Instruction Set," describes the features and conventions of the instruction set used for all S3C8-series  
microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of each  
instruction are presented in a standard format. Each instruction description includes one or more practical examples  
of how to use the instruction when writing an application program.  
A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in Part  
II. If you are not yet familiar with the S3C8-series microcontroller family and are reading this manual for the first time,  
we recommend that you first read Chapters 1–3 carefully. Then, briefly look over the detailed information in Chapters  
4, 5, and 6. Later, you can reference the information in Part I as necessary.  
Part II "hardware Descriptions," has detailed information about specific hardware components of the  
S3C8245/P8245/C8249/P8249 microcontroller. Also included in Part II are electrical, mechanical, OTP, and  
development tools data. It has 16 chapters:  
Chapter 7  
Chapter 8  
Chapter 9  
Chapter 10  
Chapter 11  
Chapter 12  
Chapter 13  
Chapter 14  
Clock Circuit  
nRESET and Power-Down  
I/O Ports  
Chapter 15  
Chapter 16  
Chapter 17  
Chapter 18  
Chapter 19  
Chapter 20  
Chapter 21  
Chapter 22  
10-bit-to-Digital Converter  
Serial I/O Interface  
Voltage Booster  
Voltage Level Detector  
Electrical Data  
Mechanical Data  
S3P8245/P8249 OTP  
Development Tools  
Basic Timer  
8-bit Timer A/B  
16-bit Timer 0/1  
Watch Timer  
LCD Controller/Driver  
Two order forms are included at the back of this manual to facilitate customer order for S3C8245/P8245/  
C8249/P8249 microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can  
photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.  
S3C8245/P8245/C8249/P8249 MICROCONTROLLER  
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Table of Contents  
Part I — Programming Model  
Chapter 1  
Product Overview  
S3C8-Series Microcontrollers ...............................................................................................................1-1  
S3C8245/P8245/C8249/P8249 Microcontroller .......................................................................................1-1  
OTP ...................................................................................................................................................1-1  
Features.............................................................................................................................................1-2  
Block Diagram ....................................................................................................................................1-3  
Pin Assignment...................................................................................................................................1-4  
Pin Descriptions..................................................................................................................................1-6  
Pin Circuits.........................................................................................................................................1-7  
Chapter 2  
Address Spaces  
Overview.............................................................................................................................................2-1  
Program Memory (ROM)......................................................................................................................2-2  
Register Architecture...........................................................................................................................2-3  
Register Page Pointer (PP)..........................................................................................................2-5  
Register Set 1.............................................................................................................................2-6  
Register Set 2.............................................................................................................................2-6  
Prime Register Space..................................................................................................................2-7  
Working Registers.......................................................................................................................2-8  
Using the Register Points.............................................................................................................2-9  
Register Addressing ............................................................................................................................2-11  
Common Working Register Area (C0H–CFH) .................................................................................2-13  
4-bit Working Register Addressing................................................................................................2-14  
8-bit Working Register Addressing................................................................................................2-16  
System and User Stacks.....................................................................................................................2-18  
Chapter 3  
Addressing Modes  
Overview.............................................................................................................................................3-1  
Register Addressing Mode (R)..............................................................................................................3-2  
Indirect Register Addressing Mode (IR)..................................................................................................3-3  
Indexed Addressing Mode (X) ...............................................................................................................3-7  
Direct Address Mode (DA)....................................................................................................................3-10  
Indirect Address Mode (IA)...................................................................................................................3-12  
Relative Address Mode (RA).................................................................................................................3-13  
Immediate Mode (IM)...........................................................................................................................3-14  
S3C8245/P8245/C8249/P8249 MICROCONTROLLER  
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Table of Contents (Continued)  
Chapter 4  
Control Registers  
Overview.............................................................................................................................................4-1  
Chapter 5  
Interrupt Structure  
Overview.............................................................................................................................................5-1  
Interrupt Types ............................................................................................................................5-2  
S3C8245/C8249 Interrupt Structure...............................................................................................5-3  
Interrupt Vector Addresses...........................................................................................................5-4  
Enable/Disable Interrupt Instructions (EI, DI) ..................................................................................5-6  
System-Level Interrupt Control Registers .......................................................................................5-6  
Interrupt Processing Control Points...............................................................................................5-7  
Peripheral Interrupt Control Registers ............................................................................................5-8  
System Mode Register (SYM)......................................................................................................5-9  
Interrupt Mask Register (IMR).......................................................................................................5-10  
Interrupt Priority Register (IPR) .....................................................................................................5-11  
Interrupt Request Register (IRQ) ...................................................................................................5-13  
Interrupt Pending Function Types..................................................................................................5-14  
Interrupt Source Polling Sequence................................................................................................5-15  
Interrupt Service Routines.............................................................................................................5-15  
Generating Interrupt Vector Addresses ..........................................................................................5-16  
Nesting Of Vectored Interrupts......................................................................................................5-16  
Instruction Pointer (IP).................................................................................................................5-16  
Fast Interrupt Processing.............................................................................................................5-16  
Chapter 6  
Instruction Set  
Overview.............................................................................................................................................6-1  
Data Types .................................................................................................................................6-1  
Register Addressing ....................................................................................................................6-1  
Addressing Modes.......................................................................................................................6-1  
Flags Register (Flags)..................................................................................................................6-6  
Flag Descriptions ........................................................................................................................6-7  
Instruction Set Notation................................................................................................................6-8  
Condition Codes..........................................................................................................................6-12  
Instruction Descriptions................................................................................................................6-13  
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Table of Contents (Continued)  
Part II Hardware Descriptions  
Chapter 7  
Clock Circuit  
Overview.............................................................................................................................................7-1  
System Clock Circuit...................................................................................................................7-1  
Clock Status During Power-Down Modes.......................................................................................7-2  
System Clock Control Register (CLKCON).....................................................................................7-3  
Chapter 8  
nRESET and Power-Down  
System nRESET.................................................................................................................................8-1  
Overview.....................................................................................................................................8-1  
Normal Mode Reset Operation......................................................................................................8-1  
Hardware Reset Values................................................................................................................8-2  
Power-Down Modes.............................................................................................................................8-5  
Stop Mode..................................................................................................................................8-5  
Idle Mode....................................................................................................................................8-6  
Chapter 9  
I/O Ports  
Overview.............................................................................................................................................9-1  
Port Data Registers .....................................................................................................................9-2  
Port 0.........................................................................................................................................9-3  
Port 1.........................................................................................................................................9-6  
Port 2.........................................................................................................................................9-8  
Port 3.........................................................................................................................................9-10  
Port 4.........................................................................................................................................9-12  
Port 5.........................................................................................................................................9-14  
Chapter 10  
Basic Timer  
Overview.............................................................................................................................................10-1  
Basic Timer (BT) .............................................................................................................................10-1  
Basic Timer Control Register (BTCON)..............................................................................................10-1  
Basic Timer Function Description......................................................................................................10-3  
S3C8245/P8245/C8249/P8249 MICROCONTROLLER  
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Table of Contents (Continued)  
Chapter 11  
8-bit Timer A/B  
8-Bit Timer A.......................................................................................................................................11-1  
Overview.....................................................................................................................................11-1  
Function Description....................................................................................................................11-2  
Timer A Control Register (TACON)................................................................................................11-3  
Block Diagram ............................................................................................................................11-4  
8-Bit Timer B.......................................................................................................................................11-5  
Overview.....................................................................................................................................11-5  
Timer B Pulse Width Calculations.................................................................................................11-7  
Chapter 12  
16-bit Timer 0/1  
16-Bit Timer 0.....................................................................................................................................12-1  
Overview.....................................................................................................................................12-1  
Function Description....................................................................................................................12-1  
Timer 0 Control Register (T0CON).................................................................................................12-2  
Block Diagram ............................................................................................................................12-3  
16-Bit Timer 1.....................................................................................................................................12-5  
Overview.....................................................................................................................................12-5  
Function Description....................................................................................................................12-6  
Timer 1 Control Register (T1CON).................................................................................................12-7  
Block Diagram ............................................................................................................................12-8  
Chapter 13  
Watch Timer  
Overview.............................................................................................................................................13-1  
Watch Timer Control Register (WTCON: R/W)...............................................................................13-2  
Watch Timer Circuit Diagram........................................................................................................13-3  
Chapter 14  
LCD Controller/Driver  
Overview.............................................................................................................................................14-1  
LCD Circuit Diagram....................................................................................................................14-2  
LCD RAM Address Area ..............................................................................................................14-3  
LCD Control Register (LCON), D0H...............................................................................................14-4  
LCD Mode Register (LMOD).........................................................................................................14-5  
LCD Drive Voltage .......................................................................................................................14-7  
LCD SEG/SEG Signals................................................................................................................14-7  
LCD Voltage Driving Method.........................................................................................................14-12  
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S3C8245/P8245/C8249/P8249 MICROCONTROLLER  
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Table of Contents (Continued)  
10-bit Analog-to-Digital Converter  
Chapter 15  
Overview.............................................................................................................................................15-1  
Function Description............................................................................................................................15-1  
Conversion Timing .......................................................................................................................15-2  
A/D Converter Control Register (ADCON).......................................................................................15-2  
Internal Reference Voltage Levels..................................................................................................15-3  
Block Diagram ....................................................................................................................................15-4  
Chapter 16  
Serial I/O Interface  
Overview.............................................................................................................................................16-1  
Programming Procedure...............................................................................................................16-1  
SIO Control Register (SIOCON) ....................................................................................................16-2  
SIO Pre-Scaler Register (SIOPS)..................................................................................................16-3  
Block Diagram ....................................................................................................................................16-3  
Serial I/O Timing Diagram.............................................................................................................16-4  
Chapter 17  
Voltage Booster  
Overview.............................................................................................................................................17-1  
Function Description............................................................................................................................17-1  
Block Diagram ....................................................................................................................................17-2  
Chapter 18  
Voltage Level Detector  
Overview.............................................................................................................................................18-1  
Voltage Level Detector Control Register (VLDCON).........................................................................18-2  
S3C8245/P8245/C8249/P8249 MICROCONTROLLER  
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Table of Contents (Concluded)  
Chapter 19  
Electrical Data  
Overview.............................................................................................................................................19-1  
Chapter 20  
Mechanical Data  
Overview.............................................................................................................................................20-1  
Chapter 21  
S3P8245/P8249 OTP  
Overview.............................................................................................................................................21-1  
Operating Mode Characteristics....................................................................................................21-4  
Chapter 22  
Development Tools  
Overview.............................................................................................................................................22-1  
SHINE........................................................................................................................................22-1  
SAMA Assembler........................................................................................................................22-1  
SASM88.....................................................................................................................................22-1  
HEX2ROM..................................................................................................................................22-1  
Target Boards .............................................................................................................................22-1  
TB8245/8249 Target Board...........................................................................................................22-3  
SMDS2+ Selection (SAM8)..........................................................................................................22-5  
IDLE LED...................................................................................................................................22-5  
STOP LED..................................................................................................................................22-5  
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List of Figures  
Figure  
Title  
Page  
Number  
Number  
1-1  
1-2  
1-3  
1-4  
1-5  
1-6  
1-7  
1-8  
1-9  
1-10  
S3C8245/C8249 Block Diagram............................................................................1-3  
S3C8245/C8249 Pin Assignment (80-QFP-1420C)..................................................1-4  
S3C8245/C8249 Pin Assignment (80-TQFP-1212)..................................................1-5  
Pin Circuit Type B (nRESET)................................................................................1-8  
Pin Circuit Type C...............................................................................................1-8  
Pin Circuit Type D-2 (P3)......................................................................................1-8  
Pin Circuit Type D-4 (P0)......................................................................................1-8  
Pin Circuit Type E-2 (P1)......................................................................................1-9  
Pin Circuit Type F-10 (P2.0–P2.6).........................................................................1-9  
Pin Circuit Type F-18 (P2.7/VLD ) .....................................................................1-9  
REF  
1-11  
1-12  
1-13  
Pin Circuit Type H (SEG/COM).............................................................................1-9  
Pin Circuit Type H-4.............................................................................................1-10  
Pin Circuit Type H-14 (P4, P5)..............................................................................1-10  
2-1  
2-2  
2-3  
2-4  
2-5  
2-6  
2-7  
2-8  
Program Memory Address Space.........................................................................2-2  
Internal Register File Organization.........................................................................2-4  
Register Page Pointer (PP)..................................................................................2-5  
Set 1, Set 2, Prime Area Register, and LCD Data Register Map ..............................2-7  
8-Byte Working Register Areas (Slices).................................................................2-8  
Contiguous 16-Byte Working Register Block..........................................................2-9  
Non-Contiguous 16-Byte Working Register Block...................................................2-10  
16-Bit Register Pair .............................................................................................2-11  
Register File Addressing......................................................................................2-12  
Common Working Register Area...........................................................................2-13  
4-Bit Working Register Addressing........................................................................2-15  
4-Bit Working Register Addressing Example..........................................................2-15  
8-Bit Working Register Addressing........................................................................2-16  
8-Bit Working Register Addressing Example..........................................................2-17  
Stack Operations ................................................................................................2-18  
2-9  
2-10  
2-11  
2-12  
2-13  
2-14  
2-15  
3-1  
3-2  
3-3  
3-4  
3-5  
3-6  
3-7  
3-8  
Register Addressing ............................................................................................3-2  
Working Register Addressing ...............................................................................3-2  
Indirect Register Addressing to Register File..........................................................3-3  
Indirect Register Addressing to Program Memory ...................................................3-4  
Indirect Working Register Addressing to Register File.............................................3-5  
Indirect Working Register Addressing to Program or Data Memory...........................3-6  
Indexed Addressing to Register File......................................................................3-7  
Indexed Addressing to Program or Data Memory with Short Offset...........................3-8  
Indexed Addressing to Program or Data Memory....................................................3-9  
Direct Addressing for Load Instructions..................................................................3-10  
Direct Addressing for Call and Jump Instructions ....................................................3-11  
Indirect Addressing..............................................................................................3-12  
Relative Addressing.............................................................................................3-13  
Immediate Addressing .........................................................................................3-14  
3-9  
3-10  
3-11  
3-12  
3-13  
3-14  
4-1  
Register Description Format .................................................................................4-4  
S3C8245/P8245/C8249/P8249 MICROCONTROLLER  
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List of Figures (Continued)  
Figure  
Title  
Page  
Number  
Number  
5-1  
5-2  
5-3  
5-4  
5-5  
5-6  
5-7  
5-8  
5-9  
S3C8-Series Interrupt Types.................................................................................5-2  
S3C8245/C8249 Interrupt Structure.......................................................................5-3  
ROM Vector Address Area...................................................................................5-4  
Interrupt Function Diagram ...................................................................................5-7  
System Mode Register (SYM)..............................................................................5-9  
Interrupt Mask Register (IMR)...............................................................................5-10  
Interrupt Request Priority Groups ..........................................................................5-11  
Interrupt Priority Register (IPR) .............................................................................5-12  
Interrupt Request Register (IRQ) ...........................................................................5-13  
6-1  
System Flags Register (FLAGS)...........................................................................6-6  
7-1  
7-2  
7-3  
7-4  
7-5  
7-6  
Main Oscillator Circuit (Crystal or Ceramic Oscillator).............................................7-1  
Main Oscillator Circuit (RC Oscillator) ...................................................................7-1  
System Clock Circuit Diagram..............................................................................7-2  
System Clock Control Register (CLKCON).............................................................7-3  
Oscillator Control Register (OSCCON)...................................................................7-4  
STOP Control Register (STPCON) ........................................................................7-4  
9-1  
9-2  
9-3  
9-4  
9-5  
9-6  
9-7  
9-8  
Port 0 High-Byte Control Register (P0CONH).........................................................9-4  
Port 0 Low-Byte Control Register (P0CONL) ..........................................................9-4  
Port 0 Interrupt Control Register (P0INT) ................................................................9-5  
Port 0 Interrupt Pending Register (P0PND).............................................................9-5  
Port 1 High-Byte Control Register (P1CONH).........................................................9-6  
Port 1 Low-Byte Control Register (P1CONL) ..........................................................9-7  
Port 1 Pull-up Control Register (P1PUP)................................................................9-7  
Port 2 High-Byte Control Register (P2CONH).........................................................9-8  
Port 2 Low-Byte Control Register (P2CONL) ..........................................................9-9  
Port 3 High-Byte Control Register (P3CONH).........................................................9-10  
Port 3 Low-Byte Control Register (P3CONL) ..........................................................9-11  
Port 4 High-Byte Control Register (P4CONH).........................................................9-12  
Port 4 Low-Byte Control Register (P4CONL) ..........................................................9-13  
Port 5 High-Byte Control Register (P5CONH).........................................................9-14  
Port 5 Low-Byte Control Register (P5CONL) ..........................................................9-15  
9-9  
9-10  
9-11  
9-12  
9-13  
9-14  
9-15  
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List of Figures (Continued)  
Page  
Title  
Page  
Number  
Number  
10-1  
10-2  
Basic Timer Control Register (BTCON)..................................................................10-2  
Basic Timer Block Diagram..................................................................................10-4  
11-1  
11-2  
11-3  
11-4  
11-5  
11-6  
Timer A Control Register (TACON)........................................................................11-3  
Timer A Functional Block Diagram........................................................................11-4  
Timer B Functional Block Diagram........................................................................11-5  
Timer B Control Register (TBCON)........................................................................11-6  
Timer B Data Register (TBDATAH/L).....................................................................11-6  
Timer B Output Flip-Flop Waveforms in Repeat Mode .............................................11-8  
12-1  
12-2  
12-3  
12-4  
12-5  
12-6  
12-7  
12-8  
Timer 0 Control Register (T0CON).........................................................................12-2  
Timer 0 Functional Block Diagram.........................................................................12-3  
Timer 0 Counter Register (T0CNTH/L)....................................................................12-4  
Timer 0 Data Register (T0DATAH/L)......................................................................12-4  
Timer 1 Control Register (T1CON).........................................................................12-7  
Timer 1 Functional Block Diagram.........................................................................12-8  
Timer 1Counter Register (T1CNTH/L).....................................................................12-9  
Timer 1 Data Register (T1DATAH/L)......................................................................12-9  
13-1  
Watch Timer Circuit Diagram................................................................................13-3  
14-1  
14-2  
14-3  
14-4  
14-5  
14-6  
14-7  
14-8  
14-9  
14-10  
LCD Function Diagram.........................................................................................14-1  
LCD Circuit Diagram............................................................................................14-2  
LCD Display Data RAM Organization ....................................................................14-3  
Select/No-Select Bias Signals in Static Display Mode............................................14-7  
Select/No-Select Bias Signals in 1/2 Duty, 1/2 Bias Display Mode ..........................14-8  
Select/No-Select Bias Signals in 1/3 Duty, 1/3 Bias Display Mode ..........................14-8  
LCD Signal and Wave Forms Example in 1/2 Duty, 1/2 Bias Display Mode...............14-9  
LCD Signals and Wave Forms Example in 1/3 Duty, 1/3 Bias Display Mode.............14-10  
LCD Signals and Wave Forms Example in 1/4 Duty, 1/3 Bias Display Mode.............14-11  
Voltage Dividing Resistor Circuit Diagram ..............................................................14-12  
15-1  
15-2  
15-3  
15-4  
A/D Converter Control Register (ADCON)...............................................................15-2  
A/D Converter Data Register (ADDATAH/L)............................................................15-3  
A/D Converter Functional Block Diagram ...............................................................15-4  
Recommended A/D Converter Circuit for Highest Absolute Accuracy........................15-5  
16-1  
16-2  
16-3  
16-4  
16-5  
Serial I/O Module Control Registers (SIOCON).......................................................16-2  
SIO Pre-scale Registers (SIOPS)..........................................................................16-3  
SIO Functional Block Diagram..............................................................................16-3  
Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0).................16-4  
Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1) .................16-4  
S3C8245/P8245/C8249/P8249 MICROCONTROLLER  
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List of Figures (Concluded)  
Page  
Title  
Page  
Number  
Number  
17-1  
17-2  
Voltage Booster Block Diagram............................................................................17-2  
Pin Connection Example......................................................................................17-2  
18-1  
18-2  
Block Diagram for Voltage Level Detect.................................................................18-1  
Voltage Level Detect Circuit and Control Register...................................................18-2  
19-1  
19-2  
19-3  
19-4  
19-5  
19-6  
19-7  
Input Timing for External Interrupts (Ports 0)...........................................................19-6  
Input Timing for nRESET......................................................................................19-6  
Stop Mode Release Timing Initiated by nRESET....................................................19-7  
Stop Mode(main) Release Timing Initiated by Interrupts ..........................................19-8  
Stop Mode(sub) Release Timing Initiated by Interrupts............................................19-8  
Serial Data Transfer Timing...................................................................................19-11  
Clock Timing Measurement at X .........................................................................19-13  
IN  
19-8  
Operating Voltage Range .....................................................................................19-14  
20-1  
20-2  
Package Dimensions(80-QFP-1420C) ...................................................................20-1  
Package Dimensions(80-TQFP-1212)....................................................................20-2  
21-1  
21-2  
S3P8245/P8249 Pin Assignments (80-QFP Package) ............................................21-2  
Operating Voltage Range .....................................................................................21-7  
22-1  
22-2  
22-3  
22-4  
SMDS Product Configuration (SMDS2+)................................................................22-2  
TB8245/9 Target Board Configuration.....................................................................22-3  
40-Pin Connectors (J101, J102) for TB8245/9.........................................................22-6  
S3E8240 Cables for 80-QFP Package...................................................................22-6  
xiv  
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List of Tables  
Table  
Title  
Page  
Number  
Number  
1-1  
S3C8245/C8249 Pin Descriptions .........................................................................1-5  
2-1  
2-2  
S3C8249/P8249 Register Type Summary ..............................................................2-3  
S3C8245/P8245 Register Type Summary ..............................................................2-3  
4-1  
4-2  
4-3  
Set 1 Registers ...................................................................................................4-1  
Set 1, Bank 0 Registers.......................................................................................4-2  
Set 1, Bank 1 Registers.......................................................................................4-3  
5-1  
5-2  
5-3  
Interrupt Vectors..................................................................................................5-5  
Interrupt Control Register Overview........................................................................5-6  
Interrupt Source Control and Data Registers...........................................................5-8  
6-1  
6-2  
6-3  
6-4  
6-5  
6-6  
Instruction Group Summary..................................................................................6-2  
Flag Notation Conventions....................................................................................6-8  
Instruction Set Symbols.......................................................................................6-8  
Instruction Notation Conventions ...........................................................................6-9  
Opcode Quick Reference.....................................................................................6-10  
Condition Codes..................................................................................................6-12  
8-1  
8-2  
8-3  
S3C8245/C8249 Set 1 Register and Values after nRESET......................................8-2  
S3C8245/C8249 Set 1, Bank 0 Register Values after nRESET................................8-3  
S3C8245/C8249 Set 1, Bank 1 Register Values after nRESET................................8-4  
9-1  
9-2  
S3C8245/C8249 Port Configuration Overview..........................................................9-1  
Port Data Register Summary................................................................................9-2  
13-1  
Watch Timer Control Register (WTCON): Set 1, Bank 1, FAH, R/W.........................13-2  
14-1  
14-2  
14-3  
14-4  
14-5  
14-6  
LCD Control Register (LCON) Organization............................................................14-4  
Relationship of LCON.0 and LMOD.3 Bit Settings...................................................14-4  
LCD Clock Signal (LCDCK) Frame Frequency........................................................14-5  
LCD Mode Control Register (LMOD) Organization, D1H ..........................................14-6  
Maximum Number of Display Digits per Duty Cycle................................................14-6  
LCD Drive Voltage Values ....................................................................................14-7  
S3C8245/P8245/C8249/P8249 MICROCONTROLLER  
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List of Tables (Continued)  
Table  
Title  
Page  
Number  
Number  
18-1  
VLDCON Value and Detection Level......................................................................18-2  
19-1  
19-2  
19-3  
19-4  
19-5  
19-6  
19-7  
19-8  
19-9  
19-10  
19-11  
Absolute Maximum Ratings..................................................................................19-2  
D.C. Electrical Characteristics..............................................................................19-2  
D.C Electrical Characteristics of S3C8245.............................................................19-5  
A.C. Electrical Characteristics..............................................................................19-6  
Input/Output Capacitance.....................................................................................19-7  
Data Retention Supply Voltage in Stop Mode.........................................................19-7  
A/D Converter Electrical Characteristics ................................................................19-9  
Voltage Booster Electrical Characteristics.............................................................19-10  
Characteristics of Voltage Level Detect Circuit .......................................................19-10  
Synchronous SIO Electrical Characteristics...........................................................19-11  
Main Oscillator Frequency (f  
).........................................................................19-12  
OSC1  
19-12  
19-13  
19-14  
Main Oscillator Clock Stabilization Time (t  
).......................................................19-12  
ST1  
Sub Oscillator Frequency (f  
)..........................................................................19-13  
OSC2  
Sub Oscillator(crystal) Stabilization Time (t  
)......................................................19-14  
ST2  
21-1  
21-2  
21-3  
21-4  
21-5  
Descriptions of Pins Used to Read/Write the EPROM.............................................21-3  
Comparison of S3P8245/P8249 and S3C8245/C8249 Features................................21-3  
Operating Mode Selection Criteria.........................................................................21-4  
D.C Electrical Characteristics...............................................................................21-4  
D.C Electrical Characteristics of S3C8245.............................................................21-7  
22-1  
22-2  
22-3  
22-4  
Power Selection Settings for TB8245/9..................................................................22-4  
Main-clock Selection Settings for TB8245/9...........................................................22-4  
Device Selection Settings for TB8245/9 .................................................................22-5  
The SMDS2+ Tool Selection Setting .....................................................................22-5  
xvi  
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List of Programming Tips  
Description  
Chapter 2:  
Page  
Number  
Address Spaces  
Using the Page Pointer for RAM clear (Page 0, Page1).......................................................................2-5  
Setting the Register Pointers............................................................................................................2-9  
Using the RPs to Calculate the Sum of a Series of Registers ..............................................................2-10  
Addressing the Common Working Register Area................................................................................2-14  
Standard Stack Operations Using PUSH and POP.............................................................................2-19  
Chapter 11:  
8-bit Timer A/B  
To Generate 38 kHz, 1/3 duty signal through P3.0..............................................................................11-9  
To Generate a one pulse signal through P3.0.....................................................................................11-10  
S3C8245/P8245/C8249/P8249 MICROCONTROLLER  
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List of Register Descriptions  
Register  
Identifier  
Full Register Name  
Page  
Number  
ADCON  
BTCON  
CLKCON  
EMT  
A/D Converter Control Register .............................................................................4-5  
Basic Timer Control Register................................................................................4-6  
System Clock Control Register.............................................................................4-7  
External Memory Timing Register .........................................................................4-8  
System Flags Register ........................................................................................4-9  
Interrupt Mask Register........................................................................................4-10  
Interrupt Pending Register....................................................................................4-11  
Instruction Pointer (High Byte) .............................................................................4-12  
Instruction Pointer (Low Byte) ..............................................................................4-12  
Interrupt Priority Register......................................................................................4-13  
Interrupt Request Register....................................................................................4-14  
LCD Control Register...........................................................................................4-15  
LCD Mode Control Register..................................................................................4-16  
Oscillator Control Register....................................................................................4-17  
Port 0 Control Register (High Byte) .......................................................................4-18  
Port 0 Control Register (Low Byte)........................................................................4-19  
Port 0 Interrupt Control Register............................................................................4-20  
Port 0 Interrupt Pending Register ..........................................................................4-22  
Port 1 Control Register (High Byte) .......................................................................4-22  
Port 1 Control Register (Low Byte)........................................................................4-23  
Port 1 Pull-up Control Register..............................................................................4-24  
Port 2 Control Register (High Byte) .......................................................................4-25  
Port 2 Control Register (Low Byte)........................................................................4-26  
Port 3 Control Register (High Byte) .......................................................................4-27  
Port 3 Control Register (Low Byte)........................................................................4-28  
Port 4 Control Register (High Byte) .......................................................................4-29  
Port 4 Control Register (Low Byte)........................................................................4-30  
Port 5 Control Register (High Byte) .......................................................................4-31  
Port 5 Control Register (Low Byte)........................................................................4-32  
FLAGS  
IMR  
INTPND  
IPH  
IPL  
IPR  
IRQ  
LCON  
LMOD  
OSCCON  
P0CONH  
P0CONL  
P0INT  
P0PND  
P1CONH  
P1CONL  
P1PUR  
P2CONH  
P2CONL  
P3CONH  
P3CONL  
P4CONH  
P4CONL  
P5CONH  
P5CONL  
S3C8245/P8245/C8249/P8249 MICROCONTROLLER  
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List of Register Descriptions (Continued)  
Register  
Identifier  
Full Register Name  
Page  
Number  
PP  
Register Page Pointer..........................................................................................4-33  
Register Pointer 0................................................................................................4-34  
Register Pointer 1................................................................................................4-34  
SIO Control Register............................................................................................4-35  
Stack Pointer (High Byte).....................................................................................4-36  
Stack Pointer (Low Byte) .....................................................................................4-36  
Stop Control Register...........................................................................................4-37  
System Mode Register ........................................................................................4-38  
Timer 0 Control Register.......................................................................................4-39  
Timer 1 Control Register.......................................................................................4-40  
Timer A Control Register......................................................................................4-41  
Timer B Control Register......................................................................................4-42  
Voltage Level Detector Control Register.................................................................4-43  
Watch Timer Control Register...............................................................................4-44  
RP0  
RP1  
SIOCON  
SPH  
SPL  
STPCON  
SYM  
T0CON  
T1CON  
TACON  
TBCON  
VLDCON  
WTCON  
xx  
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List of Instruction Descriptions  
Instruction  
Mnemonic  
Full Register Name  
Page  
Number  
ADC  
ADD  
AND  
BAND  
BCP  
BITC  
BITR  
BITS  
BOR  
BTJRF  
BTJRT  
BXOR  
CALL  
CCF  
CLR  
COM  
CP  
Add with Carry ....................................................................................................6-14  
Add....................................................................................................................6-15  
Logical AND........................................................................................................6-16  
Bit AND..............................................................................................................6-17  
Bit Compare........................................................................................................6-18  
Bit Complement ..................................................................................................6-19  
Bit Reset ............................................................................................................6-20  
Bit Set................................................................................................................6-21  
Bit OR................................................................................................................6-22  
Bit Test, Jump Relative on False...........................................................................6-23  
Bit Test, Jump Relative on True.............................................................................6-24  
Bit XOR..............................................................................................................6-25  
Call Procedure ....................................................................................................6-26  
Complement Carry Flag .......................................................................................6-27  
Clear..................................................................................................................6-28  
Complement .......................................................................................................6-29  
Compare.............................................................................................................6-30  
Compare, Increment, and Jump on Equal...............................................................6-31  
Compare, Increment, and Jump on Non-Equal........................................................6-32  
Decimal Adjust....................................................................................................6-33  
Decrement..........................................................................................................6-35  
Decrement Word.................................................................................................6-36  
Disable Interrupts ................................................................................................6-37  
Divide (Unsigned).................................................................................................6-38  
Decrement and Jump if Non-Zero ..........................................................................6-39  
Enable Interrupts.................................................................................................6-40  
Enter..................................................................................................................6-41  
Exit....................................................................................................................6-42  
Idle Operation......................................................................................................6-43  
Increment ...........................................................................................................6-44  
Increment Word...................................................................................................6-45  
Interrupt Return ...................................................................................................6-46  
Jump..................................................................................................................6-47  
Jump Relative......................................................................................................6-48  
Load...................................................................................................................6-49  
Load Bit..............................................................................................................6-51  
CPIJE  
CPIJNE  
DA  
DEC  
DECW  
DI  
DIV  
DJNZ  
EI  
ENTER  
EXIT  
IDLE  
INC  
INCW  
IRET  
JP  
JR  
LD  
LDB  
S3C8245/P8245/C8249/P8249 MICROCONTROLLER  
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List of Instruction Descriptions(Continued)  
Instruction  
Mnemonic  
Full Register Name  
Page  
Number  
LDC/LDE  
LDCD/LDED  
LDCI/LDEI  
LDCPD/LDEPD  
LDCPI/LDEPI  
LDW  
Load Memory......................................................................................................6-52  
Load Memory and Decrement...............................................................................6-54  
Load Memory and Increment ................................................................................6-55  
Load Memory with Pre-Decrement ........................................................................6-56  
Load Memory with Pre-Increment..........................................................................6-57  
Load Word..........................................................................................................6-58  
Multiply (Unsigned)..............................................................................................6-59  
Next...................................................................................................................6-60  
No Operation.......................................................................................................6-61  
Logical OR..........................................................................................................6-62  
Pop from Stack...................................................................................................6-63  
Pop User Stack (Decrementing)............................................................................6-64  
Pop User Stack (Incrementing).............................................................................6-65  
Push to Stack.....................................................................................................6-66  
Push User Stack (Decrementing)..........................................................................6-67  
Push User Stack (Incrementing) ...........................................................................6-68  
Reset Carry Flag.................................................................................................6-69  
Return................................................................................................................6-70  
Rotate Left..........................................................................................................6-71  
Rotate Left through Carry .....................................................................................6-72  
Rotate Right........................................................................................................6-73  
Rotate Right through Carry ...................................................................................6-74  
Select Bank 0.....................................................................................................6-75  
Select Bank 1.....................................................................................................6-76  
Subtract with Carry..............................................................................................6-77  
Set Carry Flag.....................................................................................................6-78  
Shift Right Arithmetic...........................................................................................6-79  
Set Register Pointer ............................................................................................6-80  
Stop Operation....................................................................................................6-81  
Subtract .............................................................................................................6-82  
Swap Nibbles......................................................................................................6-83  
Test Complement under Mask..............................................................................6-84  
Test under Mask .................................................................................................6-85  
Wait for Interrupt..................................................................................................6-86  
Logical Exclusive OR...........................................................................................6-87  
MULT  
NEXT  
NOP  
OR  
POP  
POPUD  
POPUI  
PUSH  
PUSHUD  
PUSHUI  
RCF  
RET  
RL  
RLC  
RR  
RRC  
SB0  
SB1  
SBC  
SCF  
SRA  
SRP/SRP0/SRP1  
STOP  
SUB  
SWAP  
TCM  
TM  
WFI  
XOR  
S3C8245/P8245/C8249/P8249 MICROCONTROLLER  
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S3C8245/P8245/C8249/P8249  
PRODUCT OVERVIEW  
1
PRODUCT OVERVIEW  
S3C8-SERIES MICROCONTROLLERS  
Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of  
integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are:  
— Efficient register-oriented architecture  
— Selectable CPU clock sources  
— Idle and Stop power-down mode release by interrupt  
— Built-in basic timer with watchdog function  
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt  
sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to specific  
interrupt levels.  
S3C8245/P8245/C8249/P8249 MICROCONTROLLER  
The S3C8245/P8245/C8249/P8249 single-chip CMOS  
microcontroller are fabricated using the highly  
advanced CMOS process, based on Samsung’s  
newest CPU architecture.  
— Six programmable I/O ports, including five 8-bit  
ports and one 5-bit port, for a total of 45 pins.  
— Eight bit-programmable pins for external  
interrupts.  
The S3C8245, S3C8249 are a microcontroller with a  
16K-byte, 32K-byte mask-programmable ROM  
embedded respectively.  
— One 8-bit basic timer for oscillation stabilization  
and watchdog functions (system reset).  
— Two 8-bit timer/counter and two 16-bit  
timer/counter with selectable operating modes.  
The S3P8245 is a microcontroller with a 16K-byte  
one-time-programmable ROM embedded.  
The S3P8249 is a microcontroller with a 32K-byte  
one-time-programmable ROM embedded.  
— Watch timer for real time.  
— 8-input A/D converter  
— Serial I/O interface  
Using a proven modular design approach, Samsung  
engineers have successfully developed the  
S3C8245/P8245/C8249/P8249 by integrating the  
following peripheral modules with the powerful SAM8  
core:  
The S3C8245/P8245/C8249/P8249 is versatile  
microcontroller for camera, LCD and ADC application,  
etc. They are currently available in 80-pin TQFP and  
80-pin QFP package  
OTP  
The S3P8245/P8249 are OTP (One Time Programmable) version of the S3C8245/C8249 microcontroller. The  
S3P8245 microcontroller has an on-chip 16K-byte one-time-programmable EPROM instead of a masked ROM. The  
S3P8249 microcontroller has an on-chip 32K-byte one-time-programmable EPROM instead of a masked ROM. The  
S3P8245 is comparable to the S3P8245, both in function and in pin configuration.  
The S3P8249 is comparable to the S3P8249, both in function and in pin configuration.  
1-1  
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PRODUCT OVERVIEW  
S3C8245/P8245/C8249/P8249  
FEATURES  
Memory  
45 I/O Pins  
•
•
•
•
•
ROM: 32K-byte (S3C8249/P8249)  
ROM: 16K-byte (S3C8245/P8245)  
RAM: 1056-Byte (S3C8249/P8249)  
RAM: 544-Byte (S3C8245/P8245)  
Data memory mapped I/O  
•
45 configurable I/O pins  
Basic Timer  
•
•
Overflow signal makes a system reset.  
Watchdog function  
8-Bit Timer/Counter A  
Oscillation Sources  
•
•
•
Programmable 8-bit timer  
•
•
•
Crystal, ceramic, RC (main)  
Interval, capture, PWM mode  
Crystal for subsystem clock  
Match/capture, overflow interrupt  
Main system clock frequency 1-10 MHz  
(3 MHz at 1.8 V, 10 MHz at 2.7 V)  
Subsystem clock frequency: 32.768 kHz  
CPU clock divider (1/1, 1/2, 1/8, 1/16)  
8-Bit Timer/Counter B  
•
•
Programmable 8-bit timer  
Carrier frequency generator  
•
•
16-Bit Timer/Counter 0  
Two Power-Down Modes  
•
•
Programmable 16-bit timer  
Match interrupt generates  
•
•
Idle (only CPU clock stops)  
Stop (System clock stops)  
16-Bit Timer/Counter 1  
Interrupts  
•
•
6 level 8 vector 8 internal interrupt  
2 level 8 vector 8 external interrupt  
•
•
•
Programmable 16-bit timer  
Interval, capture, PWM mode  
Match/capture, overflow interrupt  
Watch Timer  
Voltage Detector  
•
•
•
Real-time and interval time measurement  
•
Programmable detection voltage  
(2.2 V, 2.4 V, 3.0 V, 4.0 V)  
Clock generation for LCD  
•
En/Disable S/W selectable  
Four frequency outputs for buzzer sound  
Instruction Execution Times  
LCD Controller/Driver  
•
•
400 ns at 10 MHz (main)  
•
•
•
Maximum 16-digit LCD direct drive capability  
Display modes: static, 1/2 duty (1/2 bias)  
1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)  
122 us at 32.768 kHz (subsystem)  
Operating Temperature Range  
-25 °C to 85 °C  
Operating Voltage Range  
1.8 V to 5.5 V  
Package Type  
A/D Converter  
•
•
•
Eight analog input channels  
50 ms conversion speed at 1 MHz f  
clock  
ADC  
•
•
10-bit conversion resolution  
8-Bit Serial I/O Interface  
•
•
80-QFP-1420C  
80-TQFP-1212  
•
•
•
•
8-bit transmit/receive mode  
8-bit receive mode  
LSB-first/MSB-first transmission selectable  
Internal/external clock source  
Voltage Booster  
•
•
•
LCD display voltage supply  
S/W control en/disable  
3.0 V drive  
1-2  
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S3C8245/P8245/C8249/P8249  
PRODUCT OVERVIEW  
BLOCK DIAGRAM  
XIN XTIN  
nRESET  
BUZ/P1.4  
TAOUT/TAPWM/P3.1  
TACLK/P3.2  
XOUT XTOUT  
8-Bit  
Timer/  
Counter A  
Voltage  
VVLDREF/  
TACAP/P3.3  
Detector  
P2.7/ADC7  
8-Bit  
Timer/  
Counter B  
OSC/  
nRESET  
Basic  
Timer  
Watch  
Timer  
TBPWM/P3.0  
CB  
CA  
Voltage  
Booster  
16-Bit  
Timer/  
Counter 0  
VLC0-VLC2  
COM0-COM3  
SEG0-SEG15  
T1CAP/P1.0  
T1CLK/P1.1  
T1OUT/T1PWM/P1.2  
LCD  
Driver  
16-Bit  
Timer/  
Counter 1  
I/O Port and Interrupt Control  
SEG16-SEG23/  
P4.0-P4.7  
SEG24-SEG31/  
P5.0-P5.7  
P0.0-P0.7/  
INT0-INT7  
I/O Port 0  
I/O Port 1  
P1.0-P1.7  
SAM88 RC CPU  
SI/P1.7  
Serial I/O  
Port  
SO/P1.5  
SCK/P1.6  
AVREF  
AVSS  
A/D  
Converter  
P4.0-P4.7/  
SEG16-SEG23  
I/O Port 4  
I/O Port 5  
P2.0-P2.7/  
ADC0-ADC7  
544/1056 Byte  
Register File  
16/32-Kbyte  
ROM  
I/O Port 2  
I/O Port 3  
P5.0-P5.7/  
SEG24-SEG31  
P3.0-P3.4  
Figure 1-1. Block Diagram  
1-3  
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PRODUCT OVERVIEW  
S3C8245/P8245/C8249/P8249  
PIN ASSIGNMENT  
SEG26/P5.2  
1
2
3
4
5
6
7
8
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
SEG9  
SEG8  
SEG7  
SEG6  
SEG5  
SEG4  
SEG3  
SEG2  
SEG27/P5.3  
SEG28/P5.4  
SEG29/P5.5  
SEG30/P5.6  
SEG31/P5.7  
P3.0/TBPWM  
P3.1/TAOUT/TAPWM  
P3.2/TACLK  
P3.3/TACAP/SDAT  
P3.4/SCLK  
VDD  
9
SEG1  
SEG0  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
COM3  
COM2  
COM1  
COM0  
VLC2  
VLC1  
VLC0  
CA  
CB  
S3C8245/C8249  
VSS  
XOUT  
XIN  
TEST  
(80-QFP-1420C)  
XTIN  
XTOUT  
nRESET  
P0.0/INT0  
P0.1/INT1  
P0.2/INT2  
P0.3/INT3  
P0.4/INT4  
AVSS  
AVREF  
P2.7/ADC7/VVLDREF  
P2.6/ADC6  
P2.5/ADC5  
NOTE: The sequence of pins in TQFP package is identical with that in QFP package.  
Figure 1-2. S3C8245/C8249 Pin Assignments (80-QFP-1420C)  
1-4  
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S3C8245/P8245/C8249/P8249  
PRODUCT OVERVIEW  
1
2
3
4
5
6
7
8
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
SEG26/P5.2  
SEG27/P5.3  
SEG28/P5.4  
SEG29/P5.5  
SEG30/P5.6  
SEG31/P5.7  
P3.0/TBPWM  
P3.1/TAOUT/TAPWM  
P3.2/TACLK  
P3.3/TACAP/SDAT  
P3.4/SCLK  
VDD  
SEG5  
SEG4  
SEG3  
SEG2  
SEG1  
SEG0  
COM3  
COM2  
COM1  
COM0  
VLC2  
VLC1  
VLC0  
CA  
CB  
9
S3C8245/C8249  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
(80-TQFP-1212)  
VSS  
XOUT  
XIN  
TEST  
AVSS  
XTIN  
XTOUT  
nRESET  
P0.0/INT0  
AVREF  
P2.7/ADC7/V LDREF  
P2.6/ADC6  
P2.5/ADC5  
Figure 1-3. S3C8245/C8249 Pin Assignments (80-TQFP-1212)  
1-5  
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PRODUCT OVERVIEW  
S3C8245/P8245/C8249/P8249  
PIN DESCRIPTIONS  
Table 1-1. S3C8245/C8249 Pin Descriptions  
Pin  
Names  
Pin  
Type  
Pin  
Description  
Circuit  
Type  
Pin  
Share  
Pins  
(note)  
Numbers  
P0.0–P0.7  
I/O  
I/O port with bit programmable pins;  
Schmitt trigger input or output mode  
selected by software; software assignable  
pull-up. P0.0–P0.7 can be used as inputs  
for external interrupts INT0–INT7  
D–4  
20–27  
INT0–INT7  
(with noise filter and interrupt control).  
P1.0–1.7  
I/O  
I/O port with bit programmable pins; Input  
or output mode selected by software;  
Open-drain output mode can be selected  
by software; software assignable pull-up.  
Alternately P1.0–P1.7 can be used as SI,  
SO, SCK, BUZ, T1CAP, T1CLK, T1OUT,  
T1PWM  
E–2  
28-35  
SI, SO, SCK,  
BUZ, T1CAP  
T1CLK  
T1OUT  
T1PWM  
P2.0–P2.7  
P3.0–P3.4  
I/O  
I/O  
I/O port with bit programmable pins;  
normal input and AD input or output mode  
selected by software; software assignable  
pull-up.  
F–10  
F–18  
36–42,  
43  
ADC0–ADC6  
V
VLDREF  
(ADC7)  
I/O port with bit programmable pins. Input  
or push-pull output with software  
assignable pull-up. Alternately P3.0–P3.3  
can be used as TACAP, TACLK, TAOUT,  
TAPWM, TBPWM  
D–2  
7–11  
TACAP  
TACLK  
TAOUT  
TAPWM  
TBPWM  
P4.0–P4.7  
P5.0–P5.7  
I/O  
I/O  
I/O port with bit programmable pins. Push-  
pull or open drain output and input with  
software assignable pull-up.  
P4.0–P4.7 can alternately be used as  
outputs for LCD SEG  
H–14  
H–14  
71–78  
79–6  
SEG16–SEG23  
I/O port with bit programmable pins. Push-  
pull or open drain output and input with  
software assignable pull-up.  
SEG24–SEG31  
P5.0–P5.7 can alternately be used as  
outputs for LCD SEG.  
1-6  
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S3C8245/P8245/C8249/P8249  
PRODUCT OVERVIEW  
Table 1-1. S3C8245/C8249 Pin Descriptions (Continued)  
Pin  
Names  
Pin  
Type  
Pin  
Description  
Circuit  
Type  
Pin  
Share  
Pins  
(note)  
Numbers  
ADC0–ADC6  
ADC7  
I
A/D converter analog input channels  
F–10  
F–18  
36–42  
43  
P2.0–P2.6  
P2.7  
AV  
–
–
A/D converter reference voltage  
A/D converter ground  
–
–
44  
45  
–
–
REF  
AV  
SS  
INT0–INT7  
nRESET  
I
I
External interrupt input pins  
D–4  
B
20–27  
19  
P0.0–P0.7  
–
System reset pin  
(pull-up resistor: 250 kW)  
TEST  
I
0 V: Normal MCU operating  
5 V: Test mode  
–
16  
–
12 V: for OTP writing  
SDAT, SCLK  
O
–
Serial OTP interface pins; serial data  
and clock  
D–2  
–
10, 11  
12, 13  
P3.3, P3.4  
–
V
V
Power input pins for CPU operation  
(internal) and Power input for OTP  
Writing  
DD, SS  
X
X
–
Main oscillator pins  
–
14, 15  
–
OUT, IN  
SO, SCK, SI  
I/O  
I
Serial I/O interface clock signal  
E–2  
33–35  
43  
P1.5–P1.7  
P2.7  
V
Voltage detector reference voltage input  
F–18  
VLDREF  
TACAP  
I
Timer A Capture input  
D–2  
D–2  
D–2  
D–2  
E–2  
E–2  
E–2  
H
10  
9
P3.3  
P3.2  
P3.1  
P3.0  
P1.0  
P1.1  
P1.2  
–
TACLK  
I
Timer A External clock input  
Timer A output and PWM output  
Timer B PWM output  
TAOUT/TAPWM  
TBPWM  
O
O
I
8
7
T1CAP  
Timer 1 Capture input  
28  
T1CLK  
I
Timer 1 External clock input  
Timer 1 output and PWM output  
LCD common signal output  
LCD segment output  
29  
T1OUT/T1PWM  
COM0–COM3  
SEG0–SEG15  
SEG16–SEG23  
SEG24–SEG31  
O
O
O
O
O
O
30  
51–54  
55–70  
71–78  
79–6  
48–50  
H
–
LCD segment output  
H–14  
H–14  
–
P4.0–P4.7  
P5.0–P5.7  
–
LCD Segment output  
V
–V  
LCD power supply  
LC0 LC2  
BUZ  
O
0.5, 1, 2 or 4 kHz frequency output for  
buzzer sound with 4.19 MHz main  
system clock or 32768 Hz subsystem  
clock  
E–2  
32  
P1.4  
CA, CB  
–
Capacitor terminal for voltage booster  
–
46–47  
–
1-7  
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PRODUCT OVERVIEW  
S3C8245/P8245/C8249/P8249  
PIN CIRCUITS  
VDD  
VDD  
Pull-up  
Enable  
P-Channel  
Data  
Circuit  
I/O  
Type C  
Output  
Disable  
In  
Figure 1-6. Pin Circuit Type D-2 (P3)  
Figure 1-4. Pin Circuit Type B (nRESET)  
VDD  
VDD  
VDD  
Pull-up  
Enable  
Data  
P-Channel  
Pin Circuit  
Type C  
Data  
I/O  
Output  
Disable  
Out  
N-Channel  
Output  
Disable  
Noise  
Filter  
Ext.INT  
Input  
Normal  
Figure 1-7. Pin Circuit Type D-4 (P0)  
Figure 1-5. Pin Circuit Type C  
1-8  
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S3C8245/P8245/C8249/P8249  
PRODUCT OVERVIEW  
VDD  
VDD  
Open drain  
Enable  
Pull-up  
Resistor  
Pull-up  
Enable  
VDD  
P-CH  
N-CH  
Data  
Output  
Disable  
Circuit  
Type C  
Data  
I/O  
I/O  
ADC & VLD  
Enable  
Output  
Disable  
Data  
VLDREF  
To ADC  
Schmitt Trigger  
Figure 1-8. Pin Circuit Type E-2 (P1)  
Figure 1-10. Pin Circuit Type F-18 (P2.7/VLD  
)
REF  
VDD  
VLC2  
VLC1  
Pull-up  
Enable  
Data  
Circuit  
Type C  
Output  
SEG/  
COM  
Out  
I/O  
Disable  
ADCEN  
Data  
VLC0  
To ADC  
Figure 1-9. Pin Circuit Type F-10 (P2.0–P2.6)  
Figure 1-11. Pin Circuit Type H (SEG/COM)  
1-9  
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PRODUCT OVERVIEW  
S3C8245/P8245/C8249/P8249  
VLC2  
VLC1  
SEG  
Output  
Disable  
VLC0  
Figure 1-12. Pin Circuit Type H-4  
VDD  
VDD  
Open Drain EN  
Data  
Pull-up  
Enable  
LCD Out EN  
SEG  
Circuit  
Type H-4  
Output  
Disable  
Figure 1-13. Pin Circuit Type H-14 (P4, P5)  
1-10  
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S3C8245/P8245/C8249/P8249  
ADDRESS SPACES  
2
ADDRESS SPACES  
OVERVIEW  
The S3C8245/C8249 microcontroller has two types of address space:  
— Internal program memory (ROM)  
— Internal register file  
A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data  
between the CPU and the register file.  
The S3C8245 has an internal 16-Kbyte mask-programmable ROM. The S3C8249 has an internal 32-Kbyte mask-  
programmable ROM.  
The 256-byte physical register space is expanded into an addressable area of 320 bytes using addressing modes.  
A 16-byte LCD display register file is implemented.  
There are 1,109 mapped registers in the internal register file. Of these, 1,040 are for general-purpose.  
(This number includes a 16-byte working register common area used as a “scratch area” for data operations, four  
192-byte prime register areas, and four 64-byte areas (Set 2)). Thirteen 8-bit registers are used for the CPU and the  
system control, and 53 registers are mapped for peripheral controls and data registers. Twelve register locations are  
not mapped.  
2-1  
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ADDRESS SPACES  
S3C8245/P8245/C8249/P8249  
PROGRAM MEMORY (ROM)  
Program memory (ROM) stores program codes or table data. The S3C8249 has 32K bytes internal mask-  
programmable program memory, the S3C8245 has 16K bytes.  
The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this  
address range can be used as normal program memory. If you use the vector address area to store a program code,  
be careful not to overwrite the vector addresses stored in these locations.  
The ROM address at which a program execution starts after a reset is 0100H.  
(Decimal)  
32,767  
(HEX)  
7FFFH (S3C8249)  
32K-byte  
16384  
16383  
4000H  
3FFFH (S3C8245)  
16K-byte  
255  
0
0FFH  
0H  
Interrupt  
Vector Area  
Figure 2-1. Program Memory Address Space  
2-2  
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S3C8245/P8245/C8249/P8249  
ADDRESS SPACES  
REGISTER ARCHITECTURE  
In the S3C8245/C8249 implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called  
set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1),  
and the lower 32-byte area is a single 32-byte common area.  
In case of S3C8249/P8249 the total number of addressable 8-bit registers is 1122. Of these 1122 registers, 16 bytes  
are for CPU and system control registers, 16 bytes are for LCD data registers, 50 bytes are for peripheral control and  
data registers, 16 bytes are used as a shared working registers, and 1024 registers are for general-purpose use,  
page 0-page 4 (in case of S3C8245/P8245, page 0-page 2).  
You can always address set 1 register locations, regardless of which of the four register pages is currently selected.  
Set 1 locations, however, can only be addressed using register addressing modes.  
The extension of register space into separately addressable areas (sets, banks, and pages) is supported by various  
addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer (PP).  
Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2–1.  
Table 2-1. S3C8249/P8249 Register Type Summary  
Register Type  
Number of Bytes  
General-purpose registers (including the 16-byte common  
working register area, four 192-byte prime register area,  
and four 64-byte set 2 area)  
1,040  
LCD data registers  
CPU and system control registers  
Mapped clock, peripheral, I/O control, and data registers  
16  
16  
50  
1,122  
Total Addressable Bytes  
Table 2-2. S3C8245/P8245 Register Type Summary  
Register Type  
Number of Bytes  
General-purpose registers (including the 16-byte common  
working register area, four 192-byte prime register area,  
and four 64-byte set 2 area)  
528  
LCD data registers  
CPU and system control registers  
Mapped clock, peripheral, I/O control, and data registers  
16  
16  
50  
610  
Total Addressable Bytes  
2-3  
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ADDRESS SPACES  
S3C8245/P8245/C8249/P8249  
Page3  
FFH  
FFH  
FFH  
FFH  
Set1  
Page 2  
Page 1  
Bank 1  
FFH  
Bank 0  
Page 0  
Set 2  
32  
Bytes  
System and  
Peripheral Control  
Registers  
General-Purpose  
Data Registers  
E0H  
(Register Addressing Mode)  
E0H  
DFH  
64  
Bytes  
(Indirect Register, Indexed  
Mode, and Stack  
Operations)  
System Registers  
(Register Addressing Mode)  
256  
Bytes  
D0H  
CFH  
C0H  
BFH  
General Purpose Register  
(Register Addressing Mode)  
Page 0  
C0H  
0FH  
~
~
Page 4  
~
Prime  
Data Registers  
192  
Bytes  
~
~
Prime  
Data Registers  
(All Addressing Modes)  
16  
Bytes  
~
~
(All addressing modes)  
LCD Display Reigster  
00H  
00H  
NOTE:  
In case of S3C8245/P8245, there are page 0, page 1, and page 4.  
Page 4 is for LCD display register, 16 bytes.  
Figure 2-2. Internal Register File Organization  
2-4  
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S3C8245/P8245/C8249/P8249  
ADDRESS SPACES  
REGISTER PAGE POINTER (PP)  
The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using an  
8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the  
register page pointer (PP, DFH). In the S3C8245/C8249 microcontroller, a paged register file expansion is  
implemented for LCD data registers, and the register page pointer must be changed to address other pages.  
After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always  
"0000", automatically selecting page 0 as the source and destination page for register addressing.  
Register Page Pointer (PP)  
DFH ,Set 1, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Destination register page selection bits:  
Source register page selection bits:  
0000 Source: Page 0  
0000  
Destination: Page 0  
NOTE:  
A hardware reset operation writes the 4-bit destination and  
source values shown above to the register page pointer. These values should  
be modified to address other pages.  
Figure 2-3. Register Page Pointer (PP)  
+
PROGRAMMING TIP — Using the Page Pointer for RAM clear (Page 0, Page 1)  
LD  
SRP  
LD  
CLR  
DJNZ  
CLR  
PP,#00H  
#0C0H  
R0,#0FFH  
@R0  
R0,RAMCL0  
@R0  
;
;
Destination ¬ 0, Source ¬ 0  
Page 0 RAM clear starts  
RAMCL0  
;
R0 = 00H  
LD  
LD  
CLR  
DJNZ  
CLR  
PP,#10H  
R0,#0FFH  
@R0  
R0,RAMCL1  
@R0  
;
;
Destination ¬ 1, Source ¬ 0  
Page 1 RAM clear starts  
RAMCL1  
;
R0 = 00H  
NOTE: You should refer to page 6-39 and use DJNZ instruction properly when DJNZ instruction is used in your program.  
2-5  
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ADDRESS SPACES  
S3C8245/P8245/C8249/P8249  
REGISTER SET 1  
The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH.  
The upper 32-byte area of this 64-byte space (E0H–FFH) is expanded two 32-byte register banks, bank 0 and bank  
1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware reset  
operation always selects bank 0 addressing.  
The upper two 32-byte areas (bank 0 and bank 1) of set 1 (E0H–FFH) contains 50 mapped system and peripheral  
control registers. The lower 32-byte area contains 16 system registers (D0H–DFH) and a 16-byte common working  
register area (C0H–CFH). You can use the common working register area as a “scratch” area for data operations  
being performed in other areas of the register file.  
Registers in set 1 locations are directly accessible at all times using Register addressing mode. The 16-byte  
working register area can only be accessed using working register addressing (For more information about working  
register addressing, please refer to Chapter 3, “Addressing Modes.”)  
REGISTER SET 2  
The same 64-byte physical space that is used for set 1 locations C0H–FFH is logically duplicated to add another 64  
bytes of register space. This expanded area of the register file is called set 2. For the S3C8249,  
the set 2 address range (C0H–FFH) is accessible on pages 0–3.  
S3C8245, the set 2 address range (C0H-FFH) is accessible on pages 0-1.  
The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only  
Register addressing mode to access set 1 locations. In order to access registers in set 2, you must use Register  
Indirect addressing mode or Indexed addressing mode.  
The set 2 register area is commonly used for stack operations.  
2-6  
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S3C8245/P8245/C8249/P8249  
PRIME REGISTER SPACE  
ADDRESS SPACES  
The lower 192 bytes (00H–BFH) of the S3C8245/C8249's four or two 256-byte register pages is called prime register  
area. Prime registers can be accessed using any of the seven addressing modes  
(see Chapter 3, "Addressing Modes.")  
The prime register area on page 0 is immediately addressable following a reset. In order to address prime registers  
on pages 0, 1, 2, 3, or 4 you must set the register page pointer (PP) to the appropriate source and destination  
values.  
FFH  
Page 3  
FFH  
Page 2  
FFH  
FFH  
Set 1  
Page 1  
Bank 0  
Bank 1  
Page 0  
FFH  
FCH  
E0H  
D0H  
Set 2  
C0H  
BFH  
Page 0  
C0H  
Prime  
Space  
CPU and system control  
General-purpose  
Page 4  
0FH  
00H  
LCD Data  
Register Area  
Peripheral and I/O  
LCD data register  
00H  
Figure 2-4. Set 1, Set 2, Prime Area Register, and LCD Data Register Map  
2-7  
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ADDRESS SPACES  
S3C8245/P8245/C8249/P8249  
WORKING REGISTERS  
Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When  
4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that  
consists of 32 8-byte register groups or "slices." Each slice comprises of eight 8-bit registers.  
Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to  
form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block  
anywhere in the addressable register file, except the set 2 area.  
The terms slice and block are used in this manual to help you visualize the size and relative locations of selected  
working register spaces:  
— One working register slice is 8 bytes (eight 8-bit working registers, R0–R7 or R8–R15)  
— One working register block is 16 bytes (sixteen 8-bit working registers, R0–R15)  
All the registers in an 8-byte working register slice have the same binary value for their five most significant address  
bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file. The base  
addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1.  
After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H–CFH).  
FFH  
Slice 32  
F8H  
F7H  
F0H  
Slice 31  
1 1 1 1 1 X X X  
Set 1  
Only  
RP1 (Registers R8-R15)  
Each register pointer points to  
one 8-byte slice of the register  
space, selecting a total 16-byte  
working register block.  
CFH  
C0H  
~
~
0 0 0 0 0 X X X  
10H  
FH  
8H  
7H  
0H  
RP0 (Registers R0-R7)  
Slice 2  
Slice 1  
Figure 2-5. 8-Byte Working Register Areas (Slices)  
2-8  
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S3C8245/P8245/C8249/P8249  
ADDRESS SPACES  
USING THE REGISTER POINTS  
Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte  
working register slices in the register file. After a reset, they point to the working register common area: RP0 points  
to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.  
To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction.  
(see Figures 2-6 and 2-7).  
With working register addressing, you can only access those two 8-bit slices of the register file that are currently  
pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in set  
2, C0H–FFH, because these locations can be accessed only using the Indirect Register or Indexed addressing  
modes.  
The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general  
programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice  
(see Figure 2-6). In some cases, it may be necessary to define working register areas in different (non-contiguous)  
areas of the register file. In Figure 2-7, RP0 points to the "upper" slice and RP1 to the "lower" slice.  
Because a register pointer can point to either of the two 8-byte slices in the working register block, you can flexibly  
define the working register area to support program requirements.  
+
PROGRAMMING TIP — Setting the Register Pointers  
SRP  
SRP1  
SRP0  
CLR  
LD  
#70H  
#48H  
#0A0H  
RP0  
RP1,#0F8H  
;
;
;
;
;
RP0 ¬ 70H, RP1 ¬ 78H  
RP0 ¬ no change, RP1 ¬ 48H,  
RP0 ¬ A0H, RP1 ¬ no change  
RP0 ¬ 00H, RP1 ¬ no change  
RP0 ¬ no change, RP1 ¬ 0F8H  
Register File  
Contains 32  
8-Byte Slices  
0 0 0 0 1 X X X  
RP1  
FH (R15)  
16-Byte  
Contiguous  
Working  
8-Byte Slice  
8-Byte Slice  
8H  
7H  
0 0 0 0 0 X X X  
RP0  
Register block  
0H (R0)  
Figure 2-6. Contiguous 16-Byte Working Register Block  
2-9  
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ADDRESS SPACES  
S3C8245/P8245/C8249/P8249  
F7H (R7)  
F0H (R0)  
8-Byte Slice  
16-Byte  
Contiguous  
working  
Register File  
Contains 32  
8-Byte Slices  
1 1 1 1 0 X X X  
Register block  
RP0  
0 0 0 0 0 X X X  
RP1  
7H (R15)  
0H (R0)  
8-Byte Slice  
Figure 2-7. Non-Contiguous 16-Byte Working Register Block  
+
PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers  
Calculate the sum of registers 80H–85H using the register pointer. The register addresses from 80H through 85H  
contain the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively:  
SRP0  
ADD  
ADC  
ADC  
ADC  
ADC  
#80H  
;
;
;
;
;
;
RP0 ¬ 80H  
R0,R1  
R0,R2  
R0,R3  
R0,R4  
R0,R5  
R0 ¬ R0 + R1  
R0 ¬ R0 + R2 + C  
R0 ¬ R0 + R3 + C  
R0 ¬ R0 + R4 + C  
R0 ¬ R0 + R5 + C  
The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this example  
takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to calculate  
the sum of these registers, the following instruction sequence would have to be used:  
ADD  
ADC  
ADC  
ADC  
ADC  
80H,81H  
80H,82H  
80H,83H  
80H,84H  
80H,85H  
;
;
;
;
;
80H ¬ (80H) + (81H)  
80H ¬ (80H) + (82H) + C  
80H ¬ (80H) + (83H) + C  
80H ¬ (80H) + (84H) + C  
80H ¬ (80H) + (85H) + C  
Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of  
instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.  
2-10  
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S3C8245/P8245/C8249/P8249  
ADDRESS SPACES  
REGISTER ADDRESSING  
The S3C8-series register architecture provides an efficient method of working register addressing that takes full  
advantage of shorter instruction formats to reduce execution time.  
With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair,  
you can access any location in the register file except for set 2. With working register addressing, you use a register  
pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space.  
Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register pair,  
the address of the first 8-bit register is always an even number and the address of the next register is always an odd  
number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and the least  
significant byte is always stored in the next (+1) odd-numbered register.  
Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8-byte  
working register space in the internal register file and a specific 8-bit register within that space.  
MSB  
Rn  
LSB  
n = Even address  
Rn+1  
Figure 2-8. 16-Bit Register Pair  
2-11  
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ADDRESS SPACES  
S3C8245/P8245/C8249/P8249  
Special-Purpose Registers  
General-Purpose Register  
FFH  
Bank 1  
Bank 1  
FFH  
Control  
Registers  
E0H  
D0H  
Set 2  
System  
Registers  
CFH  
C0H  
C0H  
BFH  
RP1  
RP0  
Register  
Pointers  
Each register pointer (RP) can independently point  
to one of the 24 8-byte "slices" of the register file  
(other than set 2). After a reset, RP0 points to  
locations C0H-C7H and RP1 to locations C8H-CFH  
(that is, to the common working register area).  
Prime  
Registers  
LCD Data  
Registers  
NOTE:  
In the S3C8245/C8249 microcontroller,  
pages 0-4 are implemented.  
Pages 0-4 contain all of the addressable  
registers in the internal register file.  
00H  
Page 0  
Page 0  
Register Addressing Only  
All  
Indirect Register,  
All  
Addressing  
Modes  
Indexed  
Addressing  
Modes  
Addressing  
Modes  
Can be Pointed by Register Pointer  
Can be Pointed to  
By register Pointer  
Figure 2-9. Register File Addressing  
2-12  
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S3C8245/P8245/C8249/P8249  
ADDRESS SPACES  
COMMON WORKING REGISTER AREA (C0H–CFH)  
After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H–  
CFH, as the active 16-byte working register block:  
RP0 ® C0H–C7H  
RP1 ® C8H–CFH  
This 16-byte address range is called common area. That is, locations in this area can be used as working registers  
by operations that address any location on any page in the register file. Typically, these working registers serve as  
temporary buffers for data operations between different pages.  
FFH  
Page 3  
FFH  
Page 2  
FFH  
Page 1  
Set 1  
FFH  
Page 0  
FFH  
FCH  
Set 2  
E0H  
D0H  
C0H  
C0H  
BFH  
Page 0  
~
~
Following a hardware reset, register  
pointers RP0 and RP1 point to the  
common working register area,  
locations C0H-CFH.  
~
Prime  
Space  
~
~
Page 4  
0FH  
00H  
LCD Data  
Registers  
RP0 = 1 1 0 0  
RP1 = 1 1 0 0  
0 0 0 0  
1 0 0 0  
00H  
Figure 2-10. Common Working Register Area  
2-13  
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ADDRESS SPACES  
S3C8245/P8245/C8249/P8249  
+
PROGRAMMING TIP — Addressing the Common Working Register Area  
As the following examples show, you should access working registers in the common area, locations C0H–CFH,  
using working register addressing mode only.  
Examples 1. LD  
0C2H,40H  
;
Invalid addressing mode!  
Use working register addressing instead:  
SRP  
LD  
#0C0H  
R2,40H  
;
;
R2 (C2H) ® the value in location 40H  
2. ADD  
0C3H,#45H  
Invalid addressing mode!  
Use working register addressing instead:  
SRP  
ADD  
#0C0H  
R3,#45H  
;
R3 (C3H) ® R3 + 45H  
4-BIT WORKING REGISTER ADDRESSING  
Each register pointer defines a movable 8-byte slice of working register space. The address information stored in a  
register pointer serves as an addressing "window" that makes it possible for instructions to access working registers  
very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected working  
register area, the address bits are concatenated in the following way to form a complete 8-bit address:  
— The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1).  
— The five high-order bits in the register pointer select an 8-byte slice of the register space.  
— The three low-order bits of the 4-bit address select one of the eight registers in the slice.  
As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are  
concatenated with the three low-order bits from the instruction address to form the complete address. As long as the  
address stored in the register pointer remains unchanged, the three bits from the address will always point to an  
address in the same 8-byte register slice.  
Figure 2-12 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction  
"INC R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the three  
low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).  
2-14  
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S3C8245/P8245/C8249/P8249  
ADDRESS SPACES  
RP0  
RP1  
Selects  
RP0 or RP1  
Address  
OPCODE  
4-bit address  
provides three  
low-order bits  
Register pointer  
provides five  
high-order bits  
Together they create an  
8-bit register address  
Figure 2-11. 4-Bit Working Register Addressing  
RP0  
0 1 1 1 0  
RP1  
0 1 1 1 1  
0 0 0  
0 0 0  
Selects RP0  
R6  
OPCODE  
1 1 1 0  
Register  
address  
(76H)  
Instruction  
'INC R6'  
0 1 1 1 0  
1 1 0  
0 1 1 0  
Figure 2-12. 4-Bit Working Register Addressing Example  
2-15  
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ADDRESS SPACES  
S3C8245/P8245/C8249/P8249  
8-BIT WORKING REGISTER ADDRESSING  
You can also use 8-bit working register addressing to access registers in a selected working register area. To  
initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value  
"1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working register  
addressing.  
As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit  
addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the  
three low-order bits of the complete address are provided by the original instruction.  
Figure 2-14 shows an example of 8-bit working register addressing. The four high-order bits of the instruction address  
(1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in RP1  
(10101B) become the five high-order bits of the register address. The three low-order bits of the register address  
(011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from RP1 and the  
three address bits from the instruction are concatenated to form the complete register address, 0ABH (10101011B).  
RP0  
RP1  
Selects  
RP0 or RP1  
Address  
These address  
bits indicate 8-bit  
working register  
addressing  
8-bit logical  
address  
1
1
0
0
Register pointer  
provides five  
Three low-order bits  
high-order bits  
8-bit physical address  
Figure 2-13. 8-Bit Working Register Addressing  
2-16  
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ADDRESS SPACES  
RP0  
0 1 1 0 0  
RP1  
1 0 1 0 1  
0 0 0  
0 0 0  
Selects RP1  
R11  
8-bit address  
form instruction  
'LD R11, R2'  
Register  
address  
(0ABH)  
1 1 0 0  
1
0 1 1  
1 0 1 0 1  
0 1 1  
Specifies working  
register addressing  
Figure 2-14. 8-Bit Working Register Addressing Example  
2-17  
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ADDRESS SPACES  
S3C8245/P8245/C8249/P8249  
SYSTEM AND USER STACK  
The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH  
and POP instructions are used to control system stack operations. The S3C8245/C8249 architecture supports stack  
operations in the internal register file.  
Stack Operations  
Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are saved  
to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the  
PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their  
original locations. The stack address value is always decreased by one before a push operation and increased by  
one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as  
shown in Figure 2-15.  
High Address  
PCL  
PCL  
PCH  
Top of  
stack  
PCH  
Top of  
stack  
Flags  
Stack contents  
after a call  
Stack contents  
after an  
instruction  
interrupt  
Low Address  
Figure 2-15. Stack Operations  
User-Defined Stacks  
You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,  
PUSHUD, POPUI, and POPUD support user-defined stack operations.  
Stack Pointers (SPL, SPH)  
Register locations D8H and D9H contain the 16-bit stack pointer (SP) that is used for system stack operations. The  
most significant byte of the SP address, SP15–SP8, is stored in the SPH register (D8H), and the least significant  
byte, SP7–SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined.  
Because only internal memory space is implemented in the S3C8245/C8249, the SPL must be initialized to an 8-bit  
value in the range 00H–FFH. The SPH register is not needed and can be used as a general-purpose register, if  
necessary.  
When the SPL register contains the only stack pointer value (that is, when it points to a system stack in the register  
file), you can use the SPH register as a general-purpose data register. However, if an overflow or underflow condition  
occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack  
operations, the value in the SPL register will overflow (or underflow) to the SPH register, overwriting any other data  
that is currently stored there. To avoid overwriting data in the SPH register, you can initialize the SPL value to "FFH"  
instead of "00H".  
2-18  
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S3C8245/P8245/C8249/P8249  
ADDRESS SPACES  
+
PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP  
The following example shows you how to perform stack operations in the internal register file using PUSH and POP  
instructions:  
LD  
SPL,#0FFH  
;
;
;
SPL ¬ FFH  
(Normally, the SPL is set to 0FFH by the initialization  
routine)  
•
•
•
PUSH  
PUSH  
PUSH  
PUSH  
•
PP  
;
;
;
;
Stack address 0FEH ¬ PP  
Stack address 0FDH ¬ RP0  
Stack address 0FCH ¬ RP1  
Stack address 0FBH ¬ R3  
RP0  
RP1  
R3  
•
•
POP  
POP  
POP  
POP  
R3  
;
;
;
;
R3 ¬ Stack address 0FBH  
RP1 ¬ Stack address 0FCH  
RP0 ¬ Stack address 0FDH  
PP ¬ Stack address 0FEH  
RP1  
RP0  
PP  
2-19  
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ADDRESS SPACES  
S3C8245/P8245/C8249/P8249  
NOTES  
2-20  
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S3C8245/P8245/C8249/P8249  
ADDRESSING MODES  
3
ADDRESSING MODES  
OVERVIEW  
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions  
indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to  
determine the location of the data operand. The operands specified in SAM88RC instructions may be condition  
codes, immediate data, or a location in the register file, program memory, or data memory.  
The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are  
available for each instruction. The seven addressing modes and their symbols are:  
— Register (R)  
— Indirect Register (IR)  
— Indexed (X)  
— Direct Address (DA)  
— Indirect Address (IA)  
— Relative Address (RA)  
— Immediate (IM)  
3-1  
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ADDRESSING MODES  
S3C8245/P8245/C8249/P8249  
REGISTER ADDRESSING MODE (R)  
In Register addressing mode (R), the operand value is the content of a specified register or register pair  
(see Figure 3-1).  
Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte  
working register space in the register file and an 8-bit register within that space (see Figure 3-2).  
Program Memory  
Register File  
OPERAND  
8-bit Register  
File Address  
dst  
Point to One  
Register in Register  
File  
OPCODE  
One-Operand  
Instruction  
(Example)  
Value used in  
Instruction Execution  
Sample Instruction:  
DEC  
CNTR  
;
Where CNTR is the label of an 8-bit register address  
Figure 3-1. Register Addressing  
Register File  
MSB Point to  
RP0 ot RP1  
RP0 or RP1  
Selected  
RP points  
to start  
Program Memory  
of working  
register  
block  
4-bit  
Working Register  
3 LSBs  
dst  
src  
Point to the  
Working Register  
(1 of 8)  
OPCODE  
OPERAND  
Two-Operand  
Instruction  
(Example)  
Sample Instruction:  
ADD R1, R2  
;
Where R1 and R2 are registers in the currently  
selected working register area.  
Figure 3-2. Working Register Addressing  
3-2  
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ADDRESSING MODES  
INDIRECT REGISTER ADDRESSING MODE (IR)  
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the  
operand. Depending on the instruction used, the actual address may point to a register in the register file, to program  
memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).  
You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly  
address another memory location. Please note, however, that you cannot access locations C0H–FFH in set 1 using  
the Indirect Register addressing mode.  
Program Memory  
Register File  
ADDRESS  
8-bit Register  
File Address  
dst  
Point to One  
Register in Register  
File  
OPCODE  
One-Operand  
Instruction  
(Example)  
Address of Operand  
used by Instruction  
OPERAND  
Value used in  
Instruction Execution  
Sample Instruction:  
RL  
@SHIFT  
;
Where SHIFT is the label of an 8-bit register address  
Figure 3-3. Indirect Register Addressing to Register File  
3-3  
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ADDRESSING MODES  
S3C8245/P8245/C8249/P8249  
INDIRECT REGISTER ADDRESSING MODE (Continued)  
Register File  
Program Memory  
REGISTER  
PAIR  
Example  
Instruction  
References  
Program  
dst  
Points to  
Register Pair  
OPCODE  
16-Bit  
Memory  
Address  
Points to  
Program  
Memory  
Program Memory  
OPERAND  
Sample Instructions:  
Value used in  
Instruction  
CALL  
JP  
@RR2  
@RR2  
Figure 3-4. Indirect Register Addressing to Program Memory  
3-4  
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S3C8245/P8245/C8249/P8249  
ADDRESSING MODES  
INDIRECT REGISTER ADDRESSING MODE (Continued)  
Register File  
MSB Points to  
RP0 or RP1  
RP0 or RP1  
Selected  
RP points  
to start fo  
working register  
block  
Program Memory  
~
~
~
~
4-bit  
Working  
Register  
Address  
3 LSBs  
dst  
src  
Point to the  
Working Register  
(1 of 8)  
OPCODE  
ADDRESS  
OPERAND  
Sample Instruction:  
OR R3, @R6  
Value used in  
Instruction  
Figure 3-5. Indirect Working Register Addressing to Register File  
3-5  
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ADDRESSING MODES  
S3C8245/P8245/C8249/P8249  
INDIRECT REGISTER ADDRESSING MODE (Concluded)  
Register File  
MSB Points to  
RP0 or RP1  
RP0 or RP1  
Selected  
RP points  
to start of  
working  
register  
block  
Program Memory  
4-bit Working  
Register Address  
dst  
src  
Register  
Pair  
Next 2-bit Point  
to Working  
Register Pair  
(1 of 4)  
OPCODE  
Example Instruction  
References either  
Program Memory or  
Data Memory  
16-Bit  
address  
points to  
program  
memory  
or data  
Program Memory  
or  
Data Memory  
LSB Selects  
memory  
Value used in  
Instruction  
OPERAND  
Sample Instructions:  
LCD  
LDE  
LDE  
R5,@RR6  
R3,@RR14  
@RR4, R8  
; Program memory access  
; External data memory access  
; External data memory access  
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory  
3-6  
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ADDRESSING MODES  
INDEXED ADDRESSING MODE (X)  
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate  
the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the  
internal register file or in external memory. Please note, however, that you cannot access locations C0H–FFH in  
set 1 using Indexed addressing mode.  
In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128 to  
+127. This applies to external memory accesses only (see Figure 3-8.)  
For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in  
a working register. For external memory accesses, the base address is stored in the working register pair  
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address (see  
Figure 3-9).  
The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD).  
The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data  
memory, when implemented.  
Register File  
RP0 or RP1  
~
~
~
~
Selected RP  
points to  
start of  
working  
register  
block  
Value used in  
Instruction  
OPERAND  
+
Program Memory  
Base Address  
3 LSBs  
Two-Operand  
Instruction  
Example  
dst/src  
x
INDEX  
Point to One of the  
Woking Register  
(1 of 8)  
OPCODE  
Sample Instruction:  
LD R0, #BASE[R1]  
;
Where BASE is an 8-bit immediate value  
Figure 3-7. Indexed Addressing to Register File  
3-7  
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ADDRESSING MODES  
S3C8245/P8245/C8249/P8249  
INDEXED ADDRESSING MODE (Continued)  
Register File  
RP0 or RP1  
MSB Points to  
RP0 or RP1  
Selected  
RP points  
to start of  
~
~
working  
Program Memory  
OFFSET  
register  
block  
NEXT 2 Bits  
4-bit Working  
Register Address  
dst/src  
x
Register  
Pair  
Point to Working  
Register Pair  
(1 of 4)  
OPCODE  
16-Bit  
address  
added to  
offset  
Program Memory  
or  
LSB Selects  
Data Memory  
+
16-Bits  
8-Bits  
Value used in  
Instruction  
OPERAND  
16-Bits  
Sample Instructions:  
LDC  
LDE  
R4, #04H[RR2]  
R4,#04H[RR2]  
; The values in the program address (RR2 + 04H)  
are loaded into register R4.  
; Identical operation to LDC example, except that  
external program memory is accessed.  
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset  
3-8  
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S3C8245/P8245/C8249/P8249  
ADDRESSING MODES  
INDEXED ADDRESSING MODE (Concluded)  
Register File  
RP0 or RP1  
MSB Points to  
RP0 or RP1  
Selected  
RP points  
to start of  
working  
register  
block  
Program Memory  
~
~
OFFSET  
OFFSET  
NEXT 2 Bits  
4-bit Working  
Register Address  
dst/src  
src  
Register  
Pair  
Point to Working  
Register Pair  
OPCODE  
16-Bit  
address  
added to  
offset  
Program Memory  
or  
LSB Selects  
Data Memory  
+
16-Bits  
8-Bits  
Value used in  
Instruction  
OPERAND  
16-Bits  
Sample Instructions:  
LDC  
LDE  
R4, #1000H[RR2]  
R4,#1000H[RR2]  
; The values in the program address (RR2 + 1000H)  
are loaded into register R4.  
; Identical operation to LDC example, except that  
external program memory is accessed.  
Figure 3-9. Indexed Addressing to Program or Data Memory  
3-9  
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ADDRESSING MODES  
S3C8245/P8245/C8249/P8249  
DIRECT ADDRESS MODE (DA)  
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call  
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC  
whenever a JP or CALL instruction is executed.  
The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load  
operations to program memory (LDC) or to external data memory (LDE), if implemented.  
Program or  
Data Memory  
Memory  
Address  
Used  
Program Memory  
Upper Address Byte  
Lower Address Byte  
dst/src "0" or "1"  
OPCODE  
LSB Selects Program  
Memory or Data Memory:  
"0" = Program Memory  
"1" = Data Memory  
Sample Instructions:  
LDC  
LDE  
R5,1234H  
R5,1234H  
;
;
The values in the program address (1234H)  
are loaded into register R5.  
Identical operation to LDC example, except that  
external program memory is accessed.  
Figure 3-10. Direct Addressing for Load Instructions  
3-10  
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S3C8245/P8245/C8249/P8249  
ADDRESSING MODES  
DIRECT ADDRESS MODE (Continued)  
Program Memory  
Next OPCODE  
Memory  
Address  
Used  
Upper Address Byte  
Lower Address Byte  
OPCODE  
Sample Instructions:  
JP  
C,JOB1  
;
;
Where JOB1 is a 16-bit immediate address  
Where DISPLAY is a 16-bit immediate address  
CALL DISPLAY  
Figure 3-11. Direct Addressing for Call and Jump Instructions  
3-11  
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ADDRESSING MODES  
S3C8245/P8245/C8249/P8249  
INDIRECT ADDRESS MODE (IA)  
In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program  
memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.  
Only the CALL instruction can use the Indirect Address mode.  
Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program  
memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed  
to be all zeros.  
Program Memory  
Next Instruction  
LSB Must be Zero  
dst  
Current  
OPCODE  
Instruction  
Lower Address Byte  
Upper Address Byte  
Program Memory  
Locations 0-255  
Sample Instruction:  
CALL #40H  
; The 16-bit value in program memory addresses 40H  
and 41H is the subroutine start address.  
Figure 3-12. Indirect Addressing  
3-12  
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S3C8245/P8245/C8249/P8249  
ADDRESSING MODES  
RELATIVE ADDRESS MODE (RA)  
In Relative Address (RA) mode, a twos-complement signed displacement between – 128 and + 127 is specified in  
the instruction. The displacement value is then added to the current PC value. The result is the address of the next  
instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately  
following the current instruction.  
Several program control instructions use the Relative Address mode to perform conditional jumps. The instructions  
that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.  
Program Memory  
Next OPCODE  
Program Memory  
Address Used  
Current  
PC Value  
+
Displacement  
OPCODE  
Current Instruction  
Signed  
Displacement Value  
Sample Instructions:  
JR  
ULT,$+OFFSET  
;
Where OFFSET is a value in the range +127 to -128  
Figure 3-13. Relative Addressing  
3-13  
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ADDRESSING MODES  
S3C8245/P8245/C8249/P8249  
IMMEDIATE MODE (IM)  
In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand  
field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate  
addressing mode is useful for loading constant values into registers.  
Program Memory  
OPERAND  
OPCODE  
(The Operand value is in the instruction)  
Sample Instruction:  
LD R0,#0AAH  
Figure 3-14. Immediate Addressing  
3-14  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
4
CONTROL REGISTERS  
OVERVIEW  
In this chapter, detailed descriptions of the S3C8245/C8249 control registers are presented in an easy-to-read  
format. You can use this chapter as a quick-reference source when writing application programs. Figure 4-1  
illustrates the important features of the standard register description format.  
Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed  
information about control registers is presented in the context of the specific peripheral hardware descriptions in Part  
II of this manual.  
Data and counter registers are not described in detail in this reference chapter. More information about all of the  
registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this  
manual.  
The locations and read/write characteristics of all mapped registers in the S3C8245/C8249 register file are listed in  
Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, "nRESET and Power-Down."  
Table 4-1. Set 1 Registers  
Register Name  
LCD control register  
Mnemonic  
LCON  
LMOD  
INTPND  
BTCON  
CLKCON  
FLAGS  
RP0  
Decimal  
208  
209  
210  
211  
212  
213  
214  
215  
216  
217  
218  
219  
220  
221  
222  
223  
Hex  
D0H  
D1H  
D2H  
D3H  
D4H  
D5H  
D6H  
D7H  
D8H  
D9H  
DAH  
DBH  
DCH  
DDH  
DEH  
DFH  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R
LCD mode register  
Interrupt pending register  
Basic timer control register  
Clock control register  
System flags register  
Register pointer 0  
Register pointer 1  
RP1  
Stack pointer (high byte)  
Stack pointer (low byte)  
Instruction pointer (high byte)  
Instruction pointer (low byte)  
Interrupt request register  
Interrupt mask register  
System mode register  
Register page pointer  
SPH  
SPL  
IPH  
IPL  
IRQ  
IMR  
R/W  
R/W  
R/W  
SYM  
PP  
4-1  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
Table 4-2. Set 1, Bank 0 Registers  
Register Name  
Mnemonic  
P0CONH  
P0CONL  
P0INT  
Decimal  
224  
225  
226  
227  
228  
229  
230  
231  
232  
233  
234  
235  
236  
237  
238  
239  
240  
241  
242  
243  
244  
245  
246  
247  
248  
249  
250  
251  
Hex  
E0H  
E1H  
E2H  
E3H  
E4H  
E5H  
E6H  
E7H  
E8H  
E9H  
EAH  
EBH  
ECH  
EDH  
EEH  
EFH  
F0H  
F1H  
F2H  
F3H  
F4H  
F5H  
F6H  
F7H  
F8H  
F9H  
FAH  
FBH  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R
Port 0 control High register  
Port 0 control Low register  
Port 0 interrupt control register  
Port 0 interrupt pending register  
Port 1 control High register  
Port 1 control Low register  
Port 2 control High register  
Port 2 control Low register  
Port 3 control High register  
Port 3 control Low register  
Timer B data register (high byte)  
Timer B data register (low byte)  
Timer B control register  
Timer A control register  
Timer A counter register  
Timer A data register  
P0PND  
P1CONH  
P1CONL  
P2CONH  
P2CONL  
P3CONH  
P3CONL  
TBDATAH  
TBDATAL  
TBCON  
TACON  
TACNT  
TADATA  
SIOCON  
SIODATA  
SIOPS  
OSCCON  
STPCON  
P1PUP  
P0  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Serial I/O control register  
Serial I/O data register  
Serial I/O pre-scale register  
Oscillator control register  
STOP control register  
Port 1 pull-up control register  
Port 0 data register  
Port 1 data register  
P1  
Port 2 data register  
P2  
Port 3 data register  
P3  
Port 4 data register  
P4  
Port 5 data register  
P5  
Location FCH is factory use only.  
Basic timer data register  
External memory timing register  
Interrupt priority register  
BTCNT  
EMT  
253  
FDH  
FEH  
FFH  
R
254  
255  
R/W  
R/W  
IPR  
4-2  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
Table 4-3. Set 1, Bank 1 Registers  
Register Name  
Mnemonic  
Decimal  
Hex  
R/W  
Locations E0H–EBH is not mapped.  
Port 4 control High register  
Port 4 control Low register  
Port 5 control High register  
Port 5 control Low register  
P4CONH  
P4CONL  
P5CONH  
P5CONL  
236  
237  
238  
239  
ECH  
EDH  
EEH  
EFH  
R/W  
R/W  
R/W  
R/W  
Locations F0H is factory use only.  
Timer 0 control register  
T0CON  
T0CNTH  
T0CNTL  
241  
F1H  
F2H  
F3H  
F4H  
F5H  
F6H  
F7H  
F8H  
F9H  
FAH  
FBH  
FCH  
FDH  
FEH  
FFH  
R/W  
R
Timer 0 counter register (high byte)  
Timer 0 counter register (low byte)  
Timer 0 data register (high byte)  
Timer 0 data register (low byte)  
Voltage level detector control register  
A/D converter control register  
A/D converter data register (high byte)  
A/D converter data register (low byte)  
Watch timer control register  
242  
243  
244  
245  
246  
247  
248  
249  
250  
251  
252  
253  
254  
255  
R
T0DATAH  
T0DATAL  
VLDCON  
ADCON  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R
ADDATAH  
ADDATAL  
WTCON  
T1CON  
Timer 1 control register  
Timer 1 counter register (high byte)  
Timer 1 counter register (low byte)  
Timer 1 data register (high byte)  
Timer 1 data register (low byte)  
T1CNTH  
T1CNTL  
R
T1DATAH  
T1DATAL  
R/W  
R/W  
4-3  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
Bit number(s) that is/are appended to  
the register name for bit addressing  
Name of individual  
bit or related bits  
Register location  
in the internal  
register file  
Register address  
(hexadecimal)  
Register ID  
Full Register name  
FLAGS - System Flags Register  
D5H  
Set 1  
Bit Identifier  
nRESET Value  
Read/Write  
Bit Addressing  
Mode  
.7  
x
.6  
x
.5  
x
.4  
x
.3  
x
.2  
.1  
.0  
0
x
x
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Register addressing mode only  
.7  
Carry Flag (C)  
0
0
Operation does not generate a carry or borrow condition  
Operation generates carry-out or borrow into high-order bit 7  
.6  
.5  
Zero Flag (Z)  
Operation result is a non-zero value  
Operation result is zero  
0
0
Sign Flag (S)  
0
0
Operation generates positive number (MSB = "0")  
Operation generates negative number (MSB = "1")  
R = Read-only  
W = Write-only  
R/W = Read/write  
'-' = Not used  
Description of the  
effect of specific  
bit settings  
Bit number:  
MSB = Bit 7  
LSB = Bit 0  
Type of addressing  
that must be used to  
address the bit  
nRESET value notation:  
'-' = Not used  
'x' = Undetermined value  
(1-bit, 4-bit, or 8-bit)  
'0' = Logic zero  
'1' = Logic one  
Figure 4-1. Register Description Format  
4-4  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
ADCON— A/D Converter Control Register  
F7H  
Set 1, Bank 1  
Bit Identifier  
.7  
–
.6  
0
.5  
0
.4  
0
.3  
0
.2  
.1  
0
.0  
0
nRESET Value  
Read/Write  
0
–
R/W  
R/W  
R/W  
R
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
Not used for the S3C8245/C8249  
A/D Input Pin Selection Bits  
.7  
.6–.4  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ADC0  
ADC1  
ADC2  
ADC3  
ADC4  
ADC5  
ADC6  
ADC7  
.3  
End-of-Conversion bit (read-only)  
0
1
Conversion not complete  
Conversion complete  
.2–.1  
Clock Source Selection Bits  
0
0
1
1
0
1
0
1
fxx/16  
fxx/8  
fxx/4  
fxx  
.0  
Start or Enable Bit  
0
1
Disable operation  
Start operation  
4-5  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
BTCON— Basic Timer Control Register  
D3H  
Set 1  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
nRESET Value  
Read/Write  
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.4  
.3–.2  
Watchdog Timer Function Disable Code (for System Reset)  
1
0
1
0
Disable watchdog timer function  
Enable watchdog timer function  
Others  
Basic Timer Input Clock Selection Bits  
(3)  
0
0
fxx/4096  
fxx/1024  
fxx/128  
fxx/16  
0
1
1
1
0
1
(1)  
.1  
Basic Timer Counter Clear Bit  
0
1
No effect  
Clear the basic timer counter value  
(2)  
.0  
Clock Frequency Divider Clear Bit for Basic Timer and Timer/Counters  
0
1
No effect  
Clear both clock frequency dividers  
NOTES:  
1. When you write a “1” to BTCON.1, the basic timer counter value is cleared to "00H". Immediately following the write  
operation, the BTCON.1 value is automatically cleared to “0”.  
2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to "00H". Immediately following the  
write operation, the BTCON.0 value is automatically cleared to "0".  
3. The fxx is selected clock for system (main OSC. or sub OSC.).  
4-6  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
CLKCON— System Clock Control Register  
D4H  
Set 1  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
–
–
–
R/W  
R/W  
–
–
–
Addressing Mode  
Register addressing mode only  
Not used for the S3C8245/C8249  
.7–.5  
.4–.3  
(note)  
CPU Clock (System Clock) Selection Bits  
0
0
1
1
0
1
0
1
fxx/16  
fxx/8  
fxx/2  
fxx  
.2–.0  
Not used for the S3C8245/C8249  
NOTE: After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load  
the appropriate values to CLKCON.3 and CLKCON.4.  
4-7  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
EMT— External Memory Timing Register  
FEH  
Set 1, Bank 0  
Bit Identifier  
.7  
0
.6  
–
.5  
–
.4  
–
.3  
–
.2  
–
.1  
–
.0  
–
nRESET Value  
Read/Write  
–
–
–
–
–
–
–
–
Addressing Mode  
Register addressing mode only  
Not used for the S3C8245/C8249  
.7–.0  
4-8  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
FLAGS — System Flags Register  
D5H  
Set 1  
Bit Identifier  
.7  
x
.6  
x
.5  
x
.4  
x
.3  
x
.2  
x
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R
R/W  
Addressing Mode  
Register addressing mode only  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
Carry Flag (C)  
0
1
Operation does not generate a carry or borrow condition  
Operation generates a carry-out or borrow into high-order bit 7  
Zero Flag (Z)  
0
1
Operation result is a non-zero value  
Operation result is zero  
Sign Flag (S)  
0
1
Operation generates a positive number (MSB = "0")  
Operation generates a negative number (MSB = "1")  
Overflow Flag (V)  
0
1
Operation result is £ +127 or ³ –128  
Operation result is > +127 or < –128  
Decimal Adjust Flag (D)  
0
1
Add operation completed  
Subtraction operation completed  
Half-Carry Flag (H)  
0
1
No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction  
Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3  
Fast Interrupt Status Flag (FIS)  
0
1
Interrupt return (IRET) in progress (when read)  
Fast interrupt service routine in progress (when read)  
Bank Address Selection Flag (BA)  
0
1
Bank 0 is selected  
Bank 1 is selected  
4-9  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
IMR— Interrupt Mask Register  
DDH  
Set 1  
Bit Identifier  
.7  
x
.6  
x
.5  
x
.4  
x
.3  
x
.2  
x
.1  
x
.0  
nRESET Value  
Read/Write  
x
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7  
.6  
.5  
.4  
.3  
Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.4–0.7  
Disable (mask)  
0
1
Enable (unmask)  
Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.0–0.3  
Disable (mask)  
0
1
Enable (unmask)  
Interrupt Level 5 (IRQ5) Enable Bit; Watch Timer Overflow  
0
1
Disable (mask)  
Enable (unmask)  
Interrupt Level 4 (IRQ4) Enable Bit; SIO Interrupt  
0
1
Disable (mask)  
Enable (unmask)  
Interrupt Level 3 (IRQ3) Enable Bit; Timer 1 Match/Capture or Overflow  
0
1
Disable (mask)  
Enable (unmask)  
.2  
.1  
.0  
Interrupt Level 2 (IRQ2) Enable Bit; Timer 0 Match  
0
1
Disable (mask)  
Enable (unmask)  
Interrupt Level 1 (IRQ1) Enable Bit; Timer B Match  
0
1
Disable (mask)  
Enable (unmask)  
Interrupt Level 0 (IRQ0) Enable Bit; Timer A Match/Capture or Overflow  
0
1
Disable (mask)  
Enable (unmask)  
NOTE: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.  
4-10  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
INTPND— Interrupt Pending Register  
D2H  
Set 1  
Bit Identifier  
.7  
–
.6  
–
.5  
–
.4  
–
.3  
–
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
–
–
–
–
–
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
Not used for the S3C8245/C8249  
.7–.3  
.2  
Timer 1 Overflow Interrupt Pending Bit  
Interrupt request is not pending, pending bit clear when write 0  
Interrupt request is pending  
0
1
.1  
.0  
Timer 1 Match/Capture Interrupt Pending Bit  
0
1
Interrupt request is not pending, pending bit clear when write 0  
Interrupt request is pending  
Timer A Overflow Interrupt Pending bit  
0
1
Interrupt request is not pending, pending bit clear when write 0  
Interrupt request is pending  
4-11  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
IPH— Instruction Pointer (High Byte)  
DAH  
Set 1  
Bit Identifier  
.7  
x
.6  
x
.5  
x
.4  
x
.3  
x
.2  
x
.1  
x
.0  
x
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.0  
Instruction Pointer Address (High Byte)  
The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction  
pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL  
register (DBH).  
IPL — Instruction Pointer (Low Byte)  
DBH  
Set 1  
Bit Identifier  
.7  
x
.6  
x
.5  
x
.4  
x
.3  
x
.2  
x
.1  
x
.0  
nRESET Value  
Read/Write  
x
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.0  
Instruction Pointer Address (Low Byte)  
The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction  
pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH  
register (DAH).  
4-12  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
IPR— Interrupt Priority Register  
FFH  
Set 1, Bank 0  
Bit Identifier  
.7  
x
.6  
x
.5  
x
.4  
x
.3  
x
.2  
x
.1  
x
.0  
x
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7, .4, and .1  
Priority Control Bits for Interrupt Groups A, B, and C  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Group priority undefined  
B > C > A  
A > B > C  
B > A > C  
C > A > B  
C > B > A  
A > C > B  
Group priority undefined  
.6  
.5  
.3  
.2  
.0  
Interrupt Subgroup C Priority Control Bit  
0
1
IRQ6 > IRQ7  
IRQ7 > IRQ6  
Interrupt Group C Priority Control Bit  
0
1
IRQ5 > (IRQ6, IRQ7)  
(IRQ6, IRQ7) > IRQ5  
Interrupt Subgroup B Priority Control Bit  
0
1
IRQ3 > IRQ4  
IRQ4 > IRQ3  
Interrupt Group B Priority Control Bit  
0
1
IRQ2 > (IRQ3, IRQ4)  
(IRQ3, IRQ4) > IRQ2  
Interrupt Group A Priority Control Bit  
0
1
IRQ0 > IRQ1  
IRQ1 > IRQ0  
4-13  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
IRQ— Interrupt Request Register  
DCH  
Set 1  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R
R
R
R
R
R
R
R
Addressing Mode  
Register addressing mode only  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.4–0.7  
0
1
Not pending  
Pending  
Level 6 (IRQ6) Request Pending Bit; External Interrupts P0.0–0.3  
0
1
Not pending  
Pending  
Level 5 (IRQ5) Request Pending Bit; Watch Timer Overflow  
0
1
Not pending  
Pending  
Level 4 (IRQ4) Request Pending Bit; SIO Interrupt  
0
1
Not pending  
Pending  
Level 3 (IRQ3) Request Pending Bit; Timer 1 Match/Capture or Overflow  
0
1
Not pending  
Pending  
Level 2 (IRQ2) Request Pending Bit; Timer 0 Match  
0
1
Not pending  
Pending  
Level 1 (IRQ1) Request Pending Bit; Timer B Match  
0
1
Not pending  
Pending  
Level 0 (IRQ0) Request Pending Bit; Timer A Match/Capture or Overflow  
0
1
Not pending  
Pending  
4-14  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
LCON — LCD Control Register  
D0H  
Set 1  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
–
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7  
.6  
.5  
.4  
LCD Output Segment and Pin Configuration Bits  
0
1
P5.4–P5.7 I/O is selected  
SEG28–SEG31 is selected, P5.4–P5.7 I/O is disabled  
LCD Output Segment and Pin Configuration Bits  
0
1
P5.0–P5.3 I/O is selected  
SEG24–SEG27 is selected, P5.0–P5.3 I/O is disabled  
LCD Output Segment and Pin Configuration Bits  
0
1
P4.4–P4.7 I/O is selected  
SEG20–EG23 is selected, P4.4–P4.7 I/O is disabled  
LCD Output Segment and Pin Configuration Bits  
0
1
P4.0–P4.3 I/O is selected  
SEG16–SEG19 is selected, P4.0–P4.3 I/O is disabled  
.3  
.2  
Not used for the S3C8245/C8249  
LCD Bias Voltage Selection Bit  
0
1
Enable LCD initial circuit (internal bias voltage)  
Disable LCD initial circuit for external LCD driving resister (external bias voltage)  
.1  
.0  
Voltage Booster Enable/disable Bit  
0
1
Stop voltage booster (Clock stop and cut off current charge path)  
Run voltage booster (Clock run current and turn on charge path)  
LCD Display Control Bit  
0
LCD output low; turn display off, COM and SEG output low cut off voltage booster  
(Booster clock disable)  
4-15  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
1
COM and SEG output is in display mode; turn display on  
4-16  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
LMOD — LCD Mode Control Register  
D1H  
Set 1  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
–
–
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
Not used for the S3C8245/C8249  
.7–.6  
.5–.4  
LCD Clock (LCDCK) Frequency Selection Bits  
9
0
0
1
1
0
1
0
1
32.768 kHz watch timer clock (fw)/2 = 64 Hz  
8
32.768 kHz watch timer clock (fw)/2 = 128 Hz  
7
32.768 kHz watch timer clock (fw)/2 = 256 Hz  
6
32.768 kHz watch timer clock (fw)/2 = 512 Hz  
.3–.0  
Duty and Bias Selection for LCD Display  
0
1
1
1
1
1
x
0
0
0
0
1
x
0
0
1
1
x
x
0
1
1
0
x
LCD display off (COM and SEG output low)  
1/4 duty, 1/3 bias  
1/3 duty, 1/3 bias  
1/3 duty, 1/2 bias  
1/2 duty, 1/2 bias  
Static  
4-17  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
OSCCON — Oscillator Control Register  
F3H  
Set 1,Bank 0  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
.0  
0
nRESET Value  
Read/Write  
0
–
–
–
–
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
Not used for the S3C8245/C8249  
.7–.5  
.4  
Sub-system Oscillator Driving Ability Control Bit  
0
1
Strong driving ability  
Normal driving ability  
.3  
.2  
Main System Oscillator Control Bit  
0
1
Main System Oscillator RUN  
Main System Oscillator STOP  
Sub System Oscillator Control Bit  
0
1
Sub system oscillator RUN  
Sub system oscillator STOP  
.1  
.0  
Not used for the S3C8245/C8249  
System Clock Selection Bit  
0
1
Main oscillator select  
Subsystem oscillator select  
NOTE: When OSCCON.4 is set to "0", Sub operating current and sub idle current are large.  
4-18  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
P0CONH— Port 0 Control Register (High Byte)  
E0H Set 1,Bank 0  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.6  
.5–.4  
.3–.2  
.1–.0  
P0.7/INT7  
0
0
1
1
0
1
0
1
Schmitt trigger input mode; pull-up ; interrupt on falling edge  
Schmitt trigger input mode; interrupt on rising edge  
Schmitt trigger input mode; interrupt on rising or falling edge  
Output mode, push-pull  
P0.6/INT6  
0
0
1
1
0
1
0
1
Schmitt trigger input mode; pull-up ; interrupt on falling edge  
Schmitt trigger input mode; interrupt on rising edge  
Schmitt trigger input mode; interrupt on rising or falling edge  
Output mode, push-pull  
P0.5/INT5  
0
0
1
1
0
1
0
1
Schmitt trigger input mode; pull-up ; interrupt on falling edge  
Schmitt trigger input mode; interrupt on rising edge  
Schmitt trigger input mode; interrupt on rising or falling edge  
Output mode, push-pull  
P0.4/INT4  
0
0
1
1
0
1
0
1
Schmitt trigger input mode; pull-up ; interrupt on falling edge  
Schmitt trigger input mode; interrupt on rising edge  
Schmitt trigger input mode; interrupt on rising or falling edge  
Output mode, push-pull  
4-19  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
P0CONL — Port 0 Control Register (Low Byte)  
E1H  
Set 1, Bank 0  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.6  
.5–.4  
.3–.2  
.1–.0  
P0.3/INT3  
0
0
1
1
0
1
0
1
Schmitt trigger input mode; pull-up ; interrupt on falling edge  
Schmitt trigger input mode; interrupt on rising edge  
Schmitt trigger input mode; interrupt on rising or falling edge  
Output mode, push-pull  
P0.2/INT2  
0
0
1
1
0
1
0
1
Schmitt trigger input mode; pull-up ; interrupt on falling edge  
Schmitt trigger input mode; interrupt on rising edge  
Schmitt trigger input mode; interrupt on rising or falling edge  
Output mode, push-pull  
P0.1/INT1  
0
0
1
1
0
1
0
1
Schmitt trigger input mode; pull-up ; interrupt on falling edge  
Schmitt trigger input mode; interrupt on rising edge  
Schmitt trigger input mode; interrupt on rising or falling edge  
Output mode, push-pull  
P0.0/INT0  
0
0
1
1
0
1
0
1
Schmitt trigger input mode; pull-up ; interrupt on falling edge  
Schmitt trigger input mode; interrupt on rising edge  
Schmitt trigger input mode; interrupt on rising or falling edge  
Output mode, push-pull  
4-20  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
P0INT — Port 0 Interrupt Control Register  
E2H  
Set 1, Bank 0  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
P0.7 External Interrupt (INT7) Enable Bit  
0
1
Disable interrupt  
Enable interrupt  
P0.6 External Interrupt (INT6) Enable Bit  
0
1
Disable interrupt  
Enable interrupt  
P0.5 External Interrupt (INT5) Enable Bit  
0
1
Disable interrupt  
Enable interrupt  
P0.4 External Interrupt (INT4) Enable Bit  
0
1
Disable interrupt  
Enable interrupt  
P0.3 External Interrupt (INT3) Enable Bit  
0
1
Disable interrupt  
Enable interrupt  
P0.2 External Interrupt (INT2) Enable Bit  
0
1
Disable interrupt  
Enable interrupt  
P0.1 External Interrupt (INT1) Enable Bit  
0
1
Disable interrupt  
Enable interrupt  
P0.0 External Interrupt (INT0) Enable Bit  
0
1
Disable interrupt  
Enable interrupt  
4-21  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
P0PND— Port 0 Interrupt Pending Register  
E3H  
Set 1, Bank 0  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
P0.7/INT7 Interrupt Pending Bit  
0
1
Interrupt request is not pending, pending bit clear when write 0  
Interrupt request is pending  
P0.6/INT6 Interrupt Pending Bit  
0
1
Interrupt request is not pending, pending bit clear when write 0  
Interrupt request is pending  
P0.5/INT5 Interrupt Pending Bit  
0
1
Interrupt request is not pending, pending bit clear when write 0  
Interrupt request is pending  
P0.4/INT4 Interrupt Pending Bit  
0
1
Interrupt request is not pending, pending bit clear when write 0  
Interrupt request is pending  
P0.3/INT3 Interrupt Pending Bit  
0
1
Interrupt request is not pending, pending bit clear when write 0  
Interrupt request is pending  
P0.2/INT2 Interrupt Pending Bit  
0
1
Interrupt request is not pending, pending bit clear when write 0  
Interrupt request is pending  
P0.1/INT1 Interrupt Pending Bit  
0
1
Interrupt request is not pending, pending bit clear when write 0  
Interrupt request is pending  
.0  
P0.0/INT0 Interrupt Pending Bit  
4-22  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
0
1
Interrupt request is not pending, pending bit clear when write 0  
Interrupt request is pending  
4-23  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
P1CONH — Port 1 Control Register (High Byte)  
E4H  
Set 1, Bank 0  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.6  
.5–.4  
.3–.2  
.1–.0  
P1.7/SI  
0
0
1
1
0
1
0
1
Input mode (SI)  
Output mode, open-drain  
Alternative function (push-pull output)  
Output mode, push-pull  
P1.6/SCK  
0
0
1
1
0
1
0
1
Input mode (SCK)  
Output mode, open-drain  
Alternative function (SCK out)  
Output mode, push-pull  
P1.5/SO  
0
0
1
1
0
1
0
1
Input mode  
Output mode, open-drain  
Alternative function (SO)  
Output mode, push-pull  
P1.4/BUZ  
0
0
1
1
0
1
0
1
Input mode  
Output mode, open-drain  
Alternative function (BUZ)  
Output mode, push-pull  
4-24  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
P1CONL — Port 1 Control Register (Low Byte)  
E5H  
Set 1, Bank 0  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.6  
.5–.4  
.3–.2  
.1–.0  
P1.3  
0
0
1
1
0
1
0
1
Input mode  
Output mode, open-drain  
Alternative function (push-pull output mode)  
Output mode, push-pull  
P1.2/T1OUT/T1PWM  
0
0
1
1
0
1
0
1
Input mode  
Output mode, open-drain  
Alternative function (T1OUT, T1PWM)  
Output mode, push-pull  
P1.1/T1CLK  
0
0
1
1
0
1
0
1
Input mode (T1CLK)  
Output mode, open-drain  
Alternative function (push-pull output mode)  
Output mode, push-pull  
P1.0/T1CAP  
0
0
1
1
0
1
0
1
Input mode (T1CAP)  
Output mode, open-drain  
Alternative function (push-pull output mode)  
Output mode, push-pull  
4-25  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
P1PUP — Port 1 Pull-up Control Register  
F5H  
Set 1, Bank 0  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
P1.7 Pull-up Resistor Enable Bit  
0
1
Pull-up disable  
Pull-up enable  
P1.6 Pull-up Resistor Enable Bit  
0
1
Pull-up disable  
Pull-up enable  
P1.5 Pull-up Resistor Enable Bit  
0
1
Pull-up disable  
Pull-up enable  
P1.4 Pull-up Resistor Enable Bit  
0
1
Pull-up disable  
Pull-up enable  
P1.3 Pull-up Resistor Enable Bit  
0
1
Pull-up disable  
Pull-up enable  
P1.2 Pull-up Resistor Enable Bit  
0
1
Pull-up disable  
Pull-up enable  
P1.1 Pull-up Resistor Enable Bit  
0
1
Pull-up disable  
Pull-up enable  
P1.0 Pull-up Resistor Enable Bit  
0
1
Pull-up disable  
Pull-up enable  
4-26  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
4-27  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
P2CONH— Port 2 Control Register (High Byte)  
E6H  
Set 1, Bank 0  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.6  
.5-.4  
.3–.2  
.1–.0  
P2.7/VLDREF/ADC7  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Alternative function (ADC & VLD mode)  
Output mode, push-pull  
P2.6/ADC6  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Alternative function (ADC mode)  
Output mode, push-pull  
P2.5/ ADC5  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Alternative function (ADC mode)  
Output mode, push-pull  
P2.4/ ADC4  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Alternative function (ADC mode)  
Output mode, push-pull  
4-28  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
P2CONL — Port 2 Control Register (Low Byte)  
E7H  
Set 1, Bank 0  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.6  
.5–.4  
.3–.2  
.1–.0  
P2.3/ADC3  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Alternative function (ADC mode)  
Output mode, push-pull  
P2.2/ADC2  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Alternative function (ADC mode)  
Output mode, push-pull  
P2.1/ADC1  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Alternative function (ADC mode)  
Output mode, push-pull  
P2.0/ADC0  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Alternative function (ADC mode)  
Output mode, push-pull  
4-29  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
P3CONH— Port 3 Control Register (High Byte)  
E8H  
Set 1, Bank 0  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
–
–
–
–
–
–
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
Not used for the S3C8245/C8249  
P3.4 Mode Selection Bits  
.7–.2  
.1–.0  
0
0
1
0
1
x
Input mode  
Input mode, pull-up  
Output mode, push-pull  
4-30  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
P3CONL — Port 3 Control Register (Low Byte)  
E9H  
Set 1, Bank 0  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.6  
.5–.4  
.3–.2  
.1–.0  
P3.3/TACAP Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode (TACAP)  
Input mode, pull-up (TACAP)  
Output mode, push-pull  
Output mode, push-pull  
P3.2/TACLK Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode (TACLK)  
Input mode, pull-up  
Output mode, push-pull  
Output mode, push-pull  
P3.1/TAOUT/TAPWM Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Alternative function (TAOUT or TAPWM)  
Output mode, push-pull  
P3.0/TBPWM Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Alternative function (TBPWM)  
Output mode, push-pull  
4-31  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
P4CONH— Port 4 Control Register (High Byte)  
ECH  
Set 1, Bank 1  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.6  
.5–.4  
.3–.2  
.1–.0  
P4.7/SEG23 Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Open-drain output mode  
Push-pull output mode  
P4.6/SEG22 Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Open-drain output mode  
Push-pull output mode  
P4.5/SEG21 Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Open-drain output mode  
Push-pull output mode  
P4.4/SEG20 Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Open-drain output mode  
Push-pull output mode  
4-32  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
P4CONL — Port 4 Control Register (Low Byte)  
EDH  
Set 1, Bank 1  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.6  
.5–.4  
.3–.2  
.1–.0  
P4.3/SEG19 Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Open-drain output mode  
Push-pull output mode  
P4.2/SEG18 Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Open-drain output mode  
Push-pull output mode  
P4.1/SEG17 Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Open-drain output mode  
Push-pull output mode  
P4.0/SEG16 Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Open-drain output mode  
Push-pull output mode  
4-33  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
P5CONH— Port 5 Control Register (High Byte)  
EEH  
Set 1, Bank 1  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.6  
.5–.4  
.3–.2  
.1–.0  
P5.7/SEG31 Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Open-drain output mode  
Push-pull output mode  
P5.6/SEG30 Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Open-drain output mode  
Push-pull output mode  
P5.5/ SEG29 Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Open-drain output mode  
Push-pull output mode  
P5.4/ SEG28 Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Open-drain output mode  
Push-pull output mode  
4-34  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
P5CONL — Port 5 Control Register (Low Byte)  
EFH  
Set 1, Bank 1  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.6  
.5–.4  
.3–.2  
.1–.0  
P5.3/SEG27 Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Open-drain output mode  
Push-pull output mode  
P5.2/SEG26 Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Open-drain output mode  
Push-pull output mode  
P5.1/SEG25 Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Open-drain output mode  
Push-pull output mode  
P5.0/SEG24 Mode Selection Bits  
0
0
1
1
0
1
0
1
Input mode  
Input mode, pull-up  
Open-drain output mode  
Push-pull output mode  
4-35  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
PP— Register Page Pointer  
DFH  
Set 1  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
nRESET Value  
Read/Write  
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.4  
Destination Register Page Selection Bits  
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Destination: page 0  
Destination: page 1  
Destination: page 2  
Destination: page 3  
Destination: page 4  
.3 – .0  
Source Register Page Selection Bits  
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Source: page 0  
Source: page 1  
Source: page 2  
Source: page 3  
Source: page 4  
NOTE: In the S3CC8249 microcontroller, the internal register file is configured as five pages (Pages 0-4).  
The pages 0-3 are used for general purpose register file, and page 4 is used for LCD data register or general  
purpose registers.  
In case of S3C8245, pages 0-1 are used for general purpose and page 2 is used for LCD data register  
or general purpose registers.  
4-36  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
RP0— Register Pointer 0  
D6H  
Set 1  
Bit Identifier  
.7  
1
.6  
1
.5  
0
.4  
0
.3  
0
.2  
–
.1  
–
.0  
–
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
–
–
–
Addressing Mode  
Register addressing only  
.7–.3  
Register Pointer 0 Address Value  
Register pointer 0 can independently point to one of the 256-byte working register  
areas in the register file. Using the register pointers RP0 and RP1, you can select two  
8-byte register slices at one time as active working register space. After a reset, RP0  
points to address C0H in register set 1, selecting the 8-byte working register slice  
C0H–C7H.  
.2–.0  
Not used for the S3C8245/C8249  
RP1— Register Pointer 1  
D7H  
Set 1  
Bit Identifier  
.7  
1
.6  
1
.5  
0
.4  
0
.3  
1
.2  
–
.1  
–
.0  
–
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
–
–
–
Addressing Mode  
Register addressing only  
.7 – .3  
Register Pointer 1 Address Value  
Register pointer 1 can independently point to one of the 256-byte working register  
areas in the register file. Using the register pointers RP0 and RP1, you can select two  
8-byte register slices at one time as active working register space. After a reset, RP1  
points to address C8H in register set 1, selecting the 8-byte working register slice  
C8H–CFH.  
.2 – .0  
Not used for the S3C8245/C8249  
4-37  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
SIOCON— SIO Control Register  
FOH  
Set 1, Bank 0  
Bit Identifier  
.7  
1
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
SIO Shift Clock Selection Bit  
.7  
.6  
.5  
.4  
0
1
Internal clock (P.S clock)  
External clock (SCK)  
Data Direction Control Bit  
0
1
MSB-first mode  
LSB-first mode  
SIO Mode Selection Bit  
0
1
Receive-only mode  
Transmit/receive mode  
Shift Clock Edge Selection Bit  
0
1
Tx at falling edges, Rx at rising edges  
Tx at rising edges, Rx at falling edges  
SIO Counter Clear and Shift Start Bit  
.3  
.2  
.1  
.0  
0
1
No action  
Clear 3-bit counter and start shifting  
SIO Shift Operation Enable Bit  
0
1
Disable shifter and clock counter  
Enable shifter and clock counter  
SIO Interrupt Enable Bit  
0
1
Disable SIO Interrupt  
Enable SIO Interrupt  
SIO Interrupt Pending Bit  
0
0
1
No interrupt pending  
Clear pending condition (when write)  
Interrupt is pending  
4-38  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
SPH— Stack Pointer (High Byte)  
D8H  
Set 1  
Bit Identifier  
.7  
x
.6  
x
.5  
x
.4  
x
.3  
x
.2  
x
.1  
x
.0  
x
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.0  
Stack Pointer Address (High Byte)  
The high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer  
address (SP15–SP8). The lower byte of the stack pointer value is located in register  
SPL (D9H). The SP value is undefined following a reset.  
SPL — Stack Pointer (Low Byte)  
D9H  
Set 1  
Bit Identifier  
.7  
x
.6  
x
.5  
x
.4  
x
.3  
x
.2  
x
.1  
x
.0  
nRESET Value  
Read/Write  
x
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.0  
Stack Pointer Address (Low Byte)  
The low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer  
address (SP7–SP0). The upper byte of the stack pointer value is located in register  
SPH (D8H). The SP value is undefined following a reset.  
4-39  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
STPCON— Stop Control Register  
F4H  
Set 1, Bank 0  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.0  
STOP Control Bits  
1 0 1 0 0 1 0 1 Enable stop instruction  
Other values Disable stop instruction  
NOTE: Before execute the STOP instruction, You must set this STPCON register as “10100101b”. Otherwise the STOP  
instruction will not execute.  
4-40  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
SYM — System Mode Register  
DEH  
Set 1  
Bit Identifier  
.7  
0
.6  
–
.5  
–
.4  
x
.3  
x
.2  
x
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
–
–
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
Not used, But you must keep "0"  
Not used for the S3C8245/C8249  
.7  
.6–.5  
.4–.2  
(1)  
Fast Interrupt Level Selection Bits  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IRQ0  
IRQ1  
IRQ2  
IRQ3  
IRQ4  
IRQ5  
IRQ6  
IRQ7  
(2)  
.1  
Fast Interrupt Enable Bit  
0
1
Disable fast interrupt processing  
Enable fast interrupt processing  
(3)  
.0  
Global Interrupt Enable Bit  
0
1
Disable all interrupt processing  
Enable all interrupt processing  
NOTES:  
1. You can select only one interrupt level at a time for fast interrupt processing.  
2. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2–SYM.4.  
3. Following a reset, you must enable global interrupt processing by executing an EI instruction  
(not by writing a "1" to SYM.0).  
4-41  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
T0CON— Timer 0 Control Register  
F1H  
Set 1, Bank 1  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
–
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
–
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.5  
Timer 0 Input Clock Selection Bits  
0
0
1
1
x
0
1
0
1
x
0
0
0
0
1
TBOF (T-FF)  
fxx/256  
fxx/64  
fxx/8  
fxx  
.4  
.3  
Not used for the S3C8245/C8249  
Timer 0 Counter Clear Bit  
0
1
No effect  
Clear the timer 0 counter (when write)  
.2  
.1  
.0  
Timer 0 Counter Enable Bit  
0
1
Disable counting operation  
Enable counting operation  
Timer 0 Interrupt Enable Bit  
0
1
Disable timer 0 interrupt  
Enable timer 0 interrupt  
Timer 0 Interrupt Pending Bit  
0
0
1
No timer 0 interrupt pending (when read)  
Clear timer 0 interrupt pending condition (when write)  
T0 interrupt is pending  
4-42  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
T1CON— Timer 1 Control Register  
FBH  
Set 1, Bank 1  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.5  
Timer 1 Input Clock Selection Bits  
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
fxx/1024  
fxx/256  
fxx/64  
fxx/8  
fxx/1  
External clock (T1CLK) falling edge  
External clock (T1CLK) rising edge  
Counter stop  
.4–.3  
Timer 1 Operating Mode Selection Bits  
0
0
1
1
0
1
0
1
Interval mode  
Capture mode (Capture on rising edge, counter running, OVF can occur)  
Capture mode (Capture on falling edge, counter running, OVF can occur)  
PWM mode (OVF & match interrupt can occur)  
.2  
.1  
.0  
Timer 1 Counter Enable Bit  
0
1
No effect  
Clear the timer 1 counter (when write)  
Timer 1 Match/Capture Interrupt Enable Bit  
0
1
Disable interrupt  
Enable interrupt  
Timer 1 Overflow Interrupt Enable  
0
1
Disable overflow interrupt  
Enable overflow interrupt  
4-43  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
TACON— Timer A Control Register  
EDH  
Set 1, Bank 0  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.6  
Timer A Input Clock Selection Bits  
0
0
1
1
0
1
0
1
fxx/1024  
fxx/256  
fxx/64  
External clock (TACLK)  
.5–.4  
Timer A Operating Mode Selection Bits  
0
0
1
1
0
1
0
1
Internal mode (TAOUT mode)  
Capture mode (capture on rising edge, counter running, OVF can occur)  
Capture mode (capture on falling edge, counter running, OVF can occur)  
PWM mode (OVF interrupt can occur)  
.3  
.2  
.1  
.0  
Timer A Counter Clear Bit  
0
1
No effect  
Clear the timer A counter (when write)  
Timer A Overflow Interrupt Enable Bit  
0
1
Disable overflow interrupt  
Enable overflow interrupt  
Timer A Match/Capture Interrupt Enable Bit  
0
1
Disable interrupt  
Enable interrupt  
Timer A Match/Capture Interrupt Pending Bit  
0
0
1
No interrupt pending  
Clear pending bit (write)  
Interrupt is pending  
4-44  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
TBCON— Timer B Control Register  
ECH  
Set 1, Bank 0  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7–.6  
Timer B Input Clock Selection Bits  
0
0
1
1
0
1
0
1
fxx  
fxx/2  
fxx/4  
fxx/8  
.5–.4  
Timer B Interrupt Time Selection Bits  
0
0
1
1
0
1
0
1
Elapsed time for low data value  
Elapsed time for high data value  
Elapsed time for low and high data values  
Invalid setting  
.3  
.2  
.1  
.0  
Timer B Interrupt Enable Bit  
0
1
Disable Interrupt  
Enable Interrupt  
Timer B Start/Stop Bit  
0
1
Stop timer B  
Start timer B  
Timer B Mode Selection Bit  
0
1
One-shot mode  
Repeating mode  
Timer B Output flip-flop Control Bit  
0
1
T-FF is low  
T-FF is high  
NOTE: fxx is selected clock for system.  
4-45  
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CONTROL REGISTERS  
S3C8245/P8245/C8249/P8249  
VLDCON— Voltage Level Detector Control Register  
F6H  
Set 1, Bank 1  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
–
–
–
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
Not used for the S3C8245/C8249  
.7–.5  
.4  
V
Source Bit  
IN  
0
Internal source  
External source  
1
.3  
VLD Output Bit  
0
1
V
V
> V  
< V  
(when VLD is enabled)  
(when VLD is enabled)  
IN  
IN  
REF  
REF  
.2  
VLD Enable/disable Bit  
0
1
Disable the VLD  
Enable the VLD  
.1–.0  
Detection Level Bits  
0
0
1
1
0
1
0
1
V
V
V
V
= 2.2 V  
= 2.4 V  
= 3.0 V  
= 4.0 V  
VLD  
VLD  
VLD  
VLD  
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S3C8245/P8245/C8249/P8249  
CONTROL REGISTER  
WTCON— Watch Timer Control Register  
FAH  
Set 1, Bank 1  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
nRESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Addressing Mode  
Register addressing mode only  
.7  
Watch Timer Clock Selection Bit  
7
0
1
Main system clock divided by 2 (fxx/128)  
Sub system clock (fxt)  
.6  
Watch Timer Interrupt Enable Bit  
0
1
Disable watch timer interrupt  
Enable watch timer interrupt  
.5–.4  
Buzzer Signal Selection Bits  
0
0
1
1
0
1
0
1
0.5 kHz buzzer (BUZ) signal output  
1 kHz buzzer (BUZ) signal output  
2 kHz buzzer (BUZ) signal output  
4 kHz buzzer (BUZ) signal output  
.3–.2  
Watch Timer Speed Selection Bits  
0
0
1
1
0
1
0
1
0.5 s Interval  
0.25 s Interval  
0.125 s Interval  
1.955 ms Interval  
.1  
.0  
Watch Timer Enable Bit  
0
1
Disable watch timer; Clear frequency dividing circuits  
Enable watch timer  
Watch Timer Interrupt Pending Bit  
0
1
Interrupt is not pending, clear pending bit when write  
Interrupt is pending  
NOTE: Watch timer clock frequency(fw) is assumed to be 32.768 kHz.  
4-47  
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S3C8245/P8245/C8249/P8249  
INTERRUPT STRUCTURE  
5
INTERRUPT STRUCTURE  
OVERVIEW  
The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8 CPU  
recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has  
more than one vector address, the vector priorities are established in hardware. A vector address can be assigned to  
one or more sources.  
Levels  
Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks can  
issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight possible  
interrupt levels: IRQ0–IRQ7, also called level 0–level 7. Each interrupt level directly corresponds to an interrupt  
request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from device to  
device. The S3C8245/C8249 interrupt structure recognizes eight interrupt levels.  
The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just  
identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels is  
determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by IPR  
settings lets you define more complex priority relationships between different levels.  
Vectors  
Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. The  
maximum number of vectors that can be supported for a given level is 128 (The actual number of vectors used for  
S3C8-series devices is always much smaller). If an interrupt level has more than one vector address, the vector  
priorities are set in hardware. S3C8245/C8249 uses sixteen vectors.  
Sources  
A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow. Each  
vector can have several interrupt sources. In the S3C8245/C8249 interrupt structure, there are sixteen possible  
interrupt sources.  
When a service routine starts, the respective pending bit should be either cleared automatically by hardware or  
cleared "manually" by program software. The characteristics of the source's pending mechanism determine which  
method would be used to clear its respective pending bit.  
5-1  
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INTERRUPT STRUCTURE  
INTERRUPT TYPES  
S3C8245/P8245/C8249/P8249  
The three components of the S3C8 interrupt structure described before — levels, vectors, and sources — are  
combined to determine the interrupt structure of an individual device and to make full use of its available interrupt  
logic. There are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3. The  
types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1):  
Type 1:  
Type 2:  
Type 3:  
One level (IRQn) + one vector (V ) + one source (S )  
1
1
One level (IRQn) + one vector (V ) + multiple sources (S – S )  
1
1
n
One level (IRQn) + multiple vectors (V – V ) + multiple sources (S – S , S  
– S  
)
n+m  
1
n
1
n
n+1  
In the S3C8245/C8249 microcontroller, two interrupt types are implemented.  
Levels  
Vectors  
Sources  
Type 1:  
Type 2:  
IRQn  
V
1
S
S
S
S
S
S
S
S
S
1
1
2
3
n
1
2
3
n
IRQn  
IRQn  
V
1
V
V
V
V
1
2
3
n
Type 3:  
NOTES:  
Sn +  
Sn +  
Sn +  
1
2
1. The number of Sn and Vn value is expandable.  
2. In the S3C8245/C8249 implementation,  
interrupt types 1 and 3 are used.  
m
Figure 5-1. S3C8-Series Interrupt Types  
5-2  
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S3C8245/P8245/C8249/P8249  
INTERRUPT STRUCTURE  
S3C8245/C8249 INTERRUPT STRUCTURE  
The S3C8245/C8249 microcontroller supports sixteen interrupt sources. All sixteen of the interrupt sources have a  
corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this device-specific  
interrupt structure, as shown in Figure 5-2.  
When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which contending  
interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt with the lowest  
vector address is usually processed first (The relative priorities of multiple interrupts within a single level are fixed in  
hardware).  
When the CPU grants an interrupt request, interrupt processing starts. All other interrupts are disabled and the  
program counter value and status flags are pushed to stack. The starting address of the service routine is fetched  
from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service  
routine is executed.  
Levels  
Vectors  
Sources  
Reset/Clear  
E0H  
E2H  
E4H  
E6H  
Timer A match/capture  
Timer A overflow  
Timer B match  
H/W,S/W  
H/W,S/W  
H/W  
IRQ0  
IRQ1  
IRQ2  
Timer 0 match  
H/W,S/W  
E8H  
EAH  
ECH  
EEH  
Timer 1 match/capture  
Timer 1 overflow  
H/W,S/W  
H/W,S/W  
S/W  
IRQ3  
IRQ4  
IRQ5  
SIO interrupt  
Watch timer overflow  
P0.0 external interrupt  
P0.1 external interrupt  
P0.2 external interrupt  
P0.3 external interrupt  
P0.4 external interrupt  
P0.5 external interrupt  
P0.6 external interrupt  
P0.7 external interrupt  
S/W  
F0H  
F2H  
F4H  
F6H  
F8H  
FAH  
FCH  
FEH  
S/W  
S/W  
IRQ6  
S/W  
S/W  
S/W  
S/W  
IRQ7  
S/W  
S/W  
NOTES:  
1. Within a given interrupt level, the low vector address has high priority.  
For example, E0H has higher priority than E2H within the level IRQ.0 the priorities within each  
level are set at the factory.  
2. External interrupts are triggered by a rising or falling edge, depending on the corresponding control  
register setting.  
Figure 5-2. S3C8245/C8249 Interrupt Structure  
5-3  
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INTERRUPT STRUCTURE  
S3C8245/P8245/C8249/P8249  
INTERRUPT VECTOR ADDRESSES  
All interrupt vector addresses for the S3C8245/C8249 interrupt structure are stored in the vector address area of the  
internal 32-Kbyte ROM, 0H–7FFFH, or 8, 16, 24-Kbyte (see Figure 5-3).  
You can allocate unused locations in the vector address area as normal program memory. If you do so, please be  
careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses).  
The program reset address in the ROM is 0100H.  
(Decimal)  
32,767  
(HEX)  
7FFFH  
32-Kbyte  
3FFFH  
16,383  
16-Kbyte  
Internal  
Program Memory  
(ROM) Area  
100H  
FFH  
Reset  
Address  
255  
0
Interrupt  
Vector Address  
Area  
00H  
Figure 5-3. ROM Vector Address Area  
5-4  
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S3C8245/P8245/C8249/P8249  
Vector Address  
INTERRUPT STRUCTURE  
Reset/Clear  
Table 5-1. Interrupt Vectors  
Interrupt Source  
Request  
Decimal  
Value  
Hex  
Value  
Interrupt  
Priority in  
Level  
H/W  
S/W  
Level  
Reset  
IRQ0  
256  
226  
224  
228  
230  
234  
232  
236  
238  
246  
244  
242  
240  
254  
252  
250  
248  
100H  
E2H  
E0H  
E4H  
E6H  
EAH  
E8H  
ECH  
EEH  
F6H  
F4H  
F2H  
F0H  
FEH  
FCH  
FAH  
F8H  
Basic timer overflow  
–
0
1
–
–
0
1
–
–
3
2
1
0
3
2
1
0
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Timer A overflow  
Ö
Ö
Timer A match/capture  
Timer B match  
IRQ1  
IRQ2  
IRQ3  
Timer 0 match  
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Timer 1 overflow  
Timer 1 match/capture  
SIO interrupt  
IRQ4  
IRQ5  
IRQ6  
Watch timer overflow  
P0.3 external interrupt  
P0.2 external interrupt  
P0.1 external interrupt  
P0.0 external interrupt  
P0.7 external interrupt  
P0.6 external interrupt  
P0.5 external interrupt  
P0.4 external interrupt  
IRQ7  
NOTES:  
1. Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on.  
2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority  
over one with a higher vector address. The priorities within a given level are fixed in hardware.  
3. Timer A or Timer 1 can not service two interrupt sources simultaneously, then only one interrupt source have to be  
used.  
5-5  
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INTERRUPT STRUCTURE  
S3C8245/P8245/C8249/P8249  
ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)  
Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then  
serviced as they occur according to the established priorities.  
NOTE  
The system initialization routine executed after a reset must always contain an EI instruction to globally  
enable the interrupt structure.  
During the normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable  
interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register.  
SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS  
In addition to the control registers for specific interrupt sources, four system-level registers control interrupt  
processing:  
— The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels.  
— The interrupt priority register, IPR, controls the relative priorities of interrupt levels.  
— The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to each  
interrupt source).  
— The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable fast  
interrupts and control the activity of external interface, if implemented).  
Table 5-2. Interrupt Control Register Overview  
Control Register  
ID  
R/W  
Function Description  
Interrupt mask register  
IMR  
R/W  
Bit settings in the IMR register enable or disable interrupt  
processing for each of the eight interrupt levels: IRQ0–IRQ7.  
Interrupt priority register  
IPR  
R/W  
Controls the relative processing priorities of the interrupt levels.  
The seven levels of S3C8245/C8249 are organized into three  
groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is  
IRQ2, IRQ3 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7.  
Interrupt request register  
System mode register  
IRQ  
R
This register contains a request pending bit for each interrupt  
level.  
SYM  
R/W  
This register enables/disables fast interrupt processing,  
dynamic global interrupt processing, and external interface  
control (An external memory interface is implemented in the  
S3C8245/C8249 microcontroller).  
NOTE: Before IMR register is changed to any value, all interrupts must be disable. Using DI instruction is recommended.  
5-6  
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S3C8245/P8245/C8249/P8249  
INTERRUPT STRUCTURE  
INTERRUPT PROCESSING CONTROL POINTS  
Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The  
system-level control points in the interrupt structure are:  
— Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 )  
— Interrupt level enable/disable settings (IMR register)  
— Interrupt level priority settings (IPR register)  
— Interrupt source enable/disable settings in the corresponding peripheral control registers  
NOTE  
When writing an application program that handles interrupt processing, be sure to include the necessary  
register file address (register pointer) information.  
EI  
S
R
Q
Interrupt Request Register  
(Read-only)  
Polling  
Cycle  
nRESET  
IRQ0-IRQ7,  
Interrupts  
Interrupt Priority  
Register  
Vector  
Interrupt  
Cycle  
Interrupt Mask  
Register  
Global Interrupt Control (EI,  
DI or SYM.0 manipulation)  
Figure 5-4. Interrupt Function Diagram  
5-7  
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INTERRUPT STRUCTURE  
S3C8245/P8245/C8249/P8249  
PERIPHERAL INTERRUPT CONTROL REGISTERS  
For each interrupt source there is one or more corresponding peripheral control registers that let you control the  
interrupt generated by the related peripheral (see Table 5-3).  
Table 5-3. Interrupt Source Control and Data Registers  
Interrupt Source  
Timer A overflow  
Interrupt Level  
Register(s)  
Location(s) in Set 1  
IRQ0  
TACON  
TACINT  
TADATA  
EDH, bank 0  
EEH, bank 0  
EFH, bank 0  
Timer A match/capture  
Timer B match  
IRQ1  
IRQ2  
TBCON  
TBDATAH, TBDATAL  
ECH, bank 0  
EAH, EBH, bank 0  
Timer 0 match  
T0CON, T0CNTH  
T0CNTL, T0DATAH  
T0DATAL  
F1H, F2H, bank 1  
F3H, F4H, bank 1  
F5H, bank 1  
Timer 1 overflow  
Timer 1 match/capture  
IRQ3  
IRQ4  
T1CON  
FBH, bank 1  
FCH, bank 1  
FDH, bank 1  
FEH, bank 1  
FFH, bank 1  
T1CNTH  
T1CNTL  
T1DATAH  
T1DATAL  
SIO interrupt  
SIOCON  
SIODATA  
SIOPS  
F0H, bank 0  
F1H, bank 0  
F2H, bank 0  
Watch timer overflow  
IRQ5  
IRQ6  
WTCON  
FAH, bank 1  
P0.3 external interrupt  
P0.2 external interrupt  
P0.1 external interrupt  
P0.0 external interrupt  
P0CONL  
P0INT  
P0PND  
E1H, bank 0  
E2H, bank 0  
E3H, bank 0  
P0.7 external interrupt  
P0.6 external interrupt  
P0.5 external interrupt  
P0.4 external interrupt  
IRQ7  
P0CONH  
P0INT  
P0PND  
E0H, bank 0  
E2H, bank 0  
E3H, bank 0  
NOTE: Because the timer 0 overflow interrupt is cleared by hardware, the T0CON register controls only the enable/disable  
functions. The T0CON register contains enable/disable and pending bits for the timer 0 match/capture interrupt.  
5-8  
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S3C8245/P8245/C8249/P8249  
INTERRUPT STRUCTURE  
SYSTEM MODE REGISTER (SYM)  
The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to  
control fast interrupt processing (see Figure 5-5).  
A reset clears SYM.1, and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4–SYM.2, is  
undetermined.  
The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0 value of  
the SYM register. In order to enable interrupt processing an Enable Interrupt (EI) instruction must be included in the  
initialization routine, which follows a reset operation. Although you can manipulate SYM.0 directly to enable and  
disable interrupts during the normal operation, it is recommended to use the EI and DI instructions for this purpose.  
System Mode Register (SYM)  
DEH, Set 1, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Global interrupt enable bit:  
0 = Disable all interrupts processing  
1 = Enable all interrupts processing  
Not used for the S3C8245/C8249  
Fast interrupt level  
selection bits:  
Fast interrupt enable bit:  
0 = Disable fast interrupts processing  
1 = Enable fast interrupts processing  
0 0 0 = IRQ0  
0 0 1 = IRQ1  
0 1 0 = IRQ2  
0 1 1 = IRQ3  
1 0 0 = IRQ4  
1 0 1 = IRQ5  
1 1 0 = IRQ6  
1 1 1 = IRQ7  
Figure 5-5. System Mode Register (SYM)  
5-9  
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INTERRUPT STRUCTURE  
S3C8245/P8245/C8249/P8249  
INTERRUPT MASK REGISTER (IMR)  
The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt  
levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by  
the initialization routine.  
Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of an  
interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's IMR bit  
to "1", interrupt processing for the level is enabled (not masked).  
The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions  
using the Register addressing mode.  
Interrupt Mask Register (IMR)  
DDH, Set 1, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
IRQ0  
IRQ1  
IRQ2  
IRQ3  
IRQ4  
IRQ5  
IRQ6  
IRQ7  
Interrupt level enable bits (7-4, 2-0):  
0 = Disable (mask) interrupt level  
1 = Enable (un-mask) interrupt level  
NOTE:  
Before IMR register is changed to any value, all interrupts must be disable.  
Using DI instruction is recommended.  
Figure 5-6. Interrupt Mask Register (IMR)  
5-10  
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S3C8245/P8245/C8249/P8249  
INTERRUPT STRUCTURE  
INTERRUPT PRIORITY REGISTER (IPR)  
The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in  
the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be  
written to their required settings by the initialization routine.  
When more than one interrupt sources are active, the source with the highest priority level is serviced first. If two  
sources belong to the same interrupt level, the source with the lower vector address usually has the priority (This  
priority is fixed in hardware).  
To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the  
interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register priority  
definitions (see Figure 5-7):  
Group A  
Group B  
Group C  
IRQ0, IRQ1  
IRQ2, IRQ3, IRQ3  
IRQ5, IRQ6, IRQ7  
IPR  
IPR  
IPR  
Group A  
Group B  
Group C  
A1  
A2  
B1  
B2  
C1  
C2  
B21  
B22  
C21  
C22  
IRQ0  
IRQ1  
IRQ2 IRQ3  
IRQ4  
IRQ5 IRQ6  
IRQ7  
Figure 5-7. Interrupt Request Priority Groups  
As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C. For  
example, the setting "001B" for these bits would select the group relationship B > C > A. The setting "101B" would  
select the relationship C > B > A.  
The functions of the other IPR bit settings are as follows:  
— IPR.5 controls the relative priorities of group C interrupts.  
— Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5, 6,  
and 7. IPR.6 defines the subgroup C relationship. IPR.5 controls the interrupt group C.  
— IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.  
5-11  
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INTERRUPT STRUCTURE  
S3C8245/P8245/C8249/P8249  
Interrupt Priority Register (IPR)  
FFH, Set 1, Bank 0, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Group priority:  
D7 D4 D1  
Group A:  
0 = IRQ0 > IRQ1  
1 = IRQ1 > IRQ0  
Group B:  
0 = IRQ2 > (IRQ3, IRQ4)  
1 = (IRQ3, IRQ4) > IRQ2  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 = Undefined  
1 = B > C > A  
0 = A > B > C  
1 = B > A > C  
0 = C > A > B  
1 = C > B > A  
0 = A > C > B  
1 = Undefined  
Subgroup B:  
0 = IRQ3 > IRQ4  
1 = IRQ4 > IRQ3  
Group C:  
0 = IRQ5 > (IRQ6, IRQ7)  
1 = (IRQ6, IRQ7) > IRQ5  
Subgroup C:  
0 = IRQ6 > IRQ7  
1 = IRQ7 > IRQ6  
Figure 5-8. Interrupt Priority Register (IPR)  
5-12  
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S3C8245/P8245/C8249/P8249  
INTERRUPT STRUCTURE  
INTERRUPT REQUEST REGISTER (IRQ)  
You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all  
levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0  
to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued for that level. A  
"1" indicates that an interrupt request has been generated for that level.  
IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of the  
IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific  
interrupt levels. After a reset, all IRQ status bits are cleared to “0”.  
You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing is  
disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can,  
however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events  
occurred while the interrupt structure was globally disabled.  
Interrupt Request Register (IRQ)  
DCH, Set 1, Read-only  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
IRQ0  
IRQ1  
IRQ2  
IRQ3  
IRQ4  
IRQ5  
IRQ6  
IRQ7  
Interrupt level request pending bits:  
0 = Interrupt level is not pending  
1 = Interrupt level is pending  
Figure 5-9. Interrupt Request Register (IRQ)  
5-13  
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INTERRUPT STRUCTURE  
S3C8245/P8245/C8249/P8249  
INTERRUPT PENDING FUNCTION TYPES  
Overview  
There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt  
service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine.  
Pending Bits Cleared Automatically by Hardware  
For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending  
bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be  
serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service routine, and clears  
the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or written by application  
software.  
In the S3C8245/C8249 interrupt structure, the timer 0 overflow interrupt (IRQ0) belongs to this category of interrupts  
in which pending condition is cleared automatically by hardware.  
Pending Bits Cleared by the Service Routine  
The second type of pending bit is the one that should be cleared by program software. The service routine must clear  
the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must be written  
to the corresponding pending bit location in the source’s mode or control register.  
5-14  
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S3C8245/P8245/C8249/P8249  
INTERRUPT STRUCTURE  
INTERRUPT SOURCE POLLING SEQUENCE  
The interrupt request polling and servicing sequence is as follows:  
1. A source generates an interrupt request by setting the interrupt request bit to "1".  
2. The CPU polling procedure identifies a pending condition for that source.  
3. The CPU checks the source's interrupt level.  
4. The CPU generates an interrupt acknowledge signal.  
5. Interrupt logic determines the interrupt's vector address.  
6. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software).  
7. The CPU continues polling for interrupt requests.  
INTERRUPT SERVICE ROUTINES  
Before an interrupt request is serviced, the following conditions must be met:  
— Interrupt processing must be globally enabled (EI, SYM.0 = "1")  
— The interrupt level must be enabled (IMR register)  
— The interrupt level must have the highest priority if more than one levels are currently requesting service  
— The interrupt must be enabled at the interrupt's source (peripheral control register)  
When all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The  
CPU then initiates an interrupt machine cycle that completes the following processing sequence:  
1. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts.  
2. Save the program counter (PC) and status flags to the system stack.  
3. Branch to the interrupt vector to fetch the address of the service routine.  
4. Pass control to the interrupt service routine.  
When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores the  
PC and status flags, setting SYM.0 to "1". It allows the CPU to process the next interrupt request.  
5-15  
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INTERRUPT STRUCTURE  
S3C8245/P8245/C8249/P8249  
GENERATING INTERRUPT VECTOR ADDRESSES  
The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that correspond  
to each level in the interrupt structure. Vectored interrupt processing follows this sequence:  
1. Push the program counter's low-byte value to the stack.  
2. Push the program counter's high-byte value to the stack.  
3. Push the FLAG register values to the stack.  
4. Fetch the service routine's high-byte address from the vector location.  
5. Fetch the service routine's low-byte address from the vector location.  
6. Branch to the service routine specified by the concatenated 16-bit vector address.  
NOTE  
A 16-bit vector address always begins at an even-numbered ROM address within the range of 00H–FFH.  
NESTING OF VECTORED INTERRUPTS  
It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this, you  
must follow these steps:  
1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR).  
2. Load the IMR register with a new mask value that enables only the higher priority interrupt.  
3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it occurs).  
4. When the lower-priority interrupt service routine ends, restore the IMR to its original value by returning the  
previous mask value from the stack (POP IMR).  
5. Execute an IRET.  
Depending on the application, you may be able to simplify the procedure above to some extent.  
INSTRUCTION POINTER (IP)  
The instruction pointer (IP) is adopted by all the S3C8-series microcontrollers to control the optional high-speed  
interrupt processing feature called fast interrupts. The IP consists of register pair DAH and DBH. The names of IP  
registers are IPH (high byte, IP15–IP8) and IPL (low byte, IP7–IP0).  
FAST INTERRUPT PROCESSING  
The feature called fast interrupt processing allows an interrupt within a given level to be completed in approximately 6  
clock cycles rather than the usual 16 clock cycles. To select a specific interrupt level for fast interrupt processing,  
you write the appropriate 3-bit value to SYM.4–SYM.2. Then, to enable fast interrupt processing for the selected  
level, you set SYM.1 to “1”.  
5-16  
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S3C8245/P8245/C8249/P8249  
INTERRUPT STRUCTURE  
FAST INTERRUPT PROCESSING (Continued)  
Two other system registers support fast interrupt processing:  
— The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the  
program counter values), and  
— When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated register  
called FLAGS' (“FLAGS prime”).  
NOTE  
For the S3C8245/C8249 microcontroller, the service routine for any one of the eight interrupt levels: IRQ0–  
IRQ7, can be selected for fast interrupt processing.  
Procedure for Initiating Fast Interrupts  
To initiate fast interrupt processing, follow these steps:  
1. Load the start address of the service routine into the instruction pointer (IP).  
2. Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4–SYM.2)  
3. Write a "1" to the fast interrupt enable bit in the SYM register.  
Fast Interrupt Service Routine  
When an interrupt occurs in the level selected for fast interrupt processing, the following events occur:  
1. The contents of the instruction pointer and the PC are swapped.  
2. The FLAG register values are written to the FLAGS' (“FLAGS prime”) register.  
3. The fast interrupt status bit in the FLAGS register is set.  
4. The interrupt is serviced.  
5. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction  
pointer and PC values are swapped back.  
6. The content of FLAGS' (“FLAGS prime”) is copied automatically back to the FLAGS register.  
7. The fast interrupt status bit in FLAGS is cleared automatically.  
Relationship to Interrupt Pending Bit Types  
As described previously, there are two types of interrupt pending bits: One type that is automatically cleared by  
hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared by the  
application program's interrupt service routine. You can select fast interrupt processing for interrupts with either type  
of pending condition clear function — by hardware or by software.  
Programming Guidelines  
Remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the SYM  
register, SYM.1. Executing an EI or DI instruction globally enables or disables all interrupt processing, including fast  
interrupts. If you use fast interrupts, remember to load the IP with a new start address when the fast interrupt service  
routine ends.  
5-17  
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INTERRUPT STRUCTURE  
S3C8245/P8245/C8249/P8249  
NOTES  
5-18  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
6
INSTRUCTION SET  
OVERVIEW  
The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8  
microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the  
instruction set include:  
— A full complement of 8-bit arithmetic and logic operations, including multiply and divide  
— No special I/O instructions (I/O control/data registers are mapped directly into the register file)  
— Decimal adjustment included in binary-coded decimal (BCD) operations  
— 16-bit (word) data can be incremented and decremented  
— Flexible instructions for bit addressing, rotate, and shift operations  
DATA TYPES  
The SAM8 CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can be  
set, cleared, complemented, and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least  
significant (right-most) bit.  
REGISTER ADDRESSING  
To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is  
specified. Paired registers can be used to construct 16-bit data or 16-bit program memory or data memory  
addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces."  
ADDRESSING MODES  
There are seven explicit addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative  
(RA), Immediate (IM), and Indirect (IA). For detailed descriptions of these addressing modes, please refer to Section  
3, "Addressing Modes."  
6-1  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
Table 6-1. Instruction Group Summary  
Operands Instruction  
Mnemonic  
Load Instructions  
CLR  
dst  
Clear  
LD  
dst,src  
dst,src  
dst,src  
dst,src  
dst,src  
dst,src  
dst,src  
dst,src  
dst,src  
dst,src  
dst,src  
dst,src  
dst,src  
dst  
Load  
LDB  
Load bit  
LDE  
Load external data memory  
Load program memory  
LDC  
LDED  
LDCD  
LDEI  
Load external data memory and decrement  
Load program memory and decrement  
Load external data memory and increment  
Load program memory and increment  
Load external data memory with pre-decrement  
Load program memory with pre-decrement  
Load external data memory with pre-increment  
Load program memory with pre-increment  
Load word  
LDCI  
LDEPD  
LDCPD  
LDEPI  
LDCPI  
LDW  
POP  
Pop from stack  
POPUD  
POPUI  
PUSH  
PUSHUD  
PUSHUI  
dst,src  
dst,src  
src  
Pop user stack (decrementing)  
Pop user stack (incrementing)  
Push to stack  
dst,src  
dst,src  
Push user stack (decrementing)  
Push user stack (incrementing)  
6-2  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
Table 6-1. Instruction Group Summary (Continued)  
Operands Instruction  
Mnemonic  
Arithmetic Instructions  
ADC  
ADD  
CP  
dst,src  
dst,src  
Add with carry  
Add  
dst,src  
dst  
Compare  
DA  
Decimal adjust  
Decrement  
Decrement word  
Divide  
DEC  
DECW  
DIV  
dst  
dst  
dst,src  
dst  
INC  
Increment  
INCW  
MULT  
SBC  
SUB  
dst  
Increment word  
Multiply  
dst,src  
dst,src  
dst,src  
Subtract with carry  
Subtract  
Logic Instructions  
AND  
COM  
OR  
dst,src  
dst  
Logical AND  
Complement  
dst,src  
dst,src  
Logical OR  
XOR  
Logical exclusive OR  
6-3  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
Table 6-1. Instruction Group Summary (Continued)  
Operands Instruction  
Mnemonic  
Program Control Instructions  
BTJRF  
BTJRT  
CALL  
CPIJE  
CPIJNE  
DJNZ  
ENTER  
EXIT  
dst,src  
Bit test and jump relative on false  
Bit test and jump relative on true  
Call procedure  
dst,src  
dst  
dst,src  
dst,src  
r,dst  
Compare, increment and jump on equal  
Compare, increment and jump on non-equal  
Decrement register and jump on non-zero  
Enter  
Exit  
IRET  
JP  
Interrupt return  
Jump on condition code  
Jump unconditional  
Jump relative on condition code  
Next  
cc,dst  
dst  
JP  
JR  
cc,dst  
NEXT  
RET  
Return  
WFI  
Wait for interrupt  
Bit Manipulation Instructions  
BAND  
BCP  
BITC  
BITR  
BITS  
BOR  
BXOR  
TCM  
TM  
dst,src  
dst,src  
dst  
Bit AND  
Bit compare  
Bit complement  
Bit reset  
dst  
dst  
Bit set  
dst,src  
dst,src  
dst,src  
dst,src  
Bit OR  
Bit XOR  
Test complement under mask  
Test under mask  
6-4  
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INSTRUCTION SET  
Table 6-1. Instruction Group Summary (Concluded)  
Operands Instruction  
Mnemonic  
Rotate and Shift Instructions  
RL  
dst  
dst  
dst  
dst  
dst  
dst  
Rotate left  
RLC  
RR  
Rotate left through carry  
Rotate right  
RRC  
SRA  
SWAP  
Rotate right through carry  
Shift right arithmetic  
Swap nibbles  
CPU Control Instructions  
CCF  
DI  
Complement carry flag  
Disable interrupts  
Enable interrupts  
Enter Idle mode  
No operation  
EI  
IDLE  
NOP  
RCF  
SB0  
SB1  
SCF  
Reset carry flag  
Set bank 0  
Set bank 1  
Set carry flag  
SRP  
src  
Set register pointers  
Set register pointer 0  
Set register pointer 1  
Enter Stop mode  
SRP0  
SRP1  
STOP  
src  
src  
6-5  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
FLAGS REGISTER (FLAGS)  
The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits,  
FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and FLAGS.2  
are used for BCD arithmetic.  
The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank  
address status bit (FLAGS.0) to indicate whether bank 0 or bank 1 is currently being addressed. FLAGS register  
can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction.  
Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For  
example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND  
instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will  
occur to the Flags register producing an unpredictable result.  
System Flags Register (FLAGS)  
D5H, Set 1, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Bank address  
status flag (BA)  
Carry flag (C)  
First interrupt  
status flag (FIS)  
Zero flag (Z)  
Sign flag (S)  
Overflow (V)  
Half-carry flag (H)  
Decimal adjust flag (D)  
Figure 6-1. System Flags Register (FLAGS)  
6-6  
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FLAG DESCRIPTIONS  
INSTRUCTION SET  
C
Carry Flag (FLAGS.7)  
The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the  
bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified  
register. Program instructions can set, clear, or complement the carry flag.  
Z
Zero Flag (FLAGS.6)  
For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For  
operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is  
logic zero.  
S
V
D
Sign Flag (FLAGS.5)  
Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the  
result. A logic zero indicates a positive number and a logic one indicates a negative number.  
Overflow Flag (FLAGS.4)  
The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than –  
128. It is also cleared to "0" following logic operations.  
Decimal Adjust Flag (FLAGS.3)  
The DA bit is used to specify what type of instruction was executed last during BCD operations, so that a  
subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by  
programmers, and cannot be used as a test condition.  
H
Half-Carry Flag (FLAGS.2)  
The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows out  
of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous addition or  
subtraction into the correct decimal (BCD) result. The H flag is seldom accessed directly by a program.  
FIS  
BA  
Fast Interrupt Status Flag (FLAGS.1)  
The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing. When  
set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is  
executed.  
Bank Address Flag (FLAGS.0)  
The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected,  
bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when you execute the SB0 instruction and is  
set to "1" (select bank 1) when you execute the SB1 instruction.  
6-7  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
INSTRUCTION SET NOTATION  
Table 6-2. Flag Notation Conventions  
Flag  
C
Z
Description  
Carry flag  
Zero flag  
S
Sign flag  
V
Overflow flag  
D
H
0
Decimal-adjust flag  
Half-carry flag  
Cleared to logic zero  
Set to logic one  
1
*
Set or cleared according to operation  
Value is unaffected  
Value is undefined  
–
x
Table 6-3. Instruction Set Symbols  
Symbol  
Description  
Destination operand  
dst  
src  
@
Source operand  
Indirect register address prefix  
Program counter  
PC  
IP  
Instruction pointer  
FLAGS  
RP  
#
Flags register (D5H)  
Register pointer  
Immediate operand or register address prefix  
Hexadecimal number suffix  
Decimal number suffix  
Binary number suffix  
Opcode  
H
D
B
opc  
6-8  
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INSTRUCTION SET  
Table 6-4. Instruction Notation Conventions  
Description Actual Operand Range  
Notation  
cc  
r
Condition code  
See list of condition codes in Table 6-6.  
Rn (n = 0–15)  
Working register only  
rb  
r0  
rr  
Bit (b) of working register  
Rn.b (n = 0–15, b = 0–7)  
Rn (n = 0–15)  
Bit 0 (LSB) of working register  
Working register pair  
RRp (p = 0, 2, 4, ..., 14)  
reg or Rn (reg = 0–255, n = 0–15)  
reg.b (reg = 0–255, b = 0–7)  
R
Register or working register  
Bit 'b' of register or working register  
Register pair or working register pair  
Rb  
RR  
reg or RRp (reg = 0–254, even number only, where  
p = 0, 2, ..., 14)  
IA  
Ir  
Indirect addressing mode  
addr (addr = 0–254, even number only)  
@Rn (n = 0–15)  
Indirect working register only  
IR  
Irr  
Indirect register or indirect working register @Rn or @reg (reg = 0–255, n = 0–15)  
Indirect working register pair only  
@RRp (p = 0, 2, ..., 14)  
IRR  
Indirect register pair or indirect working  
register pair  
@RRp or @reg (reg = 0–254, even only, where  
p = 0, 2, ..., 14)  
X
Indexed addressing mode  
#reg [Rn] (reg = 0–255, n = 0–15)  
XS  
Indexed (short offset) addressing mode  
#addr [RRp] (addr = range –128 to +127, where  
p = 0, 2, ..., 14)  
xl  
Indexed (long offset) addressing mode  
#addr [RRp] (addr = range 0–65535, where  
p = 0, 2, ..., 14)  
da  
ra  
Direct addressing mode  
Relative addressing mode  
addr (addr = range 0–65535)  
addr (addr = number in the range +127 to –128 that is  
an offset relative to the address of the next instruction)  
im  
Immediate addressing mode  
#data (data = 0–255)  
iml  
Immediate (long) addressing mode  
#data (data = range 0–65535)  
6-9  
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S3C8245/P8245/C8249/P8249  
Table 6-5. Opcode Quick Reference  
OPCODE MAP  
LOWER NIBBLE (HEX)  
–
0
1
2
3
4
5
6
7
DEC  
R1  
DEC  
IR1  
ADD  
r1,r2  
ADD  
r1,Ir2  
ADD  
R2,R1  
ADD  
IR2,R1  
ADD  
R1,IM  
BOR  
r0–Rb  
U
P
P
E
R
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RLC  
R1  
RLC  
IR1  
ADC  
r1,r2  
ADC  
r1,Ir2  
ADC  
R2,R1  
ADC  
IR2,R1  
ADC  
R1,IM  
BCP  
r1.b, R2  
INC  
R1  
INC  
IR1  
SUB  
r1,r2  
SUB  
r1,Ir2  
SUB  
R2,R1  
SUB  
IR2,R1  
SUB  
R1,IM  
BXOR  
r0–Rb  
JP  
IRR1  
SRP/0/1  
IM  
SBC  
r1,r2  
SBC  
r1,Ir2  
SBC  
R2,R1  
SBC  
IR2,R1  
SBC  
R1,IM  
BTJR  
r2.b, RA  
DA  
R1  
DA  
IR1  
OR  
r1,r2  
OR  
r1,Ir2  
OR  
R2,R1  
OR  
IR2,R1  
OR  
R1,IM  
LDB  
r0–Rb  
POP  
R1  
POP  
IR1  
AND  
r1,r2  
AND  
r1,Ir2  
AND  
R2,R1  
AND  
IR2,R1  
AND  
R1,IM  
BITC  
r1.b  
COM  
R1  
COM  
IR1  
TCM  
r1,r2  
TCM  
r1,Ir2  
TCM  
R2,R1  
TCM  
IR2,R1  
TCM  
R1,IM  
BAND  
r0–Rb  
N
I
PUSH  
R2  
PUSH  
IR2  
TM  
r1,r2  
TM  
r1,Ir2  
TM  
R2,R1  
TM  
IR2,R1  
TM  
R1,IM  
BIT  
r1.b  
DECW  
RR1  
DECW  
IR1  
PUSHUD  
IR1,R2  
PUSHUI  
IR1,R2  
MULT  
R2,RR1  
MULT  
IR2,RR1  
MULT  
IM,RR1  
LD  
r1, x, r2  
B
B
L
E
RL  
R1  
RL  
IR1  
POPUD  
IR2,R1  
POPUI  
IR2,R1  
DIV  
R2,RR1  
DIV  
IR2,RR1  
DIV  
IM,RR1  
LD  
r2, x, r1  
INCW  
RR1  
INCW  
IR1  
CP  
r1,r2  
CP  
r1,Ir2  
CP  
R2,R1  
CP  
IR2,R1  
CP  
R1,IM  
LDC  
r1, Irr2, xL  
CLR  
R1  
CLR  
IR1  
XOR  
r1,r2  
XOR  
r1,Ir2  
XOR  
R2,R1  
XOR  
IR2,R1  
XOR  
R1,IM  
LDC  
r2, Irr2, xL  
RRC  
R1  
RRC  
IR1  
CPIJE  
Ir,r2,RA  
LDC  
r1,Irr2  
LDW  
RR2,RR1  
LDW  
IR2,RR1  
LDW  
RR1,IML  
LD  
r1, Ir2  
SRA  
R1  
SRA  
IR1  
CPIJNE  
Irr,r2,RA  
LDC  
r2,Irr1  
CALL  
IA1  
LD  
IR1,IM  
LD  
Ir1, r2  
H
E
X
RR  
R1  
RR  
IR1  
LDCD  
r1,Irr2  
LDCI  
r1,Irr2  
LD  
R2,R1  
LD  
R2,IR1  
LD  
R1,IM  
LDC  
r1, Irr2, xs  
SWAP  
R1  
SWAP  
IR1  
LDCPD  
r2,Irr1  
LDCPI  
r2,Irr1  
CALL  
IRR1  
LD  
IR2,R1  
CALL  
DA1  
LDC  
r2, Irr1, xs  
6-10  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
Table 6-5. Opcode Quick Reference (Continued)  
OPCODE MAP  
LOWER NIBBLE (HEX)  
–
0
8
9
A
B
C
D
E
F
U
P
P
E
R
LD  
r1,R2  
LD  
r2,R1  
DJNZ  
r1,RA  
JR  
cc,RA  
LD  
r1,IM  
JP  
cc,DA  
INC  
r1  
NEXT  
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ENTER  
EXIT  
WFI  
SB0  
SB1  
IDLE  
STOP  
DI  
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
N
I
B
B
L
E
EI  
RET  
IRET  
RCF  
SCF  
CCF  
NOP  
H
E
X
LD  
r1,R2  
LD  
r2,R1  
DJNZ  
r1,RA  
JR  
cc,RA  
LD  
r1,IM  
JP  
cc,DA  
INC  
r1  
6-11  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
CONDITION CODES  
The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under  
which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after  
a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.  
The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump  
instructions.  
Table 6-6. Condition Codes  
Binary  
Mnemonic  
Description  
Flags Set  
0000  
1000  
F
T
C
Always false  
Always true  
Carry  
–
–
(note)  
(note)  
(note)  
(note)  
C = 1  
0111  
1111  
0110  
NC  
Z
No carry  
Zero  
C = 0  
Z = 1  
Z = 0  
NZ  
Not zero  
1110  
1101  
0101  
0100  
1100  
PL  
MI  
Plus  
S = 0  
S = 1  
V = 1  
V = 0  
Z = 1  
Minus  
OV  
Overflow  
No overflow  
Equal  
NOV  
EQ  
(note)  
(note)  
0110  
NE  
Not equal  
Z = 0  
1110  
1001  
0001  
1010  
0010  
GE  
LT  
Greater than or equal  
Less than  
(S XOR V) = 0  
(S XOR V) = 1  
(Z OR (S XOR V)) = 0  
(Z OR (S XOR V)) = 1  
C = 0  
GT  
LE  
Greater than  
Less than or equal  
Unsigned greater than or equal  
(note)  
(note)  
UGE  
1111  
ULT  
Unsigned less than  
C = 1  
0111  
1011  
0011  
UGT  
ULE  
Unsigned greater than  
(C = 0 AND Z = 0) = 1  
(C OR Z) = 1  
Unsigned less than or equal  
NOTES:  
1. It indicates condition codes that are related to two different mnemonics but which test the same flag. For  
example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used;  
after a CP instruction, however, EQ would probably be used.  
2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.  
6-12  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
INSTRUCTION DESCRIPTIONS  
This section contains detailed information and programming examples for each instruction in the SAM8 instruction  
set. Information is arranged in a consistent format for improved readability and for fast referencing. The following  
information is included in each instruction description:  
— Instruction name (mnemonic)  
— Full instruction name  
— Source/destination format of the instruction operand  
— Shorthand notation of the instruction's operation  
— Textual description of the instruction's effect  
— Specific flag settings affected by the instruction  
— Detailed description of the instruction's format, execution time, and addressing mode(s)  
— Programming example(s) explaining how to use the instruction  
6-13  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
ADC— Add with carry  
ADC  
dst,src  
Operation:  
dst ¬ dst + src + c  
The source operand, along with the setting of the carry flag, is added to the destination operand and  
the sum is stored in the destination. The contents of the source are unaffected. Two's-complement  
addition is performed. In multiple precision arithmetic, this instruction permits the carry from the  
addition of low-order operands to be carried into the addition of high-order operands.  
Flags:  
C: Set if there is a carry from the most significant bit of the result; cleared otherwise.  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result is negative; cleared otherwise.  
V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is  
of the opposite sign; cleared otherwise.  
D: Always cleared to "0".  
H: Set if there is a carry from the most significant bit of the low-order four bits of the result; cleared  
otherwise.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
opc  
opc  
dst | src  
src  
2
4
6
12  
13  
r
r
r
lr  
dst  
src  
3
3
6
6
14  
15  
R
R
R
IR  
dst  
6
16  
R
IM  
Examples:  
Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and  
register 03H = 0AH:  
ADC  
ADC  
ADC  
ADC  
ADC  
R1,R2  
®
®
®
®
®
R1 = 14H, R2 = 03H  
R1,@R2  
01H,02H  
01H,@02H  
01H,#11H  
R1 = 1BH, R2 = 03H  
Register 01H = 24H, register 02H = 03H  
Register 01H = 2BH, register 02H = 03H  
Register 01H = 32H  
In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and  
the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and  
the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.  
6-14  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
ADD — Add  
ADD  
dst,src  
Operation:  
dst ¬ dst + src  
The source operand is added to the destination operand and the sum is stored in the destination.  
The contents of the source are unaffected. Two's-complement addition is performed.  
Flags:  
C: Set if there is a carry from the most significant bit of the result; cleared otherwise.  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result is negative; cleared otherwise.  
V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result  
is of the opposite sign; cleared otherwise.  
D: Always cleared to "0".  
H: Set if a carry from the low-order nibble occurred.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
opc  
opc  
dst | src  
src  
2
4
6
02  
03  
r
r
r
lr  
dst  
src  
3
3
6
6
04  
05  
R
R
R
IR  
dst  
6
06  
R
IM  
Examples:  
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:  
ADD  
ADD  
ADD  
ADD  
ADD  
R1,R2  
®
®
®
®
®
R1 = 15H, R2 = 03H  
R1,@R2  
01H,02H  
01H,@02H  
01H,#25H  
R1 = 1CH, R2 = 03H  
Register 01H = 24H, register 02H = 03H  
Register 01H = 2BH, register 02H = 03H  
Register 01H = 46H  
In the first example, destination working register R1 contains 12H and the source working register  
R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register  
R1.  
6-15  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
AND — Logical AND  
AND  
dst,src  
Operation:  
dst ¬ dst AND src  
The source operand is logically ANDed with the destination operand. The result is stored in the  
destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in  
the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source  
are unaffected.  
Flags:  
C: Unaffected.  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result bit 7 is set; cleared otherwise.  
V: Always cleared to "0".  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
opc  
opc  
dst | src  
src  
2
4
6
52  
53  
r
r
r
lr  
dst  
src  
3
3
6
6
54  
55  
R
R
R
IR  
dst  
6
56  
R
IM  
Examples:  
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:  
AND  
AND  
AND  
AND  
AND  
R1,R2  
®
®
®
®
®
R1 = 02H, R2 = 03H  
R1,@R2  
01H,02H  
01H,@02H  
01H,#25H  
R1 = 02H, R2 = 03H  
Register 01H = 01H, register 02H = 03H  
Register 01H = 00H, register 02H = 03H  
Register 01H = 21H  
In the first example, destination working register R1 contains the value 12H and the source working  
register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with  
the destination operand value 12H, leaving the value 02H in register R1.  
6-16  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
BAND — Bit AND  
BAND  
dst,src.b  
BAND  
dst.b,src  
Operation:  
dst(0) ¬ dst(0) AND src(b)  
or  
dst(b) ¬ dst(b) AND src(0)  
The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the  
destination (or source). The resultant bit is stored in the specified bit of the destination. No other  
bits of the destination are affected. The source is unaffected.  
Flags:  
C: Unaffected.  
Z: Set if the result is "0"; cleared otherwise.  
S: Cleared to "0".  
V: Undefined.  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
opc  
dst | b | 0  
src | b | 1  
src  
dst  
3
6
67  
r0  
Rb  
3
6
67  
Rb  
r0  
NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four  
bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.  
Examples:  
Given: R1 = 07H and register 01H = 05H:  
BAND R1,01H.1  
BAND 01H.1,R1  
®
®
R1 = 06H, register 01H = 05H  
Register 01H = 05H, R1 = 07H  
In the first example, source register 01H contains the value 05H (00000101B) and destination  
working register R1 contains 07H (00000111B). The statement "BAND R1,01H.1" ANDs the bit 1  
value of the source register ("0") with the bit 0 value of register R1 (destination), leaving the value  
06H (00000110B) in register R1.  
6-17  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
BCP — Bit Compare  
BCP  
dst,src.b  
Operation:  
dst(0) – src(b)  
The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination.  
The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands  
are unaffected by the comparison.  
Flags:  
C: Unaffected.  
Z: Set if the two bits are the same; cleared otherwise.  
S: Cleared to "0".  
V: Undefined.  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
dst | b | 0  
src  
3
6
17  
r0  
Rb  
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'  
is three bits, and the LSB address value is one bit in length.  
Example:  
Given: R1 = 07H and register 01H = 01H:  
BCP  
R1,01H.1  
®
R1 = 07H, register 01H = 01H  
If destination working register R1 contains the value 07H (00000111B) and the source register 01H  
contains the value 01H (00000001B), the statement "BCP R1,01H.1" compares bit one of the  
source register (01H) and bit zero of the destination register (R1). Because the bit values are not  
identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H).  
6-18  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
BITC — Bit Complement  
BITC  
dst.b  
Operation:  
dst(b) ¬ NOT dst(b)  
This instruction complements the specified bit within the destination without affecting any other bits  
in the destination.  
Flags:  
C: Unaffected.  
Z: Set if the result is "0"; cleared otherwise.  
S: Cleared to "0".  
V: Undefined.  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
opc  
dst | b | 0  
2
4
57  
rb  
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'  
is three bits, and the LSB address value is one bit in length.  
Example:  
Given: R1 = 07H  
BITC  
R1.1  
®
R1 = 05H  
If working register R1 contains the value 07H (00000111B), the statement "BITC R1.1"  
complements bit one of the destination and leaves the value 05H (00000101B) in register R1.  
Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H) is  
cleared.  
6-19  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
BITR— Bit Reset  
BITR  
dst.b  
Operation:  
dst(b) ¬ 0  
The BITR instruction clears the specified bit within the destination without affecting any other bits in  
the destination.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
opc  
dst | b | 0  
2
4
77  
rb  
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'  
is three bits, and the LSB address value is one bit in length.  
Example:  
Given: R1 = 07H:  
BITR  
R1.1  
®
R1 = 05H  
If the value of working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit one of  
the destination register R1, leaving the value 05H (00000101B).  
6-20  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
BITS — Bit Set  
BITS  
dst.b  
Operation:  
dst(b) ¬ 1  
The BITS instruction sets the specified bit within the destination without affecting any other bits in  
the destination.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
opc  
dst | b | 1  
2
4
77  
rb  
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'  
is three bits, and the LSB address value is one bit in length.  
Example:  
Given: R1 = 07H:  
BITS  
R1.3  
®
R1 = 0FH  
If working register R1 contains the value 07H (00000111B), the statement "BITS R1.3" sets bit  
three of the destination register R1 to "1", leaving the value 0FH (00001111B).  
6-21  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
BOR— Bit OR  
BOR  
BOR  
dst,src.b  
dst.b,src  
Operation:  
dst(0) ¬ dst(0) OR src(b)  
or  
dst(b) ¬ dst(b) OR src(0)  
The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the  
destination (or the source). The resulting bit value is stored in the specified bit of the destination. No  
other bits of the destination are affected. The source is unaffected.  
Flags:  
C: Unaffected.  
Z: Set if the result is "0"; cleared otherwise.  
S: Cleared to "0".  
V: Undefined.  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
opc  
dst | b | 0  
src | b | 1  
src  
dst  
3
6
07  
r0  
Rb  
3
6
07  
Rb  
r0  
NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four  
bits, the bit address 'b' is three bits, and the LSB address value is one bit.  
Examples:  
Given: R1 = 07H and register 01H = 03H:  
BOR  
BOR  
R1, 01H.1  
01H.2, R1  
®
®
R1 = 07H, register 01H = 03H  
Register 01H = 07H, R1 = 07H  
In the first example, destination working register R1 contains the value 07H (00000111B) and source  
register 01H the value 03H (00000011B). The statement "BOR R1,01H.1" logically ORs bit one of  
register 01H (source) with bit zero of R1 (destination). This leaves the same value (07H) in working  
register R1.  
In the second example, destination register 01H contains the value 03H (00000011B) and the  
source working register R1 the value 07H (00000111B). The statement "BOR 01H.2,R1" logically  
ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H in  
register 01H.  
6-22  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
BTJRF — Bit Test, Jump Relative on False  
BTJRF  
dst,src.b  
Operation:  
If src(b) is a "0", then PC ¬ PC + dst  
The specified bit within the source operand is tested. If it is a "0", the relative address is added to  
the program counter and control passes to the statement whose address is now in the PC;  
otherwise, the instruction following the BTJRF instruction is executed.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
(Note 1)  
src | b | 0  
dst  
src  
opc  
dst  
3
10  
37  
RA  
rb  
NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is  
three bits, and the LSB address value is one bit in length.  
Example:  
Given: R1 = 07H:  
BTJRF SKIP,R1.3  
®
PC jumps to SKIP location  
If working register R1 contains the value 07H (00000111B), the statement "BTJRF SKIP,R1.3" tests  
bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the memory  
location pointed to by the SKIP. (Remember that the memory location must be within the allowed  
range of + 127 to – 128.)  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
BTJRT — Bit Test, Jump Relative on True  
BTJRT  
dst,src.b  
Operation:  
If src(b) is a "1", then PC ¬ PC + dst  
The specified bit within the source operand is tested. If it is a "1", the relative address is added to  
the program counter and control passes to the statement whose address is now in the PC;  
otherwise, the instruction following the BTJRT instruction is executed.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
(Note 1)  
src | b | 1  
dst  
src  
opc  
dst  
3
10  
37  
RA  
rb  
NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is  
three bits, and the LSB address value is one bit in length.  
Example:  
Given: R1 = 07H:  
BTJRT  
SKIP,R1.1  
If working register R1 contains the value 07H (00000111B), the statement "BTJRT SKIP,R1.1" tests  
bit one in the source register (R1). Because it is a "1", the relative address is added to the PC and  
the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location  
must be within the allowed range of + 127 to – 128.)  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
BXOR— Bit XOR  
BXOR  
dst,src.b  
BXOR  
dst.b,src  
Operation:  
dst(0) ¬ dst(0) XOR src(b)  
or  
dst(b) ¬ dst(b) XOR src(0)  
The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of  
the destination (or source). The result bit is stored in the specified bit of the destination. No other  
bits of the destination are affected. The source is unaffected.  
Flags:  
C: Unaffected.  
Z: Set if the result is "0"; cleared otherwise.  
S: Cleared to "0".  
V: Undefined.  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
opc  
dst | b | 0  
src | b | 1  
src  
dst  
3
6
27  
r0  
Rb  
3
6
27  
Rb  
r0  
NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four  
bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.  
Examples:  
Given: R1 = 07H (00000111B) and register 01H = 03H (00000011B):  
BXOR R1,01H.1  
BXOR 01H.2,R1  
®
®
R1 = 06H, register 01H = 03H  
Register 01H = 07H, R1 = 07H  
In the first example, destination working register R1 has the value 07H (00000111B) and source  
register 01H has the value 03H (00000011B). The statement "BXOR R1,01H.1" exclusive-ORs bit  
one of register 01H (source) with bit zero of R1 (destination). The result bit value is stored in bit zero  
of R1, changing its value from 07H to 06H. The value of source register 01H is unaffected.  
6-25  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
CALL — Call Procedure  
CALL  
dst  
Operation:  
SP  
@SP  
SP  
@SP  
PC  
¬
¬
¬
¬
¬
SP – 1  
PCL  
SP –1  
PCH  
dst  
The current contents of the program counter are pushed onto the top of the stack. The program  
counter value used is the address of the first instruction following the CALL instruction. The  
specified destination address is then loaded into the program counter and points to the first  
instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to  
return to the original program flow. RET pops the top of the stack back into the program counter.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
opc  
opc  
opc  
dst  
3
14  
F6  
F4  
D4  
DA  
IRR  
IA  
dst  
dst  
2
2
12  
14  
Examples:  
Given: R0 = 35H, R1 = 21H, PC = 1A47H, and SP = 0002H:  
CALL 3521H ®  
SP = 0000H  
(Memory locations 0000H = 1AH, 0001H = 4AH, where  
4AH is the address that follows the instruction.)  
SP = 0000H (0000H = 1AH, 0001H = 49H)  
SP = 0000H (0000H = 1AH, 0001H = 49H)  
CALL @RR0 ®  
CALL #40H  
®
In the first example, if the program counter value is 1A47H and the stack pointer contains the value  
0002H, the statement "CALL 3521H" pushes the current PC value onto the top of the stack. The  
stack pointer now points to memory location 0000H. The PC is then loaded with the value 3521H,  
the address of the first instruction in the program sequence to be executed.  
If the contents of the program counter and stack pointer are the same as in the first example, the  
statement "CALL @RR0" produces the same result except that the 49H is stored in stack location  
0001H (because the two-byte instruction format was used). The PC is then loaded with the value  
3521H, the address of the first instruction in the program sequence to be executed. Assuming that  
the contents of the program counter and stack pointer are the same as in the first example, if  
program address 0040H contains 35H and program address 0041H contains 21H, the statement  
"CALL #40H" produces the same result as in the second example.  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
CCF — Complement Carry Flag  
CCF  
Operation:  
C ¬ NOT C  
The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero;  
if C = "0", the value of the carry flag is changed to logic one.  
Flags:  
C: Complemented.  
No other flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
opc  
1
4
EF  
Example:  
Given: The carry flag = "0":  
CCF  
If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing  
its value from logic zero to logic one.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
CLR— Clear  
CLR  
dst  
Operation:  
dst ¬ "0"  
The destination location is cleared to "0".  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
opc  
dst  
2
4
4
B0  
B1  
R
IR  
Examples:  
Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:  
CLR  
CLR  
00H  
®
®
Register 00H = 00H  
@01H  
Register 01H = 02H, register 02H = 00H  
In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H  
value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR)  
addressing mode to clear the 02H register value to 00H.  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
COM — Complement  
COM  
dst  
Operation:  
dst ¬ NOT dst  
The contents of the destination location are complemented (one's complement); all "1s" are  
changed to "0s", and vice-versa.  
Flags:  
C: Unaffected.  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result bit 7 is set; cleared otherwise.  
V: Always reset to "0".  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
opc  
dst  
2
4
4
60  
61  
R
IR  
Examples:  
Given: R1 = 07H and register 07H = 0F1H:  
COM R1  
®
®
R1 = 0F8H  
R1 = 07H, register 07H = 0EH  
COM @R1  
In the first example, destination working register R1 contains the value 07H (00000111B). The  
statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and  
vice-versa, leaving the value 0F8H (11111000B).  
In the second example, Indirect Register (IR) addressing mode is used to complement the value of  
destination register 07H (11110001B), leaving the new value 0EH (00001110B).  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
CP— Compare  
CP  
dst,src  
Operation:  
dst – src  
The source operand is compared to (subtracted from) the destination operand, and the appropriate  
flags are set accordingly. The contents of both operands are unaffected by the comparison.  
Flags:  
C: Set if a "borrow" occurred (src > dst); cleared otherwise.  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result is negative; cleared otherwise.  
V: Set if arithmetic overflow occurred; cleared otherwise.  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
dst |  
src  
2
4
6
A2  
r
r
A3  
r
lr  
opc  
opc  
src  
dst  
dst  
src  
3
3
6
6
A4  
A5  
R
R
R
IR  
6
A6  
R
IM  
Examples:  
1. Given: R1 = 02H and R2 = 03H:  
CP R1,R2 Set the C and S flags  
®
Destination working register R1 contains the value 02H and source register R2 contains the value  
03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value  
(destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are "1".  
2. Given: R1 = 05H and R2 = 0AH:  
CP  
JP  
INC  
R1,R2  
UGE,SKIP  
R1  
SKIP LD  
R3,R1  
In this example, destination working register R1 contains the value 05H which is less than the  
contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1"  
and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1"  
executes, the value 06H remains in working register R3.  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
CPIJE— Compare, Increment, and Jump on Equal  
CPIJE  
dst,src,RA  
Operation:  
If dst – src = "0", PC ¬ PC + RA  
Ir ¬ Ir + 1  
The source operand is compared to (subtracted from) the destination operand. If the result is "0",  
the relative address is added to the program counter and control passes to the statement whose  
address is now in the program counter. Otherwise, the instruction immediately following the CPIJE  
instruction is executed. In either case, the source pointer is incremented by one before the next  
instruction is executed.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
src dst  
RA  
3
12  
C2  
r
Ir  
NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.  
Example:  
Given: R1 = 02H, R2 = 03H, and register 03H = 02H:  
CPIJE R1,@R2,SKIP  
®
R2 = 04H, PC jumps to SKIP location  
In this example, working register R1 contains the value 02H, working register R2 the value 03H, and  
register 03 contains 02H. The statement "CPIJE R1,@R2,SKIP" compares the @R2 value 02H  
(00000010B) to 02H (00000010B). Because the result of the comparison is equal, the relative  
address is added to the PC and the PC then jumps to the memory location pointed to by SKIP. The  
source register (R2) is incremented by one, leaving a value of 04H. (Remember that the memory  
location must be within the allowed range of + 127 to – 128.)  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
CPIJNE— Compare, Increment, and Jump on Non-Equal  
CPIJNE  
dst,src,RA  
Operation:  
If dst – src "0", PC ¬ PC + RA  
Ir ¬ Ir + 1  
The source operand is compared to (subtracted from) the destination operand. If the result is not  
"0", the relative address is added to the program counter and control passes to the statement  
whose address is now in the program counter; otherwise the instruction following the CPIJNE  
instruction is executed. In either case the source pointer is incremented by one before the next  
instruction.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
src dst  
RA  
3
12  
D2  
r
Ir  
NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.  
Example:  
Given: R1 = 02H, R2 = 03H, and register 03H = 04H:  
CPIJNE R1,@R2,SKIP  
®
R2 = 04H, PC jumps to SKIP location  
Working register R1 contains the value 02H, working register R2 (the source pointer) the value 03H,  
and general register 03 the value 04H. The statement "CPIJNE R1,@R2,SKIP" subtracts 04H  
(00000100B) from 02H (00000010B). Because the result of the comparison is non-equal, the relative  
address is added to the PC and the PC then jumps to the memory location pointed to by SKIP. The  
source pointer register (R2) is also incremented by one, leaving a value of 04H. (Remember that the  
memory location must be within the allowed range of + 127 to – 128.)  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
DA— Decimal Adjust  
DA  
dst  
Operation:  
dst ¬ DA dst  
The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction  
operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the  
operation performed. (The operation is undefined if the destination operand was not the result of a  
valid addition or subtraction of BCD digits):  
Instruction  
Carry  
Before DA  
Bits 4–7  
Value (Hex)  
H Flag  
Before DA  
Bits 0–3  
Value (Hex)  
Number Added  
to Byte  
Carry  
After DA  
0
0
0
0
0
0
1
1
1
0
0
1
1
0–9  
0–8  
0–9  
A–F  
9–F  
A–F  
0–2  
0–2  
0–3  
0–9  
0–8  
7–F  
6–F  
0
0
1
0
0
1
0
0
1
0
1
0
1
0–9  
A–F  
0–3  
0–9  
A–F  
0–3  
0–9  
A–F  
0–3  
0–9  
6–F  
0–9  
6–F  
00  
0
0
0
1
1
1
1
1
1
0
0
1
1
06  
06  
ADD  
ADC  
60  
66  
66  
60  
66  
66  
00 = – 00  
FA = – 06  
A0 = – 60  
9A = – 66  
SUB  
SBC  
Flags:  
C: Set if there was a carry from the most significant bit; cleared otherwise (see table).  
Z: Set if result is "0"; cleared otherwise.  
S: Set if result bit 7 is set; cleared otherwise.  
V: Undefined.  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
opc  
dst  
2
4
4
40  
41  
R
IR  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
DA— Decimal Adjust  
DA  
(Continued)  
Example:  
Given: Working register R0 contains the value 15 (BCD), working register R1 contains  
27 (BCD), and address 27H contains 46 (BCD):  
ADD  
DA  
R1,R0  
R1  
;
;
C ¬ "0", H ¬ "0", Bits 4–7 = 3, bits 0–3 = C, R1 ¬ 3CH  
R1 ¬ 3CH + 06  
If addition is performed using the BCD values 15 and 27, the result should be 42. The sum is  
incorrect, however, when the binary representations are added in the destination location using  
standard binary arithmetic:  
0 0 0 1 0 1 0 1  
15  
27  
+ 0 0 1 0 0 1 1 1  
0 0 1 1 1 1 0 0  
=
3CH  
The DA instruction adjusts this result so that the correct BCD representation is obtained:  
0 0 1 1 1 1 0 0  
+ 0 0 0 0 0 1 1 0  
0 1 0 0 0 0 1 0  
=
42  
Assuming the same values given above, the statements  
SUB  
DA  
27H,R0 ;  
@R1  
C ¬ "0", H ¬ "0", Bits 4–7 = 3, bits 0–3 = 1  
;
@R1 ¬ 31–0  
leave the value 31 (BCD) in address 27H (@R1).  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
DEC— Decrement  
DEC  
dst  
Operation:  
dst ¬ dst – 1  
The contents of the destination operand are decremented by one.  
Flags:  
C: Unaffected.  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if result is negative; cleared otherwise.  
V: Set if arithmetic overflow occurred; cleared otherwise.  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
opc  
dst  
2
4
4
00  
01  
R
IR  
Examples:  
Given: R1 = 03H and register 03H = 10H:  
DEC  
DEC  
R1  
®
®
R1 = 02H  
@R1  
Register 03H = 0FH  
In the first example, if working register R1 contains the value 03H, the statement "DEC R1"  
decrements the hexadecimal value by one, leaving the value 02H. In the second example, the  
statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one,  
leaving the value 0FH.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
DECW — Decrement Word  
DECW  
dst  
Operation:  
dst ¬ dst – 1  
The contents of the destination location (which must be an even address) and the operand following  
that location are treated as a single 16-bit value that is decremented by one.  
Flags:  
C: Unaffected.  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result is negative; cleared otherwise.  
V: Set if arithmetic overflow occurred; cleared otherwise.  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
opc  
dst  
2
8
8
80  
81  
RR  
IR  
Examples:  
Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H:  
DECW RR0  
DECW @R2  
®
®
R0 = 12H, R1 = 33H  
Register 30H = 0FH, register 31H = 20H  
In the first example, destination register R0 contains the value 12H and register R1 the value 34H.  
The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word and  
decrements the value of R1 by one, leaving the value 33H.  
NOTE:  
A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW  
instruction. To avoid this problem, we recommend that you use DECW as shown in the following  
example:  
LOOP: DECW RR0  
LD  
OR  
JR  
R2,R1  
R2,R0  
NZ,LOOP  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
DI — Disable Interrupts  
DI  
Operation:  
SYM (0) ¬ 0  
Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all  
interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits,  
but the CPU will not service them while interrupt processing is disabled.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
opc  
1
4
8F  
Example:  
Given: SYM = 01H:  
DI  
If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the register  
and clears SYM.0 to "0", disabling interrupt processing.  
Before changing IMR, interrupt pending and interrupt source control register, be sure DI state.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
DIV— Divide (Unsigned)  
DIV  
dst,src  
Operation:  
dst ÷ src  
dst (UPPER) ¬ REMAINDER  
dst (LOWER) ¬ QUOTIENT  
The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is  
stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the  
8
destination. When the quotient is ³ 2 , the numbers stored in the upper and lower halves of the  
destination for quotient and remainder are incorrect. Both operands are treated as unsigned  
integers.  
8
9
Flags:  
C: Set if the V flag is set and quotient is between 2 and 2 –1; cleared otherwise.  
Z: Set if divisor or quotient = "0"; cleared otherwise.  
S: Set if MSB of quotient = "1"; cleared otherwise.  
8
V: Set if quotient is ³ 2 or if divisor = "0"; cleared otherwise.  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
RR  
RR  
RR  
src  
opc  
src  
dst  
3
26/10  
26/10  
26/10  
94  
95  
96  
R
IR  
IM  
NOTE: Execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles.  
Examples:  
Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H:  
DIV  
DIV  
DIV  
RR0,R2  
®
®
®
R0 = 03H, R1 = 40H  
R0 = 03H, R1 = 20H  
R0 = 03H, R1 = 80H  
RR0,@R2  
RR0,#20H  
In the first example, destination working register pair RR0 contains the values 10H (R0) and 03H  
(R1), and register R2 contains the value 40H. The statement "DIV RR0,R2" divides the 16-bit RR0  
value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains the value  
03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the destination register  
RR0 (R0) and the quotient in the lower half (R1).  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
DJNZ— Decrement and Jump if Non-Zero  
DJNZ  
r,dst  
Operation:  
r ¬ r – 1  
If r ¹ 0, PC ¬ PC + dst  
The working register being used as a counter is decremented. If the contents of the register are not  
logic zero after decrementing, the relative address is added to the program counter and control  
passes to the statement whose address is now in the PC. The range of the relative address is  
+127 to –128, and the original value of the PC is taken to be the address of the instruction byte  
following the DJNZ statement.  
NOTE: In case of using DJNZ instruction, the working register being used as a counter should be set at  
the one of location 0C0H to 0CFH with SRP, SRP0, or SRP1 instruction.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
r | opc  
dst  
2
8 (jump taken)  
8 (no jump)  
rA  
RA  
r = 0 to F  
Example:  
Given: R1 = 02H and LOOP is the label of a relative address:  
SRP #0C0H  
DJNZ R1,LOOP  
DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the  
destination operand instead of a numeric relative address value. In the example, working register R1  
contains the value 02H, and LOOP is the label for a relative address.  
The statement "DJNZ R1, LOOP" decrements register R1 by one, leaving the value 01H. Because  
the contents of R1 after the decrement are non-zero, the jump is taken to the relative address  
specified by the LOOP label.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
EI — Enable Interrupts  
EI  
Operation:  
SYM (0) ¬ 1  
An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to  
be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was set  
while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you  
execute the EI instruction.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
opc  
1
4
9F  
Example:  
Given: SYM = 00H:  
EI  
If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement  
"EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for global  
interrupt processing.)  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
ENTER— Enter  
ENTER  
Operation:  
SP  
@SP  
IP  
¬
¬
¬
¬
¬
SP – 2  
IP  
PC  
PC  
IP  
@IP  
IP + 2  
This instruction is useful when implementing threaded-code languages. The contents of the  
instruction pointer are pushed to the stack. The program counter (PC) value is then written to the  
instruction pointer. The program memory word that is pointed to by the instruction pointer is loaded  
into the PC, and the instruction pointer is incremented by two.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
opc  
1
14  
1F  
Example:  
The diagram below shows one example of how to use an ENTER statement.  
Before  
After  
Data  
Address  
IP  
Data  
Address  
IP  
0050  
0040  
0022  
0043  
0110  
0020  
Address  
Data  
1F  
Address  
40 Enter  
Data  
1F  
PC  
SP  
40 Enter  
PC  
SP  
41 Address H 01  
42 Address L 10  
43 Address H  
41 Address H 01  
42 Address L 10  
43 Address H  
20  
21  
22  
IPH  
IPL  
Data  
00  
50  
110 Routine  
Memory  
Memory  
22  
Data  
Stack  
Stack  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
EXIT — Exit  
EXIT  
Operation:  
IP  
¬
¬
¬
¬
@SP  
SP  
PC  
IP  
SP + 2  
@IP  
IP + 2  
This instruction is useful when implementing threaded-code languages. The stack value is popped  
and loaded into the instruction pointer. The program memory word that is pointed to by the  
instruction pointer is then loaded into the program counter, and the instruction pointer is  
incremented by two.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode (Hex)  
opc  
1
14 (internal stack)  
16 (internal stack)  
2F  
Example:  
The diagram below shows one example of how to use an EXIT statement.  
Before  
After  
Data  
Address  
IP  
Data  
Address  
IP  
0050  
0040  
0022  
0052  
0060  
0022  
Address  
Data  
Address  
Data  
PC  
SP  
PC  
SP  
50 PCL old  
51 PCH  
60  
00  
60 Main  
140 Exit  
2F  
20  
21  
22  
IPH  
IPL  
Data  
00  
50  
Memory  
Memory  
Data  
22  
Stack  
Stack  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
IDLE — Idle Operation  
IDLE  
Operation:  
The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle  
mode can be released by an interrupt request (IRQ) or an external reset operation.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
1
4
6F  
–
–
Example:  
The instruction  
IDLE  
stops the CPU clock but not the system clock.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
INC— Increment  
INC  
dst  
Operation:  
dst ¬ dst + 1  
The contents of the destination operand are incremented by one.  
Flags:  
C: Unaffected.  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result is negative; cleared otherwise.  
V: Set if arithmetic overflow occurred; cleared otherwise.  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
dst | opc  
1
4
rE  
r
r = 0 to F  
opc  
dst  
2
4
4
20  
21  
R
IR  
Examples:  
Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH:  
INC  
INC  
INC  
R0  
®
®
®
R0 = 1CH  
00H  
@R0  
Register 00H = 0DH  
R0 = 1BH, register 01H = 10H  
In the first example, if destination working register R0 contains the value 1BH, the statement "INC  
R0" leaves the value 1CH in that same register.  
The next example shows the effect an INC instruction has on register 00H, assuming that it  
contains the value 0CH.  
In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of  
register 1BH from 0FH to 10H.  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
INCW — Increment Word  
INCW  
dst  
Operation:  
dst ¬ dst + 1  
The contents of the destination (which must be an even address) and the byte following that location  
are treated as a single 16-bit value that is incremented by one.  
Flags:  
C: Unaffected.  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result is negative; cleared otherwise.  
V: Set if arithmetic overflow occurred; cleared otherwise.  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
opc  
dst  
2
8
8
A0  
A1  
RR  
IR  
Examples:  
Given: R0 = 1AH, R1 = 02H, register 02H = 0FH, and register 03H = 0FFH:  
INCW RR0  
INCW @R1  
®
®
R0 = 1AH, R1 = 03H  
Register 02H = 10H, register 03H = 00H  
In the first example, the working register pair RR0 contains the value 1AH in register R0 and 02H in  
register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the value  
03H in register R1. In the second example, the statement "INCW @R1" uses Indirect Register (IR)  
addressing mode to increment the contents of general register 03H from 0FFH to 00H and register  
02H from 0FH to 10H.  
NOTE:  
A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an INCW  
instruction. To avoid this problem, we recommend that you use INCW as shown in the following  
example:  
LOOP:  
INCW  
LD  
OR  
JR  
RR0  
R2,R1  
R2,R0  
NZ,LOOP  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
IRET — Interrupt Return  
IRET  
IRET (Normal)  
IRET (Fast)  
Operation:  
FLAGS ¬ @SP  
SP ¬ SP + 1  
PC ¬ @SP  
PC « IP  
FLAGS ¬ FLAGS'  
FIS ¬ 0  
SP ¬ SP + 2  
SYM(0) ¬ 1  
This instruction is used at the end of an interrupt service routine. It restores the flag register and the  
program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the fast  
interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast interrupt  
occurred, IRET clears the FIS bit that was set at the beginning of the service routine.  
Flags:  
All flags are restored to their original settings (that is, the settings before the interrupt occurred).  
Format:  
IRET  
Bytes  
Cycles  
Opcode (Hex)  
(Normal)  
opc  
1
10 (internal stack)  
12 (internal stack)  
BF  
IRET  
Bytes  
Cycles  
Opcode (Hex)  
(Fast)  
opc  
1
6
BF  
Example:  
In the figure below, the instruction pointer is initially loaded with 100H in the main program before  
interrupts are enabled. When an interrupt occurs, the program counter and instruction pointer are  
swapped. This causes the PC to jump to address 100H and the IP to keep the return address. The  
last instruction in the service routine normally is a jump to IRET at address FFH. This causes the  
instruction pointer to be loaded with 100H "again" and the program counter to jump back to the  
main program. Now, the next interrupt can occur and the IP is still correct at 100H.  
0H  
FFH  
IRET  
100H  
Interrupt  
Service  
Routine  
JP to FFH  
FFFFH  
NOTE:  
In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay  
attention to the order of the last two instructions. The IRET cannot be immediately proceeded by a  
clearing of the interrupt status (as with a reset of the IPR register).  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
JP— Jump  
JP  
cc,dst  
(Conditional)  
JP  
dst  
(Unconditional)  
Operation:  
If cc is true, PC ¬ dst  
The conditional JUMP instruction transfers program control to the destination address if the  
condition specified by the condition code (cc) is true; otherwise, the instruction following the JP  
instruction is executed. The unconditional JP simply replaces the contents of the PC with the  
contents of the specified register pair. Control then passes to the statement addressed by the PC.  
Flags:  
No flags are affected.  
(1)  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
(2)  
cc | opc  
dst  
3
8
ccD  
DA  
cc = 0 to F  
opc  
dst  
2
8
30  
IRR  
NOTES:  
1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.  
2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the  
opcode are both four bits.  
Examples:  
Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H:  
JP  
JP  
C,LABEL_W  
@00H  
®
®
LABEL_W = 1000H, PC = 1000H  
PC = 0120H  
The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement  
"JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to  
that location. Had the carry flag not been set, control would then have passed to the statement  
immediately following the JP instruction.  
The second example shows an unconditional JP. The statement "JP @00" replaces the contents of  
the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
JR— Jump Relative  
JR  
cc,dst  
Operation:  
If cc is true, PC ¬ PC + dst  
If the condition specified by the condition code (cc) is true, the relative address is added to the  
program counter and control passes to the statement whose address is now in the program  
counter; otherwise, the instruction following the JR instruction is executed. (See list of condition  
codes).  
The range of the relative address is +127, –128, and the original value of the program counter is  
taken to be the address of the first instruction byte following the JR statement.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
(1)  
cc | opc  
dst  
2
6
ccB  
RA  
cc = 0 to F  
NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each  
four bits.  
Example:  
Given: The carry flag = "1" and LABEL_X = 1FF7H:  
JR  
C,LABEL_X  
®
PC = 1FF7H  
If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will  
pass control to the statement whose address is now in the PC. Otherwise, the program instruction  
following the JR would be executed.  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
LD— Load  
LD  
dst,src  
Operation:  
dst ¬ src  
The contents of the source are loaded into the destination. The source's contents are unaffected.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
IM  
R
dst | opc  
src | opc  
opc  
src  
dst  
2
4
4
rC  
r8  
r
r
2
2
3
3
4
r9  
R
r
r = 0 to F  
dst | src  
4
4
C7  
D7  
r
lr  
r
Ir  
opc  
src  
dst  
src  
6
6
E4  
E5  
R
R
R
IR  
opc  
dst  
6
6
E6  
D6  
R
IM  
IM  
IR  
opc  
opc  
opc  
src  
dst  
x
3
3
3
6
6
6
F5  
87  
97  
IR  
r
R
x [r]  
r
dst | src  
src | dst  
x
x [r]  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
LD— Load  
LD  
(Continued)  
Examples:  
Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H,  
register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH:  
LD  
LD  
LD  
LD  
LD  
LD  
LD  
LD  
LD  
LD  
LD  
LD  
R0,#10H  
R0,01H  
®
®
®
®
®
®
®
®
®
®
R0 = 10H  
R0 = 20H, register 01H = 20H  
01H,R0  
Register 01H = 01H, R0 = 01H  
R1 = 20H, R0 = 01H  
R1,@R0  
@R0,R1  
R0 = 01H, R1 = 0AH, register 01H = 0AH  
Register 00H = 20H, register 01H = 20H  
Register 02H = 20H, register 00H = 01H  
Register 00H = 0AH  
00H,01H  
02H,@00H  
00H,#0AH  
@00H,#10H  
@00H,02H  
Register 00H = 01H, register 01H = 10H  
Register 00H = 01H, register 01H = 02, register 02H = 02H  
R0 = 0FFH, R1 = 0AH  
R0,#LOOP[R1] ®  
#LOOP[R0],R1 ®  
Register 31H = 0AH, R0 = 01H, R1 = 0AH  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
LDB— Load Bit  
LDB  
dst,src.b  
LDB  
dst.b,src  
Operation:  
dst(0) ¬ src(b)  
or  
dst(b) ¬ src(0)  
The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the  
source is loaded into the specified bit of the destination. No other bits of the destination are  
affected. The source is unaffected.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
opc  
dst | b | 0  
src | b | 1  
src  
dst  
3
6
47  
r0  
Rb  
3
6
47  
Rb  
r0  
NOTE: In the second byte of the instruction formats, the destination (or source) address is four bits, the  
bit address 'b' is three bits, and the LSB address value is one bit in length.  
Examples:  
Given: R0 = 06H and general register 00H = 05H:  
LDB  
LDB  
R0,00H.2  
00H.0,R0  
®
®
R0 = 07H, register 00H = 05H  
R0 = 06H, register 00H = 04H  
In the first example, destination working register R0 contains the value 06H and the source general  
register 00H the value 05H. The statement "LD R0,00H.2" loads the bit two value of the 00H  
register into bit zero of the R0 register, leaving the value 07H in register R0.  
In the second example, 00H is the destination register. The statement "LD 00H.0,R0" loads bit  
zero of register R0 to the specified bit (bit zero) of the destination register, leaving 04H in general  
register 00H.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
LDC/LDE — Load Memory  
LDC/LDE  
dst,src  
Operation:  
dst ¬ src  
This instruction loads a byte from program or data memory into a working register or vice-versa. The  
source values are unaffected. LDC refers to program memory and LDE to data memory. The  
assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd number for  
data memory.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
1.  
2.  
3.  
4.  
5.  
opc  
opc  
opc  
opc  
opc  
dst | src  
src | dst  
dst | src  
src | dst  
dst | src  
2
10  
C3  
D3  
E7  
F7  
A7  
r
Irr  
2
3
3
4
10  
12  
12  
14  
Irr  
r
XS  
XS  
XL  
r
XS [rr]  
r
XS [rr]  
r
XL  
XL [rr]  
L
H
6.  
7.  
opc  
opc  
opc  
opc  
src | dst  
dst | 0000  
src | 0000  
dst | 0001  
src | 0001  
XL  
XL  
4
4
4
4
4
14  
14  
14  
14  
14  
B7  
A7  
B7  
A7  
B7  
XL [rr]  
r
DA  
r
L
H
DA  
DA  
DA  
DA  
DA  
DA  
DA  
DA  
r
L
L
L
L
H
H
H
H
8.  
DA  
r
9.  
DA  
r
10.  
opc  
DA  
NOTES:  
1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0–1.  
2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one  
byte.  
3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two  
bytes.  
4. The DA and r source values for formats 7 and 8 are used to address program memory; the second  
set of values, used in formats 9 and 10, are used to address data memory.  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
LDC/LDE — Load Memory  
LDC/LDE  
(Continued)  
Examples:  
Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations  
0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations  
0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H:  
LDC  
R0,@RR2  
;
;
R0 ¬ contents of program memory location 0104H  
R0 = 1AH, R2 = 01H, R3 = 04H  
LDE  
R0,@RR2  
;
;
R0 ¬ contents of external data memory location 0104H  
R0 = 2AH, R2 = 01H, R3 = 04H  
(note)  
LDC  
LDE  
LDC  
LDE  
@RR2,R0  
;
;
;
11H (contents of R0) is loaded into program memory  
location 0104H (RR2),  
working registers R0, R2, R3 ® no change  
@RR2,R0  
;
;
;
11H (contents of R0) is loaded into external data memory  
location 0104H (RR2),  
working registers R0, R2, R3 ® no change  
R0,#01H[RR2]  
R0,#01H[RR2]  
;
;
;
R0 ¬ contents of program memory location 0105H  
(01H + RR2),  
R0 = 6DH, R2 = 01H, R3 = 04H  
;
;
R0 ¬ contents of external data memory location 0105H  
(01H + RR2), R0 = 7DH, R2 = 01H, R3 = 04H  
(note)  
LDC  
LDE  
LDC  
LDE  
#01H[RR2],R0  
#01H[RR2],R0  
R0,#1000H[RR2]  
R0,#1000H[RR2]  
;
;
11H (contents of R0) is loaded into program memory location  
0105H (01H + 0104H)  
;
;
11H (contents of R0) is loaded into external data memory  
location 0105H (01H + 0104H)  
;
;
R0 ¬ contents of program memory location 1104H  
(1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H  
;
;
R0 ¬ contents of external data memory location 1104H  
(1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H  
LDC  
LDE  
R0,1104H  
R0,1104H  
;
R0 ¬ contents of program memory location 1104H, R0 = 88H  
;
;
R0 ¬ contents of external data memory location 1104H,  
R0 = 98H  
(note)  
LDC  
LDE  
1105H,R0  
1105H,R0  
;
;
11H (contents of R0) is loaded into program memory location  
1105H, (1105H) ¬ 11H  
;
;
11H (contents of R0) is loaded into external data memory  
location 1105H, (1105H) ¬ 11H  
NOTE: These instructions are not supported by masked ROM type devices.  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
LDCD/LDED— Load Memory and Decrement  
LDCD/LDED  
dst,src  
Operation:  
dst ¬ src  
rr ¬ rr – 1  
These instructions are used for user stacks or block transfers of data from program or data memory  
to the register file. The address of the memory location is specified by a working register pair. The  
contents of the source location are loaded into the destination location. The memory address is  
then decremented. The contents of the source are unaffected.  
LDCD references program memory and LDED references external data memory. The assembler  
makes 'Irr' an even number for program memory and an odd number for data memory.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
dst | src  
2
10  
E2  
r
Irr  
Examples:  
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and  
external data memory location 1033H = 0DDH:  
LDCD  
R8,@RR6  
;
;
;
0CDH (contents of program memory location 1033H) is loaded  
into R8 and RR6 is decremented by one  
R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 ¬ RR6 – 1)  
LDED  
R8,@RR6  
;
;
;
0DDH (contents of data memory location 1033H) is loaded  
into R8 and RR6 is decremented by one (RR6 ¬ RR6 – 1)  
R8 = 0DDH, R6 = 10H, R7 = 32H  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
LDCI/LDEI — Load Memory and Increment  
LDCI/LDEI  
dst,src  
Operation:  
dst ¬ src  
rr ¬ rr + 1  
These instructions are used for user stacks or block transfers of data from program or data memory  
to the register file. The address of the memory location is specified by a working register pair. The  
contents of the source location are loaded into the destination location. The memory address is  
then incremented automatically. The contents of the source are unaffected.  
LDCI refers to program memory and LDEI refers to external data memory. The assembler makes 'Irr'  
even for program memory and odd for data memory.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
dst | src  
2
10  
E3  
r
Irr  
Examples:  
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and  
1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:  
LDCI  
R8,@RR6  
;
;
;
0CDH (contents of program memory location 1033H) is loaded  
into R8 and RR6 is incremented by one (RR6 ¬ RR6 + 1)  
R8 = 0CDH, R6 = 10H, R7 = 34H  
LDEI  
R8,@RR6  
;
;
;
0DDH (contents of data memory location 1033H) is loaded  
into R8 and RR6 is incremented by one (RR6 ¬ RR6 + 1)  
R8 = 0DDH, R6 = 10H, R7 = 34H  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
LDCPD/LDEPD— Load Memory with Pre-Decrement  
LDCPD/  
LDEPD  
dst,src  
Operation:  
rr ¬ rr – 1  
dst ¬ src  
These instructions are used for block transfers of data from program or data memory from the  
register file. The address of the memory location is specified by a working register pair and is first  
decremented. The contents of the source location are then loaded into the destination location. The  
contents of the source are unaffected.  
LDCPD refers to program memory and LDEPD refers to external data memory. The assembler  
makes 'Irr' an even number for program memory and an odd number for external data memory.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
src | dst  
2
14  
F2  
Irr  
r
Examples:  
Given: R0 = 77H, R6 = 30H, and R7 = 00H:  
LDCPD  
@RR6,R0  
;
;
;
;
(RR6 ¬ RR6 – 1)  
77H (contents of R0) is loaded into program memory location  
2FFFH (3000H – 1H)  
R0 = 77H, R6 = 2FH, R7 = 0FFH  
LDEPD  
@RR6,R0  
;
;
;
(RR6 ¬ RR6 – 1)  
77H (contents of R0) is loaded into external data memory  
location 2FFFH (3000H – 1H)  
R0 = 77H, R6 = 2FH, R7 = 0FFH  
;
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
LDCPI/LDEPI — Load Memory with Pre-Increment  
LDCPI/  
LDEPI  
dst,src  
Operation:  
rr ¬ rr + 1  
dst ¬ src  
These instructions are used for block transfers of data from program or data memory from the  
register file. The address of the memory location is specified by a working register pair and is first  
incremented. The contents of the source location are loaded into the destination location. The  
contents of the source are unaffected.  
LDCPI refers to program memory and LDEPI refers to external data memory. The assembler makes  
'Irr' an even number for program memory and an odd number for data memory.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
src | dst  
2
14  
F3  
Irr  
r
Examples:  
Given: R0 = 7FH, R6 = 21H, and R7 = 0FFH:  
LDCPI  
@RR6,R0  
;
;
;
;
(RR6 ¬ RR6 + 1)  
7FH (contents of R0) is loaded into program memory  
location 2200H (21FFH + 1H)  
R0 = 7FH, R6 = 22H, R7 = 00H  
LDEPI  
@RR6,R0  
;
;
;
;
(RR6 ¬ RR6 + 1)  
7FH (contents of R0) is loaded into external data memory  
location 2200H (21FFH + 1H)  
R0 = 7FH, R6 = 22H, R7 = 00H  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
LDW — Load Word  
LDW  
dst,src  
Operation:  
dst ¬ src  
The contents of the source (a word) are loaded into the destination. The contents of the source are  
unaffected.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
RR  
RR  
src  
RR  
IR  
opc  
opc  
src  
dst  
dst  
3
8
8
C4  
C5  
src  
4
8
C6  
RR  
IML  
Examples:  
Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH,  
register 01H = 02H, register 02H = 03H, and register 03H = 0FH:  
LDW  
LDW  
RR6,RR4  
00H,02H  
®
®
R6 = 06H, R7 = 1CH, R4 = 06H, R5 = 1CH  
Register 00H = 03H, register 01H = 0FH,  
register 02H = 03H, register 03H = 0FH  
LDW  
LDW  
LDW  
LDW  
RR2,@R7  
®
®
®
®
R2 = 03H, R3 = 0FH,  
04H,@01H  
RR6,#1234H  
02H,#0FEDH  
Register 04H = 03H, register 05H = 0FH  
R6 = 12H, R7 = 34H  
Register 02H = 0FH, register 03H = 0EDH  
In the second example, please note that the statement "LDW 00H,02H" loads the contents of the  
source word 02H, 03H into the destination word 00H, 01H. This leaves the value 03H in general  
register 00H and the value 0FH in register 01H.  
The other examples show how to use the LDW instruction with various addressing modes and  
formats.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
MULT — Multiply (Unsigned)  
MULT  
dst,src  
Operation:  
dst ¬ dst ´ src  
The 8-bit destination operand (even register of the register pair) is multiplied by the source operand  
(8 bits) and the product (16 bits) is stored in the register pair specified by the destination address.  
Both operands are treated as unsigned integers.  
Flags:  
C: Set if result is > 255; cleared otherwise.  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if MSB of the result is a "1"; cleared otherwise.  
V: Cleared.  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
RR  
RR  
RR  
src  
opc  
src  
dst  
3
22  
22  
22  
84  
85  
86  
R
IR  
IM  
Examples:  
Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H:  
MULT  
MULT  
MULT  
00H, 02H  
®
®
®
Register 00H = 01H, register 01H = 20H, register 02H = 09H  
Register 00H = 00H, register 01H = 0C0H  
00H, @01H  
00H, #30H  
Register 00H = 06H, register 01H = 00H  
In the first example, the statement "MULT 00H,02H" multiplies the 8-bit destination operand (in the  
register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The 16-bit  
product, 0120H, is stored in the register pair 00H, 01H.  
6-60  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
NEXT — Next  
NEXT  
Operation:  
PC ¬ @ IP  
IP ¬ IP + 2  
The NEXT instruction is useful when implementing threaded-code languages. The program memory  
word that is pointed to by the instruction pointer is loaded into the program counter. The instruction  
pointer is then incremented by two.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
opc  
1
10  
0F  
Example:  
The following diagram shows one example of how to use the NEXT instruction.  
Before  
After  
Data  
Address  
IP  
Data  
Address  
IP  
0043  
0120  
0045  
0130  
Address  
Data  
Address  
43 Address H  
Data  
PC  
43 Address H 01  
PC  
44 Address L 10  
45 Address H  
44 Address L  
45 Address H  
120 Next  
Memory  
130 Routine  
Memory  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
NOP — No Operation  
NOP  
Operation:  
No action is performed when the CPU executes this instruction. Typically, one or more NOPs are  
executed in sequence in order to effect a timing delay of variable duration.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
opc  
1
4
FF  
Example:  
When the instruction  
NOP  
is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution  
time.  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
OR— Logical OR  
OR  
dst,src  
Operation:  
dst ¬ dst OR src  
The source operand is logically ORed with the destination operand and the result is stored in the  
destination. The contents of the source are unaffected. The OR operation results in a "1" being  
stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is  
stored.  
Flags:  
C: Unaffected.  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result bit 7 is set; cleared otherwise.  
V: Always cleared to "0".  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
opc  
opc  
dst | src  
src  
2
4
6
42  
43  
r
r
r
lr  
dst  
src  
3
3
6
6
44  
45  
R
R
R
IR  
dst  
6
46  
R
IM  
Examples:  
Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and  
register 08H = 8AH:  
OR  
OR  
OR  
OR  
OR  
R0,R1  
®
®
®
®
®
R0 = 3FH, R1 = 2AH  
R0,@R2  
00H,01H  
01H,@00H  
00H,#02H  
R0 = 37H, R2 = 01H, register 01H = 37H  
Register 00H = 3FH, register 01H = 37H  
Register 00H = 08H, register 01H = 0BFH  
Register 00H = 0AH  
In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the  
statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in  
destination register R0.  
The other examples show the use of the logical OR instruction with the various addressing modes  
and formats.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
POP — Pop From Stack  
POP  
dst  
Operation:  
dst ¬ @SP  
SP ¬ SP + 1  
The contents of the location addressed by the stack pointer are loaded into the destination. The  
stack pointer is then incremented by one.  
Flags:  
No flags affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
opc  
dst  
2
8
8
50  
51  
R
IR  
Examples:  
Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH,  
and stack register 0FBH = 55H:  
POP  
POP  
00H  
®
®
Register 00H = 55H, SP = 00FCH  
@00H  
Register 00H = 01H, register 01H = 55H, SP = 00FCH  
In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads  
the contents of location 00FBH (55H) into destination register 00H and then increments the stack  
pointer by one. Register 00H then contains the value 55H and the SP points to location 00FCH.  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
POPUD— Pop User Stack (Decrementing)  
POPUD  
dst,src  
Operation:  
dst ¬ src  
IR ¬ IR – 1  
This instruction is used for user-defined stacks in the register file. The contents of the register file  
location addressed by the user stack pointer are loaded into the destination. The user stack pointer  
is then decremented.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
src  
dst  
3
8
92  
R
IR  
Example:  
Given: Register 00H = 42H (user stack pointer register), register 42H = 6FH, and  
register 02H = 70H:  
POPUD 02H,@00H  
®
Register 00H = 41H, register 02H = 6FH, register 42H = 6FH  
If general register 00H contains the value 42H and register 42H the value 6FH, the statement  
"POPUD 02H,@00H" loads the contents of register 42H into the destination register 02H. The user  
stack pointer is then decremented by one, leaving the value 41H.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
POPUI — Pop User Stack (Incrementing)  
POPUI  
dst,src  
Operation:  
dst ¬ src  
IR ¬ IR + 1  
The POPUI instruction is used for user-defined stacks in the register file. The contents of the  
register file location addressed by the user stack pointer are loaded into the destination. The user  
stack pointer is then incremented.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
src  
dst  
3
8
93  
R
IR  
Example:  
Given: Register 00H = 01H and register 01H = 70H:  
POPUI 02H,@00H Register 00H = 02H, register 01H = 70H, register 02H = 70H  
®
If general register 00H contains the value 01H and register 01H the value 70H, the statement  
"POPUI 02H,@00H" loads the value 70H into the destination general register 02H. The user stack  
pointer (register 00H) is then incremented by one, changing its value from 01H to 02H.  
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INSTRUCTION SET  
PUSH— Push To Stack  
PUSH  
src  
Operation:  
SP ¬ SP – 1  
@SP ¬ src  
A PUSH instruction decrements the stack pointer value and loads the contents of the source (src)  
into the location addressed by the decremented stack pointer. The operation then adds the new  
value to the top of the stack.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
opc  
src  
2
8 (internal clock)  
8 (external clock)  
70  
R
8 (internal clock)  
8 (external clock)  
71  
IR  
Examples:  
Given: Register 40H = 4FH, register 4FH = 0AAH, SPH = 00H, and SPL = 00H:  
PUSH  
40H  
®
®
Register 40H = 4FH, stack register 0FFH = 4FH,  
SPH = 0FFH, SPL = 0FFH  
PUSH  
@40H  
Register 40H = 4FH, register 4FH = 0AAH, stack register  
0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH  
In the first example, if the stack pointer contains the value 0000H, and general register 40H the  
value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. It then  
loads the contents of register 40H into location 0FFFFH and adds this new value to the top of the  
stack.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
PUSHUD— Push User Stack (Decrementing)  
PUSHUD  
dst,src  
Operation:  
IR ¬ IR – 1  
dst ¬ src  
This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the  
user stack pointer and loads the contents of the source into the register addressed by the  
decremented stack pointer.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
dst  
src  
3
8
82  
IR  
R
Example:  
Given: Register 00H = 03H, register 01H = 05H, and register 02H = 1AH:  
PUSHUD @00H,01H Register 00H = 02H, register 01H = 05H, register 02H = 05H  
®
If the user stack pointer (register 00H, for example) contains the value 03H, the statement  
"PUSHUD @00H,01H" decrements the user stack pointer by one, leaving the value 02H. The 01H  
register value, 05H, is then loaded into the register addressed by the decremented user stack  
pointer.  
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INSTRUCTION SET  
PUSHUI — Push User Stack (Incrementing)  
PUSHUI  
dst,src  
Operation:  
IR ¬ IR + 1  
dst ¬ src  
This instruction is used for user-defined stacks in the register file. PUSHUI increments the user  
stack pointer and then loads the contents of the source into the register location addressed by the  
incremented user stack pointer.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
dst  
src  
3
8
83  
IR  
R
Example:  
Given: Register 00H = 03H, register 01H = 05H, and register 04H = 2AH:  
PUSHUI @00H,01H Register 00H = 04H, register 01H = 05H, register 04H = 05H  
®
If the user stack pointer (register 00H, for example) contains the value 03H, the statement  
"PUSHUI @00H,01H" increments the user stack pointer by one, leaving the value 04H. The 01H  
register value, 05H, is then loaded into the location addressed by the incremented user stack  
pointer.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
RCF — Reset Carry Flag  
RCF  
RCF  
Operation:  
C ¬ 0  
The carry flag is cleared to logic zero, regardless of its previous value.  
Flags:  
C:  
Cleared to "0".  
No other flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
opc  
1
4
CF  
Example:  
Given: C = "1" or "0":  
The instruction RCF clears the carry flag (C) to logic zero.  
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INSTRUCTION SET  
RET — Return  
RET  
Operation:  
PC ¬ @SP  
SP ¬ SP + 2  
The RET instruction is normally used to return to the previously executing procedure at the end of a  
procedure entered by a CALL instruction. The contents of the location addressed by the stack  
pointer are popped into the program counter. The next statement that is executed is the one that is  
addressed by the new program counter value.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode (Hex)  
opc  
1
8 (internal stack)  
10 (internal stack)  
AF  
Example:  
Given: SP = 00FCH, (SP) = 101AH, and PC = 1234:  
RET PC = 101AH, SP = 00FEH  
®
The statement "RET" pops the contents of stack pointer location 00FCH (10H) into the high byte of  
the program counter. The stack pointer then pops the value in location 00FEH (1AH) into the PC's  
low byte and the instruction at location 101AH is executed. The stack pointer now points to  
memory location 00FEH.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
RL — Rotate Left  
RL  
dst  
Operation:  
C ¬ dst (7)  
dst (0) ¬ dst (7)  
dst (n + 1) ¬ dst (n), n = 0–6  
The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is  
moved to the bit zero (LSB) position and also replaces the carry flag.  
7
0
C
Flags:  
C: Set if the bit rotated from the most significant bit position (bit 7) was "1".  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result bit 7 is set; cleared otherwise.  
V: Set if arithmetic overflow occurred; cleared otherwise.  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
opc  
dst  
2
4
4
90  
91  
R
IR  
Examples:  
Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H:  
RL  
RL  
00H  
®
®
Register 00H = 55H, C = "1"  
@01H  
Register 01H = 02H, register 02H = 2EH, C = "0"  
In the first example, if general register 00H contains the value 0AAH (10101010B), the statement  
"RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and  
setting the carry and overflow flags.  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
RLC— Rotate Left Through Carry  
RLC  
dst  
Operation:  
dst (0) ¬ C  
C ¬ dst (7)  
dst (n + 1) ¬ dst (n), n = 0–6  
The contents of the destination operand with the carry flag are rotated left one bit position. The initial  
value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.  
7
0
C
Flags:  
C: Set if the bit rotated from the most significant bit position (bit 7) was "1".  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result bit 7 is set; cleared otherwise.  
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation;  
cleared otherwise.  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
opc  
dst  
2
4
4
10  
11  
R
IR  
Examples:  
Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":  
RLC  
RLC  
00H  
®
®
Register 00H = 54H, C = "1"  
@01H  
Register 01H = 02H, register 02H = 2EH, C = "0"  
In the first example, if general register 00H has the value 0AAH (10101010B), the statement "RLC  
00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the  
initial value of the C flag replaces bit zero of register 00H, leaving the value 55H (01010101B). The  
MSB of register 00H resets the carry flag to "1" and sets the overflow flag.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
RR— Rotate Right  
RR  
dst  
Operation:  
C ¬ dst (0)  
dst (7) ¬ dst (0)  
dst (n) ¬ dst (n + 1), n = 0–6  
The contents of the destination operand are rotated right one bit position. The initial value of bit zero  
(LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).  
7
0
C
Flags:  
C: Set if the bit rotated from the least significant bit position (bit zero) was "1".  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result bit 7 is set; cleared otherwise.  
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation;  
cleared otherwise.  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
opc  
dst  
2
4
4
E0  
E1  
R
IR  
Examples:  
Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H:  
RR  
RR  
00H  
®
®
Register 00H = 98H, C = "1"  
@01H  
Register 01H = 02H, register 02H = 8BH, C = "1"  
In the first example, if general register 00H contains the value 31H (00110001B), the statement "RR  
00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7,  
leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the  
C flag to "1" and the sign flag and overflow flag are also set to "1".  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
RRC— Rotate Right Through Carry  
RRC  
dst  
Operation:  
dst (7) ¬ C  
C ¬ dst (0)  
dst (n) ¬ dst (n + 1), n = 0–6  
The contents of the destination operand and the carry flag are rotated right one bit position. The  
initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7  
(MSB).  
7
0
C
Flags:  
C: Set if the bit rotated from the least significant bit position (bit zero) was "1".  
Z: Set if the result is "0" cleared otherwise.  
S: Set if the result bit 7 is set; cleared otherwise.  
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation;  
cleared otherwise.  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
opc  
dst  
2
4
4
C0  
C1  
R
IR  
Examples:  
Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0":  
RRC  
RRC  
00H  
®
®
Register 00H = 2AH, C = "1"  
@01H  
Register 01H = 02H, register 02H = 0BH, C = "1"  
In the first example, if general register 00H contains the value 55H (01010101B), the statement  
"RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces  
the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH  
(00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0".  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
SB0— Select Bank 0  
SB0  
Operation:  
BANK ¬ 0  
The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero,  
selecting bank 0 register addressing in the set 1 area of the register file.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
opc  
1
4
4F  
Example:  
The statement  
SB0  
clears FLAGS.0 to "0", selecting bank 0 register addressing.  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
SB1— Select Bank 1  
SB1  
Operation:  
BANK ¬ 1  
The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one,  
selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not  
implemented in some S3C8-series microcontrollers.)  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
opc  
1
4
5F  
Example:  
The statement  
SB1  
sets FLAGS.0 to "1", selecting bank 1 register addressing, if implemented.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
SBC— Subtract with Carry  
SBC  
dst,src  
Operation:  
dst ¬ dst – src – c  
The source operand, along with the current value of the carry flag, is subtracted from the destination  
operand and the result is stored in the destination. The contents of the source are unaffected.  
Subtraction is performed by adding the two's-complement of the source operand to the destination  
operand. In multiple precision arithmetic, this instruction permits the carry ("borrow") from the  
subtraction of the low-order operands to be subtracted from the subtraction of high-order operands.  
Flags:  
C: Set if a borrow occurred (src > dst); cleared otherwise.  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result is negative; cleared otherwise.  
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of  
the result is the same as the sign of the source; cleared otherwise.  
D: Always set to "1".  
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set  
otherwise, indicating a "borrow".  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
opc  
opc  
dst | src  
src  
2
4
6
32  
33  
r
r
r
lr  
dst  
src  
3
3
6
6
34  
35  
R
R
R
IR  
dst  
6
36  
R
IM  
Examples:  
Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register  
03H = 0AH:  
SBC  
SBC  
SBC  
SBC  
SBC  
R1,R2  
®
®
®
®
®
R1 = 0CH, R2 = 03H  
R1,@R2  
01H,02H  
01H,@02H  
01H,#8AH  
R1 = 05H, R2 = 03H, register 03H = 0AH  
Register 01H = 1CH, register 02H = 03H  
Register 01H = 15H,register 02H = 03H, register 03H = 0AH  
Register 01H = 95H; C, S, and V = "1"  
In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the  
statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the  
destination (10H) and then stores the result (0CH) in register R1.  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
SCF — Set Carry Flag  
SCF  
Operation:  
Flags:  
C ¬ 1  
The carry flag (C) is set to logic one, regardless of its previous value.  
C: Set to "1".  
No other flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
opc  
1
4
DF  
Example:  
The statement  
SCF  
sets the carry flag to logic one.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
SRA— Shift Right Arithmetic  
SRA  
dst  
Operation:  
dst (7) ¬ dst (7)  
C ¬ dst (0)  
dst (n) ¬ dst (n + 1), n = 0–6  
An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the  
LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit  
position 6.  
7
6
0
C
Flags:  
C: Set if the bit shifted from the LSB position (bit zero) was "1".  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result is negative; cleared otherwise.  
V: Always cleared to "0".  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
opc  
dst  
2
4
4
D0  
D1  
R
IR  
Examples:  
Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":  
SRA  
SRA  
00H  
®
®
Register 00H = 0CD, C = "0"  
@02H  
Register 02H = 03H, register 03H = 0DEH, C = "0"  
In the first example, if general register 00H contains the value 9AH (10011010B), the statement  
"SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag  
and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value  
0CDH (11001101B) in destination register 00H.  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
SRP/SRP0/SRP1— Set Register Pointer  
SRP  
src  
src  
src  
SRP0  
SRP1  
Operation:  
If src (1) = 1 and src (0) = 0 then: RP0 (3–7)  
¬
¬
¬
¬
¬
¬
src (3–7)  
src (3–7)  
src (4–7),  
0
If src (1) = 0 and src (0) = 1 then: RP1 (3–7)  
If src (1) = 0 and src (0) = 0 then: RP0 (4–7)  
RP0 (3)  
RP1 (4–7)  
RP1 (3)  
src (4–7),  
1
The source data bits one and zero (LSB) determine whether to write one or both of the register  
pointers, RP0 and RP1. Bits 3–7 of the selected register pointer are written unless both register  
pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
src  
opc  
src  
2
4
31  
IM  
Examples:  
The statement  
SRP #40H  
sets register pointer 0 (RP0) at location 0D6H to 40H and register pointer 1 (RP1) at location 0D7H  
to 48H.  
The statement "SRP0 #50H" sets RP0 to 50H, and the statement "SRP1 #68H" sets RP1 to 68H.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
STOP — Stop Operation  
STOP  
Operation:  
The STOP instruction stops the both the CPU clock and system clock and causes the  
microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers,  
peripheral registers, and I/O port control and data registers are retained. Stop mode can be released  
by an external reset operation or by external interrupts. For the reset operation, the RESET pin  
must be held to Low level until the required oscillation stabilization interval has elapsed.  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
1
4
7F  
–
–
Example:  
The statement  
STOP  
halts all microcontroller operations.  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
SUB— Subtract  
SUB  
dst,src  
Operation:  
dst ¬ dst – src  
The source operand is subtracted from the destination operand and the result is stored in the  
destination. The contents of the source are unaffected. Subtraction is performed by adding the two's  
complement of the source operand to the destination operand.  
Flags:  
C: Set if a "borrow" occurred; cleared otherwise.  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result is negative; cleared otherwise.  
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign  
of the result is of the same as the sign of the source operand; cleared otherwise.  
D: Always set to "1".  
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set  
otherwise indicating a "borrow".  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
dst |  
src  
2
4
6
22  
r
r
23  
r
lr  
opc  
opc  
src  
dst  
dst  
src  
3
3
6
6
24  
25  
R
R
R
IR  
6
26  
R
IM  
Examples:  
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:  
SUB  
SUB  
SUB  
SUB  
SUB  
SUB  
R1,R2  
®
®
®
®
®
®
R1 = 0FH, R2 = 03H  
R1,@R2  
01H,02H  
01H,@02H  
01H,#90H  
01H,#65H  
R1 = 08H, R2 = 03H  
Register 01H = 1EH, register 02H = 03H  
Register 01H = 17H, register 02H = 03H  
Register 01H = 91H; C, S, and V = "1"  
Register 01H = 0BCH; C and S = "1", V = "0"  
In the first example, if working register R1 contains the value 12H and if register R2 contains the  
value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value  
(12H) and stores the result (0FH) in destination register R1.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
SWAP— Swap Nibbles  
SWAP  
dst  
Operation:  
dst (0 – 3) « dst (4 – 7)  
The contents of the lower four bits and upper four bits of the destination operand are swapped.  
7
4 3  
0
Flags:  
C: Undefined.  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result bit 7 is set; cleared otherwise.  
V: Undefined.  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
opc  
dst  
2
4
4
F0  
F1  
R
IR  
Examples:  
Given: Register 00H = 3EH, register 02H = 03H, and register 03H = 0A4H:  
SWAP  
SWAP  
00H  
®
®
Register 00H = 0E3H  
@02H  
Register 02H = 03H, register 03H = 4AH  
In the first example, if general register 00H contains the value 3EH (00111110B), the statement  
"SWAP 00H" swaps the lower and upper four bits (nibbles) in the 00H register, leaving the value  
0E3H (11100011B).  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
TCM — Test Complement Under Mask  
TCM  
dst,src  
Operation:  
(NOT dst) AND src  
This instruction tests selected bits in the destination operand for a logic one value. The bits to be  
tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).  
The TCM statement complements the destination operand, which is then ANDed with the source  
mask. The zero (Z) flag can then be checked to determine the result. The destination and source  
operands are unaffected.  
Flags:  
C: Unaffected.  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result bit 7 is set; cleared otherwise.  
V: Always cleared to "0".  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
opc  
opc  
dst | src  
src  
2
4
6
62  
63  
r
r
r
lr  
dst  
src  
3
3
6
6
64  
65  
R
R
R
IR  
dst  
6
66  
R
IM  
Examples:  
Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and  
register 02H = 23H:  
TCM  
TCM  
TCM  
TCM  
R0,R1  
®
®
®
®
R0 = 0C7H, R1 = 02H, Z = "1"  
R0,@R1  
00H,01H  
00H,@01H  
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"  
Register 00H = 2BH, register 01H = 02H, Z = "1"  
Register 00H = 2BH, register 01H = 02H,  
register 02H = 23H, Z = "1"  
TCM  
00H,#34  
®
Register 00H = 2BH, Z = "0"  
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the  
value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a  
"1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can  
be tested to determine the result of the TCM operation.  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
TM — Test Under Mask  
TM  
dst,src  
Operation:  
dst AND src  
This instruction tests selected bits in the destination operand for a logic zero value. The bits to be  
tested are specified by setting a "1" bit in the corresponding position of the source operand (mask),  
which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine  
the result. The destination and source operands are unaffected.  
Flags:  
C: Unaffected.  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result bit 7 is set; cleared otherwise.  
V: Always reset to "0".  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
opc  
opc  
dst | src  
src  
2
4
6
72  
73  
r
r
r
lr  
dst  
src  
3
3
6
6
74  
75  
R
R
R
IR  
dst  
6
76  
R
IM  
Examples:  
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and  
register 02H = 23H:  
TM  
TM  
TM  
TM  
R0,R1  
®
®
®
®
R0 = 0C7H, R1 = 02H, Z = "0"  
R0,@R1  
00H,01H  
00H,@01H  
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"  
Register 00H = 2BH, register 01H = 02H, Z = "0"  
Register 00H = 2BH, register 01H = 02H,  
register 02H = 23H, Z = "0"  
TM  
00H,#54H  
®
Register 00H = 2BH, Z = "1"  
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the  
value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0"  
value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and  
can be tested to determine the result of the TM operation.  
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S3C8245/P8245/C8249/P8249  
INSTRUCTION SET  
WFI — Wait for Interrupt  
WFI  
Operation:  
The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take  
place during this wait state. The WFI status can be released by an internal interrupt, including a fast  
interrupt .  
Flags:  
No flags are affected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
opc  
1
4n  
3F  
( n = 1, 2, 3, … )  
Example:  
The following sample program structure shows the sequence of operations that follow a "WFI"  
statement:  
Main program  
.
.
.
EI  
WFI  
(Enable global interrupt)  
(Wait for interrupt)  
(Next instruction)  
.
.
.
Interrupt occurs  
Interrupt service routine  
.
.
.
Clear interrupt flag  
IRET  
Service routine completed  
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INSTRUCTION SET  
S3C8245/P8245/C8249/P8249  
XOR— Logical Exclusive OR  
XOR  
dst,src  
Operation:  
dst ¬ dst XOR src  
The source operand is logically exclusive-ORed with the destination operand and the result is stored  
in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the  
corresponding bits in the operands are different; otherwise, a "0" bit is stored.  
Flags:  
C: Unaffected.  
Z: Set if the result is "0"; cleared otherwise.  
S: Set if the result bit 7 is set; cleared otherwise.  
V: Always reset to "0".  
D: Unaffected.  
H: Unaffected.  
Format:  
Bytes  
Cycles  
Opcode  
(Hex)  
Addr Mode  
dst  
src  
opc  
opc  
opc  
dst | src  
src  
2
4
6
B2  
B3  
r
r
r
lr  
dst  
src  
3
3
6
6
B4  
B5  
R
R
R
IR  
dst  
6
B6  
R
IM  
Examples:  
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and  
register 02H = 23H:  
XOR  
XOR  
XOR  
XOR  
XOR  
R0,R1  
®
®
®
®
®
R0 = 0C5H, R1 = 02H  
R0,@R1  
00H,01H  
00H,@01H  
00H,#54H  
R0 = 0E4H, R1 = 02H, register 02H = 23H  
Register 00H = 29H, register 01H = 02H  
Register 00H = 08H, register 01H = 02H, register 02H = 23H  
Register 00H = 7FH  
In the first example, if working register R0 contains the value 0C7H and if register R1 contains the  
value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value and  
stores the result (0C5H) in the destination register R0.  
6-88  
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S3C8245/P8245/C8249/P8249  
CLOCK CIRCUIT  
7
CLOCK CIRCUIT  
OVERVIEW  
The clock frequency generated for the S3C8245/C8249 by an external crystal can range from 1 MHz to 10 MHz. The  
maximum CPU clock frequency is 10 MHz. The X and X pins connect the external oscillator or clock source to  
IN  
OUT  
the on-chip clock circuit.  
SYSTEM CLOCK CIRCUIT  
The system clock circuit has the following components:  
— External crystal or ceramic resonator oscillation source (or an external clock source)  
— Oscillator stop and wake-up functions  
— Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16)  
— System clock control register, CLKCON  
— Oscillator control register, OSCCON and STOP control register, STPCON  
C1  
C2  
XIN  
XIN  
S3C8245/C8249  
S3C8245/C8249  
XOUT  
XOUT  
Figure 7-2. Main Oscillator Circuit  
(RC Oscillator)  
Figure 7-1. Main Oscillator Circuit  
(Crystal or Ceramic Oscillator)  
7-1  
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CLOCK CIRCUIT  
S3C8245/P8245/C8249/P8249  
CLOCK STATUS DURING POWER-DOWN MODES  
The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:  
— In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator is started, by a reset  
operation or an external interrupt (with RC delay noise filter), and can be released by internal interrupt too when  
the sub-system oscillator is running and watch timer is operating with sub-system clock.  
— In Idle mode, the internal clock signal is gated to the CPU, but not to interrupt structure, timers and timer/  
counters. Idle mode is released by a reset or by an external or internal interrupt.  
Stop Release  
INT  
Driving Ability  
OSCCON.4  
Main-System  
Oscillator  
Circuit  
Sub-system  
Oscillator  
Circuit  
fx  
fxt  
Watch Timer  
Selector 1  
fxx  
Stop  
OSCCON.3  
OSCCON.0  
Stop  
OSCCON.2  
Basic Timer  
Timer/Counter  
1/8-1/4096  
STOP OSC  
inst.  
Watch Timer (fxx/128)  
LCD Controller  
SIO  
Frequency  
Dividing  
Circuit  
STPCON  
1/1 1/2 1/8 1/16  
A/D Converter  
System Clock  
CLKCON.4-.3  
Selector 2  
CPU Clock  
IDLE Instruction  
Figure 7-3. System Clock Circuit Diagram  
7-2  
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S3C8245/P8245/C8249/P8249  
CLOCK CIRCUIT  
SYSTEM CLOCK CONTROL REGISTER (CLKCON)  
The system clock control register, CLKCON, is located in the bank 0 of set 1, address D4H. It is read/write  
addressable and has the following functions:  
— Oscillator frequency divide-by value  
After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If  
necessary, you can then increase the CPU clock speed fxx/8, fxx/2, or fxx/1.  
System Clock Control Register (CLKCON)  
D4H, Set 1, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Not used (must keep always 0)  
Not used (must keep always 0)  
Divide-by selection bits for  
CPU clock frequency:  
00 = fXX/16  
01 = fXX/8  
10 = fXX/2  
11 = fXX/1 (non-divided)  
NOTE:  
The fxx can be generated by both main-system and  
sub-system oscillator therefore while main-system  
stops peripherals can be operated by sub-system.  
Figure 7-4. System Clock Control Register (CLKCON)  
7-3  
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CLOCK CIRCUIT  
S3C8245/P8245/C8249/P8249  
Oscillator Control Register (OSCCON)  
F3H, Set 1, bank 0, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Not used  
Not used  
System clock selection bit:  
0 = Main oscillator select  
1 = Subsystem oscillator select  
Subsystem oscillator driving  
ability control bit:  
0 = Strong driving ability  
Subsystem oscillator control bit:  
0 = Subsystem oscillator RUN  
1 = Subsystem oscillator STOP  
1 = Normal driving ability  
Mainsystem oscillator control bit:  
0 = Mainsystem oscillator RUN  
1 = Mainsystem oscillator STOP  
NOTE:  
In strong mode the warm-up time is less than 100 ms.  
When the CPU is operated with fxt (sub-oscillation clock), it is possible to use the stop  
instruction but in this case before using stop instruction, you must select fxx/128 for basic  
timer counter clock input.  
Then the oscillation stabilization time is 62.5 ((1/32768) x 128 x 16) ms + 100 ms  
Here the warm-up time is from the time that the stop release signal activates to the time  
that basic timer starts counting.  
Figure 7-5. Oscillator Control Register (OSCCON)  
STOP Control Register (STPCON)  
F4H, Set 1,bank 0, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
STOP Control bits:  
Other values = Disable STOP instruction  
10100101 = Enable STOP instruction  
Figure 7-6. STOP Control Register (STPCON)  
7-4  
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S3C8245/P8245/C8249/P8249  
nRESET and POWER-DOWN  
8
nRESET and POWER-DOWN  
SYSTEM nRESET  
OVERVIEW  
During a power-on reset, the voltage at V goes to High level and the nRESET pin is forced to Low level. The  
DD  
nRESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This  
procedure brings the S3C8245/C8249 into a known operating status.  
To allow time for internal CPU clock oscillation to stabilize, the nRESET pin must be held to Low level for a minimum  
time interval after the power supply comes within tolerance. The minimum required time of a reset operation for  
oscillation stabilization is 1 millisecond.  
Whenever a reset occurs during normal operation (that is, when both V and nRESET are High level), the nRESET  
DD  
pin is forced Low level and the reset operation starts. All system and peripheral control registers are then reset to  
their default hardware values  
In summary, the following sequence of events occurs during a reset operation:  
— All interrupt is disabled.  
— The watchdog function (basic timer) is enabled.  
— Ports 0-3 and set to input mode.  
— Peripheral control and data register settings are disabled and reset to their default hardware values.  
— The program counter (PC) is loaded with the program reset address in the ROM, 0100H.  
— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location  
0100H (and 0101H) is fetched and executed.  
NORMAL MODE nRESET OPERATION  
In normal (masked ROM) mode, the Test pin is tied to V . A reset enables access to the 16-Kbyte on-chip ROM.  
SS  
(The external interface is not automatically configured).  
NOTE  
To program the duration of the oscillation stabilization interval, you make the appropriate settings to the  
basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic  
timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can  
disable it by writing "1010B" to the upper nibble of BTCON.  
8-1  
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nRESET and POWER-DOWN  
S3C8245/P8245/C8249/P8249  
HARDWARE nRESET VALUES  
Table 8-1, 8-2, 8-3 list the reset values for CPU and system registers, peripheral control registers, and peripheral  
data registers following a reset operation. The following notation is used to represent reset values:  
— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.  
— An "x" means that the bit value is undefined after a reset.  
— A dash ("–") means that the bit is either not used or not mapped, but read 0 is the bit value.  
Table 8-1. S3C8245/C8249 Set 1 Register and Values after nRESET  
Register Name  
Mnemonic  
Address  
Dec  
Bit Values after nRESET  
Hex  
D0H  
D1H  
D2H  
D3H  
D4H  
D5H  
D6H  
D7H  
D8H  
D9H  
DAH  
DBH  
DCH  
DDH  
DEH  
DFH  
7
0
0
–
0
0
x
1
1
x
x
x
x
0
x
0
0
6
0
0
–
0
0
x
1
1
x
x
x
x
0
x
–
0
5
0
0
–
0
0
x
0
0
x
x
x
x
0
x
–
0
4
0
0
–
0
0
x
0
0
x
x
x
x
0
x
x
0
3
0
0
–
0
0
x
0
1
x
x
x
x
0
x
x
0
2
0
0
0
0
0
x
–
–
x
x
x
x
0
x
x
0
1
0
0
0
0
0
0
–
–
x
x
x
x
0
x
0
0
0
0
0
0
0
0
0
–
–
x
x
x
x
0
x
0
0
LCD Control Register  
LCON  
LMOD  
INTPND  
BTCON  
CLKCON  
FLAGS  
RP0  
208  
209  
210  
211  
212  
213  
214  
215  
216  
217  
218  
219  
220  
221  
222  
223  
LCD Mode Register  
Interrupt Pending Register  
Basic Timer Control Register  
Clock Control Register  
System Flags Register  
Register Pointer (High Byte)  
Register Pointer (Low Byte)  
Stack Pointer (High Byte)  
Stack Pointer (Low Byte)  
Instruction Pointer (High Byte)  
Instruction Pointer (Low Byte)  
Interrupt Request Register  
Interrupt Mask Register  
System Mode Register  
RP1  
SPH  
SPL  
IPH  
IPL  
IRQ  
IMR  
SYM  
Register Page Pointer  
PP  
8-2  
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S3C8245/P8245/C8249/P8249  
nRESET and POWER-DOWN  
Table 8-2. S3C8245/C8249 Set 1, Bank 0 Register Values after nRESET  
Register Name  
Mnemonic  
Address  
Dec  
Bit Values after nRESET  
Hex  
E0H  
E1H  
E2H  
E3H  
E4H  
E5H  
E6H  
E7H  
E8H  
E9H  
EAH  
EBH  
ECH  
EDH  
EEH  
EFH  
F0H  
F1H  
F2H  
F3H  
F4H  
F5H  
F6H  
F7H  
F8H  
F9H  
FAH  
FBH  
7
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
–
0
0
6
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
–
0
0
5
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
–
0
0
4
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
2
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Port 0 Control High Register  
Port 0 Control Low Register  
Port 0 interrupt Control Register  
Port 0 interrupt Pending Register  
Port 1 Control High Register  
Port 1 Control Low Register  
Port 2 Control High Register  
Port 2 Control Low Register  
Port 3 Control High Register  
Port 3 Control Low Register  
Timer B Data Register (High Byte)  
Timer B Data Register (Low Byte)  
Timer B Control Register  
Timer A Control Register  
Timer A Counter Register  
Timer A Data Register  
P0CONH  
P0CONL  
P0INT  
224  
225  
226  
227  
228  
229  
230  
231  
232  
233  
234  
235  
236  
237  
238  
239  
240  
241  
242  
243  
244  
245  
246  
247  
248  
249  
250  
251  
P0PND  
P1CONH  
P1CONL  
P2CONH  
P2CONL  
P3CONH  
P3CONL  
TBDATAH  
TBDATAL  
TBCON  
TACON  
TACNT  
TADATA  
SIOCON  
SIODATA  
SIOPS  
OSCCON  
STPCON  
P1PUP  
P0  
Serial I/O Control Register  
Serial I/O Data Register  
Serial I/O Pre-scale Register  
Oscillator Control Register  
STOP Control Register  
Port 1 Pull-up Control Register  
Port 0 Data Register  
Port 1 Data Register  
P1  
Port 2 Data Register  
P2  
Port 3 Data Register  
P3  
Port 4 Data Register  
P4  
Port 5 Data Register  
P5  
Location FCH is factory use only.  
Basic Timer Data Register  
External Memory Timing Register  
Interrupt Priority Register  
BTCNT  
EMT  
253  
254  
255  
FDH  
FEH  
FFH  
0
0
x
0
–
x
0
–
x
0
–
x
0
–
x
0
–
x
0
–
x
0
–
x
IPR  
8-3  
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nRESET and POWER-DOWN  
S3C8245/P8245/C8249/P8249  
Table 8-3. S3C8245/P8245 Set 1, Bank 1 Register Values after nRESET  
Register Name  
Mnemonic  
Address  
Bit Values after nRESET  
Dec  
Hex  
ECH  
EDH  
EEH  
EFH  
7
0
0
0
0
6
0
0
0
0
5
0
0
0
0
4
0
0
0
0
3
0
0
0
0
2
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Port 4 control High register  
Port 4 control Low register  
Port 5 Control High Register  
Port 5 Control Low Register  
P4CONH  
P4CONL  
P5CONH  
P5CONL  
236  
237  
238  
239  
Locations F0H is factory use only.  
Timer 0 Control Register  
T0CON  
T0CNTH  
241  
242  
243  
244  
245  
246  
247  
248  
F1H  
F2H  
F3H  
F4H  
F5H  
F6H  
F7H  
F8H  
0
0
0
1
1
0
–
x
0
0
0
1
1
0
0
x
0
0
0
1
1
0
0
x
–
0
0
1
1
0
0
x
0
0
0
1
1
0
0
x
0
0
0
1
1
0
0
x
0
0
0
1
1
0
0
x
0
0
0
1
1
0
0
x
Timer 0 Counter Register (High Byte)  
Timer 0 Counter Register (Low Byte)  
Timer 0 Data Register (High Byte)  
Timer 0 Data Register (Low Byte)  
Voltage Level Detector Control Register  
AD Converter Control Register  
T0CNTL  
T0DATAH  
T0DATAL  
VLDCON  
ADCON  
AD Converter Data Register  
(High Byte)  
ADDATAH  
AD Converter Data Register  
(Low Byte)  
ADDATAL  
249  
F9H  
x
x
x
x
x
x
x
x
Watch Timer Control Register  
Timer 1 Control Register  
WTCON  
T1CON  
250  
251  
252  
253  
254  
255  
FAH  
FBH  
FCH  
FDH  
FEH  
FFH  
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
Timer 1 Counter Register (High Byte)  
Timer 1 Counter Register (Low Byte)  
Timer 1 Data Register (High Byte)  
Timer 1 Data Register (Low Byte)  
T1CNTH  
T1CNTL  
T1DATAH  
T1DATAL  
8-4  
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S3C8245/P8245/C8249/P8249  
nRESET and POWER-DOWN  
POWER-DOWN MODES  
STOP MODE  
Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all  
peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than  
3 mA. All system functions stop when the clock “freezes”, but data stored in the internal register file is retained. Stop  
mode can be released in one of two ways: by a reset or by interrupts, for more details see Figure 7-3.  
NOTE  
Do not use stop mode if you are using an external clock source because X input must be restricted  
IN  
internally to V to reduce current leakage.  
SS  
Using nRESET to Release Stop Mode  
Stop mode is released when the nRESET signal is released and returns to high level: all system and peripheral  
control registers are reset to their default hardware values and the contents of all data registers are retained. A reset  
operation automatically selects a slow clock fxx/16 because CLKCON.3 and CLKCON.4 are cleared to  
‘00B’. After the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization  
routine by fetching the program instruction stored in ROM location 0100H (and 0101H)  
Using an External Interrupt to Release Stop Mode  
External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. Which interrupt you can  
use to release Stop mode in a given situation depends on the microcontroller’s current internal operating mode. The  
external interrupts in the S3C8245/C8249 interrupt structure that can be used to release Stop mode are:  
— External interrupts P0.0–P0.7 (INT0–INT7)  
Please note the following conditions for Stop mode release:  
— If you release Stop mode using an external interrupt, the current values in system and peripheral control  
registers are unchanged except STPCON register.  
— If you use an internal or external interrupt for stop mode release, you can also program the duration of the  
oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before  
entering stop mode.  
— When the Stop mode is released by external interrupt, the CLKCON.4 and CLKCON.3 bit-pair setting remains  
unchanged and the currently selected clock value is used.  
— The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service  
routine, the instruction immediately following the one that initiated Stop mode is executed.  
Using an Internal Interrupt to Release Stop Mode  
Activate any enabled interrupt, causing stop mode to be released. Other things are same as using external interrupt.  
How to Enter into Stop Mode  
There are two ways to enter into Stop mode:  
1. Handling OSCCON register.  
2. Handling STPCON register then writing Stop instruction (keep the order).  
8-5  
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nRESET and POWER-DOWN  
IDLE MODE  
S3C8245/P8245/C8249/P8249  
Idle mode is invoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some  
peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU, but all peripherals  
timers remain active. Port pins retain the mode (input or output) they had at the time idle mode was entered.  
There are two ways to release idle mode:  
1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of  
all data registers are retained. The reset automatically selects the slow clock fxx/16 because CLKCON.4 and  
CLKCON.3 are cleared to ‘00B’. If interrupts are masked, a reset is the only way to release idle mode.  
2. Activate any enabled interrupt, causing idle mode to be released. When you use an interrupt to release idle  
mode, the CLKCON.4 and CLKCON.3 register values remain unchanged, and the currently selected clock value  
is used. The interrupt is then serviced. When the return-from-interrupt (IRET) occurs, the instruction immediately  
following the one that initiated idle mode is executed.  
8-6  
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S3C8245/P8245/C8249/P8249  
I/O PORTS  
9
I/O PORTS  
OVERVIEW  
The S3C8245/C8249 microcontroller has two nibble-programmable and four bit-programmable I/O ports,  
P0–P5. The port 3 is a 5-bit port and the others are 8-bit ports. This gives a total of 45 I/O pins. Each port can be  
flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading  
port registers. No special I/O instructions are required.  
Table 9-1 gives you a general overview of the S3C8245/C8249 I/O port functions.  
Table 9-1. S3C8245/C8249 Port Configuration Overview  
Port  
Configuration Options  
0
1-bit programmable I/O port.  
Schmitt trigger input or output mode selected by software; software assignable pull-up.  
P0.0–P0.7 can be used as inputs for external interrupts INT0–INT7  
(with noise filter and interrupt control).  
1
1-bit programmable I/O port.  
Input or output mode selected by software; open-drain output mode can be selected by software;  
software assignable pull-up.  
Alternately P1.0–P1.7 can be used as SI, SO, SCK, BUZ, T1CAP, T1CLK, T1OUT, T1PWM.  
2
3
4
5
1-bit programmable I/O port.  
Normal input and AD input or output mode selected by software;  
software assignable pull-up.  
1-bit programmable I/O port.  
Input or push-pull output with software assignable pull-up.  
Alternately P3.0–P3.3 can be used as TACAP, TACLK, TAOUT, TAPWM, TBPWM.  
1-bit programmable I/O port.  
Push-pull or open drain output and input with software assignable pull-up.  
P4.0–P4.7 can alternately be used as outputs for LCD SEG.  
1-bit programmable I/O port.  
Push-pull or open drain output and input with software assignable pull-up.  
P5.0–P5.7 can alternately be used as outputs for LCD SEG.  
9-1  
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I/O PORTS  
S3C8245/P8245/C8249/P8249  
PORT DATA REGISTERS  
Table 9-2 gives you an overview of the register locations of all four S3C8245/C8249 I/O port data registers. Data  
registers for ports 0, 1, 2, 3, 4, and 5 have the general format shown in Figure 9-1.  
Table 9-2. Port Data Register Summary  
Register Name  
Port 0 data register  
Port 1 data register  
Port 2 data register  
Port 3 data register  
Port 4 data register  
Port 5 data register  
Mnemonic  
Decimal  
246  
Hex  
F6H  
F7H  
F8H  
F9H  
FAH  
FBH  
Location  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
P0  
P1  
P2  
P3  
P4  
P5  
Set 1, Bank 0  
Set 1, Bank 0  
Set 1, Bank 0  
Set 1, Bank 0  
Set 1, Bank 0  
Set 1, Bank 0  
247  
248  
249  
250  
251  
9-2  
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S3C8245/P8245/C8249/P8249  
I/O PORTS  
PORT 0  
Port 0 is an 8-bit I/O Port that you can use two ways:  
— General-purpose I/O  
— External interrupt inputs for INT0–INT7  
Port 0 is accessed directly by writing or reading the port 0 data register, P0 at location F6H in set 1, bank 0.  
Port 0 Control Register (P0CONH, P0CONL)  
Port 0 pins are configured individually by bit-pair settings in two control registers located in set 1, bank 0:  
P0CONL (low byte, E1H) and P0CONH (high byte, E0H).  
When you select output mode, a push-pull circuit is automatically configured. In input mode, three different  
selections are available:  
— Schmitt trigger input with interrupt generation on falling signal edges.  
— Schmitt trigger input with interrupt generation on rising signal edges.  
— Schmitt trigger input with interrupt generation on falling/rising signal edges.  
Port 0 Interrupt Enable and Pending Registers (P0INT, P0PND)  
To process external interrupts at the port 0 pins, two additional control registers are provided: the port 0 interrupt  
enable register P0INT (E2H, set 1, bank 0) and the port 0 interrupt pending register P0PND (E3H, set 1, bank 0).  
The port 0 interrupt pending register P0PND lets you check for interrupt pending conditions and clear the pending  
condition when the interrupt service routine has been initiated. The application program detects interrupt requests by  
polling the P0PND register at regular intervals.  
When the interrupt enable bit of any port 0 pin is “1”, a rising or falling signal edge at that pin will generate an  
interrupt request. The corresponding P0PND bit is then automatically set to “1” and the IRQ level goes low to signal  
the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software  
must the clear the pending condition by writing a “0” to the corresponding P0PND bit.  
9-3  
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I/O PORTS  
S3C8245/P8245/C8249/P8249  
Port 0 Control Register, High Byte (P0CONH)  
E0H, Set 1, Bank 0, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
P0.7  
(INT7)  
P0.6  
(INT6)  
P0.5  
(INT5)  
P0.4  
(INT4)  
P0CONH bit-pair pin configuration:  
00  
01  
10  
11  
Schmitt trigger input mode, pull-up, interrupt on falling edge  
Schmitt trigger input mode, interrupt on rising edge  
Schmitt trigger input mode, interrupt on rising or falling edge  
Output mode, push-pull  
Figure 9-1. Port 0 High-Byte Control Register (P0CONH)  
Port 0 Control Register, Low Byte (P0CONL)  
E1H, Set 1, Bank 0, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
P0.3  
(INT3)  
P0.2  
(INT2)  
P0.1  
(INT1)  
P0.0  
(INT0)  
P0CONL bit-pair pin configuration:  
00  
01  
10  
11  
Schmitt trigger input mode, pull-up, interrupt on falling edge  
Schmitt trigger input mode, interrupt on rising edge  
Schmitt trigger input mode, interrupt on rising or falling edge  
Output mode, push-pull  
Figure 9-2. Port 0 Low-Byte Control Register (P0CONL)  
9-4  
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I/O PORTS  
Port 0 Interrupt Control Register (P0INT)  
E2H, Set 1, Bank 0, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0  
P0INT bit configuration settings:  
0
1
Interrupt Disable  
Interrupt Enable  
Figure 9-3. Port 0 Interrupt Control Register (P0INT)  
Port 0 Interrupt Pending Register (P0PND)  
E3H, Set 1, Bank 0, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
PND7 PND6 PND5 PND4 PND3 PND2 PND1 PND0  
P0PND bit configuration settings:  
0
1
Interrupt request is not pending,  
pending bit clear when write 0  
Interrupt request is pending  
Figure 9-4. Port 0 Interrupt Pending Register (P0PND)  
9-5  
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I/O PORTS  
PORT 1  
S3C8245/P8245/C8249/P8249  
Port 1 is an 8-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading  
the port 1 data register, P1 at location F7H in set 1, bank 0. P1.0–P1.7 can serve inputs, as outputs  
(push pull or open-drain) or you can configure the following alternative functions:  
— Low-byte pins (P1.0-P1.3): T1CAP, T1CLK, T1OUT, T1PWM  
— High-byte pins (P1.4-P1.7): SCK, SI, SO and BUZ  
Port 1 Control Register  
Port 1 has two 8-bit control registers: P1CONH for P1.4–P1.7 and P1CONL for P1.0–P1.3. A reset clears the  
P1CONH and P1CONL registers to “00H”, configuring all pins to input mode. You use control registers settings to  
select input or output mode (push-pull or open drain) and enable the alternative functions.  
When programming the port, please remember that any alternative peripheral I/O function you configure using the  
port 1 control registers must also be enabled in the associated peripheral module.  
Port 1 Pull-up Resistor Enable Register (P1PUP)  
Using the port 1 pull-up resistor enable register, P1PUP (F5H, set 1, bank 0), you can configure pull-up resistors to  
individual port 1 pins.  
Port 1 Control Register, High Byte (P1CONH)  
E4H, Set 1, Bank 0, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
P1.4/BUZ  
P1.5/SO  
P1.6/SCK  
P1.7/SI  
P1CONH bit-pair pin configuration settings:  
00  
01  
10  
11  
Input mode (SI, SCK in)  
Output mode, open-drain  
Alternative function (SCK out, BUZ, SO, P1.7 is push-pull output)  
Output mode, push-pull  
NOTE: When use this port 1, user must be care of the pull-up resistance status.  
Figure 9-5. Port 1 High-Byte Control Register (P1CONH)  
9-6  
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I/O PORTS  
Port 1 Control Register, Low Byte (P1CONL)  
E5H, Set 1, Bank 0, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
P1.0/T1CAP  
P1.1/T1CLK  
P1.2/T1OUT  
/T1PWM  
P1.3  
P1CONL bit-pair pin configuration settings:  
00  
01  
10  
Input mode (T1CAP, T1CLK)  
Output mode, open-drain  
Alternative function (T1OUT, T1PWM, other pins are push-pull  
are push-pull output mode)  
11  
Output mode, push-pull  
NOTE:  
When use this port 1, user must be care of the pull-up resistance status.  
Figure 9-6. Port 1 Low-Byte Control Register (P1CONL)  
Port 1 Pull-up Control Register (P1PUR)  
F5H, Set 1, Bank 0, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0  
P1PUP bit configuration settings:  
0
1
Pull-up Disable  
Pull-up Enable  
Figure 9-7. Port 1 Pull-up Control Register (P1PUP)  
9-7  
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I/O PORTS  
PORT 2  
S3C8245/P8245/C8249/P8249  
Port 2 is an 8-bit I/O port that can be used for general-purpose I/O as A/D converter inputs, ADC0–ADC7. The pins  
are accessed directly by writing or reading the port 2 data register, P2 at location F8H in set 1, bank 0.  
To individually configure the port 2 pins P2.0–P2.7, you make bit-pair settings in two control registers located in set  
1, bank 0: P2CONL (low byte, E7H) and P2CONH (high byte, E6H). In input mode, ADC or external reference voltage  
input are also available.  
Port 2 Control Registers  
Two 8-bit control registers are used to configure port 2 pins: P2CONL (E7H, set 1, Bank 0) for pins P2.0–P2.3 and  
P2CONH (E6H, set 1, Bank 0) for pins P2.4–P2.7. Each byte contains four bit-pairs and each bit-pair configures one  
port 2 pin. The P2CONH and the P2CONL registers also control the alternative functions.  
Port 2 Control Register, High Byte (P2CONH)  
E6H, Set 1, Bank 0, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
P2.4 (ADC4)  
P2.5 (ADC5)  
P2.6 (ADC6)  
P2.7  
(VLDREF/ADC7)  
P2CONH bit-pair pin configuration:  
00  
01  
10  
Input mode  
Output mode, pull-up  
Alternative function (ADC & VLD External input ENABLE,  
ADCEN signal Gen.)  
11  
Output mode, push-pull  
NOTE:  
If a pin is enabled for ADC mode by ADCEN or ADC & VLD  
ENABLE signal, normal I/O and pull-up resistance are disabled.  
When pins are enabled for ADC mode, the pins can be selected for  
ADC input by ADCON.6. 5. 4.  
And the P2.7 can be used for VLD external input.  
Figure 9-8. Port 2 High-Byte Control Register (P2CONH)  
9-8  
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I/O PORTS  
Port 2 Control Register,Low Byte (P2CONL)  
E7H, Set 1, Bank 0, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
P2.0 (ADC0)  
P2.1 (ADC1)  
P2.2 (ADC2)  
P2.3 (ADC3)  
P2CONL bit-pair pin configuration:  
00  
01  
10  
11  
Input mode  
Input mode, pull-up  
Alternative function (ADC mode)  
Output mode, push-pull  
NOTE:  
If a pin is enabled for ADC mode by ADCEN, normal I/O and  
pull-up resistance are disabled.  
When pins are enabled for ADC mode by ADCEN, the pins can  
be selected for ADC input by ADCON.6.5.4.  
Figure 9-9. Port 2 Low-Byte Control Register (P2CONL)  
9-9  
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I/O PORTS  
PORT 3  
S3C8245/P8245/C8249/P8249  
Port 3 is an 5-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading  
the port 3 data register, P3 at location F9H in set 1, bank 0. P3.0–P3.3 can serve as inputs (with or without pull-ups),  
as push-pull outputs, or you can configure the following alternative functions:  
— TACAP, TACLK, TAOUT, TAPWM and TBPWM  
Port 3 Control Registers  
Port 3 has two 8-bit control registers: P3CONH for P3.4 and P3CONL for P3.0–P3.3. A reset clears the P3CONH  
and P3CONL registers to “00H”, configuring all pins to input mode. You use control registers settings to select input  
or output mode, enable pull-up resistors, and enable the alternative functions.  
When programming this port, please remember that any alternative peripheral I/O function you configure using the  
port 3 control registers must also be enabled in the associated peripheral module.  
Port 3 Control high Register, High Byte (P3CONH)  
E8H, Set 1, Bank 0, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Not used  
P3.4  
P3CONH bit-pair pin configuration settings:  
00  
01  
1x  
Input mode  
Input mode, pull-up  
Output mode, push-pull  
Figure 9-10. Port 3 High-Byte Control Register (P3CONH)  
9-10  
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I/O PORTS  
Port 3 Control Register, Low Byte (P3CONL)  
E9H, Set 1, Bank 0, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
P3.0/TBPWM  
P3.1/TAOUT/  
TAPWM  
P3.2/TACLK  
P3.3/TACAP  
P3CONL bit-pair pin configuration settings:  
00  
Input mode (TACAP, TACLK)  
Input mode, pull-up (TACAP)  
01  
10  
Alternative function (TAOUT,TAPWM, TBPWM  
P3.2, P3.3 is push-pull output mode)  
11  
Output mode, push-pull  
Figure 9-11. Port 3 Low-Byte Control Register (P3CONL)  
9-11  
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I/O PORTS  
PORT 4  
S3C8245/P8245/C8249/P8249  
Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading  
the port 4 data register, P4 at location FAH in set 1, bank 0. P4.0–P4.7 can serve as inputs (with or without pull-  
ups), as output (open drain or push-pull). And, they can serve as segment pins for LCD, also.  
Port 4 Control Registers  
Port 4 has two 8-bit control registers: P4CONH for P4.4–P4.7 and P4CONL for P4.0–P4.3. A reset clears the  
P4CONH and P4CONL registers to “00H”, configuring all pins to input mode.  
Port 4 Control Register, High Byte (P4CONH)  
ECH, Set 1, Bank 1, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
P4.4/SEG20  
P4.5/SEG21  
P4.6/SEG22  
P4.7/SEG23  
P4CONH bit-pair pin configuration settings:  
00  
01  
10  
Input mode  
Input mode, pull-up  
Opendrain output mode  
11  
Output mode, push-pull  
NOTE:  
If LCD is enabled by LCON.5, SEG signal go out  
otherwise port 4 I/0 can be selected.  
Figure 9-12. Port 4 High-Byte Control Register (P4CONH)  
9-12  
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S3C8245/P8245/C8249/P8249  
I/O PORTS  
Port 4 Control Register, Low Byte (P4CONL)  
EDH, Set 1, Bank 1, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
P4.0/SEG16  
P4.1/SEG17  
P4.2/SEG18  
P4.3/SEG19  
P4CONL bit-pair pin configuration settings:  
00  
01  
10  
Input mode  
Input mode, pull-up  
Opendrain output mode  
11  
Output mode, push-pull  
NOTE:  
If LCD is enabled by LCON.4, SEG signal go out  
otherwise port 4 I/0 can be selected.  
Figure 9-13. Port 4 Low-Byte Control Register (P4CONL)  
9-13  
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I/O PORTS  
PORT 5  
S3C8245/P8245/C8249/P8249  
Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading  
the port 5 data register, P5 at location FBH in set 1, bank 0. P5.0–P5.7 can serve as inputs (with without pull-ups),  
as output (open drain or push-pull). And, they can serve as segment pins for LCD also.  
Port 5 Control Registers  
Port 5 has two 8-bit control registers: P5CONH for P5.4–P5.7 and P5CONL for P5.0–P5.3. A reset clears the  
P5CONH and P5CONL registers to “00H”, configuring all pins to input mode.  
Port 5 Control Register, High Byte (P5CONH)  
EEH, Set 1, Bank 1, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
P5.4/SEG28  
P5.5/SEG29  
P5.6/SEG30  
P5.7/SEG31  
P5CONH bit-pair pin configuration settings:  
00  
01  
10  
Input mode  
Input mode, pull-up  
Opendrain output mode  
11  
Output mode, push-pull  
NOTE:  
If LCD is enabled by LCON.7, SEG signal go out  
otherwise port 5 I/0 can be selected.  
Figure 9-14. Port 5 High-Byte Control Register (P5CONH)  
9-14  
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I/O PORTS  
Port 5 Control Register, Low Byte (P5CONL)  
EFH, Set 1, Bank 1, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
P5.0/SEG24  
P5.1/SEG25  
P5.2/SEG26  
P5.3/SEG27  
P5CONL bit-pair pin configuration settings:  
00  
01  
10  
Input mode  
Input mode, pull-up  
Opendrain output mode  
11  
Output mode, push-pull  
NOTE:  
If LCD is enabled by LCON.6, SEG signal go out  
otherwise port 5 I/0 can be selected.  
Figure 9-15. Port 5 Low-Byte Control Register (P5CONL)  
9-15  
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I/O PORTS  
S3C8245/P8245/C8249/P8249  
NOTES  
9-16  
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S3C8245/P8245/C8249/P8249  
BASIC TIMER  
10  
BASIC TIMER  
OVERVIEW  
S3C8245/C8249 has an 8-bit basic timer .  
BASIC TIMER (BT)  
You can use the basic timer (BT) in two different ways:  
— As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction, or  
— To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.  
The functional components of the basic timer block are:  
— Clock frequency divider (fxx divided by 4096, 1024, 128, or 16) with multiplexer  
— 8-bit basic timer counter, BTCNT (set 1, Bank 0, FDH, read-only)  
— Basic timer control register, BTCON (set 1, D3H, read/write)  
BASIC TIMER CONTROL REGISTER (BTCON)  
The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter  
and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1, address D3H, and  
is read/write addressable using Register addressing mode.  
A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of  
fxx/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer register  
control bits BTCON.7–BTCON.4.  
The 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH), can be cleared at any time during the normal operation  
by writing a "1" to BTCON.1. To clear the frequency dividers, write a "1" to BTCON.0.  
10-1  
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BASIC TIMER  
S3C8245/P8245/C8249/P8249  
Basic TImer Control Register (BTCON)  
D3H, Set 1, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Divider clear bit:  
0 = No effect  
1= Clear dvider  
Watchdog timer enable bits:  
1010B = Disable watchdog function  
Other value = Enable watchdog function  
Basic timer counter clear bit:  
0 = No effect  
1= Clear BTCNT  
Basic timer input clock selection bits:  
00 = fXX/4096  
01 = fXX/1024  
10 = fXX/128  
11 = fXX/16  
Figure 10-1. Basic Timer Control Register (BTCON)  
10-2  
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BASIC TIMER  
BASIC TIMER FUNCTION DESCRIPTION  
Watchdog Timer Function  
You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any  
value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to "00H",  
automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the  
current CLKCON register setting), divided by 4096, as the BT clock.  
The MCU is reseted whenever a basic timer counter overflow occurs, During normal operation, the application  
program must prevent the overflow, and the accompanying reset operation, from occuring, To do this, the BTCNT  
value must be cleared (by writing a “1” to BTCON.1) at regular intervals.  
If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will  
not be executed and a basic timer overflow will occur, initiating a reset. In other words, during the normal operation,  
the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT  
clear instruction. If a malfunction does occur, a reset is triggered automatically.  
Oscillation Stabilization Interval Timer Function  
You can also use the basic timer to program a specific oscillation stabilization interval after a reset or when stop  
mode has been released by an external interrupt.  
In stop mode, whenever a reset or an external interrupt occurs, the oscillator starts.. The BTCNT value then starts  
increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an external interrupt). When  
BTCNT.4 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock  
signal off to the CPU so that it can resume the normal operation.  
In summary, the following events occur when stop mode is released:  
1. During the stop mode, a power-on reset or an external interrupt occurs to trigger the Stop mode release and  
oscillation starts.  
2. If a power-on reset occurred, the basic timer counter will increase at the rate of fxx/4096. If an interrupt is used  
to release stop mode, the BTCNT value increases at the rate of the preset clock source.  
3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows.  
4. When a BTCNT.4 overflow occurs, the normal CPU operation resumes.  
10-3  
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BASIC TIMER  
S3C8245/P8245/C8249/P8249  
nRESET or STOP  
Data Bus  
Bit 1  
Bits 3, 2  
Basic Timer Control Register  
(Write '1010xxxxB' to Disable)  
fXX/4096  
fXX/1024  
fXX/128  
fXX/16  
Clear  
8-Bit Up Counter  
(BTCNT, Read-Only)  
fXX  
DIV  
MUX  
OVF  
nRESET  
Start the CPU (NOTE)  
R
Bit 0  
NOTE:  
During a power-on reset operation, the CPU is idle during the required oscillation  
stabilization interval (until bit 4 of the basic timer counter overflows).  
Figure 10-2. Basic Timer Block Diagram  
10-4  
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S3C8245/P8245/C8249/P8249  
8-BIT TIMER A/B  
11  
8-BIT TIMER A/B  
8-BIT TIMER A  
OVERVIEW  
The 8-bit timer A is an 8-bit general-purpose timer/counter. Timer A has three operating modes, one of which you  
select using the appropriate TACON setting:  
— Interval timer mode (Toggle output at TAOUT pin)  
— Capture input mode with a rising or falling edge trigger at the TACAP pin  
— PWM mode (TAPWM)  
Timer A has the following functional components:  
— Clock frequency divider (fxx divided by 1024, 256, or 64 ) with multiplexer  
— External clock input pin ( TACLK)  
— 8-bit counter (TACNT), 8-bit comparator, and 8-bit reference data register (TADATA)  
— I/O pins for capture input (TACAP) or PWM or match output (TAPWM, TAOUT)  
— Timer A overflow interrupt (IRQ0, vector E2H) and match/capture interrupt (IRQ0, vector E0H) generation  
— Timer A control register, TACON (set 1, EDH, read/write)  
11-1  
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8-BIT TIMER A/B  
S3C8245/P8245/C8249/P8249  
FUNCTION DESCRIPTION  
Timer A Interrupts (IRQ0, Vectors E0H and E2H)  
The timer A module can generate two interrupts: the timer A overflow interrupt (TAOVF), and the timer A match/  
capture interrupt (TAINT). TAOVF is interrupt level IRQ0, vector E2H. TAINT also belongs to interrupt level IRQ0, but  
is assigned the separate vector address, E0H.  
Pending condition of timer A interrupts (overflow & match/capture) can be cleared automatically by hardware where  
the interrupts are enabled. Otherwise pending condition must be cleared manually by software.  
Interval Timer Function  
The timer A module can generate an interrupt: the timer A match interrupt (TAINT). TAINT belongs to interrupt level  
IRQ0, and is assigned the separate vector address, E0H.  
When timer A match interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by  
hardware.  
In interval timer mode, a match signal is generated and TAOUT is toggled when the counter value is identical to the  
value written to the TA reference data register, TADATA. The match signal generates a timer A match interrupt  
(TAINT, vector E0H) and clears the counter.  
If, for example, you write the value 10H to TADATA and 0AH to TACON, the counter will increment until it reaches  
10H. At this point, the TA interrupt request is generated, the counter value is reset, and counting resumes.  
Pulse Width Modulation Mode  
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the TAPWM  
pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to  
the timer A data register. In PWM mode, however, the match signal does not clear the counter. Instead, it runs  
continuously, overflowing at FFH, and then continues incrementing from 00H.  
Although timer A overflow interrupt is occurred, this interrupt is not typically used in PWM-type applications. Instead,  
the pulse at the TAPWM pin is held to Low level as long as the reference data value is less than or equal to ( £ ) the  
counter value and then the pulse is held to High level for as long as the data value is greater than ( > ) the counter  
value. One pulse width is equal to t  
• 256 .  
CLK  
Capture Mode  
In capture mode, a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value  
into the TA data register. You can select rising or falling edges to trigger this operation.  
Timer A also gives you capture input source: the signal edge at the TACAP pin. You select the capture input by  
setting the value of the timer A capture input selection bit in the port 3 control register, P3CONL, (set 1, bank 0,  
E9H). When P3CONL.7.6 is 00, the TACAP input or normal input is selected. When P3CONL.7.6 is set to 11,  
normal output is selected.  
Both kinds of timer A interrupts can be used in capture mode: the timer A overflow interrupt is generated whenever a  
counter overflow occurs; the timer A match/capture interrupt is generated whenever the counter value is loaded into  
the TA data register.  
By reading the captured data value in TADATA, and assuming a specific value for the timer A clock frequency, you  
can calculate the pulse width (duration) of the signal that is being input at the TACAP pin.  
11-2  
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S3C8245/P8245/C8249/P8249  
8-BIT TIMER A/B  
TIMER A CONTROL REGISTER (TACON)  
You use the timer A control register, TACON, to  
— Select the timer A operating mode (interval timer, capture mode, or PWM mode)  
— Select the timer A input clock frequency  
— Clear the timer A counter, TACNT  
— Enable the timer A overflow interrupt or timer A match/capture interrupt  
— Clear timer A match/capture interrupt pending conditions  
TACON is located in set 1, Bank 0 at address EDH, and is read/write addressable using Register addressing mode.  
A reset clears TACON to '00H'. This sets timer A to normal interval timer mode, selects an input clock frequency of  
fxx/1024, and disables all timer A interrupts. You can clear the timer A counter at any time during normal operation  
by writing a "1" to TACON.3.  
The timer A overflow interrupt (TAOVF) is interrupt level IRQ0 and has the vector address E2H. When a timer A  
overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware.  
Timer A Control Register (TACON)  
EDH, Set 1, Bank 0, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Timer A input clock selection bits:  
00 = fXX/1024  
Timer A match/capture interrupt  
pending bit:  
01 = fXX/256  
10 = fXX/64  
11 = External clock (TACLK)  
0 = No interrupt pending  
0 = Clear pending bit (write)  
1 = Interrupt is pending  
Timer A match/capture interrupt  
enable bit:  
0 = DIsable interrupt  
1 = Enable interrupt  
Timer A operating mode selection bits:  
00 = Interval mode (TAOUT mode)  
01 = Capture mode (capture on rising edge,  
Counter running, OVF can occur)  
10 = Capture mode (Capture on falling edge,  
Counter running, OVF can occur)  
11 = PWM mode (OVF interrupt can occur)  
Timer A overflow interrupt enable:  
0 = Disable overflow interrupt  
1 = Enable overflow interrupt  
Timer A counter clear bit:  
0 = No affect  
1 = Clear the timer A counter (when write)  
Figure 11-1. Timer A Control Register (TACON)  
11-3  
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8-BIT TIMER A/B  
S3C8245/P8245/C8249/P8249  
BLOCK DIAGRAM  
TACON.2  
TAOVF  
Overflow  
Clear  
Pending  
TACON.7-.6  
Data Bus  
8
TACON.3  
fXX /1024  
M
U
X
fXX /256  
fXX /64  
TACON.1  
8-bit Up-Counter  
(Read Only)  
TACLK  
TAINT  
M
U
X
Match  
8-bit Comparator  
TACON.0  
Pending  
M
U
X
TACAP  
Timer A Buffer Reg  
TAOUT  
TAPWM  
TACON.5.4  
TACON.5.4  
Timer A Data Register  
(Read/Write)  
8
Data Bus  
Pending  
Pending bit is located at INTPND register.  
NOTE:  
Timer A input clock must be slower than CPU clock.  
Figure 11-2. Timer A Functional Block Diagram  
11-4  
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S3C8245/P8245/C8249/P8249  
8-BIT TIMER A/B  
8-BIT TIMER B  
OVERVIEW  
The S3C8245/C8249 micro-controller has an 8-bit counter called timer B. Timer B, which can be used to generate  
the carrier frequency of a remote controller signal.  
Pending condition of timer B is cleared automatically by hardware.  
Timer B has two functions:  
— As a normal interval timer, generating a timer B interrupt at programmed time intervals.  
— To supply a clock source to the 16-bit timer/counter module, timer 0, for generating the timer 0 overflow interrupt.  
TBCON.6-.7  
TBCON.2  
fXX /1  
fXX /2  
fXX /4  
fXX /8  
M
U
X
CLK  
8-bit  
Down Counter  
TBCON.0  
(TBOF)  
To Other Block  
(P3.0/TBPWM)  
TBCON.3  
Repeat Control  
Interrupt Control  
MUX  
IRQ1  
(TBINT)  
INT.GEN  
Timer B Data  
Low Byte Register  
TBCON.4-.5  
Timer B Data  
High Byte Register  
8
Data Bus  
NOTES:  
1. The value of the TBDATAL register is loaded into the 8-bit counter when the operation of the timer B starts.  
If a borrow occurs in the counter, the value of the TBDATAH register is loaded into the 8-bit counter.  
However, if the next borrow occurs, the value of the TBDATAL register is loaded into the 8-bit counter.  
2. Timer B input clock must be slower than CPU clock.  
Figure 11-3. Timer B Functional Block Diagram  
11-5  
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8-BIT TIMER A/B  
S3C8245/P8245/C8249/P8249  
Timer B Control Register (TBCON)  
ECH, Set 1, Bank 0, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Timer B input clock selection bits:  
00 = fxx  
Timer B output flip-flop control bit:  
0 = TBOF is low  
01 = fxx/2  
10 = fxx/4  
11 = fxx/8  
1 = TBOF is high  
Timer B mode selection bit:  
0 = One-shot mode  
1 = Repeating mode  
Timer B interrupt time selection bits:  
00 = Elapsed time for low data value  
01 = Elapsed time for high data value  
10 = Elapsed time for low and high data values  
11 = Invalid setting  
Timer B start/stop bit:  
0 = Stop timer B  
1 = Start timer B  
Timer B interrupt enable bit:  
0 = Disable interrupt  
1 = Enable interrupt  
Figure 11-4. Timer B Control Register (TBCON)  
Timer B Data Register, High Byte (TBDATAH)  
FAH, Set 1, Bank 0, R/W  
MSB  
MSB  
.7  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
LSB  
Reset Value: FFh  
Timer B Data Register, Low-Byte (TBDATAL)  
EBH, Set 1, Bank 0, R/W  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
Reset Value: FFh  
Figure 11-5. Timer B Data Registers (TBDATAH/L)  
11-6  
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S3C8245/P8245/C8249/P8249  
8-BIT TIMER A/B  
TIMER B PULSE WIDTH CALCULATIONS  
tHIGH  
tLOW  
tLOW  
To generate the above repeated waveform consisted of low period time, t  
When TBOF = 0,  
, and high period time, t  
.
LOW  
HIGH  
t
t
= (TBDATAL + 2) x 1/fx, 0H < TBDATAL < 100H, where fx = The selected clock.  
= (TBDATAH + 2) x 1/fx, 0H < TBDATAH < 100H, where fx = The selected clock.  
LOW  
HIGH  
When TBOF = 1,  
t
t
= (TBDATAH + 2) x 1/fx, 0H < TBDATAH < 100H, where fx = The selected clock.  
LOW  
HIGH  
= (TBDATAL + 2) x 1/fx, 0H < TBDATAL < 100H, where fx = The selected clock.  
To make t  
= 24 us and t  
= 15 us. f  
= 4 MHz, fx = 4 MHz/4 = 1 MHz  
LOW  
HIGH  
OSC  
When TBOF = 0,  
t
t
= 24 us = (TBDATAL + 2) /fx = (TBDATAL + 2) x 1us, TBDATAL = 22.  
= 15 us = (TBDATAH + 2) /fx = (TBDATAH + 2) x 1us, TBDATAH = 13.  
LOW  
HIGH  
When TBOF = 1,  
t
t
= 15 us = (TBDATAL + 2) /fx = (TBDATAL + 2) x 1us, TBDATAL = 13.  
HIGH  
LOW  
= 24 us = (TBDATAH + 2) /fx = (TBDATAH + 2) x 1us, TBDATAH = 22.  
11-7  
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8-BIT TIMER A/B  
S3C8245/P8245/C8249/P8249  
0H  
Timer B Clock  
TBOF = '0'  
TBDATAL = 01-FFH  
TBDATAH = 00H  
Low  
High  
Low  
High  
TBOF = '0'  
TBDATAL = 00H  
TBDATAH = 01-FFH  
TBOF = '0'  
TBDATAL = 00H  
TBDATAH = 00H  
TBOF = '1'  
TBDATAL = 00H  
TBDATAH = 00H  
0H  
100H  
200H  
Timer B Clock  
E0H  
E0H  
TBOF = '1'  
TBDATAL = DEH  
TBDATAH = 1EH  
20H  
TBOF = '0'  
TBDATAL = DEH  
TBDATAH = 1EH  
20H  
TBOF = '1'  
80H  
TBDATAL = 7EH  
TBDATAH = 7EH  
80H  
TBOF = '0'  
80H  
TBDATAL = 7EH  
TBDATAH = 7EH  
80H  
Figure 11-6. Timer B Output Flip-Flop Waveforms in Repeat Mode  
11-8  
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S3C8245/P8245/C8249/P8249  
8-BIT TIMER A/B  
F
PROGRAMMING TIP — To generate 38 kHz, 1/3duty signal through P3.0  
This example sets Timer B to the repeat mode, sets the oscillation frequency as the Timer B clock source, and  
TBDATAH and TBDATAL to make a 38 kHz,1/3 Duty carrier frequency. The program parameters are:  
8.795  
ms  
17.59  
ms  
37.9 kHz 1/3 Duty  
— Timer B is used in repeat mode  
— Oscillation frequency is 4 MHz (0.25 ms)  
— TBDATAH = 8.795 ms/0.25 ms = 35.18, TBDATAL = 17.59 ms/0.25 ms = 70.36  
— Set P3.0 to TBPWM mode.  
ORG  
DI  
•
0100H  
;
Reset address  
START  
•
•
LD  
LD  
LD  
TBDATAL,#(70-2)  
TBDATAH,#(35-2)  
TBCON,#00000110B  
;
;
;
;
;
Set 17.5 ms  
Set 8.75 ms  
Clock Source ¬ fxx  
Disable Timer B interrupt.  
Select repeat mode for Timer B.  
; Start Timer B operation.  
; Set Timer B Output flip-flop (TBOF) high.  
;
LD  
P3CONL,#02H  
;
;
Set P3.0 to TBPWM mode.  
This command generates 38 kHz, 1/3 duty pulse signal  
through P3.0.  
•
•
•
11-9  
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8-BIT TIMER A/B  
S3C8245/P8245/C8249/P8249  
F
PROGRAMMING TIP — To generate a one pulse signal through P3.0  
This example sets Timer B to the one shot mode, sets the oscillation frequency as the Timer B clock source, and  
TBDATAH and TBDATAL to make a 40 ms width pulse. The program parameters are:  
40  
ms  
— Timer B is used in one shot mode  
— Oscillation frequency is 4 MHz (1 clock = 0.25 ms)  
— TBDATAH = 40 ms / 0.25 ms = 160, TBDATAL = 1  
— Set P3.0 to TBPWM mode  
ORG  
DI  
•
0100H  
;
Reset address  
START  
•
•
LD  
LD  
LD  
TBDATAH,# (160-2)  
TBDATAL,# 1  
TBCON,#00000001B  
;
;
;
Set 40 ms  
Set any value except 00H  
Clock Source ¬ f  
OSC  
;
;
Disable Timer B interrupt.  
Select one shot mode for Timer B.  
; Stop Timer B operation.  
; Set Timer B output flip-flop (TBOF) high  
LD  
•
P3CONL, #02H  
;
Set P3.0 to TBPWM mode.  
•
Pulse_out:  
LD  
TBCON,#00000101B  
;
;
;
;
Start Timer B operation  
to make the pulse at this point.  
After the instruction is executed, 0.75 ms is required  
before the falling edge of the pulse starts.  
•
•
•
11-10  
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S3C8245/P8245/C8249/P8249  
16-BIT TIMER 0/1  
12  
16-BIT TIMER 0/1  
16-BIT TIMER 0  
OVERVIEW  
The 16-bit timer 0 is an 16-bit general-purpose timer. Timer 0 has the interval timer mode by using the appropriate  
T0CON setting.  
Timer 0 has the following functional components:  
— Clock frequency divider (fxx divided by 256, 64, 8 or 1) with multiplexer  
— TBOF (from timer B) is one of the clock frequencies.  
— 16-bit counter (T0CNTH/L), 16-bit comparator, and 16-bit reference data register (T0DATAH/L)  
— Timer 0 interrupt (IRQ2, vector E6H) generation  
— Timer 0 control register, T0CON (set 1, Bank 1, F1H, read/write)  
FUNCTION DESCRIPTION  
Interval Timer Function  
The timer 0 module can generate an interrupt, the timer 0 match interrupt (T0INT). T0INT belongs to interrupt level  
IRQ2, and is assigned the separate vector address, E6H.  
The T0INT pending condition is automatically cleared by hardware when it has been serviced. Even though T0INT is  
disabled, the application’s service routine can detect a pending condition of T0INT by the software and execute it’s  
sub-routine. When this case is used, the T0INT pending bit must be cleared by the application subroutine by writing  
a “0” to the T0CON.0 pending bit.  
In interval timer mode, a match signal is generated when the counter value is identical to the values written to the T0  
reference data registers, T0DATAH/L. The match signal generates a timer 0 match interrupt (T0INT, vector E4H) and  
clears the counter.  
If, for example, you write the value 0010H to T0DATAH/L and 0FH to T0CON, the counter will increment until it  
reaches 10H. At this point, the T0 interrupt request is generated, the counter value is reset, and counting resumes.  
12-1  
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16-BIT TIMER 0/1  
S3C8245/P8245/C8249/P8249  
TIMER 0 CONTROL REGISTER (T0CON)  
You use the timer 0 control register, T0CON, to  
— Enable the timer 0 operating (interval timer)  
— Select the timer 0 input clock frequency  
— Clear the timer 0 counter, T0CNT  
— Enable the timer 0 interrupt and clear timer 0 interrupt pending condition  
T0CON is located in set 1, at address F1H, and is read/write addressable using register addressing mode.  
A reset clears T0CON to "00H". This sets timer 0 to disable interval timer mode, selects the TBOF, and disables  
timer 0 interrupt. You can clear the timer 0 counter at any time during normal operation by writing a “1” to T0CON.3  
To enable the timer 0 interrupt (IRQ2, vector E6H), you must write T0CON.2, and T0CON.1 to "1". To generate the  
exact time interval, you should write T0CON.3 and 0, which cleared counter and interrupt pending bit. To detect an  
interrupt pending condition when T0INT is disabled, the application program polls pending bit, T0CON.0. When a "1"  
is detected, a timer 0 interrupt is pending. When the T0INT sub-routine has been serviced, the pending condition  
must be cleared by software by writing a "0" to the timer 0 interrupt pending bit, T0CON.0.  
Timer 0 Control Registers (T0CON)  
F1H, Set 1, Bank 1, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Timer 0 input clock selection bits:  
000 = TBOF  
Timer 0 interrupt pending bit:  
0 = No interrupt pending  
010 = fXX/256  
100 = fXX/64  
0 = Clear pending bit (when write)  
1 = Interrupt is pending  
110 = fXX/8  
XX1 = fXX  
Timer 0 interrupt enable bit:  
0 = Disable interrupt  
1 = Enable interrupt  
Not used  
Timer 0 count enable bit:  
0 = Disable counting operation  
1 = Enable counting operation  
Timer 0 counter clear bit:  
0 = No affect  
1 = Clear the timer 0 counter (when write)  
NOTE:  
For normal operation T0CON.3 bit must be set 1.  
Figure 12-1. Timer 0 Control Register (T0CON)  
12-2  
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S3C8245/P8245/C8249/P8249  
BLOCK DIAGRAM  
16-BIT TIMER 0/1  
Bits 7, 6, 5  
Data Bus  
8
Bit 3  
TBOF  
fxx/256  
fxx/64  
M
U
X
16-bit up-Counter H/L  
(Read Only)  
R
Clear  
Match  
fxx/8  
fxx/1  
Pending  
Bit 0  
T0INT  
IRQ2  
16-bit Comparator  
Timer 0 Buffer Reg  
Bit 2  
Bit 1  
Counter clear signal (T0CON.3)  
Timer 0 Data H/L Reg  
(Read/Write)  
8
Data Bus  
NOTES:  
1. To be loaded T0DATA value to buffer register for comparing, T0CON.3 bit must be set 1.  
2. Timer 0 input clock must be slower than CPU clock.  
Figure 12-2. Timer 0 Functional Block Diagram  
12-3  
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16-BIT TIMER 0/1  
S3C8245/P8245/C8249/P8249  
Timer 0 Counter Register, High-Byte (T0CNTH)  
F2H, Set 1, Bank 1, R  
MSB  
MSB  
.7  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Reset Value: 00H  
Timer 0 Counter Register, Low-Byte (T0CNTL)  
F3H, Set 1, Bank 1, R  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Reset Value: 00H  
Figure 12-3. Timer 0 Counter Register (T0CNTH/L)  
Timer 0 Data Register, High-Byte (T0DATAH)  
F4H, Set 1, Bank 1, R/W  
MSB  
MSB  
.7  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
LSB  
Reset Value: FFh  
Timer 0 Data Register, Low-Byte (T0DATAL)  
F5H, Set 1, Bank 1, R/W  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
Reset Value: FFh  
Figure 12-4. Timer 0 Data Register (T0DATAH/L)  
12-4  
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S3C8245/P8245/C8249/P8249  
16-BIT TIMER 0/1  
16-BIT TIMER 1  
OVERVIEW  
The 16-bit timer 1 is an 16-bit general-purpose timer/counter. Timer 1 has three operating modes, one of which you  
select using the appropriate T1CON setting:  
— Interval timer mode (Toggle output at T1OUT pin)  
— Capture input mode with a rising or falling edge trigger at the T1CAP pin  
— PWM mode (T1PWM)  
Timer 1 has the following functional components:  
— Clock frequency divider (fxx divided by 1024, 256, 64, 8 or 1) with multiplexer  
— External clock input pin (T1CLK)  
— 16-bit counter (T1CNTH/L), 16-bit comparator, and 16-bit reference data register (T1DATAH/L)  
— I/O pins for capture input (T1CAP), or PWM or match output (T1PWM, T1OUT)  
— Timer 1 overflow interrupt (IRQ3, vector EAH) and match/capture interrupt (IRQ3, vector E8H) generation  
— Timer 1 control register, T1CON (set 1, FBH, Bank 1, read/write)  
12-5  
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16-BIT TIMER 0/1  
S3C8245/P8245/C8249/P8249  
FUNCTION DESCRIPTION  
Timer 1 Interrupts (IRQ3, Vectors E8H and EAH)  
The timer 1 module can generate two interrupts, the timer 1 overflow interrupt (T1OVF), and the timer 1  
match/capture interrupt (T1INT). T1OVF is interrupt level IRQ3, vector EAH. T1INT also belongs to interrupt level  
IRQ3, but is assigned the separate vector address, E8H.  
A timer 1 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced.  
A timer 1 match/capture interrupt, T1INT pending condition is also cleared by hardware when it has been serviced.  
Interval Timer Function  
The timer 1 module can generate an interrupt: the timer 1 match interrupt (T1INT). T1INT belongs to interrupt level  
IRQ3, and is assigned the separate vector address, E8H. When a timer 1 measure interrupt occurs and is serviced  
by the CPU, the pending condition is cleared automatically by hardware.  
In interval timer mode, a match signal is generated and T1OUT is toggled when the counter value is identical to the  
value written to the T1 reference data register, T1DATAH/L. The match signal generates a timer 1 match interrupt  
(T1INT, vector E8H) and clears the counter.  
If, for example, you write the value 0010H to T1DATAH/L and 06H to T1CON, the counter will increment until it  
reaches 0010H. At this point, the T1 interrupt request is generated, the counter value is reset, and counting  
resumes.  
Pulse Width Modulation Mode  
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T1PWM  
pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to  
the timer 1 data register. In PWM mode, however, the match signal does not clear the counter but can generate a  
match interrupt. The counter runs continuously, overflowing at FFFFH, and then repeat the incrementing from 0000H.  
Whenever an overflow is occurred, an overflow (OVF) interrupt can be generated.  
Although you can use the match or the overflow interrupt in PWM mode, interrupts are not typically used in PWM-  
type applications. Instead, the pulse at the T1PWM pin is held to Low level as long as the reference data value is  
less than or equal to (£) the counter value and then pulse is held to High level for as long as the data value is greater  
than (>) the counter value. One pulse width is equal to t  
CLK  
Capture Mode  
In capture mode, a signal edge that is detected at the T1CAP pin opens a gate and loads the current counter value  
into the T1 data register. You can select rising or falling edges to trigger this operation.  
Timer 1 also gives you capture input source, the signal edge at the T1CAP pin. You select the capture input by  
setting the value of the timer 1 capture input selection bit in the port 1 control register low, P1CONL, (set 1 bank 0,  
E5H). When P1CONL.1.0 is 00, the T1CAP input or normal input is selected .When P1CONL.1.0 is set to 11,  
normal output is selected.  
Both kinds of timer 1 interrupts can be used in capture mode, the timer 1 overflow interrupt is generated whenever a  
counter overflow occurs, the timer 1 match/capture interrupt is generated whenever the counter value is loaded into  
the T1 data register.  
By reading the captured data value in T1DATAH/L, and assuming a specific value for the timer 1 clock frequency,  
you can calculate the pulse width (duration) of the signal that is being input at the T1CAP pin.  
12-6  
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S3C8245/P8245/C8249/P8249  
16-BIT TIMER 0/1  
TIMER 1 CONTROL REGISTER (T1CON)  
You use the timer 1 control register, T1CON, to  
— Select the timer 1 operating mode (interval timer, capture mode, or PWM mode)  
— Select the timer 1 input clock frequency  
— Clear the timer 1 counter, T1CNTH/L  
— Enable the timer 1 overflow interrupt or timer 1 match/capture interrupt  
— Clear timer 1 match/capture interrupt pending conditions  
T1CON is located in set 1 and Bank 1 at address FBH, and is read/write addressable using Register addressing  
mode.  
A reset clears T1CON to ‘00H’. This sets timer 1 to normal interval timer mode, selects an input clock frequency of  
fxx/1024, and disables all timer 1 interrupts. To disable the counter operation, please set T1CON.7-.5 to 111B. You  
can clear the timer 1 counter at any time during normal operation by writing a “1” to T1CON.3.  
The timer 1 overflow interrupt (T1OVF) is interrupt level IRQ3 and has the vector address EAH. When a timer 1  
overflow interrupt occurs and is serviced interrupt (IRQ3, vector E8H), you must write T1CON.1 to “1”. To generate  
the exact time interval, you should write T1CON by the CPU, the pending condition is cleared automatically by  
hardware.  
To enable the timer 1 match/capture which clear counter and interrupt pending bit. To detect a match/capture or  
overflow interrupt pending condition when T1INT or T1OVF is disabled, the application program should poll the  
pending bit. When a “1” is detected, a timer 1 match/capture or overflow interrupt is pending.  
When her sub-routine has been serviced, the pending condition must be cleared by software by writing a “0” to the  
interrupt pending bit.  
Timer 1 Control Register (T1CON)  
FBH, Set 1, Bank 1, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Timer 1 overflow interrupt enable:  
1 = Enable overflow interrupt  
0 = Disable overflow interrupt  
Timer 1 input clock selection bits:  
000 = fXX/1024  
010 = fXX/256  
100 = fXX/64  
110 = fXX/8  
001 = fXX/1  
011 = External clock (T1CLK) falling edge  
101 = External clock (T1CLK) rising edge  
111 = Counter stop  
Timer 1 match/capture interrupt enable bit:  
0 = Disable interrupt  
1 = Enable interrupt  
Timer 1 counter clear bit:  
0 = No effect  
1 = Clear the timer 1 counter (when write)  
Timer 1 operating mode selection bits:  
00 = Interval mode  
01 = Capture mode (capture on rising edge, counter running, OVF can occur)  
10 = Capture mode (capture on falling edge, counter running, OVF can occur)  
11 = PWM mode (OVF & match interrupt can occur)  
Figure 12-5. Timer 1 Control Register (T1CON)  
12-7  
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16-BIT TIMER 0/1  
S3C8245/P8245/C8249/P8249  
BLOCK DIAGRAM  
T1CON.0  
T1OVF  
IRQ3  
OVF  
Pending  
T1CON.7-5  
Data Bus  
8
T1CON.2  
Clear  
f
/1024  
fXX /256  
fXXXX /64  
M
U
X
T1CON.1  
f
/8  
16-bit Up-Counter  
(Read Only)  
fXXXX /1  
R
T1CLK  
M
U
X
T1INT  
VSS  
16-bit Comparator  
Timer 1 Buffer Reg  
Pending  
IRQ3  
Match  
M
U
X
T1OUT  
T1PWM  
T1CAP  
T1CON.4-.3  
Counter Clear Signal or Match  
T1CON.4-.3  
Timer 1 Data H/L  
Register  
8
Data Bus  
Pending Pending bit is located at INTPND register  
NOTES:  
1. 16-bit PWM frequency. Where 10 MHz clock is used and fxx/8 is selected,  
PWM frequency = 1 / { (8/10 MHz) x FFFFh } = 19.07 Hz  
2. Timer 1 input clock must be slower than CPU clock.  
Figure 12-6. Timer 1 Functional Block Diagram  
12-8  
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S3C8245/P8245/C8249/P8249  
16-BIT TIMER 0/1  
Timer 1 Counter Register, High-Byte (T1CNTH)  
FCH, Set 1, Bank 1, R  
MSB  
.7  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
LSB  
Reset Value: 00H  
Timer 1 Counter Register, Low-Byte (T1CNTL)  
FDH, Set 1, Bank 1, R  
MSB  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
Reset Value: 00H  
Figure 12-7. Timer 1 Control Register (T1CNTH/L)  
Timer 1 Data Register,High-Byte (T1DATAH)  
FEH, Set 1, Bank 1, R/W  
MSB  
MSB  
.7  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
LSB  
Reset Value: FFh  
Timer 1 Data Register, Low-Byte (T1DATAL)  
FFH, Set 1, Bank 1, R/W  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
Reset Value: FFh  
NOTE:  
Pending bit is located in INTPND (D2H, set1) register.  
Figure 12-8. Timer 1 Data Register (T1DATAH/L)  
12-9  
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16-BIT TIMER 0/1  
S3C8245/P8245/C8249/P8249  
NOTES  
12-10  
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S3C8245/P8245/C8249/P8249  
WATCH TIMER  
13  
WATCH TIMER  
OVERVIEW  
Watch timer functions include real-time and watch-time measurement and interval timing for the system clock.  
To start watch timer operation, set bit1 and bit 6 of the watch timer mode register, WTCON.1and 6, to “1”. After the  
watch timer starts and elapses a time, the watch timer interrupt is automatically set to “1”, and interrupt requests  
commence in 1.955 ms or 0.125, 0.25 and 0.5-second intervals.  
The watch timer can generate a steady 0.5 kHz, 1 kHz, 2 kHz, or 4 kHz signal to the BUZZER output. By setting  
WTCON.3 and WTCON.2 to “11b”, the watch timer will function in high-speed mode, generating an interrupt every  
1.955 ms. High-speed mode is useful for timing events for program debugging sequences.  
The watch timer supplies the clock frequency for the LCD controller (f  
the LCD controller does not operate.  
). Therefore, if the watch timer is disabled,  
LCD  
— Real-time and Watch-time measurement  
— Using a main system or subsystem clock source  
— Clock source generation for LCD controller  
— Buzzer output frequency generator  
— Timing tests in high-speed mode  
13-1  
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WATCH TIMER  
S3C8245/P8245/C8249/P8249  
WATCH TIMER CONTROL REGISTER (WTCON: R/W)  
FBH  
WTCON.7 WTCON.6 WTCON.5 WTCON.4 WTCON.3 WTCON.2 WTCON.1 WTCON.0  
nRESET  
"0"  
"0"  
"0"  
"0"  
"0"  
"0"  
"0"  
"0"  
Table 13-1. Watch Timer Control Register (WTCON): Set 1, Bank 1, FAH, R/W  
Bit Name  
Values  
Function  
Select (fxx/128) as the watch timer clock  
Select subsystem clock as watch timer clock  
Disable watch timer interrupt  
Address  
WTCON.7  
0
1
0
1
FAH  
WTCON.6  
Enable watch timer interrupt  
WTCON.5–.4  
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0.5 kHz buzzer (BUZ) signal output  
1 kHz buzzer (BUZ) signal output  
2 kHz buzzer (BUZ) signal output  
4 kHz buzzer (BUZ) signal output  
Set watch timer interrupt to 0.5 s.  
Set watch timer interrupt to 0.25 s.  
Set watch timer interrupt to 0.125 s.  
Set watch timer interrupt to 1.955 ms.  
Disable watch timer, clear frequency dividing circuits  
Enable watch timer  
WTCON.3–.2  
WTCON.1  
WTCON.0  
0
1
0
1
Interrupt is not pending, clear pending bit when write  
Interrupt is pending  
NOTE: Watch timer clock frequency (fw) is assumed to be 32.768 kHz.  
13-2  
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S3C8245/P8245/C8249/P8249  
WATCH TIMER  
WATCH TIMER CIRCUIT DIAGRAM  
BUZZER Output  
WTCON.6  
WTCON.5  
WTCON.4  
MUX  
WTINT  
f
W/64 (0.5 kHz)  
W/32 (1 kHz)  
W/16 (2 kHz)  
W/8 (4 kHz)  
WTCON.3  
WTCON.2  
f
f
f
Enable/Disable  
Selector  
Circuit  
WTCON.1  
WTCON.0  
f
W
/26  
fW  
/212  
/213  
/214  
Frequency  
Dividing  
Circuit  
f
W
Clock  
WTCON.7  
fW  
Selector  
fVLD (4096 HZ)  
fBOOSTER (4096 HZ)  
f
W
1 Hz  
32.768 kHz  
fLCD (512 HZ)  
fxt  
fxx/128  
fxx = Main System Clock (4.19 MHz)  
fxt = Subsystem Clock (32.768 kHz)  
fw = Watch timer  
Figure 13-1. Watch Timer Circuit Diagram  
13-3  
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WATCH TIMER  
S3C8245/P8245/C8249/P8249  
NOTES  
13-4  
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S3C8245/P8245/C8249/P8249  
LCD CONTROLLER/DRIVER  
14  
LCD CONTROLLER/DRIVER  
OVERVIEW  
The S3C8245/C8249 micro-controller can directly drive an up-to-16-digit (32-segment) LCD panel. The LCD module  
has the following components:  
— LCD controller/driver  
— Display RAM (00H–0FH) for storing display data in page 4  
— 32 segment output pins (SEG0–SEG31)  
— Four common output pins (COM0–COM3)  
— Three LCD operating power supply pins (V  
V
)
LC0– LC2  
— LCD bias by voltage booster  
— LCD bias by voltage dividing resistors  
Bit settings in the LCD mode register, LMOD, determine the LCD frame frequency, duty and bias, and the segment  
pins used for display output. When a subsystem clock is selected as the LCD clock source, the LCD display is  
enabled even during stop and idle modes.  
The LCD control register LCON turns the LCD display on and off and switches current to the charge-pump circuits for  
the display. LCD data stored in the display RAM locations are transferred to the segment signal pins automatically  
without program control.  
CA-CB  
2
VLC0-VLC2  
LCD  
3
Controller/  
Driver  
8
COM0-COM3  
SEG0-SEG31  
4
32  
Figure 14-1. LCD Function Diagram  
14-1  
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LCD CONTROLLER/DRIVER  
LCD CIRCUIT DIAGRAM  
S3C8245/P8245/C8249/P8249  
OFH.7  
8
8
OFH.6  
OFH.5  
OFH.4  
SEG31  
SEG30  
SEG29  
SEG28  
SEG27  
SEG26  
MUX  
MUX  
MUX  
05H.1  
05H.0  
04H.7  
04H.6  
Segment  
Driver  
SEG16  
SEG15  
SEG14  
SEG13  
SEG12  
SEG11  
00H.3  
00H.2  
00H.1  
00H.0  
8
8
8
fLCD  
SEG0  
COM3  
COM2  
COM1  
COM0  
Timing  
Controller  
COM  
Control  
LMOD  
LCON  
VLC0  
VLC1  
VLC2  
CA  
LCD  
Voltage  
Control  
CB  
NOTE:  
fLCD = fW/26, fW/27, fW/28, fW/29  
Figure 14-2. LCD Circuit Diagram  
14-2  
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S3C8245/P8245/C8249/P8249  
LCD RAM ADDRESS AREA  
LCD CONTROLLER/DRIVER  
RAM addresses 00H - 0FH of page 4, or page 2, according to ROM size, are used as LCD data memory. When the  
bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off.  
Display RAM data are sent out through segment pins SEG0–SEG31 using a direct memory access (DMA) method  
that is synchronized with the fLCD signal. RAM addresses in this location that are not used for LCD display can be  
allocated to general-purpose use.  
00H  
BIT.3  
BIT.7  
BIT.2  
BIT.6  
BIT.1  
BIT.5  
BIT.0  
BIT.4  
SEG0  
SEG1  
08H  
09H  
0AH  
0BH  
0CH  
0DH  
0EH  
0FH  
BIT.3  
BIT.7  
BIT.3  
BIT.7  
BIT.3  
BIT.7  
BIT.3  
BIT.7  
BIT.3  
BIT.7  
BIT.3  
BIT.7  
BIT.3  
BIT.7  
BIT.3  
BIT.7  
BIT.2  
BIT.6  
BIT.2  
BIT.6  
BIT.2  
BIT.6  
BIT.2  
BIT.6  
BIT.2  
BIT.6  
BIT.2  
BIT.6  
BIT.2  
BIT.6  
BIT.2  
BIT.6  
BIT.1  
BIT.5  
BIT.1  
BIT.5  
BIT.1  
BIT.5  
BIT.1  
BIT.5  
BIT.1  
BIT.5  
BIT.1  
BIT.5  
BIT.1  
BIT.5  
BIT.1  
BIT.5  
BIT.0  
BIT.4  
BIT.0  
BIT.4  
BIT.0  
BIT.4  
BIT.0  
BIT.4  
BIT.0  
BIT.4  
BIT.0  
BIT.4  
BIT.0  
BIT.4  
BIT.0  
BIT.4  
SEG16  
SEG17  
SEG18  
SEG19  
SEG20  
SEG21  
SEG22  
SEG23  
SEG24  
SEG25  
SEG26  
SEG27  
SEG28  
SEG29  
SEG30  
SEG31  
COM3  
COM2  
COM1  
COM0  
Figure 14-3. LCD Display Data RAM Organization  
14-3  
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LCD CONTROLLER/DRIVER  
S3C8245/P8245/C8249/P8249  
LCD CONTROL REGISTER (LCON), D0H  
Table 14-1. LCD Control Register (LCON) Organization  
Description  
LCON Bit  
Setting  
LCON.7  
0
1
0
1
0
1
0
1
0
0
1
0
1
0
P5.4–P5.7 I/O is selected  
SEG28–SEG31 is selected, P5.4–P5.7 I/O is disabled  
P5.0–P5.3 I/O is selected  
LCON.6  
LCON.5  
LCON.4  
SEG24–SEG27 is selected, P5.0–P5.3 I/O is disabled  
P4.4–P4.7 I/O is selected  
SEG20–SEG23 is selected, P4.4–P4.7 I/O is disabled  
P4.0–P4.3 I/O is selected  
SEG16–SEG19 is selected, P4.0–P4.3 I/O is disabled  
This bit is used for internal testing only; always logic zero.  
Enable LCD initial circuit (internal bias voltage).  
LCON.3  
LCON.2  
Disable LCD initial circuit for external LCD dividing resistors(external bias voltage).  
Stop voltage booster(clock stop and cut off current charge path)  
Run voltage booster(clock run and turn on current charge path)  
LCON.1  
LCON.0  
LCD output low; turn display off, COM and SEG output Low  
Cut off voltage booster (Booster clock disable).  
1
COM and SEG output is in display mode; turn display on.  
Table 14-2. Relationship of LCON.0 and LMOD.3 Bit Settings  
LCON.0  
LMOD.3  
COM0–COM3  
Output low; LCD display off  
SEG0–SEG31  
Output low; LCD display off  
0
1
x
0
1
Output low; LCD display off  
Output low; LCD display off  
COM output corresponds to display mode  
SEG output corresponds to display mode  
NOTE: "X" means don’t care.  
14-4  
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S3C8245/P8245/C8249/P8249  
LCD CONTROLLER/DRIVER  
LCD MODE REGISTER (LMOD)  
The LCD mode control register LMOD is mapped to RAM addresses D1H.  
LMOD controls these LCD functions:  
— Duty and bias selection (LMOD.3–LMOD.0)  
— LCDCK clock frequency selection (LMOD.5–LMOD.4)  
The LCD clock signal, LCDCK, determines the frequency of COM signal scanning of each segment output. This is  
also referred to as the 'frame frequency.' Since LCDCK is generated by dividing the watch timer clock (fw), the watch  
timer must be enabled when the LCD display is turned on. Reset clears the LMOD register values to logic zero. This  
produces the following LCD control settings:  
— Display is turned off  
9
— LCDCK frequency is the watch timer clock (fw)/2 = 64 Hz  
The LCD display can continue to operate during idle and stop modes if a subsystem clock is used as the watch  
timer source. The LCD output voltage level is always 3 V, supplied by the voltage booster.  
Table 14-3. LCD Clock Signal (LCDCK) Frame Frequency  
LCDCK Frequency  
Static  
1/2 Duty  
1/3 Duty  
1/4 Duty  
9
64  
32  
21  
16  
fw/2 (64 Hz)  
8
128  
256  
512  
64  
43  
85  
32  
64  
fw/2 (128 Hz)  
7
128  
256  
fw/2 (256 Hz)  
6
171  
128  
fw/2 (512 Hz)  
NOTE: ‘fw’ is the watch timer clock frequency of 32.768 kHz.  
14-5  
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LCD CONTROLLER/DRIVER  
S3C8245/P8245/C8249/P8249  
Table 14-4. LCD Mode Control Register (LMOD) Organization, D1H  
LMOD.7  
LMOD.6  
Always logic zero.  
Always logic zero.  
LMOD.5  
LMOD.4  
LCD Clock (LCDCK) Frequency  
9
0
0
1
0
1
32.768 kHz watch timer clock (fw)/2 = 64 Hz  
8
0
1
1
32.768 kHz watch timer clock (fw)/2 = 128 Hz  
7
32.768 kHz watch timer clock (fw)/2 = 256 Hz  
6
32.768 kHz watch timer clock (fw)/2 = 512 Hz  
LMOD.3  
LMOD.2  
LMOD.1  
LMOD.0  
Duty and Bias Selection for LCD Display  
0
1
1
1
1
1
x
0
0
0
0
1
x
0
0
1
1
x
x
0
1
1
0
x
LCD display off (COM and SEG output Low)  
1/4 duty, 1/3 bias  
1/3 duty, 1/3 bias  
1/3 duty, 1/2 bias  
1/2 duty, 1/2 bias  
Static  
NOTE: ‘x’ means don’t care.  
Table 14-5. Maximum Number of Display Digits per Duty Cycle  
LCD Duty  
Static  
1/2  
LCD Bias  
Static  
1/2  
COM Output Pins  
COM0  
Maximum Seg Display  
32  
COM0–COM1  
COM0–COM2  
COM0–COM2  
COM0–COM3  
32 x 2  
32 x 3  
32 x 3  
32 x 4  
1/3  
1/2  
1/3  
1/3  
1/4  
1/3  
14-6  
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S3C8245/P8245/C8249/P8249  
LCD DRIVE VOLTAGE  
LCD CONTROLLER/DRIVER  
The LCD display is turned on only when the voltage difference between the common and segment signals is greater  
than V . The LCD display is turned off when the difference between the common and segment signal voltages is  
LCD  
less than V  
The turn-on voltage, + V  
or - V  
, is generated only when both signals are the selected signals  
LCD.  
LCD  
LCD  
of the bias. Table 14-7 shows LCD drive voltages for static mode, 1/2 bias, and 1/3 bias.  
Table 14-6. LCD Drive Voltage Values  
LCD Power Supply  
Static Mode  
1/2 Bias  
1/3 Bias  
V
V
V
V
LC2  
LCD  
LCD  
LCD  
V
–
–
V
2/3 V  
LC1  
LCD  
LCD  
V
1/2 V  
1/3 V  
LC0  
LCD  
LCD  
V
0 V  
0 V  
0 V  
ss  
NOTE: The LCD panel display may deteriorate if a DC voltage is applied that lies between the common and segment  
signal voltage. Therefore, always drive the LCD panel with AC voltage.  
LCD SEG/SEG SIGNALS  
The 32 LCD segment signal pins are connected to corresponding display RAM locations at 00H–0FH.  
Bits 0-3 (and 4-7) of the display RAM are synchronized with the common signal output pins COM0, COM1, COM2,  
and COM3.  
When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin. When  
the display bit is "0", a 'no-select' signal is sent to the corresponding segment pin. Each bias has select and no-  
select signals.  
Select  
Non-Select  
FR  
1 Frame  
VLC2  
VSS  
COM  
VLC2  
VSS  
SEG  
VLC2  
VSS  
COM-SEG  
-VLC2  
Figure 14-4. Select/No-Select Bias Signals in Static Display Mode  
14-7  
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LCD CONTROLLER/DRIVER  
S3C8245/P8245/C8249/P8249  
Select  
Non-Select  
FR  
1 Frame  
VLC1, 2  
VLC 0  
Vss  
COM  
SEG  
VLC1, 2  
VLC 0  
Vss  
VLC1, 2  
VLC 0  
Vss  
COM-SEG  
-VLC 0  
-VLC1, 2  
Figure 14-5. Select/No-Select Bias Signals in 1/2 Duty, 1/2 Bias Display Mode  
Select  
Non-Select  
FR  
1 Frame  
VLC 2  
VSS  
COM  
VLC 2  
VSS  
SEG  
VLC 2  
VSS  
COM-SEG  
-VLC 2  
Figure 14-6. Select/No-Select Bias Signals in 1/3 Duty, 1/3 Bias Display Mode  
14-8  
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S3C8245/P8245/C8249/P8249  
LCD CONTROLLER/DRIVER  
0
1
0
1
SEG0.0 x C0  
SEG1.0 x C0  
SEG2.1 x C1  
1 Frame  
FR  
VLC1, 2  
VLC0  
VSS  
COM0  
VLC1, 2  
VLC0  
VSS  
COM1  
SEG0  
SEG1  
VLC1, 2  
VLC0  
VSS  
VLC1, 2  
VLC0  
VSS  
SEG3.1 x C1  
VLC1, 2  
VLC0  
COM0  
-SEG0  
VSS  
-VLC0  
-VLC1, 2  
VLC1, 2  
VLC0  
COM0  
-SEG1  
VSS  
-VLC0  
-VLC1, 2  
VLC1, 2  
VLC0  
COM1  
-SEG0  
VSS  
-VLC0  
-VLC1, 2  
VLC1, 2  
VLC0  
COM1  
-SEG1  
VSS  
-VLC0  
-VLC1, 2  
NOTE:  
VLC1 = VLC0  
Figure 14-7. LCD Signal and Wave Forms Example in 1/2 Duty, 1/2 Bias Display Mode  
14-9  
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LCD CONTROLLER/DRIVER  
S3C8245/P8245/C8249/P8249  
0
1
2
0
1
2
SEG2.0 x C0  
SEG2.1 x C1  
SEG0.2x C2
1 Frame  
FR  
VLC2  
VLC1  
COM0  
VLC0  
VSS  
VLC2  
VLC1  
COM1  
COM2  
VLC0  
VSS  
VLC2  
VLC1  
VLC0  
VSS  
VLC2  
VLC1  
VLC0  
VSS  
SEG0  
SEG1  
SEG1.6 x C2  
VLC2  
VLC1  
VLC0  
VSS  
VLC2  
VLC1  
VLC0  
VSS  
-VLC0  
-VLC1  
-VLC2  
COM0  
-SEG0  
VLC2  
VLC1  
VLC0  
VSS  
-VLC0  
-VLC1  
-VLC2  
COM0  
-SEG1  
VLC2  
VLC1  
VLC0  
VSS  
-VLC0  
-VLC1  
-VLC2  
COM1  
-SEG0  
VLC2  
VLC1  
VLC0  
VSS  
-VLC0  
-VLC1  
-VLC2  
COM1  
-SEG1  
Figure 14-8. LCD Signals and Wave Forms Example in 1/3 Duty, 1/3 Bias Display Mode  
14-10  
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S3C8245/P8245/C8249/P8249  
LCD CONTROLLER/DRIVER  
0
1
2
3
0
1
2
3
SEG1.4 x C0  
SEG0.1 x C1  
SEG0.3 x C3  
FR  
1 Frame  
VLC2  
VLC1  
VLC0  
VSS  
COM0  
VLC2  
VLC1  
VLC0  
VSS  
COM1  
COM2  
COM3  
SEG0  
SEG1  
VLC2  
VLC1  
VLC0  
VSS  
VLC2  
VLC1  
VLC0  
VSS  
SEG1.7 x C3  
VLC2  
VLC1  
VLC0  
VSS  
VLC2  
VLC1  
VLC0  
VSS  
VLC2  
VLC1  
VLC0  
VSS  
-VLC0  
-VLC1  
-VLC2  
COM0  
-SEG0  
VLC2  
VLC1  
VLC0  
VSS  
-VLC0  
-VLC1  
-VLC2  
COM0  
-SEG1  
VLC2  
VLC1  
VLC0  
VSS  
-VLC0  
-VLC1  
-VLC2  
COM1  
-SEG0  
VLC2  
VLC1  
VLC0  
VSS  
-VLC0  
-VLC1  
-VLC2  
COM1  
-SEG1  
Figure 14-9. LCD Signals and Wave Forms Example in 1/4 Duty, 1/3 Bias Display Mode  
14-11  
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LCD CONTROLLER/DRIVER  
S3C8245/P8245/C8249/P8249  
LCD VOLTAGE DRIVING METHOD  
By Voltage Booster  
For run the voltage booster  
— Make enable the watch timer for f  
booster  
— Set LCON.2 to "0" and LCON.1 to "1" for make enable voltage booster  
— Recommendable capacitance value is 0.1 uF (CAB, C0, C1, C2)  
By Voltage Dividing Resistors (Externally)  
For make external voltage dividing resistors  
— Make enable the watch timer  
— Set LCON.2 to "1" and LCON.1 to "0" for make disable voltage booster  
— Make floating the CA and CB pin  
— Recommendable R = 100 kW  
Static and 1/3 Bias (VLCD = 3 V at VDD = 5 V)  
1/2 Bias (VLCD = 3.3 V at VDD = 5 V)  
VDD  
2 x R  
VLC2  
VDD  
VLC2  
VLC1  
VLC0  
VSS  
R
R
VLC1  
R
R
R
VLC0  
R
VSS  
Static and 1/3 Bias (VLCD = 5 V at VDD = 5 V)  
VDD  
VLC2  
R
VLC1  
R
VLC0  
R
NOTE:  
3.0 V  
£
VLCD  
£
5.5 V  
VSS  
Figure 14-10. Voltage Dividing Resistor Circuit Diagram  
14-12  
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S3C8245/P8245/C8249/P8249  
A/D CONVERTER  
15  
10-BIT ANALOG-TO-DIGITAL CONVERTER  
OVERVIEW  
The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one  
of the eight input channels to equivalent 10-bit digital values. The analog input level must lie between the AV  
and  
REF  
AV values. The A/D converter has the following components:  
SS  
— Analog comparator with successive approximation logic  
— D/A converter logic (resistor string type)  
— ADC control register (ADCON)  
— Eight multiplexed analog data input pins (ADC0–ADC7)  
— 10-bit A/D conversion data output register (ADDATAH/L)  
— 10-bit digital input port (Alternately, I/O port.)  
— AV  
and AV pins, AV is internally connected to V  
SS SS SS  
REF  
FUNCTION DESCRIPTION  
To initiate an analog-to-digital conversion procedure, at the first you must set ADCEN signal for ADC input enable at  
port 2, the pin set with 1 can be used for ADC analog input. And you write the channel selection data in the A/D  
converter control register ADCON.4–.7 to select one of the eight analog input pins (ADC0–7) and set the conversion  
start or enable bit, ADCON.0. The read-write ADCON register is located in set 1, bank 0, at address F3H. The pins  
witch are not used for ADC can be used for normal I/O.  
During a normal conversion, ADC logic initially sets the successive approximation register to 200H (the approximate  
half-way point of an 10-bit register). This register is then updated automatically during each conversion step. The  
successive approximation block performs 10-bit conversions for one input channel at a time. You can dynamically  
select different channels by manipulating the channel selection bit value (ADCON.6–4) in the ADCON register. To  
start the A/D conversion, you should set the enable bit, ADCON.0. When a conversion is completed, ADCON.3, the  
end-of-conversion(EOC) bit is automatically set to 1 and the result is dumped into the ADDATAH/L register where it  
can be read. The A/D converter then enters an idle state. Remember to read the contents of ADDATAH/L before  
another conversion starts. Otherwise, the previous result will be overwritten by the next conversion result.  
NOTE  
Because the A/D converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog level at  
the ADC0–ADC7 input pins during a conversion procedure be kept to an absolute minimum. Any change in the input  
level, perhaps due to noise, will invalidate the result. If the chip enters to STOP or IDLE mode in conversion process,  
there will be a leakage current path in A/D block. You must use STOP or IDLE mode after ADC operation is finished.  
15-1  
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A/D CONVERTER  
S3C8245/P8245/C8249/P8249  
CONVERSION TIMING  
The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D  
conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for  
conversion clock with an 8 MHz fxx clock frequency, one clock cycle is 1 us. Each bit conversion requires 4 clocks,  
the conversion rate is calculated as follows:  
4 clocks/bit ´ 10 bits + set-up time = 50 clocks, 50 clock ´ 1us = 50 ms at 1 MHz  
A/D CONVERTER CONTROL REGISTER (ADCON)  
The A/D converter control register, ADCON, is located at address F7H in set 1, bank 0. It has three functions:  
— Analog input pin selection ( bits 4, 5, and 6 )  
— End-of-conversion status detection ( bit 3)  
— A/D operation start or enable ( bit 0 )  
After a reset, the start bit is turned off. You can select only one analog input channel at a time. Other analog input  
pins (ADC0–ADC7) can be selected dynamically by manipulating the ADCON.4–6 bits. And the pins not used for  
analog input can be used for normal I/O function.  
A/D Converter Control Register (ADCON)  
F7H, Set 1, Bank 1, R/W (EOC bit is read-only)  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Always logic zero  
Start or enable bit:  
0 = Disable operation  
1 = Start operation  
A/D input pin selection bits:  
Clock Selection bit:  
0 0 = fxx/16  
0 1 = fxx/8  
1 0 = fxx/4  
1 1 = fxx/1  
0 0 0 = ADC0  
0 0 1 = ADC1  
0 1 0 = ADC2  
0 1 1 = ADC3  
1 0 0 = ADC4  
1 0 1 = ADC5  
1 1 0 = ADC6  
1 1 1 = ADC7  
End-of-conversion bit:  
0 = Conversion not complete  
1 = Conversion complete  
Figure 15-1. A/D Converter Control Register (ADCON)  
15-2  
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S3C8245/P8245/C8249/P8249  
A/D CONVERTER  
A/D Converter Data Register, High Byte (ADDATAH)  
F8H, Set 1, Bank 1, Read Only  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
LSB  
A/D Converter Data Register, Low Byte (ADDATAL)  
F9H, Set 1, Bank 1, Read Only  
MSB  
.1  
.0  
Figure 15-2. A/D Converter Data Register (ADDATAH/L)  
INTERNAL REFERENCE VOLTAGE LEVELS  
In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level  
must remain within the range AV to AV (usually, AV = V ).  
SS  
REF  
REF  
DD  
Different reference voltage levels are generated internally along the resistor tree during the analog conversion process  
for each conversion step. The reference voltage level for the first conversion bit is always 1/2 AV  
.
REF  
15-3  
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A/D CONVERTER  
S3C8245/P8245/C8249/P8249  
BLOCK DIAGRAM  
ADCON.2-.1  
ADCON.4-.6  
(Select one input pin of the assigned pins)  
To ADCON.3  
(EOC Flag)  
Clock  
Selector  
ADCON.0  
(AD/C Enable)  
M
Analog  
Comparator  
Successive  
Approximation  
Logic & Register  
-
Input Pins  
U
X
ADC0-ADC7  
(P2.0-P2.7)  
.
+
.
.
ADCON.0  
(AD/C Enable)  
Upper 8-bit is loaded to  
A/D Conversion  
Data Register  
ADCEN.0-.7  
(Assign Pins to ADC Input)  
Conversion  
Result (ADDATAH/L  
F8, F9H, Set 1, Bank 1)  
AVREF  
AVSS  
10-bit D/A  
Converter  
Figure 15-3. A/D Converter Functional Block Diagram  
15-4  
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S3C8245/P8245/C8249/P8249  
A/D CONVERTER  
VDD  
Reference  
Voltage  
Input  
R
AVREF  
+
-
C
10 pF  
103  
C
VDD  
Analog  
Input Pin  
ADC0-ADC7  
101  
S3C8245/C8249  
VSS  
NOTE: The symbol "R" signifies an offset resistor with a value of from 50  
W
to 100W.  
If this resistor is omitted, the absolute accuracy will be maximum of 3 LSBs.  
Figure 15-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy  
15-5  
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A/D CONVERTER  
S3C8245/P8245/C8249/P8249  
NOTES  
15-6  
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S3C8245/P8245/C8249/P8249  
SERIAL I/O INTERFACE  
16  
SERIAL I/O INTERFACE  
OVERVIEW  
Serial I/O module, SIO can interface with various types of external device that require serial data transfer. The  
components of each SIO function block are:  
— 8-bit control register (SIOCON)  
— Clock selector logic  
— 8-bit data buffer (SIODATA)  
— 8-bit prescaler (SIOPS)  
— 3-bit serial clock counter  
— Serial data I/O pins (SI, SO)  
— External clock input/output pins (SCK)  
The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control  
register settings. To ensure flexible data transmission rates, you can select an internal or external clock source.  
PROGRAMMING PROCEDURE  
To program the SIO modules, follow these basic steps:  
1. Configure the I/O pins at port (SO, SCK, SI) by loading the appropriate value to the P1CONH register if  
necessary.  
2. Load an 8-bit value to the SIOCON control register to properly configure the serial I/O module. In this operation,  
SIOCON.2 must be set to "1" to enable the data shifter.  
3. For interrupt generation, set the serial I/O interrupt enable bit (SIOCON.1) to "1".  
4. When you transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, the shift operation  
starts.  
5. When the shift operation (transmit/receive) is completed, the SIO pending bit (SIOCON.0) is set to "1" and an  
SIO interrupt request is generated.  
16-1  
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SERIAL I/O INTERFACE  
S3C8245/P8245/C8249/P8249  
SIO CONTROL REGISTER (SIOCON)  
The control register for serial I/O interface module, SIOCON, is located at F0H in set 1, bank 0. It has the control  
settings for SIO module.  
— Clock source selection (internal or external) for shift clock  
— Interrupt enable  
— Edge selection for shift operation  
— Clear 3-bit counter and start shift operation  
— Shift operation (transmit) enable  
— Mode selection (transmit/receive or receive-only)  
— Data direction selection (MSB first or LSB first)  
A reset clears the SIOCON value to "00H". This configures the corresponding module with an internal clock source  
at the SCK, selects receive-only operating mode, and clears the 3-bit counter. The data shift operation and the  
interrupt are disabled. The selected data direction is MSB-first.  
Serial I/O Module Control Registers (SIOCON)  
F0H, Set 1, Bank 0, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
SIO interrupt pending bit  
0 = No interrupt pending  
0 = Clear pending condition  
(when write)  
SIO shift clock selection bit  
0 = Internal clock (P.S Clock)  
1 = External clock (SCK)  
1 = Interrupt is pending  
Data direction control bit  
0 = MSB-first mode  
1 = LSB-first mode  
SIO interrupt enable bit  
0 = Disable SIO interrupt  
1 = Enable SIO interrupt  
SIO mode selection bit  
0 = Receive only mode  
1 = Transmit/receive mode  
SIO shift operation enable bit  
0 = Disable shifter and clock counter  
1 = Enable shifter and clock counter  
Shift clock edge selection bit  
0 = TX at falling edeges, Rx at rising edges  
1 = TX at rising edeges, Rx at falling edges  
SIO counter clear and shift start bit  
0 = No action  
1 = Clear 3-bit counter and start shifting  
Figure 16-1. Serial I/O Module Control Registers (SIOCON)  
16-2  
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S3C8245/P8245/C8249/P8249  
SERIAL I/O INTERFACE  
SIO PRE-SCALER REGISTER (SIOPS)  
The control register for serial I/O interface module, SIOPS, is located at F2H in set 1, bank 0.  
The value stored in the SIO pre-scale registers, SIOPS, lets you determine the SIO clock rate (baud rate) as follows:  
Baud rate = Input clock (fxx/4)/(Pre-scaler value + 1), or SCK input clock, where the input clock is fxx/4  
SIO Pre-scaler Register (SIOPS)  
F2H, Set 1, Bank 0 R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Baud rate = (fXX /4)/(SIOPS + 1)  
Figure 16-2. SIO Pre-scale Registers (SIOPS)  
BLOCK DIAGRAM  
SIO INT  
3-Bit Counter  
SIOCON.0  
Pending  
IRQ4  
Clear  
CLK  
SIOCON.1  
(Interrupt Enable)  
SIOCON.3  
SIOCON.7  
SIOCON.4  
SIOCON.2  
(Edge Select)  
(Shift Enable)  
SIOCON.5  
M
U
X
SCK  
(Mode Select)  
SIOPS (F2H, bank 0)  
8-bit P.S. 1/2  
CLK  
8-Bit SIO Shift Buffer  
SO  
(SIODATA, F1H, bank 0)  
fxx /2  
SI  
SIOCON.6  
(LSB/MSB First  
Mode Select)  
Prescaler Value = 1/(SIOPS +1)  
8
Data Bus  
Figure 16-3. SIO Functional Block Diagram  
16-3  
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SERIAL I/O INTERFACE  
S3C8245/P8245/C8249/P8249  
SERIAL I/O TIMING DIAGRAM  
SCK  
SI  
DI7  
DI6  
DI5  
DI4  
DI3  
DI2  
DI1  
DI0  
SO  
DO7  
DO6  
DO5  
DO4  
DO3  
DO2  
DO1  
DO0  
Transmit  
Complete  
IRQS  
Set SIOCON.3  
Figure 16-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)  
SCK  
DI7  
DI6  
DI5  
DI4  
DI3  
DI2  
DI1  
DI0  
SI  
SO  
DO7  
DO6  
DO5  
DO4  
DO3  
DO2  
DO1  
DO0  
Transmit  
Complete  
IRQS  
Set SIOCON.3  
Figure 16-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)  
16-4  
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S3C8245/P8245/C8249/P8249  
VOLTAGE BOOSTER  
17  
VOLTAGE BOOSTER  
OVERVIEW  
This voltage booster works for the power control of LCD : generates 3 ´ VR(VLC2), 2 ´ VR(VLC1), 1 ´ VR(VLC0). This  
voltage booster allows low voltage operation of LCD display with high quality. This voltage booster circuit provides  
constant LCD contrast level even though battery power supply was lowered.  
This voltage booster include voltage regulator, and voltage charge/pump circuit.  
FUNCTION DESCRIPTION  
The voltage booster has built for driving the LCD. The voltage booster provides the capability of directly connecting  
an LCD panel to the MCU without having to separately generate and supply the higher voltages required by the LCD  
panel. The voltage booster operates on an internally generated and regulated LCD system voltage and generates a  
doubled and a tripled voltage levels to supply the LCD drive circuit. External capacitor are required to complete the  
power supply circuits.  
The V power line is regulated to get the V (VR) level, which become a base level for voltage boosting. Then a  
DD  
LC0  
doubled and a tripled voltage will be made by capacitor charge and pump circuit.  
17-1  
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VOLTAGE BOOSTER  
S3C8245/P8245/C8249/P8249  
BLOCK DIAGRAM  
CAB  
CAB  
VDD  
VLC0 (VR  
)
VLC1 (2 x V  
C1  
R
)
VLC2 (3 x V  
C2  
R)  
Voltage  
Regulator  
Clock  
C0  
LCON.1  
LCON.0  
VSS  
LCON.2  
Figure 17-1. Voltage Booster Block Diagram  
COM0-3  
COM0-3  
SEG0-SEG31  
LCD  
Drive  
LCD  
Drive  
SEG0-SEG31  
VLC0  
VLC0  
VLC1  
VLC2  
VLC1  
VLC2  
CA  
CB  
CA  
CB  
CAB  
CAB  
C1  
Voltage  
Booster  
Voltage  
Booster  
VLC2  
VLC2  
C2  
C1  
VLC1  
VLC1  
VLC0  
VLC0  
VLC0  
Voltage  
Regulator  
(1.5 V)  
Voltage  
Regulator  
(1.5 V)  
C0  
C0  
VLC0  
1/3 Bias  
1/2 Bias and Static  
Figure 17-2. Pin Connection Example  
17-2  
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S3C8245/P8245/C8249/P8249  
VOLTAGE LEVEL DETECTOR  
18  
VOLTAGE LEVEL DETECTOR  
OVERVIEW  
The S3C8245/C8249 micro-controller has a built-in VLD (Voltage Level Detector) circuit which allows detection of  
power voltage drop or external input level through software. Turning the VLD operation on and off can be controlled by  
software. Because the IC consumes a large amount of current during VLD operation. It is recommended that the  
VLD operation should be kept OFF unless it is necessary. Also the VLD criteria voltage can be set by the software.  
The criteria voltage can be set by matching to one of the 4 kinds of voltage below that can be used.  
2.2 V, 2.4 V, 3.0 V or 4.0 V (V reference voltage), or external input level (External reference voltage)  
DD  
The V block works only when VLDCON.2 is set. If V level is lower than the reference voltage selected with  
LD  
DD  
VLDCON.1–.0, VLDCON.3 will be set. If V level is higher, VLDCON.3 will be cleared. When users need to  
DD  
minimize current consumption, do not operate the VLD block.  
VDD Pin  
Voltage  
fVLD  
Level  
Detector  
VLDCON.3  
VLD Out  
VLDCON.4  
MUX  
VLDCON.2  
VLD Run  
ExtRef/P2.7  
Voltage  
Level  
Setting  
P2CONH.7-.6  
VLDCON.1  
VLDCON.0  
ExtRef Input  
Enable  
Set the Level  
Figure 18-1. Block Diagram for Voltage Level Detect  
18-1  
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VOLTAGE LEVEL DETECTOR  
S3C8245/P8245/C8249/P8249  
VOLTAGE LEVEL DETECTOR CONTROL REGISTER (VLDCON)  
The bit 2 of VLDCON controls to run or disable the operation of Voltage level detect. Basically this V  
is set as  
VLD  
2.2 V by system reset and it can be changed in 4 kinds voltages by selecting Voltage Level Detect Control register  
(VLDCON). When you write 2 bit data value to VLDCON, an established resistor string is selected and the V is  
VLD  
fixed in accordance with this resistor. Table 18-1 shows specific V  
of 4 levels.  
VLD  
Resistor String  
Voltage Level Detect Control  
F6H, Set 1, Bank 1, R/W, Reset : 00H  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Not use  
RVLD  
VIN  
+
Comparator  
M
VLDOUT  
VREF  
Bias  
VBAT  
ExtRef  
BANDGAP  
VLD Enable/Disable  
P2CONH.7-.6  
NOTE: The reset value of VLDCON is #00H.  
Figure 18-2. Voltage Level Detect Circuit and Control Register  
Table 18-1. VLDCON Value and Detection Level  
VLDCON .1–.0  
V
VLD  
0 0  
0 1  
1 0  
1 1  
2.2 V  
2.4 V  
3.0 V  
4.0 V  
18-2  
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S3C8245/P8245/C8249/P8249  
ELECTRICAL DATA  
19  
ELECTRICAL DATA  
OVERVIEW  
In this chapter, S3C8245/C8249 electrical characteristics are presented in tables and graphs.  
The information is arranged in the following order:  
— Absolute maximum ratings  
— Input/output capacitance  
— D.C. electrical characteristics  
— A.C. electrical characteristics  
— Oscillation characteristics  
— Oscillation stabilization time  
— Data retention supply voltage in stop mode  
— Serial I/O timing characteristics  
— A/D converter electrical characteristics  
19-1  
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ELECTRICAL DATA  
S3C8245/P8245/C8249/P8249  
Table 19-1. Absolute Maximum Ratings  
°
(T = 25 C)  
A
Parameter  
Symbol  
Conditions  
Rating  
Unit  
Supply voltage  
Input voltage  
V
– 0.3 to +6.5  
V
DD  
V
– 0.3 to V + 0.3  
I
DD  
Output voltage  
Output current high  
V
– 0.3 to V + 0.3  
O
DD  
I
One I/O pin active  
– 18  
mA  
OH  
All I/O pins active  
One I/O pin active  
– 60  
+ 30  
Output current low  
I
OL  
Total pin current for port  
+ 100  
°
Operating temperature  
Storage temperature  
T
– 40 to + 85  
C
A
T
– 65 to + 150  
STG  
Table 19-2. D.C. Electrical Characteristics  
°
°
(T = -25 C to + 85 C, V  
= 1.8 V to 5.5 V)  
DD  
A
Parameter  
Symbol  
Conditions  
= 10 MHz  
CPU  
Min  
Typ  
Max  
Unit  
Operating voltage  
V
f
2.7  
–
5.5  
5.5  
V
DD  
f
1.8  
–
–
–
–
= 3 MHz  
CPU  
Input high voltage  
Input low voltage  
V
All input pins except V  
0.8 V  
V
IH1  
IH2  
IL2  
DD  
DD  
V
X
XT  
V
-0.1  
DD  
,
IH2  
IN  
IN  
V
All input pins except V  
XT  
–
0.2 V  
IL1  
DD  
V
X
0.1  
,
IL2  
IN  
IN  
19-2  
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S3C8245/P8245/C8249/P8249  
ELECTRICAL DATA  
Table 19-2. D.C. Electrical Characteristics (Continued)  
°
°
(T = -25 C to + 85 C, V = 1.8 V to 5.5 V)  
A
DD  
Parameter  
Symbol  
Conditions  
Min  
V –1.0  
DD  
Typ  
Max  
Unit  
Output high voltage  
V
V
= 5 V; I = -1 mA  
–
–
0.4  
3
V
OH  
DD  
OH  
All output pins  
= 5 V; I = 2 mA  
OL  
Output low voltage  
V
V
–
–
–
–
OL  
DD  
All output pins  
= V  
Input high leakage  
current  
I
V
uA  
LIH1  
IN  
DD  
All input pins except I  
LIH2  
I
V
= V  
X
XT  
IN  
20  
-3  
,
LIH2  
IN  
DD, IN  
Input low leakage  
current  
I
V
= 0 V  
–
–
LIL1  
IN  
All input pins except I  
LIL2  
I
V
= 0 V, X XT , nRESET  
-20  
3
,
IN  
LIL2  
IN  
IN  
Output high leakage  
current  
I
V
= V  
–
–
–
–
LOH  
OUT  
DD  
All I/O pins and output pins  
= 0 V  
Output low leakage  
current  
I
V
-3  
LOL  
OUT  
All I/O pins and output pins  
°
Oscillator feed back  
resistors  
R
300  
600  
1500  
kW  
V
= 5.0 V T = 25 C  
osc1  
A
DD  
X = V , X  
= 0 V  
IN  
DD OUT  
Pull-up resistor  
R
V
= 0 V; V = 5 V ±10 %  
25  
50  
100  
310  
1.15  
1.7  
L1  
IN  
DD  
°
Port 0,1,2,3,4,5 T = 25 C  
A
R
V
= 0 V; V = 5 V ±10%  
110  
0.9  
1.4  
210  
1.0  
L2  
IN  
DD  
°
T =25 C, nRESET only  
A
V
out voltage  
V
T = 25 °C, (1/3 bias mode)  
V
LC0  
LC0  
A
(Booster run mode)  
T = 25 °C, (1/2 bias mode)  
1.5  
–
A
V
out voltage  
V
T = 25 °C (1/2 and 1/3 bias 2V  
- 0.1  
2V  
3V  
+ 0.1  
LC1  
LC1  
A
LC0  
LC0  
(Booster run mode)  
mode)  
V
out voltage  
V
T = 25 °C (1/3 bias mode)  
3V  
- 0.1  
–
+ 0.1  
LC2  
LC2  
A
LC0  
LC0  
(Booster run mode)  
COM output  
voltage deviation  
V
V
= V = 3 V  
LC2  
–
± 60  
± 120  
mV  
DC  
DD  
(V  
-COMi)  
LCD  
IO = ± 15 mA (i = 0-3)  
= V = 3 V  
SEG output  
voltage deviation  
V
V
–
± 60  
± 120  
Ds  
DD  
LC2  
(V  
-SEGi)  
LCD  
IO = ± 15 mA (i = 0-31)  
19-3  
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ELECTRICAL DATA  
S3C8245/P8245/C8249/P8249  
NOTE: Low leakage current is absolute value.  
19-4  
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S3C8245/P8245/C8249/P8249  
ELECTRICAL DATA  
Table 19-2. D.C. Electrical Characteristics (Concluded)  
°
°
(T = -25 C to + 85 C, V = 1.8 V to 5.5 V)  
A
DD  
Parameter  
Symbol  
Conditions  
= 5 V ± 10 %  
Min  
Typ  
Max  
Unit  
(1)  
(2)  
V
–
12  
25  
mA  
Supply current  
I
DD  
DD1  
10 MHz crystal oscillator  
3 MHz crystal oscillator  
4
3
10  
8
V
= 3 V ± 10 %  
DD  
10 MHz crystal oscillator  
3 MHz crystal oscillator  
1
3
5
I
Idle mode: V = 5 V ± 10 %  
DD  
–
10  
DD2  
10 MHz crystal oscillator  
3 MHz crystal oscillator  
1.5  
1.2  
4
3
Idle mode: V = 3 V± 10 %  
DD  
10 MHz crystal oscillator  
3 MHz crystal oscillator  
Sub operating: main-osc stop  
0.5  
20  
1.5  
40  
I
–
–
–
uA  
DD3  
V
= 3 V ± 10 %  
DD  
32.768 kHz crystal oscillator  
OSCCON.4 = 1  
I
Sub idle mode: main-osc stop  
7
14  
DD4  
V
= 3 V ± 10 %  
DD  
32.768 kHz crystal oscillator  
OSCCON.4 = 1  
I
Main stop mode : sub-osc stop  
1
3
2
DD5  
°
V
= 5 V ± 10 %, T = 25 C  
A
DD  
°
0.5  
V
= 3 V ± 10 %, T = 25 C  
A
DD  
NOTES:  
1. Supply current does not include current drawn through internal pull-up resistors or external output current loads.  
2.  
I
and I  
include a power consumption of subsystem oscillator.  
DD1  
DD2  
3.  
I
and I  
are the current when the main system clock oscillation stop and the subsystem clock is used.  
DD4  
DD3  
And does not include the LCD and Voltage booster and voltage level detector  
4.  
I
is the current when the main and subsystem clock oscillation stop.  
DD5  
19-5  
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ELECTRICAL DATA  
S3C8245/P8245/C8249/P8249  
In case of S3C8245, the characteristic of V and V is differ with the characteristic of S3C8249 like as following.  
OH  
OL  
Other characteristics are same each other.  
Table 19-3. D.C Electrical Characteristics of S3C8245  
°
°
(T = -25 C to +85 C, V = 1.8 V to 5.5 V)  
A
DD  
Parameter  
Symbol  
Conditions  
Min  
-1.0  
Typ  
Max  
Unit  
Output high voltage  
V
V
= 5 V; I = -1 mA  
V
V
–
–
V
OH1  
DD  
OH  
DD  
All output pins except V  
OH2  
V
V
= 5 V; I = -6 mA  
-0.7  
DD  
OH2  
DD  
OH  
Port 3.0 only in S3C8245  
= 5 V; I = 2 mA  
Output low voltage  
V
V
–
–
0.4  
0.7  
OL1  
DD  
OL  
All output pins except V  
OL2  
V
V
= 5 V; I = 12 mA  
DD OH  
OL2  
Port 3.0 only in S3C8245  
19-6  
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S3C8245/P8245/C8249/P8249  
ELECTRICAL DATA  
Table 19-4. A.C. Electrical Characteristics  
°
°
(T = -25 C to +85 C, V = 1.8 V to 5.5 V)  
A
DD  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
Interrupt input  
high, low width  
(P0.0–P0.7)  
tINTH,  
tINTL  
P0.0–P0.7, V = 5 V  
–
–
–
ns  
DD  
nRESET input low  
width  
tRSL  
V
= 5 V  
5
–
–
us  
DD  
NOTE: User must keep more large value then min value.  
tTIL  
tTIH  
0.8 VDD  
0.2 VDD  
0.2 VDD  
Figure 19-1. Input Timing for External Interrupts (Ports 0)  
tRSL  
nRESET  
0.2 VDD  
Figure 19-2. Input Timing for nRESET  
19-7  
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ELECTRICAL DATA  
S3C8245/P8245/C8249/P8249  
Table 19-5. Input/Output Capacitance  
°
°
(T = -25 C to +85 C, V = 0 V )  
A
DD  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
Input  
C
f = 1 MHz; unmeasured pins  
–
–
10  
pF  
IN  
capacitance  
are returned to V  
SS  
Output  
C
OUT  
capacitance  
I/O capacitance  
C
IO  
Table 19-6. Data Retention Supply Voltage in Stop Mode  
°
°
(T = -25 C to + 85 C)  
A
Parameter  
Symbol  
Conditions  
Min  
Typ  
–
Max  
Unit  
Data retention  
supply voltage  
V
2
5.5  
V
DDDR  
Data retention  
supply current  
I
V
= 2 V  
DDDR  
–
–
3
uA  
DDDR  
nRESET  
Occurs  
Oscillation  
Stabilization  
Time  
Stop Mode  
Normal  
Operating Mode  
Data Retention Mode  
VDD  
VDDDR  
Execution of  
STOP Instrction  
nRESET  
0.2 VDD  
tWAIT  
NOTE:  
tWAIT is the same as 4096 x 16 x 1/fxx  
Figure 19-3. Stop Mode Release Timing Initiated by nRESET  
19-8  
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S3C8245/P8245/C8249/P8249  
ELECTRICAL DATA  
Oscillation  
Stabilization Time  
Idle Mode  
Stop Mode  
Data Retention Mode  
VDD  
VDDDR  
Normal  
Execution of  
STOP Instruction  
Operating Mode  
Interrupt  
0.2 VDD  
tWAIT  
NOTE:  
tWAIT is the same as 16 x BT clock.  
Figure 19-4. Stop Mode (Main) Release Timing Initiated by Interrupts  
Oscillation  
Stabilization Time  
Idle Mode  
Stop Mode  
Data Retention Mode  
VDD  
VDDDR  
Normal  
Execution of  
STOP Instruction  
Operating Mode  
Interrupt  
0.2 VDD  
tWAIT  
NOTE:  
When the case of select the fxx/128 for basic timer input  
clock before enter the stop mode.  
tWAIT = 128 x 16 x (1/32.768) = 62.5 ms  
Figure 19-5. Stop Mode (Sub) Release Timing Initiated by Interrupts  
19-9  
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ELECTRICAL DATA  
S3C8245/P8245/C8249/P8249  
Table 19-7. A/D Converter Electrical Characteristics  
(T = -25 °C to +85 °C, V  
A
= 2.7 V to 5.5 V, V = 0 V)  
DD  
SS  
Parameter  
Resolution  
Symbol  
Conditions  
Min  
–
Typ  
10  
–
Max  
–
Unit  
bit  
Total accuracy  
V
= 5.12 V  
–
±3  
LSB  
DD  
AV  
= 5.12 V  
REF  
AV = 0 V  
SS  
Integral Linearity  
Error  
ILE  
CPU clock = 10 MHz  
–
–
±2  
Differential Linearity  
Error  
DLE  
±1  
Offset Error of Top  
EOT  
EOB  
±1  
±3  
Offset Error of  
Bottom  
±0.5  
±2  
(1)  
t
–
–
–
–
40  
–
–
fxx  
V
Conversion time  
CON  
Analog input voltage  
V
AV  
AV  
REF  
IAN  
SS  
Analog input  
impedance  
R
2
1000  
–
MW  
AN  
Analog reference  
voltage  
AV  
–
2.5  
–
V
V
REF  
DD  
Analog ground  
Analog input current  
Analog block  
AV  
–
V
–
–
1
V + 0.3  
SS  
SS  
SS  
I
AV  
AV  
= V = 5 V  
–
–
10  
uA  
ADIN  
REF  
REF  
DD  
I
= V = 5 V  
3
mA  
ADC  
DD  
(2)  
current  
AV  
AV  
= V = 3 V  
0.5  
1.5  
REF  
REF  
DD  
= V = 5 V  
100  
500  
nA  
DD  
When power down mode  
NOTES:  
1. 'Conversion time' is the time required from the moment a conversion operation starts until it ends.  
2. is an operating current during A/D conversion.  
I
ADC  
19-10  
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S3C8245/P8245/C8249/P8249  
ELECTRICAL DATA  
Table 19-8. Voltage Booster Electrical Characteristics  
(T = 25 °C, V = 2.0 V to 5.5 V, V = 0 V)  
A
DD  
SS  
Parameter  
Symbol  
Test Conditions  
Min  
2.0  
0.9  
Typ  
–
Max  
5.5  
Unit  
Operating Voltage  
Regulated Voltage  
VDD  
V
V
I
= 5 uA (1/3 bias)  
1.0  
1.15  
LC0  
LC1  
LC0  
Booster Voltage  
V
Connect 1 MW load between  
and V  
2V  
–
2VLC0  
+ 0.1  
LC0  
V
SS  
LC1  
- 0.1  
V
Connect 1 MW load between  
3V  
–
3VLC0  
+ 0.1  
LC2  
LC0  
V
and V  
SS  
LC2  
- 0.1  
Regulated Voltage  
Booster Voltage  
V
V
I
= 6 uA (1/2 bias)  
1.4  
1.5  
–
1.7  
LC0  
LC1  
LC0  
Connect 1 MW load between  
and V  
2V  
2VLC0  
+ 0.1  
LC0  
V
SS  
LC1  
- 0.1  
V
Connect 1 MW load between  
and V  
LC2  
V
SS  
LC2  
Table 19-9. Characteristics of Voltage Level Detect Circuit  
°
(T = 25 C)  
A
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
Operating Voltage of VLD  
Voltage of VLD  
V
1.8  
–
5.5  
V
V
DDVLD  
V
VLDCON.1.0 = 00b  
2.05  
2.2  
2.35  
VLD  
VLDCON.1.0 = 01b  
VLDCON.1.0 = 10b  
VLDCON.1.0 = 11b  
VLCDCON.1-.0=00  
IVB+IVLD+IDD4,  
2.25  
2.8  
3.7  
–
2.4  
3.0  
4.0  
10  
2.55  
3.2  
4.3  
100  
40  
Hysteresys Voltage of VLD  
DV  
mV  
uA  
Sum of Voltage Booster,  
Voltage Detector and Sub-  
idle current  
IVBVLD  
–
15  
VDD=3.0V  
19-11  
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ELECTRICAL DATA  
S3C8245/P8245/C8249/P8249  
Table 19-10. Synchronous SIO Electrical Characteristics  
(T = -25 C to +85 C, V = 1.8 V to 5.5 V, V = 0 V, fxx = 10 MHz oscillator)  
°
°
A
DD  
SS  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
SCK Cycle time  
t
–
–
–
–
200  
–
–
ns  
CYC  
Serial Clock High Width  
Serial Clock Low Width  
t
60  
60  
–
–
–
–
–
–
SCKH  
t
SCKL  
Serial Output data delay  
time  
t
50  
OD  
Serial Input data setup  
time  
t
–
–
40  
–
–
–
–
ID  
Serial Input data Hold time  
t
100  
IH  
tCYC  
tSCKL  
tSCKH  
SCK  
0.8 VDD  
0.2 VDD  
tID  
tIH  
0.8 VDD  
0.2 VDD  
SI  
Input Data  
tOD  
SO  
Output Data  
Figure 19-6. Serial Data Transfer Timing  
19-12  
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S3C8245/P8245/C8249/P8249  
ELECTRICAL DATA  
Table 19-11. Main Oscillator Frequency (f  
)
OSC1  
°
°
(T = -25 C to +85 C, V  
= 1.8 V to 5.5 V)  
DD  
A
Oscillator  
Crystal  
Clock Circuit  
Test Condition  
Min  
Typ  
Max  
Unit  
Crystal oscillation frequency  
1
–
10  
MHz  
XIN  
XOUT  
C1  
C2  
Ceramic  
External clock  
RC  
Ceramic oscillation frequency  
1
1
1
–
–
–
10  
10  
2
MHz  
MHz  
MHz  
XIN  
XOUT  
C1  
C2  
X input frequency  
XIN  
XOUT  
IN  
V
= 5 V  
XIN  
XOUT  
DD  
R
Table 19-12. Main Oscillator Clock Stabilization Time (t  
)
ST1  
°
°
(T = -25 C to +85 C, V = 2.0 V to 5.5 V)  
A
DD  
Oscillator  
Test Condition  
= 2.0 V to 5.5 V  
Min  
Typ  
Max  
Unit  
Crystal  
V
–
–
40  
ms  
DD  
Ceramic  
Stabilization occurs when V is equal to the minimum  
–
–
4
ms  
DD  
oscillator voltage range.  
External clock  
X input high and low level width (t , t  
)
50  
–
500  
ns  
IN  
XH XL  
NOTE: Oscillation stabilization time (t  
) is the time required for the CPU clock to return to its normal oscillation  
ST1  
frequency after a power-on occurs, or when Stop mode is ended by a nRESET signal.  
The nRESET should therefore be held at low level until the t time has elapsed  
ST1  
19-13  
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ELECTRICAL DATA  
S3C8245/P8245/C8249/P8249  
1/fosc1, 1/fosc2  
tXL , tXTL  
tXH, tXTH  
XIN, XT IN  
VDD - 0.1V  
0.1V  
Figure 19-7. Clock Timing Measurement at X  
Table 19-13. Sub Oscillator Frequency (f  
IN  
)
OSC2  
°
°
(T = -25 C + 85 C, V  
= 1.8 V to 5.5 V)  
DD  
A
Oscillator  
Clock Circuit  
XT IN XT OUT  
R
Test Condition  
Min  
Typ  
Max  
Unit  
Crystal  
Crystal oscillation frequency  
32  
32.768  
35  
kHz  
C1 = 22 pF,  
C2 = 33 pF  
R = 39 kW  
C1  
C2  
External Clock  
XT input frequency  
32  
–
100  
kHz  
XTIN XTOUT  
IN  
19-14  
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S3C8245/P8245/C8249/P8249  
ELECTRICAL DATA  
Table 19-14. Sub Oscillator(crystal) Stabilization Time (t  
)
ST2  
°
(T = 25 C)  
A
Oscillator  
Test Condition  
Min  
Typ  
Max  
Unit  
Crystal Normal  
mode  
V
=4.5V to 5.5V  
–
1
2
sec  
DD  
V
V
=2.0V to 4.5V  
–
–
–
–
10  
6
sec  
sec  
DD  
Crystal Strong  
mode  
=3.0V to 5.5V  
DD  
V
V
=2.0V to 3.0V  
–
5
–
–
2
sec  
DD  
External clock  
=2.0V to 5.5V  
15  
ms  
DD  
XT input high and low level width(t  
, t  
)
IN  
XTH XTL  
NOTE: Oscillation stabilization time (t  
) is the time required for the oscillator to it’s normal oscillation when stop mode  
ST2  
is released by interrupts.  
fCPU  
B
10 MHz  
8 MHz  
A
3 MHz  
1 MHz  
1
2
3
4
5
6
7
1.8  
2.7  
Supply Voltage (V)  
5.5  
Minimum instruction clock = 1/4 x oscillator frequency  
Figure 19-8. Operating Voltage Range  
19-15  
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ELECTRICAL DATA  
S3C8245/P8245/C8249/P8249  
NOTES  
19-16  
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S3C8245/P8245/C8249/P8249  
MECHANICAL DATA  
20  
MECHANICAL DATA  
OVERVIEW  
The S3C8245/C8249 microcontroller is currently available in 80-pin-QFP/TQFP package.  
23.90  
20.00  
±
±
0.30  
0.20  
0-8  
+ 0.10  
- 0.05  
0.15  
0.10 MAX  
80-QFP-1420C  
#80  
#1  
0.35 + 0.10  
0.15 MAX  
0.05 MIN  
2.65  
3.00 MAX  
0.80  
(0.80)  
±
0.10  
0.80 ± 0.20  
NOTE  
:
Dimensions are in millimeters.  
Figure 20-1. Package Dimensions (80-QFP-1420C)  
20-1  
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MECHANICAL DATA  
S3C8245/P8245/C8249/P8249  
14.00 BSC  
12.00 BSC  
0-7  
0.09-0.20  
80-TQFP-1212  
#80  
#1  
0.17-0.27  
0.08 MAX  
0.05-0.15  
0.50  
M
(1.25)  
1.00  
±
0.05  
1.20 MAX  
NOTE: Dimensions are in millimeters.  
Figure 20-2. Package Dimensions (80-TQFP-1212)  
20-2  
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S3C8245/P8245/C8249/P8249  
S3P8245/P8249 OTP  
21  
S3P8245/P8249 OTP  
OVERVIEW  
The S3P8245/P8249 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the  
S3C8245/C8249 microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed  
by serial data format.  
The S3P8245/P8249 is fully compatible with the S3C8245/C8249, both in function and in pin configuration. Because  
of its simple programming requirements, the S3P8245/P8249 is ideal as an evaluation chip for the S3C8245/C8249.  
21-1  
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S3P8245/P8249 OTP  
S3C8245/P8245/C8249/P8249  
SEF26/P5.2  
SEG27/P5.3  
SEG28/P5.4  
SEG29/P5.5  
SEG30/P5.6  
SEG31/P5.7  
1
2
3
4
5
6
7
8
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
SEG9  
SEG8  
SEG7  
SEG6  
SEG5  
SEG4  
SEG3  
SEG2  
P3.0/TBPWM  
P3.1/TAOUT/TAPWM  
P3.2/TACLK  
P3.3/TACAP/SDAT  
P3.4/SCLK  
VDD  
9
SEG1  
SEG0  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
S3P8245/P8249  
COM3  
COM2  
COM1  
COM0  
VLC2  
VLC1  
VLC0  
CA  
CB  
80-QFP  
VSS  
XOUT  
XIN  
VPP/TEST  
XTIN  
(Top View)  
XT OUT  
nRESET  
P0.0/INT0  
P0.1/INT1  
P0.2/INT2  
P0.3/INT3  
P0.4/INT4  
AVSS  
AVREF  
P2.7/ADC7/VVLDREF  
P2.6/ADC6  
P2.5/ADC5  
Figure 21-1. S3P8245/P8249 Pin Assignments (80-QFP) Package  
21-2  
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S3C8245/P8245/C8249/P8249  
S3P8245/P8249 OTP  
Table 21-1. Descriptions of Pins Used to Read/Write the EPROM  
Main Chip  
Pin Name  
P3.3  
During Programming  
I/O  
Pin Name  
SDAT  
Pin No.  
Function  
10  
I/O  
Serial data pin. Output port when reading and input  
port when writing. Can be assigned as a  
Input/push-pull output port.  
P3.4  
SCLK  
TEST  
11  
16  
I
I
Serial clock pin. Input only pin.  
V
Power supply pin for EPROM cell writing  
(indicates that OTP enters into the writing mode).  
When 12.5 V is applied, OTP is in writing mode  
and when 5 V is applied, OTP is in reading mode.  
(Option)  
PP  
nRESET  
nRESET  
19  
I
Chip Initialization  
V
/V  
V
/V  
12/13  
–
Logic power supply pin. V should be tied to  
DD SS  
DD SS  
DD  
+5 V during programming.  
Table 21-2. Comparison of S3P8245/P8249 and S3C8245/C8249 Features  
Characteristic  
S3P8245/P8249  
16K/32K-byte EPROM  
1.8 V to 5.5 V  
V = 5 V, V (TEST) = 12.5 V  
DD  
S3C8245/C8249  
16K/32K-byte mask ROM  
1.8 V to 5.5 V  
Program Memory  
Operating Voltage (V  
)
DD  
OTP Programming Mode  
PP  
Pin Configuration  
80-QFP/80-TQFP  
80-QFP/80-TQFP  
EPROM Programmability  
User Program 1 time  
Programmed at the factory  
21-3  
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S3P8245/P8249 OTP  
S3C8245/P8245/C8249/P8249  
OPERATING MODE CHARACTERISTICS  
When 12.5 V is supplied to the V (TEST) pin of the S3P8245/P8249, the EPROM programming mode is entered.  
PP  
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in  
Table 21-3 below.  
Table 21-3. Operating Mode Selection Criteria  
V
V
(TEST)  
PP  
REG/nMEM  
Address(A15–A0)  
R/W  
Mode  
EPROM read  
DD  
5 V  
5 V  
0
0
0
1
0000H  
0000H  
0000H  
0E3FH  
1
0
1
0
12.5 V  
12.5 V  
12.5 V  
EPROM program  
EPROM verify  
EPROM read protection  
NOTE: "0" means Low level; "1" means High level.  
Table 21-4. D.C Electrical Characteristics  
= 1.8 V to 5.5 V)  
DD  
°
°
(T = -25 C to +85 C, V  
A
Parameter  
Symbol  
Conditions  
= 10 MHz  
CPU  
Min  
Typ  
Max  
Unit  
Operating voltage  
V
f
2.7  
–
–
–
–
–
–
5.5  
V
DD  
All input pins except V  
1.8  
5.5  
IH2, 3  
Input high  
voltage  
V
Port 4,5  
X , XT  
V
³ V  
0.8 V  
V
IH1  
LCD2  
DD  
DD  
DD  
V
0.8 V  
V
IH2  
IN  
IN  
DD  
DD  
V
All input pins except V  
X , XT  
V
- 0.1  
V
IH3  
IL2  
DD  
DD  
Input low voltage  
V
–
0.2 V  
DD  
IL1  
IN  
IN  
V
V
= 5 V; I = -1 mA  
0.1  
IL2  
DD  
OH  
All output pins  
= 5 V; I  
Output high voltage  
Output low voltage  
V
V
= 2 mA  
V
-1.0  
DD  
–
–
–
OH  
DD  
OL  
All output pins  
V
–
0.4  
OL  
21-4  
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S3C8245/P8245/C8249/P8249  
S3P8245/P8249 OTP  
Table 21-4. D.C. Electrical Characteristics (Continued)  
°
°
(T = -25 C to +85 C, V = 1.8 V to 5.5 V)  
A
DD  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
Input high leakage  
current  
I
V
= V  
DD  
–
–
3
20  
-3  
LIH1  
IN  
All input pins except I  
LIH2  
I
V
X
= V  
XT  
LIH2  
IN  
DD  
,
IN  
IN  
Input low leakage  
current  
I
V
= 0 V  
–
–
LIL1  
IN  
All input pins except I  
LIL2  
I
V
X
= 0 V  
IN  
-20  
uA  
LIL2  
XT nRESET  
,
IN  
,
IN  
Output high leakage  
current  
I
V
= V  
DD  
–
–
–
–
3
-3  
LOH  
OUT  
All I/O pins and Output pins  
V = 0 V  
OUT  
Output low leakage  
current  
I
LOL  
All I/O pins and Output pins  
°
Oscillator feed back  
resistors  
R
300  
600  
1500  
kW  
V
= 5.0 V T = 25 C  
osc1  
A
DD  
X = V , X  
= 0 V  
IN  
DD OUT  
Pull-up resistor  
R
V
= 0 V; V = 5 V ±10 %  
25  
50  
100  
310  
1.15  
L1  
IN  
DD  
°
Port 0,1,2,3,4,5 T = 25 C  
A
R
V
= 0 V; V  
= 5 V ±10%  
DD  
110  
0.9  
210  
1.0  
IN  
L2  
°
T =25 C, nRESET only  
A
V
out voltage  
V
T = 25 °C (1/3 bias mode)  
V
LC0  
LC0  
A
(Booster run mode)  
T = 25 °C (1/2 bias mode)  
1.4  
1.5  
–
1.7  
A
V
out voltage  
V
T = 25 °C  
2V  
3V  
- 0.1  
2V  
3V  
+ 0.1  
LC1  
LC1  
A
LC0  
LC0  
(Booster run mode)  
V
out voltage  
V
T = 25 °C  
- 0.1  
–
+ 0.1  
LC2  
LC2  
A
LC0  
LC0  
(Booster run mode)  
COM output  
voltage deviation  
V
V
= V = 3 V  
LC2  
–
± 60  
± 120  
mV  
DC  
DD  
(V -COMi)  
LC  
IO = ± 15 mA (1 = 0–3)  
= V = 3 V  
SEG output  
voltage deviation  
V
V
–
± 60  
± 120  
Ds  
DD  
LC2  
(V -COMi)  
LC  
IO = ± 15 mA (1 = 0–3)  
NOTE: Low leakage current is absolute value.  
21-5  
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S3P8245/P8249 OTP  
S3C8245/P8245/C8249/P8249  
Table 21-4. D.C. Electrical Characteristics (Concluded)  
°
°
(T = -25 C to + 85 C, V = 1.8 V to 5.5 V)  
A
DD  
Parameter  
Symbol  
Conditions  
= 5 V ± 10 %  
Min  
Typ  
Max  
Unit  
(1)  
(2)  
V
–
12  
25  
mA  
Supply current  
I
DD  
DD1  
10 MHz crystal oscillator  
3 MHz crystal oscillator  
4
3
10  
8
V
= 3 V ± 10 %  
DD  
10 MHz crystal oscillator  
3 MHz crystal oscillator  
1
3
5
I
Idle mode: V = 5 V ± 10 %  
DD  
10  
DD2  
10 MHz crystal oscillator  
3 MHz crystal oscillator  
1.5  
1.2  
4
3
Idle mode: V = 3 V ± 10 %  
DD  
10 MHz crystal oscillator  
3 MHz crystal oscillator  
Sub operating: main-osc stop  
0.5  
20  
1.5  
40  
I
–
–
–
uA  
DD3  
V
= 3 V ± 10 %  
DD  
32.768 kHz crystal oscillator  
OSCCON.4 = 1  
I
Sub idle mode: main-osc stop  
7
14  
DD4  
V
= 3 V ± 10 %  
DD  
32.768 kHz crystal oscillator  
OSCCON.4 = 1  
I
Main stop mode : sub-osc stop  
1
3
2
DD5  
°
V
= 5 V ± 10 %, T = 25 C  
A
DD  
°
0.5  
V
= 3 V ± 10 %, T = 25 C  
A
DD  
NOTES:  
1. Supply current does not include current drawn through internal pull-up resistors or external output current loads.  
2.  
I
and I  
include a power consumption of subsystem oscillator.  
DD  
DD2  
and I  
3.  
I
are the current when the main system clock oscillation stop and the subsystem clock is used.  
DD4  
DD3  
And does not include the LCD, voltage booster, and voltage level detector.  
I is the current when the main and subsystem clock oscillation stop.  
DD5  
4.  
21-6  
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S3C8245/P8245/C8249/P8249  
S3P8245/P8249 OTP  
Case of S3P8245, the characteristic of V and V is differ with the characteristic of S3P8249 like as bellow. Other  
OH  
OL  
characteristics are same each other.  
Table 21-5. D.C Electrical Characteristics of S3C8245  
°
°
(T = -25 C to +85 C, V = 1.8 V to 5.5 V)  
A
DD  
Parameter  
Symbol  
Conditions  
Min  
-1.0  
Typ  
Max  
Unit  
Output high voltage  
V
V
= 5 V; I = -1 mA  
V
V
–
–
V
OH1  
DD  
OH  
DD  
All output pins except V  
OH2  
V
V
= 5 V; I = -6 mA  
-0.7  
DD  
OH2  
DD  
OH  
Port 3.0 only in S3P8245  
= 5 V; I = 2 mA  
Output low voltage  
V
V
–
–
0.4  
0.7  
OL1  
DD  
OL  
All output pins except V  
OL2  
V
V
= 5 V; I = 12 mA  
DD OH  
OL2  
Port 3.0 only in S3P8245  
fCPU  
B
10 MHz  
8 MHz  
A
3 MHz  
1 MHz  
1
2
3
4
5
6
7
1.8  
2.7  
Supply Voltage (V)  
5.5  
Minimum instruction clock = 1/4 x oscillator frequency  
Figure 21-2. Operating Voltage Range  
21-7  
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S3P8245/P8249 OTP  
S3C8245/P8245/C8249/P8249  
NOTES  
21-8  
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S3C8245/P8245/C8249/P8249  
DEVELOPMENT TOOLS  
22  
DEVELOPMENT TOOLS  
OVERVIEW  
Samsung provides a powerful and easy-to-use development support system in turnkey form. The development  
support system is configured with a host system, debugging tools, and support software. For the host system, any  
standard computer that operates with MS-DOS, Windows 95, and 98 as its operating system can be used. One  
type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit  
emulator, SMDS2+, and OPENice for S3C7, S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and  
improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a  
program for setting options.  
SHINE  
Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE  
provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It  
has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized,  
moved, scrolled, highlighted, added, or removed completely.  
SAMA ASSEMBLER  
The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object  
code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data  
and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary  
definition (DEF) file with device specific information.  
SASM88  
The SASM88 is a relocatable assembler for Samsung's S3C8-series microcontrollers. The SASM88 takes a source  
file containing assembly language statements and translates into a corresponding source code, object code and  
comments. The SASM88 supports macros and conditional assembly. It runs on the MS-DOS operating system. It  
produces the relocatable object code only, so the user should link object file. Object files can be linked with other  
object files and loaded into memory.  
HEX2ROM  
HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be  
needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by  
HEX2ROM, the value "FF" is filled into the unused ROM area up to the maximum ROM size of the target device  
automatically.  
TARGET BOARDS  
Target boards are available for all S3C8-series microcontrollers. All required target system cables and adapters are  
included with the device-specific target board.  
22-1  
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DEVELOPMENT TOOLS  
S3C8245/P8245/C8249/P8249  
IBM-PC AT or Compatible  
RS-232C  
SMDS2+  
Target  
Application  
System  
PROM/OTP Writer Unit  
RAM Break/Display Unit  
Trace/Timer Unit  
Probe  
Adapter  
TB8249  
Target  
POD  
SAM8 Base Unit  
Board  
EVA  
Power Supply Unit  
Chip  
Figure 22-1. SMDS Product Configuration (SMDS2+)  
22-2  
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S3C8245/P8245/C8249/P8249  
TB8245/9 TARGET BOARD  
DEVELOPMENT TOOLS  
The TB8245/9 target board is used for the S3C8245/C8249 microcontroller. It is supported with the SMDS2+.  
TB8245/8249  
To User_VCC  
On  
Device Selection  
Off  
8245  
8249  
RESET  
Idle  
+
Stop  
+
7411  
25  
J101  
J102  
1
2
41  
42  
144 QFP  
S3E8240  
EVA Chip  
1
XI  
MDS  
XTAL  
39  
40 79  
80  
SM1317A  
Figure 22-2. TB8245/8249 Target Board Configuration  
22-3  
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DEVELOPMENT TOOLS  
S3C8245/P8245/C8249/P8249  
Table 22-1. Power Selection Settings for TB8245/9  
Operating Mode  
"To User_Vcc" Settings  
Comments  
The SMDS2/SMDS2+ supplies  
To User_VCC  
V
to the target board  
CC  
TB8245  
TB8249  
Off  
On  
Target  
System  
(evaluation chip) and the target  
system.  
VCC  
VSS  
VCC  
SMDS2/SMDS2+  
The SMDS2/SMDS2+ supplies  
To User_VCC  
On  
V
only to the target board  
CC  
TB8245  
TB8249  
External  
VCC  
Off  
Target  
System  
(evaluation chip).  
The target system must have  
its own power supply.  
VSS  
VCC  
SMDS2+  
NOTE: The following symbol in the "To User_Vcc" Setting column indicates the electrical short (off) configuration:  
Table 22-2. Main-clock Selection Settings for TB8245/9  
Sub Clock Settings  
Operating Mode  
Comments  
Set the XI switch to “MDS”  
when the target board is  
connected to the  
XIN  
EVA Chip  
S3E8240  
MDS  
XTAL  
SMDS2/SMDS2+.  
XOUT  
XIN  
No Connection  
100 Pin Connector  
SMDS2/SMDS2+  
Set the XI switch to “XTAL”  
when the target board is used  
as a standalone unit, and is  
not connected to the  
XIN  
EVA Chip  
S3E8240  
MDS  
XTAL  
SMDS2/SMDS2+.  
XOUT  
XIN  
XTAL  
Target Board  
22-4  
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S3C8245/P8245/C8249/P8249  
DEVELOPMENT TOOLS  
Comments  
Table 22-3. Device Selection Settings for TB8245/9  
Operating Mode  
"To User_Vcc" Settings  
Operate with TB8249  
Device Selection  
Target  
System  
8245  
8249  
TB8249  
TB8245  
Operate with TB8245  
Device Selection  
Target  
System  
8245  
8249  
SMDS2+ SELECTION (SAM8)  
In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for  
SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available.  
Table 22-4. The SMDS2+ Tool Selection Setting  
"SW1" Setting  
SMDS2 SMDS2+  
Operating Mode  
R/W  
SMDS2+  
R/W  
Target  
System  
IDLE LED  
The Yellow LED is ON when the evaluation chip (S3E8240) is in idle mode.  
STOP LED  
The Red LED is ON when the evaluation chip (S3E8240) is in stop mode.  
22-5  
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DEVELOPMENT TOOLS  
S3C8245/P8245/C8249/P8249  
J101  
J102  
SEG26/P5.2  
SEG28/P5.4  
SEG30/P5.6  
P3.0/TBPWM  
P3.2/TACLK  
P3.4/SCLK  
VSS  
1
3
5
7
2
4
6
SEG27/P5.3  
SEG29/P5.5  
SEG31/P5.7  
P3.1/TAOUT/TAPWM  
P3.3/TACAP/SDAT  
VDD  
XOUT  
TEST  
XTOUT  
P0.0/INT0  
P0.2/INT2  
P0.4/INT4  
P0.6/INT6  
P1.0/T1CAP  
P1.2/T1OUT/T1PWM  
P1.4/BUZ  
P2.5/ADC5  
P2.7/ADC7/VVLDREF  
AVSS  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
73  
75  
77  
79  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
74  
76  
78  
80  
P2.6/ADC6  
AVREF  
CB  
VLC0  
VLC2  
COM1  
COM3  
SEG1  
SEG3  
SEG5  
8
CA  
VLC1  
COM0  
COM2  
SEG0  
SEG2  
SEG4  
SEG6  
SEG8  
SEG10  
SEG12  
SEG14  
SEG16  
SEG18  
SEG20  
SEG22  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
XIN  
XTIN  
nRESET  
P0.1/INT1  
P0.3/INT3  
P0.5/INT5  
P0.7/INT7  
P1.1/T1CLK  
P1.3  
P1.5/SO  
P1.7/SI  
P2.1/ADC1  
P2.3/ADC3  
SEG7  
SEG9  
SEG11  
SEG13  
SEG15  
SEG17  
SEG19  
SEG21  
SEG23  
SEG25/P5.1  
P1.6/SCK  
P2.0/ADC0  
P2.2/ADC2  
P2.4/ADC4  
SEG24/P5.0  
Figure 22-3. 40-Pin Connectors (J101, J102) for TB8245/8249  
Target Board  
Target System  
J102  
J101  
J101  
J102  
1
2
41 42  
41 42  
1
2
Target Cable for 40-Pin Connector  
Part Name: AS40D-A  
Order Code: SM6306  
39 40 79 80  
79 80 39 40  
Figure 22-4. S3E8240 Cablesfor 80-QFP Package  
22-6  
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