Evaluation Board Manual
S3F401F
16/32-BIT RISC
MICROPROCESSOR
Dec, 2007
REV 1.00
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EVALUATION BOARD MANUAL
S3F401F_BD_UM_REV1.00
1
EVALUATION BOARD MANUAL
1. OVERVIEW
S3F401F EVB (Evaluation Board) is a compact platform that is suitable for code development of SAMSUNG's
S3F401F 16-/32-bit RISC microcontroller for an inverter motor and general purpose application.
EVB is consists of several blocks, which can make operate the function of S3F401F. Those functions are from the
followings:
•
•
•
•
•
•
•
•
•
•
•
•
A 16-/32-bit RISC CPU Core, ARM7TDMI-S
A built-in 256Kbyte NOR-Flash memory
An internal 20KB SRAM for stack, data, or code
An interrupt controller, supporting vectored interrupt
6xch 16-bit timers with capture and PWM function
1xch 8-bit basic timer & 3-bit watch-dog timer
Three programmable I/O port groups
2xch Inverter motor controller
2xch 16-bit Encoder counter
15xch 12-bit ADC
2xch UART
2xch SSP
If you need more detail information about S3F401F, meet the samsung web site.
1
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EVALUATION BOARD MANUAL
S3F401F_BD_UM_REV1.00
AHB
FLASH-ROM
256KB
ARM7TDMI-S
CORE
SRAM
20KB
INTERRUPT
CONTROLLER
TAP CONTROLLER
For JTAG
Crystal or
Ceramic
Oscillator
PLL
BRIDGE
APB
CLOCK
IMC0/1
ENC0/1
UART0/1
MONITOR
I/O
CONTROLLER
SSP0/1
BT & WDT
TIMER 0/1/2/3/4/5
12-BIT ADC
Figure 1. S3F401F Block Diagram
2
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EVALUATION BOARD MANUAL
1.1 FEATURES
S3F401F_BD_UM_REV1.00
Micro-Controller
S3F401F, ARM7TDMIS, 16/32-bit RISC Microcontroller
External DC 7~12V
Board Power Source
Adjustable voltage regulator out is 3.2V
Board Master Power Switch SW6
UART
Support to protocol for RS-232
Physical interface circuit connected to standard PC through DB9(female)
Interface driver IC MAX3221
Synchronous Serial Port
Provide SSP, SPI serial communication with external devices (master or slave)
SSP serial EEPROM (8K * 8bit): X25650
SSP serial EEPROM (4K * 16bit): 64LC40S
IO Port output control display
LED
JTAG Connection
20Way JTAG connector (Multi-ICE Interface, Trace 32 etc.)
1.2 SYSTEM REQUIREMENTS
This section describes the hardware and software system requirements.
Software Requirements
Hardware Requirements
ARM Compiler SW
ARM Debugger SW
S3F401F EVB Board Set
Power Supply DC 7~12V ( Recommend Default 12V)
Debugger (Multi-ICE or Trace 32 etc.)
PC(Pentium, 32MB RAM for Windows 95, or 64MB RAM for Windows NT)
COM Port for serial communication
Parallel Port (If using Multi-ICE)
3
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EVALUATION BOARD MANUAL
S3F401F_BD_UM_REV1.00
1.3 BOARD COMPONENTS
The board consists of the followings.
S3F401F Micro-controller
64LC40S and X25650 as a serial EEPROM for SSP
2 x DSUB Connector for RS-232
2 x Header groups for IMC function
1 x Buzzer
6 x Switches: IRQ x 2, Power, Reset
4 x LED: Power x1, IO Port output x 3
A regulator to generate 3.3V
4MHz Crystal as a master system clock source
Switches for ADC input capacitor selection
7-segment (4-digit) display circuit
A standard 20-pin JTAG interface connector
Dual-line header pins for a port level or signal
53 x Jumpers for function setting control
15 x TP (Test Pole) to check specific pins relating to the digital, analog, PLL power and clock
4
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EVALUATION BOARD MANUAL
S3F401F_BD_UM_REV1.00
2. CONFIGURATION
IMC1 HEADER CONNECTOR
Page 1-11
SSP BLOCK
Page 1-9
JTAG
12-bit ADC BLOCK
Page 1 -12
MODE SETTING BLOCK
Page 1-7
Buzzer
S3F401FX
Main OSC
POWER BLOCK
Page 1-6
UART BLOCK
Page 1-8
7-SEGMENT
Page 1-10
IMC0 HEADER CONNECTOR
Page 1-11
Figure 2. S3F401F Evaluation Board Top-view
5
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EVALUATION BOARD MANUAL
S3F401F_BD_UM_REV1.00
2.1 DETAILED BLOCK CONFIGURATIONS
2.1.1 Power Block
5
4
2
3
1
①
CN1, CN2, J23: Power Supply Connector
CN1 : VIN
CN2 : GND
J23 : DC adapter connector
②
U7: Adjustable Voltage Regulator
3.3V generator J VDD33, VDDCORE, VDDIO
③
④
SW6: Power Switch
DS4: Power Display LED
VDD33 Power-on status display
⑤
J22: Jumper Setting
Selection VDDCORE / VDDIO
1-2 connection: The VDD of each block is connected to VDD33.
6
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EVALUATION BOARD MANUAL
2.1.2 Mode Setting Block
S3F401F_BD_UM_REV1.00
J9 & J10 & J11: Jumper Setting
J9
J10
J11
MD[2:0]
NORMAL
2-3 Connection
1-2 Connection
2-3 Connection
2-3 Connection
Others
2-3 Connection
2-3 Connection
SPGM
Only TEST Mode
7
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EVALUATION BOARD MANUAL
2.1.3 UART Block
S3F401F_BD_UM_REV1.00
2
④
1
3
① U10, U11: UART Driver IC
② P2, P3: UART Connector
Jumper Setting
③J25
TXD0 UARTTXD0 is connected to T1IN of MAX3221.
RXD0 UARTRXD0 is connected to R1OUT of MAX3221.
Jumper Setting
④J26
TXD1 UARTTXD1 is connected to T1IN of MAX3221
RXD1 UARTRXD1 is connected to R1OUT of MAX3221.
8
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EVALUATION BOARD MANUAL
S3F401F_BD_UM_REV1.00
9
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EVALUATION BOARD MANUAL
2.1.4 SSP Block
S3F401F_BD_UM_REV1.00
2
1
①
U9: SSP8 serial EEPROM (8K × 8bit)
SW9 ON
FSS0 is connected to P1.16.
RXD0 is connected to P1.14.
SW10 ON CLK0 is connected to P1.15.
TXD0 is connected to P1.13.
②
U8: SSP16 serial EEPROM (4K × 16bit)
SW7 ON
FSS1 is connected to P1.20.
CLK1 is connected to P1.19.
RXD1 is connected to P1.18.
TXD1 is connected to P1.17.
SW8 ON
The RDY/nBUSY pin is connected to P2.11.
The RESET pin is connected to P2.10.
10
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EVALUATION BOARD MANUAL
S3F401F_BD_UM_REV1.00
11
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EVALUATION BOARD MANUAL
2.1.5 7-SEGMENT BLOCK
S3F401F_BD_UM_REV1.00
1
2
3
The assignment of 7-segment control pins on the S3F401F-EVB is the same like this.
①
②
③
SW1 ON: This Port (P0.0~P0.7) is connected to each segment of 7-segment.
SW2 ON: This Port (P1.9~P1.12) is connected to latch.
U3: 7-segment display
12
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EVALUATION BOARD MANUAL
2.1.6 IMC BLOCK
S3F401F_BD_UM_REV1.00
1
2
The assignment of IMC pins on the S3F401F-EVB is the same like this.
①
②
J20: A header pin group for MOTOR1
J21: A header pin group for MOTOR2
13
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EVALUATION BOARD MANUAL
2.1.7 ADC BLOCK
S3F401F_BD_UM_REV1.00
⑥
2
3
4
5
1
①
②
J1: ADC input connector
J2, J3, J4: J2, J3 and J4 are selected to sample test with AIN0, AIN1 and AIN2
③
④
RV1: Variable Resistor
J24: ADC Power Source
Close: When connecting (short), AVDD is same to VDD33.
Open: AVDD is a second (right) pin of J24. So, AVDD should be connected to another power.
⑤
⑥
J7: 2,3 connection - ADTRG signal is generated by SW4
SW11, SW12: Control cap for each ADC input port.
14
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EVALUATION BOARD MANUAL
S3F401F_BD_UM_REV1.00
3. TOTAL BLOCKS’ UNIT & JUMPER SUMMURY
3.1 FUNCTION BLOCKS
Block
7-SEGMENT
IMC
Symbols
U3
Description
4Digit Segment
MOTOR 1
J20
J21
MOTOR 2
UART
SSP
U14
P41
U7
RS-232 transceiver
RS-232 connector
SPI8 interface EEPROM (8K × 8bit)
SPI16 interface EEPROM (4K × 16bit)
SPI block pin assignment
3.3V generator regulator
Red LED
U8
J28
POWER
LED
U11
DS1
DS2
DS3
BZ1
Green LED
Yellow LED
BUZZER
Buzzer
15
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EVALUATION BOARD MANUAL
S3F401F_BD_UM_REV1.00
3.2 JUMPER CONNECTION
JP#
Description
Default Setting
−
J1
J2
ADC block pin assignment
AIN0 input voltage connector
AIN0~AIN14
Connect (Short)
J3
AIN1 input voltage connector
Connect (Short)
J4
AIN2 input voltage connector
Connect (Short)
J5
J6
J7
J8
SW3_INPUT
Open
VDDIO connects to INT7
Buzzer connector
SW4_INPUT
Connect (Short)
Connect ADTRG
Connect (Short)
T3PWM connects to Buzzer
VDDIO connects to INT8
LED signal connector
Port 0.0/0.1/0.2 connect to DS1, DS2, DS3
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EVALUATION BOARD MANUAL
S3F401F_BD_UM_REV1.00
3.2 JUMPER CONNECTION (Continued)
JP#
J9
Description
Default Setting
MODE selection
J9
2-3
J10
2-3
2-3
J11
2-3
2-3
MD[1:0]
NORMAL
SPGM
All 2-3 connect
:Normal Mode
J10
J11
1-2
J12 Port assignment pin
J13 Port assignment pin
J14 Port assignment pin
J15 nTRST
Port 2
Port 1
Port 0
Open
Open
Open
Open
The JTAG connects to nTRST
J16 Chip socket connection
J17
Chip socket board is connected with
S3F401F-EVB.
Use the chip socket
board
J18
J19
J20 MOTOR1
J21 MOTOR2
IMC0 and ENC0 signal connector
IMC1 and ENC1 signal connector
-
-
J22 Generated VDD33 voltage from 3.3V connects to VDD33
U11_regulator (3.3V)
Join 1-2
J23 DC Power jack ( 9~18V)
GND
-
VCC
J24 AVDD
Open
Open
-
-
J25 UART
J26
17
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EVALUATION BOARD MANUAL
S3F401F_BD_UM_REV1.00
3.3 SWITCHES
SW#
Description
ON: Port 0.0~0.7 connects to 7segment
ON: Port 1.9~1.12 connects to latch
LOW signal is generated by SW3
HIGH signal is generated by SW4
Reset signal is generated by SW6
Power on switch
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
SW9
SW10
SW11
SW12
7-Segment
Latch
INT7
INT8
RESET
Power_VIN
SSP16
SSP16
SSP8
Port connects to EEPROM
Port connects to EEPROM
Port connects to EEPROM
Port connects to EEPROM
Port connects to ADC
SSP8
AIN
AIN
Port connects to ADC
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EVALUATION BOARD MANUAL
S3F401F_BD_UM_REV1.00
4. S3F401F-EVB REV 1.0 BOARD SCHEMATICS
SCH-01
SCH-02
SCH-03
SCH-04
SCH-05
SCH-06
SCH-07
SCH-08
SCH-09
SCH-10
SCH-11
EVB TOP Block Diagram
S3F401F Micro-Controller
System Power Generation
Clock & Mode
REV 1.0
REV 1.0
REV 1.0
REV 1.0
REV 1.0
REV 1.0
REV 1.0
REV 1.0
REV 1.0
REV 1.0
REV 1.0
ADC, Interrupt & BUZZER
JTAG Connector
UART Communication
SSP Communication
IMC & ENC Signal
7-Segment Display
Expansion Connector
19
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EVALUATION BOARD MANUAL
S3F401F_BD_UM_REV1.00
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EVALUATION BOARD MANUAL
S3F401F_BD_UM_REV1.00
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S3F401F_BD_UM_REV1.00
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S3F401F_BD_UM_REV1.00
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S3F401F_BD_UM_REV1.00
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S3F401F_BD_UM_REV1.00
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S3F401F_BD_UM_REV1.00
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S3F401F_BD_UM_REV1.00
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S3F401F_BD_UM_REV1.00
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S3F401F_BD_UM_REV1.00
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S3F401F_BD_UM_REV1.00
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