Renesas Network Card SH7145F User Guide

APPLICATION NOTE  
SH7145F  
Asynchronous Serial Data Transmission/Reception  
Summary  
The SH7144 series is a single-chip microprocessor based on the SH-2 RISC (Reduced Instruction  
Set Computer) CPU core and integrating a number of peripheral functions.  
This application note describes asynchronous serial data transmission/reception using the SCI  
(Serial Communication Interface) module of the SH7145F. It is intended to be used as reference  
by users designing software applications.  
The program examples contained in this application note have been tested. However, operation  
should be confirmed before using them in an actual application.  
Device for Which Operation Has Been Confirmed  
SH7145F  
Contents  
1. Specifications ................................................................................................ 2  
2
Functions Used ............................................................................................. 3  
3. Operation....................................................................................................... 6  
4. Software ........................................................................................................ 8  
5. Flowcharts..................................................................................................... 11  
6. Program Listing............................................................................................. 14  
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SH7145F  
Asynchronous Serial Data Transmission/Reception  
2
Functions Used  
In this task example the SCI (Serial Communication Interface) is used to perform asynchronous  
serial data transmission/reception. Figure 2 shows a block diagram of channel 1 (ch1) of the SCI  
module. The functions of the elements shown in figure 2 are described below.  
SCI0 synchronous serial transfer function block  
On-chip  
Transfer rate generator  
peripheral clock  
Pφ/128  
SCI1 clock I/O pin  
(SCK1)  
Pφ/32  
Baud rate generator  
Pφ/8  
Pφ1  
Bit rate register 1  
(BRR_1)  
External  
clock  
Clock  
Transmit/receive operation control settings  
Serial mode register 1  
(SMR_1)  
Interrupt  
requests  
TEI_1  
Serial control register 1  
(SCR_1)  
Transmit/receive  
control circuit  
TXI_1  
RXI_1  
Serial status register 1  
(SSR_1)  
ERI_1  
Serial direction control register 1  
(SDCR_1)  
Transmit data control  
SCI1 transmit data  
output pin  
(TXD1)  
Transmit shift register 1  
(TSR_1)  
Transmit data register 1  
(TDR_1)  
Receive data control  
SCI1 receive data  
input pin  
(RXD1)  
Receive shift register 1  
(RSR_1)  
Receive data register 1  
(RDR_1)  
Figure 2 SCI (ch1) Block Diagram  
Asynchronous Mode  
Serial data communication is performed using synchronization by character unit. This allows  
serial communication with a standard dedicated asynchronous communication chip such as a  
Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication  
Interface Adapter (ACIA). In addition, the asynchronous mode supports serial communication  
among multiple processors (multiprocessor communication function).  
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SH7145F  
Asynchronous Serial Data Transmission/Reception  
On-Chip Peripheral Clock Pφ  
This is the reference clock for operation of on-chip peripheral functions. The clock signal is  
generated by a clock oscillator.  
Receive Shift Register (RSR_1)  
This register is used to receive serial data. Serial data is input to RSR_1 from the RxD_1 pin.  
When one frame of data has been received, it is automatically transferred to the receive data  
register (RDR_1). RSR_1 cannot be accessed by the CPU.  
Receive Data Register (RDR_1)  
Received data is stored in this 8-bit register. When one frame of data has been received, it is  
automatically transferred from RSR_1. RSR_1 and RDR_1 are in a double-buffer  
configuration, allowing continuous reception of data. RDR_1 is a receive-only register, so it  
can only be read by the CPU.  
Transmit Shift Register (TSR_1)  
This register is used to transmit serial data. In order to transmit data, the data is first  
transferred from the transmit data register (TDR_1) to TSR_1. Then the transmit data is  
output from the TxD_1 pin. TSR_1 cannot be accessed directly by the CPU.  
Transmit Data Register (TDR_1)  
Data to be transmitted is stored in this 8-bit register. When it is detected that TDR_1 is empty,  
data that has been written to TDR_1 is automatically transferred to TSR_1. TDR_1 and  
TSR_1 are in a double-buffer configuration. This allows data to be transferred to TSR_1 after  
one frame of data has been transmitted and the next frame of data is still being written to  
TDR_1, making possible continuous transmission of data. It is always possible to read or  
write to the TDR from the CPU, but before writing to the TDR it should be confirmed that the  
value of the TDRE bit in the serial status register (SSR_1) is 1.  
Serial Mode Register (SMR_1)  
This 8-bit register is used to select the serial data communication format and the clock source  
for the on-chip baud rate generator.  
Serial Control Register (SCR_1)  
This register is used for transmit and receive control, interrupt control, and to select the  
transmit and receive clock source.  
Serial Status Register (SSR_1)  
This register comprises the SCI1 status flag and the transmit and receive multiprocessor bits.  
TDRE, RDRF, ORER, PER, and FER can be cleared only.  
Serial Direction Control Register (SDCR_1)  
This register is used to select whether the LSB or MSB is first. For 8-bit communication  
either LSB-first or MSB-first may be selected, but LSB-first should be used for 7-bit  
communication.  
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Bit Rate Register (BRR_1)  
This 8-bit register is used to adjust the bit rate. The SCI has independent baud rate generators  
for the individual channels, allowing different bit rates to be set for each. See the hardware  
manual for details on setting values, execution rate relationships, etc.  
Table 2 shows the function allocations for the task example.  
Table 2 Function Allocations  
Function  
TXD1  
Classification  
Pin  
Function Allocation  
Channel 1 transmit data output pin  
Channel 1 transmit data input pin  
Sets communication format to asynchronous mode  
Enables transmit operation  
RXD1  
Pin  
SMR_1  
SCR_1  
SSR_1  
SDCR_1  
BRR_1  
TSR_1  
TDR_1  
RSR_1  
RDR_1  
SCI1  
SCI1  
SCI1  
Status flag showing SCI1 operation status  
Specifies LSB-first  
SCI1  
SCI1  
Sets communication bit rate  
SCI1  
Register for transmitting serial data  
Register for storing transmit data  
Register for receiving serial data  
Register for storing receive data  
SCI1  
SCI1  
SCI1  
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3. Operation  
Figure 3 shows the operation of asynchronous mode data transmission in the task example. To  
help explain figure 3, table 3 lists the software and hardware processing that is performed.  
(1)  
(2)  
(3)  
(4)  
(6)  
(7) (8)  
(9)  
(10)  
(11)  
(12)(13) (15)  
(14)  
(5)  
Data  
bits  
Start  
bit  
Stop Start  
bit bit  
TxD1  
(pin)  
Data bits D0 to D7  
0
0
1
RDRF  
(SSR_1 bit)  
Receive operation  
Transmit operation  
TDR_1  
(register)  
TSR_1  
(register)  
Start  
bit  
TXD1  
(pin)  
Data bits D0 to D7  
0
TDRE  
(SSR_1 bit)  
Notes: 1. The start bit, transmit data, parity bit, and stop bit are output, in that order, from the TxD1 pin.  
2. To perform continuous reception, read data transferred to RDR until reception of next data is  
complete.  
Figure 3 Data Transmission Operation  
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Table 3 Processing  
Software Processing  
Hardware Processing  
(1)  
RSR_1 receives serial data and transfers it  
to RDR_1  
(2)  
(3)  
(4)  
(5)  
(6)  
(7)  
(8)  
Set RDRF flag in SSR_1 to 1  
Read data from RDR_1  
Clear RDRF flag in SSR_1 to 0  
Write receive data to TDR_1  
Clear TDRE flag in SSR_1 to 1  
Transfer data from TDR_1 to TSR_1  
Set TDRE flag in SSR_1 to 1 and output  
transmit data from pin TXD1  
(9)  
RSR_1 receives serial data and transfers it  
to RDR_1  
(10)  
(11)  
(12)  
(13)  
(14)  
(15)  
(16)  
Set RDRF flag in SSR_1 to 1  
Read data from RDR_1  
Clear RDRF flag in SSR_1 to 0  
Write receive data to TDR_1  
Clear TDRE flag in SSR_1 to 1  
Transfer data from TDR_1 to TSR_1  
Repeat  
Repeat  
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4. Software  
(1) Module Descriptions  
Table 4 lists the modules used in the task example.  
Table 4 Module Descriptions  
Module  
Label  
Function  
Main routine  
SCI routine  
main  
Calls modules  
init_sci  
rcv_sci  
trans_sci  
err_int  
Initial settings of SCI1  
Receives serial data  
Transmits serial data  
Handles receive errors  
Receive routine  
Transmit routine  
Error handling  
(2) Argument Descriptions  
Table 5 lists the arguments used in the task example.  
Table 5 Argument Descriptions  
Argument  
Function  
Module  
Rev_data[0–2]  
trans_data  
Stores SCI_1 receive data  
Transmits data from SCI_1  
Receive routine  
Transmit routine  
(3) On-Chip Register Descriptions  
Table 6 lists the on-chip registers used in the task example. The set values shown are the values  
used in the task example and differ from the initial settings.  
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Table 6 On-Chip Register Descriptions  
Register  
Set Value  
Function  
Module standby control register 1  
Bit  
MSTCR1  
SCR_1  
MSTP17  
0
SCI1 standby control bit  
Standby cancelled when MSTP17 = 0  
Serial control register 1 (SCI_1)  
H'70  
Transmit and receive control, interrupt control, transmit and receive  
clock source control  
TIE  
RIE  
TE  
0
1
1
1
0
Transmit interrupt enable  
TXI interrupt requests enabled when set to 1  
Receive interrupt enable  
RXI and ERI interrupt requests enabled when set to 1  
Transmit enable  
Transmit operations enabled when set to 1  
Receive enable  
RE  
Receive operations enabled when set to 1  
Multiprocessor interrupt enable  
MPIE  
(In asynchronous mode, enabled when MP = 1 in SMR)  
In the task example, disabled because MP = 0  
Transmit end interrupt enable  
TEIE  
0
TEI interrupt requests enabled when set to 1  
Clock enable 1, 0  
CKE1  
CKE2  
0
0
Selects clock source and SCK pin function  
In the task example, clock source is on-chip clock and SCK pin is not  
used  
SMR_1  
H'00  
Serial mode register 1  
Selects communication format and the clock source for on-chip baud  
rate generator  
C/A  
0
0
0
0
0
Communication mode  
Asynchronous mode when cleared to 0  
CHR  
PE  
Character length (enabled in asynchronous mode only)  
8-bit transmission and reception when 0  
Parity enable (enabled in asynchronous mode only)  
No-parity transmission and reception when 0  
Parity mode (enabled in asynchronous mode when PE = 1)  
(In this example PE = 0 and this bit is disabled)  
Stop bit length (enabled in asynchronous mode only)  
1-stop-bit transmission and reception when 0  
O/E  
STOP  
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Register  
Set Value  
Function  
Bit  
SMR_1  
MP  
0
Multiprocessor mode (enabled in asynchronous mode only)  
Multiprocessor communication disabled when 0  
Clock select 1, 0  
CKS1  
0
0
CKS2  
When value is 00, Pφ clock selected using on-chip baud rate generator  
as clock source  
BRR_1  
H'40  
H'F2  
Bit rate register 1  
8-bit register for adjusting bit rate  
Serial direction control register 1  
DIR bit (bit 3) selects LSB-first or MSB-first  
In task example, DIR = 0 (LSB-first)  
Serial status register 1  
SDCR_1  
SSR_1  
H'xx  
Comprises SCI1 status flag and transmit and receive multiprocessor bits  
Only 0 may be written to the status flag, to clear it  
Transmit data register empty (status flag)  
Receive data register full (status flag)  
Overrun error (status flag)  
TDRE  
*
*
*
*
*
*
0
0
0
1
0
1
RDRF  
ORER  
FER  
Framing error (status flag)  
PER  
Parity error (status flag)  
TEND  
Transmit end (status flag)  
MPB  
Multiprocessor bit  
MPBT  
PA4MD1  
PA4MD0  
PA3MD1  
PA3MD0  
Multiprocessor bit transfer  
PACRL2  
Port A control register L2  
Function setting for port A multiplex pin (TXD1)  
Port A control register L2  
Function setting for port A multiplex pin (RXD1)  
*: Can only be cleared to 0. Setting to 1 is performed by hardware.  
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5. Flowcharts  
(1) Main Routine  
main()  
init_sci()  
rcv_sci()  
rcv_sci()  
rcv_sci()  
Initialize SCI module  
Receive 1st byte of data  
Receive 2nd byte of data  
Receive 3rd byte of data  
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(2) SCI1 Initialize Routine  
init_sci()  
Cancel SCI1 module standby status  
Clear to 0 bits TIE, RIE, TE, RE, MPIE,  
and TEIE in SCR_0  
Select on-chip clock as clock source  
using CKE1 and CKE0 in SCR_0  
Using SMR_1, select asynchronous  
mode, 8 data bits, no parity, 1 stop bit,  
and Pφ as baud rate generator clock  
source  
Using BRR_1, set communication  
speed to 19,200 bps  
Using DIR bit in SDCR_1, select  
LSB-first communication  
No  
Wait minimum  
1-bit transfer time  
Yes  
Using SCR_1, enable ERI interrupt  
Using PACRL2, set PA3 (pin 133) to  
RXD function and PA4 (pin 134)  
to RXD function  
Set bits TE and RE in SCR_1 to 1 to  
enable transmit operation and receive  
operation  
RTE  
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(3) Data Receive Routine  
rcv_sci()  
Wait until  
No  
RDR_1 finishes receiving  
data  
Yes  
Read receive data from RDR_1 and  
store it in on-chip RAM  
Clear RDRF flag in SSR_1 to 0  
Transmit receive data without  
modification  
RTE  
(4) Data Transfer Routine  
trans_sci()  
Wait until  
No  
possible to write to  
TDR_1  
Yes  
Write transmit data to TDR_1  
Clear TDRE bit in SSR_1 to 0  
RTE  
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6. Program Listing  
/**************************************************************/  
/* SH7145F Application Note  
/*  
/* Function  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
/*  
/*  
:SCI1  
/* External input clock  
/* Internal CPU clock  
/* Internal peripheral clock : 25MHz  
/*  
: 12.5MHz  
: 50MHz  
/* Written  
:2003/7  
Rev.1.0  
/**************************************************************/  
#include "iodefine.h"  
#include <machine.h>  
/*------------ Symbol Definition ----------------------------------------------*/  
#define COUNT 3  
/*------------ Function Definition --------------------------------------------*/  
void main(void);  
void init_sci(void);  
unsigned char rcv_sci(unsigned char);  
void trans_sci(char);  
void err_int(void);  
void dummy_f(void);  
/*------------ RAM allocation Definition --------------------------------------*/  
volatile unsigned char Rev_data[COUNT];  
/**************************************************************/  
/* main Program  
*/  
/**************************************************************/  
void main( void )  
{
unsigned char i = 0;  
init_sci();  
/* Initialize SCI  
*/  
i = rcv_sci(i);  
i = rcv_sci(i);  
i = rcv_sci(i);  
while(1);  
/* Receive 1st byte of serial data */  
/* Receive 2nd byte of serial data */  
/* Receive 3rd byte of serial data */  
/* LOOP  
*/  
}
/**************************************************************  
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Function : init_sci  
Operation : Initialize serial (sci1)  
Asynchronous receive operation  
-Data  
-Stop bit  
: 8bit  
: 1bit  
-Parity bit : No  
**************************************************************/  
void init_sci(void)  
{
unsigned long i;  
P_STBY.MSTCR1.BIT.MSTP17 = 0;  
/* disable SCI1 standby mode  
*/  
/* Initialize SCI Asynchronous mode *  
P_SCI1.SCR_1.BYTE &= 0x03 ;  
P_SCI1.SCR_1.BIT.CKE = 0;  
*/  
/* clear TIE,RIE,TE,RE,MPIE,TEIE  
/* clock:internal,SCK:output  
/* 8bit,No parity,1stop bit  
/* Asynchronous mode  
/* data length 8bits  
/* No parity  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
P_SCI1.SMR_1.BYTE = 0x00;  
//  
//  
//  
//  
//  
//  
CA = 0;  
CHR = 0;  
PE = 0;  
OE = 0;  
STOP = 0;  
CKS = 0;  
/* (=0)even parity  
/* 1 stop bit  
/* clock source=Pφ(25MHz)  
*/  
P_SCI1.BRR_1 = 40;  
P_SCI1.SDCR_1.BIT.DIR = 0;  
/* 19200bps@25MHz(Peripheral)  
/* LSB first send  
*/  
*/  
for( i=0; i < 0x0300 ; i++);  
/* Wait 1bit  
*/  
P_SCI1.SCR_1.BIT.TIE = 0;  
P_SCI1.SCR_1.BIT.RIE = 0;  
/* TXI1 interrupt disable  
/* RXI1,ERI interrupt disable  
*/  
*/  
/* Initialize SCI1 PORT  
*/  
P_PORTA.PACRL2.BIT.PA4MD = 1;  
P_PORTA.PACRL2.BIT.PA3MD = 1;  
/* set TXD1(PA4:134pin@SH7145)  
/* set RXD1(PA3:133pin@SH7145)  
*/  
*/  
P_SCI1.SCR_1.BYTE |= 0x30;  
/* TE=RE=1,Transmit and Receive Enable */  
}
/******************************************************************************/  
/* Function  
/* Operation  
/* Argument  
: rcv_sci  
*/  
*/  
*/  
*/  
: Serial data receive and send function calls  
: None  
/* Value returned : None  
/******************************************************************************/  
unsigned char rcv_sci(unsigned char rev_count)  
{
while(P_SCI1.SSR_1.BIT.RDRF == 0);  
/* Wait until reception finishes */  
Rev_data[rev_count] = P_SCI1.RDR_1;  
/* get receive data  
*/  
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P_SCI1.SSR_1.BIT.RDRF = 0;  
trans_sci(Rev_data[rev_count]);  
rev_count++ ;  
/* Clear RDRF  
*/  
*/  
*/  
/* Transmit receive data  
/* Increment storage address  
return(rev_count);  
}
/************************************************************************/  
/* Function  
/* Operation  
/* Argument  
: trans_sci  
: Write 1 character to serial output  
: trans_data  
*/  
*/  
*/  
*/  
/* Value returned : None  
/************************************************************************/  
void trans_sci(char tarans_data) {  
while(!(P_SCI1.SSR_1.BYTE & 0x80)){ /* Wait until data can be written to TDR */  
;
/* (until TDRE is set to 1)  
*/  
}
P_SCI1.TDR_1 = (unsigned char)trans_data; /* Write data to TDR  
*/  
*/  
P_SCI1.SSR_1.BYTE &= 0x7F;  
/* Clear flag, transmit  
}
/**************************************  
Interrupt handling  
**************************************/  
#pragma interrupt(err_int)  
void err_int(void)  
{
if(P_SCI1.SSR_1.BIT.ORER == 1){  
P_SCI1.SSR_1.BIT.ORER = 0;  
}
/* Overrun error  
/* ORER flag clear  
*/  
*/  
if(P_SCI1.SSR_1.BIT.FER == 1){  
P_SCI1.SSR_1.BIT.FER = 0;  
}
/* Framing error  
/* FER flag clear  
*/  
*/  
if(P_SCI1.SSR_1.BIT.PER == 1){  
/* Parity error  
/* PER flag clear  
*/  
*/  
P_SCI1.SSR_1.BIT.PER = 0;  
}
}
#pragma interrupt(dummy_f)  
void dummy_f(void)  
{
/*  
Other Interrupt  
*/  
}
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6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in  
whole or in part these materials.  
7. If these products or technologies are subject to the Japanese export control restrictions, they must  
be exported under a license from the Japanese government and cannot be imported into a country  
other than the approved destination.  
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the  
country of destination is prohibited.  
8. Please contact Renesas Technology Corp. for further details on these materials or the products  
contained therein.  
REJ06B0357-0100O/Rev.1.00  
March 2004  
Page 17 of 17  
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