Philips Stereo Amplifier TDA8950 User Manual

TDA8950

2 × 150 W class-D power ampliﬁer

Rev. 01 — 9 September 2008

Preliminary data sheet

1. General description

The TDA8950 is a high efﬁciency class-D audio power ampliﬁer. The typical output power

is 2 × 150 W with a speaker load impedance of 4 Ω.

The TDA8950 is available in the HSOP24 power package and DBS23P power package.

The ampliﬁer operates over a wide supply voltage range from ±12.5 V to ±40 V and

consumes a low quiescent current.

2. Features

I Pin compatible with TDA8920B for both HSOP24 and DBS23P packages

I Symmetrical high operating supply voltage range from ±12.5 V to ±40 V

I Stereo full differential inputs, usable as stereo Single-Ended (SE) or mono Bridge-Tied

Load (BTL) ampliﬁer

I High output power at typical applications:

N SE 2 × 150 W, R_L= 4 Ω (V_P= ±37 V)

N SE 2 × 170 W, R_L= 4 Ω (V_P= ±39 V)

N SE 2 × 100 W, R_L= 6 Ω (V_P= ±37 V)

N BTL 1 × 300 W, R_L= 8 Ω (V_P= ±37 V)

I Low noise in BTL due to BD-modulation

I Smooth pop noise-free start-up and switch down

I Zero dead time Pulse Width Modulation (PWM) output switching

I Fixed frequency

I Internal or external clock switching frequency

I High efﬁciency

I Low quiescent current

I Advanced protection strategy: voltage protection and output current limiting

I Thermal foldback

I Fixed gain of 30 dB in SE and 36 dB in BTL

I Full short-circuit proof across load

3. Applications

I DVD

I Mini and micro receiver

I Home Theater In A Box (HTIAB) system

I High power speaker system

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TDA8950

NXP Semiconductors

2 × 150 W class-D power ampliﬁer

6. Block diagram

VDDA

3 (20)

n.c.

10 (4)

STABI PROT

18 (12) 13 (7)

VDDP2

23 (16)

VDDP1

14 (8)

15 (9)

BOOT1

OUT1

9 (3)

8 (2)

IN1M

IN1P

DRIVER

HIGH

PWM

MODULATOR

INPUT

STAGE

SWITCH1

CONTROL

AND

16 (10)

HANDSHAKE

DRIVER

LOW

mute

11 (5)

7 (1)

n.c.

OSC

STABI

SSP1

TDA8950TH

(TDA8950J)

TEMPERATURE SENSOR

CURRENT PROTECTION

VOLTAGE PROTECTION

OSCILLATOR

MANAGER

6 (23)

DDP2

22 (15)

MODE

mute

BOOT2

OUT2

2 (19)

SGND

DRIVER

HIGH

CONTROL

AND

21 (14)

5 (22)

4 (21)

SWITCH2

IN2P

IN2M

HANDSHAKE

INPUT

STAGE

PWM

DRIVER

LOW

MODULATOR

1 (18)

12 (6)

n.c.

24 (17)

VSSD

19 (-)

n.c.

17 (11)

VSSP1

20 (13)

001aah653

VSSA

VSSP2

The pin numbers in parenthesis refer to type number TDA8950J.

Fig 1. Block diagram

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2 × 150 W class-D power ampliﬁer

7. Pinning information

7.1 Pinning

OSC

IN1P

IN1M

n.c.

PROT

VDDP1

BOOT1

OUT1

VSSP1

STABI

VSSP2

OUT2

BOOT2

VDDP2

VSSD

VSSA

SGND

VDDA

IN2M

VSSD

VDDP2

BOOT2

OUT2

VSSA

SGND

VDDA

IN2M

IN2P

MODE

OSC

IN1P

IN1M

n.c.

TDA8950J

VSSP2

n.c.

TDA8950TH

STABI

VSSP1

OUT1

BOOT1

VDDP1

PROT

n.c.

IN2P

n.c.

MODE

001aah654

001aah655

Fig 2. Pin conﬁguration TDA8950TH

Fig 3. Pin conﬁguration TDA8950J

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2 × 150 W class-D power ampliﬁer

7.2 Pin description

Table 3.

Symbol

Pin description

Description

TDA8950TH TDA8950J

VSSA

SGND

VDDA

IN2M

negative analog supply voltage

signal ground

positive analog supply voltage

negative audio input for channel 2

positive audio input for channel 2

IN2P

MODE

mode selection input: Standby, Mute or Operating

mode

OSC

oscillator frequency adjustment or tracking input

positive audio input for channel 1

negative audio input for channel 1

not connected

IN1P

IN1M

n.c.

not connected

n.c.

not connected

PROT

VDDP1

BOOT1

OUT1

VSSP1

STABI

n.c.

decoupling capacitor for protection (OCP)

positive power supply voltage for channel 1

bootstrap capacitor for channel 1

PWM output from channel 1

negative power supply voltage for channel 1

decoupling of internal stabilizer for logic supply

not connected

VSSP2

OUT2

BOOT2

VDDP2

VSSD

negative power supply voltage for channel 2

PWM output from channel 2

bootstrap capacitor for channel 2

positive power supply voltage for channel 2

negative digital supply voltage

8. Functional description

8.1 General

The TDA8950 is a two-channel audio power ampliﬁer using class-D technology.

The audio input signal is converted into a digital pulse width modulated signal via an

analog input stage and PWM modulator, see Figure 1. To enable the output power

transistors to be driven, this digital PWM signal is applied to a control and handshake

block and driver circuits for both the high side and low side. In this way a level shift is

performed from the low power digital PWM signal (at logic levels) to a high power PWM

signal that switches between the main supply lines.

A 2nd-order low-pass ﬁlter converts the PWM signal to an analog audio signal across the

loudspeakers.

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2 × 150 W class-D power ampliﬁer

The TDA8950 one-chip class-D ampliﬁer contains high power switches, drivers, timing

and handshaking between the power switches and some control logic. Also an advanced

protection strategy is implemented which contains several voltage protections,

temperature protections and a maximum current protection to secure maximum system

robustness.

The two audio channels of the TDA8950 each contain a PWM modulator, an analog

feedback loop and a differential input stage. It also contains circuits common to both

channels such as the oscillator, all reference sources, the mode interface and a digital

timing manager.

The TDA8950 contains two independent ampliﬁer channels with high output power, high

efﬁciency, low distortion and low quiescent current. The ampliﬁer channels can be

connected in the following conﬁgurations:

• Mono Bridge-Tied Load (BTL) ampliﬁer

• Stereo Single-Ended (SE) ampliﬁers

The ampliﬁer system can be switched to one of three operating modes by pin MODE:

• Standby mode; with a very low supply current

• Mute mode; the ampliﬁers are operational, but the audio signal at the output is

suppressed by disabling the VI-converter input stages

• Operating mode; the ampliﬁers are fully operational

To ensure pop noise-free start-up, the DC output offset voltage is applied gradually to the

output at a level between Mute mode and Operating mode levels. The bias current setting

of the VI converters is related to the voltage on pin MODE; in Mute mode the bias current

setting of the VI converters is zero (VI converters disabled) and in Operating mode the

bias current is at maximum. The time constant required to apply the DC output offset

voltage gradually between Mute and Operating mode levels can be generated via an

RC-network on pin MODE. An example of a switching circuit for driving pin MODE is

illustrated in Figure 4. If the capacitor C is left out of the application, the voltage on pin

MODE will be applied with a much smaller time-constant, which might result in audible

pop noises during start-up (depending on DC output offset voltage and loudspeaker

used).

5 V

standby/

mute

MODE pin

mute/on

SGND

001aab172

Fig 4. Example of mode selection circuit

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2 × 150 W class-D power ampliﬁer

In order to fully charge the coupling capacitors at the inputs, the ampliﬁer will remain

automatically in the Mute mode before switching to the Operating mode. A complete

overview of the start-up timing is given in Figure 5.

audio output

(1)

modulated PWM

MODE

50 %

duty cycle

operating

> 4.2 V

mute

2.2 V < V

< 3 V

MODE

standby

0 V (SGND)

time

100 ms

> 350 ms

50 ms

audio output

(1)

modulated PWM

MODE

50 %

duty cycle

operating

> 4.2 V

mute

2.2 V < V

< 3 V

MODE

standby

0 V (SGND)

time

100 ms

> 350 ms

50 ms

001aah657

(1) First ¹⁄₄pulse down.

Upper diagram: When switching from standby to mute, there is a delay of approximately 100 ms

before the output starts switching. The audio signal is available after V_MODEhas been set to

operating, but not earlier than 150 ms after switching to mute. For pop noise-free start-up it is

recommended that the time constant applied to pin MODE is at least 350 ms for the transition

between mute and operating.

Lower diagram: When switching directly from standby to operating, there is a ﬁrst delay of 100 ms

before the outputs starts switching. The audio signal is available after a second delay of 50 ms. For

pop noise-free start-up it is recommended that the time constant applied to pin MODE is at least

500 ms for the transition between standby and operating.

Fig 5. Timing on mode selection input

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8.2 Pulse width modulation frequency

The output signal of the ampliﬁer is a PWM signal with a carrier frequency that typically

lies between 300 kHz and 400 kHz. Using a 2nd-order LC demodulation ﬁlter in the

application results in an analog audio signal across the loudspeaker. The carrier

frequency is determined by an external resistor R_OSC, connected between pin OSC and

pin VSSA. An optimal setting for the carrier frequency is between 300 kHz and 400 kHz.

Using an external resistor of 30 kΩ on pin OSC, the carrier frequency is set to 345 kHz.

For more details see T a ble 8.

If two or more class-D ampliﬁers are used in the same audio application, it is

recommended that all devices operate at the same switching frequency by using an

external clock circuit.

Due to an internal clock divider:

• The external applied clock frequency must have the double frequency of the output

PWM frequency.

• The duty cycle of the external clock is not critical for product performance.

8.3 Protections

The following protections are included in TDA8950:

• Thermal protections:

– Thermal FoldBack (TFB)

– OverTemperature Protection (OTP)

• OverCurrent Protection (OCP, diagnostic via pin PROT)

• Window Protection (WP)

• Supply voltage protections:

– UnderVoltage Protection (UVP)

– OverVoltage Protection (OVP)

– UnBalance Protection (UBP)

The reaction of the device to the different fault conditions differs per protection.

8.3.1 Thermal protection

In the TDA8950 an advanced thermal protection strategy is implemented. It consists of a

TFB function that gradually reduces the out put power within a certain temperature range.

When temperature is still rising an OTP is implemented which shuts down the device

completely.

8.3.1.1 Thermal FoldBack (TFB)

If the junction temperature T_jexceeds a deﬁned threshold value, the gain is gradually

reduced. This will result in a smaller output signal and less dissipation. Eventually the

temperature will stabilize.

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2 × 150 W class-D power ampliﬁer

TFB is speciﬁed at the temperature value T_{act(th_fold)}where the closed loop voltage gain is

reduced with 6 dB. The range of the TFB is:

T_{act(th_fold)}− 5 °C < T_{act(th_fold)}< T_{act(th_prot)}

For the TDA8950 the value of T_{act(th_fold)}is about +153 °C. For more details see: T a ble 7.

8.3.1.2 OverTemperature Protection (OTP)

If, despite the TFB function, the junction temperature T_jof the TDA8950 continues rising

and exceeds the threshold T_{act(th_prot)}the ampliﬁer will shutdown immediately. The

ampliﬁer resumes switching approximately 100 ms after the temperature drops below

T_{act(th_prot)}

In Figure 6 the thermal behavior is visualized.

Gain

(dB)

30 dB

24 dB

0 dB

T (°C)

− 5°C)

act(th_prot)

act(th_fold)

001aah656

(1) Duty cycle of PWM output modulated according audio input signal.

(2) Duty cycle of PWM output reduced due to TFB.

(3) Ampliﬁer is switched off due to OTP.

Fig 6. Behavior of TFB and OTP

8.3.2 OverCurrent Protection (OCP)

If a short-circuit is applied to one of the demodulated outputs of the ampliﬁer, the OCP will

detect this. If the output current exceeds the maximum of 9.2 A, it is automatically limited

to its maximum value by the OCP protection circuit. The ampliﬁer outputs remain

switching (the ampliﬁer is NOT shut-down completely). If the active current limiting

continues longer than time τ, the TDA8950 shuts down. Activation of current limiting and

the triggering of the OCP are observed at pin PROT.

The ampliﬁer can distinguish between an impedance drop of the loudspeaker and a

low-ohmic short-circuit across the load. In the TDA8950 the impedance threshold (Z_th)

depends on the supply voltage used.

When a short-circuit is made across the load, causing the impedance to drop below the

threshold level (<Z_th), the ampliﬁer is switched off completely and, after a time of 100 ms,

it will try to restart. If the short-circuit condition is still present after this time, the cycle will

be repeated. The average dissipation will be low because of this low duty cycle.

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2 × 150 W class-D power ampliﬁer

Should there be an impedance drop (e.g. due to dynamic behavior of the loudspeaker) the

same protection will be activated. The maximum output current will again be limited to

9.2 A, but the ampliﬁer will not switch-off completely (thus preventing audio holes from

occurring).

The result will be a clipping output signal.

See Section 13.7 for more information on this maximum output current limiting feature.

8.3.3 Window Protection (WP)

The WP checks the conditions at the output terminals of the power stage and is activated:

• During the start-up sequence, when pin MODE is switched from standby to mute. In

the event of a short-circuit at one of the output terminals to pin VDDPn or pin VSSPn

the start-up procedure is interrupted and the TDA8950 waits until the short-circuit to

the supply lines has been removed. Because the test is done before enabling the

power stages, no large currents will ﬂow in an event of short-circuit.

• When the ampliﬁer is completely shut-down due to activation of the OCP because a

short-circuit to one of the supply lines is made, then during restart (after 100 ms) the

WP will be activated. As a result the ampliﬁer will not start-up until the short-circuit to

the supply lines is removed.

8.3.4 Supply voltage protections

If the supply voltage drops below minimum supply voltage, the UVP circuit is activated and

the system will shutdown correctly. If the internal clock is used, this switch-off will be silent

and without pop noise. When the supply voltage rises above the threshold level, the

system is restarted again after 100 ms.

If the supply voltage exceeds maximum supply voltage, the OVP circuit is activated and

the power stages will shutdown. When the supply voltage drops below the threshold level,

the system is restarted again after 100 ms.

An additional UBP circuit compares the positive analog (voltage on pin VDDA) and the

negative analog (voltage on pin VSSA) supply voltage and is triggered if the voltage

difference exceeds a factor of two.

When the supply voltage difference drops below the threshold level, the system is

restarted again after 100 ms.

Example: With a symmetrical supply of ±30 V, the protection circuit will be triggered if the

unbalance exceeds approximately 15 V. See Section 13.7.

In T a ble 4 an overview is given of all protections and their respective effects on the output

signal.

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2 × 150 W class-D power ampliﬁer

Table 4.

Overview of TDA8950 protections

Protection name Complete

shutdown

Restart directly Restart after

Pin PROT

detection

100 ms

TFB^[1]

OTP

OCP

N^[2]

Y^[2]

N^[3]

UVP

OVP

UBP

[1] Ampliﬁer gain will depend on junction temperature and heatsink size.

[2] Only complete shutdown of ampliﬁer if short-circuit impedance is below threshold of 1 Ω. In all other cases

current limiting results in clipping of the output signal.

[3] Fault condition detected during (every) transition between standby-to-mute and during restart after

activation of OCP (short-circuit to one of the supply lines).

8.4 Differential audio inputs

For a high common mode rejection ratio and a maximum of ﬂexibility in the application, the

audio inputs are fully differential.

There are two possibilities:

• For stereo operation it is advised to use the inputs in anti phase and also to connect

the speakers in anti phase (to avoid acoustical phase differences). This construction

has several advantages:

– The peak current in the power supply is minimized

– The supply pumping effect is minimized, especially at low audio frequencies

• For mono BTL operation it is required that the inputs are connected in anti parallel.

The output of one of the channels is inverted and the speaker load is now connected

between the two outputs of the TDA8950. In principle the output power to the speaker

can be signiﬁcantly boosted to two times the output power in single ended stereo.

The input conﬁguration for a mono BTL application is illustrated in Figure 7.

OUT1

IN1P

IN1M

SGND

IN2P

IN2M

OUT2

power stage

mbl466

Fig 7.

Input conﬁguration for mono BTL application

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9. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

Unit

V_P

supply voltage

non-operating mode; V_DD− V_SS

maximum output current limiting

I_ORM

repetitive peak

output current

9.2

T_stg

storage temperature

ambient temperature

junction temperature

−55

−40

+150

+85

150

°C

T_amb

T_j

V_MODE

voltage on pin

MODE

referenced to SGND

V_OSC

V_I

voltage on pin OSC

SGND

+ 6

input voltage

referenced to SGND; pin IN1P; IN1M;

IN2P and IN2M

−5

V_PROT

V_esd

voltage on pin PROT referenced to voltage on pin VSSD

electrostatic

discharge voltage

Human Body Model (HBM);

pin VSSP1 with respect to other pins

−1800 +1800

HBM; all other pins

−2000 +2000

Machine Model (MM); all pins

Charged Device Model (CDM)

−200

−500

+200

+500

I_q(tot)

total quiescent

current

Operating mode; no load; no ﬁlter; no

RC-snubber network connected

10. Thermal characteristics

Table 6.

Symbol

R_th(j-a)

Thermal characteristics

Parameter

Conditions

Typ

Unit

thermal resistance from junction to ambient in free air

thermal resistance from junction to case

K/W

R_th(j-c)

1.1

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11. Static characteristics

Table 7.

Static characteristics

V_P= ±35 V; f_osc= 345 kHz; T_amb= 25 °C; unless otherwise speciﬁed.

Symbol

Supply

V_P

Parameter

Conditions

Min

Typ

Max

Unit

[1]

supply voltage

±12.5 ±35

±40

V_P(ovp)

V_P(uvp)

I_q(tot)

overvoltage protection supply voltage non-operating; V_DD− V_SS

undervoltage protection supply voltage V_DD− V_SS

total quiescent current

Operating mode; no load; no

ﬁlter; no RC-snubber network

connected

I_stb

standby current

480

600

µA

Mode select input; pin MODE

[2]

[2][3]

V_MODE

voltage on pin MODE

referenced to SGND

Standby mode

Mute mode

6.0

0.8

3.0

6.0

150

2.2

4.2

Operating mode

V_I= 5.5 V

I_I

input current

110

µA

Audio inputs; pins IN1M, IN1P, IN2P and IN2M

V_Iinput voltage

Ampliﬁer outputs; pins OUT1 and OUT2

V_O(offset)output offset voltage

[2]

DC input

SE; mute

±15

[4]

SE; operating

BTL; mute

±150

±21

BTL; operating

±210

Stabilizer output; pin STABI

V_O(STABI)

output voltage on pin STABI

mute and operating; with

respect to VSSP1

9.3

9.8

10.3

Temperature protection

T_{act(th_prot)}thermal protection activation

temperature

154

153

°C

[5]

T_{act(th_fold)}thermal foldback activation

temperature

closed loop SE voltage gain

reduced with 6 dB

°C

[1] The circuit is DC adjusted at V_P= ±12.5 V to ±42.5 V.

[2] With respect to SGND (0 V).

[3] The transition between Standby and Mute mode has hysteresis, while the slope of the transition between Mute and Operating mode is

determined by the time-constant of the RC-network on pin MODE; see Figure 8.

[4] DC output offset voltage is gradually applied to the output during the transition between the Mute and Operating modes. The slope

caused by any DC output offset is determined by the time-constant of the RC-network on pin MODE.

[5] At a junction temperature of approximately T_{act(th_fold)}− 5 °C the gain reduction will commence and at a junction temperature of

approximately T_{act(th_prot)}the ampliﬁer switches off.

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slope is directly related to the time-constant

of the RC network on the MODE pin

(V)

O(offset)(on)

Standby

Mute

O(offset)(mute)

0.8

2.2

3.0

4.2

5.5

(V)

MODE

coa021

Fig 8.

Behavior of mode selection pin MODE

12. Dynamic characteristics

12.1 Switching characteristics

Table 8.

Dynamic characteristics

V_P= ±35 V; T_amb= 25 °C; unless otherwise speciﬁed.

Symbol Parameter

Internal oscillator

Conditions

Min

Typ

Max

Unit

f_osc(typ)

typical oscillator

frequency

R_OSC= 30.0 kΩ

325

250

345

365

450

kHz

f_osc

oscillator frequency

External oscillator or frequency tracking

V_OSCvoltage on pin OSC

SGND + 4.5 SGND + 5

SGND + 6 V

V_trip(OSC)trip voltage on pin

OSC

SGND + 2.5 -

[1]

f_track

tracking frequency

250

450

kHz

[1] When using an external oscillator, the f_osc(ext)frequency (500 kHz minimum, 900 kHz maximum) will result

in a PWM frequency f_track(250 kHz minimum, 450 kHz maximum) due to the internal clock divider. See

Section 8.2.

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12.2 Stereo and dual SE application characteristics

Table 9.

Dynamic characteristics

V_P= ±35 V; R_L= 4 Ω; f_i= 1 kHz; f_osc= 345 kHz; R_sL< 0.1 Ω^[1]; T_amb= 25 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min Typ Max Unit

[2]

P_o

output power

L = 22 µH; C = 680 nF; T_j= 85 °C

R_L= 4 Ω; THD = 0.5 %; V_P= ±37 V

R_L= 4 Ω; THD = 10 %; V_P= ±37 V

R_L= 6 Ω; THD = 10 %; V_P= ±37 V

R_L= 4 Ω; THD = 10 %; V_P= ±39 V

P_o= 1 W; f_i= 1 kHz

100

150

100

170

[3]

THD

total harmonic distortion

0.05 -

P_o= 1 W; f_i= 6 kHz

G_v(cl)

closed-loop voltage gain

SVRR

supply voltage ripple rejection

between pin VDDPn and SGND

operating; f_i= 100 Hz

operating; f_i= 1 kHz

mute; f_i= 100 Hz

[4]

standby; f_i= 100 Hz

between pin VSSPn and SGND

operating; f_i= 100 Hz

operating; f_i= 1 kHz

mute; f_i= 100 Hz

120

[4]

115

160

kΩ

µV

standby; f_i= 100 Hz

between the input pins and SGND

operating; R_s= 0 Ω

Z_i

input impedance

[5]

[6]

[7]

V_n(o)

output noise voltage

mute

α_cs

channel separation

|∆G_v|

α_mute

CMRR

η_po

voltage gain difference

mute attenuation

[8]

f_i= 1 kHz; V_i= 2 V (RMS)

V_i(CM)= 1 V (RMS)

SE, R_L= 4 Ω

200

190

common mode rejection ratio

output power efﬁciency

SE, R_L= 6 Ω

BTL, R_L= 8 Ω

[9]

R_DSon(hs)high-side drain-source on-state resistance

R_DSon(ls)low-side drain-source on-state resistance

mΩ

[1] R_sLis the series resistance of inductor of low-pass LC ﬁlter in the application.

[2] Output power is measured indirectly; based on R_DSonmeasurement. See also Section 13.3.

[3] THD is measured in a bandwidth of 22 Hz to 20 kHz, using AES17 20 kHz brickwall ﬁlter. Maximum limit is not guaranteed100 % tested.

[4] V_ripple= V_ripple(max)= 2 V (p-p); R_s= 0 Ω. Measured independently between VDDPn and SGND and between VSSPn and SGND.

[5] B = 22 Hz to 20 kHz, using AES17 20 kHz brickwall ﬁlter.

[6] B = 22 Hz to 22 kHz, using AES17 20 kHz brickwall ﬁlter; independent of R_s.

[7] P_o= 1 W; R_s= 0 Ω; f_i= 1 kHz.

[8] V_i= V_i(max)= 1 V (RMS); f_i= 1 kHz.

[9] Leads and bond wires included.

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12.3 Mono BTL application characteristics

Table 10. Dynamic characteristics

V_P= ±35 V; R_L= 8 Ω; f_i= 1 kHz; f_osc= 345 kHz; R_sL< 0.1 Ω ^[1]; T_amb= 25 °C; unless otherwise

speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max Unit

[2]

P_o

output power

L = 22 µH; C = 680 nF;

T_j= 85 °C; R_L= 8 Ω

THD = 10 %; V_P= ±39 V

THD = 10 %; V_P= ±37 V

THD = 0.5 %; V_P= ±37 V

P_o= 1 W; f_i= 1 kHz

340

300

200

0.05

[3]

THD

total harmonic

distortion

P_o= 1 W; f_i= 6 kHz

G_v(cl)

closed-loop voltage

gain

SVRR

supply voltage ripple

rejection

between pin VDDPn and

SGND

[4]

operating; f_i= 100 Hz

operating; f_i= 1 kHz

mute; f_i= 100 Hz

standby; f_i= 100 Hz

120

between pin VSSPn and

SGND

[4]

operating; f_i= 100 Hz

operating; f_i= 1 kHz

mute; f_i= 100 Hz

130

kΩ

standby; f_i= 100 Hz

Z_i

input impedance

measured between the input

pins and SGND

[5]

[6]

[7]

V_n(o)

output noise voltage

operating; R_s= 0 Ω

mute

190

µV

α_mute

mute attenuation

f_i= 1 kHz; V_i= 2 V (RMS)

V_i(CM)= 1 V (RMS)

CMRR common mode

rejection ratio

[1] R_sLis the series resistance of inductor of low-pass LC ﬁlter in the application.

[2] Output power is measured indirectly; based on R_DSonmeasurement. See also Section 13.3.

[3] Total harmonic distortion is measured in a bandwidth of 22 Hz to 20 kHz, using an AES17 20 kHz brickwall

ﬁlter. Maximum limit is guaranteed but may not be 100 % tested.

[4] V_ripple= V_ripple(max)= 2 V (p-p); R_s= 0 Ω.

[5] B = 22 Hz to 20 kHz, using an AES17 20 kHz brickwall ﬁlter. Low noise due to BD modulation.

[6] B = 22 Hz to 20 kHz, using an AES17 20 kHz brickwall ﬁlter; independent of R_s.

[7] V_i= V_i(max)= 1 V (RMS); f_i= 1 kHz.

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13. Application information

13.1 Mono BTL application

When using the power ampliﬁer in a mono BTL application the inputs of both channels

must be connected in parallel and the phase of one of the inputs must be inverted (see

Figure 7). In principle the loudspeaker can be connected between the outputs of the two

single-ended demodulation ﬁlters.

13.2 Pin MODE

For pop noise-free start-up, an RC time-constant must be applied on pin MODE. The

bias-current setting of the VI-converter input is directly related to the voltage on pin

MODE. In turn the bias-current setting of the VI converters is directly related to the DC

output offset voltage. Thus a slow dV/dt on pin MODE results in a slow dV/dt for the

DC output offset voltage, resulting in pop noise-free start-up. A time-constant of 500 ms is

sufﬁcient to guarantee pop noise-free start-up (see also Figure 4, 5 and 8).

13.3 Output power estimation

13.3.1 SE

Maximum output power:

× V × (1 – t

× 0.5 f

)

osc

----------------------------------------------------

min

R + R

+ R

DSon(hs)

(1)

(2)

---------------------------------------------------------------------------------------------------------------------------------

o(0.5%)

Maximum current internally limited to 9.2 A:

V × (1 – t

× 0.5 f

)

osc

min

-------------------------------------------------------------

R + R + R

o( peak)

DSon(hs)

Variables:

• R_L: load impedance

• R_sL: series impedance of the ﬁlter coil

• R_DSon(hs): high-side R_DSonof power stage output DMOS (temperature dependent)

• f_osc: oscillator frequency

• t_min: minimum pulse width (typical 150 ns, temp. dependent)

• V_P: single-sided supply voltage (or 0.5 × (V_DD+ |V_SS|))

• P_{o(0.5 %)}: output power at the onset of clipping

Note that I_o(peak)should be below 9.2 A (Section 8.3.2). I_o(peak)Mis the sum of the current

through the load and the ripple current. The value of the ripple current is dependent on the

coil inductance and voltage drop over the coil.

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13.3.2 Bridge-Tied Load (BTL)

Maximum output power:

× 2V × (1 – t

× 0.5 f

)

osc

-----------------------------------------------------------------

min

R + R + R

DSon(hs)

dson(ls)

(3)

(4)

-------------------------------------------------------------------------------------------------------------------------------------------------

o(0.5%)

Maximum current internally limited to 9.2 A:

2V × (1 – t

× 0.5 f

)

osc

min

------------------------------------------------------------------------------------------

R + (R + R ) + 2R

o( peak)

DSon(hs)

DSon(ls)

Variables:

• R_L: load impedance

• R_sL: series impedance of the ﬁlter coil

• R_DSon(hs): high-side R_DSonof power stage output DMOS (temperature dependent)

• R_DSon(ls): low-side R_DSsonof power stage output DMOS (temperature. dependent)

• f_osc: oscillator frequency

• t_min: minimum pulse width (typical 150 ns, temp. dependent)

• V_P: single-sided supply voltage (or 0.5 × (V_DD+ |V_SS|))

• P_{o(0.5 %)}: output power at the onset of clipping

Note that I_o(peak)Mshould be below 9.2 A (Section 8.3.2). I_o(peak)is the sum of the current

through the load and the ripple current. The value of the ripple current is dependent on the

coil inductance and voltage drop over the coil.

13.4 External clock

For duty cycle independent operation of the device, the external clock input frequency is

internally divided by two. This implies that the frequency of the external clock is as twice

as high as the internal clock (typical 2 × 345 kHz = 690 kHz).

If two or more class-D ampliﬁers are used it is recommended that all devices run at the

same switching frequency. This can be realized by connecting all OCS pins together and

feeding them from an external oscillator. When applying an external oscillator, it is

necessary to force pin OSC to a DC level above SGND. The internal oscillator is disabled

and the PWM modulator will switch with half the externally applied frequency.

The internal oscillator requires an external resistor R_ext(OSC)and capacitor C_OSCbetween

pin OSC and PIN VSSA.

The noise contribution of the internal oscillator is supply voltage dependent. An external

low noise oscillator is recommended for low noise applications running at high supply

voltage.

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13.5 Noise

2 × 150 W class-D power ampliﬁer

Noise should be measured using a high order low-pass ﬁlter with a cut-off frequency of

20 kHz. The standard audio band pass ﬁlters, used in audio analyzers, do not suppress

the residue of the carrier frequency sufﬁciently to ensure a reliable measurement of the

audible noise. Noise measurements should preferably be carried out using AES 17

(‘brickwall’) ﬁlters or an audio precision AUX 0025 ﬁlter, which was designed speciﬁcally

for measuring class-D switching ampliﬁers.

13.6 Heatsink requirements

In many applications it may be necessary to connect an external heatsink to the

TDA8950.

Equation 5 shows the relationship between the maximum power dissipation, before

activation of the TFB, and the total thermal resistance from junction to ambient

T _j– T_amb

R_{th( j – a)}

(5)

-----------------------

P_diss

Power dissipation (P_diss) is determined by the efﬁciency of the TDA8950. The efﬁciency

measured as a function of output power is given in Figure 21. The power dissipation can

be derived as a function of output power (Figure 20).

mbl469

(W)

(1)

(2)

(3)

(4)

(5)

100

(°C)

amb

(1) R_th(j-a)= 5 K/W.

(2) R_th(j-a)= 10 K/W.

(3) R_th(j-a)= 15 K/W.

(4) R_th(j-a)= 20 K/W.

(5) R_th(j-a)= 35 K/W.

Fig 9. De-rating curves for power dissipation as a function of maximum ambient

temperature

In the following example, a heatsink calculation is made for an 8 Ω BTL application with a

±35 V supply:

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The audio signal has a crest factor of 10 (the ratio between peak power and average

power (20 dB)), this means that the average output power is ¹⁄₁₀of the peak power.

In this case, the peak RMS output power level would be the 0.5 % THD level, i.e. 220 W.

The average power would then be ¹⁄₁₀× 220 W = 22 W.

The dissipated power at an output power of 22 W is approximately 5 W.

When the maximum expected ambient temperature is 85 °C, the total R_th(j-a)would then

(140 – 85)

become

= 11 K/W

-------------------------

R_th(j-a)= R_th(j-c)+ R_th(c-h)+ R_th(h-a)

R_th(j-c)= 1.1 K/W

R_th(c-h)= 0.5 K/W to 1 K/W (dependent on mounting)

So the thermal resistance between heatsink and ambient temperature is:

R_th(h-a)= 11 − (1.1 + 1) = 8.9 K/W

The de-rating curves (given for several values of R_th(j-a)) are illustrated in Figure 9. A

maximum junction temperature T_j= 150 °C is taken into account. From Figure 9 the

maximum allowable power dissipation for a given heatsink size can be derived or the

required heatsink size can be determined at a required dissipation level.

13.7 Output current limiting

To guarantee the robustness of the TDA8950, the maximum output current that can be

delivered by the output stage is limited. An advanced OverCurrent Protection (OCP) is

included for each output power switch.

When the current ﬂowing through any of the power switches exceeds the deﬁned internal

threshold current of 9.2 A (e.g. in case of a short-circuit to the supply lines or a

short-circuit across the load), the maximum output current of the ampliﬁer will be

regulated to 9.2 A.

The TDA8950 ampliﬁer can distinguish between a low-ohmic short-circuit condition and

other over current conditions like dynamic impedance drops of the loudspeakers used.

The impedance threshold (Z_th) depends on the supply voltage used.

Depending on the impedance of the short-circuit, the ampliﬁer will react as follows:

• Short-circuit impedance > Z_th: The maximum output current of the ampliﬁer is

regulated to 9.2 A, but the ampliﬁer will not shut-down its PWM outputs. Effectively

this results in a clipping output signal across the load (behavior is very similar to

voltage clipping).

• Short-circuit impedance < Z_th: The ampliﬁer will limit the maximum output current to

9.2 A and at the same time the capacitor on pin PROT is discharged. When the

voltage across this capacitor drops below an internal threshold voltage, the ampliﬁer

will shutdown completely and an internal timer will be started.

A typical value for the capacitor on pin PROT is 220 pF. After a ﬁxed time of 100 ms the

ampliﬁer is switched on again. If the requested output current is still too high, the ampliﬁer

will switch-off again. Thus the ampliﬁer will try to switch to the Operating mode every

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100 ms. The average dissipation will be low in this situation because of this low duty cycle.

If the over current condition is removed the ampliﬁer will remain in Operating mode after

being restarted. In this way the TDA8950 ampliﬁer is fully protected against short-circuit

conditions while at the same time so-called audio holes, as a result of loudspeaker

impedance drops, are eliminated.

13.8 Pumping effects

In a typical stereo half-bridge SE application the TDA8950 is supplied by a symmetrical

voltage (e.g. V_DD= +35 V and V_SS= −35 V). When the ampliﬁer is used in an SE

conﬁguration, a ‘pumping effect’ can occur. During one switching interval, energy is taken

from one supply (e.g. V_DD), while a part of that energy is returned to the other supply line

(e.g. V_SS) and vice versa. When the voltage supply source cannot sink energy, the voltage

across the output capacitors of that voltage supply source will increase and the supply

voltage is pumped to higher levels. The voltage increase caused by the pumping effect

depends on:

• Speaker impedance

• Supply voltage

• Audio signal frequency

• Value of decoupling capacitors on supply lines

• Source and sink currents of other channels

When applying the TDA8950, measures must be taken within the application to minimize

the pumping effect and prevent malfunctions of either the audio ampliﬁer and/or the

voltage supply source. Ampliﬁer malfunction due to the pumping effect can cause

triggering of the UVP, OVP or UBP.

The best remedy against pumping effects is to use the TDA8950 in a mono full-bridge

application or, in the case of stereo half-bridge applications, adapt the power supply (e.g.

increase supply decoupling capacitors).

13.9 Application schematics

Notes for the application schematic:

• A solid ground plane connected to V_SSaround the switching ampliﬁer is necessary to

prevent emission.

• 100 nF capacitors must be placed as close as possible to the power supply pins of the

TDA8950.

• The internal heat spreader of the TDA8950 is internally connected to V_SS

• The external heatsink must be connected to the ground plane.

• Use a thermally conductive, electrically non-conductive, Sil-Pad between the backside

of the TDA8950 and a small external heatsink.

• The differential inputs enable the best system level audio performance with

unbalanced signal sources. In case of hum, due to ﬂoating inputs, connect the

shielding or source ground to the ampliﬁer ground. Jumpers J1 and J2 are open on

set level and are closed on the stand-alone demo board.

• Minimum total required capacitance per power supply line is 3300 µF.

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Rvdda

VDDA

VDDP

SINGLE ENDED

OUTPUT FILTER VALUES

10 Ω

VDDP

GND

LOAD

Llc

Clc

Cvddp

470 µF

2 Ω - 3 Ω

3 Ω - 6 Ω

4 Ω - 8 Ω

10 µH

15 µH

22 µH

1000 nF

680 nF

470 nF

Cvp

22 µF

mode

control

VSSA

Cvssp

470 µF

VDDP VSSP

VSSP

VSSA

Cvddp

Cvp

Cvssp

Rvssa

VDDP

Rosc

30 kΩ

Csn

10 Ω

100 nF

220 pF

Rsn

n.c. n.c. n.c.

10 Ω

Csn

220 pF

Cin

IN1P

IN1N

VSSP

Llc

OUT1

470 nF

Cin

IN1

Rzo

22 Ω

−

Cbo

BOOT1

Clc

470 nF

−

Czo

100 nF

15 nF

SGND

IN2P

TDA8950J

Cbo

BOOT2

OUT2

Cin

−

15 nF

470 nF

Cin

Llc

IN2

IN2N

VDDP

Rzo

22 Ω

−

470 nF

Csn

220 pF

Clc

Czo

100 nF

Rsn

10 Ω

Csn

220 pF

Cvdda

100 nF

Cvssa

Cvddp

100 nF

Cvp

Cvssp

Cprot

100 nF

VSSP

Cstab

470 nF

100 nF

VDDA

VSSA

VDDP VSSP

001aai420

SSP

SSA

Fig 10. Simpliﬁed application diagram

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2 × 150 W class-D power ampliﬁer

13.10 Layout and grounding

To obtain a high-level system performance, certain grounding techniques are essential.

The input reference grounds have to be tied with their respective source grounds and

must have separate tracks from the power ground tracks. This will prevent the large

(output) signal currents from interfering with the small AC input signals. The small-signal

ground tracks should be physically located as far as possible from the power ground

tracks. Supply and output tracks should be as wide as possible for delivering maximum

output power.

R20, R21 ground

R19 FBGND

001aai421

Fig 11. Printed-circuit board layout (quasi-single-sided); components view

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13.11 Curves measured in reference design

001aai422

THD

(%)

(2)

−1

(1)

(3)

−2

−3

−2

−1

(W)

V_P= ±35 V, 2 × 4 Ω SE conﬁguration.

(1) OUT2, f_i= 6 kHz

(2) OUT2, f_i= 1 kHz

(3) OUT2, f_i= 100 Hz

Fig 12. THD as a function of output power, SE conﬁguration with 2 × 4 Ω load

001aai700

THD

(%)

(2)

−1

(1)

−2

(3)

−3

−2

−1

(W)

V_P= ±35 V, 2 × 6 Ω SE conﬁguration.

(1) OUT2, f_i= 6 kHz

(2) OUT2, f_i= 1 kHz

(3) OUT2, f_i= 100 Hz

Fig 13. THD as a function of output power, SE conﬁguration with 2 × 6 Ω load

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001aai423

THD

(%)

(1)

−1

(2)

(3)

−2

−3

−2

−1

(W)

V_P= ±35 V, f_osc= 350 kHz, 1 × 8 Ω BTL conﬁguration.

(1) f_i= 6 kHz

(2) f_i= 1 kHz

(3) f_i= 100 Hz

Fig 14. THD as a function of output power, BTL conﬁguration with 1 × 8 Ω load

001aai424

THD

(%)

−1

(1)

−2

(2)

−3

f (Hz)

V_P= ±35 V, 2 × 4 Ω SE conﬁguration.

(1) OUT2, P_O= 1 W

(2) OUT2, P_O= 10 W

Fig 15. THD as a function of frequency, SE conﬁguration with 2 × 4 Ω load

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001aai701

THD

(%)

−1

(1)

(2)

−2

−3

f (Hz)

V_P= ±35 V, 2 × 6 Ω SE conﬁguration.

(1) OUT2, P_o= 1 W

(2) OUT2, P_o= 10 W

Fig 16. THD as a function of frequency, SE conﬁguration with 2 × 6 Ω load

001aai702

THD

(%)

−1

(1)

(2)

−2

−3

f (Hz)

V_P= ±35 V, 1 × 8 Ω BTL conﬁguration

(1) P_o= 1 W

(2) P_o= 10 W

Fig 17. THD as a function of frequency, BTL conﬁguration with 1 × 8 Ω load

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001aai703

(dB)

−20

−40

−60

−80

−100

f (Hz)

V_P= ±35 V, 2 × 4 Ω SE conﬁguration

For OUT1 and OUT2 for both 1 W and 10 W.

Fig 18. Channel separation as a function of frequency, SE conﬁguration with 2 × 4 Ω load

001aai704

(dB)

−20

−40

−60

−80

−100

f (Hz)

V_P= ±35 V, 2 × 6 Ω SE conﬁguration

For OUT1 and OUT2 for both 1 W and 10 W.

Fig 19. Channel separation as a function of frequency, SE conﬁguration with 2 × 6 Ω load

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001aai705

(W)

(1)

(2)

(3)

100

120

(W)

V_P= ±35 V, f_i= 1 kHz, f_osc= 325 kHz

(1) 2 × 4 Ω SE conﬁguration

(2) 2 × 6 Ω SE conﬁguration

(3) 2 × 8 Ω SE conﬁguration

Fig 20. Power dissipation as function of output power per channel

001aai706

(3)

100

(1)

(2)

(%)

100

120

(W)

V_P= ±35 V, f_i= 1 kHz, f_osc= 325 kHz

(1) 2 × 4 Ω SE conﬁguration

(2) 2 × 6 Ω SE conﬁguration

(3) 2 × 8 Ω SE conﬁguration

Fig 21. Efﬁciency as function of output power per channel

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001aai707

200

180

160

140

120

100

(W)

(1)

(2)

(3)

(4)

12.5

17.5

22.5

27.5

32.5

37.5

(V)

f_i= 1 kHz, f_osc= 325 kHz

Note: inﬁnite heat sink used.

(1) THD = 10 %, 4 Ω

(2) THD = 0.5 %, 4 Ω; THD = 10 %, 6 Ω

(3) THD = 0.5 %, 6 Ω; THD = 10 %, 8 Ω

(4) THD = 0.5 %, 8 Ω

Fig 22. Output power as a function of supply voltage, SE conﬁguration

001aai708

350

(W)

300

250

200

150

100

(1)

(2)

(3)

(4)

12.5

17.5

22.5

27.5

32.5

37.5

(V)

f_i= 1 kHz, f_osc= 325 kHz

Note: inﬁnite heat sink used.

(1) THD = 10 %, 8 Ω

(2) THD = 0.5 %, 8 Ω

(3) THD = 10 %, 16 Ω

(4) THD = 0.5 %, 16 Ω

Fig 23. Output power as function of supply voltage, BTL conﬁguration

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001aai709

v(cl)

(dB)

(1)

(2)

(3)

(4)

f (Hz)

V_P= ±35 V, V_i= 100 mV, R_s= 0 Ω, C_i= 330 pF.

(1) 1 × 8 Ω BTL conﬁguration

(2) 2 × 4 Ω SE conﬁguration

(3) 2 × 6 Ω SE conﬁguration

(4) 2 × 8 Ω SE conﬁguration

Fig 24. Gain as function of frequency, R_s= 0 Ω, C_i= 330 pF

001aai710

−20

SVRR

(dB)

−40

−60

(1)

−80

(2)

−100

−120

(3)

−140

(Hz)

ripple

Ripple on V_DD, short on input pins.

V_P= ±35 V, R_L= 4 Ω, V_ripple= 2 V (p-p).

(1) OUT2, mute

(2) OUT2, on

(3) OUT2, standby

Fig 25. SVRR as function of ripple frequency

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001aai711

−20

SVRR

(dB)

−40

−60

−80

(2)

(1)

−100

(3)

−120

−140

(Hz)

ripple

Ripple on V_SS, short on input pins.

V_P= ±35 V, R_L= 4 Ω, V_ripple= 2 V (p-p).

(1) OUT2, mute

(2) OUT2, on

(3) OUT2, standby

Fig 26. SVRR as function of ripple frequency

001aai712

(V)

0.1

0.01

0.001

0.0001

(1)

(2)

0.00001

0.000001

0.5

1.5

2.5

3.5

4.5

(V)

MODE

V_P= ±35 V

(1) Out1, down

(2) Out1, up

Fig 27. Output voltage as function of mode voltage

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001aai713

−50

mute

(dB)

−60

−70

−80

−90

(1)

(2)

(3)

f (Hz)

V_P= ±35 V, V_i= 2 V (rms), f_osc= 325 kHz

(1) OUT2, 8 Ω

(2) OUT2, 6 Ω

(3) OUT2, 4 Ω

Fig 28. Mute attenuation as function of frequency

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14. Package outline

DBS23P: plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm)

SOT411-1

non-concave

view B: mounting base side

10 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT A

4.6 1.15 1.65 0.75 0.55 30.4 28.0

4.3 0.85 1.35 0.60 0.35 29.9 27.5

12.2

11.8

10.15 6.2 1.85 3.6 14 10.7 2.4

9.85 5.8 1.65 2.8 13 9.9 1.6

1.43

0.78

2.1

1.8

2.54 1.27 5.08

4.3

0.6 0.25 0.03 45°

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

98-02-20

02-04-24

SOT411-1

Fig 29. Package outline SOT411-1 (DBS23P)

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HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height

SOT566-3

pin 1 index

(A )

detail X

w M

10 mm

scale

DIMENSIONS (mm are the original dimensions)

max.

(1)

(2)

UNIT

8°

0°

+0.08 0.53 0.32

−0.04 0.40 0.23

16.0 13.0 1.1 11.1 6.2

15.8 12.6 0.9 10.9 5.8

2.9

2.5

14.5 1.1

13.9 0.8

1.7

1.5

2.7

2.2

3.5

3.2

3.5

0.35

0.25 0.25 0.03 0.07

Notes

1. Limits per individual lead.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

03-02-18

03-07-23

SOT566-3

Fig 30. Package outline SOT566-3 (HSOP24)

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15. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

15.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

15.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

15.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

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15.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 31) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 11 and 12

Table 11. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 12. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 31.

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 31. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

16. Revision history

Table 13. Revision history

Document ID

Release date

20080909

Data sheet status

Change notice

Supersedes

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17. Legal information

17.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

17.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: [email protected]

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19. Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

15.2

15.3

15.4

Wave and reﬂow soldering . . . . . . . . . . . . . . . 35

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 35

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 36

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering informatio n . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Revision history . . . . . . . . . . . . . . . . . . . . . . . 37

Legal information . . . . . . . . . . . . . . . . . . . . . . 38

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 38

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 38

T r ademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Pinning informatio n . . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

Contact information . . . . . . . . . . . . . . . . . . . . 38

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Functional description . . . . . . . . . . . . . . . . . . . 5

Genera l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pulse width modulation frequency . . . . . . . . . . 8

Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal protection . . . . . . . . . . . . . . . . . . . . . . 8

Thermal FoldBack (TFB) . . . . . . . . . . . . . . . . . 8

Over T e mperature Protection (OTP) . . . . . . . . . 9

OverCurrent Protection (OCP) . . . . . . . . . . . . . 9

Window Protection (WP). . . . . . . . . . . . . . . . . 10

Supply voltage protections . . . . . . . . . . . . . . . 10

Differential audio inputs . . . . . . . . . . . . . . . . . 11

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12

Thermal characteristics. . . . . . . . . . . . . . . . . . 12

Static characteristics. . . . . . . . . . . . . . . . . . . . 13

12.1

12.2

Dynamic characteristics . . . . . . . . . . . . . . . . . 14

Switching characteristics . . . . . . . . . . . . . . . . 14

Stereo and dual SE application

characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 15

Mono BTL application characteristic s . . . . . . . 1 6

12.3

Application information. . . . . . . . . . . . . . . . . . 17

Mono BTL applicatio n . . . . . . . . . . . . . . . . . . . 1 7

Pin MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Output power estimatio n . . . . . . . . . . . . . . . . . 1 7

S E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7

Bridge-Tied Load (BTL) . . . . . . . . . . . . . . . . . 18

External clock . . . . . . . . . . . . . . . . . . . . . . . . . 18

Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Heatsink requirements . . . . . . . . . . . . . . . . . . 19

Output current limiting. . . . . . . . . . . . . . . . . . . 20

Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 21

Application schematics . . . . . . . . . . . . . . . . . . 21

Layout and grounding . . . . . . . . . . . . . . . . . . . 23

Curves measured in reference design . . . . . . 24

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 33

Soldering of SMD packages . . . . . . . . . . . . . . 35

Introduction to soldering . . . . . . . . . . . . . . . . . 35

15.1

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

Date of release: 9 September 2008

Document identifier: TDA8950_1

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