September 2006
DS90C3202
3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver
General Description
Features
n Up to 9.45 Gbit/s data throughput
n 8 MHz to 135 MHz input clock support
n Supports up to QXGA panel resolutions
The DS90C3202 is a 3.3V single/dual FPD-Link 10-bit color
receiver is designed to be used in Liquid Crystal Display
TVs, LCD Monitors, Digital TVs, and Plasma Display Panel
TVs. The DS90C3202 is designed to interface between the
digital video processor and the display device using the
low-power, low-EMI LVDS (Low Voltage Differential Signal-
ing) interface. The DS90C3202 converts up to ten LVDS
data streams back into 70 bits of parallel LVCMOS/LVTTL
data. The receiver can be programmed with rising edge or
falling edge clock. Optional wo-wire serial programming al-
lows fine tuning in development and production environ-
ments. With an input clock at 135 MHz, the maximum trans-
mission rate of each LVDS line is 945 Mbps, for an
aggregate throughput rate of 9.45 Gbps (945 Mbytes/s). This
allows the dual 10-bit LVDS Receiver to support resolutions
up to HDTV.
n Supports HDTV panel resolutions and frame rates up to
1920 x 1080p
n LVDS 30-bit, 24-bit or 18-bit color data inputs
n Supports single pixel and dual pixel interfaces
n Supports spread spectrum clocking
n Two-wire serial communication interface
n Programmable clock edge and control strobe select
n Power down mode
n +3.3V supply voltage
n 128-pin TQFP Package
n Compliant to TIA/EIA-644-A-2001 LVDS Standard
Block Diagram
20147101
FIGURE 1. Receiver Block Diagram
© 2006 National Semiconductor Corporation
DS201471
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Package Derating:
ESD Rating:
25.6mW/˚C above +25˚C
>
(HBM, 1.5kΩ, 100pF)
(EIAJ, 0Ω, 200pF)
2 kV
>
200 V
Supply Voltage (VDD
)
−0.3V to +4V
−0.3V to (VDD + 0.3V)
−0.3V to (VDD + 0.3V)
LVCMOS/LVTTL Input
Voltage
Recommended Operating
Conditions
LVCMOS/LVTTL Output
Voltage
Min Nom Max Units
LVDS Receiver Input Voltage −0.3V to (VDD + 0.3V)
Supply Voltage (VDD
Operating Free Air
Temperature (TA)
)
3.15 3.3
3.6
V
Junction Temperature
Storage Temperature
Lead Temperature
+150˚C
0
+25 +70
˚C
−65˚C to +150˚C
Supply Noise Voltage (VP-P
)
100 mVp-p
VDD
135 MHz
Receiver Input Range
0
8
V
(Soldering, 10 sec.)
+260˚C
Input Clock Frequency (f)
@
Maximum Package Power Dissipation Capacity 25˚C
128 TQFP Package:
1.4W
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS (Rx outputs, control inputs and outputs)
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
2.0
0
VDD
0.8
V
V
V
VOH
Rx clock out
Rx data out
Rx clock out
Rx data out
ICL = −18 mA
VIN = VDD
IOH = −4 mA
IOH = −2 mA
IOL = +4 mA
IOL = +2 mA
2.4
VOL
Low Level Output Voltage
0.4
V
VCL
IIN
Input Clamp Voltage
Input Current
−0.8
−1.5
+10
V
µA
µA
mA
VIN = 0V
−10
IOS
Output Short Circuit Current
VOUT = 0V
−120
+100
VDD
LVDS RECEIVER DC SPECIFICATIONS
VTH
VTL
VIN
Differential Input High Threshold VCM = +1.2V
Differential Input Low Threshold
Input Voltage Range
mV
mV
V
−100
0
(Single-ended)
|VID
|
Differential Input Voltage
Differential Common Mode
Voltage
0.200
0.2
0.600
V
V
VCM
1.2
VDD−0.1
IIN
Input Current
VIN = +2.4V, VDD = 3.6V
VIN = 0V, VDD = 3.6V
10
10
µA
µA
3
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Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RECEIVER SUPPLY CURRENT
ICCRW
ICCRG
ICCRZ
Receiver Supply Current
Worst Case
CL = 8 pF,
Worst Case
Pattern
f = 8 MHz
65
130
mA
(Figures 2, 4)
f = 135 MHz
f = 8 MHz
375
55
550
120
400
2
mA
mA
mA
mA
Default Register
Settings
Receiver Supply Current
Incremental Test Pattern
(Figures 3, 4)
CL = 8 pF,
Worst Case
Pattern
f = 135 MHz
245
Default Register
Settings
Receiver Supply Current
Power Down
PDWNB = Low
Receiver Outputs stay low
during Powerdown mode.
Default Register Settings
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
= 3.3V and T = +25˚C.
DD
A
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified.
Note 4: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/LVTTL I/O.
Note 5: The incremental test pattern tests device power consumption for a “typical” LCD display pattern.
Note 6: Figures 2, 3 show a falling edge data strobe (RCLK OUT).
Note 7: Figure 8 show a rising edge data strobe (RCLK OUT).
4
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Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Condition/
Reference
Min
Typ
Max
Units
CLHT
LVCMOS/LVTTL Low-to-High Transition
Time, CL = 8pF, (Figure 5) (Note 8)
Register addr 28d/1ch,
Rx clock out
1.45
2.10
ns
bit [2] (RCLK)=0b (Default),
Rx data out
Rx clock out
Rx data out
Rx clock out
Rx data out
Rx clock out
Rx data out
2.40
1.35
2.40
2.45
3.40
2.35
3.40
3.50
2.20
3.60
ns
ns
ns
ns
ns
ns
ns
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
CHLT
LVCMOS/LVTTL High-to-Low Transition
Time, CL = 8pF, (Figure 5) (Note 8)
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
CLHT
LVCMOS/LVTTL Low-to-High Transition
Programmable Time, CL = 8pF, (Figure 5) (Note 8)
adjustment
Register addr 28d/1ch,
bit [2] (RCLK)=1b (Default),
bit [1] (RXE) =1b (Default),
bit [0] (RXO) =1b (Default)
LVCMOS/LVTTL High-to-Low Transition
CHLT
Programmable Time, CL = 8pF, (Figure 5) (Note 8)
adjustment
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
RCOP
RCOH
RCOL
RSRC
RCLK OUT Period (Figures 11, 12) (Note 8)
RCLK OUT High Time (Figures 11, 12)
RCLK OUT Low Time (Figures 11, 12)
8–135 MHz
Rx clock out
Rx clock out
7.4
T
125
0.6T
0.6T
ns
ns
ns
ns
0.4T
0.4T
2.60
0.5T
0.5T
0.5T
RxOUT Setup to RCLK OUT (Figures 11, 12) (Notes 8, 9)
Register addr 29d/1dh [2:1]= 00b (Default)
RHRC
RxOUT Hold to RCLK OUT (Figures 11, 12) (Notes 8, 9)
Register addr 29d/1dh [2:1]= 00b (Default)
3.60
0.5T
ns
ns
RSRC/RHRC
Register addr 29d/1dh [2:1] = 01b, (Figures 13, 14)
+1UI /
-1UI
Programmable (Notes 2, 10)
Adjustment
RSRC increased from default by 1UI
RHRC decreased from default by 1UI
Register addr 29d/1dh [2:1] = 10b, (Figures 13, 14)
(Notes 2, 10)
-1UI /
+1UI
ns
ns
RSRC decreased from default by 1UI
RHRC increased from default by 1UI
Register addr 29d/1dh [2:1] = 11b, (Figures 13, 14)
(Notes 2, 10)
+2UI /
-2UI
RSRC increased from default by 2UI
RHRC decreased from default by 2UI
Receiver Phase Lock Loop Set (Figure 6)
Receiver Powerdown Delay (Figure 7)
Receiver Propagation Delay — Latency (Figure 8)
RPLLS
RPDD
RPDL
RITOL
10
100
ms
ns
ns
UI
4*RCLK
0.25
Receiver Input Tolerance
VCM = 1.25V,
VID = 350mV
(Figures 10, 16) (Notes 8, 10)
Note 8: Specification is guaranteed by characterization.
Note 9: A Clock Unit Symbol (T) is defined as 1/ (Line rate of RCLK). E.g. For Line rate of RCLK at 85MHz, 1 T = 11.76ns
Note 10: A Unit Interval (UI) is defined as 1/7th of an ideal clock period (RCLK/7). E.g. For an 11.76ns clock period (85MHz), 1 UI = 1.68ns
5
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Two-Wire Serial Communication Interface
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
fSC
Parameter
S2CLK Clock Frequency
Clock Low Period
Conditions
Min
Typ
Max
Units
kHz
us
400
SC:LOW
SC:HIGH
SCD:TR
SCD:TF
SU:STA
HD:STA
HD:STO
SC:SD
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
1.5
0.6
Clock High Period
us
S2CLK and S2DAT Rise Time
S2CLK and S2DAT Fall Time
Start Condition Setup Time
Start Condition Hold Time
Stop Condition Hold Time
Clock Falling Edge to Data
Data to Clock Rising Edge
S2CLK Low to S2DAT Data
Valid
0.3
0.3
us
us
0.6
0.6
0.6
0
us
us
us
us
SD:SC
0.1
0.1
us
SCL:SD
0.9
us
BUF
Bus Free Time
RP = 4.7KΩ, CL = 50pF
13
us
AC Timing Diagrams
20147122
FIGURE 1. Two-Wire Serial Communication Interface Timing Diagram
6
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AC Timing Diagrams (Continued)
20147103
FIGURE 2. “Worst Case” Test Pattern
20147104
FIGURE 3. Incremental Test Pattern
20147105
FIGURE 4. Typical and Max ICC with Worse Case and Incremental Pattern
20147106
FIGURE 5. LVCMOS/LVTTL Output Load and Transition Times
7
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AC Timing Diagrams (Continued)
20147107
FIGURE 6. Receiver Phase Lock Loop Wake-up Time
20147108
FIGURE 7. Powerdown Delay
20147109
FIGURE 8. Receiver Propagation Delay
8
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AC Timing Diagrams (Continued)
20147110
FIGURE 9. RFB: LVTTL Level Programmable Strobe Select
20147111
RITOL ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 11) + ISI (Inter-symbol interference) (Note 12)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Please see National’s AN-1217 for more details.
Note 11: Cycle-to-cycle jitter is less than 100 ps (worse case estimate).
Note 12: ISI is dependent on interconnect length; may be zero.
FIGURE 10. Receiver Input Tolerance and Sampling Window
20147112
Register address 29d/1dh bit [2:1] = 00b
FIGURE 11. Receiver RSRC and RHRC Output Setup/Hold Time — PTO Disabled
9
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AC Timing Diagrams (Continued)
20147113
RegisterAddress 29d/1dh bit [2:1] = 00b
FIGURE 12. Receiver RSRC and RHRC Output Setup/Hold Time — PTO Enabled
20147114
FIGURE 13. Receiver RSRC and RHRC Output Setup/Hold Time Adjustment — PTO Disabled
10
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AC Timing Diagrams (Continued)
20147115
FIGURE 14. Receiver RSRC and RHRC Output Setup/Hold Time Adjustment — PTO Enabled
11
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AC Timing Diagrams (Continued)
20147116
FIGURE 15. LVDS Input Mapping
12
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AC Timing Diagrams (Continued)
20147117
FIGURE 16. Receiver RITOL Min and Max
13
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Pin Diagram
DS90C3202 Receiver
20147118
14
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DS90C3202 Pin Descriptions
Pin No.
Pin Name
S2DAT
S2CLK
VDDP1
VSSP1
VSSP0
VDDP0
PWDNB
I/O
I/OP
I/P
Pin Type
Description
Two-wire Serial Interface – Data
Two-wire Serial Interface – Clock
Power supply for PLL circuitry
Ground pin for PLL circuitry
Ground pin for PLL circuitry
Power supply for PLL circuitry
Powerdown Bar (Active LOW)
0 = DEVICE DISABLED
1
2
3
4
5
6
7
Digital
Digital
PLL
VDD
GND
GND
VDD
I/P
PLL
PLL
PLL
LVTTL I/P (pulldown)
1 = DEVICE ENABLED
8
RXEE0
RXEE1
RXEE2
RXEE3
RXEE4
RXEE5
RXEE6
VSS0
O/P
O/P
O/P
O/P
O/P
O/P
O/P
GND
VDD
LVTTL O/P
LVTTL level data output
9
LVTTL O/P
LVTTL level data output
10
11
12
13
14
15
16
LVTTL O/P
LVTTL level data output
LVTTL O/P
LVTTL level data output
LVTTL O/P
LVTTL level data output
LVTTL O/P
LVTTL level data output
LVTTL O/P
LVTTL level data output
LVTTL O/P PWR
LVTTL O/P PWR
Ground pin for LVTTL outputs and digital circuitry
Power supply pin for LVTTL outputs and digital
circuitry
VDD0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
RXED0
RXED1
RXED2
RXED3
RXED4
RXED5
RXED6
VSSR0
VDDR0
RXEC0
RXEC1
RXEC2
RXEC3
RXEC4
RXEC5
VSS1
O/P
O/P
O/P
O/P
O/P
O/P
O/P
GND
VDD
O/P
O/P
O/P
O/P
O/P
O/P
GND
VDD
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
RX LOGIC
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
Ground pin for logic
RX LOGIC
Power supply for logic
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P PWR
LVTTL O/P PWR
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
Ground pin for LVTTL outputs and digital circuitry
Power supply pin for LVTTL outputs and digital
circuitry
VDD1
34
35
36
37
38
39
40
41
42
43
44
45
RXEC6
RXEB0
RXEB1
RXEB2
RXEB3
RXEB4
RXEB5
RXEB6
VSSR1
VDDR1
RCLKOUT
VSS2
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
GND
VDD
O/P
GND
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
RX LOGIC
RX LOGIC
LVTTL O/P
LVTTL O/P PWR
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
Ground pin for logic
Power supply for logic
LVTTL level clock output
Ground pin for LVTTL outputs and digital circuitry
15
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DS90C3202 Pin Descriptions (Continued)
Pin No.
Pin Name
I/O
Pin Type
Description
Power supply pin for LVTTL outputs and digital
circuitry
46
VDD2
VDD
LVTTL O/P PWR
47
48
49
50
51
52
53
54
55
RXEA0
RXEA1
RXEA2
RXEA3
RXEA4
RXEA5
RXEA6
VSS3
O/P
O/P
O/P
O/P
O/P
O/P
O/P
GND
VDD
LVTTL O/P
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
Ground pin for LVTTL outputs and digital circuitry
Power supply pin for LVTTL outputs and digital
circuitry
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P PWR
LVTTL O/P PWR
VDD3
56
57
58
59
60
61
62
63
64
65
RXOE0
RXOE1
RXOE2
RXOE3
RXOE4
RXOE5
RXOE6
RXOD0
VSS4
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
GND
VDD
LVTTL O/P
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
Ground pin for LVTTL outputs and digital circuitry
Power supply pin for LVTTL outputs and digital
circuitry
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P PWR
LVTTL O/P PWR
VDD4
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
RXOD1
RXOD2
RXOD3
RXOD4
RXOD5
RXOD6
RXOC0
RXOC1
RXOC2
RXOC3
RXOC4
RXOC5
RXOC6
RXOB0
RXOB1
RXOB2
RXOB3
RXOB4
RXOB5
RXOB6
VDDR2
VSSR2
RXOA0
RXOA1
RXOA2
RXOA3
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
VDD
GND
O/P
O/P
O/P
O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
RX LOGIC
RX LOGIC
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
Power supply for logic
Ground pin for logic
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
16
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DS90C3202 Pin Descriptions (Continued)
Pin No.
92
Pin Name
RXOA4
RXOA5
RXOA6
VDD5
I/O
O/P
O/P
O/P
VDD
Pin Type
LVTTL O/P
Description
LVTTL level data output
93
LVTTL O/P
LVTTL level data output
94
LVTTL O/P
LVTTL level data output
95
LVTTL O/P PWR
Power supply pin for LVTTL outputs and digital
circuitry
96
97
98
VSS5
RESRVD
MODE1
GND
I/P
LVTTL O/P PWR
LVTTL I/P (pulldown)
Digital (pulldown)
Ground pin for LVTTL outputs and digital circuitry
Tie to VSS for correct functionality
“ODD” Bank Enable
I/P
0 = LVTTL ODD OUTPUTS DISABLED
(Data Output Low)
1 = LVTTL ODD OUTPUTS ENABLED
Ground pin for LVDS
99
VSSL
VDDL
GND
VDD
I/P
LVDS PWR
LVDS PWR
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS PWR
LVDS PWR
LVDS PWR
LVDS PWR
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
Digital (pulldown)
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
Power supply pin for LVDS
RXOA-
RXOA+
RXOB-
RXOB+
RXOC-
RXOC+
RXOD-
RXOD+
RXOE-
RXOE+
VSSL
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Ground pin for LVDS
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
GND
GND
VDD
VDD
I/P
VSSL
Ground pin for LVDS
VDDL
Power supply pin for LVDS
VDDL
Power supply pin for LVDS
RCLKIN-
RCLKIN+
RXEA-
RXEA+
RXEB-
RXEB+
RXEC-
RXEC+
RXED-
RXED+
RXEE-
RXEE+
MODE0
Negative LVDS differential clock input
Positive LVDS differential clock input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
“EVEN” Bank Enable
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
0 = LVTTL EVEN OUTPUTS DISABLED
(Data Output Low)
1 = LVTTL EVEN OUTPUTS ENABLED
Rising Falling Bar (Figure 9)
128
RFB
I/P
Digital (pulldown)
0 = FALLING EDGE DATA STROBE
1 = RISING EDGE DATA STROBE
17
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Reading the DS90C3202 can take place either of three ways:
Two-Wire Serial Communication
Interface Description
The DS90C3202 operates as a slave on the Serial Bus, so
the S2CLK line is an input (no clock is generated by the
DS90C3202) and the S2DAT line is bi-directional.
DS90C3202 has a fixed 7bit slave address. The address is
not user configurable in anyway.
1. If the location latched in the data register addresses is
correct, then the read can simply consist of a slave
address byte, followed by retrieving the data byte.
2. If the data register address needs to be set, then a slave
address byte, data register address will be sent first,
then the master will repeat start, send the slave address
byte and data byte to accomplish a read.
A zero in front of the register address is required. For ex-
ample, to access register 0x0Fh, “0F” is the correct way of
accessing the register.
3. When performing continuous read operations, another
write (or read) instruction in between reads needs to be
completed in order for the two-wire serial interface mod-
ule to read repeatedly.
COMMUNICATING WITH THE DS90C3202 CONTROL
REGISTERS
The data byte has the most significant bit first. At the end of
a read, the DS90C3202 can accept either Acknowledge or
No Acknowledge from the Master (No Acknowledge is typi-
cally used as a signal for the slave that the Master has read
its last byte).
There are 32 data registers (one byte each) in the
DS90C3202, and can be accessed through 32 addresses.
All registers are predefined as read only or read and write.
The DS90C3202 slave state machine does not require an
internal clock and it supports only byte read and write. Page
mode is not supported. The 7bit binary address is 0111110
All seven bits are hardwired internally.
20147119
FIGURE 17. Byte Read
The master must generate a Start by sending the 7-bit slave
address plus a 0 first, and wait for acknowledge from
DS90C3202. When DS90C3202 acknowledges (the 1st
ACK) that the master is calling, the master then sends the
data register address byte and waits for acknowledge from
the slave. When the slave acknowledges (the 2nd ACK), the
master repeats the “Start” by sending the 7-bit slave address
plus a 1 (indicating that READ operation is in progress) and
waits for acknowledge from DS90C3202. After the slave
responds (the 3rd ACK), the slave sends the data to the bus
and waits for acknowledge from the master. When the mas-
ter acknowledges (the 4th ACK), it generates a “Stop”. This
completes the “ READ”.
A Write to the DS90C3202 will always include the slave
address, data register address byte, and a data byte.
20147120
FIGURE 18. Byte Write
The master must generate a “Start” by sending the 7-bit
slave address plus a 0 and wait for acknowledge from
DS90C3202. When DS90C3202 acknowledges (the 1st
ACK) that the master is calling, the master then sends the
data register address byte and waits for acknowledge from
the slave. When the slave acknowledges (the 2nd ACK), the
master sends the data byte and wait for acknowledge from
the slave. When the slave acknowledges (the 3rd ACK), the
master generates a “ Stop”. This completes the “WRITE”.
18
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DS90C3202 Two-Wire Serial Interface Register Table
Address
0d/0h
1d/1h
2d/2h
3d/3h
4d/4h
5d/5h
6d/6h
R/W
R
RESET
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
Bit #
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Description
Vender ID low byte[7:0] = 05h
Default Value
0000_0101
0001_0011
0010_1000
0110_0111
0000_0000
0000_1000
1000_0111
R
Vender ID high byte[15:8] =13h
Device ID low byte[7:0] = 28h
Device ID high byte 15:8] = 67h
Device revision [7:0] = 00h to begin with
Low frequency limit, 8Mhz = 8h
High frequency limit 135Mhz = 87h =
0000_0000_1000_0111
Reserved
R
R
R
R
R
7d/7h
8d/8h
R
R
R
R
R
PWDN
PWDN
PWDN
PWDN
PWDN
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
Reserved
9d/9h
Reserved
10d/ah
11d/bh
Reserved
Reserved
20d/14h
21d/15h
22d/16h
R/W
R/W
R/W
None
None
None
[7:0]
[7:0]
[7:3]
[2:0]
Reserved
0000_0000
0000_0000
0000_0000
Reserved
Reserved
LVDS input skew control for CLK channel,
000 (default) applies to no delay added, ONE buffer
delay per step adjustment towards Tsetup improvement
Reserved
23d/17h
24d/18h
25d/19h
R/W
R/W
R/W
None
None
None
[7]
0000_0000
0000_0000
0000_0000
[6:4]
LVDS input skew control for RXO channel B,
000 (default) applies to no delay added, ONE buffer
delay per step adjustment towards Thold improvements
Reserved
[3]
[2:0]
LVDS input skew control for RXO channel C,
000 (default) applies to no delay added, ONE buffer
delay per step adjustment towards Thold improvements
Reserved
[7]
[6:4]
LVDS input skew control for RXO channel D,
000 (default) applies to no delay added, ONE buffer
delay per step adjustment towards Thold improvements
Reserved
[3]
[2:0]
LVDS input skew control for RXO channel E,
000 (default) applies to no delay added, ONE buffer
delay per step adjustment towards Thold improvements
Reserved
[7]
[6:4]
LVDS input skew control for RXO channel A,
000 (default) applies to no delay added, ONE buffer
delay per step adjustment towards Thold improvements
Reserved
[3]
[2:0]
LVDS input skew control for RXE channel A,
000 (default) applies to no delay added, ONE buffer
delay per step adjustment towards Thold improvements
19
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DS90C3202 Two-Wire Serial Interface Register Table (Continued)
Address
R/W
RESET
Bit #
[7]
Description
Default Value
26d/1ah
R/W
None
Reserved
0000_0000
[6:4]
LVDS input skew control for RXE channel B,
000 (default) applies to no delay added, ONE buffer
delay per step adjustment towards Thold improvements
Reserved
[3]
[2:0]
LVDS input skew control for RXE channel C,
000 (default) applies to no delay added, ONE buffer
delay per step adjustment towards Thold improvements
Reserved
27d/1bh
R/W
None
[7]
0000_0000
[6:4]
LVDS input skew control for RXE channel D,
000 (default) applies to no delay added, ONE buffer
delay per step adjustment
[3]
Reserved
[2:0]
LVDS input skew control for RXE channel E,
000 (default) applies to no delay added, ONE buffer
delay per step adjustment towards Thold improvements
Reserved
28d/1ch
R/W
None
[7:3]
[2]
0000_0000
LVTTL output transition time control for CLK
0: Tr/Tf = 1.0ns (default)
1: Tr/Tf = 1.5ns
[1]
[0]
LVTTL output transition time control for RXE
0: Tr/Tf = 1.5ns (default)
1: Tr/Tf = 2.5ns
LVTTL output transition time control for RXO
0: Tr/Tf = 1.5ns (default)
1: Tr/Tf = 2.5ns
29d/1dh
R/W
None
[7:3]
[2:1]
Reserved
0000_0000
LVTTL output setup and hold time control
00: balanced setup and hold time (default)
01: setup time is increased from default position by 1UI
& hold time is reduced from default position by 1UI
10: setup time is decreased from default position by 1UI
& hold time is reduced from default position by 1UI
11: setup time is increased from default position by 2UI
& hold time is increased from default position by 2UI
LVTTL output PTO control
[0]
1: PTO disabled, all outputs setup time are only
controlled by contents of [2:1]
0: PTO enabled (default)
Group1: CLK to latch Data is re-assigned earlier by
0.5UI respect to the normal centered position if only
PTO option enabled; but PTO option and (Tsetup or
Thold) adjustment can co-exist
Group2: CLK to latch Data stays as the normal
centered position if only PTO option enabled; but PTO
option and (Tsetup or Thold) adjustment can co-exist
20
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DS90C3202 Two-Wire Serial Interface Register Table (Continued)
Address
R/W
RESET
Bit #
[7:5]
[4]
Description
Default Value
30d/1eh
R/W
None
Reserved
0000_0000
I/O disable control for RXE channel A,
1: disable, 0: enable (default)
[3]
[2]
I/O disable control for RXE channel B,
1: disable, 0: enable (default)
I/O disable control for RXE channel C,
1: disable, 0: enable (default)
[1]
I/O disable control for RXE channel D,
1: disable, 0: enable (default)
[0]
I/O disable control for RXE channel E,
1: disable, 0: enable (default)
31d/1fh
R/W
None
[7:6]
11; LVTTL Outputs available as long as "NO CLK" is at
HIGH regardless PLL lock or not
10; LVTTL Outputs available after 1K of CLK cycles
detected & PLL generated strobes are within 0.5UI
respect to REFCLK
0000_0000
01; LVTLL Outputs available after 2K of CLK cycles
detected
00: default ; LVTTL Outputs available after 1K of CLK
cycles detected
[5]
[4]
[3]
[2]
[1]
[0]
0: default; to select the size of wait counter between 1K
or 2K, default is 1K
I/O disable control for RXO channel A,
1: disable, 0: enable (default)
I/O disable control for RXO channel B,
1 disable, 0: enable (default)
I/O disable control for RXO channel C,
1: disable, 0: enable (default)
I/O disable control for RXO channel D,
1: disable, 0: enable (default)
I/O disable control for RXO channel E,
1: disable, 0: enable (default)
Note 13: Registers with RESET designated with “None” requires device to be power cycled to reset register values to their default state.
21
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Physical Dimensions inches (millimeters) unless otherwise noted
128-Pin TQFP Package
Order Number DS90C3202VS
NS Package Number VJX128A
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the right at any time without notice to change said circuitry and specifications.
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